./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.13.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.13.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:23:03,394 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:23:03,396 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:23:03,448 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:23:03,449 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:23:03,452 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:23:03,454 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:23:03,460 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:23:03,462 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:23:03,468 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:23:03,469 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:23:03,470 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:23:03,470 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:23:03,473 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:23:03,474 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:23:03,478 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:23:03,479 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:23:03,480 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:23:03,482 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:23:03,486 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:23:03,488 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:23:03,489 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:23:03,490 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:23:03,491 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:23:03,495 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:23:03,495 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:23:03,496 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:23:03,497 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:23:03,497 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:23:03,498 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:23:03,499 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:23:03,500 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:23:03,501 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:23:03,502 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:23:03,503 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:23:03,503 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:23:03,504 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:23:03,504 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:23:03,505 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:23:03,505 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:23:03,506 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:23:03,507 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:23:03,542 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:23:03,542 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:23:03,543 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:23:03,543 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:23:03,544 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:23:03,545 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:23:03,545 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:23:03,545 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:23:03,545 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:23:03,545 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:23:03,546 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:23:03,546 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:23:03,547 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:23:03,547 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:23:03,547 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:23:03,547 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:23:03,547 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:23:03,548 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:23:03,548 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:23:03,548 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:23:03,548 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:23:03,548 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:23:03,548 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:23:03,549 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:23:03,550 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:23:03,550 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:23:03,550 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:23:03,550 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:23:03,551 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:23:03,551 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:23:03,551 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:23:03,552 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:23:03,552 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 [2022-02-21 04:23:03,777 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:23:03,798 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:23:03,800 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:23:03,801 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:23:03,802 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:23:03,803 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2022-02-21 04:23:03,859 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/92a356f9b/edbe3a8c8a3c42d297f5fc60c3a478e5/FLAG8ab232674 [2022-02-21 04:23:04,320 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:23:04,320 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2022-02-21 04:23:04,342 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/92a356f9b/edbe3a8c8a3c42d297f5fc60c3a478e5/FLAG8ab232674 [2022-02-21 04:23:04,700 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/92a356f9b/edbe3a8c8a3c42d297f5fc60c3a478e5 [2022-02-21 04:23:04,703 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:23:04,706 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:23:04,707 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:04,708 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:23:04,710 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:23:04,713 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:04" (1/1) ... [2022-02-21 04:23:04,715 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@44ac4a43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:04, skipping insertion in model container [2022-02-21 04:23:04,715 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:04" (1/1) ... [2022-02-21 04:23:04,721 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:23:04,773 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:23:04,898 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-1.c[671,684] [2022-02-21 04:23:05,014 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:05,025 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:23:05,034 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-1.c[671,684] [2022-02-21 04:23:05,097 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:05,114 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:23:05,116 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05 WrapperNode [2022-02-21 04:23:05,117 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:05,118 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:05,118 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:23:05,119 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:23:05,124 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (1/1) ... [2022-02-21 04:23:05,136 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (1/1) ... [2022-02-21 04:23:05,266 INFO L137 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4665 [2022-02-21 04:23:05,267 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:05,268 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:23:05,268 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:23:05,268 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:23:05,275 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (1/1) ... [2022-02-21 04:23:05,276 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (1/1) ... [2022-02-21 04:23:05,287 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (1/1) ... [2022-02-21 04:23:05,288 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (1/1) ... [2022-02-21 04:23:05,356 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (1/1) ... [2022-02-21 04:23:05,404 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (1/1) ... [2022-02-21 04:23:05,414 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (1/1) ... [2022-02-21 04:23:05,432 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:23:05,434 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:23:05,435 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:23:05,435 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:23:05,436 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (1/1) ... [2022-02-21 04:23:05,442 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:23:05,451 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:23:05,464 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:23:05,483 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:23:05,508 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:23:05,508 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:23:05,508 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:23:05,508 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:23:05,684 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:23:05,685 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:23:07,904 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:23:07,922 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:23:07,922 INFO L299 CfgBuilder]: Removed 16 assume(true) statements. [2022-02-21 04:23:07,925 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:07 BoogieIcfgContainer [2022-02-21 04:23:07,926 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:23:07,926 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:23:07,927 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:23:07,929 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:23:07,930 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:07,930 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:23:04" (1/3) ... [2022-02-21 04:23:07,931 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@52e29b3c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:07, skipping insertion in model container [2022-02-21 04:23:07,931 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:07,932 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:05" (2/3) ... [2022-02-21 04:23:07,932 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@52e29b3c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:07, skipping insertion in model container [2022-02-21 04:23:07,932 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:07,932 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:07" (3/3) ... [2022-02-21 04:23:07,933 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-1.c [2022-02-21 04:23:07,968 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:23:07,969 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:23:07,969 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:23:07,969 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:23:07,969 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:23:07,969 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:23:07,969 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:23:07,970 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:23:08,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,401 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1852 [2022-02-21 04:23:08,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:08,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:08,414 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:08,414 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:08,414 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:23:08,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1852 [2022-02-21 04:23:08,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:08,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:08,661 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:08,661 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:08,669 INFO L791 eck$LassoCheckResult]: Stem: 484#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1951#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1565#L1903true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1977#L907true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1850#L914true assume !(1 == ~m_i~0);~m_st~0 := 2; 836#L914-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 443#L919-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1245#L924-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1128#L929-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1855#L934-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1285#L939-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1654#L944-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 313#L949-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1328#L954-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1963#L959-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 648#L964-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1195#L969-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1764#L974-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 583#L979-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1887#L1291true assume 0 == ~M_E~0;~M_E~0 := 1; 1852#L1291-2true assume !(0 == ~T1_E~0); 1844#L1296-1true assume !(0 == ~T2_E~0); 694#L1301-1true assume !(0 == ~T3_E~0); 1240#L1306-1true assume !(0 == ~T4_E~0); 1212#L1311-1true assume !(0 == ~T5_E~0); 232#L1316-1true assume !(0 == ~T6_E~0); 1658#L1321-1true assume !(0 == ~T7_E~0); 703#L1326-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 142#L1331-1true assume !(0 == ~T9_E~0); 4#L1336-1true assume !(0 == ~T10_E~0); 1090#L1341-1true assume !(0 == ~T11_E~0); 37#L1346-1true assume !(0 == ~T12_E~0); 1453#L1351-1true assume !(0 == ~T13_E~0); 205#L1356-1true assume !(0 == ~E_M~0); 1971#L1361-1true assume !(0 == ~E_1~0); 1631#L1366-1true assume 0 == ~E_2~0;~E_2~0 := 1; 226#L1371-1true assume !(0 == ~E_3~0); 1433#L1376-1true assume !(0 == ~E_4~0); 755#L1381-1true assume !(0 == ~E_5~0); 1725#L1386-1true assume !(0 == ~E_6~0); 1884#L1391-1true assume !(0 == ~E_7~0); 1795#L1396-1true assume !(0 == ~E_8~0); 667#L1401-1true assume !(0 == ~E_9~0); 1302#L1406-1true assume 0 == ~E_10~0;~E_10~0 := 1; 908#L1411-1true assume !(0 == ~E_11~0); 1686#L1416-1true assume !(0 == ~E_12~0); 614#L1421-1true assume !(0 == ~E_13~0); 324#L1426-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 760#L640true assume !(1 == ~m_pc~0); 1799#L640-2true is_master_triggered_~__retres1~0#1 := 0; 719#L651true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1261#L652true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 638#L1603true assume !(0 != activate_threads_~tmp~1#1); 1286#L1603-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 402#L659true assume 1 == ~t1_pc~0; 461#L660true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1416#L670true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1368#L671true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 473#L1611true assume !(0 != activate_threads_~tmp___0~0#1); 481#L1611-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1599#L678true assume 1 == ~t2_pc~0; 1454#L679true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1703#L689true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1973#L690true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 548#L1619true assume !(0 != activate_threads_~tmp___1~0#1); 691#L1619-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 636#L697true assume !(1 == ~t3_pc~0); 737#L697-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1501#L708true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 588#L709true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 574#L1627true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1914#L1627-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1534#L716true assume 1 == ~t4_pc~0; 1510#L717true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 389#L727true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1556#L728true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121#L1635true assume !(0 != activate_threads_~tmp___3~0#1); 984#L1635-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1478#L735true assume !(1 == ~t5_pc~0); 104#L735-2true is_transmit5_triggered_~__retres1~5#1 := 0; 338#L746true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1646#L747true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1015#L1643true assume !(0 != activate_threads_~tmp___4~0#1); 687#L1643-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 873#L754true assume 1 == ~t6_pc~0; 521#L755true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 452#L765true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1771#L766true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 436#L1651true assume !(0 != activate_threads_~tmp___5~0#1); 1119#L1651-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1960#L773true assume !(1 == ~t7_pc~0); 897#L773-2true is_transmit7_triggered_~__retres1~7#1 := 0; 721#L784true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1258#L785true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 695#L1659true assume !(0 != activate_threads_~tmp___6~0#1); 747#L1659-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 882#L792true assume 1 == ~t8_pc~0; 1953#L793true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1288#L803true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 742#L804true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 689#L1667true assume !(0 != activate_threads_~tmp___7~0#1); 637#L1667-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 802#L811true assume 1 == ~t9_pc~0; 1340#L812true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1697#L822true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1146#L823true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 799#L1675true assume !(0 != activate_threads_~tmp___8~0#1); 644#L1675-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1728#L830true assume !(1 == ~t10_pc~0); 2019#L830-2true is_transmit10_triggered_~__retres1~10#1 := 0; 196#L841true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45#L842true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 185#L1683true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1791#L1683-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1140#L849true assume 1 == ~t11_pc~0; 1627#L850true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 91#L860true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 407#L861true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1160#L1691true assume !(0 != activate_threads_~tmp___10~0#1); 1023#L1691-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1797#L868true assume !(1 == ~t12_pc~0); 1394#L868-2true is_transmit12_triggered_~__retres1~12#1 := 0; 568#L879true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 411#L880true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1716#L1699true assume !(0 != activate_threads_~tmp___11~0#1); 213#L1699-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1629#L887true assume 1 == ~t13_pc~0; 1037#L888true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 569#L898true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 913#L899true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1106#L1707true assume !(0 != activate_threads_~tmp___12~0#1); 63#L1707-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1680#L1439true assume !(1 == ~M_E~0); 684#L1439-2true assume !(1 == ~T1_E~0); 149#L1444-1true assume !(1 == ~T2_E~0); 914#L1449-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 404#L1454-1true assume !(1 == ~T4_E~0); 1452#L1459-1true assume !(1 == ~T5_E~0); 796#L1464-1true assume !(1 == ~T6_E~0); 858#L1469-1true assume !(1 == ~T7_E~0); 1706#L1474-1true assume !(1 == ~T8_E~0); 615#L1479-1true assume !(1 == ~T9_E~0); 800#L1484-1true assume !(1 == ~T10_E~0); 1262#L1489-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 535#L1494-1true assume !(1 == ~T12_E~0); 1835#L1499-1true assume !(1 == ~T13_E~0); 660#L1504-1true assume !(1 == ~E_M~0); 1509#L1509-1true assume !(1 == ~E_1~0); 1259#L1514-1true assume !(1 == ~E_2~0); 883#L1519-1true assume !(1 == ~E_3~0); 1952#L1524-1true assume !(1 == ~E_4~0); 1670#L1529-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1765#L1534-1true assume !(1 == ~E_6~0); 60#L1539-1true assume !(1 == ~E_7~0); 270#L1544-1true assume !(1 == ~E_8~0); 1591#L1549-1true assume !(1 == ~E_9~0); 1614#L1554-1true assume !(1 == ~E_10~0); 1587#L1559-1true assume !(1 == ~E_11~0); 1320#L1564-1true assume !(1 == ~E_12~0); 1655#L1569-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1743#L1574-1true assume { :end_inline_reset_delta_events } true; 148#L1940-2true [2022-02-21 04:23:08,672 INFO L793 eck$LassoCheckResult]: Loop: 148#L1940-2true assume !false; 1557#L1941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1044#L1266true assume false; 486#L1281true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1604#L907-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 965#L1291-3true assume 0 == ~M_E~0;~M_E~0 := 1; 859#L1291-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1860#L1296-3true assume !(0 == ~T2_E~0); 1768#L1301-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1612#L1306-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 590#L1311-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 169#L1316-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 221#L1321-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 679#L1326-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1575#L1331-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 889#L1336-3true assume !(0 == ~T10_E~0); 1494#L1341-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 400#L1346-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 386#L1351-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 355#L1356-3true assume 0 == ~E_M~0;~E_M~0 := 1; 738#L1361-3true assume 0 == ~E_1~0;~E_1~0 := 1; 769#L1366-3true assume 0 == ~E_2~0;~E_2~0 := 1; 27#L1371-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1296#L1376-3true assume !(0 == ~E_4~0); 1545#L1381-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1092#L1386-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1678#L1391-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1332#L1396-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1975#L1401-3true assume 0 == ~E_9~0;~E_9~0 := 1; 203#L1406-3true assume 0 == ~E_10~0;~E_10~0 := 1; 125#L1411-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1767#L1416-3true assume !(0 == ~E_12~0); 491#L1421-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1127#L1426-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 566#L640-45true assume !(1 == ~m_pc~0); 1945#L640-47true is_master_triggered_~__retres1~0#1 := 0; 250#L651-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 523#L652-15true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24#L1603-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1854#L1603-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66#L659-45true assume 1 == ~t1_pc~0; 1919#L660-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1780#L670-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 980#L671-15true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1552#L1611-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 997#L1611-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1521#L678-45true assume 1 == ~t2_pc~0; 946#L679-15true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 571#L689-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 671#L690-15true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1360#L1619-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1666#L1619-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1607#L697-45true assume !(1 == ~t3_pc~0); 1253#L697-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1849#L708-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1502#L709-15true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 898#L1627-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 931#L1627-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2013#L716-45true assume 1 == ~t4_pc~0; 625#L717-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2007#L727-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1133#L728-15true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 629#L1635-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1505#L1635-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410#L735-45true assume !(1 == ~t5_pc~0); 1197#L735-47true is_transmit5_triggered_~__retres1~5#1 := 0; 1660#L746-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1515#L747-15true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1829#L1643-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1664#L1643-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1651#L754-45true assume !(1 == ~t6_pc~0); 1490#L754-47true is_transmit6_triggered_~__retres1~6#1 := 0; 1990#L765-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363#L766-15true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1966#L1651-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 761#L1651-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 552#L773-45true assume !(1 == ~t7_pc~0); 286#L773-47true is_transmit7_triggered_~__retres1~7#1 := 0; 937#L784-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1294#L785-15true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1397#L1659-45true assume !(0 != activate_threads_~tmp___6~0#1); 559#L1659-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 353#L792-45true assume 1 == ~t8_pc~0; 1504#L793-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1205#L803-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 144#L804-15true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 73#L1667-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 720#L1667-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 329#L811-45true assume !(1 == ~t9_pc~0); 283#L811-47true is_transmit9_triggered_~__retres1~9#1 := 0; 1107#L822-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1699#L823-15true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 924#L1675-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 609#L1675-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 465#L830-45true assume 1 == ~t10_pc~0; 1341#L831-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 683#L841-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1597#L842-15true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 155#L1683-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1374#L1683-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33#L849-45true assume !(1 == ~t11_pc~0); 1523#L849-47true is_transmit11_triggered_~__retres1~11#1 := 0; 260#L860-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 71#L861-15true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28#L1691-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 187#L1691-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 152#L868-45true assume 1 == ~t12_pc~0; 398#L869-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 118#L879-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1026#L880-15true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1916#L1699-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1388#L1699-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1936#L887-45true assume !(1 == ~t13_pc~0); 156#L887-47true is_transmit13_triggered_~__retres1~13#1 := 0; 1041#L898-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1645#L899-15true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1944#L1707-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 136#L1707-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1057#L1439-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1028#L1439-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 147#L1444-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 228#L1449-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1611#L1454-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 847#L1459-3true assume !(1 == ~T5_E~0); 2011#L1464-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1396#L1469-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1301#L1474-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1622#L1479-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1398#L1484-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 594#L1489-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1186#L1494-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1792#L1499-3true assume !(1 == ~T13_E~0); 809#L1504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1316#L1509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1361#L1514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1891#L1519-3true assume 1 == ~E_3~0;~E_3~0 := 2; 539#L1524-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1438#L1529-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1669#L1534-3true assume 1 == ~E_6~0;~E_6~0 := 2; 743#L1539-3true assume !(1 == ~E_7~0); 379#L1544-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1406#L1549-3true assume 1 == ~E_9~0;~E_9~0 := 2; 706#L1554-3true assume 1 == ~E_10~0;~E_10~0 := 2; 174#L1559-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1216#L1564-3true assume 1 == ~E_12~0;~E_12~0 := 2; 932#L1569-3true assume 1 == ~E_13~0;~E_13~0 := 2; 1179#L1574-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 111#L992-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 168#L1064-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 134#L1065-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 114#L1959true assume !(0 == start_simulation_~tmp~3#1); 130#L1959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 892#L992-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 974#L1064-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1114#L1065-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1426#L1914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1598#L1921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1469#L1922true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1613#L1972true assume !(0 != start_simulation_~tmp___0~1#1); 148#L1940-2true [2022-02-21 04:23:08,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:08,681 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2022-02-21 04:23:08,689 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:08,690 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078358300] [2022-02-21 04:23:08,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:08,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:08,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:08,974 INFO L290 TraceCheckUtils]: 0: Hoare triple {2035#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {2035#true} is VALID [2022-02-21 04:23:08,975 INFO L290 TraceCheckUtils]: 1: Hoare triple {2035#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {2037#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:08,976 INFO L290 TraceCheckUtils]: 2: Hoare triple {2037#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {2037#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:08,977 INFO L290 TraceCheckUtils]: 3: Hoare triple {2037#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {2037#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:08,977 INFO L290 TraceCheckUtils]: 4: Hoare triple {2037#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,977 INFO L290 TraceCheckUtils]: 5: Hoare triple {2036#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {2036#false} is VALID [2022-02-21 04:23:08,977 INFO L290 TraceCheckUtils]: 6: Hoare triple {2036#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,978 INFO L290 TraceCheckUtils]: 7: Hoare triple {2036#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,978 INFO L290 TraceCheckUtils]: 8: Hoare triple {2036#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,978 INFO L290 TraceCheckUtils]: 9: Hoare triple {2036#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,979 INFO L290 TraceCheckUtils]: 10: Hoare triple {2036#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,979 INFO L290 TraceCheckUtils]: 11: Hoare triple {2036#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,979 INFO L290 TraceCheckUtils]: 12: Hoare triple {2036#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,979 INFO L290 TraceCheckUtils]: 13: Hoare triple {2036#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {2036#false} is VALID [2022-02-21 04:23:08,980 INFO L290 TraceCheckUtils]: 14: Hoare triple {2036#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,980 INFO L290 TraceCheckUtils]: 15: Hoare triple {2036#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,980 INFO L290 TraceCheckUtils]: 16: Hoare triple {2036#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,980 INFO L290 TraceCheckUtils]: 17: Hoare triple {2036#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {2036#false} is VALID [2022-02-21 04:23:08,981 INFO L290 TraceCheckUtils]: 18: Hoare triple {2036#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {2036#false} is VALID [2022-02-21 04:23:08,981 INFO L290 TraceCheckUtils]: 19: Hoare triple {2036#false} assume 0 == ~M_E~0;~M_E~0 := 1; {2036#false} is VALID [2022-02-21 04:23:08,981 INFO L290 TraceCheckUtils]: 20: Hoare triple {2036#false} assume !(0 == ~T1_E~0); {2036#false} is VALID [2022-02-21 04:23:08,981 INFO L290 TraceCheckUtils]: 21: Hoare triple {2036#false} assume !(0 == ~T2_E~0); {2036#false} is VALID [2022-02-21 04:23:08,981 INFO L290 TraceCheckUtils]: 22: Hoare triple {2036#false} assume !(0 == ~T3_E~0); {2036#false} is VALID [2022-02-21 04:23:08,982 INFO L290 TraceCheckUtils]: 23: Hoare triple {2036#false} assume !(0 == ~T4_E~0); {2036#false} is VALID [2022-02-21 04:23:08,982 INFO L290 TraceCheckUtils]: 24: Hoare triple {2036#false} assume !(0 == ~T5_E~0); {2036#false} is VALID [2022-02-21 04:23:08,982 INFO L290 TraceCheckUtils]: 25: Hoare triple {2036#false} assume !(0 == ~T6_E~0); {2036#false} is VALID [2022-02-21 04:23:08,982 INFO L290 TraceCheckUtils]: 26: Hoare triple {2036#false} assume !(0 == ~T7_E~0); {2036#false} is VALID [2022-02-21 04:23:08,983 INFO L290 TraceCheckUtils]: 27: Hoare triple {2036#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {2036#false} is VALID [2022-02-21 04:23:08,983 INFO L290 TraceCheckUtils]: 28: Hoare triple {2036#false} assume !(0 == ~T9_E~0); {2036#false} is VALID [2022-02-21 04:23:08,984 INFO L290 TraceCheckUtils]: 29: Hoare triple {2036#false} assume !(0 == ~T10_E~0); {2036#false} is VALID [2022-02-21 04:23:08,984 INFO L290 TraceCheckUtils]: 30: Hoare triple {2036#false} assume !(0 == ~T11_E~0); {2036#false} is VALID [2022-02-21 04:23:08,984 INFO L290 TraceCheckUtils]: 31: Hoare triple {2036#false} assume !(0 == ~T12_E~0); {2036#false} is VALID [2022-02-21 04:23:08,985 INFO L290 TraceCheckUtils]: 32: Hoare triple {2036#false} assume !(0 == ~T13_E~0); {2036#false} is VALID [2022-02-21 04:23:08,985 INFO L290 TraceCheckUtils]: 33: Hoare triple {2036#false} assume !(0 == ~E_M~0); {2036#false} is VALID [2022-02-21 04:23:08,985 INFO L290 TraceCheckUtils]: 34: Hoare triple {2036#false} assume !(0 == ~E_1~0); {2036#false} is VALID [2022-02-21 04:23:08,985 INFO L290 TraceCheckUtils]: 35: Hoare triple {2036#false} assume 0 == ~E_2~0;~E_2~0 := 1; {2036#false} is VALID [2022-02-21 04:23:08,986 INFO L290 TraceCheckUtils]: 36: Hoare triple {2036#false} assume !(0 == ~E_3~0); {2036#false} is VALID [2022-02-21 04:23:08,986 INFO L290 TraceCheckUtils]: 37: Hoare triple {2036#false} assume !(0 == ~E_4~0); {2036#false} is VALID [2022-02-21 04:23:08,986 INFO L290 TraceCheckUtils]: 38: Hoare triple {2036#false} assume !(0 == ~E_5~0); {2036#false} is VALID [2022-02-21 04:23:08,986 INFO L290 TraceCheckUtils]: 39: Hoare triple {2036#false} assume !(0 == ~E_6~0); {2036#false} is VALID [2022-02-21 04:23:08,987 INFO L290 TraceCheckUtils]: 40: Hoare triple {2036#false} assume !(0 == ~E_7~0); {2036#false} is VALID [2022-02-21 04:23:08,987 INFO L290 TraceCheckUtils]: 41: Hoare triple {2036#false} assume !(0 == ~E_8~0); {2036#false} is VALID [2022-02-21 04:23:08,987 INFO L290 TraceCheckUtils]: 42: Hoare triple {2036#false} assume !(0 == ~E_9~0); {2036#false} is VALID [2022-02-21 04:23:08,988 INFO L290 TraceCheckUtils]: 43: Hoare triple {2036#false} assume 0 == ~E_10~0;~E_10~0 := 1; {2036#false} is VALID [2022-02-21 04:23:08,988 INFO L290 TraceCheckUtils]: 44: Hoare triple {2036#false} assume !(0 == ~E_11~0); {2036#false} is VALID [2022-02-21 04:23:08,988 INFO L290 TraceCheckUtils]: 45: Hoare triple {2036#false} assume !(0 == ~E_12~0); {2036#false} is VALID [2022-02-21 04:23:08,989 INFO L290 TraceCheckUtils]: 46: Hoare triple {2036#false} assume !(0 == ~E_13~0); {2036#false} is VALID [2022-02-21 04:23:08,989 INFO L290 TraceCheckUtils]: 47: Hoare triple {2036#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2036#false} is VALID [2022-02-21 04:23:08,989 INFO L290 TraceCheckUtils]: 48: Hoare triple {2036#false} assume !(1 == ~m_pc~0); {2036#false} is VALID [2022-02-21 04:23:08,989 INFO L290 TraceCheckUtils]: 49: Hoare triple {2036#false} is_master_triggered_~__retres1~0#1 := 0; {2036#false} is VALID [2022-02-21 04:23:08,992 INFO L290 TraceCheckUtils]: 50: Hoare triple {2036#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2036#false} is VALID [2022-02-21 04:23:08,992 INFO L290 TraceCheckUtils]: 51: Hoare triple {2036#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {2036#false} is VALID [2022-02-21 04:23:08,993 INFO L290 TraceCheckUtils]: 52: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp~1#1); {2036#false} is VALID [2022-02-21 04:23:08,993 INFO L290 TraceCheckUtils]: 53: Hoare triple {2036#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2036#false} is VALID [2022-02-21 04:23:08,993 INFO L290 TraceCheckUtils]: 54: Hoare triple {2036#false} assume 1 == ~t1_pc~0; {2036#false} is VALID [2022-02-21 04:23:08,993 INFO L290 TraceCheckUtils]: 55: Hoare triple {2036#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {2036#false} is VALID [2022-02-21 04:23:08,994 INFO L290 TraceCheckUtils]: 56: Hoare triple {2036#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2036#false} is VALID [2022-02-21 04:23:08,994 INFO L290 TraceCheckUtils]: 57: Hoare triple {2036#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {2036#false} is VALID [2022-02-21 04:23:08,995 INFO L290 TraceCheckUtils]: 58: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___0~0#1); {2036#false} is VALID [2022-02-21 04:23:08,996 INFO L290 TraceCheckUtils]: 59: Hoare triple {2036#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2036#false} is VALID [2022-02-21 04:23:08,997 INFO L290 TraceCheckUtils]: 60: Hoare triple {2036#false} assume 1 == ~t2_pc~0; {2036#false} is VALID [2022-02-21 04:23:08,997 INFO L290 TraceCheckUtils]: 61: Hoare triple {2036#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2036#false} is VALID [2022-02-21 04:23:08,998 INFO L290 TraceCheckUtils]: 62: Hoare triple {2036#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2036#false} is VALID [2022-02-21 04:23:08,998 INFO L290 TraceCheckUtils]: 63: Hoare triple {2036#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {2036#false} is VALID [2022-02-21 04:23:08,999 INFO L290 TraceCheckUtils]: 64: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___1~0#1); {2036#false} is VALID [2022-02-21 04:23:09,005 INFO L290 TraceCheckUtils]: 65: Hoare triple {2036#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2036#false} is VALID [2022-02-21 04:23:09,005 INFO L290 TraceCheckUtils]: 66: Hoare triple {2036#false} assume !(1 == ~t3_pc~0); {2036#false} is VALID [2022-02-21 04:23:09,006 INFO L290 TraceCheckUtils]: 67: Hoare triple {2036#false} is_transmit3_triggered_~__retres1~3#1 := 0; {2036#false} is VALID [2022-02-21 04:23:09,006 INFO L290 TraceCheckUtils]: 68: Hoare triple {2036#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2036#false} is VALID [2022-02-21 04:23:09,006 INFO L290 TraceCheckUtils]: 69: Hoare triple {2036#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {2036#false} is VALID [2022-02-21 04:23:09,007 INFO L290 TraceCheckUtils]: 70: Hoare triple {2036#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {2036#false} is VALID [2022-02-21 04:23:09,007 INFO L290 TraceCheckUtils]: 71: Hoare triple {2036#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2036#false} is VALID [2022-02-21 04:23:09,007 INFO L290 TraceCheckUtils]: 72: Hoare triple {2036#false} assume 1 == ~t4_pc~0; {2036#false} is VALID [2022-02-21 04:23:09,008 INFO L290 TraceCheckUtils]: 73: Hoare triple {2036#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {2036#false} is VALID [2022-02-21 04:23:09,010 INFO L290 TraceCheckUtils]: 74: Hoare triple {2036#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2036#false} is VALID [2022-02-21 04:23:09,011 INFO L290 TraceCheckUtils]: 75: Hoare triple {2036#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {2036#false} is VALID [2022-02-21 04:23:09,011 INFO L290 TraceCheckUtils]: 76: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___3~0#1); {2036#false} is VALID [2022-02-21 04:23:09,011 INFO L290 TraceCheckUtils]: 77: Hoare triple {2036#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {2036#false} is VALID [2022-02-21 04:23:09,011 INFO L290 TraceCheckUtils]: 78: Hoare triple {2036#false} assume !(1 == ~t5_pc~0); {2036#false} is VALID [2022-02-21 04:23:09,012 INFO L290 TraceCheckUtils]: 79: Hoare triple {2036#false} is_transmit5_triggered_~__retres1~5#1 := 0; {2036#false} is VALID [2022-02-21 04:23:09,012 INFO L290 TraceCheckUtils]: 80: Hoare triple {2036#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {2036#false} is VALID [2022-02-21 04:23:09,012 INFO L290 TraceCheckUtils]: 81: Hoare triple {2036#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {2036#false} is VALID [2022-02-21 04:23:09,012 INFO L290 TraceCheckUtils]: 82: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___4~0#1); {2036#false} is VALID [2022-02-21 04:23:09,013 INFO L290 TraceCheckUtils]: 83: Hoare triple {2036#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {2036#false} is VALID [2022-02-21 04:23:09,013 INFO L290 TraceCheckUtils]: 84: Hoare triple {2036#false} assume 1 == ~t6_pc~0; {2036#false} is VALID [2022-02-21 04:23:09,013 INFO L290 TraceCheckUtils]: 85: Hoare triple {2036#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {2036#false} is VALID [2022-02-21 04:23:09,013 INFO L290 TraceCheckUtils]: 86: Hoare triple {2036#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {2036#false} is VALID [2022-02-21 04:23:09,013 INFO L290 TraceCheckUtils]: 87: Hoare triple {2036#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {2036#false} is VALID [2022-02-21 04:23:09,014 INFO L290 TraceCheckUtils]: 88: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___5~0#1); {2036#false} is VALID [2022-02-21 04:23:09,014 INFO L290 TraceCheckUtils]: 89: Hoare triple {2036#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {2036#false} is VALID [2022-02-21 04:23:09,014 INFO L290 TraceCheckUtils]: 90: Hoare triple {2036#false} assume !(1 == ~t7_pc~0); {2036#false} is VALID [2022-02-21 04:23:09,014 INFO L290 TraceCheckUtils]: 91: Hoare triple {2036#false} is_transmit7_triggered_~__retres1~7#1 := 0; {2036#false} is VALID [2022-02-21 04:23:09,014 INFO L290 TraceCheckUtils]: 92: Hoare triple {2036#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {2036#false} is VALID [2022-02-21 04:23:09,015 INFO L290 TraceCheckUtils]: 93: Hoare triple {2036#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {2036#false} is VALID [2022-02-21 04:23:09,015 INFO L290 TraceCheckUtils]: 94: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___6~0#1); {2036#false} is VALID [2022-02-21 04:23:09,015 INFO L290 TraceCheckUtils]: 95: Hoare triple {2036#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {2036#false} is VALID [2022-02-21 04:23:09,015 INFO L290 TraceCheckUtils]: 96: Hoare triple {2036#false} assume 1 == ~t8_pc~0; {2036#false} is VALID [2022-02-21 04:23:09,016 INFO L290 TraceCheckUtils]: 97: Hoare triple {2036#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {2036#false} is VALID [2022-02-21 04:23:09,016 INFO L290 TraceCheckUtils]: 98: Hoare triple {2036#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {2036#false} is VALID [2022-02-21 04:23:09,016 INFO L290 TraceCheckUtils]: 99: Hoare triple {2036#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {2036#false} is VALID [2022-02-21 04:23:09,016 INFO L290 TraceCheckUtils]: 100: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___7~0#1); {2036#false} is VALID [2022-02-21 04:23:09,016 INFO L290 TraceCheckUtils]: 101: Hoare triple {2036#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {2036#false} is VALID [2022-02-21 04:23:09,017 INFO L290 TraceCheckUtils]: 102: Hoare triple {2036#false} assume 1 == ~t9_pc~0; {2036#false} is VALID [2022-02-21 04:23:09,017 INFO L290 TraceCheckUtils]: 103: Hoare triple {2036#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {2036#false} is VALID [2022-02-21 04:23:09,017 INFO L290 TraceCheckUtils]: 104: Hoare triple {2036#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {2036#false} is VALID [2022-02-21 04:23:09,017 INFO L290 TraceCheckUtils]: 105: Hoare triple {2036#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {2036#false} is VALID [2022-02-21 04:23:09,019 INFO L290 TraceCheckUtils]: 106: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___8~0#1); {2036#false} is VALID [2022-02-21 04:23:09,020 INFO L290 TraceCheckUtils]: 107: Hoare triple {2036#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {2036#false} is VALID [2022-02-21 04:23:09,020 INFO L290 TraceCheckUtils]: 108: Hoare triple {2036#false} assume !(1 == ~t10_pc~0); {2036#false} is VALID [2022-02-21 04:23:09,020 INFO L290 TraceCheckUtils]: 109: Hoare triple {2036#false} is_transmit10_triggered_~__retres1~10#1 := 0; {2036#false} is VALID [2022-02-21 04:23:09,020 INFO L290 TraceCheckUtils]: 110: Hoare triple {2036#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {2036#false} is VALID [2022-02-21 04:23:09,021 INFO L290 TraceCheckUtils]: 111: Hoare triple {2036#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {2036#false} is VALID [2022-02-21 04:23:09,021 INFO L290 TraceCheckUtils]: 112: Hoare triple {2036#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {2036#false} is VALID [2022-02-21 04:23:09,021 INFO L290 TraceCheckUtils]: 113: Hoare triple {2036#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {2036#false} is VALID [2022-02-21 04:23:09,021 INFO L290 TraceCheckUtils]: 114: Hoare triple {2036#false} assume 1 == ~t11_pc~0; {2036#false} is VALID [2022-02-21 04:23:09,022 INFO L290 TraceCheckUtils]: 115: Hoare triple {2036#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {2036#false} is VALID [2022-02-21 04:23:09,022 INFO L290 TraceCheckUtils]: 116: Hoare triple {2036#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {2036#false} is VALID [2022-02-21 04:23:09,022 INFO L290 TraceCheckUtils]: 117: Hoare triple {2036#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {2036#false} is VALID [2022-02-21 04:23:09,023 INFO L290 TraceCheckUtils]: 118: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___10~0#1); {2036#false} is VALID [2022-02-21 04:23:09,023 INFO L290 TraceCheckUtils]: 119: Hoare triple {2036#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {2036#false} is VALID [2022-02-21 04:23:09,024 INFO L290 TraceCheckUtils]: 120: Hoare triple {2036#false} assume !(1 == ~t12_pc~0); {2036#false} is VALID [2022-02-21 04:23:09,024 INFO L290 TraceCheckUtils]: 121: Hoare triple {2036#false} is_transmit12_triggered_~__retres1~12#1 := 0; {2036#false} is VALID [2022-02-21 04:23:09,032 INFO L290 TraceCheckUtils]: 122: Hoare triple {2036#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {2036#false} is VALID [2022-02-21 04:23:09,033 INFO L290 TraceCheckUtils]: 123: Hoare triple {2036#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {2036#false} is VALID [2022-02-21 04:23:09,033 INFO L290 TraceCheckUtils]: 124: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___11~0#1); {2036#false} is VALID [2022-02-21 04:23:09,034 INFO L290 TraceCheckUtils]: 125: Hoare triple {2036#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {2036#false} is VALID [2022-02-21 04:23:09,034 INFO L290 TraceCheckUtils]: 126: Hoare triple {2036#false} assume 1 == ~t13_pc~0; {2036#false} is VALID [2022-02-21 04:23:09,034 INFO L290 TraceCheckUtils]: 127: Hoare triple {2036#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {2036#false} is VALID [2022-02-21 04:23:09,035 INFO L290 TraceCheckUtils]: 128: Hoare triple {2036#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {2036#false} is VALID [2022-02-21 04:23:09,035 INFO L290 TraceCheckUtils]: 129: Hoare triple {2036#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {2036#false} is VALID [2022-02-21 04:23:09,035 INFO L290 TraceCheckUtils]: 130: Hoare triple {2036#false} assume !(0 != activate_threads_~tmp___12~0#1); {2036#false} is VALID [2022-02-21 04:23:09,035 INFO L290 TraceCheckUtils]: 131: Hoare triple {2036#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2036#false} is VALID [2022-02-21 04:23:09,035 INFO L290 TraceCheckUtils]: 132: Hoare triple {2036#false} assume !(1 == ~M_E~0); {2036#false} is VALID [2022-02-21 04:23:09,036 INFO L290 TraceCheckUtils]: 133: Hoare triple {2036#false} assume !(1 == ~T1_E~0); {2036#false} is VALID [2022-02-21 04:23:09,036 INFO L290 TraceCheckUtils]: 134: Hoare triple {2036#false} assume !(1 == ~T2_E~0); {2036#false} is VALID [2022-02-21 04:23:09,036 INFO L290 TraceCheckUtils]: 135: Hoare triple {2036#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {2036#false} is VALID [2022-02-21 04:23:09,036 INFO L290 TraceCheckUtils]: 136: Hoare triple {2036#false} assume !(1 == ~T4_E~0); {2036#false} is VALID [2022-02-21 04:23:09,036 INFO L290 TraceCheckUtils]: 137: Hoare triple {2036#false} assume !(1 == ~T5_E~0); {2036#false} is VALID [2022-02-21 04:23:09,038 INFO L290 TraceCheckUtils]: 138: Hoare triple {2036#false} assume !(1 == ~T6_E~0); {2036#false} is VALID [2022-02-21 04:23:09,038 INFO L290 TraceCheckUtils]: 139: Hoare triple {2036#false} assume !(1 == ~T7_E~0); {2036#false} is VALID [2022-02-21 04:23:09,038 INFO L290 TraceCheckUtils]: 140: Hoare triple {2036#false} assume !(1 == ~T8_E~0); {2036#false} is VALID [2022-02-21 04:23:09,038 INFO L290 TraceCheckUtils]: 141: Hoare triple {2036#false} assume !(1 == ~T9_E~0); {2036#false} is VALID [2022-02-21 04:23:09,038 INFO L290 TraceCheckUtils]: 142: Hoare triple {2036#false} assume !(1 == ~T10_E~0); {2036#false} is VALID [2022-02-21 04:23:09,039 INFO L290 TraceCheckUtils]: 143: Hoare triple {2036#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {2036#false} is VALID [2022-02-21 04:23:09,039 INFO L290 TraceCheckUtils]: 144: Hoare triple {2036#false} assume !(1 == ~T12_E~0); {2036#false} is VALID [2022-02-21 04:23:09,039 INFO L290 TraceCheckUtils]: 145: Hoare triple {2036#false} assume !(1 == ~T13_E~0); {2036#false} is VALID [2022-02-21 04:23:09,039 INFO L290 TraceCheckUtils]: 146: Hoare triple {2036#false} assume !(1 == ~E_M~0); {2036#false} is VALID [2022-02-21 04:23:09,039 INFO L290 TraceCheckUtils]: 147: Hoare triple {2036#false} assume !(1 == ~E_1~0); {2036#false} is VALID [2022-02-21 04:23:09,040 INFO L290 TraceCheckUtils]: 148: Hoare triple {2036#false} assume !(1 == ~E_2~0); {2036#false} is VALID [2022-02-21 04:23:09,040 INFO L290 TraceCheckUtils]: 149: Hoare triple {2036#false} assume !(1 == ~E_3~0); {2036#false} is VALID [2022-02-21 04:23:09,040 INFO L290 TraceCheckUtils]: 150: Hoare triple {2036#false} assume !(1 == ~E_4~0); {2036#false} is VALID [2022-02-21 04:23:09,040 INFO L290 TraceCheckUtils]: 151: Hoare triple {2036#false} assume 1 == ~E_5~0;~E_5~0 := 2; {2036#false} is VALID [2022-02-21 04:23:09,040 INFO L290 TraceCheckUtils]: 152: Hoare triple {2036#false} assume !(1 == ~E_6~0); {2036#false} is VALID [2022-02-21 04:23:09,041 INFO L290 TraceCheckUtils]: 153: Hoare triple {2036#false} assume !(1 == ~E_7~0); {2036#false} is VALID [2022-02-21 04:23:09,041 INFO L290 TraceCheckUtils]: 154: Hoare triple {2036#false} assume !(1 == ~E_8~0); {2036#false} is VALID [2022-02-21 04:23:09,041 INFO L290 TraceCheckUtils]: 155: Hoare triple {2036#false} assume !(1 == ~E_9~0); {2036#false} is VALID [2022-02-21 04:23:09,041 INFO L290 TraceCheckUtils]: 156: Hoare triple {2036#false} assume !(1 == ~E_10~0); {2036#false} is VALID [2022-02-21 04:23:09,041 INFO L290 TraceCheckUtils]: 157: Hoare triple {2036#false} assume !(1 == ~E_11~0); {2036#false} is VALID [2022-02-21 04:23:09,042 INFO L290 TraceCheckUtils]: 158: Hoare triple {2036#false} assume !(1 == ~E_12~0); {2036#false} is VALID [2022-02-21 04:23:09,042 INFO L290 TraceCheckUtils]: 159: Hoare triple {2036#false} assume 1 == ~E_13~0;~E_13~0 := 2; {2036#false} is VALID [2022-02-21 04:23:09,042 INFO L290 TraceCheckUtils]: 160: Hoare triple {2036#false} assume { :end_inline_reset_delta_events } true; {2036#false} is VALID [2022-02-21 04:23:09,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,044 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,044 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2078358300] [2022-02-21 04:23:09,046 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2078358300] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,046 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,046 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:09,048 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024777190] [2022-02-21 04:23:09,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,053 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:09,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1120841461, now seen corresponding path program 1 times [2022-02-21 04:23:09,055 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,055 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078264288] [2022-02-21 04:23:09,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 0: Hoare triple {2038#true} assume !false; {2038#true} is VALID [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 1: Hoare triple {2038#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {2038#true} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 2: Hoare triple {2038#true} assume false; {2039#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 3: Hoare triple {2039#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {2039#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 4: Hoare triple {2039#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {2039#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 5: Hoare triple {2039#false} assume 0 == ~M_E~0;~M_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 6: Hoare triple {2039#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 7: Hoare triple {2039#false} assume !(0 == ~T2_E~0); {2039#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 8: Hoare triple {2039#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 9: Hoare triple {2039#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 10: Hoare triple {2039#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 11: Hoare triple {2039#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 12: Hoare triple {2039#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 13: Hoare triple {2039#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,128 INFO L290 TraceCheckUtils]: 14: Hoare triple {2039#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 15: Hoare triple {2039#false} assume !(0 == ~T10_E~0); {2039#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 16: Hoare triple {2039#false} assume 0 == ~T11_E~0;~T11_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 17: Hoare triple {2039#false} assume 0 == ~T12_E~0;~T12_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 18: Hoare triple {2039#false} assume 0 == ~T13_E~0;~T13_E~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 19: Hoare triple {2039#false} assume 0 == ~E_M~0;~E_M~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 20: Hoare triple {2039#false} assume 0 == ~E_1~0;~E_1~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 21: Hoare triple {2039#false} assume 0 == ~E_2~0;~E_2~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 22: Hoare triple {2039#false} assume 0 == ~E_3~0;~E_3~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 23: Hoare triple {2039#false} assume !(0 == ~E_4~0); {2039#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 24: Hoare triple {2039#false} assume 0 == ~E_5~0;~E_5~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,135 INFO L290 TraceCheckUtils]: 25: Hoare triple {2039#false} assume 0 == ~E_6~0;~E_6~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,137 INFO L290 TraceCheckUtils]: 26: Hoare triple {2039#false} assume 0 == ~E_7~0;~E_7~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,138 INFO L290 TraceCheckUtils]: 27: Hoare triple {2039#false} assume 0 == ~E_8~0;~E_8~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,138 INFO L290 TraceCheckUtils]: 28: Hoare triple {2039#false} assume 0 == ~E_9~0;~E_9~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,138 INFO L290 TraceCheckUtils]: 29: Hoare triple {2039#false} assume 0 == ~E_10~0;~E_10~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,139 INFO L290 TraceCheckUtils]: 30: Hoare triple {2039#false} assume 0 == ~E_11~0;~E_11~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,140 INFO L290 TraceCheckUtils]: 31: Hoare triple {2039#false} assume !(0 == ~E_12~0); {2039#false} is VALID [2022-02-21 04:23:09,140 INFO L290 TraceCheckUtils]: 32: Hoare triple {2039#false} assume 0 == ~E_13~0;~E_13~0 := 1; {2039#false} is VALID [2022-02-21 04:23:09,140 INFO L290 TraceCheckUtils]: 33: Hoare triple {2039#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2039#false} is VALID [2022-02-21 04:23:09,140 INFO L290 TraceCheckUtils]: 34: Hoare triple {2039#false} assume !(1 == ~m_pc~0); {2039#false} is VALID [2022-02-21 04:23:09,140 INFO L290 TraceCheckUtils]: 35: Hoare triple {2039#false} is_master_triggered_~__retres1~0#1 := 0; {2039#false} is VALID [2022-02-21 04:23:09,141 INFO L290 TraceCheckUtils]: 36: Hoare triple {2039#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2039#false} is VALID [2022-02-21 04:23:09,141 INFO L290 TraceCheckUtils]: 37: Hoare triple {2039#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {2039#false} is VALID [2022-02-21 04:23:09,141 INFO L290 TraceCheckUtils]: 38: Hoare triple {2039#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,141 INFO L290 TraceCheckUtils]: 39: Hoare triple {2039#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2039#false} is VALID [2022-02-21 04:23:09,141 INFO L290 TraceCheckUtils]: 40: Hoare triple {2039#false} assume 1 == ~t1_pc~0; {2039#false} is VALID [2022-02-21 04:23:09,142 INFO L290 TraceCheckUtils]: 41: Hoare triple {2039#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {2039#false} is VALID [2022-02-21 04:23:09,142 INFO L290 TraceCheckUtils]: 42: Hoare triple {2039#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2039#false} is VALID [2022-02-21 04:23:09,145 INFO L290 TraceCheckUtils]: 43: Hoare triple {2039#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {2039#false} is VALID [2022-02-21 04:23:09,145 INFO L290 TraceCheckUtils]: 44: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,145 INFO L290 TraceCheckUtils]: 45: Hoare triple {2039#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2039#false} is VALID [2022-02-21 04:23:09,146 INFO L290 TraceCheckUtils]: 46: Hoare triple {2039#false} assume 1 == ~t2_pc~0; {2039#false} is VALID [2022-02-21 04:23:09,146 INFO L290 TraceCheckUtils]: 47: Hoare triple {2039#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2039#false} is VALID [2022-02-21 04:23:09,146 INFO L290 TraceCheckUtils]: 48: Hoare triple {2039#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2039#false} is VALID [2022-02-21 04:23:09,146 INFO L290 TraceCheckUtils]: 49: Hoare triple {2039#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {2039#false} is VALID [2022-02-21 04:23:09,146 INFO L290 TraceCheckUtils]: 50: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,146 INFO L290 TraceCheckUtils]: 51: Hoare triple {2039#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2039#false} is VALID [2022-02-21 04:23:09,147 INFO L290 TraceCheckUtils]: 52: Hoare triple {2039#false} assume !(1 == ~t3_pc~0); {2039#false} is VALID [2022-02-21 04:23:09,147 INFO L290 TraceCheckUtils]: 53: Hoare triple {2039#false} is_transmit3_triggered_~__retres1~3#1 := 0; {2039#false} is VALID [2022-02-21 04:23:09,147 INFO L290 TraceCheckUtils]: 54: Hoare triple {2039#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2039#false} is VALID [2022-02-21 04:23:09,147 INFO L290 TraceCheckUtils]: 55: Hoare triple {2039#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {2039#false} is VALID [2022-02-21 04:23:09,147 INFO L290 TraceCheckUtils]: 56: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,148 INFO L290 TraceCheckUtils]: 57: Hoare triple {2039#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2039#false} is VALID [2022-02-21 04:23:09,148 INFO L290 TraceCheckUtils]: 58: Hoare triple {2039#false} assume 1 == ~t4_pc~0; {2039#false} is VALID [2022-02-21 04:23:09,148 INFO L290 TraceCheckUtils]: 59: Hoare triple {2039#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {2039#false} is VALID [2022-02-21 04:23:09,148 INFO L290 TraceCheckUtils]: 60: Hoare triple {2039#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2039#false} is VALID [2022-02-21 04:23:09,148 INFO L290 TraceCheckUtils]: 61: Hoare triple {2039#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {2039#false} is VALID [2022-02-21 04:23:09,149 INFO L290 TraceCheckUtils]: 62: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,149 INFO L290 TraceCheckUtils]: 63: Hoare triple {2039#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {2039#false} is VALID [2022-02-21 04:23:09,149 INFO L290 TraceCheckUtils]: 64: Hoare triple {2039#false} assume !(1 == ~t5_pc~0); {2039#false} is VALID [2022-02-21 04:23:09,149 INFO L290 TraceCheckUtils]: 65: Hoare triple {2039#false} is_transmit5_triggered_~__retres1~5#1 := 0; {2039#false} is VALID [2022-02-21 04:23:09,149 INFO L290 TraceCheckUtils]: 66: Hoare triple {2039#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {2039#false} is VALID [2022-02-21 04:23:09,150 INFO L290 TraceCheckUtils]: 67: Hoare triple {2039#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {2039#false} is VALID [2022-02-21 04:23:09,150 INFO L290 TraceCheckUtils]: 68: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,150 INFO L290 TraceCheckUtils]: 69: Hoare triple {2039#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {2039#false} is VALID [2022-02-21 04:23:09,150 INFO L290 TraceCheckUtils]: 70: Hoare triple {2039#false} assume !(1 == ~t6_pc~0); {2039#false} is VALID [2022-02-21 04:23:09,150 INFO L290 TraceCheckUtils]: 71: Hoare triple {2039#false} is_transmit6_triggered_~__retres1~6#1 := 0; {2039#false} is VALID [2022-02-21 04:23:09,151 INFO L290 TraceCheckUtils]: 72: Hoare triple {2039#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {2039#false} is VALID [2022-02-21 04:23:09,151 INFO L290 TraceCheckUtils]: 73: Hoare triple {2039#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {2039#false} is VALID [2022-02-21 04:23:09,151 INFO L290 TraceCheckUtils]: 74: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,151 INFO L290 TraceCheckUtils]: 75: Hoare triple {2039#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {2039#false} is VALID [2022-02-21 04:23:09,151 INFO L290 TraceCheckUtils]: 76: Hoare triple {2039#false} assume !(1 == ~t7_pc~0); {2039#false} is VALID [2022-02-21 04:23:09,152 INFO L290 TraceCheckUtils]: 77: Hoare triple {2039#false} is_transmit7_triggered_~__retres1~7#1 := 0; {2039#false} is VALID [2022-02-21 04:23:09,152 INFO L290 TraceCheckUtils]: 78: Hoare triple {2039#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {2039#false} is VALID [2022-02-21 04:23:09,152 INFO L290 TraceCheckUtils]: 79: Hoare triple {2039#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {2039#false} is VALID [2022-02-21 04:23:09,152 INFO L290 TraceCheckUtils]: 80: Hoare triple {2039#false} assume !(0 != activate_threads_~tmp___6~0#1); {2039#false} is VALID [2022-02-21 04:23:09,152 INFO L290 TraceCheckUtils]: 81: Hoare triple {2039#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {2039#false} is VALID [2022-02-21 04:23:09,153 INFO L290 TraceCheckUtils]: 82: Hoare triple {2039#false} assume 1 == ~t8_pc~0; {2039#false} is VALID [2022-02-21 04:23:09,153 INFO L290 TraceCheckUtils]: 83: Hoare triple {2039#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {2039#false} is VALID [2022-02-21 04:23:09,153 INFO L290 TraceCheckUtils]: 84: Hoare triple {2039#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {2039#false} is VALID [2022-02-21 04:23:09,153 INFO L290 TraceCheckUtils]: 85: Hoare triple {2039#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {2039#false} is VALID [2022-02-21 04:23:09,153 INFO L290 TraceCheckUtils]: 86: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,154 INFO L290 TraceCheckUtils]: 87: Hoare triple {2039#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {2039#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 88: Hoare triple {2039#false} assume !(1 == ~t9_pc~0); {2039#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 89: Hoare triple {2039#false} is_transmit9_triggered_~__retres1~9#1 := 0; {2039#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 90: Hoare triple {2039#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {2039#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 91: Hoare triple {2039#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {2039#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 92: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 93: Hoare triple {2039#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {2039#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 94: Hoare triple {2039#false} assume 1 == ~t10_pc~0; {2039#false} is VALID [2022-02-21 04:23:09,166 INFO L290 TraceCheckUtils]: 95: Hoare triple {2039#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {2039#false} is VALID [2022-02-21 04:23:09,166 INFO L290 TraceCheckUtils]: 96: Hoare triple {2039#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {2039#false} is VALID [2022-02-21 04:23:09,166 INFO L290 TraceCheckUtils]: 97: Hoare triple {2039#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {2039#false} is VALID [2022-02-21 04:23:09,167 INFO L290 TraceCheckUtils]: 98: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,167 INFO L290 TraceCheckUtils]: 99: Hoare triple {2039#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {2039#false} is VALID [2022-02-21 04:23:09,167 INFO L290 TraceCheckUtils]: 100: Hoare triple {2039#false} assume !(1 == ~t11_pc~0); {2039#false} is VALID [2022-02-21 04:23:09,167 INFO L290 TraceCheckUtils]: 101: Hoare triple {2039#false} is_transmit11_triggered_~__retres1~11#1 := 0; {2039#false} is VALID [2022-02-21 04:23:09,167 INFO L290 TraceCheckUtils]: 102: Hoare triple {2039#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {2039#false} is VALID [2022-02-21 04:23:09,167 INFO L290 TraceCheckUtils]: 103: Hoare triple {2039#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {2039#false} is VALID [2022-02-21 04:23:09,168 INFO L290 TraceCheckUtils]: 104: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,168 INFO L290 TraceCheckUtils]: 105: Hoare triple {2039#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {2039#false} is VALID [2022-02-21 04:23:09,168 INFO L290 TraceCheckUtils]: 106: Hoare triple {2039#false} assume 1 == ~t12_pc~0; {2039#false} is VALID [2022-02-21 04:23:09,168 INFO L290 TraceCheckUtils]: 107: Hoare triple {2039#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {2039#false} is VALID [2022-02-21 04:23:09,168 INFO L290 TraceCheckUtils]: 108: Hoare triple {2039#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {2039#false} is VALID [2022-02-21 04:23:09,169 INFO L290 TraceCheckUtils]: 109: Hoare triple {2039#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {2039#false} is VALID [2022-02-21 04:23:09,169 INFO L290 TraceCheckUtils]: 110: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,169 INFO L290 TraceCheckUtils]: 111: Hoare triple {2039#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {2039#false} is VALID [2022-02-21 04:23:09,169 INFO L290 TraceCheckUtils]: 112: Hoare triple {2039#false} assume !(1 == ~t13_pc~0); {2039#false} is VALID [2022-02-21 04:23:09,169 INFO L290 TraceCheckUtils]: 113: Hoare triple {2039#false} is_transmit13_triggered_~__retres1~13#1 := 0; {2039#false} is VALID [2022-02-21 04:23:09,169 INFO L290 TraceCheckUtils]: 114: Hoare triple {2039#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {2039#false} is VALID [2022-02-21 04:23:09,170 INFO L290 TraceCheckUtils]: 115: Hoare triple {2039#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {2039#false} is VALID [2022-02-21 04:23:09,170 INFO L290 TraceCheckUtils]: 116: Hoare triple {2039#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {2039#false} is VALID [2022-02-21 04:23:09,170 INFO L290 TraceCheckUtils]: 117: Hoare triple {2039#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2039#false} is VALID [2022-02-21 04:23:09,170 INFO L290 TraceCheckUtils]: 118: Hoare triple {2039#false} assume 1 == ~M_E~0;~M_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,170 INFO L290 TraceCheckUtils]: 119: Hoare triple {2039#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,171 INFO L290 TraceCheckUtils]: 120: Hoare triple {2039#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,171 INFO L290 TraceCheckUtils]: 121: Hoare triple {2039#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,171 INFO L290 TraceCheckUtils]: 122: Hoare triple {2039#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,171 INFO L290 TraceCheckUtils]: 123: Hoare triple {2039#false} assume !(1 == ~T5_E~0); {2039#false} is VALID [2022-02-21 04:23:09,171 INFO L290 TraceCheckUtils]: 124: Hoare triple {2039#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 125: Hoare triple {2039#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 126: Hoare triple {2039#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 127: Hoare triple {2039#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 128: Hoare triple {2039#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 129: Hoare triple {2039#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,173 INFO L290 TraceCheckUtils]: 130: Hoare triple {2039#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,173 INFO L290 TraceCheckUtils]: 131: Hoare triple {2039#false} assume !(1 == ~T13_E~0); {2039#false} is VALID [2022-02-21 04:23:09,173 INFO L290 TraceCheckUtils]: 132: Hoare triple {2039#false} assume 1 == ~E_M~0;~E_M~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,173 INFO L290 TraceCheckUtils]: 133: Hoare triple {2039#false} assume 1 == ~E_1~0;~E_1~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,173 INFO L290 TraceCheckUtils]: 134: Hoare triple {2039#false} assume 1 == ~E_2~0;~E_2~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,173 INFO L290 TraceCheckUtils]: 135: Hoare triple {2039#false} assume 1 == ~E_3~0;~E_3~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,174 INFO L290 TraceCheckUtils]: 136: Hoare triple {2039#false} assume 1 == ~E_4~0;~E_4~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,174 INFO L290 TraceCheckUtils]: 137: Hoare triple {2039#false} assume 1 == ~E_5~0;~E_5~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,174 INFO L290 TraceCheckUtils]: 138: Hoare triple {2039#false} assume 1 == ~E_6~0;~E_6~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,174 INFO L290 TraceCheckUtils]: 139: Hoare triple {2039#false} assume !(1 == ~E_7~0); {2039#false} is VALID [2022-02-21 04:23:09,174 INFO L290 TraceCheckUtils]: 140: Hoare triple {2039#false} assume 1 == ~E_8~0;~E_8~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,175 INFO L290 TraceCheckUtils]: 141: Hoare triple {2039#false} assume 1 == ~E_9~0;~E_9~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,175 INFO L290 TraceCheckUtils]: 142: Hoare triple {2039#false} assume 1 == ~E_10~0;~E_10~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,175 INFO L290 TraceCheckUtils]: 143: Hoare triple {2039#false} assume 1 == ~E_11~0;~E_11~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,175 INFO L290 TraceCheckUtils]: 144: Hoare triple {2039#false} assume 1 == ~E_12~0;~E_12~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,175 INFO L290 TraceCheckUtils]: 145: Hoare triple {2039#false} assume 1 == ~E_13~0;~E_13~0 := 2; {2039#false} is VALID [2022-02-21 04:23:09,175 INFO L290 TraceCheckUtils]: 146: Hoare triple {2039#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {2039#false} is VALID [2022-02-21 04:23:09,176 INFO L290 TraceCheckUtils]: 147: Hoare triple {2039#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {2039#false} is VALID [2022-02-21 04:23:09,176 INFO L290 TraceCheckUtils]: 148: Hoare triple {2039#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {2039#false} is VALID [2022-02-21 04:23:09,176 INFO L290 TraceCheckUtils]: 149: Hoare triple {2039#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {2039#false} is VALID [2022-02-21 04:23:09,176 INFO L290 TraceCheckUtils]: 150: Hoare triple {2039#false} assume !(0 == start_simulation_~tmp~3#1); {2039#false} is VALID [2022-02-21 04:23:09,176 INFO L290 TraceCheckUtils]: 151: Hoare triple {2039#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {2039#false} is VALID [2022-02-21 04:23:09,177 INFO L290 TraceCheckUtils]: 152: Hoare triple {2039#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {2039#false} is VALID [2022-02-21 04:23:09,177 INFO L290 TraceCheckUtils]: 153: Hoare triple {2039#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {2039#false} is VALID [2022-02-21 04:23:09,177 INFO L290 TraceCheckUtils]: 154: Hoare triple {2039#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {2039#false} is VALID [2022-02-21 04:23:09,177 INFO L290 TraceCheckUtils]: 155: Hoare triple {2039#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {2039#false} is VALID [2022-02-21 04:23:09,177 INFO L290 TraceCheckUtils]: 156: Hoare triple {2039#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {2039#false} is VALID [2022-02-21 04:23:09,178 INFO L290 TraceCheckUtils]: 157: Hoare triple {2039#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {2039#false} is VALID [2022-02-21 04:23:09,178 INFO L290 TraceCheckUtils]: 158: Hoare triple {2039#false} assume !(0 != start_simulation_~tmp___0~1#1); {2039#false} is VALID [2022-02-21 04:23:09,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,179 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,179 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2078264288] [2022-02-21 04:23:09,179 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2078264288] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,180 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,180 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:09,180 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201654474] [2022-02-21 04:23:09,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,181 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:09,182 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:09,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-21 04:23:09,206 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-21 04:23:09,214 INFO L87 Difference]: Start difference. First operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,446 INFO L93 Difference]: Finished difference Result 2029 states and 3002 transitions. [2022-02-21 04:23:10,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-21 04:23:10,447 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,605 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:10,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2029 states and 3002 transitions. [2022-02-21 04:23:10,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:10,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2029 states to 2023 states and 2996 transitions. [2022-02-21 04:23:10,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:10,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:10,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2996 transitions. [2022-02-21 04:23:10,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:10,890 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2022-02-21 04:23:10,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2996 transitions. [2022-02-21 04:23:10,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:10,979 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:10,988 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2996 transitions. Second operand has 2023 states, 2023 states have (on average 1.480968858131488) internal successors, (2996), 2022 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,994 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2996 transitions. Second operand has 2023 states, 2023 states have (on average 1.480968858131488) internal successors, (2996), 2022 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,999 INFO L87 Difference]: Start difference. First operand 2023 states and 2996 transitions. Second operand has 2023 states, 2023 states have (on average 1.480968858131488) internal successors, (2996), 2022 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,123 INFO L93 Difference]: Finished difference Result 2023 states and 2996 transitions. [2022-02-21 04:23:11,124 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2996 transitions. [2022-02-21 04:23:11,130 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:11,131 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:11,135 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.480968858131488) internal successors, (2996), 2022 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2996 transitions. [2022-02-21 04:23:11,138 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.480968858131488) internal successors, (2996), 2022 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2996 transitions. [2022-02-21 04:23:11,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,287 INFO L93 Difference]: Finished difference Result 2023 states and 2996 transitions. [2022-02-21 04:23:11,287 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2996 transitions. [2022-02-21 04:23:11,290 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:11,291 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:11,291 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:11,291 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:11,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.480968858131488) internal successors, (2996), 2022 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2996 transitions. [2022-02-21 04:23:11,448 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2022-02-21 04:23:11,449 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2022-02-21 04:23:11,449 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:23:11,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2996 transitions. [2022-02-21 04:23:11,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:11,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:11,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:11,462 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,462 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,463 INFO L791 eck$LassoCheckResult]: Stem: 4996#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5995#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5996#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6081#L914 assume !(1 == ~m_i~0);~m_st~0 := 2; 5460#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4929#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4930#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5746#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5747#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5847#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5848#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4701#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4702#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5877#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5237#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5238#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5798#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5139#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5140#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 6082#L1291-2 assume !(0 == ~T1_E~0); 6080#L1296-1 assume !(0 == ~T2_E~0); 5296#L1301-1 assume !(0 == ~T3_E~0); 5297#L1306-1 assume !(0 == ~T4_E~0); 5806#L1311-1 assume !(0 == ~T5_E~0); 4544#L1316-1 assume !(0 == ~T6_E~0); 4545#L1321-1 assume !(0 == ~T7_E~0); 5309#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4372#L1331-1 assume !(0 == ~T9_E~0); 4071#L1336-1 assume !(0 == ~T10_E~0); 4072#L1341-1 assume !(0 == ~T11_E~0); 4152#L1346-1 assume !(0 == ~T12_E~0); 4153#L1351-1 assume !(0 == ~T13_E~0); 4493#L1356-1 assume !(0 == ~E_M~0); 4494#L1361-1 assume !(0 == ~E_1~0); 6021#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4534#L1371-1 assume !(0 == ~E_3~0); 4535#L1376-1 assume !(0 == ~E_4~0); 5356#L1381-1 assume !(0 == ~E_5~0); 5357#L1386-1 assume !(0 == ~E_6~0); 6051#L1391-1 assume !(0 == ~E_7~0); 6069#L1396-1 assume !(0 == ~E_8~0); 5269#L1401-1 assume !(0 == ~E_9~0); 5270#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5548#L1411-1 assume !(0 == ~E_11~0); 5549#L1416-1 assume !(0 == ~E_12~0); 5181#L1421-1 assume !(0 == ~E_13~0); 4724#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4725#L640 assume !(1 == ~m_pc~0); 5234#L640-2 is_master_triggered_~__retres1~0#1 := 0; 5233#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5325#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5219#L1603 assume !(0 != activate_threads_~tmp~1#1); 5220#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4854#L659 assume 1 == ~t1_pc~0; 4855#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4960#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5906#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4980#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 4981#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4994#L678 assume 1 == ~t2_pc~0; 5948#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5949#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6048#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5092#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 5093#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5214#L697 assume !(1 == ~t3_pc~0); 5215#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5337#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5145#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5124#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5125#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5985#L716 assume 1 == ~t4_pc~0; 5971#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4835#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4836#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4335#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 4336#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5627#L735 assume !(1 == ~t5_pc~0); 4296#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4297#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4747#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5654#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 5290#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5291#L754 assume 1 == ~t6_pc~0; 5044#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4942#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4943#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4916#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 4917#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5737#L773 assume !(1 == ~t7_pc~0); 4497#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4496#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5326#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5298#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 5299#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5346#L792 assume 1 == ~t8_pc~0; 5519#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5851#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5340#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5293#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 5217#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5218#L811 assume 1 == ~t9_pc~0; 5422#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5888#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5764#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5418#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 5230#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5231#L830 assume !(1 == ~t10_pc~0); 4952#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4476#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4169#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4170#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4457#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5755#L849 assume 1 == ~t11_pc~0; 5756#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4272#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4273#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4862#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 5661#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5662#L868 assume !(1 == ~t12_pc~0); 5077#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5076#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4871#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4872#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 4508#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4509#L887 assume 1 == ~t13_pc~0; 5676#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5118#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5119#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5555#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 4212#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4213#L1439 assume !(1 == ~M_E~0); 5286#L1439-2 assume !(1 == ~T1_E~0); 4384#L1444-1 assume !(1 == ~T2_E~0); 4385#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4858#L1454-1 assume !(1 == ~T4_E~0); 4859#L1459-1 assume !(1 == ~T5_E~0); 5415#L1464-1 assume !(1 == ~T6_E~0); 5416#L1469-1 assume !(1 == ~T7_E~0); 5488#L1474-1 assume !(1 == ~T8_E~0); 5182#L1479-1 assume !(1 == ~T9_E~0); 5183#L1484-1 assume !(1 == ~T10_E~0); 5419#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5065#L1494-1 assume !(1 == ~T12_E~0); 5066#L1499-1 assume !(1 == ~T13_E~0); 5258#L1504-1 assume !(1 == ~E_M~0); 5259#L1509-1 assume !(1 == ~E_1~0); 5834#L1514-1 assume !(1 == ~E_2~0); 5521#L1519-1 assume !(1 == ~E_3~0); 5522#L1524-1 assume !(1 == ~E_4~0); 6034#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6035#L1534-1 assume !(1 == ~E_6~0); 4205#L1539-1 assume !(1 == ~E_7~0); 4206#L1544-1 assume !(1 == ~E_8~0); 4620#L1549-1 assume !(1 == ~E_9~0); 6009#L1554-1 assume !(1 == ~E_10~0); 6005#L1559-1 assume !(1 == ~E_11~0); 5872#L1564-1 assume !(1 == ~E_12~0); 5873#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 6030#L1574-1 assume { :end_inline_reset_delta_events } true; 4382#L1940-2 [2022-02-21 04:23:11,464 INFO L793 eck$LassoCheckResult]: Loop: 4382#L1940-2 assume !false; 4383#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4665#L1266 assume !false; 5684#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4913#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4646#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5037#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5038#L1079 assume !(0 != eval_~tmp~0#1); 4999#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5000#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5604#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5489#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5490#L1296-3 assume !(0 == ~T2_E~0); 6062#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6016#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5147#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4423#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4424#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4524#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5281#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5530#L1336-3 assume !(0 == ~T10_E~0); 5531#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4851#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4831#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4776#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4777#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5338#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4127#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4128#L1376-3 assume !(0 == ~E_4~0); 5857#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5717#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5718#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5880#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5881#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4490#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4344#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4345#L1416-3 assume !(0 == ~E_12~0); 5006#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5007#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5114#L640-45 assume !(1 == ~m_pc~0); 5115#L640-47 is_master_triggered_~__retres1~0#1 := 0; 4581#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4582#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4121#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4122#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4220#L659-45 assume 1 == ~t1_pc~0; 4221#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4660#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5619#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5620#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5641#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5642#L678-45 assume 1 == ~t2_pc~0; 5585#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5120#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5121#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5273#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5898#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6015#L697-45 assume 1 == ~t3_pc~0; 5378#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5379#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5967#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5537#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5538#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5568#L716-45 assume !(1 == ~t4_pc~0); 5201#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 5200#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5750#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5205#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5206#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4868#L735-45 assume 1 == ~t5_pc~0; 4869#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5412#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5974#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5975#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6033#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6028#L754-45 assume 1 == ~t6_pc~0; 5360#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5361#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4790#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4791#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5364#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5096#L773-45 assume 1 == ~t7_pc~0; 5097#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4654#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5574#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5856#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 5102#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4772#L792-45 assume 1 == ~t8_pc~0; 4773#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5802#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4375#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4234#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4235#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4730#L811-45 assume 1 == ~t9_pc~0; 4519#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4521#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5729#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5564#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5173#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4965#L830-45 assume !(1 == ~t10_pc~0); 4162#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 4163#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5285#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4395#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4396#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4141#L849-45 assume !(1 == ~t11_pc~0); 4142#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4601#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4232#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4129#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4130#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4388#L868-45 assume 1 == ~t12_pc~0; 4389#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4328#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4329#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5667#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5918#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5919#L887-45 assume 1 == ~t13_pc~0; 5749#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4398#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5680#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 6025#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4360#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4361#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5668#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4380#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4381#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4538#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5469#L1459-3 assume !(1 == ~T5_E~0); 5470#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5921#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5860#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5861#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5922#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5154#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5155#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5791#L1499-3 assume !(1 == ~T13_E~0); 5430#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5431#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5869#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5899#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5073#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5074#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5941#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5341#L1539-3 assume !(1 == ~E_7~0); 4817#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4818#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5313#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4434#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4435#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5569#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5570#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4311#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4082#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4357#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4318#L1959 assume !(0 == start_simulation_~tmp~3#1); 4320#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4352#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4302#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5611#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5732#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5939#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5953#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5954#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 4382#L1940-2 [2022-02-21 04:23:11,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,465 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2022-02-21 04:23:11,465 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,465 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466147479] [2022-02-21 04:23:11,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,530 INFO L290 TraceCheckUtils]: 0: Hoare triple {10141#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {10141#true} is VALID [2022-02-21 04:23:11,530 INFO L290 TraceCheckUtils]: 1: Hoare triple {10141#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {10143#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:11,531 INFO L290 TraceCheckUtils]: 2: Hoare triple {10143#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10143#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:11,531 INFO L290 TraceCheckUtils]: 3: Hoare triple {10143#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10143#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:11,531 INFO L290 TraceCheckUtils]: 4: Hoare triple {10143#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,532 INFO L290 TraceCheckUtils]: 5: Hoare triple {10142#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10142#false} is VALID [2022-02-21 04:23:11,532 INFO L290 TraceCheckUtils]: 6: Hoare triple {10142#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,532 INFO L290 TraceCheckUtils]: 7: Hoare triple {10142#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,532 INFO L290 TraceCheckUtils]: 8: Hoare triple {10142#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,532 INFO L290 TraceCheckUtils]: 9: Hoare triple {10142#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,532 INFO L290 TraceCheckUtils]: 10: Hoare triple {10142#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,533 INFO L290 TraceCheckUtils]: 11: Hoare triple {10142#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,533 INFO L290 TraceCheckUtils]: 12: Hoare triple {10142#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,533 INFO L290 TraceCheckUtils]: 13: Hoare triple {10142#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {10142#false} is VALID [2022-02-21 04:23:11,533 INFO L290 TraceCheckUtils]: 14: Hoare triple {10142#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,533 INFO L290 TraceCheckUtils]: 15: Hoare triple {10142#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,533 INFO L290 TraceCheckUtils]: 16: Hoare triple {10142#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,534 INFO L290 TraceCheckUtils]: 17: Hoare triple {10142#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,534 INFO L290 TraceCheckUtils]: 18: Hoare triple {10142#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10142#false} is VALID [2022-02-21 04:23:11,534 INFO L290 TraceCheckUtils]: 19: Hoare triple {10142#false} assume 0 == ~M_E~0;~M_E~0 := 1; {10142#false} is VALID [2022-02-21 04:23:11,534 INFO L290 TraceCheckUtils]: 20: Hoare triple {10142#false} assume !(0 == ~T1_E~0); {10142#false} is VALID [2022-02-21 04:23:11,534 INFO L290 TraceCheckUtils]: 21: Hoare triple {10142#false} assume !(0 == ~T2_E~0); {10142#false} is VALID [2022-02-21 04:23:11,534 INFO L290 TraceCheckUtils]: 22: Hoare triple {10142#false} assume !(0 == ~T3_E~0); {10142#false} is VALID [2022-02-21 04:23:11,535 INFO L290 TraceCheckUtils]: 23: Hoare triple {10142#false} assume !(0 == ~T4_E~0); {10142#false} is VALID [2022-02-21 04:23:11,535 INFO L290 TraceCheckUtils]: 24: Hoare triple {10142#false} assume !(0 == ~T5_E~0); {10142#false} is VALID [2022-02-21 04:23:11,535 INFO L290 TraceCheckUtils]: 25: Hoare triple {10142#false} assume !(0 == ~T6_E~0); {10142#false} is VALID [2022-02-21 04:23:11,535 INFO L290 TraceCheckUtils]: 26: Hoare triple {10142#false} assume !(0 == ~T7_E~0); {10142#false} is VALID [2022-02-21 04:23:11,535 INFO L290 TraceCheckUtils]: 27: Hoare triple {10142#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {10142#false} is VALID [2022-02-21 04:23:11,535 INFO L290 TraceCheckUtils]: 28: Hoare triple {10142#false} assume !(0 == ~T9_E~0); {10142#false} is VALID [2022-02-21 04:23:11,536 INFO L290 TraceCheckUtils]: 29: Hoare triple {10142#false} assume !(0 == ~T10_E~0); {10142#false} is VALID [2022-02-21 04:23:11,536 INFO L290 TraceCheckUtils]: 30: Hoare triple {10142#false} assume !(0 == ~T11_E~0); {10142#false} is VALID [2022-02-21 04:23:11,536 INFO L290 TraceCheckUtils]: 31: Hoare triple {10142#false} assume !(0 == ~T12_E~0); {10142#false} is VALID [2022-02-21 04:23:11,536 INFO L290 TraceCheckUtils]: 32: Hoare triple {10142#false} assume !(0 == ~T13_E~0); {10142#false} is VALID [2022-02-21 04:23:11,536 INFO L290 TraceCheckUtils]: 33: Hoare triple {10142#false} assume !(0 == ~E_M~0); {10142#false} is VALID [2022-02-21 04:23:11,536 INFO L290 TraceCheckUtils]: 34: Hoare triple {10142#false} assume !(0 == ~E_1~0); {10142#false} is VALID [2022-02-21 04:23:11,537 INFO L290 TraceCheckUtils]: 35: Hoare triple {10142#false} assume 0 == ~E_2~0;~E_2~0 := 1; {10142#false} is VALID [2022-02-21 04:23:11,537 INFO L290 TraceCheckUtils]: 36: Hoare triple {10142#false} assume !(0 == ~E_3~0); {10142#false} is VALID [2022-02-21 04:23:11,537 INFO L290 TraceCheckUtils]: 37: Hoare triple {10142#false} assume !(0 == ~E_4~0); {10142#false} is VALID [2022-02-21 04:23:11,537 INFO L290 TraceCheckUtils]: 38: Hoare triple {10142#false} assume !(0 == ~E_5~0); {10142#false} is VALID [2022-02-21 04:23:11,537 INFO L290 TraceCheckUtils]: 39: Hoare triple {10142#false} assume !(0 == ~E_6~0); {10142#false} is VALID [2022-02-21 04:23:11,537 INFO L290 TraceCheckUtils]: 40: Hoare triple {10142#false} assume !(0 == ~E_7~0); {10142#false} is VALID [2022-02-21 04:23:11,538 INFO L290 TraceCheckUtils]: 41: Hoare triple {10142#false} assume !(0 == ~E_8~0); {10142#false} is VALID [2022-02-21 04:23:11,538 INFO L290 TraceCheckUtils]: 42: Hoare triple {10142#false} assume !(0 == ~E_9~0); {10142#false} is VALID [2022-02-21 04:23:11,538 INFO L290 TraceCheckUtils]: 43: Hoare triple {10142#false} assume 0 == ~E_10~0;~E_10~0 := 1; {10142#false} is VALID [2022-02-21 04:23:11,538 INFO L290 TraceCheckUtils]: 44: Hoare triple {10142#false} assume !(0 == ~E_11~0); {10142#false} is VALID [2022-02-21 04:23:11,538 INFO L290 TraceCheckUtils]: 45: Hoare triple {10142#false} assume !(0 == ~E_12~0); {10142#false} is VALID [2022-02-21 04:23:11,538 INFO L290 TraceCheckUtils]: 46: Hoare triple {10142#false} assume !(0 == ~E_13~0); {10142#false} is VALID [2022-02-21 04:23:11,539 INFO L290 TraceCheckUtils]: 47: Hoare triple {10142#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10142#false} is VALID [2022-02-21 04:23:11,539 INFO L290 TraceCheckUtils]: 48: Hoare triple {10142#false} assume !(1 == ~m_pc~0); {10142#false} is VALID [2022-02-21 04:23:11,539 INFO L290 TraceCheckUtils]: 49: Hoare triple {10142#false} is_master_triggered_~__retres1~0#1 := 0; {10142#false} is VALID [2022-02-21 04:23:11,539 INFO L290 TraceCheckUtils]: 50: Hoare triple {10142#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10142#false} is VALID [2022-02-21 04:23:11,539 INFO L290 TraceCheckUtils]: 51: Hoare triple {10142#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10142#false} is VALID [2022-02-21 04:23:11,539 INFO L290 TraceCheckUtils]: 52: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp~1#1); {10142#false} is VALID [2022-02-21 04:23:11,540 INFO L290 TraceCheckUtils]: 53: Hoare triple {10142#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10142#false} is VALID [2022-02-21 04:23:11,540 INFO L290 TraceCheckUtils]: 54: Hoare triple {10142#false} assume 1 == ~t1_pc~0; {10142#false} is VALID [2022-02-21 04:23:11,540 INFO L290 TraceCheckUtils]: 55: Hoare triple {10142#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10142#false} is VALID [2022-02-21 04:23:11,540 INFO L290 TraceCheckUtils]: 56: Hoare triple {10142#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10142#false} is VALID [2022-02-21 04:23:11,540 INFO L290 TraceCheckUtils]: 57: Hoare triple {10142#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10142#false} is VALID [2022-02-21 04:23:11,540 INFO L290 TraceCheckUtils]: 58: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___0~0#1); {10142#false} is VALID [2022-02-21 04:23:11,541 INFO L290 TraceCheckUtils]: 59: Hoare triple {10142#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10142#false} is VALID [2022-02-21 04:23:11,541 INFO L290 TraceCheckUtils]: 60: Hoare triple {10142#false} assume 1 == ~t2_pc~0; {10142#false} is VALID [2022-02-21 04:23:11,541 INFO L290 TraceCheckUtils]: 61: Hoare triple {10142#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10142#false} is VALID [2022-02-21 04:23:11,541 INFO L290 TraceCheckUtils]: 62: Hoare triple {10142#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10142#false} is VALID [2022-02-21 04:23:11,541 INFO L290 TraceCheckUtils]: 63: Hoare triple {10142#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {10142#false} is VALID [2022-02-21 04:23:11,541 INFO L290 TraceCheckUtils]: 64: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___1~0#1); {10142#false} is VALID [2022-02-21 04:23:11,542 INFO L290 TraceCheckUtils]: 65: Hoare triple {10142#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10142#false} is VALID [2022-02-21 04:23:11,542 INFO L290 TraceCheckUtils]: 66: Hoare triple {10142#false} assume !(1 == ~t3_pc~0); {10142#false} is VALID [2022-02-21 04:23:11,542 INFO L290 TraceCheckUtils]: 67: Hoare triple {10142#false} is_transmit3_triggered_~__retres1~3#1 := 0; {10142#false} is VALID [2022-02-21 04:23:11,542 INFO L290 TraceCheckUtils]: 68: Hoare triple {10142#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10142#false} is VALID [2022-02-21 04:23:11,542 INFO L290 TraceCheckUtils]: 69: Hoare triple {10142#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {10142#false} is VALID [2022-02-21 04:23:11,542 INFO L290 TraceCheckUtils]: 70: Hoare triple {10142#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10142#false} is VALID [2022-02-21 04:23:11,543 INFO L290 TraceCheckUtils]: 71: Hoare triple {10142#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10142#false} is VALID [2022-02-21 04:23:11,543 INFO L290 TraceCheckUtils]: 72: Hoare triple {10142#false} assume 1 == ~t4_pc~0; {10142#false} is VALID [2022-02-21 04:23:11,543 INFO L290 TraceCheckUtils]: 73: Hoare triple {10142#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10142#false} is VALID [2022-02-21 04:23:11,543 INFO L290 TraceCheckUtils]: 74: Hoare triple {10142#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10142#false} is VALID [2022-02-21 04:23:11,543 INFO L290 TraceCheckUtils]: 75: Hoare triple {10142#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {10142#false} is VALID [2022-02-21 04:23:11,543 INFO L290 TraceCheckUtils]: 76: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___3~0#1); {10142#false} is VALID [2022-02-21 04:23:11,544 INFO L290 TraceCheckUtils]: 77: Hoare triple {10142#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10142#false} is VALID [2022-02-21 04:23:11,544 INFO L290 TraceCheckUtils]: 78: Hoare triple {10142#false} assume !(1 == ~t5_pc~0); {10142#false} is VALID [2022-02-21 04:23:11,544 INFO L290 TraceCheckUtils]: 79: Hoare triple {10142#false} is_transmit5_triggered_~__retres1~5#1 := 0; {10142#false} is VALID [2022-02-21 04:23:11,544 INFO L290 TraceCheckUtils]: 80: Hoare triple {10142#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10142#false} is VALID [2022-02-21 04:23:11,544 INFO L290 TraceCheckUtils]: 81: Hoare triple {10142#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {10142#false} is VALID [2022-02-21 04:23:11,544 INFO L290 TraceCheckUtils]: 82: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___4~0#1); {10142#false} is VALID [2022-02-21 04:23:11,544 INFO L290 TraceCheckUtils]: 83: Hoare triple {10142#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10142#false} is VALID [2022-02-21 04:23:11,545 INFO L290 TraceCheckUtils]: 84: Hoare triple {10142#false} assume 1 == ~t6_pc~0; {10142#false} is VALID [2022-02-21 04:23:11,545 INFO L290 TraceCheckUtils]: 85: Hoare triple {10142#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10142#false} is VALID [2022-02-21 04:23:11,545 INFO L290 TraceCheckUtils]: 86: Hoare triple {10142#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10142#false} is VALID [2022-02-21 04:23:11,545 INFO L290 TraceCheckUtils]: 87: Hoare triple {10142#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {10142#false} is VALID [2022-02-21 04:23:11,545 INFO L290 TraceCheckUtils]: 88: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___5~0#1); {10142#false} is VALID [2022-02-21 04:23:11,545 INFO L290 TraceCheckUtils]: 89: Hoare triple {10142#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10142#false} is VALID [2022-02-21 04:23:11,546 INFO L290 TraceCheckUtils]: 90: Hoare triple {10142#false} assume !(1 == ~t7_pc~0); {10142#false} is VALID [2022-02-21 04:23:11,546 INFO L290 TraceCheckUtils]: 91: Hoare triple {10142#false} is_transmit7_triggered_~__retres1~7#1 := 0; {10142#false} is VALID [2022-02-21 04:23:11,546 INFO L290 TraceCheckUtils]: 92: Hoare triple {10142#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10142#false} is VALID [2022-02-21 04:23:11,546 INFO L290 TraceCheckUtils]: 93: Hoare triple {10142#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {10142#false} is VALID [2022-02-21 04:23:11,546 INFO L290 TraceCheckUtils]: 94: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___6~0#1); {10142#false} is VALID [2022-02-21 04:23:11,546 INFO L290 TraceCheckUtils]: 95: Hoare triple {10142#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {10142#false} is VALID [2022-02-21 04:23:11,547 INFO L290 TraceCheckUtils]: 96: Hoare triple {10142#false} assume 1 == ~t8_pc~0; {10142#false} is VALID [2022-02-21 04:23:11,547 INFO L290 TraceCheckUtils]: 97: Hoare triple {10142#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {10142#false} is VALID [2022-02-21 04:23:11,547 INFO L290 TraceCheckUtils]: 98: Hoare triple {10142#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {10142#false} is VALID [2022-02-21 04:23:11,547 INFO L290 TraceCheckUtils]: 99: Hoare triple {10142#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {10142#false} is VALID [2022-02-21 04:23:11,547 INFO L290 TraceCheckUtils]: 100: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___7~0#1); {10142#false} is VALID [2022-02-21 04:23:11,548 INFO L290 TraceCheckUtils]: 101: Hoare triple {10142#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {10142#false} is VALID [2022-02-21 04:23:11,548 INFO L290 TraceCheckUtils]: 102: Hoare triple {10142#false} assume 1 == ~t9_pc~0; {10142#false} is VALID [2022-02-21 04:23:11,548 INFO L290 TraceCheckUtils]: 103: Hoare triple {10142#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {10142#false} is VALID [2022-02-21 04:23:11,548 INFO L290 TraceCheckUtils]: 104: Hoare triple {10142#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {10142#false} is VALID [2022-02-21 04:23:11,548 INFO L290 TraceCheckUtils]: 105: Hoare triple {10142#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {10142#false} is VALID [2022-02-21 04:23:11,548 INFO L290 TraceCheckUtils]: 106: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___8~0#1); {10142#false} is VALID [2022-02-21 04:23:11,548 INFO L290 TraceCheckUtils]: 107: Hoare triple {10142#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {10142#false} is VALID [2022-02-21 04:23:11,549 INFO L290 TraceCheckUtils]: 108: Hoare triple {10142#false} assume !(1 == ~t10_pc~0); {10142#false} is VALID [2022-02-21 04:23:11,549 INFO L290 TraceCheckUtils]: 109: Hoare triple {10142#false} is_transmit10_triggered_~__retres1~10#1 := 0; {10142#false} is VALID [2022-02-21 04:23:11,549 INFO L290 TraceCheckUtils]: 110: Hoare triple {10142#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {10142#false} is VALID [2022-02-21 04:23:11,549 INFO L290 TraceCheckUtils]: 111: Hoare triple {10142#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {10142#false} is VALID [2022-02-21 04:23:11,549 INFO L290 TraceCheckUtils]: 112: Hoare triple {10142#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {10142#false} is VALID [2022-02-21 04:23:11,549 INFO L290 TraceCheckUtils]: 113: Hoare triple {10142#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {10142#false} is VALID [2022-02-21 04:23:11,550 INFO L290 TraceCheckUtils]: 114: Hoare triple {10142#false} assume 1 == ~t11_pc~0; {10142#false} is VALID [2022-02-21 04:23:11,550 INFO L290 TraceCheckUtils]: 115: Hoare triple {10142#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {10142#false} is VALID [2022-02-21 04:23:11,550 INFO L290 TraceCheckUtils]: 116: Hoare triple {10142#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {10142#false} is VALID [2022-02-21 04:23:11,550 INFO L290 TraceCheckUtils]: 117: Hoare triple {10142#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {10142#false} is VALID [2022-02-21 04:23:11,550 INFO L290 TraceCheckUtils]: 118: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___10~0#1); {10142#false} is VALID [2022-02-21 04:23:11,550 INFO L290 TraceCheckUtils]: 119: Hoare triple {10142#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {10142#false} is VALID [2022-02-21 04:23:11,551 INFO L290 TraceCheckUtils]: 120: Hoare triple {10142#false} assume !(1 == ~t12_pc~0); {10142#false} is VALID [2022-02-21 04:23:11,551 INFO L290 TraceCheckUtils]: 121: Hoare triple {10142#false} is_transmit12_triggered_~__retres1~12#1 := 0; {10142#false} is VALID [2022-02-21 04:23:11,551 INFO L290 TraceCheckUtils]: 122: Hoare triple {10142#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {10142#false} is VALID [2022-02-21 04:23:11,551 INFO L290 TraceCheckUtils]: 123: Hoare triple {10142#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {10142#false} is VALID [2022-02-21 04:23:11,551 INFO L290 TraceCheckUtils]: 124: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___11~0#1); {10142#false} is VALID [2022-02-21 04:23:11,551 INFO L290 TraceCheckUtils]: 125: Hoare triple {10142#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {10142#false} is VALID [2022-02-21 04:23:11,552 INFO L290 TraceCheckUtils]: 126: Hoare triple {10142#false} assume 1 == ~t13_pc~0; {10142#false} is VALID [2022-02-21 04:23:11,552 INFO L290 TraceCheckUtils]: 127: Hoare triple {10142#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {10142#false} is VALID [2022-02-21 04:23:11,552 INFO L290 TraceCheckUtils]: 128: Hoare triple {10142#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {10142#false} is VALID [2022-02-21 04:23:11,552 INFO L290 TraceCheckUtils]: 129: Hoare triple {10142#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {10142#false} is VALID [2022-02-21 04:23:11,552 INFO L290 TraceCheckUtils]: 130: Hoare triple {10142#false} assume !(0 != activate_threads_~tmp___12~0#1); {10142#false} is VALID [2022-02-21 04:23:11,552 INFO L290 TraceCheckUtils]: 131: Hoare triple {10142#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10142#false} is VALID [2022-02-21 04:23:11,553 INFO L290 TraceCheckUtils]: 132: Hoare triple {10142#false} assume !(1 == ~M_E~0); {10142#false} is VALID [2022-02-21 04:23:11,553 INFO L290 TraceCheckUtils]: 133: Hoare triple {10142#false} assume !(1 == ~T1_E~0); {10142#false} is VALID [2022-02-21 04:23:11,553 INFO L290 TraceCheckUtils]: 134: Hoare triple {10142#false} assume !(1 == ~T2_E~0); {10142#false} is VALID [2022-02-21 04:23:11,553 INFO L290 TraceCheckUtils]: 135: Hoare triple {10142#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,553 INFO L290 TraceCheckUtils]: 136: Hoare triple {10142#false} assume !(1 == ~T4_E~0); {10142#false} is VALID [2022-02-21 04:23:11,553 INFO L290 TraceCheckUtils]: 137: Hoare triple {10142#false} assume !(1 == ~T5_E~0); {10142#false} is VALID [2022-02-21 04:23:11,553 INFO L290 TraceCheckUtils]: 138: Hoare triple {10142#false} assume !(1 == ~T6_E~0); {10142#false} is VALID [2022-02-21 04:23:11,554 INFO L290 TraceCheckUtils]: 139: Hoare triple {10142#false} assume !(1 == ~T7_E~0); {10142#false} is VALID [2022-02-21 04:23:11,554 INFO L290 TraceCheckUtils]: 140: Hoare triple {10142#false} assume !(1 == ~T8_E~0); {10142#false} is VALID [2022-02-21 04:23:11,554 INFO L290 TraceCheckUtils]: 141: Hoare triple {10142#false} assume !(1 == ~T9_E~0); {10142#false} is VALID [2022-02-21 04:23:11,554 INFO L290 TraceCheckUtils]: 142: Hoare triple {10142#false} assume !(1 == ~T10_E~0); {10142#false} is VALID [2022-02-21 04:23:11,554 INFO L290 TraceCheckUtils]: 143: Hoare triple {10142#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,554 INFO L290 TraceCheckUtils]: 144: Hoare triple {10142#false} assume !(1 == ~T12_E~0); {10142#false} is VALID [2022-02-21 04:23:11,554 INFO L290 TraceCheckUtils]: 145: Hoare triple {10142#false} assume !(1 == ~T13_E~0); {10142#false} is VALID [2022-02-21 04:23:11,555 INFO L290 TraceCheckUtils]: 146: Hoare triple {10142#false} assume !(1 == ~E_M~0); {10142#false} is VALID [2022-02-21 04:23:11,555 INFO L290 TraceCheckUtils]: 147: Hoare triple {10142#false} assume !(1 == ~E_1~0); {10142#false} is VALID [2022-02-21 04:23:11,555 INFO L290 TraceCheckUtils]: 148: Hoare triple {10142#false} assume !(1 == ~E_2~0); {10142#false} is VALID [2022-02-21 04:23:11,555 INFO L290 TraceCheckUtils]: 149: Hoare triple {10142#false} assume !(1 == ~E_3~0); {10142#false} is VALID [2022-02-21 04:23:11,555 INFO L290 TraceCheckUtils]: 150: Hoare triple {10142#false} assume !(1 == ~E_4~0); {10142#false} is VALID [2022-02-21 04:23:11,555 INFO L290 TraceCheckUtils]: 151: Hoare triple {10142#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,556 INFO L290 TraceCheckUtils]: 152: Hoare triple {10142#false} assume !(1 == ~E_6~0); {10142#false} is VALID [2022-02-21 04:23:11,556 INFO L290 TraceCheckUtils]: 153: Hoare triple {10142#false} assume !(1 == ~E_7~0); {10142#false} is VALID [2022-02-21 04:23:11,556 INFO L290 TraceCheckUtils]: 154: Hoare triple {10142#false} assume !(1 == ~E_8~0); {10142#false} is VALID [2022-02-21 04:23:11,556 INFO L290 TraceCheckUtils]: 155: Hoare triple {10142#false} assume !(1 == ~E_9~0); {10142#false} is VALID [2022-02-21 04:23:11,556 INFO L290 TraceCheckUtils]: 156: Hoare triple {10142#false} assume !(1 == ~E_10~0); {10142#false} is VALID [2022-02-21 04:23:11,556 INFO L290 TraceCheckUtils]: 157: Hoare triple {10142#false} assume !(1 == ~E_11~0); {10142#false} is VALID [2022-02-21 04:23:11,557 INFO L290 TraceCheckUtils]: 158: Hoare triple {10142#false} assume !(1 == ~E_12~0); {10142#false} is VALID [2022-02-21 04:23:11,557 INFO L290 TraceCheckUtils]: 159: Hoare triple {10142#false} assume 1 == ~E_13~0;~E_13~0 := 2; {10142#false} is VALID [2022-02-21 04:23:11,557 INFO L290 TraceCheckUtils]: 160: Hoare triple {10142#false} assume { :end_inline_reset_delta_events } true; {10142#false} is VALID [2022-02-21 04:23:11,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,558 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,558 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466147479] [2022-02-21 04:23:11,558 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1466147479] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,558 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,559 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,559 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342007453] [2022-02-21 04:23:11,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,559 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:11,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,560 INFO L85 PathProgramCache]: Analyzing trace with hash -1800844194, now seen corresponding path program 1 times [2022-02-21 04:23:11,560 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,560 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313130603] [2022-02-21 04:23:11,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,689 INFO L290 TraceCheckUtils]: 0: Hoare triple {10144#true} assume !false; {10144#true} is VALID [2022-02-21 04:23:11,689 INFO L290 TraceCheckUtils]: 1: Hoare triple {10144#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10144#true} is VALID [2022-02-21 04:23:11,689 INFO L290 TraceCheckUtils]: 2: Hoare triple {10144#true} assume !false; {10144#true} is VALID [2022-02-21 04:23:11,689 INFO L290 TraceCheckUtils]: 3: Hoare triple {10144#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {10144#true} is VALID [2022-02-21 04:23:11,689 INFO L290 TraceCheckUtils]: 4: Hoare triple {10144#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {10144#true} is VALID [2022-02-21 04:23:11,689 INFO L290 TraceCheckUtils]: 5: Hoare triple {10144#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {10144#true} is VALID [2022-02-21 04:23:11,690 INFO L290 TraceCheckUtils]: 6: Hoare triple {10144#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {10144#true} is VALID [2022-02-21 04:23:11,690 INFO L290 TraceCheckUtils]: 7: Hoare triple {10144#true} assume !(0 != eval_~tmp~0#1); {10144#true} is VALID [2022-02-21 04:23:11,690 INFO L290 TraceCheckUtils]: 8: Hoare triple {10144#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10144#true} is VALID [2022-02-21 04:23:11,690 INFO L290 TraceCheckUtils]: 9: Hoare triple {10144#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10144#true} is VALID [2022-02-21 04:23:11,690 INFO L290 TraceCheckUtils]: 10: Hoare triple {10144#true} assume 0 == ~M_E~0;~M_E~0 := 1; {10144#true} is VALID [2022-02-21 04:23:11,690 INFO L290 TraceCheckUtils]: 11: Hoare triple {10144#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {10144#true} is VALID [2022-02-21 04:23:11,691 INFO L290 TraceCheckUtils]: 12: Hoare triple {10144#true} assume !(0 == ~T2_E~0); {10144#true} is VALID [2022-02-21 04:23:11,691 INFO L290 TraceCheckUtils]: 13: Hoare triple {10144#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10144#true} is VALID [2022-02-21 04:23:11,691 INFO L290 TraceCheckUtils]: 14: Hoare triple {10144#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10144#true} is VALID [2022-02-21 04:23:11,691 INFO L290 TraceCheckUtils]: 15: Hoare triple {10144#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,692 INFO L290 TraceCheckUtils]: 16: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,692 INFO L290 TraceCheckUtils]: 17: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,692 INFO L290 TraceCheckUtils]: 18: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,693 INFO L290 TraceCheckUtils]: 19: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,693 INFO L290 TraceCheckUtils]: 20: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,694 INFO L290 TraceCheckUtils]: 21: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,694 INFO L290 TraceCheckUtils]: 22: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,694 INFO L290 TraceCheckUtils]: 23: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,695 INFO L290 TraceCheckUtils]: 24: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,695 INFO L290 TraceCheckUtils]: 25: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,696 INFO L290 TraceCheckUtils]: 26: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,696 INFO L290 TraceCheckUtils]: 27: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,696 INFO L290 TraceCheckUtils]: 28: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,697 INFO L290 TraceCheckUtils]: 29: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,697 INFO L290 TraceCheckUtils]: 30: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,698 INFO L290 TraceCheckUtils]: 31: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,698 INFO L290 TraceCheckUtils]: 32: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,698 INFO L290 TraceCheckUtils]: 33: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,699 INFO L290 TraceCheckUtils]: 34: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,699 INFO L290 TraceCheckUtils]: 35: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,700 INFO L290 TraceCheckUtils]: 36: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,700 INFO L290 TraceCheckUtils]: 37: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,700 INFO L290 TraceCheckUtils]: 38: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,701 INFO L290 TraceCheckUtils]: 39: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,701 INFO L290 TraceCheckUtils]: 40: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,702 INFO L290 TraceCheckUtils]: 41: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,702 INFO L290 TraceCheckUtils]: 42: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,703 INFO L290 TraceCheckUtils]: 43: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,703 INFO L290 TraceCheckUtils]: 44: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,703 INFO L290 TraceCheckUtils]: 45: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,704 INFO L290 TraceCheckUtils]: 46: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,704 INFO L290 TraceCheckUtils]: 47: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,705 INFO L290 TraceCheckUtils]: 48: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,705 INFO L290 TraceCheckUtils]: 49: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,705 INFO L290 TraceCheckUtils]: 50: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,706 INFO L290 TraceCheckUtils]: 51: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,706 INFO L290 TraceCheckUtils]: 52: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,706 INFO L290 TraceCheckUtils]: 53: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,707 INFO L290 TraceCheckUtils]: 54: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,707 INFO L290 TraceCheckUtils]: 55: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,708 INFO L290 TraceCheckUtils]: 56: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,708 INFO L290 TraceCheckUtils]: 57: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,708 INFO L290 TraceCheckUtils]: 58: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,709 INFO L290 TraceCheckUtils]: 59: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,709 INFO L290 TraceCheckUtils]: 60: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,710 INFO L290 TraceCheckUtils]: 61: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,710 INFO L290 TraceCheckUtils]: 62: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,710 INFO L290 TraceCheckUtils]: 63: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,711 INFO L290 TraceCheckUtils]: 64: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,711 INFO L290 TraceCheckUtils]: 65: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,712 INFO L290 TraceCheckUtils]: 66: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,712 INFO L290 TraceCheckUtils]: 67: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,712 INFO L290 TraceCheckUtils]: 68: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,713 INFO L290 TraceCheckUtils]: 69: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,713 INFO L290 TraceCheckUtils]: 70: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,714 INFO L290 TraceCheckUtils]: 71: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,714 INFO L290 TraceCheckUtils]: 72: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,714 INFO L290 TraceCheckUtils]: 73: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,715 INFO L290 TraceCheckUtils]: 74: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,715 INFO L290 TraceCheckUtils]: 75: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,716 INFO L290 TraceCheckUtils]: 76: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,716 INFO L290 TraceCheckUtils]: 77: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,716 INFO L290 TraceCheckUtils]: 78: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,717 INFO L290 TraceCheckUtils]: 79: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,717 INFO L290 TraceCheckUtils]: 80: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,718 INFO L290 TraceCheckUtils]: 81: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,718 INFO L290 TraceCheckUtils]: 82: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,718 INFO L290 TraceCheckUtils]: 83: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,719 INFO L290 TraceCheckUtils]: 84: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,719 INFO L290 TraceCheckUtils]: 85: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,720 INFO L290 TraceCheckUtils]: 86: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,720 INFO L290 TraceCheckUtils]: 87: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,721 INFO L290 TraceCheckUtils]: 88: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,721 INFO L290 TraceCheckUtils]: 89: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,721 INFO L290 TraceCheckUtils]: 90: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,722 INFO L290 TraceCheckUtils]: 91: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,722 INFO L290 TraceCheckUtils]: 92: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,723 INFO L290 TraceCheckUtils]: 93: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,723 INFO L290 TraceCheckUtils]: 94: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,723 INFO L290 TraceCheckUtils]: 95: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,724 INFO L290 TraceCheckUtils]: 96: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,724 INFO L290 TraceCheckUtils]: 97: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,725 INFO L290 TraceCheckUtils]: 98: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,725 INFO L290 TraceCheckUtils]: 99: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,725 INFO L290 TraceCheckUtils]: 100: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,726 INFO L290 TraceCheckUtils]: 101: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,726 INFO L290 TraceCheckUtils]: 102: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,727 INFO L290 TraceCheckUtils]: 103: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,727 INFO L290 TraceCheckUtils]: 104: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,727 INFO L290 TraceCheckUtils]: 105: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,728 INFO L290 TraceCheckUtils]: 106: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,728 INFO L290 TraceCheckUtils]: 107: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,729 INFO L290 TraceCheckUtils]: 108: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,729 INFO L290 TraceCheckUtils]: 109: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,729 INFO L290 TraceCheckUtils]: 110: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,730 INFO L290 TraceCheckUtils]: 111: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,730 INFO L290 TraceCheckUtils]: 112: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,730 INFO L290 TraceCheckUtils]: 113: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,731 INFO L290 TraceCheckUtils]: 114: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,731 INFO L290 TraceCheckUtils]: 115: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,732 INFO L290 TraceCheckUtils]: 116: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,732 INFO L290 TraceCheckUtils]: 117: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,732 INFO L290 TraceCheckUtils]: 118: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,733 INFO L290 TraceCheckUtils]: 119: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,733 INFO L290 TraceCheckUtils]: 120: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,734 INFO L290 TraceCheckUtils]: 121: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,734 INFO L290 TraceCheckUtils]: 122: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,734 INFO L290 TraceCheckUtils]: 123: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,735 INFO L290 TraceCheckUtils]: 124: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,735 INFO L290 TraceCheckUtils]: 125: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,736 INFO L290 TraceCheckUtils]: 126: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,736 INFO L290 TraceCheckUtils]: 127: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:11,736 INFO L290 TraceCheckUtils]: 128: Hoare triple {10146#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {10145#false} is VALID [2022-02-21 04:23:11,737 INFO L290 TraceCheckUtils]: 129: Hoare triple {10145#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,737 INFO L290 TraceCheckUtils]: 130: Hoare triple {10145#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,737 INFO L290 TraceCheckUtils]: 131: Hoare triple {10145#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,737 INFO L290 TraceCheckUtils]: 132: Hoare triple {10145#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,737 INFO L290 TraceCheckUtils]: 133: Hoare triple {10145#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,737 INFO L290 TraceCheckUtils]: 134: Hoare triple {10145#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,737 INFO L290 TraceCheckUtils]: 135: Hoare triple {10145#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,738 INFO L290 TraceCheckUtils]: 136: Hoare triple {10145#false} assume !(1 == ~T13_E~0); {10145#false} is VALID [2022-02-21 04:23:11,738 INFO L290 TraceCheckUtils]: 137: Hoare triple {10145#false} assume 1 == ~E_M~0;~E_M~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,738 INFO L290 TraceCheckUtils]: 138: Hoare triple {10145#false} assume 1 == ~E_1~0;~E_1~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,738 INFO L290 TraceCheckUtils]: 139: Hoare triple {10145#false} assume 1 == ~E_2~0;~E_2~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,738 INFO L290 TraceCheckUtils]: 140: Hoare triple {10145#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,738 INFO L290 TraceCheckUtils]: 141: Hoare triple {10145#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,738 INFO L290 TraceCheckUtils]: 142: Hoare triple {10145#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,739 INFO L290 TraceCheckUtils]: 143: Hoare triple {10145#false} assume 1 == ~E_6~0;~E_6~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,739 INFO L290 TraceCheckUtils]: 144: Hoare triple {10145#false} assume !(1 == ~E_7~0); {10145#false} is VALID [2022-02-21 04:23:11,739 INFO L290 TraceCheckUtils]: 145: Hoare triple {10145#false} assume 1 == ~E_8~0;~E_8~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,739 INFO L290 TraceCheckUtils]: 146: Hoare triple {10145#false} assume 1 == ~E_9~0;~E_9~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,739 INFO L290 TraceCheckUtils]: 147: Hoare triple {10145#false} assume 1 == ~E_10~0;~E_10~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,739 INFO L290 TraceCheckUtils]: 148: Hoare triple {10145#false} assume 1 == ~E_11~0;~E_11~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,763 INFO L290 TraceCheckUtils]: 149: Hoare triple {10145#false} assume 1 == ~E_12~0;~E_12~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,763 INFO L290 TraceCheckUtils]: 150: Hoare triple {10145#false} assume 1 == ~E_13~0;~E_13~0 := 2; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 151: Hoare triple {10145#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 152: Hoare triple {10145#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 153: Hoare triple {10145#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 154: Hoare triple {10145#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 155: Hoare triple {10145#false} assume !(0 == start_simulation_~tmp~3#1); {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 156: Hoare triple {10145#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 157: Hoare triple {10145#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 158: Hoare triple {10145#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 159: Hoare triple {10145#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 160: Hoare triple {10145#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 161: Hoare triple {10145#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10145#false} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 162: Hoare triple {10145#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {10145#false} is VALID [2022-02-21 04:23:11,765 INFO L290 TraceCheckUtils]: 163: Hoare triple {10145#false} assume !(0 != start_simulation_~tmp___0~1#1); {10145#false} is VALID [2022-02-21 04:23:11,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,766 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,766 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1313130603] [2022-02-21 04:23:11,767 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1313130603] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,767 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,768 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,768 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127268013] [2022-02-21 04:23:11,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,768 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:11,768 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:11,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:11,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:11,769 INFO L87 Difference]: Start difference. First operand 2023 states and 2996 transitions. cyclomatic complexity: 974 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,697 INFO L93 Difference]: Finished difference Result 2023 states and 2995 transitions. [2022-02-21 04:23:13,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:13,697 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,835 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:13,836 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2995 transitions. [2022-02-21 04:23:13,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:14,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2995 transitions. [2022-02-21 04:23:14,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:14,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:14,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2995 transitions. [2022-02-21 04:23:14,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:14,132 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2022-02-21 04:23:14,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2995 transitions. [2022-02-21 04:23:14,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:14,159 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:14,165 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2995 transitions. Second operand has 2023 states, 2023 states have (on average 1.4804745427582797) internal successors, (2995), 2022 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,169 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2995 transitions. Second operand has 2023 states, 2023 states have (on average 1.4804745427582797) internal successors, (2995), 2022 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,186 INFO L87 Difference]: Start difference. First operand 2023 states and 2995 transitions. Second operand has 2023 states, 2023 states have (on average 1.4804745427582797) internal successors, (2995), 2022 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,317 INFO L93 Difference]: Finished difference Result 2023 states and 2995 transitions. [2022-02-21 04:23:14,317 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2995 transitions. [2022-02-21 04:23:14,320 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,321 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,325 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4804745427582797) internal successors, (2995), 2022 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2995 transitions. [2022-02-21 04:23:14,328 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4804745427582797) internal successors, (2995), 2022 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2995 transitions. [2022-02-21 04:23:14,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,470 INFO L93 Difference]: Finished difference Result 2023 states and 2995 transitions. [2022-02-21 04:23:14,471 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2995 transitions. [2022-02-21 04:23:14,474 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,474 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,474 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:14,474 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:14,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4804745427582797) internal successors, (2995), 2022 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2995 transitions. [2022-02-21 04:23:14,623 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2022-02-21 04:23:14,624 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2022-02-21 04:23:14,624 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:23:14,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2995 transitions. [2022-02-21 04:23:14,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:14,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:14,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:14,637 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:14,637 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:14,639 INFO L791 eck$LassoCheckResult]: Stem: 13097#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 13098#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 14096#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14097#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14182#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 13561#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13030#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 13031#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13847#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13848#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13948#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13949#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12802#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12803#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13978#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13338#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13339#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13899#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13240#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13241#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 14183#L1291-2 assume !(0 == ~T1_E~0); 14181#L1296-1 assume !(0 == ~T2_E~0); 13397#L1301-1 assume !(0 == ~T3_E~0); 13398#L1306-1 assume !(0 == ~T4_E~0); 13907#L1311-1 assume !(0 == ~T5_E~0); 12645#L1316-1 assume !(0 == ~T6_E~0); 12646#L1321-1 assume !(0 == ~T7_E~0); 13410#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12473#L1331-1 assume !(0 == ~T9_E~0); 12172#L1336-1 assume !(0 == ~T10_E~0); 12173#L1341-1 assume !(0 == ~T11_E~0); 12253#L1346-1 assume !(0 == ~T12_E~0); 12254#L1351-1 assume !(0 == ~T13_E~0); 12594#L1356-1 assume !(0 == ~E_M~0); 12595#L1361-1 assume !(0 == ~E_1~0); 14122#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12635#L1371-1 assume !(0 == ~E_3~0); 12636#L1376-1 assume !(0 == ~E_4~0); 13457#L1381-1 assume !(0 == ~E_5~0); 13458#L1386-1 assume !(0 == ~E_6~0); 14152#L1391-1 assume !(0 == ~E_7~0); 14170#L1396-1 assume !(0 == ~E_8~0); 13370#L1401-1 assume !(0 == ~E_9~0); 13371#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13649#L1411-1 assume !(0 == ~E_11~0); 13650#L1416-1 assume !(0 == ~E_12~0); 13282#L1421-1 assume !(0 == ~E_13~0); 12825#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12826#L640 assume !(1 == ~m_pc~0); 13335#L640-2 is_master_triggered_~__retres1~0#1 := 0; 13334#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13426#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13320#L1603 assume !(0 != activate_threads_~tmp~1#1); 13321#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12955#L659 assume 1 == ~t1_pc~0; 12956#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13061#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14007#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13081#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 13082#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13095#L678 assume 1 == ~t2_pc~0; 14049#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14050#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14149#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13193#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 13194#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13315#L697 assume !(1 == ~t3_pc~0); 13316#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13438#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13246#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13225#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13226#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14086#L716 assume 1 == ~t4_pc~0; 14072#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12936#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12937#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12436#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 12437#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13728#L735 assume !(1 == ~t5_pc~0); 12397#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12398#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12848#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13755#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 13391#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13392#L754 assume 1 == ~t6_pc~0; 13145#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13043#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13044#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13017#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 13018#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13838#L773 assume !(1 == ~t7_pc~0); 12598#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12597#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13427#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13399#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 13400#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13447#L792 assume 1 == ~t8_pc~0; 13620#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13952#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13441#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13394#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 13318#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13319#L811 assume 1 == ~t9_pc~0; 13523#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13989#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13865#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13519#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 13331#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13332#L830 assume !(1 == ~t10_pc~0); 13053#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12577#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12270#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12271#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12558#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13856#L849 assume 1 == ~t11_pc~0; 13857#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12373#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12374#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12963#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 13762#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13763#L868 assume !(1 == ~t12_pc~0); 13178#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 13177#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12972#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12973#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 12609#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12610#L887 assume 1 == ~t13_pc~0; 13777#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13219#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13220#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13656#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 12313#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12314#L1439 assume !(1 == ~M_E~0); 13387#L1439-2 assume !(1 == ~T1_E~0); 12485#L1444-1 assume !(1 == ~T2_E~0); 12486#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12959#L1454-1 assume !(1 == ~T4_E~0); 12960#L1459-1 assume !(1 == ~T5_E~0); 13516#L1464-1 assume !(1 == ~T6_E~0); 13517#L1469-1 assume !(1 == ~T7_E~0); 13589#L1474-1 assume !(1 == ~T8_E~0); 13283#L1479-1 assume !(1 == ~T9_E~0); 13284#L1484-1 assume !(1 == ~T10_E~0); 13520#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13166#L1494-1 assume !(1 == ~T12_E~0); 13167#L1499-1 assume !(1 == ~T13_E~0); 13359#L1504-1 assume !(1 == ~E_M~0); 13360#L1509-1 assume !(1 == ~E_1~0); 13935#L1514-1 assume !(1 == ~E_2~0); 13622#L1519-1 assume !(1 == ~E_3~0); 13623#L1524-1 assume !(1 == ~E_4~0); 14135#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14136#L1534-1 assume !(1 == ~E_6~0); 12306#L1539-1 assume !(1 == ~E_7~0); 12307#L1544-1 assume !(1 == ~E_8~0); 12721#L1549-1 assume !(1 == ~E_9~0); 14110#L1554-1 assume !(1 == ~E_10~0); 14106#L1559-1 assume !(1 == ~E_11~0); 13973#L1564-1 assume !(1 == ~E_12~0); 13974#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 14131#L1574-1 assume { :end_inline_reset_delta_events } true; 12483#L1940-2 [2022-02-21 04:23:14,640 INFO L793 eck$LassoCheckResult]: Loop: 12483#L1940-2 assume !false; 12484#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12766#L1266 assume !false; 13785#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13014#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12747#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13138#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13139#L1079 assume !(0 != eval_~tmp~0#1); 13100#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13101#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13705#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13590#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13591#L1296-3 assume !(0 == ~T2_E~0); 14163#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14117#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13248#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12524#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12525#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12625#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13382#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13631#L1336-3 assume !(0 == ~T10_E~0); 13632#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12952#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12932#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12877#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12878#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13439#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12228#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12229#L1376-3 assume !(0 == ~E_4~0); 13958#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13818#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13819#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13981#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13982#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12591#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12445#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12446#L1416-3 assume !(0 == ~E_12~0); 13107#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13108#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13215#L640-45 assume !(1 == ~m_pc~0); 13216#L640-47 is_master_triggered_~__retres1~0#1 := 0; 12682#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12683#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12222#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12223#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12321#L659-45 assume 1 == ~t1_pc~0; 12322#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12761#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13720#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13721#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13742#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13743#L678-45 assume 1 == ~t2_pc~0; 13686#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13221#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13222#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13374#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13999#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14116#L697-45 assume 1 == ~t3_pc~0; 13479#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13480#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14068#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13638#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13639#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13669#L716-45 assume 1 == ~t4_pc~0; 13300#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13301#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13851#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13306#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13307#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12969#L735-45 assume 1 == ~t5_pc~0; 12970#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13513#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14075#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14076#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14134#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14129#L754-45 assume 1 == ~t6_pc~0; 13461#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13462#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12891#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12892#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13465#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13197#L773-45 assume !(1 == ~t7_pc~0); 12754#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 12755#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13675#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13957#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 13203#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12873#L792-45 assume 1 == ~t8_pc~0; 12874#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13903#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12476#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12335#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12336#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12831#L811-45 assume 1 == ~t9_pc~0; 12620#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12622#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13830#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13665#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13274#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13066#L830-45 assume !(1 == ~t10_pc~0); 12263#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 12264#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13386#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12496#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12497#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12242#L849-45 assume !(1 == ~t11_pc~0); 12243#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 12702#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12333#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12230#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12231#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12489#L868-45 assume 1 == ~t12_pc~0; 12490#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12429#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12430#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13768#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14019#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14020#L887-45 assume !(1 == ~t13_pc~0); 12498#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 12499#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13781#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 14126#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12461#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12462#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13769#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12481#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12482#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12639#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13570#L1459-3 assume !(1 == ~T5_E~0); 13571#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14022#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13961#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13962#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14023#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13255#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13256#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13892#L1499-3 assume !(1 == ~T13_E~0); 13531#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13532#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13970#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14000#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13174#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13175#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14042#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13442#L1539-3 assume !(1 == ~E_7~0); 12918#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12919#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13414#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12535#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12536#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13670#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13671#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12412#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12183#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12458#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12419#L1959 assume !(0 == start_simulation_~tmp~3#1); 12421#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12453#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12403#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13712#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13833#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14040#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14054#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14055#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 12483#L1940-2 [2022-02-21 04:23:14,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:14,641 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2022-02-21 04:23:14,641 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:14,641 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84100051] [2022-02-21 04:23:14,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:14,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:14,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:14,709 INFO L290 TraceCheckUtils]: 0: Hoare triple {18242#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {18242#true} is VALID [2022-02-21 04:23:14,711 INFO L290 TraceCheckUtils]: 1: Hoare triple {18242#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {18244#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:14,711 INFO L290 TraceCheckUtils]: 2: Hoare triple {18244#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {18244#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:14,712 INFO L290 TraceCheckUtils]: 3: Hoare triple {18244#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {18244#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:14,712 INFO L290 TraceCheckUtils]: 4: Hoare triple {18244#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {18244#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:14,712 INFO L290 TraceCheckUtils]: 5: Hoare triple {18244#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {18244#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:14,713 INFO L290 TraceCheckUtils]: 6: Hoare triple {18244#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,713 INFO L290 TraceCheckUtils]: 7: Hoare triple {18243#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,713 INFO L290 TraceCheckUtils]: 8: Hoare triple {18243#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,713 INFO L290 TraceCheckUtils]: 9: Hoare triple {18243#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,713 INFO L290 TraceCheckUtils]: 10: Hoare triple {18243#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,714 INFO L290 TraceCheckUtils]: 11: Hoare triple {18243#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,714 INFO L290 TraceCheckUtils]: 12: Hoare triple {18243#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,714 INFO L290 TraceCheckUtils]: 13: Hoare triple {18243#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {18243#false} is VALID [2022-02-21 04:23:14,714 INFO L290 TraceCheckUtils]: 14: Hoare triple {18243#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,714 INFO L290 TraceCheckUtils]: 15: Hoare triple {18243#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,714 INFO L290 TraceCheckUtils]: 16: Hoare triple {18243#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,714 INFO L290 TraceCheckUtils]: 17: Hoare triple {18243#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,715 INFO L290 TraceCheckUtils]: 18: Hoare triple {18243#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {18243#false} is VALID [2022-02-21 04:23:14,715 INFO L290 TraceCheckUtils]: 19: Hoare triple {18243#false} assume 0 == ~M_E~0;~M_E~0 := 1; {18243#false} is VALID [2022-02-21 04:23:14,715 INFO L290 TraceCheckUtils]: 20: Hoare triple {18243#false} assume !(0 == ~T1_E~0); {18243#false} is VALID [2022-02-21 04:23:14,715 INFO L290 TraceCheckUtils]: 21: Hoare triple {18243#false} assume !(0 == ~T2_E~0); {18243#false} is VALID [2022-02-21 04:23:14,715 INFO L290 TraceCheckUtils]: 22: Hoare triple {18243#false} assume !(0 == ~T3_E~0); {18243#false} is VALID [2022-02-21 04:23:14,715 INFO L290 TraceCheckUtils]: 23: Hoare triple {18243#false} assume !(0 == ~T4_E~0); {18243#false} is VALID [2022-02-21 04:23:14,716 INFO L290 TraceCheckUtils]: 24: Hoare triple {18243#false} assume !(0 == ~T5_E~0); {18243#false} is VALID [2022-02-21 04:23:14,716 INFO L290 TraceCheckUtils]: 25: Hoare triple {18243#false} assume !(0 == ~T6_E~0); {18243#false} is VALID [2022-02-21 04:23:14,716 INFO L290 TraceCheckUtils]: 26: Hoare triple {18243#false} assume !(0 == ~T7_E~0); {18243#false} is VALID [2022-02-21 04:23:14,716 INFO L290 TraceCheckUtils]: 27: Hoare triple {18243#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {18243#false} is VALID [2022-02-21 04:23:14,716 INFO L290 TraceCheckUtils]: 28: Hoare triple {18243#false} assume !(0 == ~T9_E~0); {18243#false} is VALID [2022-02-21 04:23:14,716 INFO L290 TraceCheckUtils]: 29: Hoare triple {18243#false} assume !(0 == ~T10_E~0); {18243#false} is VALID [2022-02-21 04:23:14,716 INFO L290 TraceCheckUtils]: 30: Hoare triple {18243#false} assume !(0 == ~T11_E~0); {18243#false} is VALID [2022-02-21 04:23:14,717 INFO L290 TraceCheckUtils]: 31: Hoare triple {18243#false} assume !(0 == ~T12_E~0); {18243#false} is VALID [2022-02-21 04:23:14,717 INFO L290 TraceCheckUtils]: 32: Hoare triple {18243#false} assume !(0 == ~T13_E~0); {18243#false} is VALID [2022-02-21 04:23:14,717 INFO L290 TraceCheckUtils]: 33: Hoare triple {18243#false} assume !(0 == ~E_M~0); {18243#false} is VALID [2022-02-21 04:23:14,717 INFO L290 TraceCheckUtils]: 34: Hoare triple {18243#false} assume !(0 == ~E_1~0); {18243#false} is VALID [2022-02-21 04:23:14,717 INFO L290 TraceCheckUtils]: 35: Hoare triple {18243#false} assume 0 == ~E_2~0;~E_2~0 := 1; {18243#false} is VALID [2022-02-21 04:23:14,717 INFO L290 TraceCheckUtils]: 36: Hoare triple {18243#false} assume !(0 == ~E_3~0); {18243#false} is VALID [2022-02-21 04:23:14,720 INFO L290 TraceCheckUtils]: 37: Hoare triple {18243#false} assume !(0 == ~E_4~0); {18243#false} is VALID [2022-02-21 04:23:14,721 INFO L290 TraceCheckUtils]: 38: Hoare triple {18243#false} assume !(0 == ~E_5~0); {18243#false} is VALID [2022-02-21 04:23:14,721 INFO L290 TraceCheckUtils]: 39: Hoare triple {18243#false} assume !(0 == ~E_6~0); {18243#false} is VALID [2022-02-21 04:23:14,721 INFO L290 TraceCheckUtils]: 40: Hoare triple {18243#false} assume !(0 == ~E_7~0); {18243#false} is VALID [2022-02-21 04:23:14,721 INFO L290 TraceCheckUtils]: 41: Hoare triple {18243#false} assume !(0 == ~E_8~0); {18243#false} is VALID [2022-02-21 04:23:14,721 INFO L290 TraceCheckUtils]: 42: Hoare triple {18243#false} assume !(0 == ~E_9~0); {18243#false} is VALID [2022-02-21 04:23:14,721 INFO L290 TraceCheckUtils]: 43: Hoare triple {18243#false} assume 0 == ~E_10~0;~E_10~0 := 1; {18243#false} is VALID [2022-02-21 04:23:14,722 INFO L290 TraceCheckUtils]: 44: Hoare triple {18243#false} assume !(0 == ~E_11~0); {18243#false} is VALID [2022-02-21 04:23:14,722 INFO L290 TraceCheckUtils]: 45: Hoare triple {18243#false} assume !(0 == ~E_12~0); {18243#false} is VALID [2022-02-21 04:23:14,722 INFO L290 TraceCheckUtils]: 46: Hoare triple {18243#false} assume !(0 == ~E_13~0); {18243#false} is VALID [2022-02-21 04:23:14,722 INFO L290 TraceCheckUtils]: 47: Hoare triple {18243#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18243#false} is VALID [2022-02-21 04:23:14,722 INFO L290 TraceCheckUtils]: 48: Hoare triple {18243#false} assume !(1 == ~m_pc~0); {18243#false} is VALID [2022-02-21 04:23:14,722 INFO L290 TraceCheckUtils]: 49: Hoare triple {18243#false} is_master_triggered_~__retres1~0#1 := 0; {18243#false} is VALID [2022-02-21 04:23:14,723 INFO L290 TraceCheckUtils]: 50: Hoare triple {18243#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18243#false} is VALID [2022-02-21 04:23:14,723 INFO L290 TraceCheckUtils]: 51: Hoare triple {18243#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {18243#false} is VALID [2022-02-21 04:23:14,723 INFO L290 TraceCheckUtils]: 52: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp~1#1); {18243#false} is VALID [2022-02-21 04:23:14,723 INFO L290 TraceCheckUtils]: 53: Hoare triple {18243#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18243#false} is VALID [2022-02-21 04:23:14,723 INFO L290 TraceCheckUtils]: 54: Hoare triple {18243#false} assume 1 == ~t1_pc~0; {18243#false} is VALID [2022-02-21 04:23:14,723 INFO L290 TraceCheckUtils]: 55: Hoare triple {18243#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {18243#false} is VALID [2022-02-21 04:23:14,723 INFO L290 TraceCheckUtils]: 56: Hoare triple {18243#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18243#false} is VALID [2022-02-21 04:23:14,724 INFO L290 TraceCheckUtils]: 57: Hoare triple {18243#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {18243#false} is VALID [2022-02-21 04:23:14,724 INFO L290 TraceCheckUtils]: 58: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___0~0#1); {18243#false} is VALID [2022-02-21 04:23:14,724 INFO L290 TraceCheckUtils]: 59: Hoare triple {18243#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18243#false} is VALID [2022-02-21 04:23:14,724 INFO L290 TraceCheckUtils]: 60: Hoare triple {18243#false} assume 1 == ~t2_pc~0; {18243#false} is VALID [2022-02-21 04:23:14,724 INFO L290 TraceCheckUtils]: 61: Hoare triple {18243#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {18243#false} is VALID [2022-02-21 04:23:14,724 INFO L290 TraceCheckUtils]: 62: Hoare triple {18243#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18243#false} is VALID [2022-02-21 04:23:14,739 INFO L290 TraceCheckUtils]: 63: Hoare triple {18243#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {18243#false} is VALID [2022-02-21 04:23:14,751 INFO L290 TraceCheckUtils]: 64: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___1~0#1); {18243#false} is VALID [2022-02-21 04:23:14,752 INFO L290 TraceCheckUtils]: 65: Hoare triple {18243#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18243#false} is VALID [2022-02-21 04:23:14,752 INFO L290 TraceCheckUtils]: 66: Hoare triple {18243#false} assume !(1 == ~t3_pc~0); {18243#false} is VALID [2022-02-21 04:23:14,752 INFO L290 TraceCheckUtils]: 67: Hoare triple {18243#false} is_transmit3_triggered_~__retres1~3#1 := 0; {18243#false} is VALID [2022-02-21 04:23:14,752 INFO L290 TraceCheckUtils]: 68: Hoare triple {18243#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18243#false} is VALID [2022-02-21 04:23:14,752 INFO L290 TraceCheckUtils]: 69: Hoare triple {18243#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {18243#false} is VALID [2022-02-21 04:23:14,753 INFO L290 TraceCheckUtils]: 70: Hoare triple {18243#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {18243#false} is VALID [2022-02-21 04:23:14,753 INFO L290 TraceCheckUtils]: 71: Hoare triple {18243#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {18243#false} is VALID [2022-02-21 04:23:14,753 INFO L290 TraceCheckUtils]: 72: Hoare triple {18243#false} assume 1 == ~t4_pc~0; {18243#false} is VALID [2022-02-21 04:23:14,753 INFO L290 TraceCheckUtils]: 73: Hoare triple {18243#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {18243#false} is VALID [2022-02-21 04:23:14,753 INFO L290 TraceCheckUtils]: 74: Hoare triple {18243#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {18243#false} is VALID [2022-02-21 04:23:14,753 INFO L290 TraceCheckUtils]: 75: Hoare triple {18243#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {18243#false} is VALID [2022-02-21 04:23:14,754 INFO L290 TraceCheckUtils]: 76: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___3~0#1); {18243#false} is VALID [2022-02-21 04:23:14,754 INFO L290 TraceCheckUtils]: 77: Hoare triple {18243#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {18243#false} is VALID [2022-02-21 04:23:14,754 INFO L290 TraceCheckUtils]: 78: Hoare triple {18243#false} assume !(1 == ~t5_pc~0); {18243#false} is VALID [2022-02-21 04:23:14,754 INFO L290 TraceCheckUtils]: 79: Hoare triple {18243#false} is_transmit5_triggered_~__retres1~5#1 := 0; {18243#false} is VALID [2022-02-21 04:23:14,754 INFO L290 TraceCheckUtils]: 80: Hoare triple {18243#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {18243#false} is VALID [2022-02-21 04:23:14,754 INFO L290 TraceCheckUtils]: 81: Hoare triple {18243#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {18243#false} is VALID [2022-02-21 04:23:14,754 INFO L290 TraceCheckUtils]: 82: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___4~0#1); {18243#false} is VALID [2022-02-21 04:23:14,755 INFO L290 TraceCheckUtils]: 83: Hoare triple {18243#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {18243#false} is VALID [2022-02-21 04:23:14,755 INFO L290 TraceCheckUtils]: 84: Hoare triple {18243#false} assume 1 == ~t6_pc~0; {18243#false} is VALID [2022-02-21 04:23:14,755 INFO L290 TraceCheckUtils]: 85: Hoare triple {18243#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {18243#false} is VALID [2022-02-21 04:23:14,755 INFO L290 TraceCheckUtils]: 86: Hoare triple {18243#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {18243#false} is VALID [2022-02-21 04:23:14,755 INFO L290 TraceCheckUtils]: 87: Hoare triple {18243#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {18243#false} is VALID [2022-02-21 04:23:14,755 INFO L290 TraceCheckUtils]: 88: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___5~0#1); {18243#false} is VALID [2022-02-21 04:23:14,756 INFO L290 TraceCheckUtils]: 89: Hoare triple {18243#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {18243#false} is VALID [2022-02-21 04:23:14,756 INFO L290 TraceCheckUtils]: 90: Hoare triple {18243#false} assume !(1 == ~t7_pc~0); {18243#false} is VALID [2022-02-21 04:23:14,756 INFO L290 TraceCheckUtils]: 91: Hoare triple {18243#false} is_transmit7_triggered_~__retres1~7#1 := 0; {18243#false} is VALID [2022-02-21 04:23:14,756 INFO L290 TraceCheckUtils]: 92: Hoare triple {18243#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {18243#false} is VALID [2022-02-21 04:23:14,756 INFO L290 TraceCheckUtils]: 93: Hoare triple {18243#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {18243#false} is VALID [2022-02-21 04:23:14,756 INFO L290 TraceCheckUtils]: 94: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___6~0#1); {18243#false} is VALID [2022-02-21 04:23:14,756 INFO L290 TraceCheckUtils]: 95: Hoare triple {18243#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {18243#false} is VALID [2022-02-21 04:23:14,757 INFO L290 TraceCheckUtils]: 96: Hoare triple {18243#false} assume 1 == ~t8_pc~0; {18243#false} is VALID [2022-02-21 04:23:14,757 INFO L290 TraceCheckUtils]: 97: Hoare triple {18243#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {18243#false} is VALID [2022-02-21 04:23:14,757 INFO L290 TraceCheckUtils]: 98: Hoare triple {18243#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {18243#false} is VALID [2022-02-21 04:23:14,757 INFO L290 TraceCheckUtils]: 99: Hoare triple {18243#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {18243#false} is VALID [2022-02-21 04:23:14,757 INFO L290 TraceCheckUtils]: 100: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___7~0#1); {18243#false} is VALID [2022-02-21 04:23:14,757 INFO L290 TraceCheckUtils]: 101: Hoare triple {18243#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {18243#false} is VALID [2022-02-21 04:23:14,758 INFO L290 TraceCheckUtils]: 102: Hoare triple {18243#false} assume 1 == ~t9_pc~0; {18243#false} is VALID [2022-02-21 04:23:14,758 INFO L290 TraceCheckUtils]: 103: Hoare triple {18243#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {18243#false} is VALID [2022-02-21 04:23:14,758 INFO L290 TraceCheckUtils]: 104: Hoare triple {18243#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {18243#false} is VALID [2022-02-21 04:23:14,758 INFO L290 TraceCheckUtils]: 105: Hoare triple {18243#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {18243#false} is VALID [2022-02-21 04:23:14,758 INFO L290 TraceCheckUtils]: 106: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___8~0#1); {18243#false} is VALID [2022-02-21 04:23:14,758 INFO L290 TraceCheckUtils]: 107: Hoare triple {18243#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {18243#false} is VALID [2022-02-21 04:23:14,758 INFO L290 TraceCheckUtils]: 108: Hoare triple {18243#false} assume !(1 == ~t10_pc~0); {18243#false} is VALID [2022-02-21 04:23:14,759 INFO L290 TraceCheckUtils]: 109: Hoare triple {18243#false} is_transmit10_triggered_~__retres1~10#1 := 0; {18243#false} is VALID [2022-02-21 04:23:14,759 INFO L290 TraceCheckUtils]: 110: Hoare triple {18243#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {18243#false} is VALID [2022-02-21 04:23:14,759 INFO L290 TraceCheckUtils]: 111: Hoare triple {18243#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {18243#false} is VALID [2022-02-21 04:23:14,759 INFO L290 TraceCheckUtils]: 112: Hoare triple {18243#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {18243#false} is VALID [2022-02-21 04:23:14,759 INFO L290 TraceCheckUtils]: 113: Hoare triple {18243#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {18243#false} is VALID [2022-02-21 04:23:14,759 INFO L290 TraceCheckUtils]: 114: Hoare triple {18243#false} assume 1 == ~t11_pc~0; {18243#false} is VALID [2022-02-21 04:23:14,759 INFO L290 TraceCheckUtils]: 115: Hoare triple {18243#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {18243#false} is VALID [2022-02-21 04:23:14,760 INFO L290 TraceCheckUtils]: 116: Hoare triple {18243#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {18243#false} is VALID [2022-02-21 04:23:14,760 INFO L290 TraceCheckUtils]: 117: Hoare triple {18243#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {18243#false} is VALID [2022-02-21 04:23:14,760 INFO L290 TraceCheckUtils]: 118: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___10~0#1); {18243#false} is VALID [2022-02-21 04:23:14,760 INFO L290 TraceCheckUtils]: 119: Hoare triple {18243#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {18243#false} is VALID [2022-02-21 04:23:14,760 INFO L290 TraceCheckUtils]: 120: Hoare triple {18243#false} assume !(1 == ~t12_pc~0); {18243#false} is VALID [2022-02-21 04:23:14,760 INFO L290 TraceCheckUtils]: 121: Hoare triple {18243#false} is_transmit12_triggered_~__retres1~12#1 := 0; {18243#false} is VALID [2022-02-21 04:23:14,761 INFO L290 TraceCheckUtils]: 122: Hoare triple {18243#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {18243#false} is VALID [2022-02-21 04:23:14,761 INFO L290 TraceCheckUtils]: 123: Hoare triple {18243#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {18243#false} is VALID [2022-02-21 04:23:14,761 INFO L290 TraceCheckUtils]: 124: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___11~0#1); {18243#false} is VALID [2022-02-21 04:23:14,761 INFO L290 TraceCheckUtils]: 125: Hoare triple {18243#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {18243#false} is VALID [2022-02-21 04:23:14,761 INFO L290 TraceCheckUtils]: 126: Hoare triple {18243#false} assume 1 == ~t13_pc~0; {18243#false} is VALID [2022-02-21 04:23:14,761 INFO L290 TraceCheckUtils]: 127: Hoare triple {18243#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {18243#false} is VALID [2022-02-21 04:23:14,761 INFO L290 TraceCheckUtils]: 128: Hoare triple {18243#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {18243#false} is VALID [2022-02-21 04:23:14,762 INFO L290 TraceCheckUtils]: 129: Hoare triple {18243#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {18243#false} is VALID [2022-02-21 04:23:14,762 INFO L290 TraceCheckUtils]: 130: Hoare triple {18243#false} assume !(0 != activate_threads_~tmp___12~0#1); {18243#false} is VALID [2022-02-21 04:23:14,762 INFO L290 TraceCheckUtils]: 131: Hoare triple {18243#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18243#false} is VALID [2022-02-21 04:23:14,762 INFO L290 TraceCheckUtils]: 132: Hoare triple {18243#false} assume !(1 == ~M_E~0); {18243#false} is VALID [2022-02-21 04:23:14,762 INFO L290 TraceCheckUtils]: 133: Hoare triple {18243#false} assume !(1 == ~T1_E~0); {18243#false} is VALID [2022-02-21 04:23:14,762 INFO L290 TraceCheckUtils]: 134: Hoare triple {18243#false} assume !(1 == ~T2_E~0); {18243#false} is VALID [2022-02-21 04:23:14,762 INFO L290 TraceCheckUtils]: 135: Hoare triple {18243#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,763 INFO L290 TraceCheckUtils]: 136: Hoare triple {18243#false} assume !(1 == ~T4_E~0); {18243#false} is VALID [2022-02-21 04:23:14,763 INFO L290 TraceCheckUtils]: 137: Hoare triple {18243#false} assume !(1 == ~T5_E~0); {18243#false} is VALID [2022-02-21 04:23:14,763 INFO L290 TraceCheckUtils]: 138: Hoare triple {18243#false} assume !(1 == ~T6_E~0); {18243#false} is VALID [2022-02-21 04:23:14,763 INFO L290 TraceCheckUtils]: 139: Hoare triple {18243#false} assume !(1 == ~T7_E~0); {18243#false} is VALID [2022-02-21 04:23:14,763 INFO L290 TraceCheckUtils]: 140: Hoare triple {18243#false} assume !(1 == ~T8_E~0); {18243#false} is VALID [2022-02-21 04:23:14,763 INFO L290 TraceCheckUtils]: 141: Hoare triple {18243#false} assume !(1 == ~T9_E~0); {18243#false} is VALID [2022-02-21 04:23:14,764 INFO L290 TraceCheckUtils]: 142: Hoare triple {18243#false} assume !(1 == ~T10_E~0); {18243#false} is VALID [2022-02-21 04:23:14,764 INFO L290 TraceCheckUtils]: 143: Hoare triple {18243#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,764 INFO L290 TraceCheckUtils]: 144: Hoare triple {18243#false} assume !(1 == ~T12_E~0); {18243#false} is VALID [2022-02-21 04:23:14,764 INFO L290 TraceCheckUtils]: 145: Hoare triple {18243#false} assume !(1 == ~T13_E~0); {18243#false} is VALID [2022-02-21 04:23:14,764 INFO L290 TraceCheckUtils]: 146: Hoare triple {18243#false} assume !(1 == ~E_M~0); {18243#false} is VALID [2022-02-21 04:23:14,764 INFO L290 TraceCheckUtils]: 147: Hoare triple {18243#false} assume !(1 == ~E_1~0); {18243#false} is VALID [2022-02-21 04:23:14,764 INFO L290 TraceCheckUtils]: 148: Hoare triple {18243#false} assume !(1 == ~E_2~0); {18243#false} is VALID [2022-02-21 04:23:14,765 INFO L290 TraceCheckUtils]: 149: Hoare triple {18243#false} assume !(1 == ~E_3~0); {18243#false} is VALID [2022-02-21 04:23:14,765 INFO L290 TraceCheckUtils]: 150: Hoare triple {18243#false} assume !(1 == ~E_4~0); {18243#false} is VALID [2022-02-21 04:23:14,765 INFO L290 TraceCheckUtils]: 151: Hoare triple {18243#false} assume 1 == ~E_5~0;~E_5~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,765 INFO L290 TraceCheckUtils]: 152: Hoare triple {18243#false} assume !(1 == ~E_6~0); {18243#false} is VALID [2022-02-21 04:23:14,765 INFO L290 TraceCheckUtils]: 153: Hoare triple {18243#false} assume !(1 == ~E_7~0); {18243#false} is VALID [2022-02-21 04:23:14,765 INFO L290 TraceCheckUtils]: 154: Hoare triple {18243#false} assume !(1 == ~E_8~0); {18243#false} is VALID [2022-02-21 04:23:14,765 INFO L290 TraceCheckUtils]: 155: Hoare triple {18243#false} assume !(1 == ~E_9~0); {18243#false} is VALID [2022-02-21 04:23:14,765 INFO L290 TraceCheckUtils]: 156: Hoare triple {18243#false} assume !(1 == ~E_10~0); {18243#false} is VALID [2022-02-21 04:23:14,766 INFO L290 TraceCheckUtils]: 157: Hoare triple {18243#false} assume !(1 == ~E_11~0); {18243#false} is VALID [2022-02-21 04:23:14,766 INFO L290 TraceCheckUtils]: 158: Hoare triple {18243#false} assume !(1 == ~E_12~0); {18243#false} is VALID [2022-02-21 04:23:14,766 INFO L290 TraceCheckUtils]: 159: Hoare triple {18243#false} assume 1 == ~E_13~0;~E_13~0 := 2; {18243#false} is VALID [2022-02-21 04:23:14,766 INFO L290 TraceCheckUtils]: 160: Hoare triple {18243#false} assume { :end_inline_reset_delta_events } true; {18243#false} is VALID [2022-02-21 04:23:14,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:14,767 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:14,767 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84100051] [2022-02-21 04:23:14,767 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [84100051] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:14,767 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:14,768 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:14,768 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1878603417] [2022-02-21 04:23:14,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:14,768 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:14,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:14,769 INFO L85 PathProgramCache]: Analyzing trace with hash 230524959, now seen corresponding path program 1 times [2022-02-21 04:23:14,769 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:14,769 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143348832] [2022-02-21 04:23:14,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:14,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:14,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:14,849 INFO L290 TraceCheckUtils]: 0: Hoare triple {18245#true} assume !false; {18245#true} is VALID [2022-02-21 04:23:14,850 INFO L290 TraceCheckUtils]: 1: Hoare triple {18245#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {18245#true} is VALID [2022-02-21 04:23:14,850 INFO L290 TraceCheckUtils]: 2: Hoare triple {18245#true} assume !false; {18245#true} is VALID [2022-02-21 04:23:14,850 INFO L290 TraceCheckUtils]: 3: Hoare triple {18245#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {18245#true} is VALID [2022-02-21 04:23:14,850 INFO L290 TraceCheckUtils]: 4: Hoare triple {18245#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {18245#true} is VALID [2022-02-21 04:23:14,850 INFO L290 TraceCheckUtils]: 5: Hoare triple {18245#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {18245#true} is VALID [2022-02-21 04:23:14,850 INFO L290 TraceCheckUtils]: 6: Hoare triple {18245#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {18245#true} is VALID [2022-02-21 04:23:14,851 INFO L290 TraceCheckUtils]: 7: Hoare triple {18245#true} assume !(0 != eval_~tmp~0#1); {18245#true} is VALID [2022-02-21 04:23:14,851 INFO L290 TraceCheckUtils]: 8: Hoare triple {18245#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {18245#true} is VALID [2022-02-21 04:23:14,851 INFO L290 TraceCheckUtils]: 9: Hoare triple {18245#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {18245#true} is VALID [2022-02-21 04:23:14,851 INFO L290 TraceCheckUtils]: 10: Hoare triple {18245#true} assume 0 == ~M_E~0;~M_E~0 := 1; {18245#true} is VALID [2022-02-21 04:23:14,851 INFO L290 TraceCheckUtils]: 11: Hoare triple {18245#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {18245#true} is VALID [2022-02-21 04:23:14,856 INFO L290 TraceCheckUtils]: 12: Hoare triple {18245#true} assume !(0 == ~T2_E~0); {18245#true} is VALID [2022-02-21 04:23:14,856 INFO L290 TraceCheckUtils]: 13: Hoare triple {18245#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {18245#true} is VALID [2022-02-21 04:23:14,856 INFO L290 TraceCheckUtils]: 14: Hoare triple {18245#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {18245#true} is VALID [2022-02-21 04:23:14,857 INFO L290 TraceCheckUtils]: 15: Hoare triple {18245#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,857 INFO L290 TraceCheckUtils]: 16: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,858 INFO L290 TraceCheckUtils]: 17: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,858 INFO L290 TraceCheckUtils]: 18: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,859 INFO L290 TraceCheckUtils]: 19: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,859 INFO L290 TraceCheckUtils]: 20: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,859 INFO L290 TraceCheckUtils]: 21: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,861 INFO L290 TraceCheckUtils]: 22: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,861 INFO L290 TraceCheckUtils]: 23: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,862 INFO L290 TraceCheckUtils]: 24: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,862 INFO L290 TraceCheckUtils]: 25: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,862 INFO L290 TraceCheckUtils]: 26: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,863 INFO L290 TraceCheckUtils]: 27: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,863 INFO L290 TraceCheckUtils]: 28: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,864 INFO L290 TraceCheckUtils]: 29: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,864 INFO L290 TraceCheckUtils]: 30: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,865 INFO L290 TraceCheckUtils]: 31: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,865 INFO L290 TraceCheckUtils]: 32: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,866 INFO L290 TraceCheckUtils]: 33: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,866 INFO L290 TraceCheckUtils]: 34: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,866 INFO L290 TraceCheckUtils]: 35: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,867 INFO L290 TraceCheckUtils]: 36: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,867 INFO L290 TraceCheckUtils]: 37: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,868 INFO L290 TraceCheckUtils]: 38: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,868 INFO L290 TraceCheckUtils]: 39: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,868 INFO L290 TraceCheckUtils]: 40: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,869 INFO L290 TraceCheckUtils]: 41: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,869 INFO L290 TraceCheckUtils]: 42: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,870 INFO L290 TraceCheckUtils]: 43: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,870 INFO L290 TraceCheckUtils]: 44: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,870 INFO L290 TraceCheckUtils]: 45: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,871 INFO L290 TraceCheckUtils]: 46: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,871 INFO L290 TraceCheckUtils]: 47: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,872 INFO L290 TraceCheckUtils]: 48: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,872 INFO L290 TraceCheckUtils]: 49: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,872 INFO L290 TraceCheckUtils]: 50: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,873 INFO L290 TraceCheckUtils]: 51: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,873 INFO L290 TraceCheckUtils]: 52: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,874 INFO L290 TraceCheckUtils]: 53: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,874 INFO L290 TraceCheckUtils]: 54: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,874 INFO L290 TraceCheckUtils]: 55: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,875 INFO L290 TraceCheckUtils]: 56: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,875 INFO L290 TraceCheckUtils]: 57: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,876 INFO L290 TraceCheckUtils]: 58: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,876 INFO L290 TraceCheckUtils]: 59: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,877 INFO L290 TraceCheckUtils]: 60: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,877 INFO L290 TraceCheckUtils]: 61: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,877 INFO L290 TraceCheckUtils]: 62: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,878 INFO L290 TraceCheckUtils]: 63: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,878 INFO L290 TraceCheckUtils]: 64: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,879 INFO L290 TraceCheckUtils]: 65: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,879 INFO L290 TraceCheckUtils]: 66: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,879 INFO L290 TraceCheckUtils]: 67: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,880 INFO L290 TraceCheckUtils]: 68: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,880 INFO L290 TraceCheckUtils]: 69: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,881 INFO L290 TraceCheckUtils]: 70: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,881 INFO L290 TraceCheckUtils]: 71: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,881 INFO L290 TraceCheckUtils]: 72: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,882 INFO L290 TraceCheckUtils]: 73: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,882 INFO L290 TraceCheckUtils]: 74: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,883 INFO L290 TraceCheckUtils]: 75: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,883 INFO L290 TraceCheckUtils]: 76: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,883 INFO L290 TraceCheckUtils]: 77: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,884 INFO L290 TraceCheckUtils]: 78: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,884 INFO L290 TraceCheckUtils]: 79: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,885 INFO L290 TraceCheckUtils]: 80: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,885 INFO L290 TraceCheckUtils]: 81: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,885 INFO L290 TraceCheckUtils]: 82: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,886 INFO L290 TraceCheckUtils]: 83: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,886 INFO L290 TraceCheckUtils]: 84: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,887 INFO L290 TraceCheckUtils]: 85: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,887 INFO L290 TraceCheckUtils]: 86: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,888 INFO L290 TraceCheckUtils]: 87: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,888 INFO L290 TraceCheckUtils]: 88: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,888 INFO L290 TraceCheckUtils]: 89: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,889 INFO L290 TraceCheckUtils]: 90: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,889 INFO L290 TraceCheckUtils]: 91: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,890 INFO L290 TraceCheckUtils]: 92: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,890 INFO L290 TraceCheckUtils]: 93: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,890 INFO L290 TraceCheckUtils]: 94: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,891 INFO L290 TraceCheckUtils]: 95: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,891 INFO L290 TraceCheckUtils]: 96: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,892 INFO L290 TraceCheckUtils]: 97: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,892 INFO L290 TraceCheckUtils]: 98: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,892 INFO L290 TraceCheckUtils]: 99: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,893 INFO L290 TraceCheckUtils]: 100: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,893 INFO L290 TraceCheckUtils]: 101: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,894 INFO L290 TraceCheckUtils]: 102: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,894 INFO L290 TraceCheckUtils]: 103: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,894 INFO L290 TraceCheckUtils]: 104: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,895 INFO L290 TraceCheckUtils]: 105: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,895 INFO L290 TraceCheckUtils]: 106: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,896 INFO L290 TraceCheckUtils]: 107: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,896 INFO L290 TraceCheckUtils]: 108: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,897 INFO L290 TraceCheckUtils]: 109: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,897 INFO L290 TraceCheckUtils]: 110: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,897 INFO L290 TraceCheckUtils]: 111: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,898 INFO L290 TraceCheckUtils]: 112: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,898 INFO L290 TraceCheckUtils]: 113: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,899 INFO L290 TraceCheckUtils]: 114: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,899 INFO L290 TraceCheckUtils]: 115: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,899 INFO L290 TraceCheckUtils]: 116: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,900 INFO L290 TraceCheckUtils]: 117: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,900 INFO L290 TraceCheckUtils]: 118: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,901 INFO L290 TraceCheckUtils]: 119: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,901 INFO L290 TraceCheckUtils]: 120: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,901 INFO L290 TraceCheckUtils]: 121: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,902 INFO L290 TraceCheckUtils]: 122: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,902 INFO L290 TraceCheckUtils]: 123: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,903 INFO L290 TraceCheckUtils]: 124: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,903 INFO L290 TraceCheckUtils]: 125: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,903 INFO L290 TraceCheckUtils]: 126: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,904 INFO L290 TraceCheckUtils]: 127: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {18247#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:14,904 INFO L290 TraceCheckUtils]: 128: Hoare triple {18247#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {18246#false} is VALID [2022-02-21 04:23:14,904 INFO L290 TraceCheckUtils]: 129: Hoare triple {18246#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,905 INFO L290 TraceCheckUtils]: 130: Hoare triple {18246#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,905 INFO L290 TraceCheckUtils]: 131: Hoare triple {18246#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,905 INFO L290 TraceCheckUtils]: 132: Hoare triple {18246#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,905 INFO L290 TraceCheckUtils]: 133: Hoare triple {18246#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,905 INFO L290 TraceCheckUtils]: 134: Hoare triple {18246#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,905 INFO L290 TraceCheckUtils]: 135: Hoare triple {18246#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,906 INFO L290 TraceCheckUtils]: 136: Hoare triple {18246#false} assume !(1 == ~T13_E~0); {18246#false} is VALID [2022-02-21 04:23:14,906 INFO L290 TraceCheckUtils]: 137: Hoare triple {18246#false} assume 1 == ~E_M~0;~E_M~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,906 INFO L290 TraceCheckUtils]: 138: Hoare triple {18246#false} assume 1 == ~E_1~0;~E_1~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,906 INFO L290 TraceCheckUtils]: 139: Hoare triple {18246#false} assume 1 == ~E_2~0;~E_2~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,906 INFO L290 TraceCheckUtils]: 140: Hoare triple {18246#false} assume 1 == ~E_3~0;~E_3~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,906 INFO L290 TraceCheckUtils]: 141: Hoare triple {18246#false} assume 1 == ~E_4~0;~E_4~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,906 INFO L290 TraceCheckUtils]: 142: Hoare triple {18246#false} assume 1 == ~E_5~0;~E_5~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,907 INFO L290 TraceCheckUtils]: 143: Hoare triple {18246#false} assume 1 == ~E_6~0;~E_6~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,907 INFO L290 TraceCheckUtils]: 144: Hoare triple {18246#false} assume !(1 == ~E_7~0); {18246#false} is VALID [2022-02-21 04:23:14,907 INFO L290 TraceCheckUtils]: 145: Hoare triple {18246#false} assume 1 == ~E_8~0;~E_8~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,907 INFO L290 TraceCheckUtils]: 146: Hoare triple {18246#false} assume 1 == ~E_9~0;~E_9~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,907 INFO L290 TraceCheckUtils]: 147: Hoare triple {18246#false} assume 1 == ~E_10~0;~E_10~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,907 INFO L290 TraceCheckUtils]: 148: Hoare triple {18246#false} assume 1 == ~E_11~0;~E_11~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,907 INFO L290 TraceCheckUtils]: 149: Hoare triple {18246#false} assume 1 == ~E_12~0;~E_12~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,908 INFO L290 TraceCheckUtils]: 150: Hoare triple {18246#false} assume 1 == ~E_13~0;~E_13~0 := 2; {18246#false} is VALID [2022-02-21 04:23:14,908 INFO L290 TraceCheckUtils]: 151: Hoare triple {18246#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {18246#false} is VALID [2022-02-21 04:23:14,908 INFO L290 TraceCheckUtils]: 152: Hoare triple {18246#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {18246#false} is VALID [2022-02-21 04:23:14,908 INFO L290 TraceCheckUtils]: 153: Hoare triple {18246#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {18246#false} is VALID [2022-02-21 04:23:14,908 INFO L290 TraceCheckUtils]: 154: Hoare triple {18246#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {18246#false} is VALID [2022-02-21 04:23:14,908 INFO L290 TraceCheckUtils]: 155: Hoare triple {18246#false} assume !(0 == start_simulation_~tmp~3#1); {18246#false} is VALID [2022-02-21 04:23:14,909 INFO L290 TraceCheckUtils]: 156: Hoare triple {18246#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {18246#false} is VALID [2022-02-21 04:23:14,909 INFO L290 TraceCheckUtils]: 157: Hoare triple {18246#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {18246#false} is VALID [2022-02-21 04:23:14,909 INFO L290 TraceCheckUtils]: 158: Hoare triple {18246#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {18246#false} is VALID [2022-02-21 04:23:14,909 INFO L290 TraceCheckUtils]: 159: Hoare triple {18246#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {18246#false} is VALID [2022-02-21 04:23:14,909 INFO L290 TraceCheckUtils]: 160: Hoare triple {18246#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {18246#false} is VALID [2022-02-21 04:23:14,909 INFO L290 TraceCheckUtils]: 161: Hoare triple {18246#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {18246#false} is VALID [2022-02-21 04:23:14,909 INFO L290 TraceCheckUtils]: 162: Hoare triple {18246#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {18246#false} is VALID [2022-02-21 04:23:14,910 INFO L290 TraceCheckUtils]: 163: Hoare triple {18246#false} assume !(0 != start_simulation_~tmp___0~1#1); {18246#false} is VALID [2022-02-21 04:23:14,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:14,923 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:14,923 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143348832] [2022-02-21 04:23:14,924 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1143348832] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:14,924 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:14,924 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:14,924 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [645505303] [2022-02-21 04:23:14,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:14,925 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:14,925 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:14,926 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:14,926 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:14,927 INFO L87 Difference]: Start difference. First operand 2023 states and 2995 transitions. cyclomatic complexity: 973 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,733 INFO L93 Difference]: Finished difference Result 2023 states and 2994 transitions. [2022-02-21 04:23:16,733 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:16,734 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,873 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:16,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2994 transitions. [2022-02-21 04:23:16,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:17,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2994 transitions. [2022-02-21 04:23:17,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:17,120 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:17,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2994 transitions. [2022-02-21 04:23:17,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:17,123 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2022-02-21 04:23:17,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2994 transitions. [2022-02-21 04:23:17,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:17,150 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:17,153 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2994 transitions. Second operand has 2023 states, 2023 states have (on average 1.4799802273850717) internal successors, (2994), 2022 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,156 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2994 transitions. Second operand has 2023 states, 2023 states have (on average 1.4799802273850717) internal successors, (2994), 2022 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,159 INFO L87 Difference]: Start difference. First operand 2023 states and 2994 transitions. Second operand has 2023 states, 2023 states have (on average 1.4799802273850717) internal successors, (2994), 2022 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,279 INFO L93 Difference]: Finished difference Result 2023 states and 2994 transitions. [2022-02-21 04:23:17,279 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2994 transitions. [2022-02-21 04:23:17,282 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:17,282 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:17,286 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4799802273850717) internal successors, (2994), 2022 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2994 transitions. [2022-02-21 04:23:17,289 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4799802273850717) internal successors, (2994), 2022 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2994 transitions. [2022-02-21 04:23:17,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,404 INFO L93 Difference]: Finished difference Result 2023 states and 2994 transitions. [2022-02-21 04:23:17,404 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2994 transitions. [2022-02-21 04:23:17,406 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:17,406 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:17,407 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:17,407 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:17,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4799802273850717) internal successors, (2994), 2022 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2994 transitions. [2022-02-21 04:23:17,535 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2022-02-21 04:23:17,535 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2022-02-21 04:23:17,535 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:23:17,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2994 transitions. [2022-02-21 04:23:17,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:17,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:17,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:17,544 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:17,544 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:17,545 INFO L791 eck$LassoCheckResult]: Stem: 21198#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 21199#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 22197#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22198#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22283#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 21662#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21131#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21132#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 21948#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 21949#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 22049#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22050#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20903#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20904#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22079#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21439#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21440#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22000#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21341#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21342#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 22284#L1291-2 assume !(0 == ~T1_E~0); 22282#L1296-1 assume !(0 == ~T2_E~0); 21498#L1301-1 assume !(0 == ~T3_E~0); 21499#L1306-1 assume !(0 == ~T4_E~0); 22008#L1311-1 assume !(0 == ~T5_E~0); 20746#L1316-1 assume !(0 == ~T6_E~0); 20747#L1321-1 assume !(0 == ~T7_E~0); 21511#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20574#L1331-1 assume !(0 == ~T9_E~0); 20273#L1336-1 assume !(0 == ~T10_E~0); 20274#L1341-1 assume !(0 == ~T11_E~0); 20354#L1346-1 assume !(0 == ~T12_E~0); 20355#L1351-1 assume !(0 == ~T13_E~0); 20695#L1356-1 assume !(0 == ~E_M~0); 20696#L1361-1 assume !(0 == ~E_1~0); 22223#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 20736#L1371-1 assume !(0 == ~E_3~0); 20737#L1376-1 assume !(0 == ~E_4~0); 21558#L1381-1 assume !(0 == ~E_5~0); 21559#L1386-1 assume !(0 == ~E_6~0); 22253#L1391-1 assume !(0 == ~E_7~0); 22271#L1396-1 assume !(0 == ~E_8~0); 21471#L1401-1 assume !(0 == ~E_9~0); 21472#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21750#L1411-1 assume !(0 == ~E_11~0); 21751#L1416-1 assume !(0 == ~E_12~0); 21383#L1421-1 assume !(0 == ~E_13~0); 20926#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20927#L640 assume !(1 == ~m_pc~0); 21436#L640-2 is_master_triggered_~__retres1~0#1 := 0; 21435#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21527#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21421#L1603 assume !(0 != activate_threads_~tmp~1#1); 21422#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21056#L659 assume 1 == ~t1_pc~0; 21057#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21162#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22108#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21182#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 21183#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21196#L678 assume 1 == ~t2_pc~0; 22150#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22151#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22250#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21294#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 21295#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21416#L697 assume !(1 == ~t3_pc~0); 21417#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21539#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21347#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21326#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21327#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22187#L716 assume 1 == ~t4_pc~0; 22173#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21037#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21038#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20537#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 20538#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21829#L735 assume !(1 == ~t5_pc~0); 20498#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20499#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20949#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21856#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 21492#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21493#L754 assume 1 == ~t6_pc~0; 21246#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21144#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21145#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21118#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 21119#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21939#L773 assume !(1 == ~t7_pc~0); 20699#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20698#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21528#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21500#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 21501#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21548#L792 assume 1 == ~t8_pc~0; 21721#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22053#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21542#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21495#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 21419#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21420#L811 assume 1 == ~t9_pc~0; 21624#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22090#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21966#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21620#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 21432#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21433#L830 assume !(1 == ~t10_pc~0); 21154#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20678#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20371#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20372#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20659#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21957#L849 assume 1 == ~t11_pc~0; 21958#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20474#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20475#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21064#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 21863#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21864#L868 assume !(1 == ~t12_pc~0); 21279#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21278#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21073#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21074#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 20710#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20711#L887 assume 1 == ~t13_pc~0; 21878#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21320#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21321#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21757#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 20414#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20415#L1439 assume !(1 == ~M_E~0); 21488#L1439-2 assume !(1 == ~T1_E~0); 20586#L1444-1 assume !(1 == ~T2_E~0); 20587#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21060#L1454-1 assume !(1 == ~T4_E~0); 21061#L1459-1 assume !(1 == ~T5_E~0); 21617#L1464-1 assume !(1 == ~T6_E~0); 21618#L1469-1 assume !(1 == ~T7_E~0); 21690#L1474-1 assume !(1 == ~T8_E~0); 21384#L1479-1 assume !(1 == ~T9_E~0); 21385#L1484-1 assume !(1 == ~T10_E~0); 21621#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21267#L1494-1 assume !(1 == ~T12_E~0); 21268#L1499-1 assume !(1 == ~T13_E~0); 21460#L1504-1 assume !(1 == ~E_M~0); 21461#L1509-1 assume !(1 == ~E_1~0); 22036#L1514-1 assume !(1 == ~E_2~0); 21723#L1519-1 assume !(1 == ~E_3~0); 21724#L1524-1 assume !(1 == ~E_4~0); 22236#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22237#L1534-1 assume !(1 == ~E_6~0); 20407#L1539-1 assume !(1 == ~E_7~0); 20408#L1544-1 assume !(1 == ~E_8~0); 20822#L1549-1 assume !(1 == ~E_9~0); 22211#L1554-1 assume !(1 == ~E_10~0); 22207#L1559-1 assume !(1 == ~E_11~0); 22074#L1564-1 assume !(1 == ~E_12~0); 22075#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22232#L1574-1 assume { :end_inline_reset_delta_events } true; 20584#L1940-2 [2022-02-21 04:23:17,545 INFO L793 eck$LassoCheckResult]: Loop: 20584#L1940-2 assume !false; 20585#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20867#L1266 assume !false; 21886#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21115#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20848#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21239#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21240#L1079 assume !(0 != eval_~tmp~0#1); 21201#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21202#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21806#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21691#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21692#L1296-3 assume !(0 == ~T2_E~0); 22264#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22218#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21349#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20625#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20626#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20726#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21483#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21732#L1336-3 assume !(0 == ~T10_E~0); 21733#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21053#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21033#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 20978#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20979#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21540#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20329#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20330#L1376-3 assume !(0 == ~E_4~0); 22059#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21919#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21920#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22082#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22083#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20692#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20546#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20547#L1416-3 assume !(0 == ~E_12~0); 21208#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21209#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21316#L640-45 assume !(1 == ~m_pc~0); 21317#L640-47 is_master_triggered_~__retres1~0#1 := 0; 20783#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20784#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20323#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20324#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20422#L659-45 assume 1 == ~t1_pc~0; 20423#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20862#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21821#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21822#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21843#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21844#L678-45 assume 1 == ~t2_pc~0; 21787#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21322#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21323#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21475#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22100#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22217#L697-45 assume 1 == ~t3_pc~0; 21580#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21581#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22169#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21739#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21740#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21770#L716-45 assume 1 == ~t4_pc~0; 21401#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21402#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21952#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21407#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21408#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21070#L735-45 assume !(1 == ~t5_pc~0); 21072#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 21614#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22176#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22177#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22235#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22230#L754-45 assume 1 == ~t6_pc~0; 21562#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21563#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20992#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20993#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21566#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21298#L773-45 assume 1 == ~t7_pc~0; 21299#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20856#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21776#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22058#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 21304#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20974#L792-45 assume !(1 == ~t8_pc~0); 20976#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 22004#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20577#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20436#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20437#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20932#L811-45 assume 1 == ~t9_pc~0; 20721#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20723#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21931#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21766#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21375#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21167#L830-45 assume 1 == ~t10_pc~0; 21168#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20365#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21487#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20597#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20598#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20343#L849-45 assume !(1 == ~t11_pc~0); 20344#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 20803#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20434#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20331#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20332#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20590#L868-45 assume !(1 == ~t12_pc~0); 20592#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 20530#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20531#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21869#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22120#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22121#L887-45 assume !(1 == ~t13_pc~0); 20599#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 20600#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21882#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22227#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20562#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20563#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21870#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20582#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20583#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20740#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21671#L1459-3 assume !(1 == ~T5_E~0); 21672#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22123#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22062#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22063#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22124#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21356#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21357#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21993#L1499-3 assume !(1 == ~T13_E~0); 21632#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21633#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22071#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22101#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21275#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21276#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22143#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21543#L1539-3 assume !(1 == ~E_7~0); 21019#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21020#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21515#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20636#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20637#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21771#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21772#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20513#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20284#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20559#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 20520#L1959 assume !(0 == start_simulation_~tmp~3#1); 20522#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20554#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20504#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21813#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21934#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22141#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22155#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22156#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 20584#L1940-2 [2022-02-21 04:23:17,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:17,546 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2022-02-21 04:23:17,546 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:17,546 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412975201] [2022-02-21 04:23:17,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:17,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:17,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:17,576 INFO L290 TraceCheckUtils]: 0: Hoare triple {26343#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {26343#true} is VALID [2022-02-21 04:23:17,576 INFO L290 TraceCheckUtils]: 1: Hoare triple {26343#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {26345#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:17,577 INFO L290 TraceCheckUtils]: 2: Hoare triple {26345#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {26345#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:17,577 INFO L290 TraceCheckUtils]: 3: Hoare triple {26345#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {26345#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:17,577 INFO L290 TraceCheckUtils]: 4: Hoare triple {26345#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {26345#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:17,578 INFO L290 TraceCheckUtils]: 5: Hoare triple {26345#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {26345#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:17,578 INFO L290 TraceCheckUtils]: 6: Hoare triple {26345#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {26345#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:17,579 INFO L290 TraceCheckUtils]: 7: Hoare triple {26345#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,579 INFO L290 TraceCheckUtils]: 8: Hoare triple {26344#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,579 INFO L290 TraceCheckUtils]: 9: Hoare triple {26344#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,579 INFO L290 TraceCheckUtils]: 10: Hoare triple {26344#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,579 INFO L290 TraceCheckUtils]: 11: Hoare triple {26344#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,579 INFO L290 TraceCheckUtils]: 12: Hoare triple {26344#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,579 INFO L290 TraceCheckUtils]: 13: Hoare triple {26344#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {26344#false} is VALID [2022-02-21 04:23:17,580 INFO L290 TraceCheckUtils]: 14: Hoare triple {26344#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,580 INFO L290 TraceCheckUtils]: 15: Hoare triple {26344#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,580 INFO L290 TraceCheckUtils]: 16: Hoare triple {26344#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,580 INFO L290 TraceCheckUtils]: 17: Hoare triple {26344#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,580 INFO L290 TraceCheckUtils]: 18: Hoare triple {26344#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {26344#false} is VALID [2022-02-21 04:23:17,580 INFO L290 TraceCheckUtils]: 19: Hoare triple {26344#false} assume 0 == ~M_E~0;~M_E~0 := 1; {26344#false} is VALID [2022-02-21 04:23:17,580 INFO L290 TraceCheckUtils]: 20: Hoare triple {26344#false} assume !(0 == ~T1_E~0); {26344#false} is VALID [2022-02-21 04:23:17,581 INFO L290 TraceCheckUtils]: 21: Hoare triple {26344#false} assume !(0 == ~T2_E~0); {26344#false} is VALID [2022-02-21 04:23:17,581 INFO L290 TraceCheckUtils]: 22: Hoare triple {26344#false} assume !(0 == ~T3_E~0); {26344#false} is VALID [2022-02-21 04:23:17,581 INFO L290 TraceCheckUtils]: 23: Hoare triple {26344#false} assume !(0 == ~T4_E~0); {26344#false} is VALID [2022-02-21 04:23:17,581 INFO L290 TraceCheckUtils]: 24: Hoare triple {26344#false} assume !(0 == ~T5_E~0); {26344#false} is VALID [2022-02-21 04:23:17,581 INFO L290 TraceCheckUtils]: 25: Hoare triple {26344#false} assume !(0 == ~T6_E~0); {26344#false} is VALID [2022-02-21 04:23:17,581 INFO L290 TraceCheckUtils]: 26: Hoare triple {26344#false} assume !(0 == ~T7_E~0); {26344#false} is VALID [2022-02-21 04:23:17,581 INFO L290 TraceCheckUtils]: 27: Hoare triple {26344#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {26344#false} is VALID [2022-02-21 04:23:17,582 INFO L290 TraceCheckUtils]: 28: Hoare triple {26344#false} assume !(0 == ~T9_E~0); {26344#false} is VALID [2022-02-21 04:23:17,582 INFO L290 TraceCheckUtils]: 29: Hoare triple {26344#false} assume !(0 == ~T10_E~0); {26344#false} is VALID [2022-02-21 04:23:17,582 INFO L290 TraceCheckUtils]: 30: Hoare triple {26344#false} assume !(0 == ~T11_E~0); {26344#false} is VALID [2022-02-21 04:23:17,582 INFO L290 TraceCheckUtils]: 31: Hoare triple {26344#false} assume !(0 == ~T12_E~0); {26344#false} is VALID [2022-02-21 04:23:17,582 INFO L290 TraceCheckUtils]: 32: Hoare triple {26344#false} assume !(0 == ~T13_E~0); {26344#false} is VALID [2022-02-21 04:23:17,582 INFO L290 TraceCheckUtils]: 33: Hoare triple {26344#false} assume !(0 == ~E_M~0); {26344#false} is VALID [2022-02-21 04:23:17,582 INFO L290 TraceCheckUtils]: 34: Hoare triple {26344#false} assume !(0 == ~E_1~0); {26344#false} is VALID [2022-02-21 04:23:17,583 INFO L290 TraceCheckUtils]: 35: Hoare triple {26344#false} assume 0 == ~E_2~0;~E_2~0 := 1; {26344#false} is VALID [2022-02-21 04:23:17,583 INFO L290 TraceCheckUtils]: 36: Hoare triple {26344#false} assume !(0 == ~E_3~0); {26344#false} is VALID [2022-02-21 04:23:17,583 INFO L290 TraceCheckUtils]: 37: Hoare triple {26344#false} assume !(0 == ~E_4~0); {26344#false} is VALID [2022-02-21 04:23:17,583 INFO L290 TraceCheckUtils]: 38: Hoare triple {26344#false} assume !(0 == ~E_5~0); {26344#false} is VALID [2022-02-21 04:23:17,583 INFO L290 TraceCheckUtils]: 39: Hoare triple {26344#false} assume !(0 == ~E_6~0); {26344#false} is VALID [2022-02-21 04:23:17,583 INFO L290 TraceCheckUtils]: 40: Hoare triple {26344#false} assume !(0 == ~E_7~0); {26344#false} is VALID [2022-02-21 04:23:17,583 INFO L290 TraceCheckUtils]: 41: Hoare triple {26344#false} assume !(0 == ~E_8~0); {26344#false} is VALID [2022-02-21 04:23:17,584 INFO L290 TraceCheckUtils]: 42: Hoare triple {26344#false} assume !(0 == ~E_9~0); {26344#false} is VALID [2022-02-21 04:23:17,584 INFO L290 TraceCheckUtils]: 43: Hoare triple {26344#false} assume 0 == ~E_10~0;~E_10~0 := 1; {26344#false} is VALID [2022-02-21 04:23:17,584 INFO L290 TraceCheckUtils]: 44: Hoare triple {26344#false} assume !(0 == ~E_11~0); {26344#false} is VALID [2022-02-21 04:23:17,584 INFO L290 TraceCheckUtils]: 45: Hoare triple {26344#false} assume !(0 == ~E_12~0); {26344#false} is VALID [2022-02-21 04:23:17,584 INFO L290 TraceCheckUtils]: 46: Hoare triple {26344#false} assume !(0 == ~E_13~0); {26344#false} is VALID [2022-02-21 04:23:17,584 INFO L290 TraceCheckUtils]: 47: Hoare triple {26344#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26344#false} is VALID [2022-02-21 04:23:17,584 INFO L290 TraceCheckUtils]: 48: Hoare triple {26344#false} assume !(1 == ~m_pc~0); {26344#false} is VALID [2022-02-21 04:23:17,585 INFO L290 TraceCheckUtils]: 49: Hoare triple {26344#false} is_master_triggered_~__retres1~0#1 := 0; {26344#false} is VALID [2022-02-21 04:23:17,585 INFO L290 TraceCheckUtils]: 50: Hoare triple {26344#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26344#false} is VALID [2022-02-21 04:23:17,585 INFO L290 TraceCheckUtils]: 51: Hoare triple {26344#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26344#false} is VALID [2022-02-21 04:23:17,585 INFO L290 TraceCheckUtils]: 52: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp~1#1); {26344#false} is VALID [2022-02-21 04:23:17,585 INFO L290 TraceCheckUtils]: 53: Hoare triple {26344#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26344#false} is VALID [2022-02-21 04:23:17,585 INFO L290 TraceCheckUtils]: 54: Hoare triple {26344#false} assume 1 == ~t1_pc~0; {26344#false} is VALID [2022-02-21 04:23:17,585 INFO L290 TraceCheckUtils]: 55: Hoare triple {26344#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {26344#false} is VALID [2022-02-21 04:23:17,586 INFO L290 TraceCheckUtils]: 56: Hoare triple {26344#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26344#false} is VALID [2022-02-21 04:23:17,586 INFO L290 TraceCheckUtils]: 57: Hoare triple {26344#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26344#false} is VALID [2022-02-21 04:23:17,586 INFO L290 TraceCheckUtils]: 58: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___0~0#1); {26344#false} is VALID [2022-02-21 04:23:17,586 INFO L290 TraceCheckUtils]: 59: Hoare triple {26344#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26344#false} is VALID [2022-02-21 04:23:17,586 INFO L290 TraceCheckUtils]: 60: Hoare triple {26344#false} assume 1 == ~t2_pc~0; {26344#false} is VALID [2022-02-21 04:23:17,586 INFO L290 TraceCheckUtils]: 61: Hoare triple {26344#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26344#false} is VALID [2022-02-21 04:23:17,586 INFO L290 TraceCheckUtils]: 62: Hoare triple {26344#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26344#false} is VALID [2022-02-21 04:23:17,587 INFO L290 TraceCheckUtils]: 63: Hoare triple {26344#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26344#false} is VALID [2022-02-21 04:23:17,587 INFO L290 TraceCheckUtils]: 64: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___1~0#1); {26344#false} is VALID [2022-02-21 04:23:17,587 INFO L290 TraceCheckUtils]: 65: Hoare triple {26344#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26344#false} is VALID [2022-02-21 04:23:17,587 INFO L290 TraceCheckUtils]: 66: Hoare triple {26344#false} assume !(1 == ~t3_pc~0); {26344#false} is VALID [2022-02-21 04:23:17,587 INFO L290 TraceCheckUtils]: 67: Hoare triple {26344#false} is_transmit3_triggered_~__retres1~3#1 := 0; {26344#false} is VALID [2022-02-21 04:23:17,587 INFO L290 TraceCheckUtils]: 68: Hoare triple {26344#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26344#false} is VALID [2022-02-21 04:23:17,587 INFO L290 TraceCheckUtils]: 69: Hoare triple {26344#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26344#false} is VALID [2022-02-21 04:23:17,588 INFO L290 TraceCheckUtils]: 70: Hoare triple {26344#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26344#false} is VALID [2022-02-21 04:23:17,588 INFO L290 TraceCheckUtils]: 71: Hoare triple {26344#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26344#false} is VALID [2022-02-21 04:23:17,588 INFO L290 TraceCheckUtils]: 72: Hoare triple {26344#false} assume 1 == ~t4_pc~0; {26344#false} is VALID [2022-02-21 04:23:17,588 INFO L290 TraceCheckUtils]: 73: Hoare triple {26344#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26344#false} is VALID [2022-02-21 04:23:17,588 INFO L290 TraceCheckUtils]: 74: Hoare triple {26344#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26344#false} is VALID [2022-02-21 04:23:17,588 INFO L290 TraceCheckUtils]: 75: Hoare triple {26344#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26344#false} is VALID [2022-02-21 04:23:17,588 INFO L290 TraceCheckUtils]: 76: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___3~0#1); {26344#false} is VALID [2022-02-21 04:23:17,589 INFO L290 TraceCheckUtils]: 77: Hoare triple {26344#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26344#false} is VALID [2022-02-21 04:23:17,589 INFO L290 TraceCheckUtils]: 78: Hoare triple {26344#false} assume !(1 == ~t5_pc~0); {26344#false} is VALID [2022-02-21 04:23:17,589 INFO L290 TraceCheckUtils]: 79: Hoare triple {26344#false} is_transmit5_triggered_~__retres1~5#1 := 0; {26344#false} is VALID [2022-02-21 04:23:17,589 INFO L290 TraceCheckUtils]: 80: Hoare triple {26344#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26344#false} is VALID [2022-02-21 04:23:17,589 INFO L290 TraceCheckUtils]: 81: Hoare triple {26344#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26344#false} is VALID [2022-02-21 04:23:17,589 INFO L290 TraceCheckUtils]: 82: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___4~0#1); {26344#false} is VALID [2022-02-21 04:23:17,589 INFO L290 TraceCheckUtils]: 83: Hoare triple {26344#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26344#false} is VALID [2022-02-21 04:23:17,590 INFO L290 TraceCheckUtils]: 84: Hoare triple {26344#false} assume 1 == ~t6_pc~0; {26344#false} is VALID [2022-02-21 04:23:17,590 INFO L290 TraceCheckUtils]: 85: Hoare triple {26344#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {26344#false} is VALID [2022-02-21 04:23:17,590 INFO L290 TraceCheckUtils]: 86: Hoare triple {26344#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26344#false} is VALID [2022-02-21 04:23:17,590 INFO L290 TraceCheckUtils]: 87: Hoare triple {26344#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {26344#false} is VALID [2022-02-21 04:23:17,590 INFO L290 TraceCheckUtils]: 88: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___5~0#1); {26344#false} is VALID [2022-02-21 04:23:17,590 INFO L290 TraceCheckUtils]: 89: Hoare triple {26344#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26344#false} is VALID [2022-02-21 04:23:17,590 INFO L290 TraceCheckUtils]: 90: Hoare triple {26344#false} assume !(1 == ~t7_pc~0); {26344#false} is VALID [2022-02-21 04:23:17,591 INFO L290 TraceCheckUtils]: 91: Hoare triple {26344#false} is_transmit7_triggered_~__retres1~7#1 := 0; {26344#false} is VALID [2022-02-21 04:23:17,591 INFO L290 TraceCheckUtils]: 92: Hoare triple {26344#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26344#false} is VALID [2022-02-21 04:23:17,591 INFO L290 TraceCheckUtils]: 93: Hoare triple {26344#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {26344#false} is VALID [2022-02-21 04:23:17,591 INFO L290 TraceCheckUtils]: 94: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___6~0#1); {26344#false} is VALID [2022-02-21 04:23:17,591 INFO L290 TraceCheckUtils]: 95: Hoare triple {26344#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26344#false} is VALID [2022-02-21 04:23:17,591 INFO L290 TraceCheckUtils]: 96: Hoare triple {26344#false} assume 1 == ~t8_pc~0; {26344#false} is VALID [2022-02-21 04:23:17,591 INFO L290 TraceCheckUtils]: 97: Hoare triple {26344#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {26344#false} is VALID [2022-02-21 04:23:17,592 INFO L290 TraceCheckUtils]: 98: Hoare triple {26344#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26344#false} is VALID [2022-02-21 04:23:17,592 INFO L290 TraceCheckUtils]: 99: Hoare triple {26344#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {26344#false} is VALID [2022-02-21 04:23:17,592 INFO L290 TraceCheckUtils]: 100: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___7~0#1); {26344#false} is VALID [2022-02-21 04:23:17,592 INFO L290 TraceCheckUtils]: 101: Hoare triple {26344#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26344#false} is VALID [2022-02-21 04:23:17,592 INFO L290 TraceCheckUtils]: 102: Hoare triple {26344#false} assume 1 == ~t9_pc~0; {26344#false} is VALID [2022-02-21 04:23:17,592 INFO L290 TraceCheckUtils]: 103: Hoare triple {26344#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26344#false} is VALID [2022-02-21 04:23:17,592 INFO L290 TraceCheckUtils]: 104: Hoare triple {26344#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26344#false} is VALID [2022-02-21 04:23:17,593 INFO L290 TraceCheckUtils]: 105: Hoare triple {26344#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {26344#false} is VALID [2022-02-21 04:23:17,593 INFO L290 TraceCheckUtils]: 106: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___8~0#1); {26344#false} is VALID [2022-02-21 04:23:17,593 INFO L290 TraceCheckUtils]: 107: Hoare triple {26344#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26344#false} is VALID [2022-02-21 04:23:17,593 INFO L290 TraceCheckUtils]: 108: Hoare triple {26344#false} assume !(1 == ~t10_pc~0); {26344#false} is VALID [2022-02-21 04:23:17,593 INFO L290 TraceCheckUtils]: 109: Hoare triple {26344#false} is_transmit10_triggered_~__retres1~10#1 := 0; {26344#false} is VALID [2022-02-21 04:23:17,593 INFO L290 TraceCheckUtils]: 110: Hoare triple {26344#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26344#false} is VALID [2022-02-21 04:23:17,593 INFO L290 TraceCheckUtils]: 111: Hoare triple {26344#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {26344#false} is VALID [2022-02-21 04:23:17,594 INFO L290 TraceCheckUtils]: 112: Hoare triple {26344#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {26344#false} is VALID [2022-02-21 04:23:17,594 INFO L290 TraceCheckUtils]: 113: Hoare triple {26344#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {26344#false} is VALID [2022-02-21 04:23:17,594 INFO L290 TraceCheckUtils]: 114: Hoare triple {26344#false} assume 1 == ~t11_pc~0; {26344#false} is VALID [2022-02-21 04:23:17,594 INFO L290 TraceCheckUtils]: 115: Hoare triple {26344#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {26344#false} is VALID [2022-02-21 04:23:17,594 INFO L290 TraceCheckUtils]: 116: Hoare triple {26344#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {26344#false} is VALID [2022-02-21 04:23:17,594 INFO L290 TraceCheckUtils]: 117: Hoare triple {26344#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {26344#false} is VALID [2022-02-21 04:23:17,594 INFO L290 TraceCheckUtils]: 118: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___10~0#1); {26344#false} is VALID [2022-02-21 04:23:17,595 INFO L290 TraceCheckUtils]: 119: Hoare triple {26344#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {26344#false} is VALID [2022-02-21 04:23:17,595 INFO L290 TraceCheckUtils]: 120: Hoare triple {26344#false} assume !(1 == ~t12_pc~0); {26344#false} is VALID [2022-02-21 04:23:17,595 INFO L290 TraceCheckUtils]: 121: Hoare triple {26344#false} is_transmit12_triggered_~__retres1~12#1 := 0; {26344#false} is VALID [2022-02-21 04:23:17,595 INFO L290 TraceCheckUtils]: 122: Hoare triple {26344#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {26344#false} is VALID [2022-02-21 04:23:17,595 INFO L290 TraceCheckUtils]: 123: Hoare triple {26344#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {26344#false} is VALID [2022-02-21 04:23:17,595 INFO L290 TraceCheckUtils]: 124: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___11~0#1); {26344#false} is VALID [2022-02-21 04:23:17,596 INFO L290 TraceCheckUtils]: 125: Hoare triple {26344#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {26344#false} is VALID [2022-02-21 04:23:17,596 INFO L290 TraceCheckUtils]: 126: Hoare triple {26344#false} assume 1 == ~t13_pc~0; {26344#false} is VALID [2022-02-21 04:23:17,596 INFO L290 TraceCheckUtils]: 127: Hoare triple {26344#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {26344#false} is VALID [2022-02-21 04:23:17,596 INFO L290 TraceCheckUtils]: 128: Hoare triple {26344#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {26344#false} is VALID [2022-02-21 04:23:17,596 INFO L290 TraceCheckUtils]: 129: Hoare triple {26344#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {26344#false} is VALID [2022-02-21 04:23:17,596 INFO L290 TraceCheckUtils]: 130: Hoare triple {26344#false} assume !(0 != activate_threads_~tmp___12~0#1); {26344#false} is VALID [2022-02-21 04:23:17,596 INFO L290 TraceCheckUtils]: 131: Hoare triple {26344#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26344#false} is VALID [2022-02-21 04:23:17,597 INFO L290 TraceCheckUtils]: 132: Hoare triple {26344#false} assume !(1 == ~M_E~0); {26344#false} is VALID [2022-02-21 04:23:17,597 INFO L290 TraceCheckUtils]: 133: Hoare triple {26344#false} assume !(1 == ~T1_E~0); {26344#false} is VALID [2022-02-21 04:23:17,597 INFO L290 TraceCheckUtils]: 134: Hoare triple {26344#false} assume !(1 == ~T2_E~0); {26344#false} is VALID [2022-02-21 04:23:17,597 INFO L290 TraceCheckUtils]: 135: Hoare triple {26344#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,597 INFO L290 TraceCheckUtils]: 136: Hoare triple {26344#false} assume !(1 == ~T4_E~0); {26344#false} is VALID [2022-02-21 04:23:17,597 INFO L290 TraceCheckUtils]: 137: Hoare triple {26344#false} assume !(1 == ~T5_E~0); {26344#false} is VALID [2022-02-21 04:23:17,597 INFO L290 TraceCheckUtils]: 138: Hoare triple {26344#false} assume !(1 == ~T6_E~0); {26344#false} is VALID [2022-02-21 04:23:17,598 INFO L290 TraceCheckUtils]: 139: Hoare triple {26344#false} assume !(1 == ~T7_E~0); {26344#false} is VALID [2022-02-21 04:23:17,598 INFO L290 TraceCheckUtils]: 140: Hoare triple {26344#false} assume !(1 == ~T8_E~0); {26344#false} is VALID [2022-02-21 04:23:17,598 INFO L290 TraceCheckUtils]: 141: Hoare triple {26344#false} assume !(1 == ~T9_E~0); {26344#false} is VALID [2022-02-21 04:23:17,598 INFO L290 TraceCheckUtils]: 142: Hoare triple {26344#false} assume !(1 == ~T10_E~0); {26344#false} is VALID [2022-02-21 04:23:17,598 INFO L290 TraceCheckUtils]: 143: Hoare triple {26344#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,598 INFO L290 TraceCheckUtils]: 144: Hoare triple {26344#false} assume !(1 == ~T12_E~0); {26344#false} is VALID [2022-02-21 04:23:17,598 INFO L290 TraceCheckUtils]: 145: Hoare triple {26344#false} assume !(1 == ~T13_E~0); {26344#false} is VALID [2022-02-21 04:23:17,599 INFO L290 TraceCheckUtils]: 146: Hoare triple {26344#false} assume !(1 == ~E_M~0); {26344#false} is VALID [2022-02-21 04:23:17,599 INFO L290 TraceCheckUtils]: 147: Hoare triple {26344#false} assume !(1 == ~E_1~0); {26344#false} is VALID [2022-02-21 04:23:17,599 INFO L290 TraceCheckUtils]: 148: Hoare triple {26344#false} assume !(1 == ~E_2~0); {26344#false} is VALID [2022-02-21 04:23:17,599 INFO L290 TraceCheckUtils]: 149: Hoare triple {26344#false} assume !(1 == ~E_3~0); {26344#false} is VALID [2022-02-21 04:23:17,599 INFO L290 TraceCheckUtils]: 150: Hoare triple {26344#false} assume !(1 == ~E_4~0); {26344#false} is VALID [2022-02-21 04:23:17,599 INFO L290 TraceCheckUtils]: 151: Hoare triple {26344#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,599 INFO L290 TraceCheckUtils]: 152: Hoare triple {26344#false} assume !(1 == ~E_6~0); {26344#false} is VALID [2022-02-21 04:23:17,600 INFO L290 TraceCheckUtils]: 153: Hoare triple {26344#false} assume !(1 == ~E_7~0); {26344#false} is VALID [2022-02-21 04:23:17,600 INFO L290 TraceCheckUtils]: 154: Hoare triple {26344#false} assume !(1 == ~E_8~0); {26344#false} is VALID [2022-02-21 04:23:17,600 INFO L290 TraceCheckUtils]: 155: Hoare triple {26344#false} assume !(1 == ~E_9~0); {26344#false} is VALID [2022-02-21 04:23:17,600 INFO L290 TraceCheckUtils]: 156: Hoare triple {26344#false} assume !(1 == ~E_10~0); {26344#false} is VALID [2022-02-21 04:23:17,600 INFO L290 TraceCheckUtils]: 157: Hoare triple {26344#false} assume !(1 == ~E_11~0); {26344#false} is VALID [2022-02-21 04:23:17,600 INFO L290 TraceCheckUtils]: 158: Hoare triple {26344#false} assume !(1 == ~E_12~0); {26344#false} is VALID [2022-02-21 04:23:17,600 INFO L290 TraceCheckUtils]: 159: Hoare triple {26344#false} assume 1 == ~E_13~0;~E_13~0 := 2; {26344#false} is VALID [2022-02-21 04:23:17,601 INFO L290 TraceCheckUtils]: 160: Hoare triple {26344#false} assume { :end_inline_reset_delta_events } true; {26344#false} is VALID [2022-02-21 04:23:17,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:17,601 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:17,601 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412975201] [2022-02-21 04:23:17,602 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412975201] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:17,602 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:17,602 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:17,602 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105906024] [2022-02-21 04:23:17,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:17,603 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:17,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:17,603 INFO L85 PathProgramCache]: Analyzing trace with hash -990138912, now seen corresponding path program 1 times [2022-02-21 04:23:17,603 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:17,604 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230972852] [2022-02-21 04:23:17,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:17,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:17,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:17,662 INFO L290 TraceCheckUtils]: 0: Hoare triple {26346#true} assume !false; {26346#true} is VALID [2022-02-21 04:23:17,662 INFO L290 TraceCheckUtils]: 1: Hoare triple {26346#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {26346#true} is VALID [2022-02-21 04:23:17,663 INFO L290 TraceCheckUtils]: 2: Hoare triple {26346#true} assume !false; {26346#true} is VALID [2022-02-21 04:23:17,663 INFO L290 TraceCheckUtils]: 3: Hoare triple {26346#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {26346#true} is VALID [2022-02-21 04:23:17,663 INFO L290 TraceCheckUtils]: 4: Hoare triple {26346#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {26346#true} is VALID [2022-02-21 04:23:17,663 INFO L290 TraceCheckUtils]: 5: Hoare triple {26346#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {26346#true} is VALID [2022-02-21 04:23:17,663 INFO L290 TraceCheckUtils]: 6: Hoare triple {26346#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {26346#true} is VALID [2022-02-21 04:23:17,663 INFO L290 TraceCheckUtils]: 7: Hoare triple {26346#true} assume !(0 != eval_~tmp~0#1); {26346#true} is VALID [2022-02-21 04:23:17,663 INFO L290 TraceCheckUtils]: 8: Hoare triple {26346#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {26346#true} is VALID [2022-02-21 04:23:17,664 INFO L290 TraceCheckUtils]: 9: Hoare triple {26346#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {26346#true} is VALID [2022-02-21 04:23:17,664 INFO L290 TraceCheckUtils]: 10: Hoare triple {26346#true} assume 0 == ~M_E~0;~M_E~0 := 1; {26346#true} is VALID [2022-02-21 04:23:17,664 INFO L290 TraceCheckUtils]: 11: Hoare triple {26346#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {26346#true} is VALID [2022-02-21 04:23:17,664 INFO L290 TraceCheckUtils]: 12: Hoare triple {26346#true} assume !(0 == ~T2_E~0); {26346#true} is VALID [2022-02-21 04:23:17,664 INFO L290 TraceCheckUtils]: 13: Hoare triple {26346#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {26346#true} is VALID [2022-02-21 04:23:17,664 INFO L290 TraceCheckUtils]: 14: Hoare triple {26346#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {26346#true} is VALID [2022-02-21 04:23:17,665 INFO L290 TraceCheckUtils]: 15: Hoare triple {26346#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,665 INFO L290 TraceCheckUtils]: 16: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,665 INFO L290 TraceCheckUtils]: 17: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,666 INFO L290 TraceCheckUtils]: 18: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,666 INFO L290 TraceCheckUtils]: 19: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,667 INFO L290 TraceCheckUtils]: 20: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,667 INFO L290 TraceCheckUtils]: 21: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,667 INFO L290 TraceCheckUtils]: 22: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,668 INFO L290 TraceCheckUtils]: 23: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,668 INFO L290 TraceCheckUtils]: 24: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,669 INFO L290 TraceCheckUtils]: 25: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,669 INFO L290 TraceCheckUtils]: 26: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,669 INFO L290 TraceCheckUtils]: 27: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,670 INFO L290 TraceCheckUtils]: 28: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,670 INFO L290 TraceCheckUtils]: 29: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,670 INFO L290 TraceCheckUtils]: 30: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,671 INFO L290 TraceCheckUtils]: 31: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,671 INFO L290 TraceCheckUtils]: 32: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,672 INFO L290 TraceCheckUtils]: 33: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,672 INFO L290 TraceCheckUtils]: 34: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,672 INFO L290 TraceCheckUtils]: 35: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,673 INFO L290 TraceCheckUtils]: 36: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,673 INFO L290 TraceCheckUtils]: 37: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,674 INFO L290 TraceCheckUtils]: 38: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,674 INFO L290 TraceCheckUtils]: 39: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,674 INFO L290 TraceCheckUtils]: 40: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,675 INFO L290 TraceCheckUtils]: 41: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,675 INFO L290 TraceCheckUtils]: 42: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,676 INFO L290 TraceCheckUtils]: 43: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,676 INFO L290 TraceCheckUtils]: 44: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,676 INFO L290 TraceCheckUtils]: 45: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,677 INFO L290 TraceCheckUtils]: 46: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,677 INFO L290 TraceCheckUtils]: 47: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,678 INFO L290 TraceCheckUtils]: 48: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,678 INFO L290 TraceCheckUtils]: 49: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,678 INFO L290 TraceCheckUtils]: 50: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,679 INFO L290 TraceCheckUtils]: 51: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,679 INFO L290 TraceCheckUtils]: 52: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,679 INFO L290 TraceCheckUtils]: 53: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,680 INFO L290 TraceCheckUtils]: 54: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,680 INFO L290 TraceCheckUtils]: 55: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,681 INFO L290 TraceCheckUtils]: 56: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,681 INFO L290 TraceCheckUtils]: 57: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,681 INFO L290 TraceCheckUtils]: 58: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,682 INFO L290 TraceCheckUtils]: 59: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,682 INFO L290 TraceCheckUtils]: 60: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,683 INFO L290 TraceCheckUtils]: 61: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,683 INFO L290 TraceCheckUtils]: 62: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,683 INFO L290 TraceCheckUtils]: 63: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,684 INFO L290 TraceCheckUtils]: 64: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,684 INFO L290 TraceCheckUtils]: 65: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,685 INFO L290 TraceCheckUtils]: 66: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,685 INFO L290 TraceCheckUtils]: 67: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,685 INFO L290 TraceCheckUtils]: 68: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,686 INFO L290 TraceCheckUtils]: 69: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,686 INFO L290 TraceCheckUtils]: 70: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,686 INFO L290 TraceCheckUtils]: 71: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,687 INFO L290 TraceCheckUtils]: 72: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,687 INFO L290 TraceCheckUtils]: 73: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 74: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 75: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 76: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 77: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 78: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 79: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 80: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 81: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,691 INFO L290 TraceCheckUtils]: 82: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,691 INFO L290 TraceCheckUtils]: 83: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 84: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 85: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 86: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 87: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 88: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 89: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 90: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 91: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 92: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 93: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 94: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,696 INFO L290 TraceCheckUtils]: 95: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,696 INFO L290 TraceCheckUtils]: 96: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,697 INFO L290 TraceCheckUtils]: 97: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,697 INFO L290 TraceCheckUtils]: 98: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,697 INFO L290 TraceCheckUtils]: 99: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,698 INFO L290 TraceCheckUtils]: 100: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,698 INFO L290 TraceCheckUtils]: 101: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,698 INFO L290 TraceCheckUtils]: 102: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,699 INFO L290 TraceCheckUtils]: 103: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,699 INFO L290 TraceCheckUtils]: 104: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,700 INFO L290 TraceCheckUtils]: 105: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,700 INFO L290 TraceCheckUtils]: 106: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,700 INFO L290 TraceCheckUtils]: 107: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,701 INFO L290 TraceCheckUtils]: 108: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,701 INFO L290 TraceCheckUtils]: 109: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 110: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 111: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t12_pc~0); {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 112: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 113: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 114: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 115: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,704 INFO L290 TraceCheckUtils]: 116: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,704 INFO L290 TraceCheckUtils]: 117: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 118: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 119: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 120: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 121: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 122: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 123: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,707 INFO L290 TraceCheckUtils]: 124: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,707 INFO L290 TraceCheckUtils]: 125: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 126: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 127: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {26348#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 128: Hoare triple {26348#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {26347#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 129: Hoare triple {26347#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 130: Hoare triple {26347#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 131: Hoare triple {26347#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 132: Hoare triple {26347#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 133: Hoare triple {26347#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 134: Hoare triple {26347#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 135: Hoare triple {26347#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 136: Hoare triple {26347#false} assume !(1 == ~T13_E~0); {26347#false} is VALID [2022-02-21 04:23:17,710 INFO L290 TraceCheckUtils]: 137: Hoare triple {26347#false} assume 1 == ~E_M~0;~E_M~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,710 INFO L290 TraceCheckUtils]: 138: Hoare triple {26347#false} assume 1 == ~E_1~0;~E_1~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,710 INFO L290 TraceCheckUtils]: 139: Hoare triple {26347#false} assume 1 == ~E_2~0;~E_2~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,710 INFO L290 TraceCheckUtils]: 140: Hoare triple {26347#false} assume 1 == ~E_3~0;~E_3~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,710 INFO L290 TraceCheckUtils]: 141: Hoare triple {26347#false} assume 1 == ~E_4~0;~E_4~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,710 INFO L290 TraceCheckUtils]: 142: Hoare triple {26347#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,710 INFO L290 TraceCheckUtils]: 143: Hoare triple {26347#false} assume 1 == ~E_6~0;~E_6~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,711 INFO L290 TraceCheckUtils]: 144: Hoare triple {26347#false} assume !(1 == ~E_7~0); {26347#false} is VALID [2022-02-21 04:23:17,711 INFO L290 TraceCheckUtils]: 145: Hoare triple {26347#false} assume 1 == ~E_8~0;~E_8~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,711 INFO L290 TraceCheckUtils]: 146: Hoare triple {26347#false} assume 1 == ~E_9~0;~E_9~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,711 INFO L290 TraceCheckUtils]: 147: Hoare triple {26347#false} assume 1 == ~E_10~0;~E_10~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,711 INFO L290 TraceCheckUtils]: 148: Hoare triple {26347#false} assume 1 == ~E_11~0;~E_11~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,711 INFO L290 TraceCheckUtils]: 149: Hoare triple {26347#false} assume 1 == ~E_12~0;~E_12~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,711 INFO L290 TraceCheckUtils]: 150: Hoare triple {26347#false} assume 1 == ~E_13~0;~E_13~0 := 2; {26347#false} is VALID [2022-02-21 04:23:17,712 INFO L290 TraceCheckUtils]: 151: Hoare triple {26347#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {26347#false} is VALID [2022-02-21 04:23:17,712 INFO L290 TraceCheckUtils]: 152: Hoare triple {26347#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {26347#false} is VALID [2022-02-21 04:23:17,712 INFO L290 TraceCheckUtils]: 153: Hoare triple {26347#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {26347#false} is VALID [2022-02-21 04:23:17,712 INFO L290 TraceCheckUtils]: 154: Hoare triple {26347#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {26347#false} is VALID [2022-02-21 04:23:17,712 INFO L290 TraceCheckUtils]: 155: Hoare triple {26347#false} assume !(0 == start_simulation_~tmp~3#1); {26347#false} is VALID [2022-02-21 04:23:17,712 INFO L290 TraceCheckUtils]: 156: Hoare triple {26347#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {26347#false} is VALID [2022-02-21 04:23:17,712 INFO L290 TraceCheckUtils]: 157: Hoare triple {26347#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {26347#false} is VALID [2022-02-21 04:23:17,712 INFO L290 TraceCheckUtils]: 158: Hoare triple {26347#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {26347#false} is VALID [2022-02-21 04:23:17,713 INFO L290 TraceCheckUtils]: 159: Hoare triple {26347#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {26347#false} is VALID [2022-02-21 04:23:17,713 INFO L290 TraceCheckUtils]: 160: Hoare triple {26347#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {26347#false} is VALID [2022-02-21 04:23:17,713 INFO L290 TraceCheckUtils]: 161: Hoare triple {26347#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {26347#false} is VALID [2022-02-21 04:23:17,713 INFO L290 TraceCheckUtils]: 162: Hoare triple {26347#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {26347#false} is VALID [2022-02-21 04:23:17,713 INFO L290 TraceCheckUtils]: 163: Hoare triple {26347#false} assume !(0 != start_simulation_~tmp___0~1#1); {26347#false} is VALID [2022-02-21 04:23:17,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:17,714 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:17,715 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230972852] [2022-02-21 04:23:17,715 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230972852] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:17,715 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:17,715 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:17,715 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670618253] [2022-02-21 04:23:17,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:17,716 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:17,716 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:17,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:17,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:17,717 INFO L87 Difference]: Start difference. First operand 2023 states and 2994 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,317 INFO L93 Difference]: Finished difference Result 2023 states and 2993 transitions. [2022-02-21 04:23:19,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:19,318 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,415 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:19,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2993 transitions. [2022-02-21 04:23:19,515 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:19,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2993 transitions. [2022-02-21 04:23:19,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:19,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:19,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2993 transitions. [2022-02-21 04:23:19,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:19,678 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2022-02-21 04:23:19,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2993 transitions. [2022-02-21 04:23:19,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:19,705 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:19,709 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2993 transitions. Second operand has 2023 states, 2023 states have (on average 1.4794859120118635) internal successors, (2993), 2022 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,711 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2993 transitions. Second operand has 2023 states, 2023 states have (on average 1.4794859120118635) internal successors, (2993), 2022 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,714 INFO L87 Difference]: Start difference. First operand 2023 states and 2993 transitions. Second operand has 2023 states, 2023 states have (on average 1.4794859120118635) internal successors, (2993), 2022 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,826 INFO L93 Difference]: Finished difference Result 2023 states and 2993 transitions. [2022-02-21 04:23:19,826 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2993 transitions. [2022-02-21 04:23:19,828 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:19,828 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:19,831 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4794859120118635) internal successors, (2993), 2022 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2993 transitions. [2022-02-21 04:23:19,833 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4794859120118635) internal successors, (2993), 2022 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2993 transitions. [2022-02-21 04:23:19,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,988 INFO L93 Difference]: Finished difference Result 2023 states and 2993 transitions. [2022-02-21 04:23:19,988 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2993 transitions. [2022-02-21 04:23:19,989 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:19,989 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:19,989 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:19,990 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:19,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4794859120118635) internal successors, (2993), 2022 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2993 transitions. [2022-02-21 04:23:20,132 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2022-02-21 04:23:20,133 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2022-02-21 04:23:20,133 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:23:20,133 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2993 transitions. [2022-02-21 04:23:20,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:20,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:20,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:20,140 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:20,140 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:20,140 INFO L791 eck$LassoCheckResult]: Stem: 29299#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 29300#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 30298#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30299#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30384#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 29763#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29232#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29233#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30049#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 30050#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 30150#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 30151#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29004#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29005#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30180#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29540#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29541#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30101#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29442#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29443#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 30385#L1291-2 assume !(0 == ~T1_E~0); 30383#L1296-1 assume !(0 == ~T2_E~0); 29599#L1301-1 assume !(0 == ~T3_E~0); 29600#L1306-1 assume !(0 == ~T4_E~0); 30109#L1311-1 assume !(0 == ~T5_E~0); 28847#L1316-1 assume !(0 == ~T6_E~0); 28848#L1321-1 assume !(0 == ~T7_E~0); 29612#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28675#L1331-1 assume !(0 == ~T9_E~0); 28374#L1336-1 assume !(0 == ~T10_E~0); 28375#L1341-1 assume !(0 == ~T11_E~0); 28455#L1346-1 assume !(0 == ~T12_E~0); 28456#L1351-1 assume !(0 == ~T13_E~0); 28796#L1356-1 assume !(0 == ~E_M~0); 28797#L1361-1 assume !(0 == ~E_1~0); 30324#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 28837#L1371-1 assume !(0 == ~E_3~0); 28838#L1376-1 assume !(0 == ~E_4~0); 29659#L1381-1 assume !(0 == ~E_5~0); 29660#L1386-1 assume !(0 == ~E_6~0); 30354#L1391-1 assume !(0 == ~E_7~0); 30372#L1396-1 assume !(0 == ~E_8~0); 29572#L1401-1 assume !(0 == ~E_9~0); 29573#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 29851#L1411-1 assume !(0 == ~E_11~0); 29852#L1416-1 assume !(0 == ~E_12~0); 29484#L1421-1 assume !(0 == ~E_13~0); 29027#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29028#L640 assume !(1 == ~m_pc~0); 29537#L640-2 is_master_triggered_~__retres1~0#1 := 0; 29536#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29628#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29522#L1603 assume !(0 != activate_threads_~tmp~1#1); 29523#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29157#L659 assume 1 == ~t1_pc~0; 29158#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29263#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30209#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29283#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 29284#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29297#L678 assume 1 == ~t2_pc~0; 30251#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30252#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30351#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29395#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 29396#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29517#L697 assume !(1 == ~t3_pc~0); 29518#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29640#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29448#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29427#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29428#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30288#L716 assume 1 == ~t4_pc~0; 30274#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29138#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29139#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28638#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 28639#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29930#L735 assume !(1 == ~t5_pc~0); 28599#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28600#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29050#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29957#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 29593#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29594#L754 assume 1 == ~t6_pc~0; 29347#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29245#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29246#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29219#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 29220#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30040#L773 assume !(1 == ~t7_pc~0); 28800#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28799#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29629#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29601#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 29602#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29649#L792 assume 1 == ~t8_pc~0; 29822#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30154#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29643#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29596#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 29520#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29521#L811 assume 1 == ~t9_pc~0; 29725#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30191#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30067#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29721#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 29533#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29534#L830 assume !(1 == ~t10_pc~0); 29255#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28779#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28472#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28473#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28760#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30058#L849 assume 1 == ~t11_pc~0; 30059#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28575#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28576#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29165#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 29964#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29965#L868 assume !(1 == ~t12_pc~0); 29380#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29379#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29174#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29175#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 28811#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28812#L887 assume 1 == ~t13_pc~0; 29979#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29421#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29422#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29858#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 28515#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28516#L1439 assume !(1 == ~M_E~0); 29589#L1439-2 assume !(1 == ~T1_E~0); 28687#L1444-1 assume !(1 == ~T2_E~0); 28688#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29161#L1454-1 assume !(1 == ~T4_E~0); 29162#L1459-1 assume !(1 == ~T5_E~0); 29718#L1464-1 assume !(1 == ~T6_E~0); 29719#L1469-1 assume !(1 == ~T7_E~0); 29791#L1474-1 assume !(1 == ~T8_E~0); 29485#L1479-1 assume !(1 == ~T9_E~0); 29486#L1484-1 assume !(1 == ~T10_E~0); 29722#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29368#L1494-1 assume !(1 == ~T12_E~0); 29369#L1499-1 assume !(1 == ~T13_E~0); 29561#L1504-1 assume !(1 == ~E_M~0); 29562#L1509-1 assume !(1 == ~E_1~0); 30137#L1514-1 assume !(1 == ~E_2~0); 29824#L1519-1 assume !(1 == ~E_3~0); 29825#L1524-1 assume !(1 == ~E_4~0); 30337#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30338#L1534-1 assume !(1 == ~E_6~0); 28508#L1539-1 assume !(1 == ~E_7~0); 28509#L1544-1 assume !(1 == ~E_8~0); 28923#L1549-1 assume !(1 == ~E_9~0); 30312#L1554-1 assume !(1 == ~E_10~0); 30308#L1559-1 assume !(1 == ~E_11~0); 30175#L1564-1 assume !(1 == ~E_12~0); 30176#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30333#L1574-1 assume { :end_inline_reset_delta_events } true; 28685#L1940-2 [2022-02-21 04:23:20,141 INFO L793 eck$LassoCheckResult]: Loop: 28685#L1940-2 assume !false; 28686#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28968#L1266 assume !false; 29987#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29216#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28949#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29340#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29341#L1079 assume !(0 != eval_~tmp~0#1); 29302#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29303#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29907#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29792#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29793#L1296-3 assume !(0 == ~T2_E~0); 30365#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30319#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29450#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28726#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28727#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28827#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29584#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29833#L1336-3 assume !(0 == ~T10_E~0); 29834#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29154#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29134#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29079#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29080#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29641#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28430#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28431#L1376-3 assume !(0 == ~E_4~0); 30160#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30020#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30021#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30183#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30184#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28793#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28647#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28648#L1416-3 assume !(0 == ~E_12~0); 29309#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29310#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29417#L640-45 assume !(1 == ~m_pc~0); 29418#L640-47 is_master_triggered_~__retres1~0#1 := 0; 28884#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28885#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28424#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28425#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28523#L659-45 assume 1 == ~t1_pc~0; 28524#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28963#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29922#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29923#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29944#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29945#L678-45 assume 1 == ~t2_pc~0; 29888#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29423#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29424#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29576#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30201#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30318#L697-45 assume 1 == ~t3_pc~0; 29681#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29682#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30270#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29840#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29841#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29871#L716-45 assume !(1 == ~t4_pc~0); 29504#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 29503#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30053#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29508#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29509#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29171#L735-45 assume 1 == ~t5_pc~0; 29172#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29715#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30277#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30278#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30336#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30331#L754-45 assume !(1 == ~t6_pc~0); 29665#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 29664#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29093#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29094#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29667#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29399#L773-45 assume 1 == ~t7_pc~0; 29400#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28957#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29877#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30159#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 29405#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29075#L792-45 assume 1 == ~t8_pc~0; 29076#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30105#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28678#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28537#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28538#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29033#L811-45 assume 1 == ~t9_pc~0; 28822#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28824#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30032#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29867#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29476#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29268#L830-45 assume !(1 == ~t10_pc~0); 28465#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 28466#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29588#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28698#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28699#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28444#L849-45 assume !(1 == ~t11_pc~0); 28445#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 28904#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28535#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28432#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28433#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28691#L868-45 assume 1 == ~t12_pc~0; 28692#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28631#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28632#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29970#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30221#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30222#L887-45 assume 1 == ~t13_pc~0; 30052#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 28701#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29983#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30328#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 28663#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28664#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29971#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28683#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28684#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28841#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29772#L1459-3 assume !(1 == ~T5_E~0); 29773#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30224#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30163#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30164#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30225#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29457#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29458#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30094#L1499-3 assume !(1 == ~T13_E~0); 29733#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29734#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30172#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30202#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29376#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29377#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30244#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29644#L1539-3 assume !(1 == ~E_7~0); 29120#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29121#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29616#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28737#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28738#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29872#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29873#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28614#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28385#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28660#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 28621#L1959 assume !(0 == start_simulation_~tmp~3#1); 28623#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28655#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28605#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29914#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 30035#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30242#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30256#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30257#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 28685#L1940-2 [2022-02-21 04:23:20,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:20,142 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2022-02-21 04:23:20,142 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:20,142 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647174044] [2022-02-21 04:23:20,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:20,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:20,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:20,171 INFO L290 TraceCheckUtils]: 0: Hoare triple {34444#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {34444#true} is VALID [2022-02-21 04:23:20,172 INFO L290 TraceCheckUtils]: 1: Hoare triple {34444#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {34446#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:20,172 INFO L290 TraceCheckUtils]: 2: Hoare triple {34446#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {34446#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:20,173 INFO L290 TraceCheckUtils]: 3: Hoare triple {34446#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {34446#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:20,173 INFO L290 TraceCheckUtils]: 4: Hoare triple {34446#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {34446#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:20,173 INFO L290 TraceCheckUtils]: 5: Hoare triple {34446#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {34446#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:20,174 INFO L290 TraceCheckUtils]: 6: Hoare triple {34446#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {34446#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:20,174 INFO L290 TraceCheckUtils]: 7: Hoare triple {34446#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {34446#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:20,174 INFO L290 TraceCheckUtils]: 8: Hoare triple {34446#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,175 INFO L290 TraceCheckUtils]: 9: Hoare triple {34445#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,175 INFO L290 TraceCheckUtils]: 10: Hoare triple {34445#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,175 INFO L290 TraceCheckUtils]: 11: Hoare triple {34445#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,175 INFO L290 TraceCheckUtils]: 12: Hoare triple {34445#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,175 INFO L290 TraceCheckUtils]: 13: Hoare triple {34445#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {34445#false} is VALID [2022-02-21 04:23:20,175 INFO L290 TraceCheckUtils]: 14: Hoare triple {34445#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,175 INFO L290 TraceCheckUtils]: 15: Hoare triple {34445#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,176 INFO L290 TraceCheckUtils]: 16: Hoare triple {34445#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,176 INFO L290 TraceCheckUtils]: 17: Hoare triple {34445#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,176 INFO L290 TraceCheckUtils]: 18: Hoare triple {34445#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {34445#false} is VALID [2022-02-21 04:23:20,176 INFO L290 TraceCheckUtils]: 19: Hoare triple {34445#false} assume 0 == ~M_E~0;~M_E~0 := 1; {34445#false} is VALID [2022-02-21 04:23:20,176 INFO L290 TraceCheckUtils]: 20: Hoare triple {34445#false} assume !(0 == ~T1_E~0); {34445#false} is VALID [2022-02-21 04:23:20,176 INFO L290 TraceCheckUtils]: 21: Hoare triple {34445#false} assume !(0 == ~T2_E~0); {34445#false} is VALID [2022-02-21 04:23:20,176 INFO L290 TraceCheckUtils]: 22: Hoare triple {34445#false} assume !(0 == ~T3_E~0); {34445#false} is VALID [2022-02-21 04:23:20,177 INFO L290 TraceCheckUtils]: 23: Hoare triple {34445#false} assume !(0 == ~T4_E~0); {34445#false} is VALID [2022-02-21 04:23:20,177 INFO L290 TraceCheckUtils]: 24: Hoare triple {34445#false} assume !(0 == ~T5_E~0); {34445#false} is VALID [2022-02-21 04:23:20,177 INFO L290 TraceCheckUtils]: 25: Hoare triple {34445#false} assume !(0 == ~T6_E~0); {34445#false} is VALID [2022-02-21 04:23:20,177 INFO L290 TraceCheckUtils]: 26: Hoare triple {34445#false} assume !(0 == ~T7_E~0); {34445#false} is VALID [2022-02-21 04:23:20,177 INFO L290 TraceCheckUtils]: 27: Hoare triple {34445#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {34445#false} is VALID [2022-02-21 04:23:20,177 INFO L290 TraceCheckUtils]: 28: Hoare triple {34445#false} assume !(0 == ~T9_E~0); {34445#false} is VALID [2022-02-21 04:23:20,177 INFO L290 TraceCheckUtils]: 29: Hoare triple {34445#false} assume !(0 == ~T10_E~0); {34445#false} is VALID [2022-02-21 04:23:20,178 INFO L290 TraceCheckUtils]: 30: Hoare triple {34445#false} assume !(0 == ~T11_E~0); {34445#false} is VALID [2022-02-21 04:23:20,178 INFO L290 TraceCheckUtils]: 31: Hoare triple {34445#false} assume !(0 == ~T12_E~0); {34445#false} is VALID [2022-02-21 04:23:20,178 INFO L290 TraceCheckUtils]: 32: Hoare triple {34445#false} assume !(0 == ~T13_E~0); {34445#false} is VALID [2022-02-21 04:23:20,178 INFO L290 TraceCheckUtils]: 33: Hoare triple {34445#false} assume !(0 == ~E_M~0); {34445#false} is VALID [2022-02-21 04:23:20,178 INFO L290 TraceCheckUtils]: 34: Hoare triple {34445#false} assume !(0 == ~E_1~0); {34445#false} is VALID [2022-02-21 04:23:20,178 INFO L290 TraceCheckUtils]: 35: Hoare triple {34445#false} assume 0 == ~E_2~0;~E_2~0 := 1; {34445#false} is VALID [2022-02-21 04:23:20,178 INFO L290 TraceCheckUtils]: 36: Hoare triple {34445#false} assume !(0 == ~E_3~0); {34445#false} is VALID [2022-02-21 04:23:20,179 INFO L290 TraceCheckUtils]: 37: Hoare triple {34445#false} assume !(0 == ~E_4~0); {34445#false} is VALID [2022-02-21 04:23:20,179 INFO L290 TraceCheckUtils]: 38: Hoare triple {34445#false} assume !(0 == ~E_5~0); {34445#false} is VALID [2022-02-21 04:23:20,179 INFO L290 TraceCheckUtils]: 39: Hoare triple {34445#false} assume !(0 == ~E_6~0); {34445#false} is VALID [2022-02-21 04:23:20,179 INFO L290 TraceCheckUtils]: 40: Hoare triple {34445#false} assume !(0 == ~E_7~0); {34445#false} is VALID [2022-02-21 04:23:20,179 INFO L290 TraceCheckUtils]: 41: Hoare triple {34445#false} assume !(0 == ~E_8~0); {34445#false} is VALID [2022-02-21 04:23:20,179 INFO L290 TraceCheckUtils]: 42: Hoare triple {34445#false} assume !(0 == ~E_9~0); {34445#false} is VALID [2022-02-21 04:23:20,179 INFO L290 TraceCheckUtils]: 43: Hoare triple {34445#false} assume 0 == ~E_10~0;~E_10~0 := 1; {34445#false} is VALID [2022-02-21 04:23:20,180 INFO L290 TraceCheckUtils]: 44: Hoare triple {34445#false} assume !(0 == ~E_11~0); {34445#false} is VALID [2022-02-21 04:23:20,180 INFO L290 TraceCheckUtils]: 45: Hoare triple {34445#false} assume !(0 == ~E_12~0); {34445#false} is VALID [2022-02-21 04:23:20,180 INFO L290 TraceCheckUtils]: 46: Hoare triple {34445#false} assume !(0 == ~E_13~0); {34445#false} is VALID [2022-02-21 04:23:20,180 INFO L290 TraceCheckUtils]: 47: Hoare triple {34445#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34445#false} is VALID [2022-02-21 04:23:20,180 INFO L290 TraceCheckUtils]: 48: Hoare triple {34445#false} assume !(1 == ~m_pc~0); {34445#false} is VALID [2022-02-21 04:23:20,180 INFO L290 TraceCheckUtils]: 49: Hoare triple {34445#false} is_master_triggered_~__retres1~0#1 := 0; {34445#false} is VALID [2022-02-21 04:23:20,180 INFO L290 TraceCheckUtils]: 50: Hoare triple {34445#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34445#false} is VALID [2022-02-21 04:23:20,181 INFO L290 TraceCheckUtils]: 51: Hoare triple {34445#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34445#false} is VALID [2022-02-21 04:23:20,181 INFO L290 TraceCheckUtils]: 52: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp~1#1); {34445#false} is VALID [2022-02-21 04:23:20,181 INFO L290 TraceCheckUtils]: 53: Hoare triple {34445#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34445#false} is VALID [2022-02-21 04:23:20,181 INFO L290 TraceCheckUtils]: 54: Hoare triple {34445#false} assume 1 == ~t1_pc~0; {34445#false} is VALID [2022-02-21 04:23:20,181 INFO L290 TraceCheckUtils]: 55: Hoare triple {34445#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34445#false} is VALID [2022-02-21 04:23:20,181 INFO L290 TraceCheckUtils]: 56: Hoare triple {34445#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34445#false} is VALID [2022-02-21 04:23:20,181 INFO L290 TraceCheckUtils]: 57: Hoare triple {34445#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34445#false} is VALID [2022-02-21 04:23:20,182 INFO L290 TraceCheckUtils]: 58: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___0~0#1); {34445#false} is VALID [2022-02-21 04:23:20,182 INFO L290 TraceCheckUtils]: 59: Hoare triple {34445#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34445#false} is VALID [2022-02-21 04:23:20,182 INFO L290 TraceCheckUtils]: 60: Hoare triple {34445#false} assume 1 == ~t2_pc~0; {34445#false} is VALID [2022-02-21 04:23:20,182 INFO L290 TraceCheckUtils]: 61: Hoare triple {34445#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34445#false} is VALID [2022-02-21 04:23:20,182 INFO L290 TraceCheckUtils]: 62: Hoare triple {34445#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34445#false} is VALID [2022-02-21 04:23:20,182 INFO L290 TraceCheckUtils]: 63: Hoare triple {34445#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34445#false} is VALID [2022-02-21 04:23:20,182 INFO L290 TraceCheckUtils]: 64: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___1~0#1); {34445#false} is VALID [2022-02-21 04:23:20,183 INFO L290 TraceCheckUtils]: 65: Hoare triple {34445#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34445#false} is VALID [2022-02-21 04:23:20,183 INFO L290 TraceCheckUtils]: 66: Hoare triple {34445#false} assume !(1 == ~t3_pc~0); {34445#false} is VALID [2022-02-21 04:23:20,183 INFO L290 TraceCheckUtils]: 67: Hoare triple {34445#false} is_transmit3_triggered_~__retres1~3#1 := 0; {34445#false} is VALID [2022-02-21 04:23:20,183 INFO L290 TraceCheckUtils]: 68: Hoare triple {34445#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34445#false} is VALID [2022-02-21 04:23:20,183 INFO L290 TraceCheckUtils]: 69: Hoare triple {34445#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34445#false} is VALID [2022-02-21 04:23:20,183 INFO L290 TraceCheckUtils]: 70: Hoare triple {34445#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34445#false} is VALID [2022-02-21 04:23:20,184 INFO L290 TraceCheckUtils]: 71: Hoare triple {34445#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34445#false} is VALID [2022-02-21 04:23:20,184 INFO L290 TraceCheckUtils]: 72: Hoare triple {34445#false} assume 1 == ~t4_pc~0; {34445#false} is VALID [2022-02-21 04:23:20,184 INFO L290 TraceCheckUtils]: 73: Hoare triple {34445#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34445#false} is VALID [2022-02-21 04:23:20,184 INFO L290 TraceCheckUtils]: 74: Hoare triple {34445#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34445#false} is VALID [2022-02-21 04:23:20,184 INFO L290 TraceCheckUtils]: 75: Hoare triple {34445#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34445#false} is VALID [2022-02-21 04:23:20,184 INFO L290 TraceCheckUtils]: 76: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___3~0#1); {34445#false} is VALID [2022-02-21 04:23:20,184 INFO L290 TraceCheckUtils]: 77: Hoare triple {34445#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34445#false} is VALID [2022-02-21 04:23:20,185 INFO L290 TraceCheckUtils]: 78: Hoare triple {34445#false} assume !(1 == ~t5_pc~0); {34445#false} is VALID [2022-02-21 04:23:20,185 INFO L290 TraceCheckUtils]: 79: Hoare triple {34445#false} is_transmit5_triggered_~__retres1~5#1 := 0; {34445#false} is VALID [2022-02-21 04:23:20,185 INFO L290 TraceCheckUtils]: 80: Hoare triple {34445#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34445#false} is VALID [2022-02-21 04:23:20,185 INFO L290 TraceCheckUtils]: 81: Hoare triple {34445#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34445#false} is VALID [2022-02-21 04:23:20,185 INFO L290 TraceCheckUtils]: 82: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___4~0#1); {34445#false} is VALID [2022-02-21 04:23:20,185 INFO L290 TraceCheckUtils]: 83: Hoare triple {34445#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34445#false} is VALID [2022-02-21 04:23:20,185 INFO L290 TraceCheckUtils]: 84: Hoare triple {34445#false} assume 1 == ~t6_pc~0; {34445#false} is VALID [2022-02-21 04:23:20,186 INFO L290 TraceCheckUtils]: 85: Hoare triple {34445#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {34445#false} is VALID [2022-02-21 04:23:20,186 INFO L290 TraceCheckUtils]: 86: Hoare triple {34445#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34445#false} is VALID [2022-02-21 04:23:20,186 INFO L290 TraceCheckUtils]: 87: Hoare triple {34445#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34445#false} is VALID [2022-02-21 04:23:20,186 INFO L290 TraceCheckUtils]: 88: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___5~0#1); {34445#false} is VALID [2022-02-21 04:23:20,186 INFO L290 TraceCheckUtils]: 89: Hoare triple {34445#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34445#false} is VALID [2022-02-21 04:23:20,186 INFO L290 TraceCheckUtils]: 90: Hoare triple {34445#false} assume !(1 == ~t7_pc~0); {34445#false} is VALID [2022-02-21 04:23:20,186 INFO L290 TraceCheckUtils]: 91: Hoare triple {34445#false} is_transmit7_triggered_~__retres1~7#1 := 0; {34445#false} is VALID [2022-02-21 04:23:20,187 INFO L290 TraceCheckUtils]: 92: Hoare triple {34445#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34445#false} is VALID [2022-02-21 04:23:20,187 INFO L290 TraceCheckUtils]: 93: Hoare triple {34445#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {34445#false} is VALID [2022-02-21 04:23:20,187 INFO L290 TraceCheckUtils]: 94: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___6~0#1); {34445#false} is VALID [2022-02-21 04:23:20,187 INFO L290 TraceCheckUtils]: 95: Hoare triple {34445#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34445#false} is VALID [2022-02-21 04:23:20,187 INFO L290 TraceCheckUtils]: 96: Hoare triple {34445#false} assume 1 == ~t8_pc~0; {34445#false} is VALID [2022-02-21 04:23:20,187 INFO L290 TraceCheckUtils]: 97: Hoare triple {34445#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {34445#false} is VALID [2022-02-21 04:23:20,187 INFO L290 TraceCheckUtils]: 98: Hoare triple {34445#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34445#false} is VALID [2022-02-21 04:23:20,188 INFO L290 TraceCheckUtils]: 99: Hoare triple {34445#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {34445#false} is VALID [2022-02-21 04:23:20,188 INFO L290 TraceCheckUtils]: 100: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___7~0#1); {34445#false} is VALID [2022-02-21 04:23:20,188 INFO L290 TraceCheckUtils]: 101: Hoare triple {34445#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34445#false} is VALID [2022-02-21 04:23:20,188 INFO L290 TraceCheckUtils]: 102: Hoare triple {34445#false} assume 1 == ~t9_pc~0; {34445#false} is VALID [2022-02-21 04:23:20,188 INFO L290 TraceCheckUtils]: 103: Hoare triple {34445#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {34445#false} is VALID [2022-02-21 04:23:20,188 INFO L290 TraceCheckUtils]: 104: Hoare triple {34445#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34445#false} is VALID [2022-02-21 04:23:20,188 INFO L290 TraceCheckUtils]: 105: Hoare triple {34445#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {34445#false} is VALID [2022-02-21 04:23:20,189 INFO L290 TraceCheckUtils]: 106: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___8~0#1); {34445#false} is VALID [2022-02-21 04:23:20,189 INFO L290 TraceCheckUtils]: 107: Hoare triple {34445#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34445#false} is VALID [2022-02-21 04:23:20,189 INFO L290 TraceCheckUtils]: 108: Hoare triple {34445#false} assume !(1 == ~t10_pc~0); {34445#false} is VALID [2022-02-21 04:23:20,189 INFO L290 TraceCheckUtils]: 109: Hoare triple {34445#false} is_transmit10_triggered_~__retres1~10#1 := 0; {34445#false} is VALID [2022-02-21 04:23:20,189 INFO L290 TraceCheckUtils]: 110: Hoare triple {34445#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34445#false} is VALID [2022-02-21 04:23:20,189 INFO L290 TraceCheckUtils]: 111: Hoare triple {34445#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {34445#false} is VALID [2022-02-21 04:23:20,189 INFO L290 TraceCheckUtils]: 112: Hoare triple {34445#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {34445#false} is VALID [2022-02-21 04:23:20,190 INFO L290 TraceCheckUtils]: 113: Hoare triple {34445#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {34445#false} is VALID [2022-02-21 04:23:20,190 INFO L290 TraceCheckUtils]: 114: Hoare triple {34445#false} assume 1 == ~t11_pc~0; {34445#false} is VALID [2022-02-21 04:23:20,190 INFO L290 TraceCheckUtils]: 115: Hoare triple {34445#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {34445#false} is VALID [2022-02-21 04:23:20,190 INFO L290 TraceCheckUtils]: 116: Hoare triple {34445#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {34445#false} is VALID [2022-02-21 04:23:20,190 INFO L290 TraceCheckUtils]: 117: Hoare triple {34445#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {34445#false} is VALID [2022-02-21 04:23:20,190 INFO L290 TraceCheckUtils]: 118: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___10~0#1); {34445#false} is VALID [2022-02-21 04:23:20,190 INFO L290 TraceCheckUtils]: 119: Hoare triple {34445#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {34445#false} is VALID [2022-02-21 04:23:20,191 INFO L290 TraceCheckUtils]: 120: Hoare triple {34445#false} assume !(1 == ~t12_pc~0); {34445#false} is VALID [2022-02-21 04:23:20,191 INFO L290 TraceCheckUtils]: 121: Hoare triple {34445#false} is_transmit12_triggered_~__retres1~12#1 := 0; {34445#false} is VALID [2022-02-21 04:23:20,191 INFO L290 TraceCheckUtils]: 122: Hoare triple {34445#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {34445#false} is VALID [2022-02-21 04:23:20,191 INFO L290 TraceCheckUtils]: 123: Hoare triple {34445#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {34445#false} is VALID [2022-02-21 04:23:20,191 INFO L290 TraceCheckUtils]: 124: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___11~0#1); {34445#false} is VALID [2022-02-21 04:23:20,191 INFO L290 TraceCheckUtils]: 125: Hoare triple {34445#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {34445#false} is VALID [2022-02-21 04:23:20,191 INFO L290 TraceCheckUtils]: 126: Hoare triple {34445#false} assume 1 == ~t13_pc~0; {34445#false} is VALID [2022-02-21 04:23:20,192 INFO L290 TraceCheckUtils]: 127: Hoare triple {34445#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {34445#false} is VALID [2022-02-21 04:23:20,192 INFO L290 TraceCheckUtils]: 128: Hoare triple {34445#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {34445#false} is VALID [2022-02-21 04:23:20,192 INFO L290 TraceCheckUtils]: 129: Hoare triple {34445#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {34445#false} is VALID [2022-02-21 04:23:20,192 INFO L290 TraceCheckUtils]: 130: Hoare triple {34445#false} assume !(0 != activate_threads_~tmp___12~0#1); {34445#false} is VALID [2022-02-21 04:23:20,192 INFO L290 TraceCheckUtils]: 131: Hoare triple {34445#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34445#false} is VALID [2022-02-21 04:23:20,192 INFO L290 TraceCheckUtils]: 132: Hoare triple {34445#false} assume !(1 == ~M_E~0); {34445#false} is VALID [2022-02-21 04:23:20,192 INFO L290 TraceCheckUtils]: 133: Hoare triple {34445#false} assume !(1 == ~T1_E~0); {34445#false} is VALID [2022-02-21 04:23:20,193 INFO L290 TraceCheckUtils]: 134: Hoare triple {34445#false} assume !(1 == ~T2_E~0); {34445#false} is VALID [2022-02-21 04:23:20,193 INFO L290 TraceCheckUtils]: 135: Hoare triple {34445#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,193 INFO L290 TraceCheckUtils]: 136: Hoare triple {34445#false} assume !(1 == ~T4_E~0); {34445#false} is VALID [2022-02-21 04:23:20,193 INFO L290 TraceCheckUtils]: 137: Hoare triple {34445#false} assume !(1 == ~T5_E~0); {34445#false} is VALID [2022-02-21 04:23:20,193 INFO L290 TraceCheckUtils]: 138: Hoare triple {34445#false} assume !(1 == ~T6_E~0); {34445#false} is VALID [2022-02-21 04:23:20,193 INFO L290 TraceCheckUtils]: 139: Hoare triple {34445#false} assume !(1 == ~T7_E~0); {34445#false} is VALID [2022-02-21 04:23:20,193 INFO L290 TraceCheckUtils]: 140: Hoare triple {34445#false} assume !(1 == ~T8_E~0); {34445#false} is VALID [2022-02-21 04:23:20,194 INFO L290 TraceCheckUtils]: 141: Hoare triple {34445#false} assume !(1 == ~T9_E~0); {34445#false} is VALID [2022-02-21 04:23:20,194 INFO L290 TraceCheckUtils]: 142: Hoare triple {34445#false} assume !(1 == ~T10_E~0); {34445#false} is VALID [2022-02-21 04:23:20,194 INFO L290 TraceCheckUtils]: 143: Hoare triple {34445#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,194 INFO L290 TraceCheckUtils]: 144: Hoare triple {34445#false} assume !(1 == ~T12_E~0); {34445#false} is VALID [2022-02-21 04:23:20,194 INFO L290 TraceCheckUtils]: 145: Hoare triple {34445#false} assume !(1 == ~T13_E~0); {34445#false} is VALID [2022-02-21 04:23:20,194 INFO L290 TraceCheckUtils]: 146: Hoare triple {34445#false} assume !(1 == ~E_M~0); {34445#false} is VALID [2022-02-21 04:23:20,194 INFO L290 TraceCheckUtils]: 147: Hoare triple {34445#false} assume !(1 == ~E_1~0); {34445#false} is VALID [2022-02-21 04:23:20,195 INFO L290 TraceCheckUtils]: 148: Hoare triple {34445#false} assume !(1 == ~E_2~0); {34445#false} is VALID [2022-02-21 04:23:20,195 INFO L290 TraceCheckUtils]: 149: Hoare triple {34445#false} assume !(1 == ~E_3~0); {34445#false} is VALID [2022-02-21 04:23:20,195 INFO L290 TraceCheckUtils]: 150: Hoare triple {34445#false} assume !(1 == ~E_4~0); {34445#false} is VALID [2022-02-21 04:23:20,195 INFO L290 TraceCheckUtils]: 151: Hoare triple {34445#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,195 INFO L290 TraceCheckUtils]: 152: Hoare triple {34445#false} assume !(1 == ~E_6~0); {34445#false} is VALID [2022-02-21 04:23:20,195 INFO L290 TraceCheckUtils]: 153: Hoare triple {34445#false} assume !(1 == ~E_7~0); {34445#false} is VALID [2022-02-21 04:23:20,195 INFO L290 TraceCheckUtils]: 154: Hoare triple {34445#false} assume !(1 == ~E_8~0); {34445#false} is VALID [2022-02-21 04:23:20,196 INFO L290 TraceCheckUtils]: 155: Hoare triple {34445#false} assume !(1 == ~E_9~0); {34445#false} is VALID [2022-02-21 04:23:20,196 INFO L290 TraceCheckUtils]: 156: Hoare triple {34445#false} assume !(1 == ~E_10~0); {34445#false} is VALID [2022-02-21 04:23:20,196 INFO L290 TraceCheckUtils]: 157: Hoare triple {34445#false} assume !(1 == ~E_11~0); {34445#false} is VALID [2022-02-21 04:23:20,196 INFO L290 TraceCheckUtils]: 158: Hoare triple {34445#false} assume !(1 == ~E_12~0); {34445#false} is VALID [2022-02-21 04:23:20,196 INFO L290 TraceCheckUtils]: 159: Hoare triple {34445#false} assume 1 == ~E_13~0;~E_13~0 := 2; {34445#false} is VALID [2022-02-21 04:23:20,196 INFO L290 TraceCheckUtils]: 160: Hoare triple {34445#false} assume { :end_inline_reset_delta_events } true; {34445#false} is VALID [2022-02-21 04:23:20,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:20,197 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:20,197 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647174044] [2022-02-21 04:23:20,197 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [647174044] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:20,197 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:20,198 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:20,198 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067843692] [2022-02-21 04:23:20,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:20,198 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:20,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:20,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1107441823, now seen corresponding path program 1 times [2022-02-21 04:23:20,199 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:20,199 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523181365] [2022-02-21 04:23:20,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:20,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:20,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:20,246 INFO L290 TraceCheckUtils]: 0: Hoare triple {34447#true} assume !false; {34447#true} is VALID [2022-02-21 04:23:20,246 INFO L290 TraceCheckUtils]: 1: Hoare triple {34447#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {34447#true} is VALID [2022-02-21 04:23:20,246 INFO L290 TraceCheckUtils]: 2: Hoare triple {34447#true} assume !false; {34447#true} is VALID [2022-02-21 04:23:20,246 INFO L290 TraceCheckUtils]: 3: Hoare triple {34447#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {34447#true} is VALID [2022-02-21 04:23:20,247 INFO L290 TraceCheckUtils]: 4: Hoare triple {34447#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {34447#true} is VALID [2022-02-21 04:23:20,247 INFO L290 TraceCheckUtils]: 5: Hoare triple {34447#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {34447#true} is VALID [2022-02-21 04:23:20,247 INFO L290 TraceCheckUtils]: 6: Hoare triple {34447#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {34447#true} is VALID [2022-02-21 04:23:20,247 INFO L290 TraceCheckUtils]: 7: Hoare triple {34447#true} assume !(0 != eval_~tmp~0#1); {34447#true} is VALID [2022-02-21 04:23:20,247 INFO L290 TraceCheckUtils]: 8: Hoare triple {34447#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {34447#true} is VALID [2022-02-21 04:23:20,247 INFO L290 TraceCheckUtils]: 9: Hoare triple {34447#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {34447#true} is VALID [2022-02-21 04:23:20,248 INFO L290 TraceCheckUtils]: 10: Hoare triple {34447#true} assume 0 == ~M_E~0;~M_E~0 := 1; {34447#true} is VALID [2022-02-21 04:23:20,248 INFO L290 TraceCheckUtils]: 11: Hoare triple {34447#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {34447#true} is VALID [2022-02-21 04:23:20,248 INFO L290 TraceCheckUtils]: 12: Hoare triple {34447#true} assume !(0 == ~T2_E~0); {34447#true} is VALID [2022-02-21 04:23:20,248 INFO L290 TraceCheckUtils]: 13: Hoare triple {34447#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34447#true} is VALID [2022-02-21 04:23:20,248 INFO L290 TraceCheckUtils]: 14: Hoare triple {34447#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {34447#true} is VALID [2022-02-21 04:23:20,248 INFO L290 TraceCheckUtils]: 15: Hoare triple {34447#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,249 INFO L290 TraceCheckUtils]: 16: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,249 INFO L290 TraceCheckUtils]: 17: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,250 INFO L290 TraceCheckUtils]: 18: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,250 INFO L290 TraceCheckUtils]: 19: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,250 INFO L290 TraceCheckUtils]: 20: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,251 INFO L290 TraceCheckUtils]: 21: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,251 INFO L290 TraceCheckUtils]: 22: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,252 INFO L290 TraceCheckUtils]: 23: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,252 INFO L290 TraceCheckUtils]: 24: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,252 INFO L290 TraceCheckUtils]: 25: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,253 INFO L290 TraceCheckUtils]: 26: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,253 INFO L290 TraceCheckUtils]: 27: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,253 INFO L290 TraceCheckUtils]: 28: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,254 INFO L290 TraceCheckUtils]: 29: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,254 INFO L290 TraceCheckUtils]: 30: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,255 INFO L290 TraceCheckUtils]: 31: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,255 INFO L290 TraceCheckUtils]: 32: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,255 INFO L290 TraceCheckUtils]: 33: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,256 INFO L290 TraceCheckUtils]: 34: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,256 INFO L290 TraceCheckUtils]: 35: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,257 INFO L290 TraceCheckUtils]: 36: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,257 INFO L290 TraceCheckUtils]: 37: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,257 INFO L290 TraceCheckUtils]: 38: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,258 INFO L290 TraceCheckUtils]: 39: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,258 INFO L290 TraceCheckUtils]: 40: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,258 INFO L290 TraceCheckUtils]: 41: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,259 INFO L290 TraceCheckUtils]: 42: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,259 INFO L290 TraceCheckUtils]: 43: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,260 INFO L290 TraceCheckUtils]: 44: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,260 INFO L290 TraceCheckUtils]: 45: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,260 INFO L290 TraceCheckUtils]: 46: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,261 INFO L290 TraceCheckUtils]: 47: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,261 INFO L290 TraceCheckUtils]: 48: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,262 INFO L290 TraceCheckUtils]: 49: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,262 INFO L290 TraceCheckUtils]: 50: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,262 INFO L290 TraceCheckUtils]: 51: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,263 INFO L290 TraceCheckUtils]: 52: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,263 INFO L290 TraceCheckUtils]: 53: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,263 INFO L290 TraceCheckUtils]: 54: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,264 INFO L290 TraceCheckUtils]: 55: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,264 INFO L290 TraceCheckUtils]: 56: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,265 INFO L290 TraceCheckUtils]: 57: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,266 INFO L290 TraceCheckUtils]: 58: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,266 INFO L290 TraceCheckUtils]: 59: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,266 INFO L290 TraceCheckUtils]: 60: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,267 INFO L290 TraceCheckUtils]: 61: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,267 INFO L290 TraceCheckUtils]: 62: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,268 INFO L290 TraceCheckUtils]: 63: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,268 INFO L290 TraceCheckUtils]: 64: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,268 INFO L290 TraceCheckUtils]: 65: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,269 INFO L290 TraceCheckUtils]: 66: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,269 INFO L290 TraceCheckUtils]: 67: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,269 INFO L290 TraceCheckUtils]: 68: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,270 INFO L290 TraceCheckUtils]: 69: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,270 INFO L290 TraceCheckUtils]: 70: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,271 INFO L290 TraceCheckUtils]: 71: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,271 INFO L290 TraceCheckUtils]: 72: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,271 INFO L290 TraceCheckUtils]: 73: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,272 INFO L290 TraceCheckUtils]: 74: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,272 INFO L290 TraceCheckUtils]: 75: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,273 INFO L290 TraceCheckUtils]: 76: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,273 INFO L290 TraceCheckUtils]: 77: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,273 INFO L290 TraceCheckUtils]: 78: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,274 INFO L290 TraceCheckUtils]: 79: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,274 INFO L290 TraceCheckUtils]: 80: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,274 INFO L290 TraceCheckUtils]: 81: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,275 INFO L290 TraceCheckUtils]: 82: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,275 INFO L290 TraceCheckUtils]: 83: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,276 INFO L290 TraceCheckUtils]: 84: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,276 INFO L290 TraceCheckUtils]: 85: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,276 INFO L290 TraceCheckUtils]: 86: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,277 INFO L290 TraceCheckUtils]: 87: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,277 INFO L290 TraceCheckUtils]: 88: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,278 INFO L290 TraceCheckUtils]: 89: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,278 INFO L290 TraceCheckUtils]: 90: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,278 INFO L290 TraceCheckUtils]: 91: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,279 INFO L290 TraceCheckUtils]: 92: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,279 INFO L290 TraceCheckUtils]: 93: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,279 INFO L290 TraceCheckUtils]: 94: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,280 INFO L290 TraceCheckUtils]: 95: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,280 INFO L290 TraceCheckUtils]: 96: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,281 INFO L290 TraceCheckUtils]: 97: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,281 INFO L290 TraceCheckUtils]: 98: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,281 INFO L290 TraceCheckUtils]: 99: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,282 INFO L290 TraceCheckUtils]: 100: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,282 INFO L290 TraceCheckUtils]: 101: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,283 INFO L290 TraceCheckUtils]: 102: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,283 INFO L290 TraceCheckUtils]: 103: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,283 INFO L290 TraceCheckUtils]: 104: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,284 INFO L290 TraceCheckUtils]: 105: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,284 INFO L290 TraceCheckUtils]: 106: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,284 INFO L290 TraceCheckUtils]: 107: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,285 INFO L290 TraceCheckUtils]: 108: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,285 INFO L290 TraceCheckUtils]: 109: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,286 INFO L290 TraceCheckUtils]: 110: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,286 INFO L290 TraceCheckUtils]: 111: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,286 INFO L290 TraceCheckUtils]: 112: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,287 INFO L290 TraceCheckUtils]: 113: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,287 INFO L290 TraceCheckUtils]: 114: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,288 INFO L290 TraceCheckUtils]: 115: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,288 INFO L290 TraceCheckUtils]: 116: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,288 INFO L290 TraceCheckUtils]: 117: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,289 INFO L290 TraceCheckUtils]: 118: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,289 INFO L290 TraceCheckUtils]: 119: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,289 INFO L290 TraceCheckUtils]: 120: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,290 INFO L290 TraceCheckUtils]: 121: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,290 INFO L290 TraceCheckUtils]: 122: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,291 INFO L290 TraceCheckUtils]: 123: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,291 INFO L290 TraceCheckUtils]: 124: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,291 INFO L290 TraceCheckUtils]: 125: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,292 INFO L290 TraceCheckUtils]: 126: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,292 INFO L290 TraceCheckUtils]: 127: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {34449#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:20,292 INFO L290 TraceCheckUtils]: 128: Hoare triple {34449#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {34448#false} is VALID [2022-02-21 04:23:20,293 INFO L290 TraceCheckUtils]: 129: Hoare triple {34448#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,293 INFO L290 TraceCheckUtils]: 130: Hoare triple {34448#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,293 INFO L290 TraceCheckUtils]: 131: Hoare triple {34448#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,293 INFO L290 TraceCheckUtils]: 132: Hoare triple {34448#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,293 INFO L290 TraceCheckUtils]: 133: Hoare triple {34448#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,293 INFO L290 TraceCheckUtils]: 134: Hoare triple {34448#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,293 INFO L290 TraceCheckUtils]: 135: Hoare triple {34448#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,294 INFO L290 TraceCheckUtils]: 136: Hoare triple {34448#false} assume !(1 == ~T13_E~0); {34448#false} is VALID [2022-02-21 04:23:20,294 INFO L290 TraceCheckUtils]: 137: Hoare triple {34448#false} assume 1 == ~E_M~0;~E_M~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,294 INFO L290 TraceCheckUtils]: 138: Hoare triple {34448#false} assume 1 == ~E_1~0;~E_1~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,294 INFO L290 TraceCheckUtils]: 139: Hoare triple {34448#false} assume 1 == ~E_2~0;~E_2~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,294 INFO L290 TraceCheckUtils]: 140: Hoare triple {34448#false} assume 1 == ~E_3~0;~E_3~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,294 INFO L290 TraceCheckUtils]: 141: Hoare triple {34448#false} assume 1 == ~E_4~0;~E_4~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,294 INFO L290 TraceCheckUtils]: 142: Hoare triple {34448#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,295 INFO L290 TraceCheckUtils]: 143: Hoare triple {34448#false} assume 1 == ~E_6~0;~E_6~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,295 INFO L290 TraceCheckUtils]: 144: Hoare triple {34448#false} assume !(1 == ~E_7~0); {34448#false} is VALID [2022-02-21 04:23:20,295 INFO L290 TraceCheckUtils]: 145: Hoare triple {34448#false} assume 1 == ~E_8~0;~E_8~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,295 INFO L290 TraceCheckUtils]: 146: Hoare triple {34448#false} assume 1 == ~E_9~0;~E_9~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,295 INFO L290 TraceCheckUtils]: 147: Hoare triple {34448#false} assume 1 == ~E_10~0;~E_10~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,295 INFO L290 TraceCheckUtils]: 148: Hoare triple {34448#false} assume 1 == ~E_11~0;~E_11~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,295 INFO L290 TraceCheckUtils]: 149: Hoare triple {34448#false} assume 1 == ~E_12~0;~E_12~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,296 INFO L290 TraceCheckUtils]: 150: Hoare triple {34448#false} assume 1 == ~E_13~0;~E_13~0 := 2; {34448#false} is VALID [2022-02-21 04:23:20,296 INFO L290 TraceCheckUtils]: 151: Hoare triple {34448#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {34448#false} is VALID [2022-02-21 04:23:20,296 INFO L290 TraceCheckUtils]: 152: Hoare triple {34448#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {34448#false} is VALID [2022-02-21 04:23:20,296 INFO L290 TraceCheckUtils]: 153: Hoare triple {34448#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {34448#false} is VALID [2022-02-21 04:23:20,296 INFO L290 TraceCheckUtils]: 154: Hoare triple {34448#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {34448#false} is VALID [2022-02-21 04:23:20,296 INFO L290 TraceCheckUtils]: 155: Hoare triple {34448#false} assume !(0 == start_simulation_~tmp~3#1); {34448#false} is VALID [2022-02-21 04:23:20,296 INFO L290 TraceCheckUtils]: 156: Hoare triple {34448#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {34448#false} is VALID [2022-02-21 04:23:20,297 INFO L290 TraceCheckUtils]: 157: Hoare triple {34448#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {34448#false} is VALID [2022-02-21 04:23:20,297 INFO L290 TraceCheckUtils]: 158: Hoare triple {34448#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {34448#false} is VALID [2022-02-21 04:23:20,297 INFO L290 TraceCheckUtils]: 159: Hoare triple {34448#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {34448#false} is VALID [2022-02-21 04:23:20,297 INFO L290 TraceCheckUtils]: 160: Hoare triple {34448#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {34448#false} is VALID [2022-02-21 04:23:20,297 INFO L290 TraceCheckUtils]: 161: Hoare triple {34448#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {34448#false} is VALID [2022-02-21 04:23:20,297 INFO L290 TraceCheckUtils]: 162: Hoare triple {34448#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {34448#false} is VALID [2022-02-21 04:23:20,297 INFO L290 TraceCheckUtils]: 163: Hoare triple {34448#false} assume !(0 != start_simulation_~tmp___0~1#1); {34448#false} is VALID [2022-02-21 04:23:20,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:20,298 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:20,298 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1523181365] [2022-02-21 04:23:20,298 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1523181365] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:20,299 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:20,299 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:20,299 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820194062] [2022-02-21 04:23:20,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:20,299 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:20,300 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:20,301 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:20,301 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:20,301 INFO L87 Difference]: Start difference. First operand 2023 states and 2993 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:21,846 INFO L93 Difference]: Finished difference Result 2023 states and 2992 transitions. [2022-02-21 04:23:21,846 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:21,846 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,968 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:21,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2992 transitions. [2022-02-21 04:23:22,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:22,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2992 transitions. [2022-02-21 04:23:22,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:22,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:22,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2992 transitions. [2022-02-21 04:23:22,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:22,170 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2022-02-21 04:23:22,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2992 transitions. [2022-02-21 04:23:22,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:22,197 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:22,200 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2992 transitions. Second operand has 2023 states, 2023 states have (on average 1.4789915966386555) internal successors, (2992), 2022 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,203 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2992 transitions. Second operand has 2023 states, 2023 states have (on average 1.4789915966386555) internal successors, (2992), 2022 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,205 INFO L87 Difference]: Start difference. First operand 2023 states and 2992 transitions. Second operand has 2023 states, 2023 states have (on average 1.4789915966386555) internal successors, (2992), 2022 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:22,341 INFO L93 Difference]: Finished difference Result 2023 states and 2992 transitions. [2022-02-21 04:23:22,342 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2992 transitions. [2022-02-21 04:23:22,344 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:22,344 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:22,348 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4789915966386555) internal successors, (2992), 2022 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2992 transitions. [2022-02-21 04:23:22,349 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4789915966386555) internal successors, (2992), 2022 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2992 transitions. [2022-02-21 04:23:22,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:22,493 INFO L93 Difference]: Finished difference Result 2023 states and 2992 transitions. [2022-02-21 04:23:22,493 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2992 transitions. [2022-02-21 04:23:22,495 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:22,495 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:22,495 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:22,495 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:22,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4789915966386555) internal successors, (2992), 2022 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2992 transitions. [2022-02-21 04:23:22,603 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2022-02-21 04:23:22,604 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2022-02-21 04:23:22,604 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:23:22,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2992 transitions. [2022-02-21 04:23:22,608 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:22,608 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:22,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:22,610 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:22,610 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:22,610 INFO L791 eck$LassoCheckResult]: Stem: 37400#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 38399#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38400#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38485#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 37864#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37333#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37334#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38150#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38151#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 38251#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 38252#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 37105#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 37106#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38281#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37641#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37642#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38202#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37543#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37544#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 38486#L1291-2 assume !(0 == ~T1_E~0); 38484#L1296-1 assume !(0 == ~T2_E~0); 37700#L1301-1 assume !(0 == ~T3_E~0); 37701#L1306-1 assume !(0 == ~T4_E~0); 38210#L1311-1 assume !(0 == ~T5_E~0); 36948#L1316-1 assume !(0 == ~T6_E~0); 36949#L1321-1 assume !(0 == ~T7_E~0); 37713#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36776#L1331-1 assume !(0 == ~T9_E~0); 36475#L1336-1 assume !(0 == ~T10_E~0); 36476#L1341-1 assume !(0 == ~T11_E~0); 36556#L1346-1 assume !(0 == ~T12_E~0); 36557#L1351-1 assume !(0 == ~T13_E~0); 36897#L1356-1 assume !(0 == ~E_M~0); 36898#L1361-1 assume !(0 == ~E_1~0); 38425#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 36938#L1371-1 assume !(0 == ~E_3~0); 36939#L1376-1 assume !(0 == ~E_4~0); 37760#L1381-1 assume !(0 == ~E_5~0); 37761#L1386-1 assume !(0 == ~E_6~0); 38455#L1391-1 assume !(0 == ~E_7~0); 38473#L1396-1 assume !(0 == ~E_8~0); 37673#L1401-1 assume !(0 == ~E_9~0); 37674#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 37952#L1411-1 assume !(0 == ~E_11~0); 37953#L1416-1 assume !(0 == ~E_12~0); 37585#L1421-1 assume !(0 == ~E_13~0); 37128#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37129#L640 assume !(1 == ~m_pc~0); 37638#L640-2 is_master_triggered_~__retres1~0#1 := 0; 37637#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37729#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37623#L1603 assume !(0 != activate_threads_~tmp~1#1); 37624#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37258#L659 assume 1 == ~t1_pc~0; 37259#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37364#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38310#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37384#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 37385#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37398#L678 assume 1 == ~t2_pc~0; 38352#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38353#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38452#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37496#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 37497#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37618#L697 assume !(1 == ~t3_pc~0); 37619#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37741#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37549#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37528#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37529#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38389#L716 assume 1 == ~t4_pc~0; 38375#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37239#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37240#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36739#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 36740#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38031#L735 assume !(1 == ~t5_pc~0); 36700#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36701#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37151#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38058#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 37694#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37695#L754 assume 1 == ~t6_pc~0; 37448#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37346#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37347#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37320#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 37321#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38141#L773 assume !(1 == ~t7_pc~0); 36901#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 36900#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37730#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37702#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 37703#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37750#L792 assume 1 == ~t8_pc~0; 37923#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38255#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37744#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37697#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 37621#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37622#L811 assume 1 == ~t9_pc~0; 37826#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38292#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38168#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37822#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 37634#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37635#L830 assume !(1 == ~t10_pc~0); 37356#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36880#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36573#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36574#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36861#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38159#L849 assume 1 == ~t11_pc~0; 38160#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36676#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36677#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37266#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 38065#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38066#L868 assume !(1 == ~t12_pc~0); 37481#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37480#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37275#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37276#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 36912#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36913#L887 assume 1 == ~t13_pc~0; 38080#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37522#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37523#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37959#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 36616#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36617#L1439 assume !(1 == ~M_E~0); 37690#L1439-2 assume !(1 == ~T1_E~0); 36788#L1444-1 assume !(1 == ~T2_E~0); 36789#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37262#L1454-1 assume !(1 == ~T4_E~0); 37263#L1459-1 assume !(1 == ~T5_E~0); 37819#L1464-1 assume !(1 == ~T6_E~0); 37820#L1469-1 assume !(1 == ~T7_E~0); 37892#L1474-1 assume !(1 == ~T8_E~0); 37586#L1479-1 assume !(1 == ~T9_E~0); 37587#L1484-1 assume !(1 == ~T10_E~0); 37823#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37469#L1494-1 assume !(1 == ~T12_E~0); 37470#L1499-1 assume !(1 == ~T13_E~0); 37662#L1504-1 assume !(1 == ~E_M~0); 37663#L1509-1 assume !(1 == ~E_1~0); 38238#L1514-1 assume !(1 == ~E_2~0); 37925#L1519-1 assume !(1 == ~E_3~0); 37926#L1524-1 assume !(1 == ~E_4~0); 38438#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38439#L1534-1 assume !(1 == ~E_6~0); 36609#L1539-1 assume !(1 == ~E_7~0); 36610#L1544-1 assume !(1 == ~E_8~0); 37024#L1549-1 assume !(1 == ~E_9~0); 38413#L1554-1 assume !(1 == ~E_10~0); 38409#L1559-1 assume !(1 == ~E_11~0); 38276#L1564-1 assume !(1 == ~E_12~0); 38277#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38434#L1574-1 assume { :end_inline_reset_delta_events } true; 36786#L1940-2 [2022-02-21 04:23:22,611 INFO L793 eck$LassoCheckResult]: Loop: 36786#L1940-2 assume !false; 36787#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37069#L1266 assume !false; 38088#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37317#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37050#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37441#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37442#L1079 assume !(0 != eval_~tmp~0#1); 37403#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37404#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38008#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37893#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37894#L1296-3 assume !(0 == ~T2_E~0); 38466#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38420#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37551#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36827#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36828#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36928#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37685#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37934#L1336-3 assume !(0 == ~T10_E~0); 37935#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37255#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37235#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37180#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37181#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37742#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36531#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36532#L1376-3 assume !(0 == ~E_4~0); 38261#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38121#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38122#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38284#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38285#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36894#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36748#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36749#L1416-3 assume !(0 == ~E_12~0); 37410#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37411#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37518#L640-45 assume 1 == ~m_pc~0; 37520#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36985#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36986#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36525#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36526#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36624#L659-45 assume 1 == ~t1_pc~0; 36625#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37064#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38023#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38024#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38045#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38046#L678-45 assume 1 == ~t2_pc~0; 37989#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37524#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37525#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37677#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38302#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38419#L697-45 assume 1 == ~t3_pc~0; 37782#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37783#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38371#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37941#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37942#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37972#L716-45 assume 1 == ~t4_pc~0; 37603#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37604#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38154#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37609#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37610#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37272#L735-45 assume 1 == ~t5_pc~0; 37273#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37816#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38378#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38379#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38437#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38432#L754-45 assume 1 == ~t6_pc~0; 37764#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37765#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37194#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37195#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37768#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37500#L773-45 assume !(1 == ~t7_pc~0); 37057#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 37058#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37978#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38260#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 37506#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37176#L792-45 assume 1 == ~t8_pc~0; 37177#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38206#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36779#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36638#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36639#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37134#L811-45 assume 1 == ~t9_pc~0; 36923#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36925#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38133#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37968#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37577#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37369#L830-45 assume !(1 == ~t10_pc~0); 36566#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 36567#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37689#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36799#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36800#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36545#L849-45 assume !(1 == ~t11_pc~0); 36546#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37005#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36636#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36533#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36534#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36792#L868-45 assume 1 == ~t12_pc~0; 36793#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36732#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36733#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38071#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 38322#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38323#L887-45 assume !(1 == ~t13_pc~0); 36801#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 36802#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38084#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38429#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 36764#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36765#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38072#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36784#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36785#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36942#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37873#L1459-3 assume !(1 == ~T5_E~0); 37874#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38325#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38264#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38265#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38326#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37558#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37559#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38195#L1499-3 assume !(1 == ~T13_E~0); 37834#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37835#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38273#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38303#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37477#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37478#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38345#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37745#L1539-3 assume !(1 == ~E_7~0); 37221#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37222#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37717#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36838#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36839#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37973#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37974#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36715#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36486#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36761#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 36722#L1959 assume !(0 == start_simulation_~tmp~3#1); 36724#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36756#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36706#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38015#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38136#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38343#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38357#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38358#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 36786#L1940-2 [2022-02-21 04:23:22,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:22,612 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2022-02-21 04:23:22,612 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:22,612 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390904943] [2022-02-21 04:23:22,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:22,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:22,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:22,638 INFO L290 TraceCheckUtils]: 0: Hoare triple {42545#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {42545#true} is VALID [2022-02-21 04:23:22,639 INFO L290 TraceCheckUtils]: 1: Hoare triple {42545#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {42547#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:22,639 INFO L290 TraceCheckUtils]: 2: Hoare triple {42547#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {42547#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:22,640 INFO L290 TraceCheckUtils]: 3: Hoare triple {42547#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {42547#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:22,640 INFO L290 TraceCheckUtils]: 4: Hoare triple {42547#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {42547#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:22,640 INFO L290 TraceCheckUtils]: 5: Hoare triple {42547#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {42547#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:22,641 INFO L290 TraceCheckUtils]: 6: Hoare triple {42547#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {42547#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:22,641 INFO L290 TraceCheckUtils]: 7: Hoare triple {42547#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {42547#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:22,641 INFO L290 TraceCheckUtils]: 8: Hoare triple {42547#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {42547#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:22,641 INFO L290 TraceCheckUtils]: 9: Hoare triple {42547#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,642 INFO L290 TraceCheckUtils]: 10: Hoare triple {42546#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,642 INFO L290 TraceCheckUtils]: 11: Hoare triple {42546#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,642 INFO L290 TraceCheckUtils]: 12: Hoare triple {42546#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,642 INFO L290 TraceCheckUtils]: 13: Hoare triple {42546#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {42546#false} is VALID [2022-02-21 04:23:22,642 INFO L290 TraceCheckUtils]: 14: Hoare triple {42546#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,642 INFO L290 TraceCheckUtils]: 15: Hoare triple {42546#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,642 INFO L290 TraceCheckUtils]: 16: Hoare triple {42546#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,643 INFO L290 TraceCheckUtils]: 17: Hoare triple {42546#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,643 INFO L290 TraceCheckUtils]: 18: Hoare triple {42546#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {42546#false} is VALID [2022-02-21 04:23:22,643 INFO L290 TraceCheckUtils]: 19: Hoare triple {42546#false} assume 0 == ~M_E~0;~M_E~0 := 1; {42546#false} is VALID [2022-02-21 04:23:22,643 INFO L290 TraceCheckUtils]: 20: Hoare triple {42546#false} assume !(0 == ~T1_E~0); {42546#false} is VALID [2022-02-21 04:23:22,643 INFO L290 TraceCheckUtils]: 21: Hoare triple {42546#false} assume !(0 == ~T2_E~0); {42546#false} is VALID [2022-02-21 04:23:22,643 INFO L290 TraceCheckUtils]: 22: Hoare triple {42546#false} assume !(0 == ~T3_E~0); {42546#false} is VALID [2022-02-21 04:23:22,643 INFO L290 TraceCheckUtils]: 23: Hoare triple {42546#false} assume !(0 == ~T4_E~0); {42546#false} is VALID [2022-02-21 04:23:22,644 INFO L290 TraceCheckUtils]: 24: Hoare triple {42546#false} assume !(0 == ~T5_E~0); {42546#false} is VALID [2022-02-21 04:23:22,644 INFO L290 TraceCheckUtils]: 25: Hoare triple {42546#false} assume !(0 == ~T6_E~0); {42546#false} is VALID [2022-02-21 04:23:22,644 INFO L290 TraceCheckUtils]: 26: Hoare triple {42546#false} assume !(0 == ~T7_E~0); {42546#false} is VALID [2022-02-21 04:23:22,644 INFO L290 TraceCheckUtils]: 27: Hoare triple {42546#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {42546#false} is VALID [2022-02-21 04:23:22,644 INFO L290 TraceCheckUtils]: 28: Hoare triple {42546#false} assume !(0 == ~T9_E~0); {42546#false} is VALID [2022-02-21 04:23:22,644 INFO L290 TraceCheckUtils]: 29: Hoare triple {42546#false} assume !(0 == ~T10_E~0); {42546#false} is VALID [2022-02-21 04:23:22,644 INFO L290 TraceCheckUtils]: 30: Hoare triple {42546#false} assume !(0 == ~T11_E~0); {42546#false} is VALID [2022-02-21 04:23:22,645 INFO L290 TraceCheckUtils]: 31: Hoare triple {42546#false} assume !(0 == ~T12_E~0); {42546#false} is VALID [2022-02-21 04:23:22,645 INFO L290 TraceCheckUtils]: 32: Hoare triple {42546#false} assume !(0 == ~T13_E~0); {42546#false} is VALID [2022-02-21 04:23:22,645 INFO L290 TraceCheckUtils]: 33: Hoare triple {42546#false} assume !(0 == ~E_M~0); {42546#false} is VALID [2022-02-21 04:23:22,645 INFO L290 TraceCheckUtils]: 34: Hoare triple {42546#false} assume !(0 == ~E_1~0); {42546#false} is VALID [2022-02-21 04:23:22,645 INFO L290 TraceCheckUtils]: 35: Hoare triple {42546#false} assume 0 == ~E_2~0;~E_2~0 := 1; {42546#false} is VALID [2022-02-21 04:23:22,645 INFO L290 TraceCheckUtils]: 36: Hoare triple {42546#false} assume !(0 == ~E_3~0); {42546#false} is VALID [2022-02-21 04:23:22,645 INFO L290 TraceCheckUtils]: 37: Hoare triple {42546#false} assume !(0 == ~E_4~0); {42546#false} is VALID [2022-02-21 04:23:22,646 INFO L290 TraceCheckUtils]: 38: Hoare triple {42546#false} assume !(0 == ~E_5~0); {42546#false} is VALID [2022-02-21 04:23:22,646 INFO L290 TraceCheckUtils]: 39: Hoare triple {42546#false} assume !(0 == ~E_6~0); {42546#false} is VALID [2022-02-21 04:23:22,646 INFO L290 TraceCheckUtils]: 40: Hoare triple {42546#false} assume !(0 == ~E_7~0); {42546#false} is VALID [2022-02-21 04:23:22,646 INFO L290 TraceCheckUtils]: 41: Hoare triple {42546#false} assume !(0 == ~E_8~0); {42546#false} is VALID [2022-02-21 04:23:22,646 INFO L290 TraceCheckUtils]: 42: Hoare triple {42546#false} assume !(0 == ~E_9~0); {42546#false} is VALID [2022-02-21 04:23:22,646 INFO L290 TraceCheckUtils]: 43: Hoare triple {42546#false} assume 0 == ~E_10~0;~E_10~0 := 1; {42546#false} is VALID [2022-02-21 04:23:22,646 INFO L290 TraceCheckUtils]: 44: Hoare triple {42546#false} assume !(0 == ~E_11~0); {42546#false} is VALID [2022-02-21 04:23:22,647 INFO L290 TraceCheckUtils]: 45: Hoare triple {42546#false} assume !(0 == ~E_12~0); {42546#false} is VALID [2022-02-21 04:23:22,647 INFO L290 TraceCheckUtils]: 46: Hoare triple {42546#false} assume !(0 == ~E_13~0); {42546#false} is VALID [2022-02-21 04:23:22,647 INFO L290 TraceCheckUtils]: 47: Hoare triple {42546#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {42546#false} is VALID [2022-02-21 04:23:22,647 INFO L290 TraceCheckUtils]: 48: Hoare triple {42546#false} assume !(1 == ~m_pc~0); {42546#false} is VALID [2022-02-21 04:23:22,647 INFO L290 TraceCheckUtils]: 49: Hoare triple {42546#false} is_master_triggered_~__retres1~0#1 := 0; {42546#false} is VALID [2022-02-21 04:23:22,647 INFO L290 TraceCheckUtils]: 50: Hoare triple {42546#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {42546#false} is VALID [2022-02-21 04:23:22,647 INFO L290 TraceCheckUtils]: 51: Hoare triple {42546#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {42546#false} is VALID [2022-02-21 04:23:22,648 INFO L290 TraceCheckUtils]: 52: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp~1#1); {42546#false} is VALID [2022-02-21 04:23:22,648 INFO L290 TraceCheckUtils]: 53: Hoare triple {42546#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {42546#false} is VALID [2022-02-21 04:23:22,648 INFO L290 TraceCheckUtils]: 54: Hoare triple {42546#false} assume 1 == ~t1_pc~0; {42546#false} is VALID [2022-02-21 04:23:22,648 INFO L290 TraceCheckUtils]: 55: Hoare triple {42546#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {42546#false} is VALID [2022-02-21 04:23:22,648 INFO L290 TraceCheckUtils]: 56: Hoare triple {42546#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {42546#false} is VALID [2022-02-21 04:23:22,648 INFO L290 TraceCheckUtils]: 57: Hoare triple {42546#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {42546#false} is VALID [2022-02-21 04:23:22,649 INFO L290 TraceCheckUtils]: 58: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___0~0#1); {42546#false} is VALID [2022-02-21 04:23:22,649 INFO L290 TraceCheckUtils]: 59: Hoare triple {42546#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {42546#false} is VALID [2022-02-21 04:23:22,649 INFO L290 TraceCheckUtils]: 60: Hoare triple {42546#false} assume 1 == ~t2_pc~0; {42546#false} is VALID [2022-02-21 04:23:22,649 INFO L290 TraceCheckUtils]: 61: Hoare triple {42546#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {42546#false} is VALID [2022-02-21 04:23:22,649 INFO L290 TraceCheckUtils]: 62: Hoare triple {42546#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {42546#false} is VALID [2022-02-21 04:23:22,649 INFO L290 TraceCheckUtils]: 63: Hoare triple {42546#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {42546#false} is VALID [2022-02-21 04:23:22,649 INFO L290 TraceCheckUtils]: 64: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___1~0#1); {42546#false} is VALID [2022-02-21 04:23:22,650 INFO L290 TraceCheckUtils]: 65: Hoare triple {42546#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {42546#false} is VALID [2022-02-21 04:23:22,650 INFO L290 TraceCheckUtils]: 66: Hoare triple {42546#false} assume !(1 == ~t3_pc~0); {42546#false} is VALID [2022-02-21 04:23:22,650 INFO L290 TraceCheckUtils]: 67: Hoare triple {42546#false} is_transmit3_triggered_~__retres1~3#1 := 0; {42546#false} is VALID [2022-02-21 04:23:22,650 INFO L290 TraceCheckUtils]: 68: Hoare triple {42546#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {42546#false} is VALID [2022-02-21 04:23:22,650 INFO L290 TraceCheckUtils]: 69: Hoare triple {42546#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {42546#false} is VALID [2022-02-21 04:23:22,650 INFO L290 TraceCheckUtils]: 70: Hoare triple {42546#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {42546#false} is VALID [2022-02-21 04:23:22,651 INFO L290 TraceCheckUtils]: 71: Hoare triple {42546#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {42546#false} is VALID [2022-02-21 04:23:22,651 INFO L290 TraceCheckUtils]: 72: Hoare triple {42546#false} assume 1 == ~t4_pc~0; {42546#false} is VALID [2022-02-21 04:23:22,651 INFO L290 TraceCheckUtils]: 73: Hoare triple {42546#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {42546#false} is VALID [2022-02-21 04:23:22,651 INFO L290 TraceCheckUtils]: 74: Hoare triple {42546#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {42546#false} is VALID [2022-02-21 04:23:22,651 INFO L290 TraceCheckUtils]: 75: Hoare triple {42546#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {42546#false} is VALID [2022-02-21 04:23:22,651 INFO L290 TraceCheckUtils]: 76: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___3~0#1); {42546#false} is VALID [2022-02-21 04:23:22,651 INFO L290 TraceCheckUtils]: 77: Hoare triple {42546#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {42546#false} is VALID [2022-02-21 04:23:22,652 INFO L290 TraceCheckUtils]: 78: Hoare triple {42546#false} assume !(1 == ~t5_pc~0); {42546#false} is VALID [2022-02-21 04:23:22,652 INFO L290 TraceCheckUtils]: 79: Hoare triple {42546#false} is_transmit5_triggered_~__retres1~5#1 := 0; {42546#false} is VALID [2022-02-21 04:23:22,652 INFO L290 TraceCheckUtils]: 80: Hoare triple {42546#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {42546#false} is VALID [2022-02-21 04:23:22,652 INFO L290 TraceCheckUtils]: 81: Hoare triple {42546#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {42546#false} is VALID [2022-02-21 04:23:22,652 INFO L290 TraceCheckUtils]: 82: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___4~0#1); {42546#false} is VALID [2022-02-21 04:23:22,652 INFO L290 TraceCheckUtils]: 83: Hoare triple {42546#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {42546#false} is VALID [2022-02-21 04:23:22,652 INFO L290 TraceCheckUtils]: 84: Hoare triple {42546#false} assume 1 == ~t6_pc~0; {42546#false} is VALID [2022-02-21 04:23:22,653 INFO L290 TraceCheckUtils]: 85: Hoare triple {42546#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {42546#false} is VALID [2022-02-21 04:23:22,653 INFO L290 TraceCheckUtils]: 86: Hoare triple {42546#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {42546#false} is VALID [2022-02-21 04:23:22,653 INFO L290 TraceCheckUtils]: 87: Hoare triple {42546#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {42546#false} is VALID [2022-02-21 04:23:22,653 INFO L290 TraceCheckUtils]: 88: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___5~0#1); {42546#false} is VALID [2022-02-21 04:23:22,653 INFO L290 TraceCheckUtils]: 89: Hoare triple {42546#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {42546#false} is VALID [2022-02-21 04:23:22,653 INFO L290 TraceCheckUtils]: 90: Hoare triple {42546#false} assume !(1 == ~t7_pc~0); {42546#false} is VALID [2022-02-21 04:23:22,653 INFO L290 TraceCheckUtils]: 91: Hoare triple {42546#false} is_transmit7_triggered_~__retres1~7#1 := 0; {42546#false} is VALID [2022-02-21 04:23:22,654 INFO L290 TraceCheckUtils]: 92: Hoare triple {42546#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {42546#false} is VALID [2022-02-21 04:23:22,654 INFO L290 TraceCheckUtils]: 93: Hoare triple {42546#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {42546#false} is VALID [2022-02-21 04:23:22,654 INFO L290 TraceCheckUtils]: 94: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___6~0#1); {42546#false} is VALID [2022-02-21 04:23:22,654 INFO L290 TraceCheckUtils]: 95: Hoare triple {42546#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {42546#false} is VALID [2022-02-21 04:23:22,654 INFO L290 TraceCheckUtils]: 96: Hoare triple {42546#false} assume 1 == ~t8_pc~0; {42546#false} is VALID [2022-02-21 04:23:22,654 INFO L290 TraceCheckUtils]: 97: Hoare triple {42546#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {42546#false} is VALID [2022-02-21 04:23:22,654 INFO L290 TraceCheckUtils]: 98: Hoare triple {42546#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {42546#false} is VALID [2022-02-21 04:23:22,654 INFO L290 TraceCheckUtils]: 99: Hoare triple {42546#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {42546#false} is VALID [2022-02-21 04:23:22,655 INFO L290 TraceCheckUtils]: 100: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___7~0#1); {42546#false} is VALID [2022-02-21 04:23:22,655 INFO L290 TraceCheckUtils]: 101: Hoare triple {42546#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {42546#false} is VALID [2022-02-21 04:23:22,655 INFO L290 TraceCheckUtils]: 102: Hoare triple {42546#false} assume 1 == ~t9_pc~0; {42546#false} is VALID [2022-02-21 04:23:22,655 INFO L290 TraceCheckUtils]: 103: Hoare triple {42546#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {42546#false} is VALID [2022-02-21 04:23:22,655 INFO L290 TraceCheckUtils]: 104: Hoare triple {42546#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {42546#false} is VALID [2022-02-21 04:23:22,655 INFO L290 TraceCheckUtils]: 105: Hoare triple {42546#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {42546#false} is VALID [2022-02-21 04:23:22,656 INFO L290 TraceCheckUtils]: 106: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___8~0#1); {42546#false} is VALID [2022-02-21 04:23:22,656 INFO L290 TraceCheckUtils]: 107: Hoare triple {42546#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {42546#false} is VALID [2022-02-21 04:23:22,656 INFO L290 TraceCheckUtils]: 108: Hoare triple {42546#false} assume !(1 == ~t10_pc~0); {42546#false} is VALID [2022-02-21 04:23:22,656 INFO L290 TraceCheckUtils]: 109: Hoare triple {42546#false} is_transmit10_triggered_~__retres1~10#1 := 0; {42546#false} is VALID [2022-02-21 04:23:22,656 INFO L290 TraceCheckUtils]: 110: Hoare triple {42546#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {42546#false} is VALID [2022-02-21 04:23:22,656 INFO L290 TraceCheckUtils]: 111: Hoare triple {42546#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {42546#false} is VALID [2022-02-21 04:23:22,656 INFO L290 TraceCheckUtils]: 112: Hoare triple {42546#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {42546#false} is VALID [2022-02-21 04:23:22,656 INFO L290 TraceCheckUtils]: 113: Hoare triple {42546#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {42546#false} is VALID [2022-02-21 04:23:22,657 INFO L290 TraceCheckUtils]: 114: Hoare triple {42546#false} assume 1 == ~t11_pc~0; {42546#false} is VALID [2022-02-21 04:23:22,657 INFO L290 TraceCheckUtils]: 115: Hoare triple {42546#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {42546#false} is VALID [2022-02-21 04:23:22,657 INFO L290 TraceCheckUtils]: 116: Hoare triple {42546#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {42546#false} is VALID [2022-02-21 04:23:22,657 INFO L290 TraceCheckUtils]: 117: Hoare triple {42546#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {42546#false} is VALID [2022-02-21 04:23:22,657 INFO L290 TraceCheckUtils]: 118: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___10~0#1); {42546#false} is VALID [2022-02-21 04:23:22,657 INFO L290 TraceCheckUtils]: 119: Hoare triple {42546#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {42546#false} is VALID [2022-02-21 04:23:22,657 INFO L290 TraceCheckUtils]: 120: Hoare triple {42546#false} assume !(1 == ~t12_pc~0); {42546#false} is VALID [2022-02-21 04:23:22,658 INFO L290 TraceCheckUtils]: 121: Hoare triple {42546#false} is_transmit12_triggered_~__retres1~12#1 := 0; {42546#false} is VALID [2022-02-21 04:23:22,658 INFO L290 TraceCheckUtils]: 122: Hoare triple {42546#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {42546#false} is VALID [2022-02-21 04:23:22,658 INFO L290 TraceCheckUtils]: 123: Hoare triple {42546#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {42546#false} is VALID [2022-02-21 04:23:22,658 INFO L290 TraceCheckUtils]: 124: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___11~0#1); {42546#false} is VALID [2022-02-21 04:23:22,658 INFO L290 TraceCheckUtils]: 125: Hoare triple {42546#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {42546#false} is VALID [2022-02-21 04:23:22,658 INFO L290 TraceCheckUtils]: 126: Hoare triple {42546#false} assume 1 == ~t13_pc~0; {42546#false} is VALID [2022-02-21 04:23:22,658 INFO L290 TraceCheckUtils]: 127: Hoare triple {42546#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {42546#false} is VALID [2022-02-21 04:23:22,659 INFO L290 TraceCheckUtils]: 128: Hoare triple {42546#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {42546#false} is VALID [2022-02-21 04:23:22,659 INFO L290 TraceCheckUtils]: 129: Hoare triple {42546#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {42546#false} is VALID [2022-02-21 04:23:22,659 INFO L290 TraceCheckUtils]: 130: Hoare triple {42546#false} assume !(0 != activate_threads_~tmp___12~0#1); {42546#false} is VALID [2022-02-21 04:23:22,659 INFO L290 TraceCheckUtils]: 131: Hoare triple {42546#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {42546#false} is VALID [2022-02-21 04:23:22,659 INFO L290 TraceCheckUtils]: 132: Hoare triple {42546#false} assume !(1 == ~M_E~0); {42546#false} is VALID [2022-02-21 04:23:22,659 INFO L290 TraceCheckUtils]: 133: Hoare triple {42546#false} assume !(1 == ~T1_E~0); {42546#false} is VALID [2022-02-21 04:23:22,659 INFO L290 TraceCheckUtils]: 134: Hoare triple {42546#false} assume !(1 == ~T2_E~0); {42546#false} is VALID [2022-02-21 04:23:22,660 INFO L290 TraceCheckUtils]: 135: Hoare triple {42546#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,660 INFO L290 TraceCheckUtils]: 136: Hoare triple {42546#false} assume !(1 == ~T4_E~0); {42546#false} is VALID [2022-02-21 04:23:22,660 INFO L290 TraceCheckUtils]: 137: Hoare triple {42546#false} assume !(1 == ~T5_E~0); {42546#false} is VALID [2022-02-21 04:23:22,660 INFO L290 TraceCheckUtils]: 138: Hoare triple {42546#false} assume !(1 == ~T6_E~0); {42546#false} is VALID [2022-02-21 04:23:22,660 INFO L290 TraceCheckUtils]: 139: Hoare triple {42546#false} assume !(1 == ~T7_E~0); {42546#false} is VALID [2022-02-21 04:23:22,660 INFO L290 TraceCheckUtils]: 140: Hoare triple {42546#false} assume !(1 == ~T8_E~0); {42546#false} is VALID [2022-02-21 04:23:22,660 INFO L290 TraceCheckUtils]: 141: Hoare triple {42546#false} assume !(1 == ~T9_E~0); {42546#false} is VALID [2022-02-21 04:23:22,661 INFO L290 TraceCheckUtils]: 142: Hoare triple {42546#false} assume !(1 == ~T10_E~0); {42546#false} is VALID [2022-02-21 04:23:22,661 INFO L290 TraceCheckUtils]: 143: Hoare triple {42546#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,661 INFO L290 TraceCheckUtils]: 144: Hoare triple {42546#false} assume !(1 == ~T12_E~0); {42546#false} is VALID [2022-02-21 04:23:22,661 INFO L290 TraceCheckUtils]: 145: Hoare triple {42546#false} assume !(1 == ~T13_E~0); {42546#false} is VALID [2022-02-21 04:23:22,661 INFO L290 TraceCheckUtils]: 146: Hoare triple {42546#false} assume !(1 == ~E_M~0); {42546#false} is VALID [2022-02-21 04:23:22,661 INFO L290 TraceCheckUtils]: 147: Hoare triple {42546#false} assume !(1 == ~E_1~0); {42546#false} is VALID [2022-02-21 04:23:22,661 INFO L290 TraceCheckUtils]: 148: Hoare triple {42546#false} assume !(1 == ~E_2~0); {42546#false} is VALID [2022-02-21 04:23:22,662 INFO L290 TraceCheckUtils]: 149: Hoare triple {42546#false} assume !(1 == ~E_3~0); {42546#false} is VALID [2022-02-21 04:23:22,662 INFO L290 TraceCheckUtils]: 150: Hoare triple {42546#false} assume !(1 == ~E_4~0); {42546#false} is VALID [2022-02-21 04:23:22,662 INFO L290 TraceCheckUtils]: 151: Hoare triple {42546#false} assume 1 == ~E_5~0;~E_5~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,662 INFO L290 TraceCheckUtils]: 152: Hoare triple {42546#false} assume !(1 == ~E_6~0); {42546#false} is VALID [2022-02-21 04:23:22,662 INFO L290 TraceCheckUtils]: 153: Hoare triple {42546#false} assume !(1 == ~E_7~0); {42546#false} is VALID [2022-02-21 04:23:22,662 INFO L290 TraceCheckUtils]: 154: Hoare triple {42546#false} assume !(1 == ~E_8~0); {42546#false} is VALID [2022-02-21 04:23:22,662 INFO L290 TraceCheckUtils]: 155: Hoare triple {42546#false} assume !(1 == ~E_9~0); {42546#false} is VALID [2022-02-21 04:23:22,663 INFO L290 TraceCheckUtils]: 156: Hoare triple {42546#false} assume !(1 == ~E_10~0); {42546#false} is VALID [2022-02-21 04:23:22,663 INFO L290 TraceCheckUtils]: 157: Hoare triple {42546#false} assume !(1 == ~E_11~0); {42546#false} is VALID [2022-02-21 04:23:22,663 INFO L290 TraceCheckUtils]: 158: Hoare triple {42546#false} assume !(1 == ~E_12~0); {42546#false} is VALID [2022-02-21 04:23:22,663 INFO L290 TraceCheckUtils]: 159: Hoare triple {42546#false} assume 1 == ~E_13~0;~E_13~0 := 2; {42546#false} is VALID [2022-02-21 04:23:22,663 INFO L290 TraceCheckUtils]: 160: Hoare triple {42546#false} assume { :end_inline_reset_delta_events } true; {42546#false} is VALID [2022-02-21 04:23:22,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:22,664 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:22,664 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390904943] [2022-02-21 04:23:22,664 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390904943] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:22,664 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:22,664 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:22,665 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450586127] [2022-02-21 04:23:22,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:22,665 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:22,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:22,666 INFO L85 PathProgramCache]: Analyzing trace with hash 2009983070, now seen corresponding path program 1 times [2022-02-21 04:23:22,666 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:22,666 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335238773] [2022-02-21 04:23:22,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:22,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:22,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:22,702 INFO L290 TraceCheckUtils]: 0: Hoare triple {42548#true} assume !false; {42548#true} is VALID [2022-02-21 04:23:22,703 INFO L290 TraceCheckUtils]: 1: Hoare triple {42548#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {42548#true} is VALID [2022-02-21 04:23:22,703 INFO L290 TraceCheckUtils]: 2: Hoare triple {42548#true} assume !false; {42548#true} is VALID [2022-02-21 04:23:22,703 INFO L290 TraceCheckUtils]: 3: Hoare triple {42548#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {42548#true} is VALID [2022-02-21 04:23:22,703 INFO L290 TraceCheckUtils]: 4: Hoare triple {42548#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {42548#true} is VALID [2022-02-21 04:23:22,703 INFO L290 TraceCheckUtils]: 5: Hoare triple {42548#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {42548#true} is VALID [2022-02-21 04:23:22,703 INFO L290 TraceCheckUtils]: 6: Hoare triple {42548#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {42548#true} is VALID [2022-02-21 04:23:22,704 INFO L290 TraceCheckUtils]: 7: Hoare triple {42548#true} assume !(0 != eval_~tmp~0#1); {42548#true} is VALID [2022-02-21 04:23:22,704 INFO L290 TraceCheckUtils]: 8: Hoare triple {42548#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {42548#true} is VALID [2022-02-21 04:23:22,704 INFO L290 TraceCheckUtils]: 9: Hoare triple {42548#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {42548#true} is VALID [2022-02-21 04:23:22,704 INFO L290 TraceCheckUtils]: 10: Hoare triple {42548#true} assume 0 == ~M_E~0;~M_E~0 := 1; {42548#true} is VALID [2022-02-21 04:23:22,704 INFO L290 TraceCheckUtils]: 11: Hoare triple {42548#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {42548#true} is VALID [2022-02-21 04:23:22,704 INFO L290 TraceCheckUtils]: 12: Hoare triple {42548#true} assume !(0 == ~T2_E~0); {42548#true} is VALID [2022-02-21 04:23:22,704 INFO L290 TraceCheckUtils]: 13: Hoare triple {42548#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {42548#true} is VALID [2022-02-21 04:23:22,705 INFO L290 TraceCheckUtils]: 14: Hoare triple {42548#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {42548#true} is VALID [2022-02-21 04:23:22,705 INFO L290 TraceCheckUtils]: 15: Hoare triple {42548#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,705 INFO L290 TraceCheckUtils]: 16: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,706 INFO L290 TraceCheckUtils]: 17: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,706 INFO L290 TraceCheckUtils]: 18: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,707 INFO L290 TraceCheckUtils]: 19: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,707 INFO L290 TraceCheckUtils]: 20: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,707 INFO L290 TraceCheckUtils]: 21: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,708 INFO L290 TraceCheckUtils]: 22: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,708 INFO L290 TraceCheckUtils]: 23: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,708 INFO L290 TraceCheckUtils]: 24: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,709 INFO L290 TraceCheckUtils]: 25: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,709 INFO L290 TraceCheckUtils]: 26: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,710 INFO L290 TraceCheckUtils]: 27: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,710 INFO L290 TraceCheckUtils]: 28: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,710 INFO L290 TraceCheckUtils]: 29: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,711 INFO L290 TraceCheckUtils]: 30: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,711 INFO L290 TraceCheckUtils]: 31: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,711 INFO L290 TraceCheckUtils]: 32: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,712 INFO L290 TraceCheckUtils]: 33: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,712 INFO L290 TraceCheckUtils]: 34: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,712 INFO L290 TraceCheckUtils]: 35: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,713 INFO L290 TraceCheckUtils]: 36: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,713 INFO L290 TraceCheckUtils]: 37: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,714 INFO L290 TraceCheckUtils]: 38: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,714 INFO L290 TraceCheckUtils]: 39: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,714 INFO L290 TraceCheckUtils]: 40: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,715 INFO L290 TraceCheckUtils]: 41: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,715 INFO L290 TraceCheckUtils]: 42: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,715 INFO L290 TraceCheckUtils]: 43: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,716 INFO L290 TraceCheckUtils]: 44: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,716 INFO L290 TraceCheckUtils]: 45: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,717 INFO L290 TraceCheckUtils]: 46: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,717 INFO L290 TraceCheckUtils]: 47: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,717 INFO L290 TraceCheckUtils]: 48: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,718 INFO L290 TraceCheckUtils]: 49: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,718 INFO L290 TraceCheckUtils]: 50: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,718 INFO L290 TraceCheckUtils]: 51: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,719 INFO L290 TraceCheckUtils]: 52: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,719 INFO L290 TraceCheckUtils]: 53: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,720 INFO L290 TraceCheckUtils]: 54: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,720 INFO L290 TraceCheckUtils]: 55: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,720 INFO L290 TraceCheckUtils]: 56: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,721 INFO L290 TraceCheckUtils]: 57: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,721 INFO L290 TraceCheckUtils]: 58: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,722 INFO L290 TraceCheckUtils]: 59: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,722 INFO L290 TraceCheckUtils]: 60: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,722 INFO L290 TraceCheckUtils]: 61: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,723 INFO L290 TraceCheckUtils]: 62: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,723 INFO L290 TraceCheckUtils]: 63: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,723 INFO L290 TraceCheckUtils]: 64: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,724 INFO L290 TraceCheckUtils]: 65: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,724 INFO L290 TraceCheckUtils]: 66: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,725 INFO L290 TraceCheckUtils]: 67: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,725 INFO L290 TraceCheckUtils]: 68: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,725 INFO L290 TraceCheckUtils]: 69: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,726 INFO L290 TraceCheckUtils]: 70: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,726 INFO L290 TraceCheckUtils]: 71: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,726 INFO L290 TraceCheckUtils]: 72: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,727 INFO L290 TraceCheckUtils]: 73: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,727 INFO L290 TraceCheckUtils]: 74: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,727 INFO L290 TraceCheckUtils]: 75: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,728 INFO L290 TraceCheckUtils]: 76: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,728 INFO L290 TraceCheckUtils]: 77: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,729 INFO L290 TraceCheckUtils]: 78: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,729 INFO L290 TraceCheckUtils]: 79: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,729 INFO L290 TraceCheckUtils]: 80: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,730 INFO L290 TraceCheckUtils]: 81: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,730 INFO L290 TraceCheckUtils]: 82: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,730 INFO L290 TraceCheckUtils]: 83: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,731 INFO L290 TraceCheckUtils]: 84: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,731 INFO L290 TraceCheckUtils]: 85: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,732 INFO L290 TraceCheckUtils]: 86: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,732 INFO L290 TraceCheckUtils]: 87: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,732 INFO L290 TraceCheckUtils]: 88: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,733 INFO L290 TraceCheckUtils]: 89: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,733 INFO L290 TraceCheckUtils]: 90: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,733 INFO L290 TraceCheckUtils]: 91: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,734 INFO L290 TraceCheckUtils]: 92: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,734 INFO L290 TraceCheckUtils]: 93: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,735 INFO L290 TraceCheckUtils]: 94: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,735 INFO L290 TraceCheckUtils]: 95: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,735 INFO L290 TraceCheckUtils]: 96: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,736 INFO L290 TraceCheckUtils]: 97: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,736 INFO L290 TraceCheckUtils]: 98: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,736 INFO L290 TraceCheckUtils]: 99: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,737 INFO L290 TraceCheckUtils]: 100: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,737 INFO L290 TraceCheckUtils]: 101: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,738 INFO L290 TraceCheckUtils]: 102: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,738 INFO L290 TraceCheckUtils]: 103: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,738 INFO L290 TraceCheckUtils]: 104: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,739 INFO L290 TraceCheckUtils]: 105: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,739 INFO L290 TraceCheckUtils]: 106: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,748 INFO L290 TraceCheckUtils]: 107: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,748 INFO L290 TraceCheckUtils]: 108: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,749 INFO L290 TraceCheckUtils]: 109: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,749 INFO L290 TraceCheckUtils]: 110: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,750 INFO L290 TraceCheckUtils]: 111: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,750 INFO L290 TraceCheckUtils]: 112: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,750 INFO L290 TraceCheckUtils]: 113: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,751 INFO L290 TraceCheckUtils]: 114: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,751 INFO L290 TraceCheckUtils]: 115: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,751 INFO L290 TraceCheckUtils]: 116: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,752 INFO L290 TraceCheckUtils]: 117: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,752 INFO L290 TraceCheckUtils]: 118: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,753 INFO L290 TraceCheckUtils]: 119: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,753 INFO L290 TraceCheckUtils]: 120: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,753 INFO L290 TraceCheckUtils]: 121: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,754 INFO L290 TraceCheckUtils]: 122: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,754 INFO L290 TraceCheckUtils]: 123: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,754 INFO L290 TraceCheckUtils]: 124: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,755 INFO L290 TraceCheckUtils]: 125: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,755 INFO L290 TraceCheckUtils]: 126: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,756 INFO L290 TraceCheckUtils]: 127: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {42550#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:22,756 INFO L290 TraceCheckUtils]: 128: Hoare triple {42550#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {42549#false} is VALID [2022-02-21 04:23:22,756 INFO L290 TraceCheckUtils]: 129: Hoare triple {42549#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,756 INFO L290 TraceCheckUtils]: 130: Hoare triple {42549#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,756 INFO L290 TraceCheckUtils]: 131: Hoare triple {42549#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,757 INFO L290 TraceCheckUtils]: 132: Hoare triple {42549#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,757 INFO L290 TraceCheckUtils]: 133: Hoare triple {42549#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,757 INFO L290 TraceCheckUtils]: 134: Hoare triple {42549#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,757 INFO L290 TraceCheckUtils]: 135: Hoare triple {42549#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,757 INFO L290 TraceCheckUtils]: 136: Hoare triple {42549#false} assume !(1 == ~T13_E~0); {42549#false} is VALID [2022-02-21 04:23:22,757 INFO L290 TraceCheckUtils]: 137: Hoare triple {42549#false} assume 1 == ~E_M~0;~E_M~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,757 INFO L290 TraceCheckUtils]: 138: Hoare triple {42549#false} assume 1 == ~E_1~0;~E_1~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,758 INFO L290 TraceCheckUtils]: 139: Hoare triple {42549#false} assume 1 == ~E_2~0;~E_2~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,758 INFO L290 TraceCheckUtils]: 140: Hoare triple {42549#false} assume 1 == ~E_3~0;~E_3~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,758 INFO L290 TraceCheckUtils]: 141: Hoare triple {42549#false} assume 1 == ~E_4~0;~E_4~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,758 INFO L290 TraceCheckUtils]: 142: Hoare triple {42549#false} assume 1 == ~E_5~0;~E_5~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,758 INFO L290 TraceCheckUtils]: 143: Hoare triple {42549#false} assume 1 == ~E_6~0;~E_6~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,758 INFO L290 TraceCheckUtils]: 144: Hoare triple {42549#false} assume !(1 == ~E_7~0); {42549#false} is VALID [2022-02-21 04:23:22,758 INFO L290 TraceCheckUtils]: 145: Hoare triple {42549#false} assume 1 == ~E_8~0;~E_8~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,759 INFO L290 TraceCheckUtils]: 146: Hoare triple {42549#false} assume 1 == ~E_9~0;~E_9~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,759 INFO L290 TraceCheckUtils]: 147: Hoare triple {42549#false} assume 1 == ~E_10~0;~E_10~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,759 INFO L290 TraceCheckUtils]: 148: Hoare triple {42549#false} assume 1 == ~E_11~0;~E_11~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,759 INFO L290 TraceCheckUtils]: 149: Hoare triple {42549#false} assume 1 == ~E_12~0;~E_12~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,759 INFO L290 TraceCheckUtils]: 150: Hoare triple {42549#false} assume 1 == ~E_13~0;~E_13~0 := 2; {42549#false} is VALID [2022-02-21 04:23:22,759 INFO L290 TraceCheckUtils]: 151: Hoare triple {42549#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {42549#false} is VALID [2022-02-21 04:23:22,759 INFO L290 TraceCheckUtils]: 152: Hoare triple {42549#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {42549#false} is VALID [2022-02-21 04:23:22,760 INFO L290 TraceCheckUtils]: 153: Hoare triple {42549#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {42549#false} is VALID [2022-02-21 04:23:22,760 INFO L290 TraceCheckUtils]: 154: Hoare triple {42549#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {42549#false} is VALID [2022-02-21 04:23:22,760 INFO L290 TraceCheckUtils]: 155: Hoare triple {42549#false} assume !(0 == start_simulation_~tmp~3#1); {42549#false} is VALID [2022-02-21 04:23:22,760 INFO L290 TraceCheckUtils]: 156: Hoare triple {42549#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {42549#false} is VALID [2022-02-21 04:23:22,760 INFO L290 TraceCheckUtils]: 157: Hoare triple {42549#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {42549#false} is VALID [2022-02-21 04:23:22,760 INFO L290 TraceCheckUtils]: 158: Hoare triple {42549#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {42549#false} is VALID [2022-02-21 04:23:22,760 INFO L290 TraceCheckUtils]: 159: Hoare triple {42549#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {42549#false} is VALID [2022-02-21 04:23:22,761 INFO L290 TraceCheckUtils]: 160: Hoare triple {42549#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {42549#false} is VALID [2022-02-21 04:23:22,761 INFO L290 TraceCheckUtils]: 161: Hoare triple {42549#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {42549#false} is VALID [2022-02-21 04:23:22,761 INFO L290 TraceCheckUtils]: 162: Hoare triple {42549#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {42549#false} is VALID [2022-02-21 04:23:22,761 INFO L290 TraceCheckUtils]: 163: Hoare triple {42549#false} assume !(0 != start_simulation_~tmp___0~1#1); {42549#false} is VALID [2022-02-21 04:23:22,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:22,762 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:22,762 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335238773] [2022-02-21 04:23:22,762 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335238773] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:22,762 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:22,762 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:22,763 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992553707] [2022-02-21 04:23:22,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:22,763 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:22,763 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:22,764 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:22,764 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:22,764 INFO L87 Difference]: Start difference. First operand 2023 states and 2992 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,207 INFO L93 Difference]: Finished difference Result 2023 states and 2991 transitions. [2022-02-21 04:23:24,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:24,208 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,313 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:24,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2991 transitions. [2022-02-21 04:23:24,430 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:24,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2991 transitions. [2022-02-21 04:23:24,534 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:24,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:24,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2991 transitions. [2022-02-21 04:23:24,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:24,538 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2022-02-21 04:23:24,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2991 transitions. [2022-02-21 04:23:24,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:24,561 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:24,563 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2991 transitions. Second operand has 2023 states, 2023 states have (on average 1.4784972812654473) internal successors, (2991), 2022 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,565 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2991 transitions. Second operand has 2023 states, 2023 states have (on average 1.4784972812654473) internal successors, (2991), 2022 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,567 INFO L87 Difference]: Start difference. First operand 2023 states and 2991 transitions. Second operand has 2023 states, 2023 states have (on average 1.4784972812654473) internal successors, (2991), 2022 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,665 INFO L93 Difference]: Finished difference Result 2023 states and 2991 transitions. [2022-02-21 04:23:24,665 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2991 transitions. [2022-02-21 04:23:24,667 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:24,667 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:24,670 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4784972812654473) internal successors, (2991), 2022 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2991 transitions. [2022-02-21 04:23:24,672 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4784972812654473) internal successors, (2991), 2022 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2991 transitions. [2022-02-21 04:23:24,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,833 INFO L93 Difference]: Finished difference Result 2023 states and 2991 transitions. [2022-02-21 04:23:24,833 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2991 transitions. [2022-02-21 04:23:24,835 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:24,835 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:24,835 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:24,835 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:24,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4784972812654473) internal successors, (2991), 2022 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2991 transitions. [2022-02-21 04:23:24,951 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2022-02-21 04:23:24,951 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2022-02-21 04:23:24,951 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:23:24,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2991 transitions. [2022-02-21 04:23:24,954 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:24,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:24,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:24,955 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:24,955 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:24,956 INFO L791 eck$LassoCheckResult]: Stem: 45501#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45502#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46500#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46501#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46586#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 45965#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45434#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45435#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46251#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46252#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46352#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 46353#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 45206#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 45207#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46382#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 45742#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 45743#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 46303#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45644#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45645#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 46587#L1291-2 assume !(0 == ~T1_E~0); 46585#L1296-1 assume !(0 == ~T2_E~0); 45801#L1301-1 assume !(0 == ~T3_E~0); 45802#L1306-1 assume !(0 == ~T4_E~0); 46311#L1311-1 assume !(0 == ~T5_E~0); 45049#L1316-1 assume !(0 == ~T6_E~0); 45050#L1321-1 assume !(0 == ~T7_E~0); 45814#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44877#L1331-1 assume !(0 == ~T9_E~0); 44576#L1336-1 assume !(0 == ~T10_E~0); 44577#L1341-1 assume !(0 == ~T11_E~0); 44657#L1346-1 assume !(0 == ~T12_E~0); 44658#L1351-1 assume !(0 == ~T13_E~0); 44998#L1356-1 assume !(0 == ~E_M~0); 44999#L1361-1 assume !(0 == ~E_1~0); 46526#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 45039#L1371-1 assume !(0 == ~E_3~0); 45040#L1376-1 assume !(0 == ~E_4~0); 45861#L1381-1 assume !(0 == ~E_5~0); 45862#L1386-1 assume !(0 == ~E_6~0); 46556#L1391-1 assume !(0 == ~E_7~0); 46574#L1396-1 assume !(0 == ~E_8~0); 45774#L1401-1 assume !(0 == ~E_9~0); 45775#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46053#L1411-1 assume !(0 == ~E_11~0); 46054#L1416-1 assume !(0 == ~E_12~0); 45686#L1421-1 assume !(0 == ~E_13~0); 45229#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45230#L640 assume !(1 == ~m_pc~0); 45739#L640-2 is_master_triggered_~__retres1~0#1 := 0; 45738#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45830#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45724#L1603 assume !(0 != activate_threads_~tmp~1#1); 45725#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45359#L659 assume 1 == ~t1_pc~0; 45360#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45465#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46411#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45485#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 45486#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45499#L678 assume 1 == ~t2_pc~0; 46453#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46454#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46553#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45597#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 45598#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45719#L697 assume !(1 == ~t3_pc~0); 45720#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45842#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45650#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45629#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45630#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46490#L716 assume 1 == ~t4_pc~0; 46476#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45340#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45341#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44840#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 44841#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46132#L735 assume !(1 == ~t5_pc~0); 44801#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 44802#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45252#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46159#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 45795#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45796#L754 assume 1 == ~t6_pc~0; 45549#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45447#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45448#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45421#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 45422#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46242#L773 assume !(1 == ~t7_pc~0); 45002#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45001#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45831#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45803#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 45804#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45851#L792 assume 1 == ~t8_pc~0; 46024#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46356#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45845#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45798#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 45722#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45723#L811 assume 1 == ~t9_pc~0; 45927#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46393#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46269#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45923#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 45735#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45736#L830 assume !(1 == ~t10_pc~0); 45457#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44981#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44674#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44675#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44962#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46260#L849 assume 1 == ~t11_pc~0; 46261#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44777#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44778#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45367#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 46166#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46167#L868 assume !(1 == ~t12_pc~0); 45582#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45581#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45376#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45377#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 45013#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45014#L887 assume 1 == ~t13_pc~0; 46181#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45623#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45624#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46060#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 44717#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44718#L1439 assume !(1 == ~M_E~0); 45791#L1439-2 assume !(1 == ~T1_E~0); 44889#L1444-1 assume !(1 == ~T2_E~0); 44890#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45363#L1454-1 assume !(1 == ~T4_E~0); 45364#L1459-1 assume !(1 == ~T5_E~0); 45920#L1464-1 assume !(1 == ~T6_E~0); 45921#L1469-1 assume !(1 == ~T7_E~0); 45993#L1474-1 assume !(1 == ~T8_E~0); 45687#L1479-1 assume !(1 == ~T9_E~0); 45688#L1484-1 assume !(1 == ~T10_E~0); 45924#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45570#L1494-1 assume !(1 == ~T12_E~0); 45571#L1499-1 assume !(1 == ~T13_E~0); 45763#L1504-1 assume !(1 == ~E_M~0); 45764#L1509-1 assume !(1 == ~E_1~0); 46339#L1514-1 assume !(1 == ~E_2~0); 46026#L1519-1 assume !(1 == ~E_3~0); 46027#L1524-1 assume !(1 == ~E_4~0); 46539#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46540#L1534-1 assume !(1 == ~E_6~0); 44710#L1539-1 assume !(1 == ~E_7~0); 44711#L1544-1 assume !(1 == ~E_8~0); 45125#L1549-1 assume !(1 == ~E_9~0); 46514#L1554-1 assume !(1 == ~E_10~0); 46510#L1559-1 assume !(1 == ~E_11~0); 46377#L1564-1 assume !(1 == ~E_12~0); 46378#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46535#L1574-1 assume { :end_inline_reset_delta_events } true; 44887#L1940-2 [2022-02-21 04:23:24,956 INFO L793 eck$LassoCheckResult]: Loop: 44887#L1940-2 assume !false; 44888#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45170#L1266 assume !false; 46189#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45418#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45151#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45542#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 45543#L1079 assume !(0 != eval_~tmp~0#1); 45504#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45505#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46109#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45994#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45995#L1296-3 assume !(0 == ~T2_E~0); 46567#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46521#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45652#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44928#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44929#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45029#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45786#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46035#L1336-3 assume !(0 == ~T10_E~0); 46036#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45356#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45336#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45281#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45282#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45843#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44632#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44633#L1376-3 assume !(0 == ~E_4~0); 46362#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46222#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46223#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46385#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46386#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44995#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44849#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44850#L1416-3 assume !(0 == ~E_12~0); 45511#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45512#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45619#L640-45 assume !(1 == ~m_pc~0); 45620#L640-47 is_master_triggered_~__retres1~0#1 := 0; 45086#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45087#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44626#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44627#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44725#L659-45 assume 1 == ~t1_pc~0; 44726#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45165#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46124#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46125#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46146#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46147#L678-45 assume 1 == ~t2_pc~0; 46090#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45625#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45626#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45778#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46403#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46520#L697-45 assume 1 == ~t3_pc~0; 45883#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45884#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46472#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46042#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46043#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46073#L716-45 assume 1 == ~t4_pc~0; 45704#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45705#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46255#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45710#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45711#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45373#L735-45 assume 1 == ~t5_pc~0; 45374#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45917#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46479#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46480#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46538#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46533#L754-45 assume 1 == ~t6_pc~0; 45865#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45866#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45295#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45296#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45869#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45601#L773-45 assume 1 == ~t7_pc~0; 45602#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45159#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46079#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46361#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 45607#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45277#L792-45 assume 1 == ~t8_pc~0; 45278#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46307#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44880#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44739#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44740#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45235#L811-45 assume 1 == ~t9_pc~0; 45024#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45026#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46234#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46069#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45678#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45470#L830-45 assume !(1 == ~t10_pc~0); 44667#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 44668#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45790#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44900#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44901#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44646#L849-45 assume !(1 == ~t11_pc~0); 44647#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45106#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44737#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44634#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44635#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44893#L868-45 assume 1 == ~t12_pc~0; 44894#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44833#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44834#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46172#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46423#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46424#L887-45 assume !(1 == ~t13_pc~0); 44902#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 44903#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46185#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46530#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 44865#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44866#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46173#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44885#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44886#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45043#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45974#L1459-3 assume !(1 == ~T5_E~0); 45975#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46426#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46365#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46366#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46427#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45659#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45660#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46296#L1499-3 assume !(1 == ~T13_E~0); 45935#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45936#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46374#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46404#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45578#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45579#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46446#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45846#L1539-3 assume !(1 == ~E_7~0); 45322#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45323#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45818#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44939#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44940#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46074#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46075#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44816#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44587#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44862#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 44823#L1959 assume !(0 == start_simulation_~tmp~3#1); 44825#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44857#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44807#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46116#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46237#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46444#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46458#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46459#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 44887#L1940-2 [2022-02-21 04:23:24,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:24,957 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2022-02-21 04:23:24,957 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:24,957 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653259343] [2022-02-21 04:23:24,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:24,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:24,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:24,994 INFO L290 TraceCheckUtils]: 0: Hoare triple {50646#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {50646#true} is VALID [2022-02-21 04:23:24,994 INFO L290 TraceCheckUtils]: 1: Hoare triple {50646#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {50648#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:24,995 INFO L290 TraceCheckUtils]: 2: Hoare triple {50648#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {50648#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:24,995 INFO L290 TraceCheckUtils]: 3: Hoare triple {50648#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {50648#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:24,995 INFO L290 TraceCheckUtils]: 4: Hoare triple {50648#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {50648#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:24,996 INFO L290 TraceCheckUtils]: 5: Hoare triple {50648#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {50648#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:24,996 INFO L290 TraceCheckUtils]: 6: Hoare triple {50648#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {50648#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:24,996 INFO L290 TraceCheckUtils]: 7: Hoare triple {50648#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {50648#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:24,997 INFO L290 TraceCheckUtils]: 8: Hoare triple {50648#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {50648#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:24,997 INFO L290 TraceCheckUtils]: 9: Hoare triple {50648#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {50648#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:24,997 INFO L290 TraceCheckUtils]: 10: Hoare triple {50648#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {50647#false} is VALID [2022-02-21 04:23:24,997 INFO L290 TraceCheckUtils]: 11: Hoare triple {50647#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {50647#false} is VALID [2022-02-21 04:23:24,998 INFO L290 TraceCheckUtils]: 12: Hoare triple {50647#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {50647#false} is VALID [2022-02-21 04:23:24,998 INFO L290 TraceCheckUtils]: 13: Hoare triple {50647#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {50647#false} is VALID [2022-02-21 04:23:24,998 INFO L290 TraceCheckUtils]: 14: Hoare triple {50647#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {50647#false} is VALID [2022-02-21 04:23:24,998 INFO L290 TraceCheckUtils]: 15: Hoare triple {50647#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {50647#false} is VALID [2022-02-21 04:23:24,998 INFO L290 TraceCheckUtils]: 16: Hoare triple {50647#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {50647#false} is VALID [2022-02-21 04:23:24,998 INFO L290 TraceCheckUtils]: 17: Hoare triple {50647#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {50647#false} is VALID [2022-02-21 04:23:24,998 INFO L290 TraceCheckUtils]: 18: Hoare triple {50647#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {50647#false} is VALID [2022-02-21 04:23:24,999 INFO L290 TraceCheckUtils]: 19: Hoare triple {50647#false} assume 0 == ~M_E~0;~M_E~0 := 1; {50647#false} is VALID [2022-02-21 04:23:24,999 INFO L290 TraceCheckUtils]: 20: Hoare triple {50647#false} assume !(0 == ~T1_E~0); {50647#false} is VALID [2022-02-21 04:23:24,999 INFO L290 TraceCheckUtils]: 21: Hoare triple {50647#false} assume !(0 == ~T2_E~0); {50647#false} is VALID [2022-02-21 04:23:24,999 INFO L290 TraceCheckUtils]: 22: Hoare triple {50647#false} assume !(0 == ~T3_E~0); {50647#false} is VALID [2022-02-21 04:23:24,999 INFO L290 TraceCheckUtils]: 23: Hoare triple {50647#false} assume !(0 == ~T4_E~0); {50647#false} is VALID [2022-02-21 04:23:24,999 INFO L290 TraceCheckUtils]: 24: Hoare triple {50647#false} assume !(0 == ~T5_E~0); {50647#false} is VALID [2022-02-21 04:23:24,999 INFO L290 TraceCheckUtils]: 25: Hoare triple {50647#false} assume !(0 == ~T6_E~0); {50647#false} is VALID [2022-02-21 04:23:25,000 INFO L290 TraceCheckUtils]: 26: Hoare triple {50647#false} assume !(0 == ~T7_E~0); {50647#false} is VALID [2022-02-21 04:23:25,000 INFO L290 TraceCheckUtils]: 27: Hoare triple {50647#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {50647#false} is VALID [2022-02-21 04:23:25,000 INFO L290 TraceCheckUtils]: 28: Hoare triple {50647#false} assume !(0 == ~T9_E~0); {50647#false} is VALID [2022-02-21 04:23:25,000 INFO L290 TraceCheckUtils]: 29: Hoare triple {50647#false} assume !(0 == ~T10_E~0); {50647#false} is VALID [2022-02-21 04:23:25,000 INFO L290 TraceCheckUtils]: 30: Hoare triple {50647#false} assume !(0 == ~T11_E~0); {50647#false} is VALID [2022-02-21 04:23:25,000 INFO L290 TraceCheckUtils]: 31: Hoare triple {50647#false} assume !(0 == ~T12_E~0); {50647#false} is VALID [2022-02-21 04:23:25,001 INFO L290 TraceCheckUtils]: 32: Hoare triple {50647#false} assume !(0 == ~T13_E~0); {50647#false} is VALID [2022-02-21 04:23:25,001 INFO L290 TraceCheckUtils]: 33: Hoare triple {50647#false} assume !(0 == ~E_M~0); {50647#false} is VALID [2022-02-21 04:23:25,001 INFO L290 TraceCheckUtils]: 34: Hoare triple {50647#false} assume !(0 == ~E_1~0); {50647#false} is VALID [2022-02-21 04:23:25,001 INFO L290 TraceCheckUtils]: 35: Hoare triple {50647#false} assume 0 == ~E_2~0;~E_2~0 := 1; {50647#false} is VALID [2022-02-21 04:23:25,001 INFO L290 TraceCheckUtils]: 36: Hoare triple {50647#false} assume !(0 == ~E_3~0); {50647#false} is VALID [2022-02-21 04:23:25,001 INFO L290 TraceCheckUtils]: 37: Hoare triple {50647#false} assume !(0 == ~E_4~0); {50647#false} is VALID [2022-02-21 04:23:25,001 INFO L290 TraceCheckUtils]: 38: Hoare triple {50647#false} assume !(0 == ~E_5~0); {50647#false} is VALID [2022-02-21 04:23:25,002 INFO L290 TraceCheckUtils]: 39: Hoare triple {50647#false} assume !(0 == ~E_6~0); {50647#false} is VALID [2022-02-21 04:23:25,002 INFO L290 TraceCheckUtils]: 40: Hoare triple {50647#false} assume !(0 == ~E_7~0); {50647#false} is VALID [2022-02-21 04:23:25,002 INFO L290 TraceCheckUtils]: 41: Hoare triple {50647#false} assume !(0 == ~E_8~0); {50647#false} is VALID [2022-02-21 04:23:25,002 INFO L290 TraceCheckUtils]: 42: Hoare triple {50647#false} assume !(0 == ~E_9~0); {50647#false} is VALID [2022-02-21 04:23:25,002 INFO L290 TraceCheckUtils]: 43: Hoare triple {50647#false} assume 0 == ~E_10~0;~E_10~0 := 1; {50647#false} is VALID [2022-02-21 04:23:25,002 INFO L290 TraceCheckUtils]: 44: Hoare triple {50647#false} assume !(0 == ~E_11~0); {50647#false} is VALID [2022-02-21 04:23:25,002 INFO L290 TraceCheckUtils]: 45: Hoare triple {50647#false} assume !(0 == ~E_12~0); {50647#false} is VALID [2022-02-21 04:23:25,003 INFO L290 TraceCheckUtils]: 46: Hoare triple {50647#false} assume !(0 == ~E_13~0); {50647#false} is VALID [2022-02-21 04:23:25,003 INFO L290 TraceCheckUtils]: 47: Hoare triple {50647#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {50647#false} is VALID [2022-02-21 04:23:25,003 INFO L290 TraceCheckUtils]: 48: Hoare triple {50647#false} assume !(1 == ~m_pc~0); {50647#false} is VALID [2022-02-21 04:23:25,003 INFO L290 TraceCheckUtils]: 49: Hoare triple {50647#false} is_master_triggered_~__retres1~0#1 := 0; {50647#false} is VALID [2022-02-21 04:23:25,003 INFO L290 TraceCheckUtils]: 50: Hoare triple {50647#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {50647#false} is VALID [2022-02-21 04:23:25,003 INFO L290 TraceCheckUtils]: 51: Hoare triple {50647#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {50647#false} is VALID [2022-02-21 04:23:25,003 INFO L290 TraceCheckUtils]: 52: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp~1#1); {50647#false} is VALID [2022-02-21 04:23:25,004 INFO L290 TraceCheckUtils]: 53: Hoare triple {50647#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {50647#false} is VALID [2022-02-21 04:23:25,004 INFO L290 TraceCheckUtils]: 54: Hoare triple {50647#false} assume 1 == ~t1_pc~0; {50647#false} is VALID [2022-02-21 04:23:25,004 INFO L290 TraceCheckUtils]: 55: Hoare triple {50647#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {50647#false} is VALID [2022-02-21 04:23:25,004 INFO L290 TraceCheckUtils]: 56: Hoare triple {50647#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {50647#false} is VALID [2022-02-21 04:23:25,004 INFO L290 TraceCheckUtils]: 57: Hoare triple {50647#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {50647#false} is VALID [2022-02-21 04:23:25,004 INFO L290 TraceCheckUtils]: 58: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___0~0#1); {50647#false} is VALID [2022-02-21 04:23:25,004 INFO L290 TraceCheckUtils]: 59: Hoare triple {50647#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {50647#false} is VALID [2022-02-21 04:23:25,005 INFO L290 TraceCheckUtils]: 60: Hoare triple {50647#false} assume 1 == ~t2_pc~0; {50647#false} is VALID [2022-02-21 04:23:25,005 INFO L290 TraceCheckUtils]: 61: Hoare triple {50647#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {50647#false} is VALID [2022-02-21 04:23:25,005 INFO L290 TraceCheckUtils]: 62: Hoare triple {50647#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {50647#false} is VALID [2022-02-21 04:23:25,005 INFO L290 TraceCheckUtils]: 63: Hoare triple {50647#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {50647#false} is VALID [2022-02-21 04:23:25,005 INFO L290 TraceCheckUtils]: 64: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___1~0#1); {50647#false} is VALID [2022-02-21 04:23:25,005 INFO L290 TraceCheckUtils]: 65: Hoare triple {50647#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {50647#false} is VALID [2022-02-21 04:23:25,005 INFO L290 TraceCheckUtils]: 66: Hoare triple {50647#false} assume !(1 == ~t3_pc~0); {50647#false} is VALID [2022-02-21 04:23:25,006 INFO L290 TraceCheckUtils]: 67: Hoare triple {50647#false} is_transmit3_triggered_~__retres1~3#1 := 0; {50647#false} is VALID [2022-02-21 04:23:25,006 INFO L290 TraceCheckUtils]: 68: Hoare triple {50647#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {50647#false} is VALID [2022-02-21 04:23:25,006 INFO L290 TraceCheckUtils]: 69: Hoare triple {50647#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {50647#false} is VALID [2022-02-21 04:23:25,006 INFO L290 TraceCheckUtils]: 70: Hoare triple {50647#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {50647#false} is VALID [2022-02-21 04:23:25,006 INFO L290 TraceCheckUtils]: 71: Hoare triple {50647#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {50647#false} is VALID [2022-02-21 04:23:25,006 INFO L290 TraceCheckUtils]: 72: Hoare triple {50647#false} assume 1 == ~t4_pc~0; {50647#false} is VALID [2022-02-21 04:23:25,006 INFO L290 TraceCheckUtils]: 73: Hoare triple {50647#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {50647#false} is VALID [2022-02-21 04:23:25,007 INFO L290 TraceCheckUtils]: 74: Hoare triple {50647#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {50647#false} is VALID [2022-02-21 04:23:25,007 INFO L290 TraceCheckUtils]: 75: Hoare triple {50647#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {50647#false} is VALID [2022-02-21 04:23:25,007 INFO L290 TraceCheckUtils]: 76: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___3~0#1); {50647#false} is VALID [2022-02-21 04:23:25,007 INFO L290 TraceCheckUtils]: 77: Hoare triple {50647#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {50647#false} is VALID [2022-02-21 04:23:25,007 INFO L290 TraceCheckUtils]: 78: Hoare triple {50647#false} assume !(1 == ~t5_pc~0); {50647#false} is VALID [2022-02-21 04:23:25,007 INFO L290 TraceCheckUtils]: 79: Hoare triple {50647#false} is_transmit5_triggered_~__retres1~5#1 := 0; {50647#false} is VALID [2022-02-21 04:23:25,007 INFO L290 TraceCheckUtils]: 80: Hoare triple {50647#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {50647#false} is VALID [2022-02-21 04:23:25,008 INFO L290 TraceCheckUtils]: 81: Hoare triple {50647#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {50647#false} is VALID [2022-02-21 04:23:25,008 INFO L290 TraceCheckUtils]: 82: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___4~0#1); {50647#false} is VALID [2022-02-21 04:23:25,008 INFO L290 TraceCheckUtils]: 83: Hoare triple {50647#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {50647#false} is VALID [2022-02-21 04:23:25,008 INFO L290 TraceCheckUtils]: 84: Hoare triple {50647#false} assume 1 == ~t6_pc~0; {50647#false} is VALID [2022-02-21 04:23:25,008 INFO L290 TraceCheckUtils]: 85: Hoare triple {50647#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {50647#false} is VALID [2022-02-21 04:23:25,008 INFO L290 TraceCheckUtils]: 86: Hoare triple {50647#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {50647#false} is VALID [2022-02-21 04:23:25,008 INFO L290 TraceCheckUtils]: 87: Hoare triple {50647#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {50647#false} is VALID [2022-02-21 04:23:25,009 INFO L290 TraceCheckUtils]: 88: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___5~0#1); {50647#false} is VALID [2022-02-21 04:23:25,009 INFO L290 TraceCheckUtils]: 89: Hoare triple {50647#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {50647#false} is VALID [2022-02-21 04:23:25,009 INFO L290 TraceCheckUtils]: 90: Hoare triple {50647#false} assume !(1 == ~t7_pc~0); {50647#false} is VALID [2022-02-21 04:23:25,009 INFO L290 TraceCheckUtils]: 91: Hoare triple {50647#false} is_transmit7_triggered_~__retres1~7#1 := 0; {50647#false} is VALID [2022-02-21 04:23:25,009 INFO L290 TraceCheckUtils]: 92: Hoare triple {50647#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {50647#false} is VALID [2022-02-21 04:23:25,009 INFO L290 TraceCheckUtils]: 93: Hoare triple {50647#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {50647#false} is VALID [2022-02-21 04:23:25,009 INFO L290 TraceCheckUtils]: 94: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___6~0#1); {50647#false} is VALID [2022-02-21 04:23:25,010 INFO L290 TraceCheckUtils]: 95: Hoare triple {50647#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {50647#false} is VALID [2022-02-21 04:23:25,010 INFO L290 TraceCheckUtils]: 96: Hoare triple {50647#false} assume 1 == ~t8_pc~0; {50647#false} is VALID [2022-02-21 04:23:25,010 INFO L290 TraceCheckUtils]: 97: Hoare triple {50647#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {50647#false} is VALID [2022-02-21 04:23:25,010 INFO L290 TraceCheckUtils]: 98: Hoare triple {50647#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {50647#false} is VALID [2022-02-21 04:23:25,010 INFO L290 TraceCheckUtils]: 99: Hoare triple {50647#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {50647#false} is VALID [2022-02-21 04:23:25,010 INFO L290 TraceCheckUtils]: 100: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___7~0#1); {50647#false} is VALID [2022-02-21 04:23:25,011 INFO L290 TraceCheckUtils]: 101: Hoare triple {50647#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {50647#false} is VALID [2022-02-21 04:23:25,011 INFO L290 TraceCheckUtils]: 102: Hoare triple {50647#false} assume 1 == ~t9_pc~0; {50647#false} is VALID [2022-02-21 04:23:25,011 INFO L290 TraceCheckUtils]: 103: Hoare triple {50647#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {50647#false} is VALID [2022-02-21 04:23:25,011 INFO L290 TraceCheckUtils]: 104: Hoare triple {50647#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {50647#false} is VALID [2022-02-21 04:23:25,011 INFO L290 TraceCheckUtils]: 105: Hoare triple {50647#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {50647#false} is VALID [2022-02-21 04:23:25,011 INFO L290 TraceCheckUtils]: 106: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___8~0#1); {50647#false} is VALID [2022-02-21 04:23:25,011 INFO L290 TraceCheckUtils]: 107: Hoare triple {50647#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {50647#false} is VALID [2022-02-21 04:23:25,012 INFO L290 TraceCheckUtils]: 108: Hoare triple {50647#false} assume !(1 == ~t10_pc~0); {50647#false} is VALID [2022-02-21 04:23:25,012 INFO L290 TraceCheckUtils]: 109: Hoare triple {50647#false} is_transmit10_triggered_~__retres1~10#1 := 0; {50647#false} is VALID [2022-02-21 04:23:25,012 INFO L290 TraceCheckUtils]: 110: Hoare triple {50647#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {50647#false} is VALID [2022-02-21 04:23:25,012 INFO L290 TraceCheckUtils]: 111: Hoare triple {50647#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {50647#false} is VALID [2022-02-21 04:23:25,012 INFO L290 TraceCheckUtils]: 112: Hoare triple {50647#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {50647#false} is VALID [2022-02-21 04:23:25,012 INFO L290 TraceCheckUtils]: 113: Hoare triple {50647#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {50647#false} is VALID [2022-02-21 04:23:25,012 INFO L290 TraceCheckUtils]: 114: Hoare triple {50647#false} assume 1 == ~t11_pc~0; {50647#false} is VALID [2022-02-21 04:23:25,013 INFO L290 TraceCheckUtils]: 115: Hoare triple {50647#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {50647#false} is VALID [2022-02-21 04:23:25,013 INFO L290 TraceCheckUtils]: 116: Hoare triple {50647#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {50647#false} is VALID [2022-02-21 04:23:25,013 INFO L290 TraceCheckUtils]: 117: Hoare triple {50647#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {50647#false} is VALID [2022-02-21 04:23:25,013 INFO L290 TraceCheckUtils]: 118: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___10~0#1); {50647#false} is VALID [2022-02-21 04:23:25,013 INFO L290 TraceCheckUtils]: 119: Hoare triple {50647#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {50647#false} is VALID [2022-02-21 04:23:25,013 INFO L290 TraceCheckUtils]: 120: Hoare triple {50647#false} assume !(1 == ~t12_pc~0); {50647#false} is VALID [2022-02-21 04:23:25,013 INFO L290 TraceCheckUtils]: 121: Hoare triple {50647#false} is_transmit12_triggered_~__retres1~12#1 := 0; {50647#false} is VALID [2022-02-21 04:23:25,014 INFO L290 TraceCheckUtils]: 122: Hoare triple {50647#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {50647#false} is VALID [2022-02-21 04:23:25,014 INFO L290 TraceCheckUtils]: 123: Hoare triple {50647#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {50647#false} is VALID [2022-02-21 04:23:25,014 INFO L290 TraceCheckUtils]: 124: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___11~0#1); {50647#false} is VALID [2022-02-21 04:23:25,014 INFO L290 TraceCheckUtils]: 125: Hoare triple {50647#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {50647#false} is VALID [2022-02-21 04:23:25,014 INFO L290 TraceCheckUtils]: 126: Hoare triple {50647#false} assume 1 == ~t13_pc~0; {50647#false} is VALID [2022-02-21 04:23:25,014 INFO L290 TraceCheckUtils]: 127: Hoare triple {50647#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {50647#false} is VALID [2022-02-21 04:23:25,014 INFO L290 TraceCheckUtils]: 128: Hoare triple {50647#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {50647#false} is VALID [2022-02-21 04:23:25,015 INFO L290 TraceCheckUtils]: 129: Hoare triple {50647#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {50647#false} is VALID [2022-02-21 04:23:25,015 INFO L290 TraceCheckUtils]: 130: Hoare triple {50647#false} assume !(0 != activate_threads_~tmp___12~0#1); {50647#false} is VALID [2022-02-21 04:23:25,015 INFO L290 TraceCheckUtils]: 131: Hoare triple {50647#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {50647#false} is VALID [2022-02-21 04:23:25,015 INFO L290 TraceCheckUtils]: 132: Hoare triple {50647#false} assume !(1 == ~M_E~0); {50647#false} is VALID [2022-02-21 04:23:25,015 INFO L290 TraceCheckUtils]: 133: Hoare triple {50647#false} assume !(1 == ~T1_E~0); {50647#false} is VALID [2022-02-21 04:23:25,015 INFO L290 TraceCheckUtils]: 134: Hoare triple {50647#false} assume !(1 == ~T2_E~0); {50647#false} is VALID [2022-02-21 04:23:25,016 INFO L290 TraceCheckUtils]: 135: Hoare triple {50647#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {50647#false} is VALID [2022-02-21 04:23:25,016 INFO L290 TraceCheckUtils]: 136: Hoare triple {50647#false} assume !(1 == ~T4_E~0); {50647#false} is VALID [2022-02-21 04:23:25,016 INFO L290 TraceCheckUtils]: 137: Hoare triple {50647#false} assume !(1 == ~T5_E~0); {50647#false} is VALID [2022-02-21 04:23:25,016 INFO L290 TraceCheckUtils]: 138: Hoare triple {50647#false} assume !(1 == ~T6_E~0); {50647#false} is VALID [2022-02-21 04:23:25,016 INFO L290 TraceCheckUtils]: 139: Hoare triple {50647#false} assume !(1 == ~T7_E~0); {50647#false} is VALID [2022-02-21 04:23:25,016 INFO L290 TraceCheckUtils]: 140: Hoare triple {50647#false} assume !(1 == ~T8_E~0); {50647#false} is VALID [2022-02-21 04:23:25,016 INFO L290 TraceCheckUtils]: 141: Hoare triple {50647#false} assume !(1 == ~T9_E~0); {50647#false} is VALID [2022-02-21 04:23:25,016 INFO L290 TraceCheckUtils]: 142: Hoare triple {50647#false} assume !(1 == ~T10_E~0); {50647#false} is VALID [2022-02-21 04:23:25,017 INFO L290 TraceCheckUtils]: 143: Hoare triple {50647#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {50647#false} is VALID [2022-02-21 04:23:25,017 INFO L290 TraceCheckUtils]: 144: Hoare triple {50647#false} assume !(1 == ~T12_E~0); {50647#false} is VALID [2022-02-21 04:23:25,017 INFO L290 TraceCheckUtils]: 145: Hoare triple {50647#false} assume !(1 == ~T13_E~0); {50647#false} is VALID [2022-02-21 04:23:25,017 INFO L290 TraceCheckUtils]: 146: Hoare triple {50647#false} assume !(1 == ~E_M~0); {50647#false} is VALID [2022-02-21 04:23:25,017 INFO L290 TraceCheckUtils]: 147: Hoare triple {50647#false} assume !(1 == ~E_1~0); {50647#false} is VALID [2022-02-21 04:23:25,017 INFO L290 TraceCheckUtils]: 148: Hoare triple {50647#false} assume !(1 == ~E_2~0); {50647#false} is VALID [2022-02-21 04:23:25,017 INFO L290 TraceCheckUtils]: 149: Hoare triple {50647#false} assume !(1 == ~E_3~0); {50647#false} is VALID [2022-02-21 04:23:25,018 INFO L290 TraceCheckUtils]: 150: Hoare triple {50647#false} assume !(1 == ~E_4~0); {50647#false} is VALID [2022-02-21 04:23:25,018 INFO L290 TraceCheckUtils]: 151: Hoare triple {50647#false} assume 1 == ~E_5~0;~E_5~0 := 2; {50647#false} is VALID [2022-02-21 04:23:25,018 INFO L290 TraceCheckUtils]: 152: Hoare triple {50647#false} assume !(1 == ~E_6~0); {50647#false} is VALID [2022-02-21 04:23:25,018 INFO L290 TraceCheckUtils]: 153: Hoare triple {50647#false} assume !(1 == ~E_7~0); {50647#false} is VALID [2022-02-21 04:23:25,018 INFO L290 TraceCheckUtils]: 154: Hoare triple {50647#false} assume !(1 == ~E_8~0); {50647#false} is VALID [2022-02-21 04:23:25,018 INFO L290 TraceCheckUtils]: 155: Hoare triple {50647#false} assume !(1 == ~E_9~0); {50647#false} is VALID [2022-02-21 04:23:25,018 INFO L290 TraceCheckUtils]: 156: Hoare triple {50647#false} assume !(1 == ~E_10~0); {50647#false} is VALID [2022-02-21 04:23:25,019 INFO L290 TraceCheckUtils]: 157: Hoare triple {50647#false} assume !(1 == ~E_11~0); {50647#false} is VALID [2022-02-21 04:23:25,019 INFO L290 TraceCheckUtils]: 158: Hoare triple {50647#false} assume !(1 == ~E_12~0); {50647#false} is VALID [2022-02-21 04:23:25,019 INFO L290 TraceCheckUtils]: 159: Hoare triple {50647#false} assume 1 == ~E_13~0;~E_13~0 := 2; {50647#false} is VALID [2022-02-21 04:23:25,019 INFO L290 TraceCheckUtils]: 160: Hoare triple {50647#false} assume { :end_inline_reset_delta_events } true; {50647#false} is VALID [2022-02-21 04:23:25,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:25,020 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:25,020 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653259343] [2022-02-21 04:23:25,020 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1653259343] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:25,020 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:25,020 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:25,021 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753399114] [2022-02-21 04:23:25,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:25,021 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:25,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:25,022 INFO L85 PathProgramCache]: Analyzing trace with hash 1630672670, now seen corresponding path program 1 times [2022-02-21 04:23:25,022 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:25,022 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557096959] [2022-02-21 04:23:25,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:25,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:25,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 0: Hoare triple {50649#true} assume !false; {50649#true} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 1: Hoare triple {50649#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {50649#true} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 2: Hoare triple {50649#true} assume !false; {50649#true} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 3: Hoare triple {50649#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {50649#true} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 4: Hoare triple {50649#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {50649#true} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 5: Hoare triple {50649#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {50649#true} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 6: Hoare triple {50649#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {50649#true} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 7: Hoare triple {50649#true} assume !(0 != eval_~tmp~0#1); {50649#true} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 8: Hoare triple {50649#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {50649#true} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 9: Hoare triple {50649#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {50649#true} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 10: Hoare triple {50649#true} assume 0 == ~M_E~0;~M_E~0 := 1; {50649#true} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 11: Hoare triple {50649#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {50649#true} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 12: Hoare triple {50649#true} assume !(0 == ~T2_E~0); {50649#true} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 13: Hoare triple {50649#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {50649#true} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 14: Hoare triple {50649#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {50649#true} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 15: Hoare triple {50649#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,065 INFO L290 TraceCheckUtils]: 16: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,065 INFO L290 TraceCheckUtils]: 17: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,065 INFO L290 TraceCheckUtils]: 18: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,066 INFO L290 TraceCheckUtils]: 19: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,066 INFO L290 TraceCheckUtils]: 20: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,066 INFO L290 TraceCheckUtils]: 21: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,067 INFO L290 TraceCheckUtils]: 22: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,067 INFO L290 TraceCheckUtils]: 23: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,068 INFO L290 TraceCheckUtils]: 24: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,068 INFO L290 TraceCheckUtils]: 25: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,068 INFO L290 TraceCheckUtils]: 26: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,069 INFO L290 TraceCheckUtils]: 27: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,069 INFO L290 TraceCheckUtils]: 28: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,069 INFO L290 TraceCheckUtils]: 29: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,070 INFO L290 TraceCheckUtils]: 30: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,070 INFO L290 TraceCheckUtils]: 31: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,071 INFO L290 TraceCheckUtils]: 32: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,071 INFO L290 TraceCheckUtils]: 33: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,071 INFO L290 TraceCheckUtils]: 34: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,072 INFO L290 TraceCheckUtils]: 35: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,072 INFO L290 TraceCheckUtils]: 36: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,072 INFO L290 TraceCheckUtils]: 37: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,073 INFO L290 TraceCheckUtils]: 38: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,073 INFO L290 TraceCheckUtils]: 39: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,074 INFO L290 TraceCheckUtils]: 40: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,074 INFO L290 TraceCheckUtils]: 41: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,074 INFO L290 TraceCheckUtils]: 42: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,075 INFO L290 TraceCheckUtils]: 43: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,075 INFO L290 TraceCheckUtils]: 44: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,075 INFO L290 TraceCheckUtils]: 45: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,076 INFO L290 TraceCheckUtils]: 46: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,076 INFO L290 TraceCheckUtils]: 47: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,077 INFO L290 TraceCheckUtils]: 48: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,077 INFO L290 TraceCheckUtils]: 49: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,077 INFO L290 TraceCheckUtils]: 50: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,078 INFO L290 TraceCheckUtils]: 51: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,078 INFO L290 TraceCheckUtils]: 52: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,078 INFO L290 TraceCheckUtils]: 53: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,079 INFO L290 TraceCheckUtils]: 54: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,079 INFO L290 TraceCheckUtils]: 55: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,079 INFO L290 TraceCheckUtils]: 56: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,080 INFO L290 TraceCheckUtils]: 57: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,080 INFO L290 TraceCheckUtils]: 58: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,081 INFO L290 TraceCheckUtils]: 59: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,081 INFO L290 TraceCheckUtils]: 60: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,081 INFO L290 TraceCheckUtils]: 61: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,082 INFO L290 TraceCheckUtils]: 62: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,082 INFO L290 TraceCheckUtils]: 63: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,082 INFO L290 TraceCheckUtils]: 64: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,083 INFO L290 TraceCheckUtils]: 65: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,083 INFO L290 TraceCheckUtils]: 66: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,084 INFO L290 TraceCheckUtils]: 67: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,084 INFO L290 TraceCheckUtils]: 68: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,084 INFO L290 TraceCheckUtils]: 69: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,085 INFO L290 TraceCheckUtils]: 70: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,085 INFO L290 TraceCheckUtils]: 71: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,085 INFO L290 TraceCheckUtils]: 72: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,086 INFO L290 TraceCheckUtils]: 73: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,086 INFO L290 TraceCheckUtils]: 74: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,087 INFO L290 TraceCheckUtils]: 75: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,087 INFO L290 TraceCheckUtils]: 76: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,087 INFO L290 TraceCheckUtils]: 77: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,088 INFO L290 TraceCheckUtils]: 78: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,088 INFO L290 TraceCheckUtils]: 79: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,088 INFO L290 TraceCheckUtils]: 80: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 81: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 82: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 83: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 84: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 85: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 86: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 87: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 88: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 89: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 90: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 91: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 92: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 93: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 94: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 95: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 96: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 97: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 98: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 99: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 100: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 101: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 102: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 103: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 104: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 105: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 106: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 107: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 108: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 109: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 110: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 111: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 112: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 113: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 114: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 115: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 116: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 117: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 118: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 119: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 120: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 121: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 122: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 123: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 124: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 125: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 126: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 127: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {50651#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 128: Hoare triple {50651#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {50650#false} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 129: Hoare triple {50650#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 130: Hoare triple {50650#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 131: Hoare triple {50650#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 132: Hoare triple {50650#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 133: Hoare triple {50650#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 134: Hoare triple {50650#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 135: Hoare triple {50650#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 136: Hoare triple {50650#false} assume !(1 == ~T13_E~0); {50650#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 137: Hoare triple {50650#false} assume 1 == ~E_M~0;~E_M~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 138: Hoare triple {50650#false} assume 1 == ~E_1~0;~E_1~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 139: Hoare triple {50650#false} assume 1 == ~E_2~0;~E_2~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 140: Hoare triple {50650#false} assume 1 == ~E_3~0;~E_3~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 141: Hoare triple {50650#false} assume 1 == ~E_4~0;~E_4~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 142: Hoare triple {50650#false} assume 1 == ~E_5~0;~E_5~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 143: Hoare triple {50650#false} assume 1 == ~E_6~0;~E_6~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 144: Hoare triple {50650#false} assume !(1 == ~E_7~0); {50650#false} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 145: Hoare triple {50650#false} assume 1 == ~E_8~0;~E_8~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 146: Hoare triple {50650#false} assume 1 == ~E_9~0;~E_9~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 147: Hoare triple {50650#false} assume 1 == ~E_10~0;~E_10~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 148: Hoare triple {50650#false} assume 1 == ~E_11~0;~E_11~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 149: Hoare triple {50650#false} assume 1 == ~E_12~0;~E_12~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 150: Hoare triple {50650#false} assume 1 == ~E_13~0;~E_13~0 := 2; {50650#false} is VALID [2022-02-21 04:23:25,110 INFO L290 TraceCheckUtils]: 151: Hoare triple {50650#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {50650#false} is VALID [2022-02-21 04:23:25,110 INFO L290 TraceCheckUtils]: 152: Hoare triple {50650#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {50650#false} is VALID [2022-02-21 04:23:25,110 INFO L290 TraceCheckUtils]: 153: Hoare triple {50650#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {50650#false} is VALID [2022-02-21 04:23:25,110 INFO L290 TraceCheckUtils]: 154: Hoare triple {50650#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {50650#false} is VALID [2022-02-21 04:23:25,110 INFO L290 TraceCheckUtils]: 155: Hoare triple {50650#false} assume !(0 == start_simulation_~tmp~3#1); {50650#false} is VALID [2022-02-21 04:23:25,110 INFO L290 TraceCheckUtils]: 156: Hoare triple {50650#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {50650#false} is VALID [2022-02-21 04:23:25,110 INFO L290 TraceCheckUtils]: 157: Hoare triple {50650#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {50650#false} is VALID [2022-02-21 04:23:25,111 INFO L290 TraceCheckUtils]: 158: Hoare triple {50650#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {50650#false} is VALID [2022-02-21 04:23:25,111 INFO L290 TraceCheckUtils]: 159: Hoare triple {50650#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {50650#false} is VALID [2022-02-21 04:23:25,111 INFO L290 TraceCheckUtils]: 160: Hoare triple {50650#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {50650#false} is VALID [2022-02-21 04:23:25,111 INFO L290 TraceCheckUtils]: 161: Hoare triple {50650#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {50650#false} is VALID [2022-02-21 04:23:25,111 INFO L290 TraceCheckUtils]: 162: Hoare triple {50650#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {50650#false} is VALID [2022-02-21 04:23:25,111 INFO L290 TraceCheckUtils]: 163: Hoare triple {50650#false} assume !(0 != start_simulation_~tmp___0~1#1); {50650#false} is VALID [2022-02-21 04:23:25,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:25,112 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:25,112 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1557096959] [2022-02-21 04:23:25,112 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1557096959] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:25,113 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:25,113 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:25,113 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1936820163] [2022-02-21 04:23:25,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:25,113 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:25,114 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:25,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:25,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:25,115 INFO L87 Difference]: Start difference. First operand 2023 states and 2991 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,543 INFO L93 Difference]: Finished difference Result 2023 states and 2990 transitions. [2022-02-21 04:23:26,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:26,543 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,644 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:26,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2990 transitions. [2022-02-21 04:23:26,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:26,813 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2990 transitions. [2022-02-21 04:23:26,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:26,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:26,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2990 transitions. [2022-02-21 04:23:26,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:26,816 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2022-02-21 04:23:26,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2990 transitions. [2022-02-21 04:23:26,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:26,837 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:26,839 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2990 transitions. Second operand has 2023 states, 2023 states have (on average 1.4780029658922393) internal successors, (2990), 2022 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,841 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2990 transitions. Second operand has 2023 states, 2023 states have (on average 1.4780029658922393) internal successors, (2990), 2022 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,842 INFO L87 Difference]: Start difference. First operand 2023 states and 2990 transitions. Second operand has 2023 states, 2023 states have (on average 1.4780029658922393) internal successors, (2990), 2022 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,940 INFO L93 Difference]: Finished difference Result 2023 states and 2990 transitions. [2022-02-21 04:23:26,940 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2990 transitions. [2022-02-21 04:23:26,941 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:26,941 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:26,943 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4780029658922393) internal successors, (2990), 2022 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2990 transitions. [2022-02-21 04:23:26,944 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4780029658922393) internal successors, (2990), 2022 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2990 transitions. [2022-02-21 04:23:27,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:27,027 INFO L93 Difference]: Finished difference Result 2023 states and 2990 transitions. [2022-02-21 04:23:27,027 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2990 transitions. [2022-02-21 04:23:27,029 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:27,029 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:27,029 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:27,029 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:27,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4780029658922393) internal successors, (2990), 2022 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2990 transitions. [2022-02-21 04:23:27,124 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2022-02-21 04:23:27,124 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2022-02-21 04:23:27,124 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:23:27,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2990 transitions. [2022-02-21 04:23:27,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:27,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:27,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:27,129 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:27,130 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:27,132 INFO L791 eck$LassoCheckResult]: Stem: 53602#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54601#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54602#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54687#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 54066#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53535#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53536#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54352#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54353#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54453#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54454#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 53307#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 53308#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54483#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 53843#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 53844#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 54404#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 53745#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53746#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 54688#L1291-2 assume !(0 == ~T1_E~0); 54686#L1296-1 assume !(0 == ~T2_E~0); 53902#L1301-1 assume !(0 == ~T3_E~0); 53903#L1306-1 assume !(0 == ~T4_E~0); 54412#L1311-1 assume !(0 == ~T5_E~0); 53150#L1316-1 assume !(0 == ~T6_E~0); 53151#L1321-1 assume !(0 == ~T7_E~0); 53915#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52978#L1331-1 assume !(0 == ~T9_E~0); 52677#L1336-1 assume !(0 == ~T10_E~0); 52678#L1341-1 assume !(0 == ~T11_E~0); 52758#L1346-1 assume !(0 == ~T12_E~0); 52759#L1351-1 assume !(0 == ~T13_E~0); 53099#L1356-1 assume !(0 == ~E_M~0); 53100#L1361-1 assume !(0 == ~E_1~0); 54627#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 53140#L1371-1 assume !(0 == ~E_3~0); 53141#L1376-1 assume !(0 == ~E_4~0); 53962#L1381-1 assume !(0 == ~E_5~0); 53963#L1386-1 assume !(0 == ~E_6~0); 54657#L1391-1 assume !(0 == ~E_7~0); 54675#L1396-1 assume !(0 == ~E_8~0); 53875#L1401-1 assume !(0 == ~E_9~0); 53876#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54154#L1411-1 assume !(0 == ~E_11~0); 54155#L1416-1 assume !(0 == ~E_12~0); 53787#L1421-1 assume !(0 == ~E_13~0); 53330#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53331#L640 assume !(1 == ~m_pc~0); 53840#L640-2 is_master_triggered_~__retres1~0#1 := 0; 53839#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53931#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53825#L1603 assume !(0 != activate_threads_~tmp~1#1); 53826#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53460#L659 assume 1 == ~t1_pc~0; 53461#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53566#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54512#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53586#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 53587#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53600#L678 assume 1 == ~t2_pc~0; 54554#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54555#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54654#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53698#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 53699#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53820#L697 assume !(1 == ~t3_pc~0); 53821#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53943#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53751#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53730#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53731#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54591#L716 assume 1 == ~t4_pc~0; 54577#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53441#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53442#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52941#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 52942#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54233#L735 assume !(1 == ~t5_pc~0); 52902#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52903#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53353#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54260#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 53896#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53897#L754 assume 1 == ~t6_pc~0; 53650#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53548#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53549#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53522#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 53523#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54343#L773 assume !(1 == ~t7_pc~0); 53103#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53102#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53932#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53904#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 53905#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53952#L792 assume 1 == ~t8_pc~0; 54125#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54457#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53946#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53899#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 53823#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53824#L811 assume 1 == ~t9_pc~0; 54028#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54494#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54370#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54024#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 53836#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53837#L830 assume !(1 == ~t10_pc~0); 53558#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53082#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52775#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52776#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53063#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54361#L849 assume 1 == ~t11_pc~0; 54362#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52878#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52879#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53468#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 54267#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54268#L868 assume !(1 == ~t12_pc~0); 53683#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53682#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53477#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53478#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 53114#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53115#L887 assume 1 == ~t13_pc~0; 54282#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53724#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53725#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54161#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 52818#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52819#L1439 assume !(1 == ~M_E~0); 53892#L1439-2 assume !(1 == ~T1_E~0); 52990#L1444-1 assume !(1 == ~T2_E~0); 52991#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53464#L1454-1 assume !(1 == ~T4_E~0); 53465#L1459-1 assume !(1 == ~T5_E~0); 54021#L1464-1 assume !(1 == ~T6_E~0); 54022#L1469-1 assume !(1 == ~T7_E~0); 54094#L1474-1 assume !(1 == ~T8_E~0); 53788#L1479-1 assume !(1 == ~T9_E~0); 53789#L1484-1 assume !(1 == ~T10_E~0); 54025#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53671#L1494-1 assume !(1 == ~T12_E~0); 53672#L1499-1 assume !(1 == ~T13_E~0); 53864#L1504-1 assume !(1 == ~E_M~0); 53865#L1509-1 assume !(1 == ~E_1~0); 54440#L1514-1 assume !(1 == ~E_2~0); 54127#L1519-1 assume !(1 == ~E_3~0); 54128#L1524-1 assume !(1 == ~E_4~0); 54640#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54641#L1534-1 assume !(1 == ~E_6~0); 52811#L1539-1 assume !(1 == ~E_7~0); 52812#L1544-1 assume !(1 == ~E_8~0); 53226#L1549-1 assume !(1 == ~E_9~0); 54615#L1554-1 assume !(1 == ~E_10~0); 54611#L1559-1 assume !(1 == ~E_11~0); 54478#L1564-1 assume !(1 == ~E_12~0); 54479#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 54636#L1574-1 assume { :end_inline_reset_delta_events } true; 52988#L1940-2 [2022-02-21 04:23:27,133 INFO L793 eck$LassoCheckResult]: Loop: 52988#L1940-2 assume !false; 52989#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53271#L1266 assume !false; 54290#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53519#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53252#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53643#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53644#L1079 assume !(0 != eval_~tmp~0#1); 53605#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53606#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54210#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54095#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54096#L1296-3 assume !(0 == ~T2_E~0); 54668#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54622#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53753#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53029#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53030#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53130#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53887#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54136#L1336-3 assume !(0 == ~T10_E~0); 54137#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53457#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53437#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53382#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53383#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53944#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52733#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52734#L1376-3 assume !(0 == ~E_4~0); 54463#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54323#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54324#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54486#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54487#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53096#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52950#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52951#L1416-3 assume !(0 == ~E_12~0); 53612#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53613#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53720#L640-45 assume !(1 == ~m_pc~0); 53721#L640-47 is_master_triggered_~__retres1~0#1 := 0; 53187#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53188#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52727#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52728#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52826#L659-45 assume 1 == ~t1_pc~0; 52827#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53266#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54225#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54226#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54247#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54248#L678-45 assume !(1 == ~t2_pc~0); 54192#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 53726#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53727#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53879#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54504#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54621#L697-45 assume 1 == ~t3_pc~0; 53984#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53985#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54573#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54143#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54144#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54174#L716-45 assume 1 == ~t4_pc~0; 53805#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53806#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54356#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53811#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53812#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53474#L735-45 assume 1 == ~t5_pc~0; 53475#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54018#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54580#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54581#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54639#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54634#L754-45 assume !(1 == ~t6_pc~0); 53968#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 53967#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53396#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53397#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53970#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53702#L773-45 assume 1 == ~t7_pc~0; 53703#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53260#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54180#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54462#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 53708#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53378#L792-45 assume 1 == ~t8_pc~0; 53379#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54408#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52981#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52840#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52841#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53336#L811-45 assume 1 == ~t9_pc~0; 53125#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53127#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54335#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54170#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53779#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53571#L830-45 assume !(1 == ~t10_pc~0); 52768#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 52769#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53891#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53001#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53002#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52747#L849-45 assume !(1 == ~t11_pc~0); 52748#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53207#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52838#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52735#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52736#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52994#L868-45 assume 1 == ~t12_pc~0; 52995#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52934#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52935#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54273#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54524#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54525#L887-45 assume 1 == ~t13_pc~0; 54355#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53004#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54286#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54631#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 52966#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52967#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54274#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52986#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52987#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53144#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54075#L1459-3 assume !(1 == ~T5_E~0); 54076#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54527#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54466#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54467#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54528#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53760#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53761#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54397#L1499-3 assume !(1 == ~T13_E~0); 54036#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54037#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54475#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54505#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53679#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53680#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54547#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53947#L1539-3 assume !(1 == ~E_7~0); 53423#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53424#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53919#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53040#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53041#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54175#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54176#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52917#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52688#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 52963#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 52924#L1959 assume !(0 == start_simulation_~tmp~3#1); 52926#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52958#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52908#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54217#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54338#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54545#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54559#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54560#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 52988#L1940-2 [2022-02-21 04:23:27,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:27,134 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2022-02-21 04:23:27,134 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:27,134 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418137187] [2022-02-21 04:23:27,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:27,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:27,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:27,170 INFO L290 TraceCheckUtils]: 0: Hoare triple {58747#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {58747#true} is VALID [2022-02-21 04:23:27,170 INFO L290 TraceCheckUtils]: 1: Hoare triple {58747#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {58749#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,171 INFO L290 TraceCheckUtils]: 2: Hoare triple {58749#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {58749#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,171 INFO L290 TraceCheckUtils]: 3: Hoare triple {58749#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {58749#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,171 INFO L290 TraceCheckUtils]: 4: Hoare triple {58749#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {58749#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,172 INFO L290 TraceCheckUtils]: 5: Hoare triple {58749#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {58749#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,172 INFO L290 TraceCheckUtils]: 6: Hoare triple {58749#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {58749#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,172 INFO L290 TraceCheckUtils]: 7: Hoare triple {58749#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {58749#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,173 INFO L290 TraceCheckUtils]: 8: Hoare triple {58749#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {58749#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,173 INFO L290 TraceCheckUtils]: 9: Hoare triple {58749#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {58749#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,173 INFO L290 TraceCheckUtils]: 10: Hoare triple {58749#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {58749#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,174 INFO L290 TraceCheckUtils]: 11: Hoare triple {58749#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {58748#false} is VALID [2022-02-21 04:23:27,174 INFO L290 TraceCheckUtils]: 12: Hoare triple {58748#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {58748#false} is VALID [2022-02-21 04:23:27,174 INFO L290 TraceCheckUtils]: 13: Hoare triple {58748#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {58748#false} is VALID [2022-02-21 04:23:27,174 INFO L290 TraceCheckUtils]: 14: Hoare triple {58748#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {58748#false} is VALID [2022-02-21 04:23:27,174 INFO L290 TraceCheckUtils]: 15: Hoare triple {58748#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {58748#false} is VALID [2022-02-21 04:23:27,174 INFO L290 TraceCheckUtils]: 16: Hoare triple {58748#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {58748#false} is VALID [2022-02-21 04:23:27,174 INFO L290 TraceCheckUtils]: 17: Hoare triple {58748#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {58748#false} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 18: Hoare triple {58748#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {58748#false} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 19: Hoare triple {58748#false} assume 0 == ~M_E~0;~M_E~0 := 1; {58748#false} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 20: Hoare triple {58748#false} assume !(0 == ~T1_E~0); {58748#false} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 21: Hoare triple {58748#false} assume !(0 == ~T2_E~0); {58748#false} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 22: Hoare triple {58748#false} assume !(0 == ~T3_E~0); {58748#false} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 23: Hoare triple {58748#false} assume !(0 == ~T4_E~0); {58748#false} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 24: Hoare triple {58748#false} assume !(0 == ~T5_E~0); {58748#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 25: Hoare triple {58748#false} assume !(0 == ~T6_E~0); {58748#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 26: Hoare triple {58748#false} assume !(0 == ~T7_E~0); {58748#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 27: Hoare triple {58748#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {58748#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 28: Hoare triple {58748#false} assume !(0 == ~T9_E~0); {58748#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 29: Hoare triple {58748#false} assume !(0 == ~T10_E~0); {58748#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 30: Hoare triple {58748#false} assume !(0 == ~T11_E~0); {58748#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 31: Hoare triple {58748#false} assume !(0 == ~T12_E~0); {58748#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 32: Hoare triple {58748#false} assume !(0 == ~T13_E~0); {58748#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 33: Hoare triple {58748#false} assume !(0 == ~E_M~0); {58748#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 34: Hoare triple {58748#false} assume !(0 == ~E_1~0); {58748#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 35: Hoare triple {58748#false} assume 0 == ~E_2~0;~E_2~0 := 1; {58748#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 36: Hoare triple {58748#false} assume !(0 == ~E_3~0); {58748#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 37: Hoare triple {58748#false} assume !(0 == ~E_4~0); {58748#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 38: Hoare triple {58748#false} assume !(0 == ~E_5~0); {58748#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 39: Hoare triple {58748#false} assume !(0 == ~E_6~0); {58748#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 40: Hoare triple {58748#false} assume !(0 == ~E_7~0); {58748#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 41: Hoare triple {58748#false} assume !(0 == ~E_8~0); {58748#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 42: Hoare triple {58748#false} assume !(0 == ~E_9~0); {58748#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 43: Hoare triple {58748#false} assume 0 == ~E_10~0;~E_10~0 := 1; {58748#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 44: Hoare triple {58748#false} assume !(0 == ~E_11~0); {58748#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 45: Hoare triple {58748#false} assume !(0 == ~E_12~0); {58748#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 46: Hoare triple {58748#false} assume !(0 == ~E_13~0); {58748#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 47: Hoare triple {58748#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {58748#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 48: Hoare triple {58748#false} assume !(1 == ~m_pc~0); {58748#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 49: Hoare triple {58748#false} is_master_triggered_~__retres1~0#1 := 0; {58748#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 50: Hoare triple {58748#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {58748#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 51: Hoare triple {58748#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {58748#false} is VALID [2022-02-21 04:23:27,180 INFO L290 TraceCheckUtils]: 52: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp~1#1); {58748#false} is VALID [2022-02-21 04:23:27,180 INFO L290 TraceCheckUtils]: 53: Hoare triple {58748#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {58748#false} is VALID [2022-02-21 04:23:27,180 INFO L290 TraceCheckUtils]: 54: Hoare triple {58748#false} assume 1 == ~t1_pc~0; {58748#false} is VALID [2022-02-21 04:23:27,180 INFO L290 TraceCheckUtils]: 55: Hoare triple {58748#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {58748#false} is VALID [2022-02-21 04:23:27,180 INFO L290 TraceCheckUtils]: 56: Hoare triple {58748#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {58748#false} is VALID [2022-02-21 04:23:27,180 INFO L290 TraceCheckUtils]: 57: Hoare triple {58748#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {58748#false} is VALID [2022-02-21 04:23:27,180 INFO L290 TraceCheckUtils]: 58: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___0~0#1); {58748#false} is VALID [2022-02-21 04:23:27,181 INFO L290 TraceCheckUtils]: 59: Hoare triple {58748#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {58748#false} is VALID [2022-02-21 04:23:27,181 INFO L290 TraceCheckUtils]: 60: Hoare triple {58748#false} assume 1 == ~t2_pc~0; {58748#false} is VALID [2022-02-21 04:23:27,181 INFO L290 TraceCheckUtils]: 61: Hoare triple {58748#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {58748#false} is VALID [2022-02-21 04:23:27,181 INFO L290 TraceCheckUtils]: 62: Hoare triple {58748#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {58748#false} is VALID [2022-02-21 04:23:27,181 INFO L290 TraceCheckUtils]: 63: Hoare triple {58748#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {58748#false} is VALID [2022-02-21 04:23:27,181 INFO L290 TraceCheckUtils]: 64: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___1~0#1); {58748#false} is VALID [2022-02-21 04:23:27,181 INFO L290 TraceCheckUtils]: 65: Hoare triple {58748#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {58748#false} is VALID [2022-02-21 04:23:27,181 INFO L290 TraceCheckUtils]: 66: Hoare triple {58748#false} assume !(1 == ~t3_pc~0); {58748#false} is VALID [2022-02-21 04:23:27,182 INFO L290 TraceCheckUtils]: 67: Hoare triple {58748#false} is_transmit3_triggered_~__retres1~3#1 := 0; {58748#false} is VALID [2022-02-21 04:23:27,182 INFO L290 TraceCheckUtils]: 68: Hoare triple {58748#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {58748#false} is VALID [2022-02-21 04:23:27,182 INFO L290 TraceCheckUtils]: 69: Hoare triple {58748#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {58748#false} is VALID [2022-02-21 04:23:27,182 INFO L290 TraceCheckUtils]: 70: Hoare triple {58748#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {58748#false} is VALID [2022-02-21 04:23:27,182 INFO L290 TraceCheckUtils]: 71: Hoare triple {58748#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {58748#false} is VALID [2022-02-21 04:23:27,182 INFO L290 TraceCheckUtils]: 72: Hoare triple {58748#false} assume 1 == ~t4_pc~0; {58748#false} is VALID [2022-02-21 04:23:27,182 INFO L290 TraceCheckUtils]: 73: Hoare triple {58748#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {58748#false} is VALID [2022-02-21 04:23:27,183 INFO L290 TraceCheckUtils]: 74: Hoare triple {58748#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {58748#false} is VALID [2022-02-21 04:23:27,183 INFO L290 TraceCheckUtils]: 75: Hoare triple {58748#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {58748#false} is VALID [2022-02-21 04:23:27,183 INFO L290 TraceCheckUtils]: 76: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___3~0#1); {58748#false} is VALID [2022-02-21 04:23:27,183 INFO L290 TraceCheckUtils]: 77: Hoare triple {58748#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {58748#false} is VALID [2022-02-21 04:23:27,183 INFO L290 TraceCheckUtils]: 78: Hoare triple {58748#false} assume !(1 == ~t5_pc~0); {58748#false} is VALID [2022-02-21 04:23:27,183 INFO L290 TraceCheckUtils]: 79: Hoare triple {58748#false} is_transmit5_triggered_~__retres1~5#1 := 0; {58748#false} is VALID [2022-02-21 04:23:27,183 INFO L290 TraceCheckUtils]: 80: Hoare triple {58748#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {58748#false} is VALID [2022-02-21 04:23:27,184 INFO L290 TraceCheckUtils]: 81: Hoare triple {58748#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {58748#false} is VALID [2022-02-21 04:23:27,184 INFO L290 TraceCheckUtils]: 82: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___4~0#1); {58748#false} is VALID [2022-02-21 04:23:27,184 INFO L290 TraceCheckUtils]: 83: Hoare triple {58748#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {58748#false} is VALID [2022-02-21 04:23:27,184 INFO L290 TraceCheckUtils]: 84: Hoare triple {58748#false} assume 1 == ~t6_pc~0; {58748#false} is VALID [2022-02-21 04:23:27,184 INFO L290 TraceCheckUtils]: 85: Hoare triple {58748#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {58748#false} is VALID [2022-02-21 04:23:27,184 INFO L290 TraceCheckUtils]: 86: Hoare triple {58748#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {58748#false} is VALID [2022-02-21 04:23:27,184 INFO L290 TraceCheckUtils]: 87: Hoare triple {58748#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {58748#false} is VALID [2022-02-21 04:23:27,185 INFO L290 TraceCheckUtils]: 88: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___5~0#1); {58748#false} is VALID [2022-02-21 04:23:27,185 INFO L290 TraceCheckUtils]: 89: Hoare triple {58748#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {58748#false} is VALID [2022-02-21 04:23:27,185 INFO L290 TraceCheckUtils]: 90: Hoare triple {58748#false} assume !(1 == ~t7_pc~0); {58748#false} is VALID [2022-02-21 04:23:27,185 INFO L290 TraceCheckUtils]: 91: Hoare triple {58748#false} is_transmit7_triggered_~__retres1~7#1 := 0; {58748#false} is VALID [2022-02-21 04:23:27,185 INFO L290 TraceCheckUtils]: 92: Hoare triple {58748#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {58748#false} is VALID [2022-02-21 04:23:27,185 INFO L290 TraceCheckUtils]: 93: Hoare triple {58748#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {58748#false} is VALID [2022-02-21 04:23:27,185 INFO L290 TraceCheckUtils]: 94: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___6~0#1); {58748#false} is VALID [2022-02-21 04:23:27,186 INFO L290 TraceCheckUtils]: 95: Hoare triple {58748#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {58748#false} is VALID [2022-02-21 04:23:27,186 INFO L290 TraceCheckUtils]: 96: Hoare triple {58748#false} assume 1 == ~t8_pc~0; {58748#false} is VALID [2022-02-21 04:23:27,186 INFO L290 TraceCheckUtils]: 97: Hoare triple {58748#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {58748#false} is VALID [2022-02-21 04:23:27,186 INFO L290 TraceCheckUtils]: 98: Hoare triple {58748#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {58748#false} is VALID [2022-02-21 04:23:27,186 INFO L290 TraceCheckUtils]: 99: Hoare triple {58748#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {58748#false} is VALID [2022-02-21 04:23:27,186 INFO L290 TraceCheckUtils]: 100: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___7~0#1); {58748#false} is VALID [2022-02-21 04:23:27,186 INFO L290 TraceCheckUtils]: 101: Hoare triple {58748#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {58748#false} is VALID [2022-02-21 04:23:27,187 INFO L290 TraceCheckUtils]: 102: Hoare triple {58748#false} assume 1 == ~t9_pc~0; {58748#false} is VALID [2022-02-21 04:23:27,187 INFO L290 TraceCheckUtils]: 103: Hoare triple {58748#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {58748#false} is VALID [2022-02-21 04:23:27,187 INFO L290 TraceCheckUtils]: 104: Hoare triple {58748#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {58748#false} is VALID [2022-02-21 04:23:27,187 INFO L290 TraceCheckUtils]: 105: Hoare triple {58748#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {58748#false} is VALID [2022-02-21 04:23:27,187 INFO L290 TraceCheckUtils]: 106: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___8~0#1); {58748#false} is VALID [2022-02-21 04:23:27,187 INFO L290 TraceCheckUtils]: 107: Hoare triple {58748#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {58748#false} is VALID [2022-02-21 04:23:27,187 INFO L290 TraceCheckUtils]: 108: Hoare triple {58748#false} assume !(1 == ~t10_pc~0); {58748#false} is VALID [2022-02-21 04:23:27,188 INFO L290 TraceCheckUtils]: 109: Hoare triple {58748#false} is_transmit10_triggered_~__retres1~10#1 := 0; {58748#false} is VALID [2022-02-21 04:23:27,188 INFO L290 TraceCheckUtils]: 110: Hoare triple {58748#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {58748#false} is VALID [2022-02-21 04:23:27,188 INFO L290 TraceCheckUtils]: 111: Hoare triple {58748#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {58748#false} is VALID [2022-02-21 04:23:27,188 INFO L290 TraceCheckUtils]: 112: Hoare triple {58748#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {58748#false} is VALID [2022-02-21 04:23:27,188 INFO L290 TraceCheckUtils]: 113: Hoare triple {58748#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {58748#false} is VALID [2022-02-21 04:23:27,188 INFO L290 TraceCheckUtils]: 114: Hoare triple {58748#false} assume 1 == ~t11_pc~0; {58748#false} is VALID [2022-02-21 04:23:27,188 INFO L290 TraceCheckUtils]: 115: Hoare triple {58748#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {58748#false} is VALID [2022-02-21 04:23:27,189 INFO L290 TraceCheckUtils]: 116: Hoare triple {58748#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {58748#false} is VALID [2022-02-21 04:23:27,189 INFO L290 TraceCheckUtils]: 117: Hoare triple {58748#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {58748#false} is VALID [2022-02-21 04:23:27,189 INFO L290 TraceCheckUtils]: 118: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___10~0#1); {58748#false} is VALID [2022-02-21 04:23:27,189 INFO L290 TraceCheckUtils]: 119: Hoare triple {58748#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {58748#false} is VALID [2022-02-21 04:23:27,189 INFO L290 TraceCheckUtils]: 120: Hoare triple {58748#false} assume !(1 == ~t12_pc~0); {58748#false} is VALID [2022-02-21 04:23:27,189 INFO L290 TraceCheckUtils]: 121: Hoare triple {58748#false} is_transmit12_triggered_~__retres1~12#1 := 0; {58748#false} is VALID [2022-02-21 04:23:27,189 INFO L290 TraceCheckUtils]: 122: Hoare triple {58748#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {58748#false} is VALID [2022-02-21 04:23:27,190 INFO L290 TraceCheckUtils]: 123: Hoare triple {58748#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {58748#false} is VALID [2022-02-21 04:23:27,190 INFO L290 TraceCheckUtils]: 124: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___11~0#1); {58748#false} is VALID [2022-02-21 04:23:27,190 INFO L290 TraceCheckUtils]: 125: Hoare triple {58748#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {58748#false} is VALID [2022-02-21 04:23:27,190 INFO L290 TraceCheckUtils]: 126: Hoare triple {58748#false} assume 1 == ~t13_pc~0; {58748#false} is VALID [2022-02-21 04:23:27,190 INFO L290 TraceCheckUtils]: 127: Hoare triple {58748#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {58748#false} is VALID [2022-02-21 04:23:27,190 INFO L290 TraceCheckUtils]: 128: Hoare triple {58748#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {58748#false} is VALID [2022-02-21 04:23:27,190 INFO L290 TraceCheckUtils]: 129: Hoare triple {58748#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {58748#false} is VALID [2022-02-21 04:23:27,191 INFO L290 TraceCheckUtils]: 130: Hoare triple {58748#false} assume !(0 != activate_threads_~tmp___12~0#1); {58748#false} is VALID [2022-02-21 04:23:27,191 INFO L290 TraceCheckUtils]: 131: Hoare triple {58748#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {58748#false} is VALID [2022-02-21 04:23:27,191 INFO L290 TraceCheckUtils]: 132: Hoare triple {58748#false} assume !(1 == ~M_E~0); {58748#false} is VALID [2022-02-21 04:23:27,191 INFO L290 TraceCheckUtils]: 133: Hoare triple {58748#false} assume !(1 == ~T1_E~0); {58748#false} is VALID [2022-02-21 04:23:27,191 INFO L290 TraceCheckUtils]: 134: Hoare triple {58748#false} assume !(1 == ~T2_E~0); {58748#false} is VALID [2022-02-21 04:23:27,191 INFO L290 TraceCheckUtils]: 135: Hoare triple {58748#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {58748#false} is VALID [2022-02-21 04:23:27,191 INFO L290 TraceCheckUtils]: 136: Hoare triple {58748#false} assume !(1 == ~T4_E~0); {58748#false} is VALID [2022-02-21 04:23:27,192 INFO L290 TraceCheckUtils]: 137: Hoare triple {58748#false} assume !(1 == ~T5_E~0); {58748#false} is VALID [2022-02-21 04:23:27,192 INFO L290 TraceCheckUtils]: 138: Hoare triple {58748#false} assume !(1 == ~T6_E~0); {58748#false} is VALID [2022-02-21 04:23:27,192 INFO L290 TraceCheckUtils]: 139: Hoare triple {58748#false} assume !(1 == ~T7_E~0); {58748#false} is VALID [2022-02-21 04:23:27,192 INFO L290 TraceCheckUtils]: 140: Hoare triple {58748#false} assume !(1 == ~T8_E~0); {58748#false} is VALID [2022-02-21 04:23:27,192 INFO L290 TraceCheckUtils]: 141: Hoare triple {58748#false} assume !(1 == ~T9_E~0); {58748#false} is VALID [2022-02-21 04:23:27,192 INFO L290 TraceCheckUtils]: 142: Hoare triple {58748#false} assume !(1 == ~T10_E~0); {58748#false} is VALID [2022-02-21 04:23:27,192 INFO L290 TraceCheckUtils]: 143: Hoare triple {58748#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {58748#false} is VALID [2022-02-21 04:23:27,193 INFO L290 TraceCheckUtils]: 144: Hoare triple {58748#false} assume !(1 == ~T12_E~0); {58748#false} is VALID [2022-02-21 04:23:27,193 INFO L290 TraceCheckUtils]: 145: Hoare triple {58748#false} assume !(1 == ~T13_E~0); {58748#false} is VALID [2022-02-21 04:23:27,193 INFO L290 TraceCheckUtils]: 146: Hoare triple {58748#false} assume !(1 == ~E_M~0); {58748#false} is VALID [2022-02-21 04:23:27,193 INFO L290 TraceCheckUtils]: 147: Hoare triple {58748#false} assume !(1 == ~E_1~0); {58748#false} is VALID [2022-02-21 04:23:27,193 INFO L290 TraceCheckUtils]: 148: Hoare triple {58748#false} assume !(1 == ~E_2~0); {58748#false} is VALID [2022-02-21 04:23:27,193 INFO L290 TraceCheckUtils]: 149: Hoare triple {58748#false} assume !(1 == ~E_3~0); {58748#false} is VALID [2022-02-21 04:23:27,193 INFO L290 TraceCheckUtils]: 150: Hoare triple {58748#false} assume !(1 == ~E_4~0); {58748#false} is VALID [2022-02-21 04:23:27,194 INFO L290 TraceCheckUtils]: 151: Hoare triple {58748#false} assume 1 == ~E_5~0;~E_5~0 := 2; {58748#false} is VALID [2022-02-21 04:23:27,194 INFO L290 TraceCheckUtils]: 152: Hoare triple {58748#false} assume !(1 == ~E_6~0); {58748#false} is VALID [2022-02-21 04:23:27,194 INFO L290 TraceCheckUtils]: 153: Hoare triple {58748#false} assume !(1 == ~E_7~0); {58748#false} is VALID [2022-02-21 04:23:27,194 INFO L290 TraceCheckUtils]: 154: Hoare triple {58748#false} assume !(1 == ~E_8~0); {58748#false} is VALID [2022-02-21 04:23:27,194 INFO L290 TraceCheckUtils]: 155: Hoare triple {58748#false} assume !(1 == ~E_9~0); {58748#false} is VALID [2022-02-21 04:23:27,194 INFO L290 TraceCheckUtils]: 156: Hoare triple {58748#false} assume !(1 == ~E_10~0); {58748#false} is VALID [2022-02-21 04:23:27,194 INFO L290 TraceCheckUtils]: 157: Hoare triple {58748#false} assume !(1 == ~E_11~0); {58748#false} is VALID [2022-02-21 04:23:27,195 INFO L290 TraceCheckUtils]: 158: Hoare triple {58748#false} assume !(1 == ~E_12~0); {58748#false} is VALID [2022-02-21 04:23:27,195 INFO L290 TraceCheckUtils]: 159: Hoare triple {58748#false} assume 1 == ~E_13~0;~E_13~0 := 2; {58748#false} is VALID [2022-02-21 04:23:27,195 INFO L290 TraceCheckUtils]: 160: Hoare triple {58748#false} assume { :end_inline_reset_delta_events } true; {58748#false} is VALID [2022-02-21 04:23:27,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:27,196 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:27,196 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418137187] [2022-02-21 04:23:27,196 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418137187] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:27,197 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:27,197 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:27,197 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [527263669] [2022-02-21 04:23:27,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:27,198 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:27,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:27,199 INFO L85 PathProgramCache]: Analyzing trace with hash -1140908257, now seen corresponding path program 1 times [2022-02-21 04:23:27,199 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:27,202 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065003529] [2022-02-21 04:23:27,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:27,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:27,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:27,238 INFO L290 TraceCheckUtils]: 0: Hoare triple {58750#true} assume !false; {58750#true} is VALID [2022-02-21 04:23:27,239 INFO L290 TraceCheckUtils]: 1: Hoare triple {58750#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {58750#true} is VALID [2022-02-21 04:23:27,239 INFO L290 TraceCheckUtils]: 2: Hoare triple {58750#true} assume !false; {58750#true} is VALID [2022-02-21 04:23:27,239 INFO L290 TraceCheckUtils]: 3: Hoare triple {58750#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {58750#true} is VALID [2022-02-21 04:23:27,239 INFO L290 TraceCheckUtils]: 4: Hoare triple {58750#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {58750#true} is VALID [2022-02-21 04:23:27,239 INFO L290 TraceCheckUtils]: 5: Hoare triple {58750#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {58750#true} is VALID [2022-02-21 04:23:27,239 INFO L290 TraceCheckUtils]: 6: Hoare triple {58750#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {58750#true} is VALID [2022-02-21 04:23:27,240 INFO L290 TraceCheckUtils]: 7: Hoare triple {58750#true} assume !(0 != eval_~tmp~0#1); {58750#true} is VALID [2022-02-21 04:23:27,240 INFO L290 TraceCheckUtils]: 8: Hoare triple {58750#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {58750#true} is VALID [2022-02-21 04:23:27,240 INFO L290 TraceCheckUtils]: 9: Hoare triple {58750#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {58750#true} is VALID [2022-02-21 04:23:27,240 INFO L290 TraceCheckUtils]: 10: Hoare triple {58750#true} assume 0 == ~M_E~0;~M_E~0 := 1; {58750#true} is VALID [2022-02-21 04:23:27,240 INFO L290 TraceCheckUtils]: 11: Hoare triple {58750#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {58750#true} is VALID [2022-02-21 04:23:27,240 INFO L290 TraceCheckUtils]: 12: Hoare triple {58750#true} assume !(0 == ~T2_E~0); {58750#true} is VALID [2022-02-21 04:23:27,240 INFO L290 TraceCheckUtils]: 13: Hoare triple {58750#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {58750#true} is VALID [2022-02-21 04:23:27,241 INFO L290 TraceCheckUtils]: 14: Hoare triple {58750#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {58750#true} is VALID [2022-02-21 04:23:27,241 INFO L290 TraceCheckUtils]: 15: Hoare triple {58750#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,241 INFO L290 TraceCheckUtils]: 16: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,242 INFO L290 TraceCheckUtils]: 17: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,242 INFO L290 TraceCheckUtils]: 18: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,242 INFO L290 TraceCheckUtils]: 19: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,243 INFO L290 TraceCheckUtils]: 20: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,243 INFO L290 TraceCheckUtils]: 21: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,244 INFO L290 TraceCheckUtils]: 22: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,244 INFO L290 TraceCheckUtils]: 23: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,244 INFO L290 TraceCheckUtils]: 24: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,245 INFO L290 TraceCheckUtils]: 25: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,245 INFO L290 TraceCheckUtils]: 26: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,246 INFO L290 TraceCheckUtils]: 27: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,246 INFO L290 TraceCheckUtils]: 28: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,246 INFO L290 TraceCheckUtils]: 29: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,247 INFO L290 TraceCheckUtils]: 30: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,247 INFO L290 TraceCheckUtils]: 31: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,247 INFO L290 TraceCheckUtils]: 32: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,248 INFO L290 TraceCheckUtils]: 33: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,248 INFO L290 TraceCheckUtils]: 34: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,249 INFO L290 TraceCheckUtils]: 35: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,249 INFO L290 TraceCheckUtils]: 36: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,249 INFO L290 TraceCheckUtils]: 37: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,250 INFO L290 TraceCheckUtils]: 38: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,250 INFO L290 TraceCheckUtils]: 39: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,250 INFO L290 TraceCheckUtils]: 40: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,251 INFO L290 TraceCheckUtils]: 41: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,251 INFO L290 TraceCheckUtils]: 42: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,251 INFO L290 TraceCheckUtils]: 43: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,252 INFO L290 TraceCheckUtils]: 44: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,252 INFO L290 TraceCheckUtils]: 45: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,253 INFO L290 TraceCheckUtils]: 46: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,253 INFO L290 TraceCheckUtils]: 47: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,253 INFO L290 TraceCheckUtils]: 48: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,254 INFO L290 TraceCheckUtils]: 49: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,254 INFO L290 TraceCheckUtils]: 50: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,254 INFO L290 TraceCheckUtils]: 51: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,255 INFO L290 TraceCheckUtils]: 52: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,255 INFO L290 TraceCheckUtils]: 53: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,255 INFO L290 TraceCheckUtils]: 54: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,256 INFO L290 TraceCheckUtils]: 55: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,256 INFO L290 TraceCheckUtils]: 56: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,257 INFO L290 TraceCheckUtils]: 57: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,257 INFO L290 TraceCheckUtils]: 58: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,257 INFO L290 TraceCheckUtils]: 59: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,258 INFO L290 TraceCheckUtils]: 60: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,258 INFO L290 TraceCheckUtils]: 61: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,258 INFO L290 TraceCheckUtils]: 62: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,259 INFO L290 TraceCheckUtils]: 63: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,259 INFO L290 TraceCheckUtils]: 64: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,260 INFO L290 TraceCheckUtils]: 65: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,260 INFO L290 TraceCheckUtils]: 66: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,260 INFO L290 TraceCheckUtils]: 67: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,261 INFO L290 TraceCheckUtils]: 68: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,261 INFO L290 TraceCheckUtils]: 69: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,261 INFO L290 TraceCheckUtils]: 70: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,262 INFO L290 TraceCheckUtils]: 71: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,262 INFO L290 TraceCheckUtils]: 72: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,263 INFO L290 TraceCheckUtils]: 73: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,263 INFO L290 TraceCheckUtils]: 74: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,263 INFO L290 TraceCheckUtils]: 75: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,264 INFO L290 TraceCheckUtils]: 76: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,264 INFO L290 TraceCheckUtils]: 77: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,264 INFO L290 TraceCheckUtils]: 78: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,265 INFO L290 TraceCheckUtils]: 79: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,265 INFO L290 TraceCheckUtils]: 80: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,266 INFO L290 TraceCheckUtils]: 81: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,266 INFO L290 TraceCheckUtils]: 82: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,266 INFO L290 TraceCheckUtils]: 83: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,267 INFO L290 TraceCheckUtils]: 84: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,267 INFO L290 TraceCheckUtils]: 85: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,267 INFO L290 TraceCheckUtils]: 86: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,268 INFO L290 TraceCheckUtils]: 87: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,268 INFO L290 TraceCheckUtils]: 88: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,268 INFO L290 TraceCheckUtils]: 89: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,269 INFO L290 TraceCheckUtils]: 90: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,269 INFO L290 TraceCheckUtils]: 91: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,270 INFO L290 TraceCheckUtils]: 92: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,270 INFO L290 TraceCheckUtils]: 93: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,270 INFO L290 TraceCheckUtils]: 94: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,271 INFO L290 TraceCheckUtils]: 95: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,271 INFO L290 TraceCheckUtils]: 96: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,271 INFO L290 TraceCheckUtils]: 97: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,272 INFO L290 TraceCheckUtils]: 98: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,272 INFO L290 TraceCheckUtils]: 99: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,272 INFO L290 TraceCheckUtils]: 100: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,273 INFO L290 TraceCheckUtils]: 101: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,273 INFO L290 TraceCheckUtils]: 102: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,274 INFO L290 TraceCheckUtils]: 103: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,274 INFO L290 TraceCheckUtils]: 104: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,274 INFO L290 TraceCheckUtils]: 105: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,275 INFO L290 TraceCheckUtils]: 106: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,275 INFO L290 TraceCheckUtils]: 107: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,275 INFO L290 TraceCheckUtils]: 108: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,276 INFO L290 TraceCheckUtils]: 109: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,276 INFO L290 TraceCheckUtils]: 110: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,277 INFO L290 TraceCheckUtils]: 111: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,277 INFO L290 TraceCheckUtils]: 112: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,277 INFO L290 TraceCheckUtils]: 113: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,278 INFO L290 TraceCheckUtils]: 114: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,278 INFO L290 TraceCheckUtils]: 115: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,278 INFO L290 TraceCheckUtils]: 116: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,279 INFO L290 TraceCheckUtils]: 117: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,279 INFO L290 TraceCheckUtils]: 118: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,280 INFO L290 TraceCheckUtils]: 119: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,280 INFO L290 TraceCheckUtils]: 120: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,280 INFO L290 TraceCheckUtils]: 121: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,281 INFO L290 TraceCheckUtils]: 122: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,281 INFO L290 TraceCheckUtils]: 123: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,281 INFO L290 TraceCheckUtils]: 124: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,282 INFO L290 TraceCheckUtils]: 125: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,282 INFO L290 TraceCheckUtils]: 126: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,283 INFO L290 TraceCheckUtils]: 127: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {58752#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:27,283 INFO L290 TraceCheckUtils]: 128: Hoare triple {58752#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {58751#false} is VALID [2022-02-21 04:23:27,283 INFO L290 TraceCheckUtils]: 129: Hoare triple {58751#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,283 INFO L290 TraceCheckUtils]: 130: Hoare triple {58751#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,283 INFO L290 TraceCheckUtils]: 131: Hoare triple {58751#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,283 INFO L290 TraceCheckUtils]: 132: Hoare triple {58751#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,284 INFO L290 TraceCheckUtils]: 133: Hoare triple {58751#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,284 INFO L290 TraceCheckUtils]: 134: Hoare triple {58751#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,284 INFO L290 TraceCheckUtils]: 135: Hoare triple {58751#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,284 INFO L290 TraceCheckUtils]: 136: Hoare triple {58751#false} assume !(1 == ~T13_E~0); {58751#false} is VALID [2022-02-21 04:23:27,284 INFO L290 TraceCheckUtils]: 137: Hoare triple {58751#false} assume 1 == ~E_M~0;~E_M~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,284 INFO L290 TraceCheckUtils]: 138: Hoare triple {58751#false} assume 1 == ~E_1~0;~E_1~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,284 INFO L290 TraceCheckUtils]: 139: Hoare triple {58751#false} assume 1 == ~E_2~0;~E_2~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,285 INFO L290 TraceCheckUtils]: 140: Hoare triple {58751#false} assume 1 == ~E_3~0;~E_3~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,285 INFO L290 TraceCheckUtils]: 141: Hoare triple {58751#false} assume 1 == ~E_4~0;~E_4~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,285 INFO L290 TraceCheckUtils]: 142: Hoare triple {58751#false} assume 1 == ~E_5~0;~E_5~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,285 INFO L290 TraceCheckUtils]: 143: Hoare triple {58751#false} assume 1 == ~E_6~0;~E_6~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,285 INFO L290 TraceCheckUtils]: 144: Hoare triple {58751#false} assume !(1 == ~E_7~0); {58751#false} is VALID [2022-02-21 04:23:27,285 INFO L290 TraceCheckUtils]: 145: Hoare triple {58751#false} assume 1 == ~E_8~0;~E_8~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,285 INFO L290 TraceCheckUtils]: 146: Hoare triple {58751#false} assume 1 == ~E_9~0;~E_9~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,286 INFO L290 TraceCheckUtils]: 147: Hoare triple {58751#false} assume 1 == ~E_10~0;~E_10~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,286 INFO L290 TraceCheckUtils]: 148: Hoare triple {58751#false} assume 1 == ~E_11~0;~E_11~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,286 INFO L290 TraceCheckUtils]: 149: Hoare triple {58751#false} assume 1 == ~E_12~0;~E_12~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,286 INFO L290 TraceCheckUtils]: 150: Hoare triple {58751#false} assume 1 == ~E_13~0;~E_13~0 := 2; {58751#false} is VALID [2022-02-21 04:23:27,286 INFO L290 TraceCheckUtils]: 151: Hoare triple {58751#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {58751#false} is VALID [2022-02-21 04:23:27,286 INFO L290 TraceCheckUtils]: 152: Hoare triple {58751#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {58751#false} is VALID [2022-02-21 04:23:27,286 INFO L290 TraceCheckUtils]: 153: Hoare triple {58751#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {58751#false} is VALID [2022-02-21 04:23:27,287 INFO L290 TraceCheckUtils]: 154: Hoare triple {58751#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {58751#false} is VALID [2022-02-21 04:23:27,287 INFO L290 TraceCheckUtils]: 155: Hoare triple {58751#false} assume !(0 == start_simulation_~tmp~3#1); {58751#false} is VALID [2022-02-21 04:23:27,287 INFO L290 TraceCheckUtils]: 156: Hoare triple {58751#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {58751#false} is VALID [2022-02-21 04:23:27,287 INFO L290 TraceCheckUtils]: 157: Hoare triple {58751#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {58751#false} is VALID [2022-02-21 04:23:27,287 INFO L290 TraceCheckUtils]: 158: Hoare triple {58751#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {58751#false} is VALID [2022-02-21 04:23:27,287 INFO L290 TraceCheckUtils]: 159: Hoare triple {58751#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {58751#false} is VALID [2022-02-21 04:23:27,288 INFO L290 TraceCheckUtils]: 160: Hoare triple {58751#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {58751#false} is VALID [2022-02-21 04:23:27,288 INFO L290 TraceCheckUtils]: 161: Hoare triple {58751#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {58751#false} is VALID [2022-02-21 04:23:27,288 INFO L290 TraceCheckUtils]: 162: Hoare triple {58751#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {58751#false} is VALID [2022-02-21 04:23:27,288 INFO L290 TraceCheckUtils]: 163: Hoare triple {58751#false} assume !(0 != start_simulation_~tmp___0~1#1); {58751#false} is VALID [2022-02-21 04:23:27,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:27,289 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:27,290 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065003529] [2022-02-21 04:23:27,292 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065003529] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:27,292 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:27,292 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:27,292 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1289906861] [2022-02-21 04:23:27,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:27,293 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:27,293 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:27,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:27,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:27,294 INFO L87 Difference]: Start difference. First operand 2023 states and 2990 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:28,720 INFO L93 Difference]: Finished difference Result 2023 states and 2989 transitions. [2022-02-21 04:23:28,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:28,721 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,818 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:28,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2989 transitions. [2022-02-21 04:23:28,907 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:29,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2989 transitions. [2022-02-21 04:23:29,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:29,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:29,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2989 transitions. [2022-02-21 04:23:29,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:29,001 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2022-02-21 04:23:29,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2989 transitions. [2022-02-21 04:23:29,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:29,021 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:29,023 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2989 transitions. Second operand has 2023 states, 2023 states have (on average 1.4775086505190311) internal successors, (2989), 2022 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,024 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2989 transitions. Second operand has 2023 states, 2023 states have (on average 1.4775086505190311) internal successors, (2989), 2022 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,025 INFO L87 Difference]: Start difference. First operand 2023 states and 2989 transitions. Second operand has 2023 states, 2023 states have (on average 1.4775086505190311) internal successors, (2989), 2022 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,119 INFO L93 Difference]: Finished difference Result 2023 states and 2989 transitions. [2022-02-21 04:23:29,119 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2989 transitions. [2022-02-21 04:23:29,120 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:29,120 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:29,122 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4775086505190311) internal successors, (2989), 2022 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2989 transitions. [2022-02-21 04:23:29,123 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4775086505190311) internal successors, (2989), 2022 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2989 transitions. [2022-02-21 04:23:29,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,207 INFO L93 Difference]: Finished difference Result 2023 states and 2989 transitions. [2022-02-21 04:23:29,207 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2989 transitions. [2022-02-21 04:23:29,209 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:29,209 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:29,209 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:29,209 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:29,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4775086505190311) internal successors, (2989), 2022 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2989 transitions. [2022-02-21 04:23:29,294 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2022-02-21 04:23:29,294 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2022-02-21 04:23:29,294 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:23:29,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2989 transitions. [2022-02-21 04:23:29,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:29,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:29,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:29,298 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:29,298 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:29,298 INFO L791 eck$LassoCheckResult]: Stem: 61703#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 61704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 62702#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62703#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62788#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 62167#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61636#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61637#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62453#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62454#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62554#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62555#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61408#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 61409#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62584#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 61944#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 61945#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 62505#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 61846#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61847#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 62789#L1291-2 assume !(0 == ~T1_E~0); 62787#L1296-1 assume !(0 == ~T2_E~0); 62003#L1301-1 assume !(0 == ~T3_E~0); 62004#L1306-1 assume !(0 == ~T4_E~0); 62513#L1311-1 assume !(0 == ~T5_E~0); 61251#L1316-1 assume !(0 == ~T6_E~0); 61252#L1321-1 assume !(0 == ~T7_E~0); 62016#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 61079#L1331-1 assume !(0 == ~T9_E~0); 60778#L1336-1 assume !(0 == ~T10_E~0); 60779#L1341-1 assume !(0 == ~T11_E~0); 60859#L1346-1 assume !(0 == ~T12_E~0); 60860#L1351-1 assume !(0 == ~T13_E~0); 61200#L1356-1 assume !(0 == ~E_M~0); 61201#L1361-1 assume !(0 == ~E_1~0); 62728#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 61241#L1371-1 assume !(0 == ~E_3~0); 61242#L1376-1 assume !(0 == ~E_4~0); 62063#L1381-1 assume !(0 == ~E_5~0); 62064#L1386-1 assume !(0 == ~E_6~0); 62758#L1391-1 assume !(0 == ~E_7~0); 62776#L1396-1 assume !(0 == ~E_8~0); 61976#L1401-1 assume !(0 == ~E_9~0); 61977#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 62255#L1411-1 assume !(0 == ~E_11~0); 62256#L1416-1 assume !(0 == ~E_12~0); 61888#L1421-1 assume !(0 == ~E_13~0); 61431#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61432#L640 assume !(1 == ~m_pc~0); 61941#L640-2 is_master_triggered_~__retres1~0#1 := 0; 61940#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62032#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61926#L1603 assume !(0 != activate_threads_~tmp~1#1); 61927#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61561#L659 assume 1 == ~t1_pc~0; 61562#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 61667#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62613#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61687#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 61688#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61701#L678 assume 1 == ~t2_pc~0; 62655#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62656#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62755#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61799#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 61800#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61921#L697 assume !(1 == ~t3_pc~0); 61922#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62044#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61852#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61831#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61832#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62692#L716 assume 1 == ~t4_pc~0; 62678#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61542#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61543#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61042#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 61043#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62334#L735 assume !(1 == ~t5_pc~0); 61003#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 61004#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61454#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62361#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 61997#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61998#L754 assume 1 == ~t6_pc~0; 61751#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61649#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61650#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61623#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 61624#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62444#L773 assume !(1 == ~t7_pc~0); 61204#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 61203#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62033#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62005#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 62006#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62053#L792 assume 1 == ~t8_pc~0; 62226#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62558#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62047#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62000#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 61924#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61925#L811 assume 1 == ~t9_pc~0; 62129#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62595#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62471#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62125#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 61937#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61938#L830 assume !(1 == ~t10_pc~0); 61659#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 61183#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60876#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60877#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61164#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62462#L849 assume 1 == ~t11_pc~0; 62463#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60979#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60980#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61569#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 62368#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62369#L868 assume !(1 == ~t12_pc~0); 61784#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 61783#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61578#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 61579#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 61215#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61216#L887 assume 1 == ~t13_pc~0; 62383#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 61825#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 61826#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 62262#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 60919#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60920#L1439 assume !(1 == ~M_E~0); 61993#L1439-2 assume !(1 == ~T1_E~0); 61091#L1444-1 assume !(1 == ~T2_E~0); 61092#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61565#L1454-1 assume !(1 == ~T4_E~0); 61566#L1459-1 assume !(1 == ~T5_E~0); 62122#L1464-1 assume !(1 == ~T6_E~0); 62123#L1469-1 assume !(1 == ~T7_E~0); 62195#L1474-1 assume !(1 == ~T8_E~0); 61889#L1479-1 assume !(1 == ~T9_E~0); 61890#L1484-1 assume !(1 == ~T10_E~0); 62126#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61772#L1494-1 assume !(1 == ~T12_E~0); 61773#L1499-1 assume !(1 == ~T13_E~0); 61965#L1504-1 assume !(1 == ~E_M~0); 61966#L1509-1 assume !(1 == ~E_1~0); 62541#L1514-1 assume !(1 == ~E_2~0); 62228#L1519-1 assume !(1 == ~E_3~0); 62229#L1524-1 assume !(1 == ~E_4~0); 62741#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 62742#L1534-1 assume !(1 == ~E_6~0); 60912#L1539-1 assume !(1 == ~E_7~0); 60913#L1544-1 assume !(1 == ~E_8~0); 61327#L1549-1 assume !(1 == ~E_9~0); 62716#L1554-1 assume !(1 == ~E_10~0); 62712#L1559-1 assume !(1 == ~E_11~0); 62579#L1564-1 assume !(1 == ~E_12~0); 62580#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 62737#L1574-1 assume { :end_inline_reset_delta_events } true; 61089#L1940-2 [2022-02-21 04:23:29,299 INFO L793 eck$LassoCheckResult]: Loop: 61089#L1940-2 assume !false; 61090#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61372#L1266 assume !false; 62391#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61620#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61353#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61744#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 61745#L1079 assume !(0 != eval_~tmp~0#1); 61706#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61707#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62311#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 62196#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62197#L1296-3 assume !(0 == ~T2_E~0); 62769#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62723#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61854#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61130#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61131#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61231#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 61988#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62237#L1336-3 assume !(0 == ~T10_E~0); 62238#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 61558#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 61538#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 61483#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 61484#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62045#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60834#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60835#L1376-3 assume !(0 == ~E_4~0); 62564#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62424#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62425#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62587#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62588#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 61197#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 61051#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 61052#L1416-3 assume !(0 == ~E_12~0); 61713#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 61714#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61821#L640-45 assume !(1 == ~m_pc~0); 61822#L640-47 is_master_triggered_~__retres1~0#1 := 0; 61288#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61289#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60828#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60829#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60927#L659-45 assume 1 == ~t1_pc~0; 60928#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 61367#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62326#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62327#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62348#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62349#L678-45 assume 1 == ~t2_pc~0; 62292#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61827#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61828#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61980#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62605#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62722#L697-45 assume 1 == ~t3_pc~0; 62085#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62086#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62674#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62244#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62245#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62275#L716-45 assume 1 == ~t4_pc~0; 61906#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61907#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62457#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61912#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61913#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61575#L735-45 assume 1 == ~t5_pc~0; 61576#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62119#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62681#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62682#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62740#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62735#L754-45 assume 1 == ~t6_pc~0; 62067#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62068#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61497#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61498#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62071#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61803#L773-45 assume !(1 == ~t7_pc~0); 61360#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 61361#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62281#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62563#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 61809#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61479#L792-45 assume 1 == ~t8_pc~0; 61480#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62509#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61082#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60941#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60942#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61437#L811-45 assume 1 == ~t9_pc~0; 61226#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61228#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62436#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62271#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61880#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61672#L830-45 assume !(1 == ~t10_pc~0); 60869#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 60870#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61992#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61102#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61103#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60848#L849-45 assume !(1 == ~t11_pc~0); 60849#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 61308#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60939#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60836#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 60837#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61095#L868-45 assume 1 == ~t12_pc~0; 61096#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61035#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61036#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 62374#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 62625#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 62626#L887-45 assume !(1 == ~t13_pc~0); 61104#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 61105#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 62387#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 62732#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 61067#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61068#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62375#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61087#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61088#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61245#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62176#L1459-3 assume !(1 == ~T5_E~0); 62177#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62628#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62567#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62568#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62629#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61861#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61862#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 62498#L1499-3 assume !(1 == ~T13_E~0); 62137#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62138#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62576#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62606#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61780#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61781#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62648#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62048#L1539-3 assume !(1 == ~E_7~0); 61524#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61525#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 62020#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 61141#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 61142#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 62276#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 62277#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61018#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60789#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61064#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 61025#L1959 assume !(0 == start_simulation_~tmp~3#1); 61027#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61059#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61009#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 62318#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 62439#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 62646#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 62660#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 62661#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 61089#L1940-2 [2022-02-21 04:23:29,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:29,300 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2022-02-21 04:23:29,300 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:29,300 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002682727] [2022-02-21 04:23:29,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:29,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:29,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:29,324 INFO L290 TraceCheckUtils]: 0: Hoare triple {66848#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {66848#true} is VALID [2022-02-21 04:23:29,325 INFO L290 TraceCheckUtils]: 1: Hoare triple {66848#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,325 INFO L290 TraceCheckUtils]: 2: Hoare triple {66850#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,326 INFO L290 TraceCheckUtils]: 3: Hoare triple {66850#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,326 INFO L290 TraceCheckUtils]: 4: Hoare triple {66850#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,326 INFO L290 TraceCheckUtils]: 5: Hoare triple {66850#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,326 INFO L290 TraceCheckUtils]: 6: Hoare triple {66850#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,327 INFO L290 TraceCheckUtils]: 7: Hoare triple {66850#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,327 INFO L290 TraceCheckUtils]: 8: Hoare triple {66850#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,327 INFO L290 TraceCheckUtils]: 9: Hoare triple {66850#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,328 INFO L290 TraceCheckUtils]: 10: Hoare triple {66850#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,328 INFO L290 TraceCheckUtils]: 11: Hoare triple {66850#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {66850#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,328 INFO L290 TraceCheckUtils]: 12: Hoare triple {66850#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {66849#false} is VALID [2022-02-21 04:23:29,329 INFO L290 TraceCheckUtils]: 13: Hoare triple {66849#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {66849#false} is VALID [2022-02-21 04:23:29,329 INFO L290 TraceCheckUtils]: 14: Hoare triple {66849#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {66849#false} is VALID [2022-02-21 04:23:29,329 INFO L290 TraceCheckUtils]: 15: Hoare triple {66849#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {66849#false} is VALID [2022-02-21 04:23:29,329 INFO L290 TraceCheckUtils]: 16: Hoare triple {66849#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {66849#false} is VALID [2022-02-21 04:23:29,329 INFO L290 TraceCheckUtils]: 17: Hoare triple {66849#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {66849#false} is VALID [2022-02-21 04:23:29,329 INFO L290 TraceCheckUtils]: 18: Hoare triple {66849#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {66849#false} is VALID [2022-02-21 04:23:29,329 INFO L290 TraceCheckUtils]: 19: Hoare triple {66849#false} assume 0 == ~M_E~0;~M_E~0 := 1; {66849#false} is VALID [2022-02-21 04:23:29,330 INFO L290 TraceCheckUtils]: 20: Hoare triple {66849#false} assume !(0 == ~T1_E~0); {66849#false} is VALID [2022-02-21 04:23:29,330 INFO L290 TraceCheckUtils]: 21: Hoare triple {66849#false} assume !(0 == ~T2_E~0); {66849#false} is VALID [2022-02-21 04:23:29,330 INFO L290 TraceCheckUtils]: 22: Hoare triple {66849#false} assume !(0 == ~T3_E~0); {66849#false} is VALID [2022-02-21 04:23:29,330 INFO L290 TraceCheckUtils]: 23: Hoare triple {66849#false} assume !(0 == ~T4_E~0); {66849#false} is VALID [2022-02-21 04:23:29,330 INFO L290 TraceCheckUtils]: 24: Hoare triple {66849#false} assume !(0 == ~T5_E~0); {66849#false} is VALID [2022-02-21 04:23:29,330 INFO L290 TraceCheckUtils]: 25: Hoare triple {66849#false} assume !(0 == ~T6_E~0); {66849#false} is VALID [2022-02-21 04:23:29,330 INFO L290 TraceCheckUtils]: 26: Hoare triple {66849#false} assume !(0 == ~T7_E~0); {66849#false} is VALID [2022-02-21 04:23:29,331 INFO L290 TraceCheckUtils]: 27: Hoare triple {66849#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {66849#false} is VALID [2022-02-21 04:23:29,331 INFO L290 TraceCheckUtils]: 28: Hoare triple {66849#false} assume !(0 == ~T9_E~0); {66849#false} is VALID [2022-02-21 04:23:29,331 INFO L290 TraceCheckUtils]: 29: Hoare triple {66849#false} assume !(0 == ~T10_E~0); {66849#false} is VALID [2022-02-21 04:23:29,331 INFO L290 TraceCheckUtils]: 30: Hoare triple {66849#false} assume !(0 == ~T11_E~0); {66849#false} is VALID [2022-02-21 04:23:29,331 INFO L290 TraceCheckUtils]: 31: Hoare triple {66849#false} assume !(0 == ~T12_E~0); {66849#false} is VALID [2022-02-21 04:23:29,331 INFO L290 TraceCheckUtils]: 32: Hoare triple {66849#false} assume !(0 == ~T13_E~0); {66849#false} is VALID [2022-02-21 04:23:29,331 INFO L290 TraceCheckUtils]: 33: Hoare triple {66849#false} assume !(0 == ~E_M~0); {66849#false} is VALID [2022-02-21 04:23:29,332 INFO L290 TraceCheckUtils]: 34: Hoare triple {66849#false} assume !(0 == ~E_1~0); {66849#false} is VALID [2022-02-21 04:23:29,332 INFO L290 TraceCheckUtils]: 35: Hoare triple {66849#false} assume 0 == ~E_2~0;~E_2~0 := 1; {66849#false} is VALID [2022-02-21 04:23:29,332 INFO L290 TraceCheckUtils]: 36: Hoare triple {66849#false} assume !(0 == ~E_3~0); {66849#false} is VALID [2022-02-21 04:23:29,332 INFO L290 TraceCheckUtils]: 37: Hoare triple {66849#false} assume !(0 == ~E_4~0); {66849#false} is VALID [2022-02-21 04:23:29,332 INFO L290 TraceCheckUtils]: 38: Hoare triple {66849#false} assume !(0 == ~E_5~0); {66849#false} is VALID [2022-02-21 04:23:29,332 INFO L290 TraceCheckUtils]: 39: Hoare triple {66849#false} assume !(0 == ~E_6~0); {66849#false} is VALID [2022-02-21 04:23:29,332 INFO L290 TraceCheckUtils]: 40: Hoare triple {66849#false} assume !(0 == ~E_7~0); {66849#false} is VALID [2022-02-21 04:23:29,333 INFO L290 TraceCheckUtils]: 41: Hoare triple {66849#false} assume !(0 == ~E_8~0); {66849#false} is VALID [2022-02-21 04:23:29,333 INFO L290 TraceCheckUtils]: 42: Hoare triple {66849#false} assume !(0 == ~E_9~0); {66849#false} is VALID [2022-02-21 04:23:29,333 INFO L290 TraceCheckUtils]: 43: Hoare triple {66849#false} assume 0 == ~E_10~0;~E_10~0 := 1; {66849#false} is VALID [2022-02-21 04:23:29,333 INFO L290 TraceCheckUtils]: 44: Hoare triple {66849#false} assume !(0 == ~E_11~0); {66849#false} is VALID [2022-02-21 04:23:29,333 INFO L290 TraceCheckUtils]: 45: Hoare triple {66849#false} assume !(0 == ~E_12~0); {66849#false} is VALID [2022-02-21 04:23:29,333 INFO L290 TraceCheckUtils]: 46: Hoare triple {66849#false} assume !(0 == ~E_13~0); {66849#false} is VALID [2022-02-21 04:23:29,333 INFO L290 TraceCheckUtils]: 47: Hoare triple {66849#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66849#false} is VALID [2022-02-21 04:23:29,334 INFO L290 TraceCheckUtils]: 48: Hoare triple {66849#false} assume !(1 == ~m_pc~0); {66849#false} is VALID [2022-02-21 04:23:29,334 INFO L290 TraceCheckUtils]: 49: Hoare triple {66849#false} is_master_triggered_~__retres1~0#1 := 0; {66849#false} is VALID [2022-02-21 04:23:29,334 INFO L290 TraceCheckUtils]: 50: Hoare triple {66849#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66849#false} is VALID [2022-02-21 04:23:29,334 INFO L290 TraceCheckUtils]: 51: Hoare triple {66849#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {66849#false} is VALID [2022-02-21 04:23:29,334 INFO L290 TraceCheckUtils]: 52: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp~1#1); {66849#false} is VALID [2022-02-21 04:23:29,334 INFO L290 TraceCheckUtils]: 53: Hoare triple {66849#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66849#false} is VALID [2022-02-21 04:23:29,334 INFO L290 TraceCheckUtils]: 54: Hoare triple {66849#false} assume 1 == ~t1_pc~0; {66849#false} is VALID [2022-02-21 04:23:29,335 INFO L290 TraceCheckUtils]: 55: Hoare triple {66849#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {66849#false} is VALID [2022-02-21 04:23:29,335 INFO L290 TraceCheckUtils]: 56: Hoare triple {66849#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66849#false} is VALID [2022-02-21 04:23:29,335 INFO L290 TraceCheckUtils]: 57: Hoare triple {66849#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {66849#false} is VALID [2022-02-21 04:23:29,335 INFO L290 TraceCheckUtils]: 58: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___0~0#1); {66849#false} is VALID [2022-02-21 04:23:29,335 INFO L290 TraceCheckUtils]: 59: Hoare triple {66849#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66849#false} is VALID [2022-02-21 04:23:29,335 INFO L290 TraceCheckUtils]: 60: Hoare triple {66849#false} assume 1 == ~t2_pc~0; {66849#false} is VALID [2022-02-21 04:23:29,336 INFO L290 TraceCheckUtils]: 61: Hoare triple {66849#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {66849#false} is VALID [2022-02-21 04:23:29,336 INFO L290 TraceCheckUtils]: 62: Hoare triple {66849#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66849#false} is VALID [2022-02-21 04:23:29,336 INFO L290 TraceCheckUtils]: 63: Hoare triple {66849#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {66849#false} is VALID [2022-02-21 04:23:29,336 INFO L290 TraceCheckUtils]: 64: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___1~0#1); {66849#false} is VALID [2022-02-21 04:23:29,336 INFO L290 TraceCheckUtils]: 65: Hoare triple {66849#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66849#false} is VALID [2022-02-21 04:23:29,336 INFO L290 TraceCheckUtils]: 66: Hoare triple {66849#false} assume !(1 == ~t3_pc~0); {66849#false} is VALID [2022-02-21 04:23:29,336 INFO L290 TraceCheckUtils]: 67: Hoare triple {66849#false} is_transmit3_triggered_~__retres1~3#1 := 0; {66849#false} is VALID [2022-02-21 04:23:29,337 INFO L290 TraceCheckUtils]: 68: Hoare triple {66849#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66849#false} is VALID [2022-02-21 04:23:29,337 INFO L290 TraceCheckUtils]: 69: Hoare triple {66849#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {66849#false} is VALID [2022-02-21 04:23:29,337 INFO L290 TraceCheckUtils]: 70: Hoare triple {66849#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {66849#false} is VALID [2022-02-21 04:23:29,337 INFO L290 TraceCheckUtils]: 71: Hoare triple {66849#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66849#false} is VALID [2022-02-21 04:23:29,337 INFO L290 TraceCheckUtils]: 72: Hoare triple {66849#false} assume 1 == ~t4_pc~0; {66849#false} is VALID [2022-02-21 04:23:29,337 INFO L290 TraceCheckUtils]: 73: Hoare triple {66849#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {66849#false} is VALID [2022-02-21 04:23:29,337 INFO L290 TraceCheckUtils]: 74: Hoare triple {66849#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66849#false} is VALID [2022-02-21 04:23:29,338 INFO L290 TraceCheckUtils]: 75: Hoare triple {66849#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {66849#false} is VALID [2022-02-21 04:23:29,338 INFO L290 TraceCheckUtils]: 76: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___3~0#1); {66849#false} is VALID [2022-02-21 04:23:29,338 INFO L290 TraceCheckUtils]: 77: Hoare triple {66849#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66849#false} is VALID [2022-02-21 04:23:29,338 INFO L290 TraceCheckUtils]: 78: Hoare triple {66849#false} assume !(1 == ~t5_pc~0); {66849#false} is VALID [2022-02-21 04:23:29,338 INFO L290 TraceCheckUtils]: 79: Hoare triple {66849#false} is_transmit5_triggered_~__retres1~5#1 := 0; {66849#false} is VALID [2022-02-21 04:23:29,338 INFO L290 TraceCheckUtils]: 80: Hoare triple {66849#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66849#false} is VALID [2022-02-21 04:23:29,338 INFO L290 TraceCheckUtils]: 81: Hoare triple {66849#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {66849#false} is VALID [2022-02-21 04:23:29,339 INFO L290 TraceCheckUtils]: 82: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___4~0#1); {66849#false} is VALID [2022-02-21 04:23:29,339 INFO L290 TraceCheckUtils]: 83: Hoare triple {66849#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66849#false} is VALID [2022-02-21 04:23:29,339 INFO L290 TraceCheckUtils]: 84: Hoare triple {66849#false} assume 1 == ~t6_pc~0; {66849#false} is VALID [2022-02-21 04:23:29,339 INFO L290 TraceCheckUtils]: 85: Hoare triple {66849#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {66849#false} is VALID [2022-02-21 04:23:29,339 INFO L290 TraceCheckUtils]: 86: Hoare triple {66849#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66849#false} is VALID [2022-02-21 04:23:29,339 INFO L290 TraceCheckUtils]: 87: Hoare triple {66849#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {66849#false} is VALID [2022-02-21 04:23:29,339 INFO L290 TraceCheckUtils]: 88: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___5~0#1); {66849#false} is VALID [2022-02-21 04:23:29,340 INFO L290 TraceCheckUtils]: 89: Hoare triple {66849#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {66849#false} is VALID [2022-02-21 04:23:29,340 INFO L290 TraceCheckUtils]: 90: Hoare triple {66849#false} assume !(1 == ~t7_pc~0); {66849#false} is VALID [2022-02-21 04:23:29,340 INFO L290 TraceCheckUtils]: 91: Hoare triple {66849#false} is_transmit7_triggered_~__retres1~7#1 := 0; {66849#false} is VALID [2022-02-21 04:23:29,340 INFO L290 TraceCheckUtils]: 92: Hoare triple {66849#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {66849#false} is VALID [2022-02-21 04:23:29,340 INFO L290 TraceCheckUtils]: 93: Hoare triple {66849#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {66849#false} is VALID [2022-02-21 04:23:29,340 INFO L290 TraceCheckUtils]: 94: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___6~0#1); {66849#false} is VALID [2022-02-21 04:23:29,340 INFO L290 TraceCheckUtils]: 95: Hoare triple {66849#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {66849#false} is VALID [2022-02-21 04:23:29,341 INFO L290 TraceCheckUtils]: 96: Hoare triple {66849#false} assume 1 == ~t8_pc~0; {66849#false} is VALID [2022-02-21 04:23:29,341 INFO L290 TraceCheckUtils]: 97: Hoare triple {66849#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {66849#false} is VALID [2022-02-21 04:23:29,341 INFO L290 TraceCheckUtils]: 98: Hoare triple {66849#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {66849#false} is VALID [2022-02-21 04:23:29,341 INFO L290 TraceCheckUtils]: 99: Hoare triple {66849#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {66849#false} is VALID [2022-02-21 04:23:29,341 INFO L290 TraceCheckUtils]: 100: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___7~0#1); {66849#false} is VALID [2022-02-21 04:23:29,341 INFO L290 TraceCheckUtils]: 101: Hoare triple {66849#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {66849#false} is VALID [2022-02-21 04:23:29,341 INFO L290 TraceCheckUtils]: 102: Hoare triple {66849#false} assume 1 == ~t9_pc~0; {66849#false} is VALID [2022-02-21 04:23:29,342 INFO L290 TraceCheckUtils]: 103: Hoare triple {66849#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {66849#false} is VALID [2022-02-21 04:23:29,342 INFO L290 TraceCheckUtils]: 104: Hoare triple {66849#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {66849#false} is VALID [2022-02-21 04:23:29,342 INFO L290 TraceCheckUtils]: 105: Hoare triple {66849#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {66849#false} is VALID [2022-02-21 04:23:29,342 INFO L290 TraceCheckUtils]: 106: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___8~0#1); {66849#false} is VALID [2022-02-21 04:23:29,342 INFO L290 TraceCheckUtils]: 107: Hoare triple {66849#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {66849#false} is VALID [2022-02-21 04:23:29,342 INFO L290 TraceCheckUtils]: 108: Hoare triple {66849#false} assume !(1 == ~t10_pc~0); {66849#false} is VALID [2022-02-21 04:23:29,342 INFO L290 TraceCheckUtils]: 109: Hoare triple {66849#false} is_transmit10_triggered_~__retres1~10#1 := 0; {66849#false} is VALID [2022-02-21 04:23:29,343 INFO L290 TraceCheckUtils]: 110: Hoare triple {66849#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {66849#false} is VALID [2022-02-21 04:23:29,343 INFO L290 TraceCheckUtils]: 111: Hoare triple {66849#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {66849#false} is VALID [2022-02-21 04:23:29,343 INFO L290 TraceCheckUtils]: 112: Hoare triple {66849#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {66849#false} is VALID [2022-02-21 04:23:29,343 INFO L290 TraceCheckUtils]: 113: Hoare triple {66849#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {66849#false} is VALID [2022-02-21 04:23:29,343 INFO L290 TraceCheckUtils]: 114: Hoare triple {66849#false} assume 1 == ~t11_pc~0; {66849#false} is VALID [2022-02-21 04:23:29,343 INFO L290 TraceCheckUtils]: 115: Hoare triple {66849#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {66849#false} is VALID [2022-02-21 04:23:29,343 INFO L290 TraceCheckUtils]: 116: Hoare triple {66849#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {66849#false} is VALID [2022-02-21 04:23:29,344 INFO L290 TraceCheckUtils]: 117: Hoare triple {66849#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {66849#false} is VALID [2022-02-21 04:23:29,344 INFO L290 TraceCheckUtils]: 118: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___10~0#1); {66849#false} is VALID [2022-02-21 04:23:29,344 INFO L290 TraceCheckUtils]: 119: Hoare triple {66849#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {66849#false} is VALID [2022-02-21 04:23:29,344 INFO L290 TraceCheckUtils]: 120: Hoare triple {66849#false} assume !(1 == ~t12_pc~0); {66849#false} is VALID [2022-02-21 04:23:29,344 INFO L290 TraceCheckUtils]: 121: Hoare triple {66849#false} is_transmit12_triggered_~__retres1~12#1 := 0; {66849#false} is VALID [2022-02-21 04:23:29,344 INFO L290 TraceCheckUtils]: 122: Hoare triple {66849#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {66849#false} is VALID [2022-02-21 04:23:29,344 INFO L290 TraceCheckUtils]: 123: Hoare triple {66849#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {66849#false} is VALID [2022-02-21 04:23:29,345 INFO L290 TraceCheckUtils]: 124: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___11~0#1); {66849#false} is VALID [2022-02-21 04:23:29,345 INFO L290 TraceCheckUtils]: 125: Hoare triple {66849#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {66849#false} is VALID [2022-02-21 04:23:29,345 INFO L290 TraceCheckUtils]: 126: Hoare triple {66849#false} assume 1 == ~t13_pc~0; {66849#false} is VALID [2022-02-21 04:23:29,345 INFO L290 TraceCheckUtils]: 127: Hoare triple {66849#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {66849#false} is VALID [2022-02-21 04:23:29,345 INFO L290 TraceCheckUtils]: 128: Hoare triple {66849#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {66849#false} is VALID [2022-02-21 04:23:29,345 INFO L290 TraceCheckUtils]: 129: Hoare triple {66849#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {66849#false} is VALID [2022-02-21 04:23:29,345 INFO L290 TraceCheckUtils]: 130: Hoare triple {66849#false} assume !(0 != activate_threads_~tmp___12~0#1); {66849#false} is VALID [2022-02-21 04:23:29,346 INFO L290 TraceCheckUtils]: 131: Hoare triple {66849#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66849#false} is VALID [2022-02-21 04:23:29,346 INFO L290 TraceCheckUtils]: 132: Hoare triple {66849#false} assume !(1 == ~M_E~0); {66849#false} is VALID [2022-02-21 04:23:29,346 INFO L290 TraceCheckUtils]: 133: Hoare triple {66849#false} assume !(1 == ~T1_E~0); {66849#false} is VALID [2022-02-21 04:23:29,346 INFO L290 TraceCheckUtils]: 134: Hoare triple {66849#false} assume !(1 == ~T2_E~0); {66849#false} is VALID [2022-02-21 04:23:29,346 INFO L290 TraceCheckUtils]: 135: Hoare triple {66849#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {66849#false} is VALID [2022-02-21 04:23:29,346 INFO L290 TraceCheckUtils]: 136: Hoare triple {66849#false} assume !(1 == ~T4_E~0); {66849#false} is VALID [2022-02-21 04:23:29,346 INFO L290 TraceCheckUtils]: 137: Hoare triple {66849#false} assume !(1 == ~T5_E~0); {66849#false} is VALID [2022-02-21 04:23:29,347 INFO L290 TraceCheckUtils]: 138: Hoare triple {66849#false} assume !(1 == ~T6_E~0); {66849#false} is VALID [2022-02-21 04:23:29,347 INFO L290 TraceCheckUtils]: 139: Hoare triple {66849#false} assume !(1 == ~T7_E~0); {66849#false} is VALID [2022-02-21 04:23:29,347 INFO L290 TraceCheckUtils]: 140: Hoare triple {66849#false} assume !(1 == ~T8_E~0); {66849#false} is VALID [2022-02-21 04:23:29,347 INFO L290 TraceCheckUtils]: 141: Hoare triple {66849#false} assume !(1 == ~T9_E~0); {66849#false} is VALID [2022-02-21 04:23:29,347 INFO L290 TraceCheckUtils]: 142: Hoare triple {66849#false} assume !(1 == ~T10_E~0); {66849#false} is VALID [2022-02-21 04:23:29,347 INFO L290 TraceCheckUtils]: 143: Hoare triple {66849#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {66849#false} is VALID [2022-02-21 04:23:29,347 INFO L290 TraceCheckUtils]: 144: Hoare triple {66849#false} assume !(1 == ~T12_E~0); {66849#false} is VALID [2022-02-21 04:23:29,348 INFO L290 TraceCheckUtils]: 145: Hoare triple {66849#false} assume !(1 == ~T13_E~0); {66849#false} is VALID [2022-02-21 04:23:29,348 INFO L290 TraceCheckUtils]: 146: Hoare triple {66849#false} assume !(1 == ~E_M~0); {66849#false} is VALID [2022-02-21 04:23:29,348 INFO L290 TraceCheckUtils]: 147: Hoare triple {66849#false} assume !(1 == ~E_1~0); {66849#false} is VALID [2022-02-21 04:23:29,348 INFO L290 TraceCheckUtils]: 148: Hoare triple {66849#false} assume !(1 == ~E_2~0); {66849#false} is VALID [2022-02-21 04:23:29,348 INFO L290 TraceCheckUtils]: 149: Hoare triple {66849#false} assume !(1 == ~E_3~0); {66849#false} is VALID [2022-02-21 04:23:29,348 INFO L290 TraceCheckUtils]: 150: Hoare triple {66849#false} assume !(1 == ~E_4~0); {66849#false} is VALID [2022-02-21 04:23:29,348 INFO L290 TraceCheckUtils]: 151: Hoare triple {66849#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66849#false} is VALID [2022-02-21 04:23:29,349 INFO L290 TraceCheckUtils]: 152: Hoare triple {66849#false} assume !(1 == ~E_6~0); {66849#false} is VALID [2022-02-21 04:23:29,349 INFO L290 TraceCheckUtils]: 153: Hoare triple {66849#false} assume !(1 == ~E_7~0); {66849#false} is VALID [2022-02-21 04:23:29,349 INFO L290 TraceCheckUtils]: 154: Hoare triple {66849#false} assume !(1 == ~E_8~0); {66849#false} is VALID [2022-02-21 04:23:29,349 INFO L290 TraceCheckUtils]: 155: Hoare triple {66849#false} assume !(1 == ~E_9~0); {66849#false} is VALID [2022-02-21 04:23:29,349 INFO L290 TraceCheckUtils]: 156: Hoare triple {66849#false} assume !(1 == ~E_10~0); {66849#false} is VALID [2022-02-21 04:23:29,349 INFO L290 TraceCheckUtils]: 157: Hoare triple {66849#false} assume !(1 == ~E_11~0); {66849#false} is VALID [2022-02-21 04:23:29,349 INFO L290 TraceCheckUtils]: 158: Hoare triple {66849#false} assume !(1 == ~E_12~0); {66849#false} is VALID [2022-02-21 04:23:29,350 INFO L290 TraceCheckUtils]: 159: Hoare triple {66849#false} assume 1 == ~E_13~0;~E_13~0 := 2; {66849#false} is VALID [2022-02-21 04:23:29,350 INFO L290 TraceCheckUtils]: 160: Hoare triple {66849#false} assume { :end_inline_reset_delta_events } true; {66849#false} is VALID [2022-02-21 04:23:29,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:29,350 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:29,350 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2002682727] [2022-02-21 04:23:29,351 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2002682727] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:29,351 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:29,351 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:29,351 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343448929] [2022-02-21 04:23:29,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:29,352 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:29,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:29,352 INFO L85 PathProgramCache]: Analyzing trace with hash 230524959, now seen corresponding path program 2 times [2022-02-21 04:23:29,352 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:29,352 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49946154] [2022-02-21 04:23:29,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:29,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:29,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:29,386 INFO L290 TraceCheckUtils]: 0: Hoare triple {66851#true} assume !false; {66851#true} is VALID [2022-02-21 04:23:29,387 INFO L290 TraceCheckUtils]: 1: Hoare triple {66851#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {66851#true} is VALID [2022-02-21 04:23:29,387 INFO L290 TraceCheckUtils]: 2: Hoare triple {66851#true} assume !false; {66851#true} is VALID [2022-02-21 04:23:29,387 INFO L290 TraceCheckUtils]: 3: Hoare triple {66851#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {66851#true} is VALID [2022-02-21 04:23:29,387 INFO L290 TraceCheckUtils]: 4: Hoare triple {66851#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {66851#true} is VALID [2022-02-21 04:23:29,387 INFO L290 TraceCheckUtils]: 5: Hoare triple {66851#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {66851#true} is VALID [2022-02-21 04:23:29,387 INFO L290 TraceCheckUtils]: 6: Hoare triple {66851#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {66851#true} is VALID [2022-02-21 04:23:29,387 INFO L290 TraceCheckUtils]: 7: Hoare triple {66851#true} assume !(0 != eval_~tmp~0#1); {66851#true} is VALID [2022-02-21 04:23:29,388 INFO L290 TraceCheckUtils]: 8: Hoare triple {66851#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {66851#true} is VALID [2022-02-21 04:23:29,388 INFO L290 TraceCheckUtils]: 9: Hoare triple {66851#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {66851#true} is VALID [2022-02-21 04:23:29,388 INFO L290 TraceCheckUtils]: 10: Hoare triple {66851#true} assume 0 == ~M_E~0;~M_E~0 := 1; {66851#true} is VALID [2022-02-21 04:23:29,388 INFO L290 TraceCheckUtils]: 11: Hoare triple {66851#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {66851#true} is VALID [2022-02-21 04:23:29,388 INFO L290 TraceCheckUtils]: 12: Hoare triple {66851#true} assume !(0 == ~T2_E~0); {66851#true} is VALID [2022-02-21 04:23:29,388 INFO L290 TraceCheckUtils]: 13: Hoare triple {66851#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {66851#true} is VALID [2022-02-21 04:23:29,388 INFO L290 TraceCheckUtils]: 14: Hoare triple {66851#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {66851#true} is VALID [2022-02-21 04:23:29,389 INFO L290 TraceCheckUtils]: 15: Hoare triple {66851#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,389 INFO L290 TraceCheckUtils]: 16: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,390 INFO L290 TraceCheckUtils]: 17: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,390 INFO L290 TraceCheckUtils]: 18: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,390 INFO L290 TraceCheckUtils]: 19: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,391 INFO L290 TraceCheckUtils]: 20: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,391 INFO L290 TraceCheckUtils]: 21: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,391 INFO L290 TraceCheckUtils]: 22: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,392 INFO L290 TraceCheckUtils]: 23: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,392 INFO L290 TraceCheckUtils]: 24: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,393 INFO L290 TraceCheckUtils]: 25: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,393 INFO L290 TraceCheckUtils]: 26: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,393 INFO L290 TraceCheckUtils]: 27: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,394 INFO L290 TraceCheckUtils]: 28: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,394 INFO L290 TraceCheckUtils]: 29: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,394 INFO L290 TraceCheckUtils]: 30: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,395 INFO L290 TraceCheckUtils]: 31: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,395 INFO L290 TraceCheckUtils]: 32: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,395 INFO L290 TraceCheckUtils]: 33: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,396 INFO L290 TraceCheckUtils]: 34: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,396 INFO L290 TraceCheckUtils]: 35: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,397 INFO L290 TraceCheckUtils]: 36: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,397 INFO L290 TraceCheckUtils]: 37: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,397 INFO L290 TraceCheckUtils]: 38: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,398 INFO L290 TraceCheckUtils]: 39: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,398 INFO L290 TraceCheckUtils]: 40: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,398 INFO L290 TraceCheckUtils]: 41: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,399 INFO L290 TraceCheckUtils]: 42: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,399 INFO L290 TraceCheckUtils]: 43: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,399 INFO L290 TraceCheckUtils]: 44: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,400 INFO L290 TraceCheckUtils]: 45: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,400 INFO L290 TraceCheckUtils]: 46: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,401 INFO L290 TraceCheckUtils]: 47: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,401 INFO L290 TraceCheckUtils]: 48: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,401 INFO L290 TraceCheckUtils]: 49: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,402 INFO L290 TraceCheckUtils]: 50: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,402 INFO L290 TraceCheckUtils]: 51: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,402 INFO L290 TraceCheckUtils]: 52: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,403 INFO L290 TraceCheckUtils]: 53: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,403 INFO L290 TraceCheckUtils]: 54: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,404 INFO L290 TraceCheckUtils]: 55: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,404 INFO L290 TraceCheckUtils]: 56: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,404 INFO L290 TraceCheckUtils]: 57: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,405 INFO L290 TraceCheckUtils]: 58: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,405 INFO L290 TraceCheckUtils]: 59: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,405 INFO L290 TraceCheckUtils]: 60: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,406 INFO L290 TraceCheckUtils]: 61: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,406 INFO L290 TraceCheckUtils]: 62: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,407 INFO L290 TraceCheckUtils]: 63: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,407 INFO L290 TraceCheckUtils]: 64: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,407 INFO L290 TraceCheckUtils]: 65: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,408 INFO L290 TraceCheckUtils]: 66: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,408 INFO L290 TraceCheckUtils]: 67: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,408 INFO L290 TraceCheckUtils]: 68: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,409 INFO L290 TraceCheckUtils]: 69: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,409 INFO L290 TraceCheckUtils]: 70: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,410 INFO L290 TraceCheckUtils]: 71: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,410 INFO L290 TraceCheckUtils]: 72: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,410 INFO L290 TraceCheckUtils]: 73: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,411 INFO L290 TraceCheckUtils]: 74: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,411 INFO L290 TraceCheckUtils]: 75: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,411 INFO L290 TraceCheckUtils]: 76: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,412 INFO L290 TraceCheckUtils]: 77: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,412 INFO L290 TraceCheckUtils]: 78: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,412 INFO L290 TraceCheckUtils]: 79: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,413 INFO L290 TraceCheckUtils]: 80: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,413 INFO L290 TraceCheckUtils]: 81: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,414 INFO L290 TraceCheckUtils]: 82: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,414 INFO L290 TraceCheckUtils]: 83: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,414 INFO L290 TraceCheckUtils]: 84: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,415 INFO L290 TraceCheckUtils]: 85: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,415 INFO L290 TraceCheckUtils]: 86: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,416 INFO L290 TraceCheckUtils]: 87: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,416 INFO L290 TraceCheckUtils]: 88: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,416 INFO L290 TraceCheckUtils]: 89: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,417 INFO L290 TraceCheckUtils]: 90: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,417 INFO L290 TraceCheckUtils]: 91: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,417 INFO L290 TraceCheckUtils]: 92: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,418 INFO L290 TraceCheckUtils]: 93: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,418 INFO L290 TraceCheckUtils]: 94: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,418 INFO L290 TraceCheckUtils]: 95: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,419 INFO L290 TraceCheckUtils]: 96: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,419 INFO L290 TraceCheckUtils]: 97: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,420 INFO L290 TraceCheckUtils]: 98: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,420 INFO L290 TraceCheckUtils]: 99: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,420 INFO L290 TraceCheckUtils]: 100: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,421 INFO L290 TraceCheckUtils]: 101: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,421 INFO L290 TraceCheckUtils]: 102: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,421 INFO L290 TraceCheckUtils]: 103: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,422 INFO L290 TraceCheckUtils]: 104: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,422 INFO L290 TraceCheckUtils]: 105: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,423 INFO L290 TraceCheckUtils]: 106: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,423 INFO L290 TraceCheckUtils]: 107: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,423 INFO L290 TraceCheckUtils]: 108: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,424 INFO L290 TraceCheckUtils]: 109: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,424 INFO L290 TraceCheckUtils]: 110: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,424 INFO L290 TraceCheckUtils]: 111: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,425 INFO L290 TraceCheckUtils]: 112: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,425 INFO L290 TraceCheckUtils]: 113: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,426 INFO L290 TraceCheckUtils]: 114: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,426 INFO L290 TraceCheckUtils]: 115: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,426 INFO L290 TraceCheckUtils]: 116: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,427 INFO L290 TraceCheckUtils]: 117: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,427 INFO L290 TraceCheckUtils]: 118: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,427 INFO L290 TraceCheckUtils]: 119: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,428 INFO L290 TraceCheckUtils]: 120: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,428 INFO L290 TraceCheckUtils]: 121: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,428 INFO L290 TraceCheckUtils]: 122: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,429 INFO L290 TraceCheckUtils]: 123: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,429 INFO L290 TraceCheckUtils]: 124: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,430 INFO L290 TraceCheckUtils]: 125: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,430 INFO L290 TraceCheckUtils]: 126: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,430 INFO L290 TraceCheckUtils]: 127: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {66853#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:29,431 INFO L290 TraceCheckUtils]: 128: Hoare triple {66853#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {66852#false} is VALID [2022-02-21 04:23:29,431 INFO L290 TraceCheckUtils]: 129: Hoare triple {66852#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,431 INFO L290 TraceCheckUtils]: 130: Hoare triple {66852#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,431 INFO L290 TraceCheckUtils]: 131: Hoare triple {66852#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,431 INFO L290 TraceCheckUtils]: 132: Hoare triple {66852#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,431 INFO L290 TraceCheckUtils]: 133: Hoare triple {66852#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,432 INFO L290 TraceCheckUtils]: 134: Hoare triple {66852#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,432 INFO L290 TraceCheckUtils]: 135: Hoare triple {66852#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,432 INFO L290 TraceCheckUtils]: 136: Hoare triple {66852#false} assume !(1 == ~T13_E~0); {66852#false} is VALID [2022-02-21 04:23:29,432 INFO L290 TraceCheckUtils]: 137: Hoare triple {66852#false} assume 1 == ~E_M~0;~E_M~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,432 INFO L290 TraceCheckUtils]: 138: Hoare triple {66852#false} assume 1 == ~E_1~0;~E_1~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,432 INFO L290 TraceCheckUtils]: 139: Hoare triple {66852#false} assume 1 == ~E_2~0;~E_2~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,432 INFO L290 TraceCheckUtils]: 140: Hoare triple {66852#false} assume 1 == ~E_3~0;~E_3~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,433 INFO L290 TraceCheckUtils]: 141: Hoare triple {66852#false} assume 1 == ~E_4~0;~E_4~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,433 INFO L290 TraceCheckUtils]: 142: Hoare triple {66852#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,433 INFO L290 TraceCheckUtils]: 143: Hoare triple {66852#false} assume 1 == ~E_6~0;~E_6~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,433 INFO L290 TraceCheckUtils]: 144: Hoare triple {66852#false} assume !(1 == ~E_7~0); {66852#false} is VALID [2022-02-21 04:23:29,433 INFO L290 TraceCheckUtils]: 145: Hoare triple {66852#false} assume 1 == ~E_8~0;~E_8~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,433 INFO L290 TraceCheckUtils]: 146: Hoare triple {66852#false} assume 1 == ~E_9~0;~E_9~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,433 INFO L290 TraceCheckUtils]: 147: Hoare triple {66852#false} assume 1 == ~E_10~0;~E_10~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,434 INFO L290 TraceCheckUtils]: 148: Hoare triple {66852#false} assume 1 == ~E_11~0;~E_11~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,434 INFO L290 TraceCheckUtils]: 149: Hoare triple {66852#false} assume 1 == ~E_12~0;~E_12~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,434 INFO L290 TraceCheckUtils]: 150: Hoare triple {66852#false} assume 1 == ~E_13~0;~E_13~0 := 2; {66852#false} is VALID [2022-02-21 04:23:29,434 INFO L290 TraceCheckUtils]: 151: Hoare triple {66852#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {66852#false} is VALID [2022-02-21 04:23:29,434 INFO L290 TraceCheckUtils]: 152: Hoare triple {66852#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {66852#false} is VALID [2022-02-21 04:23:29,434 INFO L290 TraceCheckUtils]: 153: Hoare triple {66852#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {66852#false} is VALID [2022-02-21 04:23:29,434 INFO L290 TraceCheckUtils]: 154: Hoare triple {66852#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {66852#false} is VALID [2022-02-21 04:23:29,443 INFO L290 TraceCheckUtils]: 155: Hoare triple {66852#false} assume !(0 == start_simulation_~tmp~3#1); {66852#false} is VALID [2022-02-21 04:23:29,443 INFO L290 TraceCheckUtils]: 156: Hoare triple {66852#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {66852#false} is VALID [2022-02-21 04:23:29,443 INFO L290 TraceCheckUtils]: 157: Hoare triple {66852#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {66852#false} is VALID [2022-02-21 04:23:29,443 INFO L290 TraceCheckUtils]: 158: Hoare triple {66852#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {66852#false} is VALID [2022-02-21 04:23:29,444 INFO L290 TraceCheckUtils]: 159: Hoare triple {66852#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {66852#false} is VALID [2022-02-21 04:23:29,444 INFO L290 TraceCheckUtils]: 160: Hoare triple {66852#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {66852#false} is VALID [2022-02-21 04:23:29,444 INFO L290 TraceCheckUtils]: 161: Hoare triple {66852#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {66852#false} is VALID [2022-02-21 04:23:29,444 INFO L290 TraceCheckUtils]: 162: Hoare triple {66852#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {66852#false} is VALID [2022-02-21 04:23:29,444 INFO L290 TraceCheckUtils]: 163: Hoare triple {66852#false} assume !(0 != start_simulation_~tmp___0~1#1); {66852#false} is VALID [2022-02-21 04:23:29,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:29,445 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:29,445 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [49946154] [2022-02-21 04:23:29,445 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [49946154] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:29,445 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:29,446 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:29,446 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653447852] [2022-02-21 04:23:29,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:29,446 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:29,446 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:29,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:29,447 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:29,447 INFO L87 Difference]: Start difference. First operand 2023 states and 2989 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:30,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:30,912 INFO L93 Difference]: Finished difference Result 2023 states and 2988 transitions. [2022-02-21 04:23:30,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:30,913 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,022 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:31,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2988 transitions. [2022-02-21 04:23:31,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:31,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2988 transitions. [2022-02-21 04:23:31,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:31,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:31,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2988 transitions. [2022-02-21 04:23:31,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:31,240 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2022-02-21 04:23:31,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2988 transitions. [2022-02-21 04:23:31,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:31,257 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:31,259 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2988 transitions. Second operand has 2023 states, 2023 states have (on average 1.4770143351458231) internal successors, (2988), 2022 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,261 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2988 transitions. Second operand has 2023 states, 2023 states have (on average 1.4770143351458231) internal successors, (2988), 2022 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,262 INFO L87 Difference]: Start difference. First operand 2023 states and 2988 transitions. Second operand has 2023 states, 2023 states have (on average 1.4770143351458231) internal successors, (2988), 2022 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:31,362 INFO L93 Difference]: Finished difference Result 2023 states and 2988 transitions. [2022-02-21 04:23:31,362 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2988 transitions. [2022-02-21 04:23:31,363 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:31,363 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:31,365 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4770143351458231) internal successors, (2988), 2022 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2988 transitions. [2022-02-21 04:23:31,366 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4770143351458231) internal successors, (2988), 2022 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2988 transitions. [2022-02-21 04:23:31,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:31,464 INFO L93 Difference]: Finished difference Result 2023 states and 2988 transitions. [2022-02-21 04:23:31,464 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2988 transitions. [2022-02-21 04:23:31,466 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:31,466 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:31,466 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:31,466 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:31,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4770143351458231) internal successors, (2988), 2022 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2988 transitions. [2022-02-21 04:23:31,564 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2022-02-21 04:23:31,564 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2022-02-21 04:23:31,564 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:23:31,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2988 transitions. [2022-02-21 04:23:31,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:31,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:31,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:31,569 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:31,569 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:31,569 INFO L791 eck$LassoCheckResult]: Stem: 69804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 69805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 70803#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70804#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70889#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 70268#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69737#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69738#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70554#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 70555#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 70655#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 70656#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69509#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 69510#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70685#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 70045#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 70046#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 70606#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 69947#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69948#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 70890#L1291-2 assume !(0 == ~T1_E~0); 70888#L1296-1 assume !(0 == ~T2_E~0); 70104#L1301-1 assume !(0 == ~T3_E~0); 70105#L1306-1 assume !(0 == ~T4_E~0); 70614#L1311-1 assume !(0 == ~T5_E~0); 69352#L1316-1 assume !(0 == ~T6_E~0); 69353#L1321-1 assume !(0 == ~T7_E~0); 70117#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 69180#L1331-1 assume !(0 == ~T9_E~0); 68879#L1336-1 assume !(0 == ~T10_E~0); 68880#L1341-1 assume !(0 == ~T11_E~0); 68960#L1346-1 assume !(0 == ~T12_E~0); 68961#L1351-1 assume !(0 == ~T13_E~0); 69301#L1356-1 assume !(0 == ~E_M~0); 69302#L1361-1 assume !(0 == ~E_1~0); 70829#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 69342#L1371-1 assume !(0 == ~E_3~0); 69343#L1376-1 assume !(0 == ~E_4~0); 70164#L1381-1 assume !(0 == ~E_5~0); 70165#L1386-1 assume !(0 == ~E_6~0); 70859#L1391-1 assume !(0 == ~E_7~0); 70877#L1396-1 assume !(0 == ~E_8~0); 70077#L1401-1 assume !(0 == ~E_9~0); 70078#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 70356#L1411-1 assume !(0 == ~E_11~0); 70357#L1416-1 assume !(0 == ~E_12~0); 69989#L1421-1 assume !(0 == ~E_13~0); 69532#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69533#L640 assume !(1 == ~m_pc~0); 70042#L640-2 is_master_triggered_~__retres1~0#1 := 0; 70041#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70133#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70027#L1603 assume !(0 != activate_threads_~tmp~1#1); 70028#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69662#L659 assume 1 == ~t1_pc~0; 69663#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 69768#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70714#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69788#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 69789#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69802#L678 assume 1 == ~t2_pc~0; 70756#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 70757#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70856#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69900#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 69901#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70022#L697 assume !(1 == ~t3_pc~0); 70023#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 70145#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69953#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69932#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69933#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70793#L716 assume 1 == ~t4_pc~0; 70779#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 69643#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69644#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69143#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 69144#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70435#L735 assume !(1 == ~t5_pc~0); 69104#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69105#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69555#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70462#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 70098#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70099#L754 assume 1 == ~t6_pc~0; 69852#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69750#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69751#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69724#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 69725#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70545#L773 assume !(1 == ~t7_pc~0); 69305#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 69304#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70134#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70106#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 70107#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70154#L792 assume 1 == ~t8_pc~0; 70327#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 70659#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70148#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70101#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 70025#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70026#L811 assume 1 == ~t9_pc~0; 70230#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 70696#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70572#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 70226#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 70038#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70039#L830 assume !(1 == ~t10_pc~0); 69760#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 69284#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68977#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68978#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69265#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 70563#L849 assume 1 == ~t11_pc~0; 70564#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 69080#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69081#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69670#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 70469#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 70470#L868 assume !(1 == ~t12_pc~0); 69885#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69884#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69679#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69680#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 69316#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69317#L887 assume 1 == ~t13_pc~0; 70484#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69926#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69927#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 70363#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 69020#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69021#L1439 assume !(1 == ~M_E~0); 70094#L1439-2 assume !(1 == ~T1_E~0); 69192#L1444-1 assume !(1 == ~T2_E~0); 69193#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69666#L1454-1 assume !(1 == ~T4_E~0); 69667#L1459-1 assume !(1 == ~T5_E~0); 70223#L1464-1 assume !(1 == ~T6_E~0); 70224#L1469-1 assume !(1 == ~T7_E~0); 70296#L1474-1 assume !(1 == ~T8_E~0); 69990#L1479-1 assume !(1 == ~T9_E~0); 69991#L1484-1 assume !(1 == ~T10_E~0); 70227#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69873#L1494-1 assume !(1 == ~T12_E~0); 69874#L1499-1 assume !(1 == ~T13_E~0); 70066#L1504-1 assume !(1 == ~E_M~0); 70067#L1509-1 assume !(1 == ~E_1~0); 70642#L1514-1 assume !(1 == ~E_2~0); 70329#L1519-1 assume !(1 == ~E_3~0); 70330#L1524-1 assume !(1 == ~E_4~0); 70842#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 70843#L1534-1 assume !(1 == ~E_6~0); 69013#L1539-1 assume !(1 == ~E_7~0); 69014#L1544-1 assume !(1 == ~E_8~0); 69428#L1549-1 assume !(1 == ~E_9~0); 70817#L1554-1 assume !(1 == ~E_10~0); 70813#L1559-1 assume !(1 == ~E_11~0); 70680#L1564-1 assume !(1 == ~E_12~0); 70681#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 70838#L1574-1 assume { :end_inline_reset_delta_events } true; 69190#L1940-2 [2022-02-21 04:23:31,569 INFO L793 eck$LassoCheckResult]: Loop: 69190#L1940-2 assume !false; 69191#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69473#L1266 assume !false; 70492#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69721#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69454#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69845#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 69846#L1079 assume !(0 != eval_~tmp~0#1); 69807#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69808#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70412#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 70297#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 70298#L1296-3 assume !(0 == ~T2_E~0); 70870#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70824#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69955#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69231#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69232#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69332#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 70089#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 70338#L1336-3 assume !(0 == ~T10_E~0); 70339#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 69659#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 69639#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 69584#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69585#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 70146#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68935#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68936#L1376-3 assume !(0 == ~E_4~0); 70665#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70525#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70526#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70688#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 70689#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 69298#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 69152#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69153#L1416-3 assume !(0 == ~E_12~0); 69814#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 69815#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69922#L640-45 assume !(1 == ~m_pc~0); 69923#L640-47 is_master_triggered_~__retres1~0#1 := 0; 69389#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69390#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68929#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68930#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69028#L659-45 assume 1 == ~t1_pc~0; 69029#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 69468#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70427#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70428#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70449#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70450#L678-45 assume 1 == ~t2_pc~0; 70393#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69928#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69929#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70081#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70706#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70823#L697-45 assume 1 == ~t3_pc~0; 70186#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 70187#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70775#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70345#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70346#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70376#L716-45 assume 1 == ~t4_pc~0; 70007#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70008#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70558#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70013#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70014#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69676#L735-45 assume 1 == ~t5_pc~0; 69677#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 70220#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70782#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70783#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70841#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70836#L754-45 assume 1 == ~t6_pc~0; 70168#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 70169#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69598#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69599#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 70172#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69904#L773-45 assume 1 == ~t7_pc~0; 69905#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69462#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70382#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70664#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 69910#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69580#L792-45 assume 1 == ~t8_pc~0; 69581#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 70610#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69183#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69042#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 69043#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69538#L811-45 assume !(1 == ~t9_pc~0); 69328#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 69329#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70537#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 70372#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69981#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69773#L830-45 assume !(1 == ~t10_pc~0); 68970#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 68971#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70093#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69203#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69204#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 68949#L849-45 assume 1 == ~t11_pc~0; 68951#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 69409#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69040#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68937#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68938#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69196#L868-45 assume 1 == ~t12_pc~0; 69197#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 69136#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69137#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 70475#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 70726#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70727#L887-45 assume !(1 == ~t13_pc~0); 69205#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 69206#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 70488#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 70833#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 69168#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69169#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 70476#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69188#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69189#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69346#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70277#L1459-3 assume !(1 == ~T5_E~0); 70278#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70729#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70668#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70669#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70730#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69962#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69963#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70599#L1499-3 assume !(1 == ~T13_E~0); 70238#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70239#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70677#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70707#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69881#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69882#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70749#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70149#L1539-3 assume !(1 == ~E_7~0); 69625#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 69626#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70121#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 69242#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69243#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 70377#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 70378#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69119#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68890#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69165#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 69126#L1959 assume !(0 == start_simulation_~tmp~3#1); 69128#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69160#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69110#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 70419#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 70540#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70747#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70761#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 70762#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 69190#L1940-2 [2022-02-21 04:23:31,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:31,570 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2022-02-21 04:23:31,570 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:31,571 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976699008] [2022-02-21 04:23:31,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:31,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:31,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:31,598 INFO L290 TraceCheckUtils]: 0: Hoare triple {74949#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {74949#true} is VALID [2022-02-21 04:23:31,598 INFO L290 TraceCheckUtils]: 1: Hoare triple {74949#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,599 INFO L290 TraceCheckUtils]: 2: Hoare triple {74951#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,599 INFO L290 TraceCheckUtils]: 3: Hoare triple {74951#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,599 INFO L290 TraceCheckUtils]: 4: Hoare triple {74951#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,600 INFO L290 TraceCheckUtils]: 5: Hoare triple {74951#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,600 INFO L290 TraceCheckUtils]: 6: Hoare triple {74951#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,600 INFO L290 TraceCheckUtils]: 7: Hoare triple {74951#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,601 INFO L290 TraceCheckUtils]: 8: Hoare triple {74951#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,601 INFO L290 TraceCheckUtils]: 9: Hoare triple {74951#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,601 INFO L290 TraceCheckUtils]: 10: Hoare triple {74951#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,602 INFO L290 TraceCheckUtils]: 11: Hoare triple {74951#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,602 INFO L290 TraceCheckUtils]: 12: Hoare triple {74951#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,602 INFO L290 TraceCheckUtils]: 13: Hoare triple {74951#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {74951#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 14: Hoare triple {74951#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {74950#false} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 15: Hoare triple {74950#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {74950#false} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 16: Hoare triple {74950#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {74950#false} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 17: Hoare triple {74950#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {74950#false} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 18: Hoare triple {74950#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {74950#false} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 19: Hoare triple {74950#false} assume 0 == ~M_E~0;~M_E~0 := 1; {74950#false} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 20: Hoare triple {74950#false} assume !(0 == ~T1_E~0); {74950#false} is VALID [2022-02-21 04:23:31,604 INFO L290 TraceCheckUtils]: 21: Hoare triple {74950#false} assume !(0 == ~T2_E~0); {74950#false} is VALID [2022-02-21 04:23:31,604 INFO L290 TraceCheckUtils]: 22: Hoare triple {74950#false} assume !(0 == ~T3_E~0); {74950#false} is VALID [2022-02-21 04:23:31,604 INFO L290 TraceCheckUtils]: 23: Hoare triple {74950#false} assume !(0 == ~T4_E~0); {74950#false} is VALID [2022-02-21 04:23:31,604 INFO L290 TraceCheckUtils]: 24: Hoare triple {74950#false} assume !(0 == ~T5_E~0); {74950#false} is VALID [2022-02-21 04:23:31,604 INFO L290 TraceCheckUtils]: 25: Hoare triple {74950#false} assume !(0 == ~T6_E~0); {74950#false} is VALID [2022-02-21 04:23:31,604 INFO L290 TraceCheckUtils]: 26: Hoare triple {74950#false} assume !(0 == ~T7_E~0); {74950#false} is VALID [2022-02-21 04:23:31,604 INFO L290 TraceCheckUtils]: 27: Hoare triple {74950#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {74950#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 28: Hoare triple {74950#false} assume !(0 == ~T9_E~0); {74950#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 29: Hoare triple {74950#false} assume !(0 == ~T10_E~0); {74950#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 30: Hoare triple {74950#false} assume !(0 == ~T11_E~0); {74950#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 31: Hoare triple {74950#false} assume !(0 == ~T12_E~0); {74950#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 32: Hoare triple {74950#false} assume !(0 == ~T13_E~0); {74950#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 33: Hoare triple {74950#false} assume !(0 == ~E_M~0); {74950#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 34: Hoare triple {74950#false} assume !(0 == ~E_1~0); {74950#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 35: Hoare triple {74950#false} assume 0 == ~E_2~0;~E_2~0 := 1; {74950#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 36: Hoare triple {74950#false} assume !(0 == ~E_3~0); {74950#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 37: Hoare triple {74950#false} assume !(0 == ~E_4~0); {74950#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 38: Hoare triple {74950#false} assume !(0 == ~E_5~0); {74950#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 39: Hoare triple {74950#false} assume !(0 == ~E_6~0); {74950#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 40: Hoare triple {74950#false} assume !(0 == ~E_7~0); {74950#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 41: Hoare triple {74950#false} assume !(0 == ~E_8~0); {74950#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 42: Hoare triple {74950#false} assume !(0 == ~E_9~0); {74950#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 43: Hoare triple {74950#false} assume 0 == ~E_10~0;~E_10~0 := 1; {74950#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 44: Hoare triple {74950#false} assume !(0 == ~E_11~0); {74950#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 45: Hoare triple {74950#false} assume !(0 == ~E_12~0); {74950#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 46: Hoare triple {74950#false} assume !(0 == ~E_13~0); {74950#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 47: Hoare triple {74950#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {74950#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 48: Hoare triple {74950#false} assume !(1 == ~m_pc~0); {74950#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 49: Hoare triple {74950#false} is_master_triggered_~__retres1~0#1 := 0; {74950#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 50: Hoare triple {74950#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {74950#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 51: Hoare triple {74950#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {74950#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 52: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp~1#1); {74950#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 53: Hoare triple {74950#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {74950#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 54: Hoare triple {74950#false} assume 1 == ~t1_pc~0; {74950#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 55: Hoare triple {74950#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {74950#false} is VALID [2022-02-21 04:23:31,609 INFO L290 TraceCheckUtils]: 56: Hoare triple {74950#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {74950#false} is VALID [2022-02-21 04:23:31,609 INFO L290 TraceCheckUtils]: 57: Hoare triple {74950#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {74950#false} is VALID [2022-02-21 04:23:31,609 INFO L290 TraceCheckUtils]: 58: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___0~0#1); {74950#false} is VALID [2022-02-21 04:23:31,609 INFO L290 TraceCheckUtils]: 59: Hoare triple {74950#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {74950#false} is VALID [2022-02-21 04:23:31,609 INFO L290 TraceCheckUtils]: 60: Hoare triple {74950#false} assume 1 == ~t2_pc~0; {74950#false} is VALID [2022-02-21 04:23:31,609 INFO L290 TraceCheckUtils]: 61: Hoare triple {74950#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {74950#false} is VALID [2022-02-21 04:23:31,609 INFO L290 TraceCheckUtils]: 62: Hoare triple {74950#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {74950#false} is VALID [2022-02-21 04:23:31,610 INFO L290 TraceCheckUtils]: 63: Hoare triple {74950#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {74950#false} is VALID [2022-02-21 04:23:31,610 INFO L290 TraceCheckUtils]: 64: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___1~0#1); {74950#false} is VALID [2022-02-21 04:23:31,610 INFO L290 TraceCheckUtils]: 65: Hoare triple {74950#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {74950#false} is VALID [2022-02-21 04:23:31,610 INFO L290 TraceCheckUtils]: 66: Hoare triple {74950#false} assume !(1 == ~t3_pc~0); {74950#false} is VALID [2022-02-21 04:23:31,610 INFO L290 TraceCheckUtils]: 67: Hoare triple {74950#false} is_transmit3_triggered_~__retres1~3#1 := 0; {74950#false} is VALID [2022-02-21 04:23:31,610 INFO L290 TraceCheckUtils]: 68: Hoare triple {74950#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {74950#false} is VALID [2022-02-21 04:23:31,610 INFO L290 TraceCheckUtils]: 69: Hoare triple {74950#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {74950#false} is VALID [2022-02-21 04:23:31,611 INFO L290 TraceCheckUtils]: 70: Hoare triple {74950#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {74950#false} is VALID [2022-02-21 04:23:31,611 INFO L290 TraceCheckUtils]: 71: Hoare triple {74950#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {74950#false} is VALID [2022-02-21 04:23:31,611 INFO L290 TraceCheckUtils]: 72: Hoare triple {74950#false} assume 1 == ~t4_pc~0; {74950#false} is VALID [2022-02-21 04:23:31,611 INFO L290 TraceCheckUtils]: 73: Hoare triple {74950#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {74950#false} is VALID [2022-02-21 04:23:31,611 INFO L290 TraceCheckUtils]: 74: Hoare triple {74950#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {74950#false} is VALID [2022-02-21 04:23:31,611 INFO L290 TraceCheckUtils]: 75: Hoare triple {74950#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {74950#false} is VALID [2022-02-21 04:23:31,611 INFO L290 TraceCheckUtils]: 76: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___3~0#1); {74950#false} is VALID [2022-02-21 04:23:31,612 INFO L290 TraceCheckUtils]: 77: Hoare triple {74950#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {74950#false} is VALID [2022-02-21 04:23:31,612 INFO L290 TraceCheckUtils]: 78: Hoare triple {74950#false} assume !(1 == ~t5_pc~0); {74950#false} is VALID [2022-02-21 04:23:31,612 INFO L290 TraceCheckUtils]: 79: Hoare triple {74950#false} is_transmit5_triggered_~__retres1~5#1 := 0; {74950#false} is VALID [2022-02-21 04:23:31,612 INFO L290 TraceCheckUtils]: 80: Hoare triple {74950#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {74950#false} is VALID [2022-02-21 04:23:31,612 INFO L290 TraceCheckUtils]: 81: Hoare triple {74950#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {74950#false} is VALID [2022-02-21 04:23:31,612 INFO L290 TraceCheckUtils]: 82: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___4~0#1); {74950#false} is VALID [2022-02-21 04:23:31,612 INFO L290 TraceCheckUtils]: 83: Hoare triple {74950#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {74950#false} is VALID [2022-02-21 04:23:31,613 INFO L290 TraceCheckUtils]: 84: Hoare triple {74950#false} assume 1 == ~t6_pc~0; {74950#false} is VALID [2022-02-21 04:23:31,613 INFO L290 TraceCheckUtils]: 85: Hoare triple {74950#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {74950#false} is VALID [2022-02-21 04:23:31,613 INFO L290 TraceCheckUtils]: 86: Hoare triple {74950#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {74950#false} is VALID [2022-02-21 04:23:31,613 INFO L290 TraceCheckUtils]: 87: Hoare triple {74950#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {74950#false} is VALID [2022-02-21 04:23:31,613 INFO L290 TraceCheckUtils]: 88: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___5~0#1); {74950#false} is VALID [2022-02-21 04:23:31,613 INFO L290 TraceCheckUtils]: 89: Hoare triple {74950#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {74950#false} is VALID [2022-02-21 04:23:31,613 INFO L290 TraceCheckUtils]: 90: Hoare triple {74950#false} assume !(1 == ~t7_pc~0); {74950#false} is VALID [2022-02-21 04:23:31,614 INFO L290 TraceCheckUtils]: 91: Hoare triple {74950#false} is_transmit7_triggered_~__retres1~7#1 := 0; {74950#false} is VALID [2022-02-21 04:23:31,614 INFO L290 TraceCheckUtils]: 92: Hoare triple {74950#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {74950#false} is VALID [2022-02-21 04:23:31,614 INFO L290 TraceCheckUtils]: 93: Hoare triple {74950#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {74950#false} is VALID [2022-02-21 04:23:31,614 INFO L290 TraceCheckUtils]: 94: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___6~0#1); {74950#false} is VALID [2022-02-21 04:23:31,614 INFO L290 TraceCheckUtils]: 95: Hoare triple {74950#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {74950#false} is VALID [2022-02-21 04:23:31,614 INFO L290 TraceCheckUtils]: 96: Hoare triple {74950#false} assume 1 == ~t8_pc~0; {74950#false} is VALID [2022-02-21 04:23:31,614 INFO L290 TraceCheckUtils]: 97: Hoare triple {74950#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {74950#false} is VALID [2022-02-21 04:23:31,615 INFO L290 TraceCheckUtils]: 98: Hoare triple {74950#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {74950#false} is VALID [2022-02-21 04:23:31,615 INFO L290 TraceCheckUtils]: 99: Hoare triple {74950#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {74950#false} is VALID [2022-02-21 04:23:31,615 INFO L290 TraceCheckUtils]: 100: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___7~0#1); {74950#false} is VALID [2022-02-21 04:23:31,615 INFO L290 TraceCheckUtils]: 101: Hoare triple {74950#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {74950#false} is VALID [2022-02-21 04:23:31,615 INFO L290 TraceCheckUtils]: 102: Hoare triple {74950#false} assume 1 == ~t9_pc~0; {74950#false} is VALID [2022-02-21 04:23:31,615 INFO L290 TraceCheckUtils]: 103: Hoare triple {74950#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {74950#false} is VALID [2022-02-21 04:23:31,615 INFO L290 TraceCheckUtils]: 104: Hoare triple {74950#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {74950#false} is VALID [2022-02-21 04:23:31,616 INFO L290 TraceCheckUtils]: 105: Hoare triple {74950#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {74950#false} is VALID [2022-02-21 04:23:31,616 INFO L290 TraceCheckUtils]: 106: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___8~0#1); {74950#false} is VALID [2022-02-21 04:23:31,616 INFO L290 TraceCheckUtils]: 107: Hoare triple {74950#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {74950#false} is VALID [2022-02-21 04:23:31,616 INFO L290 TraceCheckUtils]: 108: Hoare triple {74950#false} assume !(1 == ~t10_pc~0); {74950#false} is VALID [2022-02-21 04:23:31,616 INFO L290 TraceCheckUtils]: 109: Hoare triple {74950#false} is_transmit10_triggered_~__retres1~10#1 := 0; {74950#false} is VALID [2022-02-21 04:23:31,616 INFO L290 TraceCheckUtils]: 110: Hoare triple {74950#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {74950#false} is VALID [2022-02-21 04:23:31,616 INFO L290 TraceCheckUtils]: 111: Hoare triple {74950#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {74950#false} is VALID [2022-02-21 04:23:31,617 INFO L290 TraceCheckUtils]: 112: Hoare triple {74950#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {74950#false} is VALID [2022-02-21 04:23:31,617 INFO L290 TraceCheckUtils]: 113: Hoare triple {74950#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {74950#false} is VALID [2022-02-21 04:23:31,617 INFO L290 TraceCheckUtils]: 114: Hoare triple {74950#false} assume 1 == ~t11_pc~0; {74950#false} is VALID [2022-02-21 04:23:31,617 INFO L290 TraceCheckUtils]: 115: Hoare triple {74950#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {74950#false} is VALID [2022-02-21 04:23:31,617 INFO L290 TraceCheckUtils]: 116: Hoare triple {74950#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {74950#false} is VALID [2022-02-21 04:23:31,617 INFO L290 TraceCheckUtils]: 117: Hoare triple {74950#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {74950#false} is VALID [2022-02-21 04:23:31,617 INFO L290 TraceCheckUtils]: 118: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___10~0#1); {74950#false} is VALID [2022-02-21 04:23:31,618 INFO L290 TraceCheckUtils]: 119: Hoare triple {74950#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {74950#false} is VALID [2022-02-21 04:23:31,618 INFO L290 TraceCheckUtils]: 120: Hoare triple {74950#false} assume !(1 == ~t12_pc~0); {74950#false} is VALID [2022-02-21 04:23:31,618 INFO L290 TraceCheckUtils]: 121: Hoare triple {74950#false} is_transmit12_triggered_~__retres1~12#1 := 0; {74950#false} is VALID [2022-02-21 04:23:31,618 INFO L290 TraceCheckUtils]: 122: Hoare triple {74950#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {74950#false} is VALID [2022-02-21 04:23:31,618 INFO L290 TraceCheckUtils]: 123: Hoare triple {74950#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {74950#false} is VALID [2022-02-21 04:23:31,618 INFO L290 TraceCheckUtils]: 124: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___11~0#1); {74950#false} is VALID [2022-02-21 04:23:31,618 INFO L290 TraceCheckUtils]: 125: Hoare triple {74950#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {74950#false} is VALID [2022-02-21 04:23:31,619 INFO L290 TraceCheckUtils]: 126: Hoare triple {74950#false} assume 1 == ~t13_pc~0; {74950#false} is VALID [2022-02-21 04:23:31,619 INFO L290 TraceCheckUtils]: 127: Hoare triple {74950#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {74950#false} is VALID [2022-02-21 04:23:31,619 INFO L290 TraceCheckUtils]: 128: Hoare triple {74950#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {74950#false} is VALID [2022-02-21 04:23:31,619 INFO L290 TraceCheckUtils]: 129: Hoare triple {74950#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {74950#false} is VALID [2022-02-21 04:23:31,619 INFO L290 TraceCheckUtils]: 130: Hoare triple {74950#false} assume !(0 != activate_threads_~tmp___12~0#1); {74950#false} is VALID [2022-02-21 04:23:31,619 INFO L290 TraceCheckUtils]: 131: Hoare triple {74950#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {74950#false} is VALID [2022-02-21 04:23:31,619 INFO L290 TraceCheckUtils]: 132: Hoare triple {74950#false} assume !(1 == ~M_E~0); {74950#false} is VALID [2022-02-21 04:23:31,620 INFO L290 TraceCheckUtils]: 133: Hoare triple {74950#false} assume !(1 == ~T1_E~0); {74950#false} is VALID [2022-02-21 04:23:31,620 INFO L290 TraceCheckUtils]: 134: Hoare triple {74950#false} assume !(1 == ~T2_E~0); {74950#false} is VALID [2022-02-21 04:23:31,620 INFO L290 TraceCheckUtils]: 135: Hoare triple {74950#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {74950#false} is VALID [2022-02-21 04:23:31,620 INFO L290 TraceCheckUtils]: 136: Hoare triple {74950#false} assume !(1 == ~T4_E~0); {74950#false} is VALID [2022-02-21 04:23:31,620 INFO L290 TraceCheckUtils]: 137: Hoare triple {74950#false} assume !(1 == ~T5_E~0); {74950#false} is VALID [2022-02-21 04:23:31,620 INFO L290 TraceCheckUtils]: 138: Hoare triple {74950#false} assume !(1 == ~T6_E~0); {74950#false} is VALID [2022-02-21 04:23:31,620 INFO L290 TraceCheckUtils]: 139: Hoare triple {74950#false} assume !(1 == ~T7_E~0); {74950#false} is VALID [2022-02-21 04:23:31,621 INFO L290 TraceCheckUtils]: 140: Hoare triple {74950#false} assume !(1 == ~T8_E~0); {74950#false} is VALID [2022-02-21 04:23:31,621 INFO L290 TraceCheckUtils]: 141: Hoare triple {74950#false} assume !(1 == ~T9_E~0); {74950#false} is VALID [2022-02-21 04:23:31,621 INFO L290 TraceCheckUtils]: 142: Hoare triple {74950#false} assume !(1 == ~T10_E~0); {74950#false} is VALID [2022-02-21 04:23:31,621 INFO L290 TraceCheckUtils]: 143: Hoare triple {74950#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {74950#false} is VALID [2022-02-21 04:23:31,621 INFO L290 TraceCheckUtils]: 144: Hoare triple {74950#false} assume !(1 == ~T12_E~0); {74950#false} is VALID [2022-02-21 04:23:31,621 INFO L290 TraceCheckUtils]: 145: Hoare triple {74950#false} assume !(1 == ~T13_E~0); {74950#false} is VALID [2022-02-21 04:23:31,621 INFO L290 TraceCheckUtils]: 146: Hoare triple {74950#false} assume !(1 == ~E_M~0); {74950#false} is VALID [2022-02-21 04:23:31,622 INFO L290 TraceCheckUtils]: 147: Hoare triple {74950#false} assume !(1 == ~E_1~0); {74950#false} is VALID [2022-02-21 04:23:31,622 INFO L290 TraceCheckUtils]: 148: Hoare triple {74950#false} assume !(1 == ~E_2~0); {74950#false} is VALID [2022-02-21 04:23:31,622 INFO L290 TraceCheckUtils]: 149: Hoare triple {74950#false} assume !(1 == ~E_3~0); {74950#false} is VALID [2022-02-21 04:23:31,622 INFO L290 TraceCheckUtils]: 150: Hoare triple {74950#false} assume !(1 == ~E_4~0); {74950#false} is VALID [2022-02-21 04:23:31,622 INFO L290 TraceCheckUtils]: 151: Hoare triple {74950#false} assume 1 == ~E_5~0;~E_5~0 := 2; {74950#false} is VALID [2022-02-21 04:23:31,622 INFO L290 TraceCheckUtils]: 152: Hoare triple {74950#false} assume !(1 == ~E_6~0); {74950#false} is VALID [2022-02-21 04:23:31,623 INFO L290 TraceCheckUtils]: 153: Hoare triple {74950#false} assume !(1 == ~E_7~0); {74950#false} is VALID [2022-02-21 04:23:31,623 INFO L290 TraceCheckUtils]: 154: Hoare triple {74950#false} assume !(1 == ~E_8~0); {74950#false} is VALID [2022-02-21 04:23:31,623 INFO L290 TraceCheckUtils]: 155: Hoare triple {74950#false} assume !(1 == ~E_9~0); {74950#false} is VALID [2022-02-21 04:23:31,623 INFO L290 TraceCheckUtils]: 156: Hoare triple {74950#false} assume !(1 == ~E_10~0); {74950#false} is VALID [2022-02-21 04:23:31,623 INFO L290 TraceCheckUtils]: 157: Hoare triple {74950#false} assume !(1 == ~E_11~0); {74950#false} is VALID [2022-02-21 04:23:31,623 INFO L290 TraceCheckUtils]: 158: Hoare triple {74950#false} assume !(1 == ~E_12~0); {74950#false} is VALID [2022-02-21 04:23:31,623 INFO L290 TraceCheckUtils]: 159: Hoare triple {74950#false} assume 1 == ~E_13~0;~E_13~0 := 2; {74950#false} is VALID [2022-02-21 04:23:31,624 INFO L290 TraceCheckUtils]: 160: Hoare triple {74950#false} assume { :end_inline_reset_delta_events } true; {74950#false} is VALID [2022-02-21 04:23:31,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:31,624 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:31,624 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976699008] [2022-02-21 04:23:31,624 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [976699008] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:31,625 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:31,625 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:31,625 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312669761] [2022-02-21 04:23:31,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:31,626 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:31,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:31,627 INFO L85 PathProgramCache]: Analyzing trace with hash 706682270, now seen corresponding path program 1 times [2022-02-21 04:23:31,627 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:31,627 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1924196220] [2022-02-21 04:23:31,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:31,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:31,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:31,727 INFO L290 TraceCheckUtils]: 0: Hoare triple {74952#true} assume !false; {74952#true} is VALID [2022-02-21 04:23:31,727 INFO L290 TraceCheckUtils]: 1: Hoare triple {74952#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {74952#true} is VALID [2022-02-21 04:23:31,727 INFO L290 TraceCheckUtils]: 2: Hoare triple {74952#true} assume !false; {74952#true} is VALID [2022-02-21 04:23:31,727 INFO L290 TraceCheckUtils]: 3: Hoare triple {74952#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {74952#true} is VALID [2022-02-21 04:23:31,727 INFO L290 TraceCheckUtils]: 4: Hoare triple {74952#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {74952#true} is VALID [2022-02-21 04:23:31,728 INFO L290 TraceCheckUtils]: 5: Hoare triple {74952#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {74952#true} is VALID [2022-02-21 04:23:31,728 INFO L290 TraceCheckUtils]: 6: Hoare triple {74952#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {74952#true} is VALID [2022-02-21 04:23:31,728 INFO L290 TraceCheckUtils]: 7: Hoare triple {74952#true} assume !(0 != eval_~tmp~0#1); {74952#true} is VALID [2022-02-21 04:23:31,728 INFO L290 TraceCheckUtils]: 8: Hoare triple {74952#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {74952#true} is VALID [2022-02-21 04:23:31,728 INFO L290 TraceCheckUtils]: 9: Hoare triple {74952#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {74952#true} is VALID [2022-02-21 04:23:31,728 INFO L290 TraceCheckUtils]: 10: Hoare triple {74952#true} assume 0 == ~M_E~0;~M_E~0 := 1; {74952#true} is VALID [2022-02-21 04:23:31,728 INFO L290 TraceCheckUtils]: 11: Hoare triple {74952#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {74952#true} is VALID [2022-02-21 04:23:31,728 INFO L290 TraceCheckUtils]: 12: Hoare triple {74952#true} assume !(0 == ~T2_E~0); {74952#true} is VALID [2022-02-21 04:23:31,728 INFO L290 TraceCheckUtils]: 13: Hoare triple {74952#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {74952#true} is VALID [2022-02-21 04:23:31,728 INFO L290 TraceCheckUtils]: 14: Hoare triple {74952#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {74952#true} is VALID [2022-02-21 04:23:31,729 INFO L290 TraceCheckUtils]: 15: Hoare triple {74952#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,729 INFO L290 TraceCheckUtils]: 16: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,730 INFO L290 TraceCheckUtils]: 17: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,730 INFO L290 TraceCheckUtils]: 18: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,731 INFO L290 TraceCheckUtils]: 19: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,731 INFO L290 TraceCheckUtils]: 20: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,731 INFO L290 TraceCheckUtils]: 21: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,732 INFO L290 TraceCheckUtils]: 22: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,732 INFO L290 TraceCheckUtils]: 23: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,732 INFO L290 TraceCheckUtils]: 24: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,733 INFO L290 TraceCheckUtils]: 25: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,733 INFO L290 TraceCheckUtils]: 26: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,734 INFO L290 TraceCheckUtils]: 27: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,734 INFO L290 TraceCheckUtils]: 28: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,734 INFO L290 TraceCheckUtils]: 29: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,735 INFO L290 TraceCheckUtils]: 30: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,735 INFO L290 TraceCheckUtils]: 31: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,735 INFO L290 TraceCheckUtils]: 32: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,736 INFO L290 TraceCheckUtils]: 33: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,736 INFO L290 TraceCheckUtils]: 34: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,737 INFO L290 TraceCheckUtils]: 35: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,737 INFO L290 TraceCheckUtils]: 36: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,737 INFO L290 TraceCheckUtils]: 37: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,738 INFO L290 TraceCheckUtils]: 38: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,738 INFO L290 TraceCheckUtils]: 39: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,738 INFO L290 TraceCheckUtils]: 40: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,739 INFO L290 TraceCheckUtils]: 41: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,739 INFO L290 TraceCheckUtils]: 42: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,740 INFO L290 TraceCheckUtils]: 43: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,740 INFO L290 TraceCheckUtils]: 44: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,740 INFO L290 TraceCheckUtils]: 45: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,741 INFO L290 TraceCheckUtils]: 46: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,741 INFO L290 TraceCheckUtils]: 47: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,741 INFO L290 TraceCheckUtils]: 48: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,742 INFO L290 TraceCheckUtils]: 49: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,742 INFO L290 TraceCheckUtils]: 50: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,742 INFO L290 TraceCheckUtils]: 51: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,743 INFO L290 TraceCheckUtils]: 52: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,743 INFO L290 TraceCheckUtils]: 53: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,744 INFO L290 TraceCheckUtils]: 54: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,744 INFO L290 TraceCheckUtils]: 55: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,744 INFO L290 TraceCheckUtils]: 56: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,745 INFO L290 TraceCheckUtils]: 57: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,745 INFO L290 TraceCheckUtils]: 58: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,745 INFO L290 TraceCheckUtils]: 59: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,746 INFO L290 TraceCheckUtils]: 60: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,746 INFO L290 TraceCheckUtils]: 61: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,747 INFO L290 TraceCheckUtils]: 62: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,747 INFO L290 TraceCheckUtils]: 63: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,747 INFO L290 TraceCheckUtils]: 64: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,748 INFO L290 TraceCheckUtils]: 65: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,748 INFO L290 TraceCheckUtils]: 66: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,748 INFO L290 TraceCheckUtils]: 67: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,749 INFO L290 TraceCheckUtils]: 68: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,749 INFO L290 TraceCheckUtils]: 69: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,750 INFO L290 TraceCheckUtils]: 70: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,750 INFO L290 TraceCheckUtils]: 71: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,750 INFO L290 TraceCheckUtils]: 72: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,751 INFO L290 TraceCheckUtils]: 73: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,751 INFO L290 TraceCheckUtils]: 74: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,751 INFO L290 TraceCheckUtils]: 75: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,752 INFO L290 TraceCheckUtils]: 76: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,752 INFO L290 TraceCheckUtils]: 77: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,752 INFO L290 TraceCheckUtils]: 78: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,753 INFO L290 TraceCheckUtils]: 79: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,753 INFO L290 TraceCheckUtils]: 80: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,754 INFO L290 TraceCheckUtils]: 81: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,754 INFO L290 TraceCheckUtils]: 82: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,754 INFO L290 TraceCheckUtils]: 83: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,755 INFO L290 TraceCheckUtils]: 84: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,755 INFO L290 TraceCheckUtils]: 85: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,755 INFO L290 TraceCheckUtils]: 86: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,756 INFO L290 TraceCheckUtils]: 87: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,756 INFO L290 TraceCheckUtils]: 88: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,757 INFO L290 TraceCheckUtils]: 89: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,757 INFO L290 TraceCheckUtils]: 90: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,757 INFO L290 TraceCheckUtils]: 91: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,758 INFO L290 TraceCheckUtils]: 92: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,758 INFO L290 TraceCheckUtils]: 93: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,758 INFO L290 TraceCheckUtils]: 94: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,759 INFO L290 TraceCheckUtils]: 95: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,759 INFO L290 TraceCheckUtils]: 96: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,760 INFO L290 TraceCheckUtils]: 97: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,760 INFO L290 TraceCheckUtils]: 98: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,760 INFO L290 TraceCheckUtils]: 99: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,761 INFO L290 TraceCheckUtils]: 100: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,761 INFO L290 TraceCheckUtils]: 101: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,761 INFO L290 TraceCheckUtils]: 102: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,762 INFO L290 TraceCheckUtils]: 103: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,762 INFO L290 TraceCheckUtils]: 104: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,763 INFO L290 TraceCheckUtils]: 105: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,763 INFO L290 TraceCheckUtils]: 106: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,763 INFO L290 TraceCheckUtils]: 107: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,764 INFO L290 TraceCheckUtils]: 108: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,764 INFO L290 TraceCheckUtils]: 109: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,764 INFO L290 TraceCheckUtils]: 110: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,765 INFO L290 TraceCheckUtils]: 111: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,765 INFO L290 TraceCheckUtils]: 112: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,766 INFO L290 TraceCheckUtils]: 113: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,766 INFO L290 TraceCheckUtils]: 114: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,766 INFO L290 TraceCheckUtils]: 115: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,767 INFO L290 TraceCheckUtils]: 116: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,767 INFO L290 TraceCheckUtils]: 117: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,767 INFO L290 TraceCheckUtils]: 118: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,768 INFO L290 TraceCheckUtils]: 119: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,768 INFO L290 TraceCheckUtils]: 120: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,769 INFO L290 TraceCheckUtils]: 121: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,769 INFO L290 TraceCheckUtils]: 122: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,769 INFO L290 TraceCheckUtils]: 123: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,770 INFO L290 TraceCheckUtils]: 124: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,770 INFO L290 TraceCheckUtils]: 125: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,771 INFO L290 TraceCheckUtils]: 126: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,771 INFO L290 TraceCheckUtils]: 127: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {74954#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:31,771 INFO L290 TraceCheckUtils]: 128: Hoare triple {74954#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {74953#false} is VALID [2022-02-21 04:23:31,771 INFO L290 TraceCheckUtils]: 129: Hoare triple {74953#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,772 INFO L290 TraceCheckUtils]: 130: Hoare triple {74953#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,772 INFO L290 TraceCheckUtils]: 131: Hoare triple {74953#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,772 INFO L290 TraceCheckUtils]: 132: Hoare triple {74953#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,772 INFO L290 TraceCheckUtils]: 133: Hoare triple {74953#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,772 INFO L290 TraceCheckUtils]: 134: Hoare triple {74953#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,772 INFO L290 TraceCheckUtils]: 135: Hoare triple {74953#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,772 INFO L290 TraceCheckUtils]: 136: Hoare triple {74953#false} assume !(1 == ~T13_E~0); {74953#false} is VALID [2022-02-21 04:23:31,773 INFO L290 TraceCheckUtils]: 137: Hoare triple {74953#false} assume 1 == ~E_M~0;~E_M~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,773 INFO L290 TraceCheckUtils]: 138: Hoare triple {74953#false} assume 1 == ~E_1~0;~E_1~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,773 INFO L290 TraceCheckUtils]: 139: Hoare triple {74953#false} assume 1 == ~E_2~0;~E_2~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,773 INFO L290 TraceCheckUtils]: 140: Hoare triple {74953#false} assume 1 == ~E_3~0;~E_3~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,773 INFO L290 TraceCheckUtils]: 141: Hoare triple {74953#false} assume 1 == ~E_4~0;~E_4~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,773 INFO L290 TraceCheckUtils]: 142: Hoare triple {74953#false} assume 1 == ~E_5~0;~E_5~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,773 INFO L290 TraceCheckUtils]: 143: Hoare triple {74953#false} assume 1 == ~E_6~0;~E_6~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,774 INFO L290 TraceCheckUtils]: 144: Hoare triple {74953#false} assume !(1 == ~E_7~0); {74953#false} is VALID [2022-02-21 04:23:31,774 INFO L290 TraceCheckUtils]: 145: Hoare triple {74953#false} assume 1 == ~E_8~0;~E_8~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,774 INFO L290 TraceCheckUtils]: 146: Hoare triple {74953#false} assume 1 == ~E_9~0;~E_9~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,774 INFO L290 TraceCheckUtils]: 147: Hoare triple {74953#false} assume 1 == ~E_10~0;~E_10~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,774 INFO L290 TraceCheckUtils]: 148: Hoare triple {74953#false} assume 1 == ~E_11~0;~E_11~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,774 INFO L290 TraceCheckUtils]: 149: Hoare triple {74953#false} assume 1 == ~E_12~0;~E_12~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,774 INFO L290 TraceCheckUtils]: 150: Hoare triple {74953#false} assume 1 == ~E_13~0;~E_13~0 := 2; {74953#false} is VALID [2022-02-21 04:23:31,775 INFO L290 TraceCheckUtils]: 151: Hoare triple {74953#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {74953#false} is VALID [2022-02-21 04:23:31,775 INFO L290 TraceCheckUtils]: 152: Hoare triple {74953#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {74953#false} is VALID [2022-02-21 04:23:31,775 INFO L290 TraceCheckUtils]: 153: Hoare triple {74953#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {74953#false} is VALID [2022-02-21 04:23:31,775 INFO L290 TraceCheckUtils]: 154: Hoare triple {74953#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {74953#false} is VALID [2022-02-21 04:23:31,775 INFO L290 TraceCheckUtils]: 155: Hoare triple {74953#false} assume !(0 == start_simulation_~tmp~3#1); {74953#false} is VALID [2022-02-21 04:23:31,775 INFO L290 TraceCheckUtils]: 156: Hoare triple {74953#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {74953#false} is VALID [2022-02-21 04:23:31,775 INFO L290 TraceCheckUtils]: 157: Hoare triple {74953#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {74953#false} is VALID [2022-02-21 04:23:31,776 INFO L290 TraceCheckUtils]: 158: Hoare triple {74953#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {74953#false} is VALID [2022-02-21 04:23:31,776 INFO L290 TraceCheckUtils]: 159: Hoare triple {74953#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {74953#false} is VALID [2022-02-21 04:23:31,776 INFO L290 TraceCheckUtils]: 160: Hoare triple {74953#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {74953#false} is VALID [2022-02-21 04:23:31,776 INFO L290 TraceCheckUtils]: 161: Hoare triple {74953#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {74953#false} is VALID [2022-02-21 04:23:31,776 INFO L290 TraceCheckUtils]: 162: Hoare triple {74953#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {74953#false} is VALID [2022-02-21 04:23:31,776 INFO L290 TraceCheckUtils]: 163: Hoare triple {74953#false} assume !(0 != start_simulation_~tmp___0~1#1); {74953#false} is VALID [2022-02-21 04:23:31,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:31,777 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:31,777 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1924196220] [2022-02-21 04:23:31,777 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1924196220] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:31,778 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:31,778 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:31,778 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265684881] [2022-02-21 04:23:31,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:31,778 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:31,779 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:31,779 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:31,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:31,779 INFO L87 Difference]: Start difference. First operand 2023 states and 2988 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:33,245 INFO L93 Difference]: Finished difference Result 2023 states and 2987 transitions. [2022-02-21 04:23:33,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:33,246 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,340 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:33,340 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2987 transitions. [2022-02-21 04:23:33,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:33,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2987 transitions. [2022-02-21 04:23:33,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:33,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:33,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2987 transitions. [2022-02-21 04:23:33,516 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:33,516 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2022-02-21 04:23:33,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2987 transitions. [2022-02-21 04:23:33,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:33,534 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:33,536 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2987 transitions. Second operand has 2023 states, 2023 states have (on average 1.476520019772615) internal successors, (2987), 2022 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,538 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2987 transitions. Second operand has 2023 states, 2023 states have (on average 1.476520019772615) internal successors, (2987), 2022 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,539 INFO L87 Difference]: Start difference. First operand 2023 states and 2987 transitions. Second operand has 2023 states, 2023 states have (on average 1.476520019772615) internal successors, (2987), 2022 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:33,650 INFO L93 Difference]: Finished difference Result 2023 states and 2987 transitions. [2022-02-21 04:23:33,650 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2987 transitions. [2022-02-21 04:23:33,651 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:33,651 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:33,653 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.476520019772615) internal successors, (2987), 2022 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2987 transitions. [2022-02-21 04:23:33,654 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.476520019772615) internal successors, (2987), 2022 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2987 transitions. [2022-02-21 04:23:33,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:33,737 INFO L93 Difference]: Finished difference Result 2023 states and 2987 transitions. [2022-02-21 04:23:33,737 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2987 transitions. [2022-02-21 04:23:33,738 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:33,738 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:33,739 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:33,739 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:33,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.476520019772615) internal successors, (2987), 2022 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2987 transitions. [2022-02-21 04:23:33,824 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2022-02-21 04:23:33,824 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2022-02-21 04:23:33,824 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:23:33,824 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2987 transitions. [2022-02-21 04:23:33,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:33,827 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:33,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:33,828 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:33,828 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:33,828 INFO L791 eck$LassoCheckResult]: Stem: 77905#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 77906#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 78904#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 78905#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78990#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 78369#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77838#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77839#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78655#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78656#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78756#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 78757#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77610#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77611#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 78786#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 78146#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 78147#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 78707#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 78048#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 78049#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 78991#L1291-2 assume !(0 == ~T1_E~0); 78989#L1296-1 assume !(0 == ~T2_E~0); 78205#L1301-1 assume !(0 == ~T3_E~0); 78206#L1306-1 assume !(0 == ~T4_E~0); 78715#L1311-1 assume !(0 == ~T5_E~0); 77453#L1316-1 assume !(0 == ~T6_E~0); 77454#L1321-1 assume !(0 == ~T7_E~0); 78218#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 77281#L1331-1 assume !(0 == ~T9_E~0); 76980#L1336-1 assume !(0 == ~T10_E~0); 76981#L1341-1 assume !(0 == ~T11_E~0); 77061#L1346-1 assume !(0 == ~T12_E~0); 77062#L1351-1 assume !(0 == ~T13_E~0); 77402#L1356-1 assume !(0 == ~E_M~0); 77403#L1361-1 assume !(0 == ~E_1~0); 78930#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 77443#L1371-1 assume !(0 == ~E_3~0); 77444#L1376-1 assume !(0 == ~E_4~0); 78265#L1381-1 assume !(0 == ~E_5~0); 78266#L1386-1 assume !(0 == ~E_6~0); 78960#L1391-1 assume !(0 == ~E_7~0); 78978#L1396-1 assume !(0 == ~E_8~0); 78178#L1401-1 assume !(0 == ~E_9~0); 78179#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 78457#L1411-1 assume !(0 == ~E_11~0); 78458#L1416-1 assume !(0 == ~E_12~0); 78090#L1421-1 assume !(0 == ~E_13~0); 77633#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77634#L640 assume !(1 == ~m_pc~0); 78143#L640-2 is_master_triggered_~__retres1~0#1 := 0; 78142#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78234#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78128#L1603 assume !(0 != activate_threads_~tmp~1#1); 78129#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77763#L659 assume 1 == ~t1_pc~0; 77764#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77869#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78815#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77889#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 77890#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77903#L678 assume 1 == ~t2_pc~0; 78857#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78858#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78957#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78001#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 78002#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78123#L697 assume !(1 == ~t3_pc~0); 78124#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 78246#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78054#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78033#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78034#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78894#L716 assume 1 == ~t4_pc~0; 78880#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77744#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77745#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77244#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 77245#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78536#L735 assume !(1 == ~t5_pc~0); 77205#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 77206#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77656#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78563#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 78199#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78200#L754 assume 1 == ~t6_pc~0; 77953#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77851#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77852#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77825#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 77826#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78646#L773 assume !(1 == ~t7_pc~0); 77406#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 77405#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78235#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78207#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 78208#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78255#L792 assume 1 == ~t8_pc~0; 78428#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 78760#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78249#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78202#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 78126#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78127#L811 assume 1 == ~t9_pc~0; 78331#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78797#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78673#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78327#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 78139#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78140#L830 assume !(1 == ~t10_pc~0); 77861#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 77385#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77078#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 77079#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77366#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78664#L849 assume 1 == ~t11_pc~0; 78665#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77181#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77182#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77771#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 78570#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78571#L868 assume !(1 == ~t12_pc~0); 77986#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 77985#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77780#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77781#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 77417#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77418#L887 assume 1 == ~t13_pc~0; 78585#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 78027#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78028#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 78464#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 77121#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77122#L1439 assume !(1 == ~M_E~0); 78195#L1439-2 assume !(1 == ~T1_E~0); 77293#L1444-1 assume !(1 == ~T2_E~0); 77294#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77767#L1454-1 assume !(1 == ~T4_E~0); 77768#L1459-1 assume !(1 == ~T5_E~0); 78324#L1464-1 assume !(1 == ~T6_E~0); 78325#L1469-1 assume !(1 == ~T7_E~0); 78397#L1474-1 assume !(1 == ~T8_E~0); 78091#L1479-1 assume !(1 == ~T9_E~0); 78092#L1484-1 assume !(1 == ~T10_E~0); 78328#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77974#L1494-1 assume !(1 == ~T12_E~0); 77975#L1499-1 assume !(1 == ~T13_E~0); 78167#L1504-1 assume !(1 == ~E_M~0); 78168#L1509-1 assume !(1 == ~E_1~0); 78743#L1514-1 assume !(1 == ~E_2~0); 78430#L1519-1 assume !(1 == ~E_3~0); 78431#L1524-1 assume !(1 == ~E_4~0); 78943#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 78944#L1534-1 assume !(1 == ~E_6~0); 77114#L1539-1 assume !(1 == ~E_7~0); 77115#L1544-1 assume !(1 == ~E_8~0); 77529#L1549-1 assume !(1 == ~E_9~0); 78918#L1554-1 assume !(1 == ~E_10~0); 78914#L1559-1 assume !(1 == ~E_11~0); 78781#L1564-1 assume !(1 == ~E_12~0); 78782#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 78939#L1574-1 assume { :end_inline_reset_delta_events } true; 77291#L1940-2 [2022-02-21 04:23:33,828 INFO L793 eck$LassoCheckResult]: Loop: 77291#L1940-2 assume !false; 77292#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77574#L1266 assume !false; 78593#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77822#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77555#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77946#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77947#L1079 assume !(0 != eval_~tmp~0#1); 77908#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77909#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78513#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 78398#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78399#L1296-3 assume !(0 == ~T2_E~0); 78971#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78925#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78056#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77332#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 77333#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 77433#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 78190#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78439#L1336-3 assume !(0 == ~T10_E~0); 78440#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 77760#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 77740#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 77685#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 77686#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 78247#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 77036#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 77037#L1376-3 assume !(0 == ~E_4~0); 78766#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78626#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 78627#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 78789#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 78790#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 77399#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77253#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77254#L1416-3 assume !(0 == ~E_12~0); 77915#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 77916#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78023#L640-45 assume 1 == ~m_pc~0; 78025#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 77490#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77491#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77030#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77031#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77129#L659-45 assume !(1 == ~t1_pc~0); 77131#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 77569#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78528#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78529#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78550#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78551#L678-45 assume !(1 == ~t2_pc~0); 78495#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 78029#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78030#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78182#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78807#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78924#L697-45 assume !(1 == ~t3_pc~0); 78289#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 78288#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78876#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78446#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78447#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78477#L716-45 assume 1 == ~t4_pc~0; 78108#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78109#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78659#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78114#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78115#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77777#L735-45 assume !(1 == ~t5_pc~0); 77779#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 78321#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78883#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78884#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78942#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78937#L754-45 assume 1 == ~t6_pc~0; 78269#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 78270#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77699#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77700#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78273#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78005#L773-45 assume 1 == ~t7_pc~0; 78006#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77563#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78483#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78765#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 78011#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77681#L792-45 assume !(1 == ~t8_pc~0); 77683#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 78711#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77284#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77143#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77144#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77639#L811-45 assume !(1 == ~t9_pc~0); 77429#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 77430#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78638#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78473#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78082#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77874#L830-45 assume 1 == ~t10_pc~0; 77875#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 77072#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78194#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 77304#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77305#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77050#L849-45 assume !(1 == ~t11_pc~0); 77051#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 77510#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77141#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77038#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 77039#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77297#L868-45 assume !(1 == ~t12_pc~0); 77299#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 77237#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77238#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 78576#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 78827#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78828#L887-45 assume 1 == ~t13_pc~0; 78658#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 77307#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78589#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 78934#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 77269#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77270#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 78577#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77289#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77290#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77447#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78378#L1459-3 assume !(1 == ~T5_E~0); 78379#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78830#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78769#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78770#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78831#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78063#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78064#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78700#L1499-3 assume !(1 == ~T13_E~0); 78339#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78340#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78778#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78808#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77982#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77983#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78850#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78250#L1539-3 assume !(1 == ~E_7~0); 77726#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77727#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78222#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 77343#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 77344#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78478#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 78479#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77220#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76991#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77266#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77227#L1959 assume !(0 == start_simulation_~tmp~3#1); 77229#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77261#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77211#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 78520#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 78641#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78848#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78862#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 78863#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 77291#L1940-2 [2022-02-21 04:23:33,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:33,829 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2022-02-21 04:23:33,829 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:33,829 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972527047] [2022-02-21 04:23:33,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:33,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:33,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:33,860 INFO L290 TraceCheckUtils]: 0: Hoare triple {83050#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {83050#true} is VALID [2022-02-21 04:23:33,861 INFO L290 TraceCheckUtils]: 1: Hoare triple {83050#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,861 INFO L290 TraceCheckUtils]: 2: Hoare triple {83052#(= ~t11_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,861 INFO L290 TraceCheckUtils]: 3: Hoare triple {83052#(= ~t11_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,862 INFO L290 TraceCheckUtils]: 4: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,862 INFO L290 TraceCheckUtils]: 5: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,862 INFO L290 TraceCheckUtils]: 6: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,863 INFO L290 TraceCheckUtils]: 7: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,863 INFO L290 TraceCheckUtils]: 8: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,863 INFO L290 TraceCheckUtils]: 9: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,864 INFO L290 TraceCheckUtils]: 10: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,864 INFO L290 TraceCheckUtils]: 11: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,864 INFO L290 TraceCheckUtils]: 12: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,865 INFO L290 TraceCheckUtils]: 13: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,865 INFO L290 TraceCheckUtils]: 14: Hoare triple {83052#(= ~t11_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {83052#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:33,865 INFO L290 TraceCheckUtils]: 15: Hoare triple {83052#(= ~t11_i~0 1)} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {83051#false} is VALID [2022-02-21 04:23:33,865 INFO L290 TraceCheckUtils]: 16: Hoare triple {83051#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {83051#false} is VALID [2022-02-21 04:23:33,865 INFO L290 TraceCheckUtils]: 17: Hoare triple {83051#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 18: Hoare triple {83051#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 19: Hoare triple {83051#false} assume 0 == ~M_E~0;~M_E~0 := 1; {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 20: Hoare triple {83051#false} assume !(0 == ~T1_E~0); {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 21: Hoare triple {83051#false} assume !(0 == ~T2_E~0); {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 22: Hoare triple {83051#false} assume !(0 == ~T3_E~0); {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 23: Hoare triple {83051#false} assume !(0 == ~T4_E~0); {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 24: Hoare triple {83051#false} assume !(0 == ~T5_E~0); {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 25: Hoare triple {83051#false} assume !(0 == ~T6_E~0); {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 26: Hoare triple {83051#false} assume !(0 == ~T7_E~0); {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 27: Hoare triple {83051#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {83051#false} is VALID [2022-02-21 04:23:33,866 INFO L290 TraceCheckUtils]: 28: Hoare triple {83051#false} assume !(0 == ~T9_E~0); {83051#false} is VALID [2022-02-21 04:23:33,867 INFO L290 TraceCheckUtils]: 29: Hoare triple {83051#false} assume !(0 == ~T10_E~0); {83051#false} is VALID [2022-02-21 04:23:33,867 INFO L290 TraceCheckUtils]: 30: Hoare triple {83051#false} assume !(0 == ~T11_E~0); {83051#false} is VALID [2022-02-21 04:23:33,874 INFO L290 TraceCheckUtils]: 31: Hoare triple {83051#false} assume !(0 == ~T12_E~0); {83051#false} is VALID [2022-02-21 04:23:33,874 INFO L290 TraceCheckUtils]: 32: Hoare triple {83051#false} assume !(0 == ~T13_E~0); {83051#false} is VALID [2022-02-21 04:23:33,874 INFO L290 TraceCheckUtils]: 33: Hoare triple {83051#false} assume !(0 == ~E_M~0); {83051#false} is VALID [2022-02-21 04:23:33,875 INFO L290 TraceCheckUtils]: 34: Hoare triple {83051#false} assume !(0 == ~E_1~0); {83051#false} is VALID [2022-02-21 04:23:33,875 INFO L290 TraceCheckUtils]: 35: Hoare triple {83051#false} assume 0 == ~E_2~0;~E_2~0 := 1; {83051#false} is VALID [2022-02-21 04:23:33,875 INFO L290 TraceCheckUtils]: 36: Hoare triple {83051#false} assume !(0 == ~E_3~0); {83051#false} is VALID [2022-02-21 04:23:33,875 INFO L290 TraceCheckUtils]: 37: Hoare triple {83051#false} assume !(0 == ~E_4~0); {83051#false} is VALID [2022-02-21 04:23:33,875 INFO L290 TraceCheckUtils]: 38: Hoare triple {83051#false} assume !(0 == ~E_5~0); {83051#false} is VALID [2022-02-21 04:23:33,875 INFO L290 TraceCheckUtils]: 39: Hoare triple {83051#false} assume !(0 == ~E_6~0); {83051#false} is VALID [2022-02-21 04:23:33,875 INFO L290 TraceCheckUtils]: 40: Hoare triple {83051#false} assume !(0 == ~E_7~0); {83051#false} is VALID [2022-02-21 04:23:33,875 INFO L290 TraceCheckUtils]: 41: Hoare triple {83051#false} assume !(0 == ~E_8~0); {83051#false} is VALID [2022-02-21 04:23:33,875 INFO L290 TraceCheckUtils]: 42: Hoare triple {83051#false} assume !(0 == ~E_9~0); {83051#false} is VALID [2022-02-21 04:23:33,875 INFO L290 TraceCheckUtils]: 43: Hoare triple {83051#false} assume 0 == ~E_10~0;~E_10~0 := 1; {83051#false} is VALID [2022-02-21 04:23:33,876 INFO L290 TraceCheckUtils]: 44: Hoare triple {83051#false} assume !(0 == ~E_11~0); {83051#false} is VALID [2022-02-21 04:23:33,876 INFO L290 TraceCheckUtils]: 45: Hoare triple {83051#false} assume !(0 == ~E_12~0); {83051#false} is VALID [2022-02-21 04:23:33,876 INFO L290 TraceCheckUtils]: 46: Hoare triple {83051#false} assume !(0 == ~E_13~0); {83051#false} is VALID [2022-02-21 04:23:33,876 INFO L290 TraceCheckUtils]: 47: Hoare triple {83051#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {83051#false} is VALID [2022-02-21 04:23:33,876 INFO L290 TraceCheckUtils]: 48: Hoare triple {83051#false} assume !(1 == ~m_pc~0); {83051#false} is VALID [2022-02-21 04:23:33,876 INFO L290 TraceCheckUtils]: 49: Hoare triple {83051#false} is_master_triggered_~__retres1~0#1 := 0; {83051#false} is VALID [2022-02-21 04:23:33,876 INFO L290 TraceCheckUtils]: 50: Hoare triple {83051#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {83051#false} is VALID [2022-02-21 04:23:33,876 INFO L290 TraceCheckUtils]: 51: Hoare triple {83051#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {83051#false} is VALID [2022-02-21 04:23:33,876 INFO L290 TraceCheckUtils]: 52: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp~1#1); {83051#false} is VALID [2022-02-21 04:23:33,876 INFO L290 TraceCheckUtils]: 53: Hoare triple {83051#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 54: Hoare triple {83051#false} assume 1 == ~t1_pc~0; {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 55: Hoare triple {83051#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 56: Hoare triple {83051#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 57: Hoare triple {83051#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 58: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___0~0#1); {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 59: Hoare triple {83051#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 60: Hoare triple {83051#false} assume 1 == ~t2_pc~0; {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 61: Hoare triple {83051#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 62: Hoare triple {83051#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 63: Hoare triple {83051#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {83051#false} is VALID [2022-02-21 04:23:33,877 INFO L290 TraceCheckUtils]: 64: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___1~0#1); {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 65: Hoare triple {83051#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 66: Hoare triple {83051#false} assume !(1 == ~t3_pc~0); {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 67: Hoare triple {83051#false} is_transmit3_triggered_~__retres1~3#1 := 0; {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 68: Hoare triple {83051#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 69: Hoare triple {83051#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 70: Hoare triple {83051#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 71: Hoare triple {83051#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 72: Hoare triple {83051#false} assume 1 == ~t4_pc~0; {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 73: Hoare triple {83051#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 74: Hoare triple {83051#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {83051#false} is VALID [2022-02-21 04:23:33,878 INFO L290 TraceCheckUtils]: 75: Hoare triple {83051#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {83051#false} is VALID [2022-02-21 04:23:33,879 INFO L290 TraceCheckUtils]: 76: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___3~0#1); {83051#false} is VALID [2022-02-21 04:23:33,879 INFO L290 TraceCheckUtils]: 77: Hoare triple {83051#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {83051#false} is VALID [2022-02-21 04:23:33,879 INFO L290 TraceCheckUtils]: 78: Hoare triple {83051#false} assume !(1 == ~t5_pc~0); {83051#false} is VALID [2022-02-21 04:23:33,879 INFO L290 TraceCheckUtils]: 79: Hoare triple {83051#false} is_transmit5_triggered_~__retres1~5#1 := 0; {83051#false} is VALID [2022-02-21 04:23:33,879 INFO L290 TraceCheckUtils]: 80: Hoare triple {83051#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {83051#false} is VALID [2022-02-21 04:23:33,879 INFO L290 TraceCheckUtils]: 81: Hoare triple {83051#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {83051#false} is VALID [2022-02-21 04:23:33,879 INFO L290 TraceCheckUtils]: 82: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___4~0#1); {83051#false} is VALID [2022-02-21 04:23:33,879 INFO L290 TraceCheckUtils]: 83: Hoare triple {83051#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {83051#false} is VALID [2022-02-21 04:23:33,879 INFO L290 TraceCheckUtils]: 84: Hoare triple {83051#false} assume 1 == ~t6_pc~0; {83051#false} is VALID [2022-02-21 04:23:33,879 INFO L290 TraceCheckUtils]: 85: Hoare triple {83051#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 86: Hoare triple {83051#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 87: Hoare triple {83051#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 88: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___5~0#1); {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 89: Hoare triple {83051#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 90: Hoare triple {83051#false} assume !(1 == ~t7_pc~0); {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 91: Hoare triple {83051#false} is_transmit7_triggered_~__retres1~7#1 := 0; {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 92: Hoare triple {83051#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 93: Hoare triple {83051#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 94: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___6~0#1); {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 95: Hoare triple {83051#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {83051#false} is VALID [2022-02-21 04:23:33,880 INFO L290 TraceCheckUtils]: 96: Hoare triple {83051#false} assume 1 == ~t8_pc~0; {83051#false} is VALID [2022-02-21 04:23:33,881 INFO L290 TraceCheckUtils]: 97: Hoare triple {83051#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {83051#false} is VALID [2022-02-21 04:23:33,881 INFO L290 TraceCheckUtils]: 98: Hoare triple {83051#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {83051#false} is VALID [2022-02-21 04:23:33,881 INFO L290 TraceCheckUtils]: 99: Hoare triple {83051#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {83051#false} is VALID [2022-02-21 04:23:33,881 INFO L290 TraceCheckUtils]: 100: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___7~0#1); {83051#false} is VALID [2022-02-21 04:23:33,881 INFO L290 TraceCheckUtils]: 101: Hoare triple {83051#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {83051#false} is VALID [2022-02-21 04:23:33,881 INFO L290 TraceCheckUtils]: 102: Hoare triple {83051#false} assume 1 == ~t9_pc~0; {83051#false} is VALID [2022-02-21 04:23:33,881 INFO L290 TraceCheckUtils]: 103: Hoare triple {83051#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {83051#false} is VALID [2022-02-21 04:23:33,881 INFO L290 TraceCheckUtils]: 104: Hoare triple {83051#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {83051#false} is VALID [2022-02-21 04:23:33,881 INFO L290 TraceCheckUtils]: 105: Hoare triple {83051#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {83051#false} is VALID [2022-02-21 04:23:33,881 INFO L290 TraceCheckUtils]: 106: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___8~0#1); {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 107: Hoare triple {83051#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 108: Hoare triple {83051#false} assume !(1 == ~t10_pc~0); {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 109: Hoare triple {83051#false} is_transmit10_triggered_~__retres1~10#1 := 0; {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 110: Hoare triple {83051#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 111: Hoare triple {83051#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 112: Hoare triple {83051#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 113: Hoare triple {83051#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 114: Hoare triple {83051#false} assume 1 == ~t11_pc~0; {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 115: Hoare triple {83051#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 116: Hoare triple {83051#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {83051#false} is VALID [2022-02-21 04:23:33,882 INFO L290 TraceCheckUtils]: 117: Hoare triple {83051#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 118: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___10~0#1); {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 119: Hoare triple {83051#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 120: Hoare triple {83051#false} assume !(1 == ~t12_pc~0); {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 121: Hoare triple {83051#false} is_transmit12_triggered_~__retres1~12#1 := 0; {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 122: Hoare triple {83051#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 123: Hoare triple {83051#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 124: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___11~0#1); {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 125: Hoare triple {83051#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 126: Hoare triple {83051#false} assume 1 == ~t13_pc~0; {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 127: Hoare triple {83051#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {83051#false} is VALID [2022-02-21 04:23:33,883 INFO L290 TraceCheckUtils]: 128: Hoare triple {83051#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {83051#false} is VALID [2022-02-21 04:23:33,884 INFO L290 TraceCheckUtils]: 129: Hoare triple {83051#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {83051#false} is VALID [2022-02-21 04:23:33,884 INFO L290 TraceCheckUtils]: 130: Hoare triple {83051#false} assume !(0 != activate_threads_~tmp___12~0#1); {83051#false} is VALID [2022-02-21 04:23:33,884 INFO L290 TraceCheckUtils]: 131: Hoare triple {83051#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {83051#false} is VALID [2022-02-21 04:23:33,884 INFO L290 TraceCheckUtils]: 132: Hoare triple {83051#false} assume !(1 == ~M_E~0); {83051#false} is VALID [2022-02-21 04:23:33,884 INFO L290 TraceCheckUtils]: 133: Hoare triple {83051#false} assume !(1 == ~T1_E~0); {83051#false} is VALID [2022-02-21 04:23:33,884 INFO L290 TraceCheckUtils]: 134: Hoare triple {83051#false} assume !(1 == ~T2_E~0); {83051#false} is VALID [2022-02-21 04:23:33,884 INFO L290 TraceCheckUtils]: 135: Hoare triple {83051#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {83051#false} is VALID [2022-02-21 04:23:33,884 INFO L290 TraceCheckUtils]: 136: Hoare triple {83051#false} assume !(1 == ~T4_E~0); {83051#false} is VALID [2022-02-21 04:23:33,884 INFO L290 TraceCheckUtils]: 137: Hoare triple {83051#false} assume !(1 == ~T5_E~0); {83051#false} is VALID [2022-02-21 04:23:33,884 INFO L290 TraceCheckUtils]: 138: Hoare triple {83051#false} assume !(1 == ~T6_E~0); {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 139: Hoare triple {83051#false} assume !(1 == ~T7_E~0); {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 140: Hoare triple {83051#false} assume !(1 == ~T8_E~0); {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 141: Hoare triple {83051#false} assume !(1 == ~T9_E~0); {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 142: Hoare triple {83051#false} assume !(1 == ~T10_E~0); {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 143: Hoare triple {83051#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 144: Hoare triple {83051#false} assume !(1 == ~T12_E~0); {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 145: Hoare triple {83051#false} assume !(1 == ~T13_E~0); {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 146: Hoare triple {83051#false} assume !(1 == ~E_M~0); {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 147: Hoare triple {83051#false} assume !(1 == ~E_1~0); {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 148: Hoare triple {83051#false} assume !(1 == ~E_2~0); {83051#false} is VALID [2022-02-21 04:23:33,885 INFO L290 TraceCheckUtils]: 149: Hoare triple {83051#false} assume !(1 == ~E_3~0); {83051#false} is VALID [2022-02-21 04:23:33,886 INFO L290 TraceCheckUtils]: 150: Hoare triple {83051#false} assume !(1 == ~E_4~0); {83051#false} is VALID [2022-02-21 04:23:33,886 INFO L290 TraceCheckUtils]: 151: Hoare triple {83051#false} assume 1 == ~E_5~0;~E_5~0 := 2; {83051#false} is VALID [2022-02-21 04:23:33,886 INFO L290 TraceCheckUtils]: 152: Hoare triple {83051#false} assume !(1 == ~E_6~0); {83051#false} is VALID [2022-02-21 04:23:33,886 INFO L290 TraceCheckUtils]: 153: Hoare triple {83051#false} assume !(1 == ~E_7~0); {83051#false} is VALID [2022-02-21 04:23:33,886 INFO L290 TraceCheckUtils]: 154: Hoare triple {83051#false} assume !(1 == ~E_8~0); {83051#false} is VALID [2022-02-21 04:23:33,886 INFO L290 TraceCheckUtils]: 155: Hoare triple {83051#false} assume !(1 == ~E_9~0); {83051#false} is VALID [2022-02-21 04:23:33,886 INFO L290 TraceCheckUtils]: 156: Hoare triple {83051#false} assume !(1 == ~E_10~0); {83051#false} is VALID [2022-02-21 04:23:33,886 INFO L290 TraceCheckUtils]: 157: Hoare triple {83051#false} assume !(1 == ~E_11~0); {83051#false} is VALID [2022-02-21 04:23:33,886 INFO L290 TraceCheckUtils]: 158: Hoare triple {83051#false} assume !(1 == ~E_12~0); {83051#false} is VALID [2022-02-21 04:23:33,886 INFO L290 TraceCheckUtils]: 159: Hoare triple {83051#false} assume 1 == ~E_13~0;~E_13~0 := 2; {83051#false} is VALID [2022-02-21 04:23:33,887 INFO L290 TraceCheckUtils]: 160: Hoare triple {83051#false} assume { :end_inline_reset_delta_events } true; {83051#false} is VALID [2022-02-21 04:23:33,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:33,887 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:33,887 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [972527047] [2022-02-21 04:23:33,887 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [972527047] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:33,887 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:33,887 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:33,888 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170096928] [2022-02-21 04:23:33,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:33,888 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:33,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:33,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1690031842, now seen corresponding path program 1 times [2022-02-21 04:23:33,889 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:33,889 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987456270] [2022-02-21 04:23:33,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:33,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:33,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:33,931 INFO L290 TraceCheckUtils]: 0: Hoare triple {83053#true} assume !false; {83053#true} is VALID [2022-02-21 04:23:33,932 INFO L290 TraceCheckUtils]: 1: Hoare triple {83053#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {83053#true} is VALID [2022-02-21 04:23:33,932 INFO L290 TraceCheckUtils]: 2: Hoare triple {83053#true} assume !false; {83053#true} is VALID [2022-02-21 04:23:33,932 INFO L290 TraceCheckUtils]: 3: Hoare triple {83053#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {83053#true} is VALID [2022-02-21 04:23:33,932 INFO L290 TraceCheckUtils]: 4: Hoare triple {83053#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {83053#true} is VALID [2022-02-21 04:23:33,932 INFO L290 TraceCheckUtils]: 5: Hoare triple {83053#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {83053#true} is VALID [2022-02-21 04:23:33,932 INFO L290 TraceCheckUtils]: 6: Hoare triple {83053#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {83053#true} is VALID [2022-02-21 04:23:33,932 INFO L290 TraceCheckUtils]: 7: Hoare triple {83053#true} assume !(0 != eval_~tmp~0#1); {83053#true} is VALID [2022-02-21 04:23:33,932 INFO L290 TraceCheckUtils]: 8: Hoare triple {83053#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {83053#true} is VALID [2022-02-21 04:23:33,932 INFO L290 TraceCheckUtils]: 9: Hoare triple {83053#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {83053#true} is VALID [2022-02-21 04:23:33,932 INFO L290 TraceCheckUtils]: 10: Hoare triple {83053#true} assume 0 == ~M_E~0;~M_E~0 := 1; {83053#true} is VALID [2022-02-21 04:23:33,933 INFO L290 TraceCheckUtils]: 11: Hoare triple {83053#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {83053#true} is VALID [2022-02-21 04:23:33,933 INFO L290 TraceCheckUtils]: 12: Hoare triple {83053#true} assume !(0 == ~T2_E~0); {83053#true} is VALID [2022-02-21 04:23:33,933 INFO L290 TraceCheckUtils]: 13: Hoare triple {83053#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {83053#true} is VALID [2022-02-21 04:23:33,933 INFO L290 TraceCheckUtils]: 14: Hoare triple {83053#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {83053#true} is VALID [2022-02-21 04:23:33,933 INFO L290 TraceCheckUtils]: 15: Hoare triple {83053#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,934 INFO L290 TraceCheckUtils]: 16: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,934 INFO L290 TraceCheckUtils]: 17: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,934 INFO L290 TraceCheckUtils]: 18: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,935 INFO L290 TraceCheckUtils]: 19: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,935 INFO L290 TraceCheckUtils]: 20: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,935 INFO L290 TraceCheckUtils]: 21: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,936 INFO L290 TraceCheckUtils]: 22: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,936 INFO L290 TraceCheckUtils]: 23: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,936 INFO L290 TraceCheckUtils]: 24: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,937 INFO L290 TraceCheckUtils]: 25: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,937 INFO L290 TraceCheckUtils]: 26: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,938 INFO L290 TraceCheckUtils]: 27: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,938 INFO L290 TraceCheckUtils]: 28: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,938 INFO L290 TraceCheckUtils]: 29: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,939 INFO L290 TraceCheckUtils]: 30: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,939 INFO L290 TraceCheckUtils]: 31: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,939 INFO L290 TraceCheckUtils]: 32: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,940 INFO L290 TraceCheckUtils]: 33: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,940 INFO L290 TraceCheckUtils]: 34: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,940 INFO L290 TraceCheckUtils]: 35: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,941 INFO L290 TraceCheckUtils]: 36: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,941 INFO L290 TraceCheckUtils]: 37: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,942 INFO L290 TraceCheckUtils]: 38: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,942 INFO L290 TraceCheckUtils]: 39: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,942 INFO L290 TraceCheckUtils]: 40: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,943 INFO L290 TraceCheckUtils]: 41: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,943 INFO L290 TraceCheckUtils]: 42: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,943 INFO L290 TraceCheckUtils]: 43: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,944 INFO L290 TraceCheckUtils]: 44: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,944 INFO L290 TraceCheckUtils]: 45: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,944 INFO L290 TraceCheckUtils]: 46: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,945 INFO L290 TraceCheckUtils]: 47: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,945 INFO L290 TraceCheckUtils]: 48: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,946 INFO L290 TraceCheckUtils]: 49: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,946 INFO L290 TraceCheckUtils]: 50: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,946 INFO L290 TraceCheckUtils]: 51: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,947 INFO L290 TraceCheckUtils]: 52: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,947 INFO L290 TraceCheckUtils]: 53: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,947 INFO L290 TraceCheckUtils]: 54: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,948 INFO L290 TraceCheckUtils]: 55: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,948 INFO L290 TraceCheckUtils]: 56: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,948 INFO L290 TraceCheckUtils]: 57: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,949 INFO L290 TraceCheckUtils]: 58: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,949 INFO L290 TraceCheckUtils]: 59: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,950 INFO L290 TraceCheckUtils]: 60: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,950 INFO L290 TraceCheckUtils]: 61: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,950 INFO L290 TraceCheckUtils]: 62: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,951 INFO L290 TraceCheckUtils]: 63: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,951 INFO L290 TraceCheckUtils]: 64: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,951 INFO L290 TraceCheckUtils]: 65: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,952 INFO L290 TraceCheckUtils]: 66: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,952 INFO L290 TraceCheckUtils]: 67: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,952 INFO L290 TraceCheckUtils]: 68: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,953 INFO L290 TraceCheckUtils]: 69: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,953 INFO L290 TraceCheckUtils]: 70: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,953 INFO L290 TraceCheckUtils]: 71: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,954 INFO L290 TraceCheckUtils]: 72: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,954 INFO L290 TraceCheckUtils]: 73: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,955 INFO L290 TraceCheckUtils]: 74: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,955 INFO L290 TraceCheckUtils]: 75: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,955 INFO L290 TraceCheckUtils]: 76: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,956 INFO L290 TraceCheckUtils]: 77: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,956 INFO L290 TraceCheckUtils]: 78: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,956 INFO L290 TraceCheckUtils]: 79: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,957 INFO L290 TraceCheckUtils]: 80: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,957 INFO L290 TraceCheckUtils]: 81: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,957 INFO L290 TraceCheckUtils]: 82: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,958 INFO L290 TraceCheckUtils]: 83: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,958 INFO L290 TraceCheckUtils]: 84: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,959 INFO L290 TraceCheckUtils]: 85: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,959 INFO L290 TraceCheckUtils]: 86: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,959 INFO L290 TraceCheckUtils]: 87: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,960 INFO L290 TraceCheckUtils]: 88: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,960 INFO L290 TraceCheckUtils]: 89: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,960 INFO L290 TraceCheckUtils]: 90: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,961 INFO L290 TraceCheckUtils]: 91: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,961 INFO L290 TraceCheckUtils]: 92: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,961 INFO L290 TraceCheckUtils]: 93: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,962 INFO L290 TraceCheckUtils]: 94: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,962 INFO L290 TraceCheckUtils]: 95: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,963 INFO L290 TraceCheckUtils]: 96: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,963 INFO L290 TraceCheckUtils]: 97: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,963 INFO L290 TraceCheckUtils]: 98: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,964 INFO L290 TraceCheckUtils]: 99: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,964 INFO L290 TraceCheckUtils]: 100: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,964 INFO L290 TraceCheckUtils]: 101: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,965 INFO L290 TraceCheckUtils]: 102: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,965 INFO L290 TraceCheckUtils]: 103: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,965 INFO L290 TraceCheckUtils]: 104: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,966 INFO L290 TraceCheckUtils]: 105: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,966 INFO L290 TraceCheckUtils]: 106: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,967 INFO L290 TraceCheckUtils]: 107: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,967 INFO L290 TraceCheckUtils]: 108: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,967 INFO L290 TraceCheckUtils]: 109: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,968 INFO L290 TraceCheckUtils]: 110: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,968 INFO L290 TraceCheckUtils]: 111: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t12_pc~0); {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,968 INFO L290 TraceCheckUtils]: 112: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,969 INFO L290 TraceCheckUtils]: 113: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,969 INFO L290 TraceCheckUtils]: 114: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,969 INFO L290 TraceCheckUtils]: 115: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,970 INFO L290 TraceCheckUtils]: 116: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,970 INFO L290 TraceCheckUtils]: 117: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,970 INFO L290 TraceCheckUtils]: 118: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,971 INFO L290 TraceCheckUtils]: 119: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,971 INFO L290 TraceCheckUtils]: 120: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,972 INFO L290 TraceCheckUtils]: 121: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,972 INFO L290 TraceCheckUtils]: 122: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,972 INFO L290 TraceCheckUtils]: 123: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,973 INFO L290 TraceCheckUtils]: 124: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,973 INFO L290 TraceCheckUtils]: 125: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,973 INFO L290 TraceCheckUtils]: 126: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,974 INFO L290 TraceCheckUtils]: 127: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {83055#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:33,974 INFO L290 TraceCheckUtils]: 128: Hoare triple {83055#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {83054#false} is VALID [2022-02-21 04:23:33,974 INFO L290 TraceCheckUtils]: 129: Hoare triple {83054#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,974 INFO L290 TraceCheckUtils]: 130: Hoare triple {83054#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,974 INFO L290 TraceCheckUtils]: 131: Hoare triple {83054#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,974 INFO L290 TraceCheckUtils]: 132: Hoare triple {83054#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 133: Hoare triple {83054#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 134: Hoare triple {83054#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 135: Hoare triple {83054#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 136: Hoare triple {83054#false} assume !(1 == ~T13_E~0); {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 137: Hoare triple {83054#false} assume 1 == ~E_M~0;~E_M~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 138: Hoare triple {83054#false} assume 1 == ~E_1~0;~E_1~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 139: Hoare triple {83054#false} assume 1 == ~E_2~0;~E_2~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 140: Hoare triple {83054#false} assume 1 == ~E_3~0;~E_3~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 141: Hoare triple {83054#false} assume 1 == ~E_4~0;~E_4~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 142: Hoare triple {83054#false} assume 1 == ~E_5~0;~E_5~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,975 INFO L290 TraceCheckUtils]: 143: Hoare triple {83054#false} assume 1 == ~E_6~0;~E_6~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,976 INFO L290 TraceCheckUtils]: 144: Hoare triple {83054#false} assume !(1 == ~E_7~0); {83054#false} is VALID [2022-02-21 04:23:33,976 INFO L290 TraceCheckUtils]: 145: Hoare triple {83054#false} assume 1 == ~E_8~0;~E_8~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,976 INFO L290 TraceCheckUtils]: 146: Hoare triple {83054#false} assume 1 == ~E_9~0;~E_9~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,976 INFO L290 TraceCheckUtils]: 147: Hoare triple {83054#false} assume 1 == ~E_10~0;~E_10~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,976 INFO L290 TraceCheckUtils]: 148: Hoare triple {83054#false} assume 1 == ~E_11~0;~E_11~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,976 INFO L290 TraceCheckUtils]: 149: Hoare triple {83054#false} assume 1 == ~E_12~0;~E_12~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,976 INFO L290 TraceCheckUtils]: 150: Hoare triple {83054#false} assume 1 == ~E_13~0;~E_13~0 := 2; {83054#false} is VALID [2022-02-21 04:23:33,976 INFO L290 TraceCheckUtils]: 151: Hoare triple {83054#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {83054#false} is VALID [2022-02-21 04:23:33,976 INFO L290 TraceCheckUtils]: 152: Hoare triple {83054#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {83054#false} is VALID [2022-02-21 04:23:33,976 INFO L290 TraceCheckUtils]: 153: Hoare triple {83054#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {83054#false} is VALID [2022-02-21 04:23:33,977 INFO L290 TraceCheckUtils]: 154: Hoare triple {83054#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {83054#false} is VALID [2022-02-21 04:23:33,977 INFO L290 TraceCheckUtils]: 155: Hoare triple {83054#false} assume !(0 == start_simulation_~tmp~3#1); {83054#false} is VALID [2022-02-21 04:23:33,977 INFO L290 TraceCheckUtils]: 156: Hoare triple {83054#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {83054#false} is VALID [2022-02-21 04:23:33,977 INFO L290 TraceCheckUtils]: 157: Hoare triple {83054#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {83054#false} is VALID [2022-02-21 04:23:33,977 INFO L290 TraceCheckUtils]: 158: Hoare triple {83054#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {83054#false} is VALID [2022-02-21 04:23:33,977 INFO L290 TraceCheckUtils]: 159: Hoare triple {83054#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {83054#false} is VALID [2022-02-21 04:23:33,977 INFO L290 TraceCheckUtils]: 160: Hoare triple {83054#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {83054#false} is VALID [2022-02-21 04:23:33,977 INFO L290 TraceCheckUtils]: 161: Hoare triple {83054#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {83054#false} is VALID [2022-02-21 04:23:33,977 INFO L290 TraceCheckUtils]: 162: Hoare triple {83054#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {83054#false} is VALID [2022-02-21 04:23:33,977 INFO L290 TraceCheckUtils]: 163: Hoare triple {83054#false} assume !(0 != start_simulation_~tmp___0~1#1); {83054#false} is VALID [2022-02-21 04:23:33,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:33,978 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:33,978 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987456270] [2022-02-21 04:23:33,978 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987456270] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:33,978 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:33,978 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:33,979 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [274598476] [2022-02-21 04:23:33,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:33,979 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:33,979 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:33,979 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:33,979 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:33,980 INFO L87 Difference]: Start difference. First operand 2023 states and 2987 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:35,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:35,411 INFO L93 Difference]: Finished difference Result 2023 states and 2986 transitions. [2022-02-21 04:23:35,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:35,412 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:35,524 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:35,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2986 transitions. [2022-02-21 04:23:35,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:35,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2986 transitions. [2022-02-21 04:23:35,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:35,701 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:35,701 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2986 transitions. [2022-02-21 04:23:35,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:35,702 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2022-02-21 04:23:35,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2986 transitions. [2022-02-21 04:23:35,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:35,717 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:35,718 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2986 transitions. Second operand has 2023 states, 2023 states have (on average 1.4760257043994067) internal successors, (2986), 2022 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:35,720 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2986 transitions. Second operand has 2023 states, 2023 states have (on average 1.4760257043994067) internal successors, (2986), 2022 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:35,721 INFO L87 Difference]: Start difference. First operand 2023 states and 2986 transitions. Second operand has 2023 states, 2023 states have (on average 1.4760257043994067) internal successors, (2986), 2022 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:35,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:35,829 INFO L93 Difference]: Finished difference Result 2023 states and 2986 transitions. [2022-02-21 04:23:35,829 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2986 transitions. [2022-02-21 04:23:35,831 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:35,831 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:35,833 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4760257043994067) internal successors, (2986), 2022 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2986 transitions. [2022-02-21 04:23:35,834 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4760257043994067) internal successors, (2986), 2022 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2986 transitions. [2022-02-21 04:23:35,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:35,915 INFO L93 Difference]: Finished difference Result 2023 states and 2986 transitions. [2022-02-21 04:23:35,916 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2986 transitions. [2022-02-21 04:23:35,917 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:35,917 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:35,917 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:35,917 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:35,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4760257043994067) internal successors, (2986), 2022 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2986 transitions. [2022-02-21 04:23:36,000 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2022-02-21 04:23:36,000 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2022-02-21 04:23:36,000 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:23:36,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2986 transitions. [2022-02-21 04:23:36,003 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:36,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:36,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:36,005 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:36,005 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:36,005 INFO L791 eck$LassoCheckResult]: Stem: 86006#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 86007#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 87005#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87006#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87091#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 86470#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85939#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85940#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86756#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86757#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86857#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86858#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85711#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85712#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 86887#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86247#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 86248#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 86808#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 86149#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86150#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 87092#L1291-2 assume !(0 == ~T1_E~0); 87090#L1296-1 assume !(0 == ~T2_E~0); 86306#L1301-1 assume !(0 == ~T3_E~0); 86307#L1306-1 assume !(0 == ~T4_E~0); 86816#L1311-1 assume !(0 == ~T5_E~0); 85554#L1316-1 assume !(0 == ~T6_E~0); 85555#L1321-1 assume !(0 == ~T7_E~0); 86319#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 85382#L1331-1 assume !(0 == ~T9_E~0); 85081#L1336-1 assume !(0 == ~T10_E~0); 85082#L1341-1 assume !(0 == ~T11_E~0); 85162#L1346-1 assume !(0 == ~T12_E~0); 85163#L1351-1 assume !(0 == ~T13_E~0); 85503#L1356-1 assume !(0 == ~E_M~0); 85504#L1361-1 assume !(0 == ~E_1~0); 87031#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 85544#L1371-1 assume !(0 == ~E_3~0); 85545#L1376-1 assume !(0 == ~E_4~0); 86366#L1381-1 assume !(0 == ~E_5~0); 86367#L1386-1 assume !(0 == ~E_6~0); 87061#L1391-1 assume !(0 == ~E_7~0); 87079#L1396-1 assume !(0 == ~E_8~0); 86279#L1401-1 assume !(0 == ~E_9~0); 86280#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 86558#L1411-1 assume !(0 == ~E_11~0); 86559#L1416-1 assume !(0 == ~E_12~0); 86191#L1421-1 assume !(0 == ~E_13~0); 85734#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85735#L640 assume !(1 == ~m_pc~0); 86244#L640-2 is_master_triggered_~__retres1~0#1 := 0; 86243#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86335#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86229#L1603 assume !(0 != activate_threads_~tmp~1#1); 86230#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85864#L659 assume 1 == ~t1_pc~0; 85865#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85970#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86916#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85990#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 85991#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86004#L678 assume 1 == ~t2_pc~0; 86958#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86959#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87058#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86102#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 86103#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86224#L697 assume !(1 == ~t3_pc~0); 86225#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86347#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86155#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86134#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86135#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86995#L716 assume 1 == ~t4_pc~0; 86981#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85845#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85846#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85345#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 85346#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86637#L735 assume !(1 == ~t5_pc~0); 85306#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 85307#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85757#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86664#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 86300#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86301#L754 assume 1 == ~t6_pc~0; 86054#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85952#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85953#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85926#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 85927#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86747#L773 assume !(1 == ~t7_pc~0); 85507#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85506#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86336#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86308#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 86309#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86356#L792 assume 1 == ~t8_pc~0; 86529#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86861#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86350#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86303#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 86227#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86228#L811 assume 1 == ~t9_pc~0; 86432#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86898#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86774#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86428#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 86240#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86241#L830 assume !(1 == ~t10_pc~0); 85962#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 85486#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85179#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85180#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85467#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86765#L849 assume 1 == ~t11_pc~0; 86766#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85282#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85283#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85872#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 86671#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86672#L868 assume !(1 == ~t12_pc~0); 86087#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 86086#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85881#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85882#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 85518#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85519#L887 assume 1 == ~t13_pc~0; 86686#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86128#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86129#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86565#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 85222#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85223#L1439 assume !(1 == ~M_E~0); 86296#L1439-2 assume !(1 == ~T1_E~0); 85394#L1444-1 assume !(1 == ~T2_E~0); 85395#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85868#L1454-1 assume !(1 == ~T4_E~0); 85869#L1459-1 assume !(1 == ~T5_E~0); 86425#L1464-1 assume !(1 == ~T6_E~0); 86426#L1469-1 assume !(1 == ~T7_E~0); 86498#L1474-1 assume !(1 == ~T8_E~0); 86192#L1479-1 assume !(1 == ~T9_E~0); 86193#L1484-1 assume !(1 == ~T10_E~0); 86429#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86075#L1494-1 assume !(1 == ~T12_E~0); 86076#L1499-1 assume !(1 == ~T13_E~0); 86268#L1504-1 assume !(1 == ~E_M~0); 86269#L1509-1 assume !(1 == ~E_1~0); 86844#L1514-1 assume !(1 == ~E_2~0); 86531#L1519-1 assume !(1 == ~E_3~0); 86532#L1524-1 assume !(1 == ~E_4~0); 87044#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 87045#L1534-1 assume !(1 == ~E_6~0); 85215#L1539-1 assume !(1 == ~E_7~0); 85216#L1544-1 assume !(1 == ~E_8~0); 85630#L1549-1 assume !(1 == ~E_9~0); 87019#L1554-1 assume !(1 == ~E_10~0); 87015#L1559-1 assume !(1 == ~E_11~0); 86882#L1564-1 assume !(1 == ~E_12~0); 86883#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 87040#L1574-1 assume { :end_inline_reset_delta_events } true; 85392#L1940-2 [2022-02-21 04:23:36,008 INFO L793 eck$LassoCheckResult]: Loop: 85392#L1940-2 assume !false; 85393#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85675#L1266 assume !false; 86694#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85923#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85656#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86047#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 86048#L1079 assume !(0 != eval_~tmp~0#1); 86009#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86010#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86614#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 86499#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 86500#L1296-3 assume !(0 == ~T2_E~0); 87072#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87026#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 86157#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85433#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85434#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85534#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 86291#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86540#L1336-3 assume !(0 == ~T10_E~0); 86541#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85861#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85841#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85786#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85787#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 86348#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 85137#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85138#L1376-3 assume !(0 == ~E_4~0); 86867#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86727#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86728#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 86890#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86891#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 85500#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 85354#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 85355#L1416-3 assume !(0 == ~E_12~0); 86016#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 86017#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86124#L640-45 assume !(1 == ~m_pc~0); 86125#L640-47 is_master_triggered_~__retres1~0#1 := 0; 85591#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85592#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85131#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85132#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85230#L659-45 assume !(1 == ~t1_pc~0); 85232#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 85670#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86629#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86630#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86651#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86652#L678-45 assume 1 == ~t2_pc~0; 86595#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86130#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86131#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86283#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86908#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87025#L697-45 assume 1 == ~t3_pc~0; 86388#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86389#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86977#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86547#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86548#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86578#L716-45 assume 1 == ~t4_pc~0; 86209#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 86210#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86760#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86215#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86216#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85878#L735-45 assume 1 == ~t5_pc~0; 85879#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 86422#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86984#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86985#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87043#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87038#L754-45 assume 1 == ~t6_pc~0; 86370#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86371#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85800#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85801#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86374#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86106#L773-45 assume 1 == ~t7_pc~0; 86107#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85664#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86584#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86866#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 86112#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85782#L792-45 assume 1 == ~t8_pc~0; 85783#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86812#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85385#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85244#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85245#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85740#L811-45 assume 1 == ~t9_pc~0; 85529#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85531#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86739#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86574#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 86183#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85975#L830-45 assume !(1 == ~t10_pc~0); 85172#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 85173#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86295#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85405#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85406#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85151#L849-45 assume 1 == ~t11_pc~0; 85153#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85611#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85242#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85139#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 85140#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85398#L868-45 assume 1 == ~t12_pc~0; 85399#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 85338#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85339#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86677#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 86928#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86929#L887-45 assume 1 == ~t13_pc~0; 86759#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85408#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86690#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 87035#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 85370#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85371#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 86678#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85390#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85391#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85548#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86479#L1459-3 assume !(1 == ~T5_E~0); 86480#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 86931#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86870#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86871#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86932#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86164#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86165#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 86801#L1499-3 assume !(1 == ~T13_E~0); 86440#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 86441#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86879#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86909#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86083#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86084#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86951#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86351#L1539-3 assume !(1 == ~E_7~0); 85827#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85828#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86323#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 85444#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85445#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 86579#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 86580#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85321#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85092#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85367#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 85328#L1959 assume !(0 == start_simulation_~tmp~3#1); 85330#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85362#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85312#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86621#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 86742#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86949#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86963#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 86964#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 85392#L1940-2 [2022-02-21 04:23:36,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:36,009 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2022-02-21 04:23:36,009 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:36,010 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541942838] [2022-02-21 04:23:36,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:36,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:36,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:36,036 INFO L290 TraceCheckUtils]: 0: Hoare triple {91151#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {91151#true} is VALID [2022-02-21 04:23:36,037 INFO L290 TraceCheckUtils]: 1: Hoare triple {91151#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,037 INFO L290 TraceCheckUtils]: 2: Hoare triple {91153#(= ~t12_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,037 INFO L290 TraceCheckUtils]: 3: Hoare triple {91153#(= ~t12_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,038 INFO L290 TraceCheckUtils]: 4: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,038 INFO L290 TraceCheckUtils]: 5: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,038 INFO L290 TraceCheckUtils]: 6: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,039 INFO L290 TraceCheckUtils]: 7: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,039 INFO L290 TraceCheckUtils]: 8: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,039 INFO L290 TraceCheckUtils]: 9: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,040 INFO L290 TraceCheckUtils]: 10: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,040 INFO L290 TraceCheckUtils]: 11: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,040 INFO L290 TraceCheckUtils]: 12: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,041 INFO L290 TraceCheckUtils]: 13: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,041 INFO L290 TraceCheckUtils]: 14: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,041 INFO L290 TraceCheckUtils]: 15: Hoare triple {91153#(= ~t12_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {91153#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:36,042 INFO L290 TraceCheckUtils]: 16: Hoare triple {91153#(= ~t12_i~0 1)} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {91152#false} is VALID [2022-02-21 04:23:36,042 INFO L290 TraceCheckUtils]: 17: Hoare triple {91152#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {91152#false} is VALID [2022-02-21 04:23:36,042 INFO L290 TraceCheckUtils]: 18: Hoare triple {91152#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {91152#false} is VALID [2022-02-21 04:23:36,042 INFO L290 TraceCheckUtils]: 19: Hoare triple {91152#false} assume 0 == ~M_E~0;~M_E~0 := 1; {91152#false} is VALID [2022-02-21 04:23:36,042 INFO L290 TraceCheckUtils]: 20: Hoare triple {91152#false} assume !(0 == ~T1_E~0); {91152#false} is VALID [2022-02-21 04:23:36,042 INFO L290 TraceCheckUtils]: 21: Hoare triple {91152#false} assume !(0 == ~T2_E~0); {91152#false} is VALID [2022-02-21 04:23:36,042 INFO L290 TraceCheckUtils]: 22: Hoare triple {91152#false} assume !(0 == ~T3_E~0); {91152#false} is VALID [2022-02-21 04:23:36,042 INFO L290 TraceCheckUtils]: 23: Hoare triple {91152#false} assume !(0 == ~T4_E~0); {91152#false} is VALID [2022-02-21 04:23:36,043 INFO L290 TraceCheckUtils]: 24: Hoare triple {91152#false} assume !(0 == ~T5_E~0); {91152#false} is VALID [2022-02-21 04:23:36,043 INFO L290 TraceCheckUtils]: 25: Hoare triple {91152#false} assume !(0 == ~T6_E~0); {91152#false} is VALID [2022-02-21 04:23:36,043 INFO L290 TraceCheckUtils]: 26: Hoare triple {91152#false} assume !(0 == ~T7_E~0); {91152#false} is VALID [2022-02-21 04:23:36,043 INFO L290 TraceCheckUtils]: 27: Hoare triple {91152#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {91152#false} is VALID [2022-02-21 04:23:36,043 INFO L290 TraceCheckUtils]: 28: Hoare triple {91152#false} assume !(0 == ~T9_E~0); {91152#false} is VALID [2022-02-21 04:23:36,043 INFO L290 TraceCheckUtils]: 29: Hoare triple {91152#false} assume !(0 == ~T10_E~0); {91152#false} is VALID [2022-02-21 04:23:36,043 INFO L290 TraceCheckUtils]: 30: Hoare triple {91152#false} assume !(0 == ~T11_E~0); {91152#false} is VALID [2022-02-21 04:23:36,044 INFO L290 TraceCheckUtils]: 31: Hoare triple {91152#false} assume !(0 == ~T12_E~0); {91152#false} is VALID [2022-02-21 04:23:36,044 INFO L290 TraceCheckUtils]: 32: Hoare triple {91152#false} assume !(0 == ~T13_E~0); {91152#false} is VALID [2022-02-21 04:23:36,044 INFO L290 TraceCheckUtils]: 33: Hoare triple {91152#false} assume !(0 == ~E_M~0); {91152#false} is VALID [2022-02-21 04:23:36,044 INFO L290 TraceCheckUtils]: 34: Hoare triple {91152#false} assume !(0 == ~E_1~0); {91152#false} is VALID [2022-02-21 04:23:36,044 INFO L290 TraceCheckUtils]: 35: Hoare triple {91152#false} assume 0 == ~E_2~0;~E_2~0 := 1; {91152#false} is VALID [2022-02-21 04:23:36,044 INFO L290 TraceCheckUtils]: 36: Hoare triple {91152#false} assume !(0 == ~E_3~0); {91152#false} is VALID [2022-02-21 04:23:36,044 INFO L290 TraceCheckUtils]: 37: Hoare triple {91152#false} assume !(0 == ~E_4~0); {91152#false} is VALID [2022-02-21 04:23:36,045 INFO L290 TraceCheckUtils]: 38: Hoare triple {91152#false} assume !(0 == ~E_5~0); {91152#false} is VALID [2022-02-21 04:23:36,045 INFO L290 TraceCheckUtils]: 39: Hoare triple {91152#false} assume !(0 == ~E_6~0); {91152#false} is VALID [2022-02-21 04:23:36,045 INFO L290 TraceCheckUtils]: 40: Hoare triple {91152#false} assume !(0 == ~E_7~0); {91152#false} is VALID [2022-02-21 04:23:36,045 INFO L290 TraceCheckUtils]: 41: Hoare triple {91152#false} assume !(0 == ~E_8~0); {91152#false} is VALID [2022-02-21 04:23:36,045 INFO L290 TraceCheckUtils]: 42: Hoare triple {91152#false} assume !(0 == ~E_9~0); {91152#false} is VALID [2022-02-21 04:23:36,045 INFO L290 TraceCheckUtils]: 43: Hoare triple {91152#false} assume 0 == ~E_10~0;~E_10~0 := 1; {91152#false} is VALID [2022-02-21 04:23:36,045 INFO L290 TraceCheckUtils]: 44: Hoare triple {91152#false} assume !(0 == ~E_11~0); {91152#false} is VALID [2022-02-21 04:23:36,046 INFO L290 TraceCheckUtils]: 45: Hoare triple {91152#false} assume !(0 == ~E_12~0); {91152#false} is VALID [2022-02-21 04:23:36,046 INFO L290 TraceCheckUtils]: 46: Hoare triple {91152#false} assume !(0 == ~E_13~0); {91152#false} is VALID [2022-02-21 04:23:36,046 INFO L290 TraceCheckUtils]: 47: Hoare triple {91152#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {91152#false} is VALID [2022-02-21 04:23:36,046 INFO L290 TraceCheckUtils]: 48: Hoare triple {91152#false} assume !(1 == ~m_pc~0); {91152#false} is VALID [2022-02-21 04:23:36,046 INFO L290 TraceCheckUtils]: 49: Hoare triple {91152#false} is_master_triggered_~__retres1~0#1 := 0; {91152#false} is VALID [2022-02-21 04:23:36,046 INFO L290 TraceCheckUtils]: 50: Hoare triple {91152#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {91152#false} is VALID [2022-02-21 04:23:36,046 INFO L290 TraceCheckUtils]: 51: Hoare triple {91152#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {91152#false} is VALID [2022-02-21 04:23:36,047 INFO L290 TraceCheckUtils]: 52: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp~1#1); {91152#false} is VALID [2022-02-21 04:23:36,047 INFO L290 TraceCheckUtils]: 53: Hoare triple {91152#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {91152#false} is VALID [2022-02-21 04:23:36,047 INFO L290 TraceCheckUtils]: 54: Hoare triple {91152#false} assume 1 == ~t1_pc~0; {91152#false} is VALID [2022-02-21 04:23:36,047 INFO L290 TraceCheckUtils]: 55: Hoare triple {91152#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {91152#false} is VALID [2022-02-21 04:23:36,047 INFO L290 TraceCheckUtils]: 56: Hoare triple {91152#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {91152#false} is VALID [2022-02-21 04:23:36,047 INFO L290 TraceCheckUtils]: 57: Hoare triple {91152#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {91152#false} is VALID [2022-02-21 04:23:36,047 INFO L290 TraceCheckUtils]: 58: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___0~0#1); {91152#false} is VALID [2022-02-21 04:23:36,047 INFO L290 TraceCheckUtils]: 59: Hoare triple {91152#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {91152#false} is VALID [2022-02-21 04:23:36,048 INFO L290 TraceCheckUtils]: 60: Hoare triple {91152#false} assume 1 == ~t2_pc~0; {91152#false} is VALID [2022-02-21 04:23:36,048 INFO L290 TraceCheckUtils]: 61: Hoare triple {91152#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {91152#false} is VALID [2022-02-21 04:23:36,048 INFO L290 TraceCheckUtils]: 62: Hoare triple {91152#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {91152#false} is VALID [2022-02-21 04:23:36,048 INFO L290 TraceCheckUtils]: 63: Hoare triple {91152#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {91152#false} is VALID [2022-02-21 04:23:36,048 INFO L290 TraceCheckUtils]: 64: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___1~0#1); {91152#false} is VALID [2022-02-21 04:23:36,048 INFO L290 TraceCheckUtils]: 65: Hoare triple {91152#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {91152#false} is VALID [2022-02-21 04:23:36,048 INFO L290 TraceCheckUtils]: 66: Hoare triple {91152#false} assume !(1 == ~t3_pc~0); {91152#false} is VALID [2022-02-21 04:23:36,049 INFO L290 TraceCheckUtils]: 67: Hoare triple {91152#false} is_transmit3_triggered_~__retres1~3#1 := 0; {91152#false} is VALID [2022-02-21 04:23:36,049 INFO L290 TraceCheckUtils]: 68: Hoare triple {91152#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {91152#false} is VALID [2022-02-21 04:23:36,049 INFO L290 TraceCheckUtils]: 69: Hoare triple {91152#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {91152#false} is VALID [2022-02-21 04:23:36,049 INFO L290 TraceCheckUtils]: 70: Hoare triple {91152#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {91152#false} is VALID [2022-02-21 04:23:36,049 INFO L290 TraceCheckUtils]: 71: Hoare triple {91152#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {91152#false} is VALID [2022-02-21 04:23:36,049 INFO L290 TraceCheckUtils]: 72: Hoare triple {91152#false} assume 1 == ~t4_pc~0; {91152#false} is VALID [2022-02-21 04:23:36,049 INFO L290 TraceCheckUtils]: 73: Hoare triple {91152#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {91152#false} is VALID [2022-02-21 04:23:36,050 INFO L290 TraceCheckUtils]: 74: Hoare triple {91152#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {91152#false} is VALID [2022-02-21 04:23:36,050 INFO L290 TraceCheckUtils]: 75: Hoare triple {91152#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {91152#false} is VALID [2022-02-21 04:23:36,050 INFO L290 TraceCheckUtils]: 76: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___3~0#1); {91152#false} is VALID [2022-02-21 04:23:36,050 INFO L290 TraceCheckUtils]: 77: Hoare triple {91152#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {91152#false} is VALID [2022-02-21 04:23:36,050 INFO L290 TraceCheckUtils]: 78: Hoare triple {91152#false} assume !(1 == ~t5_pc~0); {91152#false} is VALID [2022-02-21 04:23:36,050 INFO L290 TraceCheckUtils]: 79: Hoare triple {91152#false} is_transmit5_triggered_~__retres1~5#1 := 0; {91152#false} is VALID [2022-02-21 04:23:36,050 INFO L290 TraceCheckUtils]: 80: Hoare triple {91152#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {91152#false} is VALID [2022-02-21 04:23:36,051 INFO L290 TraceCheckUtils]: 81: Hoare triple {91152#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {91152#false} is VALID [2022-02-21 04:23:36,051 INFO L290 TraceCheckUtils]: 82: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___4~0#1); {91152#false} is VALID [2022-02-21 04:23:36,051 INFO L290 TraceCheckUtils]: 83: Hoare triple {91152#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {91152#false} is VALID [2022-02-21 04:23:36,051 INFO L290 TraceCheckUtils]: 84: Hoare triple {91152#false} assume 1 == ~t6_pc~0; {91152#false} is VALID [2022-02-21 04:23:36,051 INFO L290 TraceCheckUtils]: 85: Hoare triple {91152#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {91152#false} is VALID [2022-02-21 04:23:36,051 INFO L290 TraceCheckUtils]: 86: Hoare triple {91152#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {91152#false} is VALID [2022-02-21 04:23:36,051 INFO L290 TraceCheckUtils]: 87: Hoare triple {91152#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {91152#false} is VALID [2022-02-21 04:23:36,051 INFO L290 TraceCheckUtils]: 88: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___5~0#1); {91152#false} is VALID [2022-02-21 04:23:36,052 INFO L290 TraceCheckUtils]: 89: Hoare triple {91152#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {91152#false} is VALID [2022-02-21 04:23:36,052 INFO L290 TraceCheckUtils]: 90: Hoare triple {91152#false} assume !(1 == ~t7_pc~0); {91152#false} is VALID [2022-02-21 04:23:36,052 INFO L290 TraceCheckUtils]: 91: Hoare triple {91152#false} is_transmit7_triggered_~__retres1~7#1 := 0; {91152#false} is VALID [2022-02-21 04:23:36,052 INFO L290 TraceCheckUtils]: 92: Hoare triple {91152#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {91152#false} is VALID [2022-02-21 04:23:36,052 INFO L290 TraceCheckUtils]: 93: Hoare triple {91152#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {91152#false} is VALID [2022-02-21 04:23:36,052 INFO L290 TraceCheckUtils]: 94: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___6~0#1); {91152#false} is VALID [2022-02-21 04:23:36,052 INFO L290 TraceCheckUtils]: 95: Hoare triple {91152#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {91152#false} is VALID [2022-02-21 04:23:36,053 INFO L290 TraceCheckUtils]: 96: Hoare triple {91152#false} assume 1 == ~t8_pc~0; {91152#false} is VALID [2022-02-21 04:23:36,053 INFO L290 TraceCheckUtils]: 97: Hoare triple {91152#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {91152#false} is VALID [2022-02-21 04:23:36,053 INFO L290 TraceCheckUtils]: 98: Hoare triple {91152#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {91152#false} is VALID [2022-02-21 04:23:36,053 INFO L290 TraceCheckUtils]: 99: Hoare triple {91152#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {91152#false} is VALID [2022-02-21 04:23:36,053 INFO L290 TraceCheckUtils]: 100: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___7~0#1); {91152#false} is VALID [2022-02-21 04:23:36,053 INFO L290 TraceCheckUtils]: 101: Hoare triple {91152#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {91152#false} is VALID [2022-02-21 04:23:36,053 INFO L290 TraceCheckUtils]: 102: Hoare triple {91152#false} assume 1 == ~t9_pc~0; {91152#false} is VALID [2022-02-21 04:23:36,054 INFO L290 TraceCheckUtils]: 103: Hoare triple {91152#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {91152#false} is VALID [2022-02-21 04:23:36,054 INFO L290 TraceCheckUtils]: 104: Hoare triple {91152#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {91152#false} is VALID [2022-02-21 04:23:36,054 INFO L290 TraceCheckUtils]: 105: Hoare triple {91152#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {91152#false} is VALID [2022-02-21 04:23:36,054 INFO L290 TraceCheckUtils]: 106: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___8~0#1); {91152#false} is VALID [2022-02-21 04:23:36,054 INFO L290 TraceCheckUtils]: 107: Hoare triple {91152#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {91152#false} is VALID [2022-02-21 04:23:36,054 INFO L290 TraceCheckUtils]: 108: Hoare triple {91152#false} assume !(1 == ~t10_pc~0); {91152#false} is VALID [2022-02-21 04:23:36,054 INFO L290 TraceCheckUtils]: 109: Hoare triple {91152#false} is_transmit10_triggered_~__retres1~10#1 := 0; {91152#false} is VALID [2022-02-21 04:23:36,055 INFO L290 TraceCheckUtils]: 110: Hoare triple {91152#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {91152#false} is VALID [2022-02-21 04:23:36,055 INFO L290 TraceCheckUtils]: 111: Hoare triple {91152#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {91152#false} is VALID [2022-02-21 04:23:36,055 INFO L290 TraceCheckUtils]: 112: Hoare triple {91152#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {91152#false} is VALID [2022-02-21 04:23:36,055 INFO L290 TraceCheckUtils]: 113: Hoare triple {91152#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {91152#false} is VALID [2022-02-21 04:23:36,055 INFO L290 TraceCheckUtils]: 114: Hoare triple {91152#false} assume 1 == ~t11_pc~0; {91152#false} is VALID [2022-02-21 04:23:36,055 INFO L290 TraceCheckUtils]: 115: Hoare triple {91152#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {91152#false} is VALID [2022-02-21 04:23:36,055 INFO L290 TraceCheckUtils]: 116: Hoare triple {91152#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {91152#false} is VALID [2022-02-21 04:23:36,056 INFO L290 TraceCheckUtils]: 117: Hoare triple {91152#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {91152#false} is VALID [2022-02-21 04:23:36,056 INFO L290 TraceCheckUtils]: 118: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___10~0#1); {91152#false} is VALID [2022-02-21 04:23:36,056 INFO L290 TraceCheckUtils]: 119: Hoare triple {91152#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {91152#false} is VALID [2022-02-21 04:23:36,056 INFO L290 TraceCheckUtils]: 120: Hoare triple {91152#false} assume !(1 == ~t12_pc~0); {91152#false} is VALID [2022-02-21 04:23:36,056 INFO L290 TraceCheckUtils]: 121: Hoare triple {91152#false} is_transmit12_triggered_~__retres1~12#1 := 0; {91152#false} is VALID [2022-02-21 04:23:36,056 INFO L290 TraceCheckUtils]: 122: Hoare triple {91152#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {91152#false} is VALID [2022-02-21 04:23:36,056 INFO L290 TraceCheckUtils]: 123: Hoare triple {91152#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {91152#false} is VALID [2022-02-21 04:23:36,056 INFO L290 TraceCheckUtils]: 124: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___11~0#1); {91152#false} is VALID [2022-02-21 04:23:36,057 INFO L290 TraceCheckUtils]: 125: Hoare triple {91152#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {91152#false} is VALID [2022-02-21 04:23:36,057 INFO L290 TraceCheckUtils]: 126: Hoare triple {91152#false} assume 1 == ~t13_pc~0; {91152#false} is VALID [2022-02-21 04:23:36,057 INFO L290 TraceCheckUtils]: 127: Hoare triple {91152#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {91152#false} is VALID [2022-02-21 04:23:36,057 INFO L290 TraceCheckUtils]: 128: Hoare triple {91152#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {91152#false} is VALID [2022-02-21 04:23:36,057 INFO L290 TraceCheckUtils]: 129: Hoare triple {91152#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {91152#false} is VALID [2022-02-21 04:23:36,057 INFO L290 TraceCheckUtils]: 130: Hoare triple {91152#false} assume !(0 != activate_threads_~tmp___12~0#1); {91152#false} is VALID [2022-02-21 04:23:36,057 INFO L290 TraceCheckUtils]: 131: Hoare triple {91152#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {91152#false} is VALID [2022-02-21 04:23:36,058 INFO L290 TraceCheckUtils]: 132: Hoare triple {91152#false} assume !(1 == ~M_E~0); {91152#false} is VALID [2022-02-21 04:23:36,058 INFO L290 TraceCheckUtils]: 133: Hoare triple {91152#false} assume !(1 == ~T1_E~0); {91152#false} is VALID [2022-02-21 04:23:36,058 INFO L290 TraceCheckUtils]: 134: Hoare triple {91152#false} assume !(1 == ~T2_E~0); {91152#false} is VALID [2022-02-21 04:23:36,058 INFO L290 TraceCheckUtils]: 135: Hoare triple {91152#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {91152#false} is VALID [2022-02-21 04:23:36,058 INFO L290 TraceCheckUtils]: 136: Hoare triple {91152#false} assume !(1 == ~T4_E~0); {91152#false} is VALID [2022-02-21 04:23:36,058 INFO L290 TraceCheckUtils]: 137: Hoare triple {91152#false} assume !(1 == ~T5_E~0); {91152#false} is VALID [2022-02-21 04:23:36,058 INFO L290 TraceCheckUtils]: 138: Hoare triple {91152#false} assume !(1 == ~T6_E~0); {91152#false} is VALID [2022-02-21 04:23:36,059 INFO L290 TraceCheckUtils]: 139: Hoare triple {91152#false} assume !(1 == ~T7_E~0); {91152#false} is VALID [2022-02-21 04:23:36,059 INFO L290 TraceCheckUtils]: 140: Hoare triple {91152#false} assume !(1 == ~T8_E~0); {91152#false} is VALID [2022-02-21 04:23:36,059 INFO L290 TraceCheckUtils]: 141: Hoare triple {91152#false} assume !(1 == ~T9_E~0); {91152#false} is VALID [2022-02-21 04:23:36,059 INFO L290 TraceCheckUtils]: 142: Hoare triple {91152#false} assume !(1 == ~T10_E~0); {91152#false} is VALID [2022-02-21 04:23:36,059 INFO L290 TraceCheckUtils]: 143: Hoare triple {91152#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {91152#false} is VALID [2022-02-21 04:23:36,059 INFO L290 TraceCheckUtils]: 144: Hoare triple {91152#false} assume !(1 == ~T12_E~0); {91152#false} is VALID [2022-02-21 04:23:36,059 INFO L290 TraceCheckUtils]: 145: Hoare triple {91152#false} assume !(1 == ~T13_E~0); {91152#false} is VALID [2022-02-21 04:23:36,059 INFO L290 TraceCheckUtils]: 146: Hoare triple {91152#false} assume !(1 == ~E_M~0); {91152#false} is VALID [2022-02-21 04:23:36,060 INFO L290 TraceCheckUtils]: 147: Hoare triple {91152#false} assume !(1 == ~E_1~0); {91152#false} is VALID [2022-02-21 04:23:36,060 INFO L290 TraceCheckUtils]: 148: Hoare triple {91152#false} assume !(1 == ~E_2~0); {91152#false} is VALID [2022-02-21 04:23:36,060 INFO L290 TraceCheckUtils]: 149: Hoare triple {91152#false} assume !(1 == ~E_3~0); {91152#false} is VALID [2022-02-21 04:23:36,060 INFO L290 TraceCheckUtils]: 150: Hoare triple {91152#false} assume !(1 == ~E_4~0); {91152#false} is VALID [2022-02-21 04:23:36,060 INFO L290 TraceCheckUtils]: 151: Hoare triple {91152#false} assume 1 == ~E_5~0;~E_5~0 := 2; {91152#false} is VALID [2022-02-21 04:23:36,060 INFO L290 TraceCheckUtils]: 152: Hoare triple {91152#false} assume !(1 == ~E_6~0); {91152#false} is VALID [2022-02-21 04:23:36,060 INFO L290 TraceCheckUtils]: 153: Hoare triple {91152#false} assume !(1 == ~E_7~0); {91152#false} is VALID [2022-02-21 04:23:36,061 INFO L290 TraceCheckUtils]: 154: Hoare triple {91152#false} assume !(1 == ~E_8~0); {91152#false} is VALID [2022-02-21 04:23:36,061 INFO L290 TraceCheckUtils]: 155: Hoare triple {91152#false} assume !(1 == ~E_9~0); {91152#false} is VALID [2022-02-21 04:23:36,061 INFO L290 TraceCheckUtils]: 156: Hoare triple {91152#false} assume !(1 == ~E_10~0); {91152#false} is VALID [2022-02-21 04:23:36,061 INFO L290 TraceCheckUtils]: 157: Hoare triple {91152#false} assume !(1 == ~E_11~0); {91152#false} is VALID [2022-02-21 04:23:36,061 INFO L290 TraceCheckUtils]: 158: Hoare triple {91152#false} assume !(1 == ~E_12~0); {91152#false} is VALID [2022-02-21 04:23:36,061 INFO L290 TraceCheckUtils]: 159: Hoare triple {91152#false} assume 1 == ~E_13~0;~E_13~0 := 2; {91152#false} is VALID [2022-02-21 04:23:36,061 INFO L290 TraceCheckUtils]: 160: Hoare triple {91152#false} assume { :end_inline_reset_delta_events } true; {91152#false} is VALID [2022-02-21 04:23:36,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:36,062 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:36,062 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [541942838] [2022-02-21 04:23:36,062 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [541942838] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:36,062 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:36,063 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:36,063 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228752921] [2022-02-21 04:23:36,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:36,063 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:36,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:36,064 INFO L85 PathProgramCache]: Analyzing trace with hash -1164617187, now seen corresponding path program 1 times [2022-02-21 04:23:36,064 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:36,064 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223753513] [2022-02-21 04:23:36,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:36,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:36,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:36,097 INFO L290 TraceCheckUtils]: 0: Hoare triple {91154#true} assume !false; {91154#true} is VALID [2022-02-21 04:23:36,097 INFO L290 TraceCheckUtils]: 1: Hoare triple {91154#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {91154#true} is VALID [2022-02-21 04:23:36,097 INFO L290 TraceCheckUtils]: 2: Hoare triple {91154#true} assume !false; {91154#true} is VALID [2022-02-21 04:23:36,097 INFO L290 TraceCheckUtils]: 3: Hoare triple {91154#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {91154#true} is VALID [2022-02-21 04:23:36,098 INFO L290 TraceCheckUtils]: 4: Hoare triple {91154#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {91154#true} is VALID [2022-02-21 04:23:36,098 INFO L290 TraceCheckUtils]: 5: Hoare triple {91154#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {91154#true} is VALID [2022-02-21 04:23:36,098 INFO L290 TraceCheckUtils]: 6: Hoare triple {91154#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {91154#true} is VALID [2022-02-21 04:23:36,098 INFO L290 TraceCheckUtils]: 7: Hoare triple {91154#true} assume !(0 != eval_~tmp~0#1); {91154#true} is VALID [2022-02-21 04:23:36,098 INFO L290 TraceCheckUtils]: 8: Hoare triple {91154#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {91154#true} is VALID [2022-02-21 04:23:36,098 INFO L290 TraceCheckUtils]: 9: Hoare triple {91154#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {91154#true} is VALID [2022-02-21 04:23:36,098 INFO L290 TraceCheckUtils]: 10: Hoare triple {91154#true} assume 0 == ~M_E~0;~M_E~0 := 1; {91154#true} is VALID [2022-02-21 04:23:36,099 INFO L290 TraceCheckUtils]: 11: Hoare triple {91154#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {91154#true} is VALID [2022-02-21 04:23:36,099 INFO L290 TraceCheckUtils]: 12: Hoare triple {91154#true} assume !(0 == ~T2_E~0); {91154#true} is VALID [2022-02-21 04:23:36,099 INFO L290 TraceCheckUtils]: 13: Hoare triple {91154#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {91154#true} is VALID [2022-02-21 04:23:36,099 INFO L290 TraceCheckUtils]: 14: Hoare triple {91154#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {91154#true} is VALID [2022-02-21 04:23:36,099 INFO L290 TraceCheckUtils]: 15: Hoare triple {91154#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,100 INFO L290 TraceCheckUtils]: 16: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,100 INFO L290 TraceCheckUtils]: 17: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,100 INFO L290 TraceCheckUtils]: 18: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,101 INFO L290 TraceCheckUtils]: 19: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,101 INFO L290 TraceCheckUtils]: 20: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,102 INFO L290 TraceCheckUtils]: 21: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,102 INFO L290 TraceCheckUtils]: 22: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,102 INFO L290 TraceCheckUtils]: 23: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,103 INFO L290 TraceCheckUtils]: 24: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,103 INFO L290 TraceCheckUtils]: 25: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,103 INFO L290 TraceCheckUtils]: 26: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,104 INFO L290 TraceCheckUtils]: 27: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,104 INFO L290 TraceCheckUtils]: 28: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,104 INFO L290 TraceCheckUtils]: 29: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,105 INFO L290 TraceCheckUtils]: 30: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,105 INFO L290 TraceCheckUtils]: 31: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,106 INFO L290 TraceCheckUtils]: 32: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,106 INFO L290 TraceCheckUtils]: 33: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,106 INFO L290 TraceCheckUtils]: 34: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,107 INFO L290 TraceCheckUtils]: 35: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,107 INFO L290 TraceCheckUtils]: 36: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,107 INFO L290 TraceCheckUtils]: 37: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,108 INFO L290 TraceCheckUtils]: 38: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,108 INFO L290 TraceCheckUtils]: 39: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,109 INFO L290 TraceCheckUtils]: 40: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,109 INFO L290 TraceCheckUtils]: 41: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,109 INFO L290 TraceCheckUtils]: 42: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,110 INFO L290 TraceCheckUtils]: 43: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,110 INFO L290 TraceCheckUtils]: 44: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,110 INFO L290 TraceCheckUtils]: 45: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,111 INFO L290 TraceCheckUtils]: 46: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,111 INFO L290 TraceCheckUtils]: 47: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,112 INFO L290 TraceCheckUtils]: 48: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,112 INFO L290 TraceCheckUtils]: 49: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,112 INFO L290 TraceCheckUtils]: 50: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,113 INFO L290 TraceCheckUtils]: 51: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,113 INFO L290 TraceCheckUtils]: 52: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,113 INFO L290 TraceCheckUtils]: 53: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,114 INFO L290 TraceCheckUtils]: 54: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,114 INFO L290 TraceCheckUtils]: 55: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,114 INFO L290 TraceCheckUtils]: 56: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,115 INFO L290 TraceCheckUtils]: 57: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,115 INFO L290 TraceCheckUtils]: 58: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,116 INFO L290 TraceCheckUtils]: 59: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,116 INFO L290 TraceCheckUtils]: 60: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,116 INFO L290 TraceCheckUtils]: 61: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,117 INFO L290 TraceCheckUtils]: 62: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,117 INFO L290 TraceCheckUtils]: 63: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,117 INFO L290 TraceCheckUtils]: 64: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,118 INFO L290 TraceCheckUtils]: 65: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,118 INFO L290 TraceCheckUtils]: 66: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,118 INFO L290 TraceCheckUtils]: 67: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,119 INFO L290 TraceCheckUtils]: 68: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,119 INFO L290 TraceCheckUtils]: 69: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,120 INFO L290 TraceCheckUtils]: 70: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,120 INFO L290 TraceCheckUtils]: 71: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,120 INFO L290 TraceCheckUtils]: 72: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,121 INFO L290 TraceCheckUtils]: 73: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,121 INFO L290 TraceCheckUtils]: 74: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,121 INFO L290 TraceCheckUtils]: 75: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,122 INFO L290 TraceCheckUtils]: 76: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,122 INFO L290 TraceCheckUtils]: 77: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,122 INFO L290 TraceCheckUtils]: 78: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,123 INFO L290 TraceCheckUtils]: 79: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,123 INFO L290 TraceCheckUtils]: 80: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,124 INFO L290 TraceCheckUtils]: 81: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,124 INFO L290 TraceCheckUtils]: 82: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,124 INFO L290 TraceCheckUtils]: 83: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,125 INFO L290 TraceCheckUtils]: 84: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,125 INFO L290 TraceCheckUtils]: 85: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,125 INFO L290 TraceCheckUtils]: 86: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,126 INFO L290 TraceCheckUtils]: 87: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,126 INFO L290 TraceCheckUtils]: 88: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,127 INFO L290 TraceCheckUtils]: 89: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,127 INFO L290 TraceCheckUtils]: 90: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,127 INFO L290 TraceCheckUtils]: 91: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,128 INFO L290 TraceCheckUtils]: 92: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,128 INFO L290 TraceCheckUtils]: 93: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,128 INFO L290 TraceCheckUtils]: 94: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,129 INFO L290 TraceCheckUtils]: 95: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,129 INFO L290 TraceCheckUtils]: 96: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,130 INFO L290 TraceCheckUtils]: 97: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,130 INFO L290 TraceCheckUtils]: 98: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,130 INFO L290 TraceCheckUtils]: 99: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,131 INFO L290 TraceCheckUtils]: 100: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,131 INFO L290 TraceCheckUtils]: 101: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,131 INFO L290 TraceCheckUtils]: 102: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,132 INFO L290 TraceCheckUtils]: 103: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,132 INFO L290 TraceCheckUtils]: 104: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,132 INFO L290 TraceCheckUtils]: 105: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,133 INFO L290 TraceCheckUtils]: 106: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,133 INFO L290 TraceCheckUtils]: 107: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,134 INFO L290 TraceCheckUtils]: 108: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,134 INFO L290 TraceCheckUtils]: 109: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,134 INFO L290 TraceCheckUtils]: 110: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,135 INFO L290 TraceCheckUtils]: 111: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,135 INFO L290 TraceCheckUtils]: 112: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,135 INFO L290 TraceCheckUtils]: 113: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,136 INFO L290 TraceCheckUtils]: 114: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,136 INFO L290 TraceCheckUtils]: 115: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,136 INFO L290 TraceCheckUtils]: 116: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,137 INFO L290 TraceCheckUtils]: 117: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,137 INFO L290 TraceCheckUtils]: 118: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,138 INFO L290 TraceCheckUtils]: 119: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,138 INFO L290 TraceCheckUtils]: 120: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,138 INFO L290 TraceCheckUtils]: 121: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,139 INFO L290 TraceCheckUtils]: 122: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,139 INFO L290 TraceCheckUtils]: 123: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,139 INFO L290 TraceCheckUtils]: 124: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,140 INFO L290 TraceCheckUtils]: 125: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,140 INFO L290 TraceCheckUtils]: 126: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,141 INFO L290 TraceCheckUtils]: 127: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {91156#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:36,141 INFO L290 TraceCheckUtils]: 128: Hoare triple {91156#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {91155#false} is VALID [2022-02-21 04:23:36,141 INFO L290 TraceCheckUtils]: 129: Hoare triple {91155#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,141 INFO L290 TraceCheckUtils]: 130: Hoare triple {91155#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,141 INFO L290 TraceCheckUtils]: 131: Hoare triple {91155#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,142 INFO L290 TraceCheckUtils]: 132: Hoare triple {91155#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,142 INFO L290 TraceCheckUtils]: 133: Hoare triple {91155#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,142 INFO L290 TraceCheckUtils]: 134: Hoare triple {91155#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,142 INFO L290 TraceCheckUtils]: 135: Hoare triple {91155#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,142 INFO L290 TraceCheckUtils]: 136: Hoare triple {91155#false} assume !(1 == ~T13_E~0); {91155#false} is VALID [2022-02-21 04:23:36,142 INFO L290 TraceCheckUtils]: 137: Hoare triple {91155#false} assume 1 == ~E_M~0;~E_M~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,142 INFO L290 TraceCheckUtils]: 138: Hoare triple {91155#false} assume 1 == ~E_1~0;~E_1~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,142 INFO L290 TraceCheckUtils]: 139: Hoare triple {91155#false} assume 1 == ~E_2~0;~E_2~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,143 INFO L290 TraceCheckUtils]: 140: Hoare triple {91155#false} assume 1 == ~E_3~0;~E_3~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,143 INFO L290 TraceCheckUtils]: 141: Hoare triple {91155#false} assume 1 == ~E_4~0;~E_4~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,143 INFO L290 TraceCheckUtils]: 142: Hoare triple {91155#false} assume 1 == ~E_5~0;~E_5~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,143 INFO L290 TraceCheckUtils]: 143: Hoare triple {91155#false} assume 1 == ~E_6~0;~E_6~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,143 INFO L290 TraceCheckUtils]: 144: Hoare triple {91155#false} assume !(1 == ~E_7~0); {91155#false} is VALID [2022-02-21 04:23:36,143 INFO L290 TraceCheckUtils]: 145: Hoare triple {91155#false} assume 1 == ~E_8~0;~E_8~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,143 INFO L290 TraceCheckUtils]: 146: Hoare triple {91155#false} assume 1 == ~E_9~0;~E_9~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,144 INFO L290 TraceCheckUtils]: 147: Hoare triple {91155#false} assume 1 == ~E_10~0;~E_10~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,144 INFO L290 TraceCheckUtils]: 148: Hoare triple {91155#false} assume 1 == ~E_11~0;~E_11~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,144 INFO L290 TraceCheckUtils]: 149: Hoare triple {91155#false} assume 1 == ~E_12~0;~E_12~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,144 INFO L290 TraceCheckUtils]: 150: Hoare triple {91155#false} assume 1 == ~E_13~0;~E_13~0 := 2; {91155#false} is VALID [2022-02-21 04:23:36,144 INFO L290 TraceCheckUtils]: 151: Hoare triple {91155#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {91155#false} is VALID [2022-02-21 04:23:36,144 INFO L290 TraceCheckUtils]: 152: Hoare triple {91155#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {91155#false} is VALID [2022-02-21 04:23:36,144 INFO L290 TraceCheckUtils]: 153: Hoare triple {91155#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {91155#false} is VALID [2022-02-21 04:23:36,145 INFO L290 TraceCheckUtils]: 154: Hoare triple {91155#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {91155#false} is VALID [2022-02-21 04:23:36,145 INFO L290 TraceCheckUtils]: 155: Hoare triple {91155#false} assume !(0 == start_simulation_~tmp~3#1); {91155#false} is VALID [2022-02-21 04:23:36,145 INFO L290 TraceCheckUtils]: 156: Hoare triple {91155#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {91155#false} is VALID [2022-02-21 04:23:36,145 INFO L290 TraceCheckUtils]: 157: Hoare triple {91155#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {91155#false} is VALID [2022-02-21 04:23:36,145 INFO L290 TraceCheckUtils]: 158: Hoare triple {91155#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {91155#false} is VALID [2022-02-21 04:23:36,145 INFO L290 TraceCheckUtils]: 159: Hoare triple {91155#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {91155#false} is VALID [2022-02-21 04:23:36,145 INFO L290 TraceCheckUtils]: 160: Hoare triple {91155#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {91155#false} is VALID [2022-02-21 04:23:36,145 INFO L290 TraceCheckUtils]: 161: Hoare triple {91155#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {91155#false} is VALID [2022-02-21 04:23:36,145 INFO L290 TraceCheckUtils]: 162: Hoare triple {91155#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {91155#false} is VALID [2022-02-21 04:23:36,145 INFO L290 TraceCheckUtils]: 163: Hoare triple {91155#false} assume !(0 != start_simulation_~tmp___0~1#1); {91155#false} is VALID [2022-02-21 04:23:36,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:36,146 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:36,146 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223753513] [2022-02-21 04:23:36,146 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1223753513] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:36,146 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:36,146 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:36,146 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732700345] [2022-02-21 04:23:36,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:36,156 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:36,156 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:36,157 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:36,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:36,157 INFO L87 Difference]: Start difference. First operand 2023 states and 2986 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:37,583 INFO L93 Difference]: Finished difference Result 2023 states and 2985 transitions. [2022-02-21 04:23:37,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:37,583 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,676 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:37,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2985 transitions. [2022-02-21 04:23:37,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:37,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2985 transitions. [2022-02-21 04:23:37,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:37,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:37,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2985 transitions. [2022-02-21 04:23:37,877 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:37,877 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2022-02-21 04:23:37,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2985 transitions. [2022-02-21 04:23:37,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:37,894 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:37,895 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2985 transitions. Second operand has 2023 states, 2023 states have (on average 1.4755313890261987) internal successors, (2985), 2022 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,896 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2985 transitions. Second operand has 2023 states, 2023 states have (on average 1.4755313890261987) internal successors, (2985), 2022 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,897 INFO L87 Difference]: Start difference. First operand 2023 states and 2985 transitions. Second operand has 2023 states, 2023 states have (on average 1.4755313890261987) internal successors, (2985), 2022 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:37,979 INFO L93 Difference]: Finished difference Result 2023 states and 2985 transitions. [2022-02-21 04:23:37,979 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2985 transitions. [2022-02-21 04:23:37,981 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:37,981 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:37,982 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4755313890261987) internal successors, (2985), 2022 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2985 transitions. [2022-02-21 04:23:37,983 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4755313890261987) internal successors, (2985), 2022 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2985 transitions. [2022-02-21 04:23:38,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:38,067 INFO L93 Difference]: Finished difference Result 2023 states and 2985 transitions. [2022-02-21 04:23:38,067 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2985 transitions. [2022-02-21 04:23:38,069 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:38,069 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:38,069 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:38,069 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:38,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4755313890261987) internal successors, (2985), 2022 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2985 transitions. [2022-02-21 04:23:38,169 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2022-02-21 04:23:38,169 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2022-02-21 04:23:38,169 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:23:38,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2985 transitions. [2022-02-21 04:23:38,172 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:38,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:38,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:38,173 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:38,173 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:38,174 INFO L791 eck$LassoCheckResult]: Stem: 94107#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 94108#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 95106#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95107#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95192#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 94571#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94040#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94041#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94857#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94858#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94958#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 94959#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 93812#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 93813#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 94988#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 94348#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 94349#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 94909#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 94250#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94251#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 95193#L1291-2 assume !(0 == ~T1_E~0); 95191#L1296-1 assume !(0 == ~T2_E~0); 94407#L1301-1 assume !(0 == ~T3_E~0); 94408#L1306-1 assume !(0 == ~T4_E~0); 94917#L1311-1 assume !(0 == ~T5_E~0); 93655#L1316-1 assume !(0 == ~T6_E~0); 93656#L1321-1 assume !(0 == ~T7_E~0); 94420#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 93483#L1331-1 assume !(0 == ~T9_E~0); 93182#L1336-1 assume !(0 == ~T10_E~0); 93183#L1341-1 assume !(0 == ~T11_E~0); 93263#L1346-1 assume !(0 == ~T12_E~0); 93264#L1351-1 assume !(0 == ~T13_E~0); 93604#L1356-1 assume !(0 == ~E_M~0); 93605#L1361-1 assume !(0 == ~E_1~0); 95132#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 93645#L1371-1 assume !(0 == ~E_3~0); 93646#L1376-1 assume !(0 == ~E_4~0); 94467#L1381-1 assume !(0 == ~E_5~0); 94468#L1386-1 assume !(0 == ~E_6~0); 95162#L1391-1 assume !(0 == ~E_7~0); 95180#L1396-1 assume !(0 == ~E_8~0); 94380#L1401-1 assume !(0 == ~E_9~0); 94381#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 94659#L1411-1 assume !(0 == ~E_11~0); 94660#L1416-1 assume !(0 == ~E_12~0); 94292#L1421-1 assume !(0 == ~E_13~0); 93835#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93836#L640 assume !(1 == ~m_pc~0); 94345#L640-2 is_master_triggered_~__retres1~0#1 := 0; 94344#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94436#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94330#L1603 assume !(0 != activate_threads_~tmp~1#1); 94331#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93965#L659 assume 1 == ~t1_pc~0; 93966#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 94071#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95017#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94091#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 94092#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94105#L678 assume 1 == ~t2_pc~0; 95059#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95060#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95159#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94203#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 94204#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94325#L697 assume !(1 == ~t3_pc~0); 94326#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94448#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94256#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94235#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 94236#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95096#L716 assume 1 == ~t4_pc~0; 95082#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 93946#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93947#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 93446#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 93447#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94738#L735 assume !(1 == ~t5_pc~0); 93407#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 93408#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 93858#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 94765#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 94401#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94402#L754 assume 1 == ~t6_pc~0; 94155#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 94053#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94054#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94027#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 94028#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94848#L773 assume !(1 == ~t7_pc~0); 93608#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 93607#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94437#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94409#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 94410#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94457#L792 assume 1 == ~t8_pc~0; 94630#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 94962#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 94451#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 94404#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 94328#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94329#L811 assume 1 == ~t9_pc~0; 94533#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 94999#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94875#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 94529#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 94341#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 94342#L830 assume !(1 == ~t10_pc~0); 94063#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 93587#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 93280#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 93281#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 93568#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 94866#L849 assume 1 == ~t11_pc~0; 94867#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 93383#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 93384#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 93973#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 94772#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 94773#L868 assume !(1 == ~t12_pc~0); 94188#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 94187#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 93982#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 93983#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 93619#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 93620#L887 assume 1 == ~t13_pc~0; 94787#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 94229#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 94230#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 94666#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 93323#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93324#L1439 assume !(1 == ~M_E~0); 94397#L1439-2 assume !(1 == ~T1_E~0); 93495#L1444-1 assume !(1 == ~T2_E~0); 93496#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93969#L1454-1 assume !(1 == ~T4_E~0); 93970#L1459-1 assume !(1 == ~T5_E~0); 94526#L1464-1 assume !(1 == ~T6_E~0); 94527#L1469-1 assume !(1 == ~T7_E~0); 94599#L1474-1 assume !(1 == ~T8_E~0); 94293#L1479-1 assume !(1 == ~T9_E~0); 94294#L1484-1 assume !(1 == ~T10_E~0); 94530#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94176#L1494-1 assume !(1 == ~T12_E~0); 94177#L1499-1 assume !(1 == ~T13_E~0); 94369#L1504-1 assume !(1 == ~E_M~0); 94370#L1509-1 assume !(1 == ~E_1~0); 94945#L1514-1 assume !(1 == ~E_2~0); 94632#L1519-1 assume !(1 == ~E_3~0); 94633#L1524-1 assume !(1 == ~E_4~0); 95145#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 95146#L1534-1 assume !(1 == ~E_6~0); 93316#L1539-1 assume !(1 == ~E_7~0); 93317#L1544-1 assume !(1 == ~E_8~0); 93731#L1549-1 assume !(1 == ~E_9~0); 95120#L1554-1 assume !(1 == ~E_10~0); 95116#L1559-1 assume !(1 == ~E_11~0); 94983#L1564-1 assume !(1 == ~E_12~0); 94984#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 95141#L1574-1 assume { :end_inline_reset_delta_events } true; 93493#L1940-2 [2022-02-21 04:23:38,174 INFO L793 eck$LassoCheckResult]: Loop: 93493#L1940-2 assume !false; 93494#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93776#L1266 assume !false; 94795#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 94024#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93757#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 94148#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 94149#L1079 assume !(0 != eval_~tmp~0#1); 94110#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94111#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94715#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 94600#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 94601#L1296-3 assume !(0 == ~T2_E~0); 95173#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 95127#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 94258#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 93534#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 93535#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 93635#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 94392#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 94641#L1336-3 assume !(0 == ~T10_E~0); 94642#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 93962#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 93942#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 93887#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 93888#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 94449#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 93238#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 93239#L1376-3 assume !(0 == ~E_4~0); 94968#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 94828#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 94829#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 94991#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 94992#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 93601#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 93455#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 93456#L1416-3 assume !(0 == ~E_12~0); 94117#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 94118#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94225#L640-45 assume 1 == ~m_pc~0; 94227#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 93692#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93693#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 93232#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 93233#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93331#L659-45 assume !(1 == ~t1_pc~0); 93333#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 93771#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94730#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94731#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 94752#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94753#L678-45 assume !(1 == ~t2_pc~0); 94697#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 94231#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94232#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94384#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95009#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95126#L697-45 assume 1 == ~t3_pc~0; 94489#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94490#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95078#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94648#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 94649#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94679#L716-45 assume 1 == ~t4_pc~0; 94310#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 94311#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94861#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 94316#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94317#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 93979#L735-45 assume !(1 == ~t5_pc~0); 93981#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 94523#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95085#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 95086#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 95144#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95139#L754-45 assume 1 == ~t6_pc~0; 94471#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 94472#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 93901#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93902#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 94475#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94207#L773-45 assume 1 == ~t7_pc~0; 94208#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 93765#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94685#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94967#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 94213#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 93883#L792-45 assume !(1 == ~t8_pc~0); 93885#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 94913#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 93486#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 93345#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 93346#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 93841#L811-45 assume !(1 == ~t9_pc~0); 93631#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 93632#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94840#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 94675#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 94284#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 94076#L830-45 assume !(1 == ~t10_pc~0); 93273#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 93274#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94396#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 93506#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 93507#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 93252#L849-45 assume !(1 == ~t11_pc~0); 93253#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 93712#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 93343#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 93240#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 93241#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 93499#L868-45 assume !(1 == ~t12_pc~0); 93501#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 93439#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 93440#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 94778#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 95029#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 95030#L887-45 assume !(1 == ~t13_pc~0); 93508#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 93509#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 94791#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 95136#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 93471#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93472#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 94779#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 93491#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 93492#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93649#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94580#L1459-3 assume !(1 == ~T5_E~0); 94581#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 95032#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 94971#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 94972#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 95033#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 94265#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94266#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 94902#L1499-3 assume !(1 == ~T13_E~0); 94541#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 94542#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 94980#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 95010#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94184#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 94185#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 95052#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 94452#L1539-3 assume !(1 == ~E_7~0); 93928#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 93929#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 94424#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 93545#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 93546#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 94680#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 94681#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 93422#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93193#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 93468#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 93429#L1959 assume !(0 == start_simulation_~tmp~3#1); 93431#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 93463#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93413#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 94722#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 94843#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 95050#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 95064#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 95065#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 93493#L1940-2 [2022-02-21 04:23:38,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:38,175 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2022-02-21 04:23:38,175 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:38,175 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973975971] [2022-02-21 04:23:38,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:38,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:38,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:38,200 INFO L290 TraceCheckUtils]: 0: Hoare triple {99252#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {99252#true} is VALID [2022-02-21 04:23:38,201 INFO L290 TraceCheckUtils]: 1: Hoare triple {99252#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,201 INFO L290 TraceCheckUtils]: 2: Hoare triple {99254#(= ~t13_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,202 INFO L290 TraceCheckUtils]: 3: Hoare triple {99254#(= ~t13_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,202 INFO L290 TraceCheckUtils]: 4: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,202 INFO L290 TraceCheckUtils]: 5: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,202 INFO L290 TraceCheckUtils]: 6: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,203 INFO L290 TraceCheckUtils]: 7: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,203 INFO L290 TraceCheckUtils]: 8: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,203 INFO L290 TraceCheckUtils]: 9: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,204 INFO L290 TraceCheckUtils]: 10: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,204 INFO L290 TraceCheckUtils]: 11: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,204 INFO L290 TraceCheckUtils]: 12: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,205 INFO L290 TraceCheckUtils]: 13: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,205 INFO L290 TraceCheckUtils]: 14: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,205 INFO L290 TraceCheckUtils]: 15: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,206 INFO L290 TraceCheckUtils]: 16: Hoare triple {99254#(= ~t13_i~0 1)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {99254#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:38,206 INFO L290 TraceCheckUtils]: 17: Hoare triple {99254#(= ~t13_i~0 1)} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {99253#false} is VALID [2022-02-21 04:23:38,206 INFO L290 TraceCheckUtils]: 18: Hoare triple {99253#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {99253#false} is VALID [2022-02-21 04:23:38,206 INFO L290 TraceCheckUtils]: 19: Hoare triple {99253#false} assume 0 == ~M_E~0;~M_E~0 := 1; {99253#false} is VALID [2022-02-21 04:23:38,206 INFO L290 TraceCheckUtils]: 20: Hoare triple {99253#false} assume !(0 == ~T1_E~0); {99253#false} is VALID [2022-02-21 04:23:38,206 INFO L290 TraceCheckUtils]: 21: Hoare triple {99253#false} assume !(0 == ~T2_E~0); {99253#false} is VALID [2022-02-21 04:23:38,207 INFO L290 TraceCheckUtils]: 22: Hoare triple {99253#false} assume !(0 == ~T3_E~0); {99253#false} is VALID [2022-02-21 04:23:38,207 INFO L290 TraceCheckUtils]: 23: Hoare triple {99253#false} assume !(0 == ~T4_E~0); {99253#false} is VALID [2022-02-21 04:23:38,207 INFO L290 TraceCheckUtils]: 24: Hoare triple {99253#false} assume !(0 == ~T5_E~0); {99253#false} is VALID [2022-02-21 04:23:38,207 INFO L290 TraceCheckUtils]: 25: Hoare triple {99253#false} assume !(0 == ~T6_E~0); {99253#false} is VALID [2022-02-21 04:23:38,207 INFO L290 TraceCheckUtils]: 26: Hoare triple {99253#false} assume !(0 == ~T7_E~0); {99253#false} is VALID [2022-02-21 04:23:38,207 INFO L290 TraceCheckUtils]: 27: Hoare triple {99253#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {99253#false} is VALID [2022-02-21 04:23:38,207 INFO L290 TraceCheckUtils]: 28: Hoare triple {99253#false} assume !(0 == ~T9_E~0); {99253#false} is VALID [2022-02-21 04:23:38,208 INFO L290 TraceCheckUtils]: 29: Hoare triple {99253#false} assume !(0 == ~T10_E~0); {99253#false} is VALID [2022-02-21 04:23:38,208 INFO L290 TraceCheckUtils]: 30: Hoare triple {99253#false} assume !(0 == ~T11_E~0); {99253#false} is VALID [2022-02-21 04:23:38,208 INFO L290 TraceCheckUtils]: 31: Hoare triple {99253#false} assume !(0 == ~T12_E~0); {99253#false} is VALID [2022-02-21 04:23:38,208 INFO L290 TraceCheckUtils]: 32: Hoare triple {99253#false} assume !(0 == ~T13_E~0); {99253#false} is VALID [2022-02-21 04:23:38,208 INFO L290 TraceCheckUtils]: 33: Hoare triple {99253#false} assume !(0 == ~E_M~0); {99253#false} is VALID [2022-02-21 04:23:38,208 INFO L290 TraceCheckUtils]: 34: Hoare triple {99253#false} assume !(0 == ~E_1~0); {99253#false} is VALID [2022-02-21 04:23:38,208 INFO L290 TraceCheckUtils]: 35: Hoare triple {99253#false} assume 0 == ~E_2~0;~E_2~0 := 1; {99253#false} is VALID [2022-02-21 04:23:38,209 INFO L290 TraceCheckUtils]: 36: Hoare triple {99253#false} assume !(0 == ~E_3~0); {99253#false} is VALID [2022-02-21 04:23:38,209 INFO L290 TraceCheckUtils]: 37: Hoare triple {99253#false} assume !(0 == ~E_4~0); {99253#false} is VALID [2022-02-21 04:23:38,209 INFO L290 TraceCheckUtils]: 38: Hoare triple {99253#false} assume !(0 == ~E_5~0); {99253#false} is VALID [2022-02-21 04:23:38,209 INFO L290 TraceCheckUtils]: 39: Hoare triple {99253#false} assume !(0 == ~E_6~0); {99253#false} is VALID [2022-02-21 04:23:38,209 INFO L290 TraceCheckUtils]: 40: Hoare triple {99253#false} assume !(0 == ~E_7~0); {99253#false} is VALID [2022-02-21 04:23:38,209 INFO L290 TraceCheckUtils]: 41: Hoare triple {99253#false} assume !(0 == ~E_8~0); {99253#false} is VALID [2022-02-21 04:23:38,209 INFO L290 TraceCheckUtils]: 42: Hoare triple {99253#false} assume !(0 == ~E_9~0); {99253#false} is VALID [2022-02-21 04:23:38,210 INFO L290 TraceCheckUtils]: 43: Hoare triple {99253#false} assume 0 == ~E_10~0;~E_10~0 := 1; {99253#false} is VALID [2022-02-21 04:23:38,210 INFO L290 TraceCheckUtils]: 44: Hoare triple {99253#false} assume !(0 == ~E_11~0); {99253#false} is VALID [2022-02-21 04:23:38,210 INFO L290 TraceCheckUtils]: 45: Hoare triple {99253#false} assume !(0 == ~E_12~0); {99253#false} is VALID [2022-02-21 04:23:38,210 INFO L290 TraceCheckUtils]: 46: Hoare triple {99253#false} assume !(0 == ~E_13~0); {99253#false} is VALID [2022-02-21 04:23:38,210 INFO L290 TraceCheckUtils]: 47: Hoare triple {99253#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {99253#false} is VALID [2022-02-21 04:23:38,210 INFO L290 TraceCheckUtils]: 48: Hoare triple {99253#false} assume !(1 == ~m_pc~0); {99253#false} is VALID [2022-02-21 04:23:38,210 INFO L290 TraceCheckUtils]: 49: Hoare triple {99253#false} is_master_triggered_~__retres1~0#1 := 0; {99253#false} is VALID [2022-02-21 04:23:38,210 INFO L290 TraceCheckUtils]: 50: Hoare triple {99253#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {99253#false} is VALID [2022-02-21 04:23:38,211 INFO L290 TraceCheckUtils]: 51: Hoare triple {99253#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {99253#false} is VALID [2022-02-21 04:23:38,211 INFO L290 TraceCheckUtils]: 52: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp~1#1); {99253#false} is VALID [2022-02-21 04:23:38,211 INFO L290 TraceCheckUtils]: 53: Hoare triple {99253#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {99253#false} is VALID [2022-02-21 04:23:38,211 INFO L290 TraceCheckUtils]: 54: Hoare triple {99253#false} assume 1 == ~t1_pc~0; {99253#false} is VALID [2022-02-21 04:23:38,211 INFO L290 TraceCheckUtils]: 55: Hoare triple {99253#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {99253#false} is VALID [2022-02-21 04:23:38,211 INFO L290 TraceCheckUtils]: 56: Hoare triple {99253#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {99253#false} is VALID [2022-02-21 04:23:38,211 INFO L290 TraceCheckUtils]: 57: Hoare triple {99253#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {99253#false} is VALID [2022-02-21 04:23:38,212 INFO L290 TraceCheckUtils]: 58: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___0~0#1); {99253#false} is VALID [2022-02-21 04:23:38,212 INFO L290 TraceCheckUtils]: 59: Hoare triple {99253#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {99253#false} is VALID [2022-02-21 04:23:38,212 INFO L290 TraceCheckUtils]: 60: Hoare triple {99253#false} assume 1 == ~t2_pc~0; {99253#false} is VALID [2022-02-21 04:23:38,212 INFO L290 TraceCheckUtils]: 61: Hoare triple {99253#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {99253#false} is VALID [2022-02-21 04:23:38,212 INFO L290 TraceCheckUtils]: 62: Hoare triple {99253#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {99253#false} is VALID [2022-02-21 04:23:38,212 INFO L290 TraceCheckUtils]: 63: Hoare triple {99253#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {99253#false} is VALID [2022-02-21 04:23:38,212 INFO L290 TraceCheckUtils]: 64: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___1~0#1); {99253#false} is VALID [2022-02-21 04:23:38,213 INFO L290 TraceCheckUtils]: 65: Hoare triple {99253#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {99253#false} is VALID [2022-02-21 04:23:38,213 INFO L290 TraceCheckUtils]: 66: Hoare triple {99253#false} assume !(1 == ~t3_pc~0); {99253#false} is VALID [2022-02-21 04:23:38,213 INFO L290 TraceCheckUtils]: 67: Hoare triple {99253#false} is_transmit3_triggered_~__retres1~3#1 := 0; {99253#false} is VALID [2022-02-21 04:23:38,213 INFO L290 TraceCheckUtils]: 68: Hoare triple {99253#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {99253#false} is VALID [2022-02-21 04:23:38,213 INFO L290 TraceCheckUtils]: 69: Hoare triple {99253#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {99253#false} is VALID [2022-02-21 04:23:38,213 INFO L290 TraceCheckUtils]: 70: Hoare triple {99253#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {99253#false} is VALID [2022-02-21 04:23:38,213 INFO L290 TraceCheckUtils]: 71: Hoare triple {99253#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {99253#false} is VALID [2022-02-21 04:23:38,213 INFO L290 TraceCheckUtils]: 72: Hoare triple {99253#false} assume 1 == ~t4_pc~0; {99253#false} is VALID [2022-02-21 04:23:38,214 INFO L290 TraceCheckUtils]: 73: Hoare triple {99253#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {99253#false} is VALID [2022-02-21 04:23:38,214 INFO L290 TraceCheckUtils]: 74: Hoare triple {99253#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {99253#false} is VALID [2022-02-21 04:23:38,214 INFO L290 TraceCheckUtils]: 75: Hoare triple {99253#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {99253#false} is VALID [2022-02-21 04:23:38,214 INFO L290 TraceCheckUtils]: 76: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___3~0#1); {99253#false} is VALID [2022-02-21 04:23:38,214 INFO L290 TraceCheckUtils]: 77: Hoare triple {99253#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {99253#false} is VALID [2022-02-21 04:23:38,214 INFO L290 TraceCheckUtils]: 78: Hoare triple {99253#false} assume !(1 == ~t5_pc~0); {99253#false} is VALID [2022-02-21 04:23:38,214 INFO L290 TraceCheckUtils]: 79: Hoare triple {99253#false} is_transmit5_triggered_~__retres1~5#1 := 0; {99253#false} is VALID [2022-02-21 04:23:38,215 INFO L290 TraceCheckUtils]: 80: Hoare triple {99253#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {99253#false} is VALID [2022-02-21 04:23:38,215 INFO L290 TraceCheckUtils]: 81: Hoare triple {99253#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {99253#false} is VALID [2022-02-21 04:23:38,215 INFO L290 TraceCheckUtils]: 82: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___4~0#1); {99253#false} is VALID [2022-02-21 04:23:38,215 INFO L290 TraceCheckUtils]: 83: Hoare triple {99253#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {99253#false} is VALID [2022-02-21 04:23:38,215 INFO L290 TraceCheckUtils]: 84: Hoare triple {99253#false} assume 1 == ~t6_pc~0; {99253#false} is VALID [2022-02-21 04:23:38,215 INFO L290 TraceCheckUtils]: 85: Hoare triple {99253#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {99253#false} is VALID [2022-02-21 04:23:38,215 INFO L290 TraceCheckUtils]: 86: Hoare triple {99253#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {99253#false} is VALID [2022-02-21 04:23:38,216 INFO L290 TraceCheckUtils]: 87: Hoare triple {99253#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {99253#false} is VALID [2022-02-21 04:23:38,216 INFO L290 TraceCheckUtils]: 88: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___5~0#1); {99253#false} is VALID [2022-02-21 04:23:38,216 INFO L290 TraceCheckUtils]: 89: Hoare triple {99253#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {99253#false} is VALID [2022-02-21 04:23:38,216 INFO L290 TraceCheckUtils]: 90: Hoare triple {99253#false} assume !(1 == ~t7_pc~0); {99253#false} is VALID [2022-02-21 04:23:38,216 INFO L290 TraceCheckUtils]: 91: Hoare triple {99253#false} is_transmit7_triggered_~__retres1~7#1 := 0; {99253#false} is VALID [2022-02-21 04:23:38,216 INFO L290 TraceCheckUtils]: 92: Hoare triple {99253#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {99253#false} is VALID [2022-02-21 04:23:38,216 INFO L290 TraceCheckUtils]: 93: Hoare triple {99253#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {99253#false} is VALID [2022-02-21 04:23:38,216 INFO L290 TraceCheckUtils]: 94: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___6~0#1); {99253#false} is VALID [2022-02-21 04:23:38,217 INFO L290 TraceCheckUtils]: 95: Hoare triple {99253#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {99253#false} is VALID [2022-02-21 04:23:38,217 INFO L290 TraceCheckUtils]: 96: Hoare triple {99253#false} assume 1 == ~t8_pc~0; {99253#false} is VALID [2022-02-21 04:23:38,217 INFO L290 TraceCheckUtils]: 97: Hoare triple {99253#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {99253#false} is VALID [2022-02-21 04:23:38,217 INFO L290 TraceCheckUtils]: 98: Hoare triple {99253#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {99253#false} is VALID [2022-02-21 04:23:38,217 INFO L290 TraceCheckUtils]: 99: Hoare triple {99253#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {99253#false} is VALID [2022-02-21 04:23:38,217 INFO L290 TraceCheckUtils]: 100: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___7~0#1); {99253#false} is VALID [2022-02-21 04:23:38,217 INFO L290 TraceCheckUtils]: 101: Hoare triple {99253#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {99253#false} is VALID [2022-02-21 04:23:38,218 INFO L290 TraceCheckUtils]: 102: Hoare triple {99253#false} assume 1 == ~t9_pc~0; {99253#false} is VALID [2022-02-21 04:23:38,218 INFO L290 TraceCheckUtils]: 103: Hoare triple {99253#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {99253#false} is VALID [2022-02-21 04:23:38,218 INFO L290 TraceCheckUtils]: 104: Hoare triple {99253#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {99253#false} is VALID [2022-02-21 04:23:38,218 INFO L290 TraceCheckUtils]: 105: Hoare triple {99253#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {99253#false} is VALID [2022-02-21 04:23:38,218 INFO L290 TraceCheckUtils]: 106: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___8~0#1); {99253#false} is VALID [2022-02-21 04:23:38,218 INFO L290 TraceCheckUtils]: 107: Hoare triple {99253#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {99253#false} is VALID [2022-02-21 04:23:38,218 INFO L290 TraceCheckUtils]: 108: Hoare triple {99253#false} assume !(1 == ~t10_pc~0); {99253#false} is VALID [2022-02-21 04:23:38,218 INFO L290 TraceCheckUtils]: 109: Hoare triple {99253#false} is_transmit10_triggered_~__retres1~10#1 := 0; {99253#false} is VALID [2022-02-21 04:23:38,219 INFO L290 TraceCheckUtils]: 110: Hoare triple {99253#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {99253#false} is VALID [2022-02-21 04:23:38,219 INFO L290 TraceCheckUtils]: 111: Hoare triple {99253#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {99253#false} is VALID [2022-02-21 04:23:38,219 INFO L290 TraceCheckUtils]: 112: Hoare triple {99253#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {99253#false} is VALID [2022-02-21 04:23:38,219 INFO L290 TraceCheckUtils]: 113: Hoare triple {99253#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {99253#false} is VALID [2022-02-21 04:23:38,219 INFO L290 TraceCheckUtils]: 114: Hoare triple {99253#false} assume 1 == ~t11_pc~0; {99253#false} is VALID [2022-02-21 04:23:38,219 INFO L290 TraceCheckUtils]: 115: Hoare triple {99253#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {99253#false} is VALID [2022-02-21 04:23:38,219 INFO L290 TraceCheckUtils]: 116: Hoare triple {99253#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {99253#false} is VALID [2022-02-21 04:23:38,220 INFO L290 TraceCheckUtils]: 117: Hoare triple {99253#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {99253#false} is VALID [2022-02-21 04:23:38,220 INFO L290 TraceCheckUtils]: 118: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___10~0#1); {99253#false} is VALID [2022-02-21 04:23:38,220 INFO L290 TraceCheckUtils]: 119: Hoare triple {99253#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {99253#false} is VALID [2022-02-21 04:23:38,220 INFO L290 TraceCheckUtils]: 120: Hoare triple {99253#false} assume !(1 == ~t12_pc~0); {99253#false} is VALID [2022-02-21 04:23:38,220 INFO L290 TraceCheckUtils]: 121: Hoare triple {99253#false} is_transmit12_triggered_~__retres1~12#1 := 0; {99253#false} is VALID [2022-02-21 04:23:38,220 INFO L290 TraceCheckUtils]: 122: Hoare triple {99253#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {99253#false} is VALID [2022-02-21 04:23:38,220 INFO L290 TraceCheckUtils]: 123: Hoare triple {99253#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {99253#false} is VALID [2022-02-21 04:23:38,221 INFO L290 TraceCheckUtils]: 124: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___11~0#1); {99253#false} is VALID [2022-02-21 04:23:38,221 INFO L290 TraceCheckUtils]: 125: Hoare triple {99253#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {99253#false} is VALID [2022-02-21 04:23:38,221 INFO L290 TraceCheckUtils]: 126: Hoare triple {99253#false} assume 1 == ~t13_pc~0; {99253#false} is VALID [2022-02-21 04:23:38,221 INFO L290 TraceCheckUtils]: 127: Hoare triple {99253#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {99253#false} is VALID [2022-02-21 04:23:38,221 INFO L290 TraceCheckUtils]: 128: Hoare triple {99253#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {99253#false} is VALID [2022-02-21 04:23:38,221 INFO L290 TraceCheckUtils]: 129: Hoare triple {99253#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {99253#false} is VALID [2022-02-21 04:23:38,221 INFO L290 TraceCheckUtils]: 130: Hoare triple {99253#false} assume !(0 != activate_threads_~tmp___12~0#1); {99253#false} is VALID [2022-02-21 04:23:38,222 INFO L290 TraceCheckUtils]: 131: Hoare triple {99253#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {99253#false} is VALID [2022-02-21 04:23:38,222 INFO L290 TraceCheckUtils]: 132: Hoare triple {99253#false} assume !(1 == ~M_E~0); {99253#false} is VALID [2022-02-21 04:23:38,222 INFO L290 TraceCheckUtils]: 133: Hoare triple {99253#false} assume !(1 == ~T1_E~0); {99253#false} is VALID [2022-02-21 04:23:38,222 INFO L290 TraceCheckUtils]: 134: Hoare triple {99253#false} assume !(1 == ~T2_E~0); {99253#false} is VALID [2022-02-21 04:23:38,222 INFO L290 TraceCheckUtils]: 135: Hoare triple {99253#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {99253#false} is VALID [2022-02-21 04:23:38,222 INFO L290 TraceCheckUtils]: 136: Hoare triple {99253#false} assume !(1 == ~T4_E~0); {99253#false} is VALID [2022-02-21 04:23:38,222 INFO L290 TraceCheckUtils]: 137: Hoare triple {99253#false} assume !(1 == ~T5_E~0); {99253#false} is VALID [2022-02-21 04:23:38,222 INFO L290 TraceCheckUtils]: 138: Hoare triple {99253#false} assume !(1 == ~T6_E~0); {99253#false} is VALID [2022-02-21 04:23:38,223 INFO L290 TraceCheckUtils]: 139: Hoare triple {99253#false} assume !(1 == ~T7_E~0); {99253#false} is VALID [2022-02-21 04:23:38,223 INFO L290 TraceCheckUtils]: 140: Hoare triple {99253#false} assume !(1 == ~T8_E~0); {99253#false} is VALID [2022-02-21 04:23:38,223 INFO L290 TraceCheckUtils]: 141: Hoare triple {99253#false} assume !(1 == ~T9_E~0); {99253#false} is VALID [2022-02-21 04:23:38,223 INFO L290 TraceCheckUtils]: 142: Hoare triple {99253#false} assume !(1 == ~T10_E~0); {99253#false} is VALID [2022-02-21 04:23:38,223 INFO L290 TraceCheckUtils]: 143: Hoare triple {99253#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {99253#false} is VALID [2022-02-21 04:23:38,223 INFO L290 TraceCheckUtils]: 144: Hoare triple {99253#false} assume !(1 == ~T12_E~0); {99253#false} is VALID [2022-02-21 04:23:38,223 INFO L290 TraceCheckUtils]: 145: Hoare triple {99253#false} assume !(1 == ~T13_E~0); {99253#false} is VALID [2022-02-21 04:23:38,224 INFO L290 TraceCheckUtils]: 146: Hoare triple {99253#false} assume !(1 == ~E_M~0); {99253#false} is VALID [2022-02-21 04:23:38,224 INFO L290 TraceCheckUtils]: 147: Hoare triple {99253#false} assume !(1 == ~E_1~0); {99253#false} is VALID [2022-02-21 04:23:38,224 INFO L290 TraceCheckUtils]: 148: Hoare triple {99253#false} assume !(1 == ~E_2~0); {99253#false} is VALID [2022-02-21 04:23:38,224 INFO L290 TraceCheckUtils]: 149: Hoare triple {99253#false} assume !(1 == ~E_3~0); {99253#false} is VALID [2022-02-21 04:23:38,224 INFO L290 TraceCheckUtils]: 150: Hoare triple {99253#false} assume !(1 == ~E_4~0); {99253#false} is VALID [2022-02-21 04:23:38,224 INFO L290 TraceCheckUtils]: 151: Hoare triple {99253#false} assume 1 == ~E_5~0;~E_5~0 := 2; {99253#false} is VALID [2022-02-21 04:23:38,224 INFO L290 TraceCheckUtils]: 152: Hoare triple {99253#false} assume !(1 == ~E_6~0); {99253#false} is VALID [2022-02-21 04:23:38,224 INFO L290 TraceCheckUtils]: 153: Hoare triple {99253#false} assume !(1 == ~E_7~0); {99253#false} is VALID [2022-02-21 04:23:38,225 INFO L290 TraceCheckUtils]: 154: Hoare triple {99253#false} assume !(1 == ~E_8~0); {99253#false} is VALID [2022-02-21 04:23:38,225 INFO L290 TraceCheckUtils]: 155: Hoare triple {99253#false} assume !(1 == ~E_9~0); {99253#false} is VALID [2022-02-21 04:23:38,225 INFO L290 TraceCheckUtils]: 156: Hoare triple {99253#false} assume !(1 == ~E_10~0); {99253#false} is VALID [2022-02-21 04:23:38,225 INFO L290 TraceCheckUtils]: 157: Hoare triple {99253#false} assume !(1 == ~E_11~0); {99253#false} is VALID [2022-02-21 04:23:38,225 INFO L290 TraceCheckUtils]: 158: Hoare triple {99253#false} assume !(1 == ~E_12~0); {99253#false} is VALID [2022-02-21 04:23:38,225 INFO L290 TraceCheckUtils]: 159: Hoare triple {99253#false} assume 1 == ~E_13~0;~E_13~0 := 2; {99253#false} is VALID [2022-02-21 04:23:38,225 INFO L290 TraceCheckUtils]: 160: Hoare triple {99253#false} assume { :end_inline_reset_delta_events } true; {99253#false} is VALID [2022-02-21 04:23:38,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:38,226 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:38,226 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973975971] [2022-02-21 04:23:38,226 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973975971] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:38,226 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:38,227 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:38,227 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [666401079] [2022-02-21 04:23:38,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:38,227 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:38,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:38,228 INFO L85 PathProgramCache]: Analyzing trace with hash -1196829277, now seen corresponding path program 1 times [2022-02-21 04:23:38,228 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:38,228 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028074370] [2022-02-21 04:23:38,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:38,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:38,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:38,259 INFO L290 TraceCheckUtils]: 0: Hoare triple {99255#true} assume !false; {99255#true} is VALID [2022-02-21 04:23:38,259 INFO L290 TraceCheckUtils]: 1: Hoare triple {99255#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {99255#true} is VALID [2022-02-21 04:23:38,259 INFO L290 TraceCheckUtils]: 2: Hoare triple {99255#true} assume !false; {99255#true} is VALID [2022-02-21 04:23:38,259 INFO L290 TraceCheckUtils]: 3: Hoare triple {99255#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {99255#true} is VALID [2022-02-21 04:23:38,259 INFO L290 TraceCheckUtils]: 4: Hoare triple {99255#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {99255#true} is VALID [2022-02-21 04:23:38,260 INFO L290 TraceCheckUtils]: 5: Hoare triple {99255#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {99255#true} is VALID [2022-02-21 04:23:38,260 INFO L290 TraceCheckUtils]: 6: Hoare triple {99255#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {99255#true} is VALID [2022-02-21 04:23:38,260 INFO L290 TraceCheckUtils]: 7: Hoare triple {99255#true} assume !(0 != eval_~tmp~0#1); {99255#true} is VALID [2022-02-21 04:23:38,260 INFO L290 TraceCheckUtils]: 8: Hoare triple {99255#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {99255#true} is VALID [2022-02-21 04:23:38,260 INFO L290 TraceCheckUtils]: 9: Hoare triple {99255#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {99255#true} is VALID [2022-02-21 04:23:38,260 INFO L290 TraceCheckUtils]: 10: Hoare triple {99255#true} assume 0 == ~M_E~0;~M_E~0 := 1; {99255#true} is VALID [2022-02-21 04:23:38,260 INFO L290 TraceCheckUtils]: 11: Hoare triple {99255#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {99255#true} is VALID [2022-02-21 04:23:38,261 INFO L290 TraceCheckUtils]: 12: Hoare triple {99255#true} assume !(0 == ~T2_E~0); {99255#true} is VALID [2022-02-21 04:23:38,261 INFO L290 TraceCheckUtils]: 13: Hoare triple {99255#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {99255#true} is VALID [2022-02-21 04:23:38,261 INFO L290 TraceCheckUtils]: 14: Hoare triple {99255#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {99255#true} is VALID [2022-02-21 04:23:38,261 INFO L290 TraceCheckUtils]: 15: Hoare triple {99255#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,262 INFO L290 TraceCheckUtils]: 16: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,262 INFO L290 TraceCheckUtils]: 17: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,262 INFO L290 TraceCheckUtils]: 18: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,263 INFO L290 TraceCheckUtils]: 19: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,263 INFO L290 TraceCheckUtils]: 20: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,263 INFO L290 TraceCheckUtils]: 21: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,264 INFO L290 TraceCheckUtils]: 22: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,264 INFO L290 TraceCheckUtils]: 23: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,265 INFO L290 TraceCheckUtils]: 24: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,265 INFO L290 TraceCheckUtils]: 25: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,265 INFO L290 TraceCheckUtils]: 26: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,266 INFO L290 TraceCheckUtils]: 27: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,266 INFO L290 TraceCheckUtils]: 28: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,266 INFO L290 TraceCheckUtils]: 29: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,267 INFO L290 TraceCheckUtils]: 30: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,267 INFO L290 TraceCheckUtils]: 31: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,267 INFO L290 TraceCheckUtils]: 32: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,268 INFO L290 TraceCheckUtils]: 33: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,268 INFO L290 TraceCheckUtils]: 34: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,269 INFO L290 TraceCheckUtils]: 35: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,269 INFO L290 TraceCheckUtils]: 36: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,269 INFO L290 TraceCheckUtils]: 37: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,270 INFO L290 TraceCheckUtils]: 38: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,270 INFO L290 TraceCheckUtils]: 39: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,270 INFO L290 TraceCheckUtils]: 40: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,271 INFO L290 TraceCheckUtils]: 41: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,271 INFO L290 TraceCheckUtils]: 42: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,271 INFO L290 TraceCheckUtils]: 43: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,272 INFO L290 TraceCheckUtils]: 44: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,272 INFO L290 TraceCheckUtils]: 45: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,272 INFO L290 TraceCheckUtils]: 46: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,273 INFO L290 TraceCheckUtils]: 47: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,273 INFO L290 TraceCheckUtils]: 48: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,274 INFO L290 TraceCheckUtils]: 49: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,274 INFO L290 TraceCheckUtils]: 50: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,274 INFO L290 TraceCheckUtils]: 51: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,275 INFO L290 TraceCheckUtils]: 52: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,275 INFO L290 TraceCheckUtils]: 53: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,275 INFO L290 TraceCheckUtils]: 54: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,276 INFO L290 TraceCheckUtils]: 55: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,276 INFO L290 TraceCheckUtils]: 56: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,276 INFO L290 TraceCheckUtils]: 57: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,277 INFO L290 TraceCheckUtils]: 58: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,277 INFO L290 TraceCheckUtils]: 59: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,278 INFO L290 TraceCheckUtils]: 60: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,278 INFO L290 TraceCheckUtils]: 61: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,278 INFO L290 TraceCheckUtils]: 62: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,279 INFO L290 TraceCheckUtils]: 63: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,279 INFO L290 TraceCheckUtils]: 64: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,279 INFO L290 TraceCheckUtils]: 65: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,280 INFO L290 TraceCheckUtils]: 66: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,280 INFO L290 TraceCheckUtils]: 67: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,280 INFO L290 TraceCheckUtils]: 68: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,281 INFO L290 TraceCheckUtils]: 69: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,281 INFO L290 TraceCheckUtils]: 70: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,281 INFO L290 TraceCheckUtils]: 71: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,282 INFO L290 TraceCheckUtils]: 72: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,282 INFO L290 TraceCheckUtils]: 73: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,283 INFO L290 TraceCheckUtils]: 74: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,283 INFO L290 TraceCheckUtils]: 75: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,283 INFO L290 TraceCheckUtils]: 76: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,284 INFO L290 TraceCheckUtils]: 77: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,284 INFO L290 TraceCheckUtils]: 78: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,284 INFO L290 TraceCheckUtils]: 79: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,285 INFO L290 TraceCheckUtils]: 80: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,285 INFO L290 TraceCheckUtils]: 81: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,285 INFO L290 TraceCheckUtils]: 82: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,286 INFO L290 TraceCheckUtils]: 83: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,286 INFO L290 TraceCheckUtils]: 84: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,286 INFO L290 TraceCheckUtils]: 85: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,287 INFO L290 TraceCheckUtils]: 86: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,287 INFO L290 TraceCheckUtils]: 87: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,288 INFO L290 TraceCheckUtils]: 88: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,288 INFO L290 TraceCheckUtils]: 89: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,288 INFO L290 TraceCheckUtils]: 90: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,289 INFO L290 TraceCheckUtils]: 91: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,289 INFO L290 TraceCheckUtils]: 92: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,289 INFO L290 TraceCheckUtils]: 93: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,290 INFO L290 TraceCheckUtils]: 94: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,290 INFO L290 TraceCheckUtils]: 95: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,290 INFO L290 TraceCheckUtils]: 96: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,291 INFO L290 TraceCheckUtils]: 97: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,291 INFO L290 TraceCheckUtils]: 98: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,292 INFO L290 TraceCheckUtils]: 99: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,292 INFO L290 TraceCheckUtils]: 100: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,292 INFO L290 TraceCheckUtils]: 101: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,293 INFO L290 TraceCheckUtils]: 102: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,293 INFO L290 TraceCheckUtils]: 103: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,293 INFO L290 TraceCheckUtils]: 104: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,294 INFO L290 TraceCheckUtils]: 105: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,294 INFO L290 TraceCheckUtils]: 106: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,294 INFO L290 TraceCheckUtils]: 107: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,295 INFO L290 TraceCheckUtils]: 108: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,295 INFO L290 TraceCheckUtils]: 109: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,295 INFO L290 TraceCheckUtils]: 110: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,296 INFO L290 TraceCheckUtils]: 111: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t12_pc~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,296 INFO L290 TraceCheckUtils]: 112: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,297 INFO L290 TraceCheckUtils]: 113: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,297 INFO L290 TraceCheckUtils]: 114: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,297 INFO L290 TraceCheckUtils]: 115: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,298 INFO L290 TraceCheckUtils]: 116: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,298 INFO L290 TraceCheckUtils]: 117: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,298 INFO L290 TraceCheckUtils]: 118: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,299 INFO L290 TraceCheckUtils]: 119: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,299 INFO L290 TraceCheckUtils]: 120: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,299 INFO L290 TraceCheckUtils]: 121: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,300 INFO L290 TraceCheckUtils]: 122: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,300 INFO L290 TraceCheckUtils]: 123: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,301 INFO L290 TraceCheckUtils]: 124: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,301 INFO L290 TraceCheckUtils]: 125: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,301 INFO L290 TraceCheckUtils]: 126: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,302 INFO L290 TraceCheckUtils]: 127: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {99257#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:38,302 INFO L290 TraceCheckUtils]: 128: Hoare triple {99257#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {99256#false} is VALID [2022-02-21 04:23:38,302 INFO L290 TraceCheckUtils]: 129: Hoare triple {99256#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,302 INFO L290 TraceCheckUtils]: 130: Hoare triple {99256#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,302 INFO L290 TraceCheckUtils]: 131: Hoare triple {99256#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,302 INFO L290 TraceCheckUtils]: 132: Hoare triple {99256#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,303 INFO L290 TraceCheckUtils]: 133: Hoare triple {99256#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,303 INFO L290 TraceCheckUtils]: 134: Hoare triple {99256#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,303 INFO L290 TraceCheckUtils]: 135: Hoare triple {99256#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,303 INFO L290 TraceCheckUtils]: 136: Hoare triple {99256#false} assume !(1 == ~T13_E~0); {99256#false} is VALID [2022-02-21 04:23:38,303 INFO L290 TraceCheckUtils]: 137: Hoare triple {99256#false} assume 1 == ~E_M~0;~E_M~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,303 INFO L290 TraceCheckUtils]: 138: Hoare triple {99256#false} assume 1 == ~E_1~0;~E_1~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,303 INFO L290 TraceCheckUtils]: 139: Hoare triple {99256#false} assume 1 == ~E_2~0;~E_2~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,304 INFO L290 TraceCheckUtils]: 140: Hoare triple {99256#false} assume 1 == ~E_3~0;~E_3~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,304 INFO L290 TraceCheckUtils]: 141: Hoare triple {99256#false} assume 1 == ~E_4~0;~E_4~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,304 INFO L290 TraceCheckUtils]: 142: Hoare triple {99256#false} assume 1 == ~E_5~0;~E_5~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,304 INFO L290 TraceCheckUtils]: 143: Hoare triple {99256#false} assume 1 == ~E_6~0;~E_6~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,304 INFO L290 TraceCheckUtils]: 144: Hoare triple {99256#false} assume !(1 == ~E_7~0); {99256#false} is VALID [2022-02-21 04:23:38,304 INFO L290 TraceCheckUtils]: 145: Hoare triple {99256#false} assume 1 == ~E_8~0;~E_8~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,304 INFO L290 TraceCheckUtils]: 146: Hoare triple {99256#false} assume 1 == ~E_9~0;~E_9~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,305 INFO L290 TraceCheckUtils]: 147: Hoare triple {99256#false} assume 1 == ~E_10~0;~E_10~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,305 INFO L290 TraceCheckUtils]: 148: Hoare triple {99256#false} assume 1 == ~E_11~0;~E_11~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,305 INFO L290 TraceCheckUtils]: 149: Hoare triple {99256#false} assume 1 == ~E_12~0;~E_12~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,305 INFO L290 TraceCheckUtils]: 150: Hoare triple {99256#false} assume 1 == ~E_13~0;~E_13~0 := 2; {99256#false} is VALID [2022-02-21 04:23:38,305 INFO L290 TraceCheckUtils]: 151: Hoare triple {99256#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {99256#false} is VALID [2022-02-21 04:23:38,305 INFO L290 TraceCheckUtils]: 152: Hoare triple {99256#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {99256#false} is VALID [2022-02-21 04:23:38,305 INFO L290 TraceCheckUtils]: 153: Hoare triple {99256#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {99256#false} is VALID [2022-02-21 04:23:38,305 INFO L290 TraceCheckUtils]: 154: Hoare triple {99256#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {99256#false} is VALID [2022-02-21 04:23:38,306 INFO L290 TraceCheckUtils]: 155: Hoare triple {99256#false} assume !(0 == start_simulation_~tmp~3#1); {99256#false} is VALID [2022-02-21 04:23:38,306 INFO L290 TraceCheckUtils]: 156: Hoare triple {99256#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {99256#false} is VALID [2022-02-21 04:23:38,306 INFO L290 TraceCheckUtils]: 157: Hoare triple {99256#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {99256#false} is VALID [2022-02-21 04:23:38,306 INFO L290 TraceCheckUtils]: 158: Hoare triple {99256#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {99256#false} is VALID [2022-02-21 04:23:38,306 INFO L290 TraceCheckUtils]: 159: Hoare triple {99256#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {99256#false} is VALID [2022-02-21 04:23:38,306 INFO L290 TraceCheckUtils]: 160: Hoare triple {99256#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {99256#false} is VALID [2022-02-21 04:23:38,306 INFO L290 TraceCheckUtils]: 161: Hoare triple {99256#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {99256#false} is VALID [2022-02-21 04:23:38,307 INFO L290 TraceCheckUtils]: 162: Hoare triple {99256#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {99256#false} is VALID [2022-02-21 04:23:38,307 INFO L290 TraceCheckUtils]: 163: Hoare triple {99256#false} assume !(0 != start_simulation_~tmp___0~1#1); {99256#false} is VALID [2022-02-21 04:23:38,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:38,307 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:38,308 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028074370] [2022-02-21 04:23:38,308 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1028074370] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:38,308 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:38,308 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:38,308 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1564458387] [2022-02-21 04:23:38,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:38,309 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:38,309 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:38,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:38,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:38,310 INFO L87 Difference]: Start difference. First operand 2023 states and 2985 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:39,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:39,704 INFO L93 Difference]: Finished difference Result 2023 states and 2984 transitions. [2022-02-21 04:23:39,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:39,704 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:39,797 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:39,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2984 transitions. [2022-02-21 04:23:39,883 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:39,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2984 transitions. [2022-02-21 04:23:39,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-02-21 04:23:39,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-02-21 04:23:39,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2984 transitions. [2022-02-21 04:23:39,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:39,971 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2022-02-21 04:23:39,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2984 transitions. [2022-02-21 04:23:39,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-02-21 04:23:39,985 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:39,987 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2023 states and 2984 transitions. Second operand has 2023 states, 2023 states have (on average 1.4750370736529905) internal successors, (2984), 2022 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:39,988 INFO L74 IsIncluded]: Start isIncluded. First operand 2023 states and 2984 transitions. Second operand has 2023 states, 2023 states have (on average 1.4750370736529905) internal successors, (2984), 2022 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:39,989 INFO L87 Difference]: Start difference. First operand 2023 states and 2984 transitions. Second operand has 2023 states, 2023 states have (on average 1.4750370736529905) internal successors, (2984), 2022 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:40,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:40,071 INFO L93 Difference]: Finished difference Result 2023 states and 2984 transitions. [2022-02-21 04:23:40,072 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2984 transitions. [2022-02-21 04:23:40,073 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:40,073 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:40,075 INFO L74 IsIncluded]: Start isIncluded. First operand has 2023 states, 2023 states have (on average 1.4750370736529905) internal successors, (2984), 2022 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2984 transitions. [2022-02-21 04:23:40,076 INFO L87 Difference]: Start difference. First operand has 2023 states, 2023 states have (on average 1.4750370736529905) internal successors, (2984), 2022 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2023 states and 2984 transitions. [2022-02-21 04:23:40,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:40,158 INFO L93 Difference]: Finished difference Result 2023 states and 2984 transitions. [2022-02-21 04:23:40,158 INFO L276 IsEmpty]: Start isEmpty. Operand 2023 states and 2984 transitions. [2022-02-21 04:23:40,160 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:40,160 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:40,160 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:40,160 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:40,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4750370736529905) internal successors, (2984), 2022 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:40,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2984 transitions. [2022-02-21 04:23:40,246 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2022-02-21 04:23:40,246 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2022-02-21 04:23:40,246 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:23:40,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2984 transitions. [2022-02-21 04:23:40,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-02-21 04:23:40,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:40,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:40,251 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:40,251 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:40,252 INFO L791 eck$LassoCheckResult]: Stem: 102208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 102209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 103207#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 103208#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103293#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 102672#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102141#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102142#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102958#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102959#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 103059#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 103060#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 101913#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 101914#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 103089#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 102449#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 102450#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 103010#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 102351#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102352#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 103294#L1291-2 assume !(0 == ~T1_E~0); 103292#L1296-1 assume !(0 == ~T2_E~0); 102508#L1301-1 assume !(0 == ~T3_E~0); 102509#L1306-1 assume !(0 == ~T4_E~0); 103018#L1311-1 assume !(0 == ~T5_E~0); 101756#L1316-1 assume !(0 == ~T6_E~0); 101757#L1321-1 assume !(0 == ~T7_E~0); 102521#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 101584#L1331-1 assume !(0 == ~T9_E~0); 101283#L1336-1 assume !(0 == ~T10_E~0); 101284#L1341-1 assume !(0 == ~T11_E~0); 101364#L1346-1 assume !(0 == ~T12_E~0); 101365#L1351-1 assume !(0 == ~T13_E~0); 101705#L1356-1 assume !(0 == ~E_M~0); 101706#L1361-1 assume !(0 == ~E_1~0); 103233#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 101746#L1371-1 assume !(0 == ~E_3~0); 101747#L1376-1 assume !(0 == ~E_4~0); 102568#L1381-1 assume !(0 == ~E_5~0); 102569#L1386-1 assume !(0 == ~E_6~0); 103263#L1391-1 assume !(0 == ~E_7~0); 103281#L1396-1 assume !(0 == ~E_8~0); 102481#L1401-1 assume !(0 == ~E_9~0); 102482#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 102760#L1411-1 assume !(0 == ~E_11~0); 102761#L1416-1 assume !(0 == ~E_12~0); 102393#L1421-1 assume !(0 == ~E_13~0); 101936#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101937#L640 assume !(1 == ~m_pc~0); 102446#L640-2 is_master_triggered_~__retres1~0#1 := 0; 102445#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102537#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102431#L1603 assume !(0 != activate_threads_~tmp~1#1); 102432#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102066#L659 assume 1 == ~t1_pc~0; 102067#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 102172#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103118#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102192#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 102193#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102206#L678 assume 1 == ~t2_pc~0; 103160#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 103161#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103260#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102304#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 102305#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102426#L697 assume !(1 == ~t3_pc~0); 102427#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102549#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102357#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 102336#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 102337#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103197#L716 assume 1 == ~t4_pc~0; 103183#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 102047#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102048#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 101547#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 101548#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102839#L735 assume !(1 == ~t5_pc~0); 101508#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 101509#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101959#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 102866#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 102502#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102503#L754 assume 1 == ~t6_pc~0; 102256#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 102154#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102155#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 102128#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 102129#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 102949#L773 assume !(1 == ~t7_pc~0); 101709#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 101708#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102538#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 102510#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 102511#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102558#L792 assume 1 == ~t8_pc~0; 102731#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 103063#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 102552#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 102505#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 102429#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102430#L811 assume 1 == ~t9_pc~0; 102634#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 103100#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 102976#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 102630#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 102442#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 102443#L830 assume !(1 == ~t10_pc~0); 102164#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 101688#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 101381#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 101382#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101669#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 102967#L849 assume 1 == ~t11_pc~0; 102968#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 101484#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 101485#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 102074#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 102873#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 102874#L868 assume !(1 == ~t12_pc~0); 102289#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 102288#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 102083#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 102084#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 101720#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 101721#L887 assume 1 == ~t13_pc~0; 102888#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 102330#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 102331#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 102767#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 101424#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101425#L1439 assume !(1 == ~M_E~0); 102498#L1439-2 assume !(1 == ~T1_E~0); 101596#L1444-1 assume !(1 == ~T2_E~0); 101597#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102070#L1454-1 assume !(1 == ~T4_E~0); 102071#L1459-1 assume !(1 == ~T5_E~0); 102627#L1464-1 assume !(1 == ~T6_E~0); 102628#L1469-1 assume !(1 == ~T7_E~0); 102700#L1474-1 assume !(1 == ~T8_E~0); 102394#L1479-1 assume !(1 == ~T9_E~0); 102395#L1484-1 assume !(1 == ~T10_E~0); 102631#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 102277#L1494-1 assume !(1 == ~T12_E~0); 102278#L1499-1 assume !(1 == ~T13_E~0); 102470#L1504-1 assume !(1 == ~E_M~0); 102471#L1509-1 assume !(1 == ~E_1~0); 103046#L1514-1 assume !(1 == ~E_2~0); 102733#L1519-1 assume !(1 == ~E_3~0); 102734#L1524-1 assume !(1 == ~E_4~0); 103246#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 103247#L1534-1 assume !(1 == ~E_6~0); 101417#L1539-1 assume !(1 == ~E_7~0); 101418#L1544-1 assume !(1 == ~E_8~0); 101832#L1549-1 assume !(1 == ~E_9~0); 103221#L1554-1 assume !(1 == ~E_10~0); 103217#L1559-1 assume !(1 == ~E_11~0); 103084#L1564-1 assume !(1 == ~E_12~0); 103085#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 103242#L1574-1 assume { :end_inline_reset_delta_events } true; 101594#L1940-2 [2022-02-21 04:23:40,252 INFO L793 eck$LassoCheckResult]: Loop: 101594#L1940-2 assume !false; 101595#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 101877#L1266 assume !false; 102896#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 102125#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101858#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 102249#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 102250#L1079 assume !(0 != eval_~tmp~0#1); 102211#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 102212#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 102816#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 102701#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 102702#L1296-3 assume !(0 == ~T2_E~0); 103274#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103228#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 102359#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 101635#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 101636#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 101736#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 102493#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 102742#L1336-3 assume !(0 == ~T10_E~0); 102743#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 102063#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 102043#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 101988#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 101989#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 102550#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 101339#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 101340#L1376-3 assume !(0 == ~E_4~0); 103069#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102929#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 102930#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 103092#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103093#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 101702#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 101556#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 101557#L1416-3 assume !(0 == ~E_12~0); 102218#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 102219#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102326#L640-45 assume !(1 == ~m_pc~0); 102327#L640-47 is_master_triggered_~__retres1~0#1 := 0; 101793#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101794#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101333#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 101334#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101432#L659-45 assume 1 == ~t1_pc~0; 101433#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 101872#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102831#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102832#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 102853#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102854#L678-45 assume 1 == ~t2_pc~0; 102797#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 102332#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102333#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102485#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103110#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103227#L697-45 assume !(1 == ~t3_pc~0); 102592#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 102591#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103179#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 102749#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 102750#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102780#L716-45 assume 1 == ~t4_pc~0; 102411#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 102412#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102962#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 102417#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 102418#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102080#L735-45 assume 1 == ~t5_pc~0; 102081#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 102624#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103186#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 103187#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 103245#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103240#L754-45 assume 1 == ~t6_pc~0; 102572#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 102573#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102002#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 102003#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 102576#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 102308#L773-45 assume 1 == ~t7_pc~0; 102309#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 101866#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102786#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 103068#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 102314#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 101984#L792-45 assume 1 == ~t8_pc~0; 101985#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 103014#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101587#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 101446#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101447#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 101942#L811-45 assume 1 == ~t9_pc~0; 101731#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 101733#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 102941#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 102776#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 102385#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 102177#L830-45 assume 1 == ~t10_pc~0; 102178#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 101375#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 102497#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 101607#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101608#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 101353#L849-45 assume 1 == ~t11_pc~0; 101355#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 101813#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 101444#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 101341#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 101342#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 101600#L868-45 assume 1 == ~t12_pc~0; 101601#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 101540#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 101541#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 102879#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 103130#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 103131#L887-45 assume 1 == ~t13_pc~0; 102961#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 101610#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 102892#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 103237#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 101572#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101573#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 102880#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101592#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 101593#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101750#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 102681#L1459-3 assume !(1 == ~T5_E~0); 102682#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103133#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 103072#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 103073#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 103134#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 102366#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 102367#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 103003#L1499-3 assume !(1 == ~T13_E~0); 102642#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 102643#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 103081#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103111#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 102285#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 102286#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 103153#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 102553#L1539-3 assume !(1 == ~E_7~0); 102029#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 102030#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 102525#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 101646#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 101647#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 102781#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 102782#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 101523#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101294#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 101569#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 101530#L1959 assume !(0 == start_simulation_~tmp~3#1); 101532#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 101564#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101514#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 102823#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 102944#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103151#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103165#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 103166#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 101594#L1940-2 [2022-02-21 04:23:40,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:40,253 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2022-02-21 04:23:40,253 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:40,253 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639180015] [2022-02-21 04:23:40,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:40,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:40,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:40,292 INFO L290 TraceCheckUtils]: 0: Hoare triple {107353#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,293 INFO L290 TraceCheckUtils]: 1: Hoare triple {107355#(= ~M_E~0 2)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,294 INFO L290 TraceCheckUtils]: 2: Hoare triple {107355#(= ~M_E~0 2)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,294 INFO L290 TraceCheckUtils]: 3: Hoare triple {107355#(= ~M_E~0 2)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,294 INFO L290 TraceCheckUtils]: 4: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~m_i~0;~m_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,295 INFO L290 TraceCheckUtils]: 5: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,295 INFO L290 TraceCheckUtils]: 6: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,296 INFO L290 TraceCheckUtils]: 7: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,296 INFO L290 TraceCheckUtils]: 8: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,296 INFO L290 TraceCheckUtils]: 9: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,297 INFO L290 TraceCheckUtils]: 10: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,297 INFO L290 TraceCheckUtils]: 11: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,297 INFO L290 TraceCheckUtils]: 12: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,298 INFO L290 TraceCheckUtils]: 13: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,298 INFO L290 TraceCheckUtils]: 14: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,299 INFO L290 TraceCheckUtils]: 15: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,299 INFO L290 TraceCheckUtils]: 16: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,299 INFO L290 TraceCheckUtils]: 17: Hoare triple {107355#(= ~M_E~0 2)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,300 INFO L290 TraceCheckUtils]: 18: Hoare triple {107355#(= ~M_E~0 2)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {107355#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:40,300 INFO L290 TraceCheckUtils]: 19: Hoare triple {107355#(= ~M_E~0 2)} assume 0 == ~M_E~0;~M_E~0 := 1; {107354#false} is VALID [2022-02-21 04:23:40,300 INFO L290 TraceCheckUtils]: 20: Hoare triple {107354#false} assume !(0 == ~T1_E~0); {107354#false} is VALID [2022-02-21 04:23:40,300 INFO L290 TraceCheckUtils]: 21: Hoare triple {107354#false} assume !(0 == ~T2_E~0); {107354#false} is VALID [2022-02-21 04:23:40,301 INFO L290 TraceCheckUtils]: 22: Hoare triple {107354#false} assume !(0 == ~T3_E~0); {107354#false} is VALID [2022-02-21 04:23:40,301 INFO L290 TraceCheckUtils]: 23: Hoare triple {107354#false} assume !(0 == ~T4_E~0); {107354#false} is VALID [2022-02-21 04:23:40,301 INFO L290 TraceCheckUtils]: 24: Hoare triple {107354#false} assume !(0 == ~T5_E~0); {107354#false} is VALID [2022-02-21 04:23:40,301 INFO L290 TraceCheckUtils]: 25: Hoare triple {107354#false} assume !(0 == ~T6_E~0); {107354#false} is VALID [2022-02-21 04:23:40,301 INFO L290 TraceCheckUtils]: 26: Hoare triple {107354#false} assume !(0 == ~T7_E~0); {107354#false} is VALID [2022-02-21 04:23:40,301 INFO L290 TraceCheckUtils]: 27: Hoare triple {107354#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {107354#false} is VALID [2022-02-21 04:23:40,301 INFO L290 TraceCheckUtils]: 28: Hoare triple {107354#false} assume !(0 == ~T9_E~0); {107354#false} is VALID [2022-02-21 04:23:40,302 INFO L290 TraceCheckUtils]: 29: Hoare triple {107354#false} assume !(0 == ~T10_E~0); {107354#false} is VALID [2022-02-21 04:23:40,302 INFO L290 TraceCheckUtils]: 30: Hoare triple {107354#false} assume !(0 == ~T11_E~0); {107354#false} is VALID [2022-02-21 04:23:40,302 INFO L290 TraceCheckUtils]: 31: Hoare triple {107354#false} assume !(0 == ~T12_E~0); {107354#false} is VALID [2022-02-21 04:23:40,302 INFO L290 TraceCheckUtils]: 32: Hoare triple {107354#false} assume !(0 == ~T13_E~0); {107354#false} is VALID [2022-02-21 04:23:40,302 INFO L290 TraceCheckUtils]: 33: Hoare triple {107354#false} assume !(0 == ~E_M~0); {107354#false} is VALID [2022-02-21 04:23:40,302 INFO L290 TraceCheckUtils]: 34: Hoare triple {107354#false} assume !(0 == ~E_1~0); {107354#false} is VALID [2022-02-21 04:23:40,302 INFO L290 TraceCheckUtils]: 35: Hoare triple {107354#false} assume 0 == ~E_2~0;~E_2~0 := 1; {107354#false} is VALID [2022-02-21 04:23:40,304 INFO L290 TraceCheckUtils]: 36: Hoare triple {107354#false} assume !(0 == ~E_3~0); {107354#false} is VALID [2022-02-21 04:23:40,304 INFO L290 TraceCheckUtils]: 37: Hoare triple {107354#false} assume !(0 == ~E_4~0); {107354#false} is VALID [2022-02-21 04:23:40,304 INFO L290 TraceCheckUtils]: 38: Hoare triple {107354#false} assume !(0 == ~E_5~0); {107354#false} is VALID [2022-02-21 04:23:40,305 INFO L290 TraceCheckUtils]: 39: Hoare triple {107354#false} assume !(0 == ~E_6~0); {107354#false} is VALID [2022-02-21 04:23:40,305 INFO L290 TraceCheckUtils]: 40: Hoare triple {107354#false} assume !(0 == ~E_7~0); {107354#false} is VALID [2022-02-21 04:23:40,305 INFO L290 TraceCheckUtils]: 41: Hoare triple {107354#false} assume !(0 == ~E_8~0); {107354#false} is VALID [2022-02-21 04:23:40,305 INFO L290 TraceCheckUtils]: 42: Hoare triple {107354#false} assume !(0 == ~E_9~0); {107354#false} is VALID [2022-02-21 04:23:40,305 INFO L290 TraceCheckUtils]: 43: Hoare triple {107354#false} assume 0 == ~E_10~0;~E_10~0 := 1; {107354#false} is VALID [2022-02-21 04:23:40,305 INFO L290 TraceCheckUtils]: 44: Hoare triple {107354#false} assume !(0 == ~E_11~0); {107354#false} is VALID [2022-02-21 04:23:40,305 INFO L290 TraceCheckUtils]: 45: Hoare triple {107354#false} assume !(0 == ~E_12~0); {107354#false} is VALID [2022-02-21 04:23:40,306 INFO L290 TraceCheckUtils]: 46: Hoare triple {107354#false} assume !(0 == ~E_13~0); {107354#false} is VALID [2022-02-21 04:23:40,306 INFO L290 TraceCheckUtils]: 47: Hoare triple {107354#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {107354#false} is VALID [2022-02-21 04:23:40,306 INFO L290 TraceCheckUtils]: 48: Hoare triple {107354#false} assume !(1 == ~m_pc~0); {107354#false} is VALID [2022-02-21 04:23:40,306 INFO L290 TraceCheckUtils]: 49: Hoare triple {107354#false} is_master_triggered_~__retres1~0#1 := 0; {107354#false} is VALID [2022-02-21 04:23:40,306 INFO L290 TraceCheckUtils]: 50: Hoare triple {107354#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {107354#false} is VALID [2022-02-21 04:23:40,306 INFO L290 TraceCheckUtils]: 51: Hoare triple {107354#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {107354#false} is VALID [2022-02-21 04:23:40,306 INFO L290 TraceCheckUtils]: 52: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp~1#1); {107354#false} is VALID [2022-02-21 04:23:40,306 INFO L290 TraceCheckUtils]: 53: Hoare triple {107354#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {107354#false} is VALID [2022-02-21 04:23:40,306 INFO L290 TraceCheckUtils]: 54: Hoare triple {107354#false} assume 1 == ~t1_pc~0; {107354#false} is VALID [2022-02-21 04:23:40,306 INFO L290 TraceCheckUtils]: 55: Hoare triple {107354#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {107354#false} is VALID [2022-02-21 04:23:40,307 INFO L290 TraceCheckUtils]: 56: Hoare triple {107354#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {107354#false} is VALID [2022-02-21 04:23:40,307 INFO L290 TraceCheckUtils]: 57: Hoare triple {107354#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {107354#false} is VALID [2022-02-21 04:23:40,307 INFO L290 TraceCheckUtils]: 58: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___0~0#1); {107354#false} is VALID [2022-02-21 04:23:40,307 INFO L290 TraceCheckUtils]: 59: Hoare triple {107354#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {107354#false} is VALID [2022-02-21 04:23:40,307 INFO L290 TraceCheckUtils]: 60: Hoare triple {107354#false} assume 1 == ~t2_pc~0; {107354#false} is VALID [2022-02-21 04:23:40,307 INFO L290 TraceCheckUtils]: 61: Hoare triple {107354#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {107354#false} is VALID [2022-02-21 04:23:40,307 INFO L290 TraceCheckUtils]: 62: Hoare triple {107354#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {107354#false} is VALID [2022-02-21 04:23:40,308 INFO L290 TraceCheckUtils]: 63: Hoare triple {107354#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {107354#false} is VALID [2022-02-21 04:23:40,308 INFO L290 TraceCheckUtils]: 64: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___1~0#1); {107354#false} is VALID [2022-02-21 04:23:40,308 INFO L290 TraceCheckUtils]: 65: Hoare triple {107354#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {107354#false} is VALID [2022-02-21 04:23:40,308 INFO L290 TraceCheckUtils]: 66: Hoare triple {107354#false} assume !(1 == ~t3_pc~0); {107354#false} is VALID [2022-02-21 04:23:40,308 INFO L290 TraceCheckUtils]: 67: Hoare triple {107354#false} is_transmit3_triggered_~__retres1~3#1 := 0; {107354#false} is VALID [2022-02-21 04:23:40,308 INFO L290 TraceCheckUtils]: 68: Hoare triple {107354#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {107354#false} is VALID [2022-02-21 04:23:40,308 INFO L290 TraceCheckUtils]: 69: Hoare triple {107354#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {107354#false} is VALID [2022-02-21 04:23:40,309 INFO L290 TraceCheckUtils]: 70: Hoare triple {107354#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {107354#false} is VALID [2022-02-21 04:23:40,309 INFO L290 TraceCheckUtils]: 71: Hoare triple {107354#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {107354#false} is VALID [2022-02-21 04:23:40,309 INFO L290 TraceCheckUtils]: 72: Hoare triple {107354#false} assume 1 == ~t4_pc~0; {107354#false} is VALID [2022-02-21 04:23:40,309 INFO L290 TraceCheckUtils]: 73: Hoare triple {107354#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {107354#false} is VALID [2022-02-21 04:23:40,309 INFO L290 TraceCheckUtils]: 74: Hoare triple {107354#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {107354#false} is VALID [2022-02-21 04:23:40,309 INFO L290 TraceCheckUtils]: 75: Hoare triple {107354#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {107354#false} is VALID [2022-02-21 04:23:40,309 INFO L290 TraceCheckUtils]: 76: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___3~0#1); {107354#false} is VALID [2022-02-21 04:23:40,309 INFO L290 TraceCheckUtils]: 77: Hoare triple {107354#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {107354#false} is VALID [2022-02-21 04:23:40,309 INFO L290 TraceCheckUtils]: 78: Hoare triple {107354#false} assume !(1 == ~t5_pc~0); {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 79: Hoare triple {107354#false} is_transmit5_triggered_~__retres1~5#1 := 0; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 80: Hoare triple {107354#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 81: Hoare triple {107354#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 82: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___4~0#1); {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 83: Hoare triple {107354#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 84: Hoare triple {107354#false} assume 1 == ~t6_pc~0; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 85: Hoare triple {107354#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 86: Hoare triple {107354#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 87: Hoare triple {107354#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 88: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___5~0#1); {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 89: Hoare triple {107354#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 90: Hoare triple {107354#false} assume !(1 == ~t7_pc~0); {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 91: Hoare triple {107354#false} is_transmit7_triggered_~__retres1~7#1 := 0; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 92: Hoare triple {107354#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 93: Hoare triple {107354#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {107354#false} is VALID [2022-02-21 04:23:40,310 INFO L290 TraceCheckUtils]: 94: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___6~0#1); {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 95: Hoare triple {107354#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 96: Hoare triple {107354#false} assume 1 == ~t8_pc~0; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 97: Hoare triple {107354#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 98: Hoare triple {107354#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 99: Hoare triple {107354#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 100: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___7~0#1); {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 101: Hoare triple {107354#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 102: Hoare triple {107354#false} assume 1 == ~t9_pc~0; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 103: Hoare triple {107354#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 104: Hoare triple {107354#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 105: Hoare triple {107354#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 106: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___8~0#1); {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 107: Hoare triple {107354#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 108: Hoare triple {107354#false} assume !(1 == ~t10_pc~0); {107354#false} is VALID [2022-02-21 04:23:40,311 INFO L290 TraceCheckUtils]: 109: Hoare triple {107354#false} is_transmit10_triggered_~__retres1~10#1 := 0; {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 110: Hoare triple {107354#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 111: Hoare triple {107354#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 112: Hoare triple {107354#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 113: Hoare triple {107354#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 114: Hoare triple {107354#false} assume 1 == ~t11_pc~0; {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 115: Hoare triple {107354#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 116: Hoare triple {107354#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 117: Hoare triple {107354#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 118: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___10~0#1); {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 119: Hoare triple {107354#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {107354#false} is VALID [2022-02-21 04:23:40,312 INFO L290 TraceCheckUtils]: 120: Hoare triple {107354#false} assume !(1 == ~t12_pc~0); {107354#false} is VALID [2022-02-21 04:23:40,313 INFO L290 TraceCheckUtils]: 121: Hoare triple {107354#false} is_transmit12_triggered_~__retres1~12#1 := 0; {107354#false} is VALID [2022-02-21 04:23:40,313 INFO L290 TraceCheckUtils]: 122: Hoare triple {107354#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {107354#false} is VALID [2022-02-21 04:23:40,313 INFO L290 TraceCheckUtils]: 123: Hoare triple {107354#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {107354#false} is VALID [2022-02-21 04:23:40,313 INFO L290 TraceCheckUtils]: 124: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___11~0#1); {107354#false} is VALID [2022-02-21 04:23:40,313 INFO L290 TraceCheckUtils]: 125: Hoare triple {107354#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {107354#false} is VALID [2022-02-21 04:23:40,313 INFO L290 TraceCheckUtils]: 126: Hoare triple {107354#false} assume 1 == ~t13_pc~0; {107354#false} is VALID [2022-02-21 04:23:40,313 INFO L290 TraceCheckUtils]: 127: Hoare triple {107354#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {107354#false} is VALID [2022-02-21 04:23:40,314 INFO L290 TraceCheckUtils]: 128: Hoare triple {107354#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {107354#false} is VALID [2022-02-21 04:23:40,314 INFO L290 TraceCheckUtils]: 129: Hoare triple {107354#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {107354#false} is VALID [2022-02-21 04:23:40,314 INFO L290 TraceCheckUtils]: 130: Hoare triple {107354#false} assume !(0 != activate_threads_~tmp___12~0#1); {107354#false} is VALID [2022-02-21 04:23:40,314 INFO L290 TraceCheckUtils]: 131: Hoare triple {107354#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {107354#false} is VALID [2022-02-21 04:23:40,314 INFO L290 TraceCheckUtils]: 132: Hoare triple {107354#false} assume !(1 == ~M_E~0); {107354#false} is VALID [2022-02-21 04:23:40,314 INFO L290 TraceCheckUtils]: 133: Hoare triple {107354#false} assume !(1 == ~T1_E~0); {107354#false} is VALID [2022-02-21 04:23:40,314 INFO L290 TraceCheckUtils]: 134: Hoare triple {107354#false} assume !(1 == ~T2_E~0); {107354#false} is VALID [2022-02-21 04:23:40,315 INFO L290 TraceCheckUtils]: 135: Hoare triple {107354#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {107354#false} is VALID [2022-02-21 04:23:40,315 INFO L290 TraceCheckUtils]: 136: Hoare triple {107354#false} assume !(1 == ~T4_E~0); {107354#false} is VALID [2022-02-21 04:23:40,315 INFO L290 TraceCheckUtils]: 137: Hoare triple {107354#false} assume !(1 == ~T5_E~0); {107354#false} is VALID [2022-02-21 04:23:40,315 INFO L290 TraceCheckUtils]: 138: Hoare triple {107354#false} assume !(1 == ~T6_E~0); {107354#false} is VALID [2022-02-21 04:23:40,315 INFO L290 TraceCheckUtils]: 139: Hoare triple {107354#false} assume !(1 == ~T7_E~0); {107354#false} is VALID [2022-02-21 04:23:40,315 INFO L290 TraceCheckUtils]: 140: Hoare triple {107354#false} assume !(1 == ~T8_E~0); {107354#false} is VALID [2022-02-21 04:23:40,315 INFO L290 TraceCheckUtils]: 141: Hoare triple {107354#false} assume !(1 == ~T9_E~0); {107354#false} is VALID [2022-02-21 04:23:40,315 INFO L290 TraceCheckUtils]: 142: Hoare triple {107354#false} assume !(1 == ~T10_E~0); {107354#false} is VALID [2022-02-21 04:23:40,316 INFO L290 TraceCheckUtils]: 143: Hoare triple {107354#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {107354#false} is VALID [2022-02-21 04:23:40,316 INFO L290 TraceCheckUtils]: 144: Hoare triple {107354#false} assume !(1 == ~T12_E~0); {107354#false} is VALID [2022-02-21 04:23:40,316 INFO L290 TraceCheckUtils]: 145: Hoare triple {107354#false} assume !(1 == ~T13_E~0); {107354#false} is VALID [2022-02-21 04:23:40,316 INFO L290 TraceCheckUtils]: 146: Hoare triple {107354#false} assume !(1 == ~E_M~0); {107354#false} is VALID [2022-02-21 04:23:40,316 INFO L290 TraceCheckUtils]: 147: Hoare triple {107354#false} assume !(1 == ~E_1~0); {107354#false} is VALID [2022-02-21 04:23:40,316 INFO L290 TraceCheckUtils]: 148: Hoare triple {107354#false} assume !(1 == ~E_2~0); {107354#false} is VALID [2022-02-21 04:23:40,316 INFO L290 TraceCheckUtils]: 149: Hoare triple {107354#false} assume !(1 == ~E_3~0); {107354#false} is VALID [2022-02-21 04:23:40,317 INFO L290 TraceCheckUtils]: 150: Hoare triple {107354#false} assume !(1 == ~E_4~0); {107354#false} is VALID [2022-02-21 04:23:40,317 INFO L290 TraceCheckUtils]: 151: Hoare triple {107354#false} assume 1 == ~E_5~0;~E_5~0 := 2; {107354#false} is VALID [2022-02-21 04:23:40,317 INFO L290 TraceCheckUtils]: 152: Hoare triple {107354#false} assume !(1 == ~E_6~0); {107354#false} is VALID [2022-02-21 04:23:40,317 INFO L290 TraceCheckUtils]: 153: Hoare triple {107354#false} assume !(1 == ~E_7~0); {107354#false} is VALID [2022-02-21 04:23:40,317 INFO L290 TraceCheckUtils]: 154: Hoare triple {107354#false} assume !(1 == ~E_8~0); {107354#false} is VALID [2022-02-21 04:23:40,317 INFO L290 TraceCheckUtils]: 155: Hoare triple {107354#false} assume !(1 == ~E_9~0); {107354#false} is VALID [2022-02-21 04:23:40,317 INFO L290 TraceCheckUtils]: 156: Hoare triple {107354#false} assume !(1 == ~E_10~0); {107354#false} is VALID [2022-02-21 04:23:40,317 INFO L290 TraceCheckUtils]: 157: Hoare triple {107354#false} assume !(1 == ~E_11~0); {107354#false} is VALID [2022-02-21 04:23:40,318 INFO L290 TraceCheckUtils]: 158: Hoare triple {107354#false} assume !(1 == ~E_12~0); {107354#false} is VALID [2022-02-21 04:23:40,318 INFO L290 TraceCheckUtils]: 159: Hoare triple {107354#false} assume 1 == ~E_13~0;~E_13~0 := 2; {107354#false} is VALID [2022-02-21 04:23:40,318 INFO L290 TraceCheckUtils]: 160: Hoare triple {107354#false} assume { :end_inline_reset_delta_events } true; {107354#false} is VALID [2022-02-21 04:23:40,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:40,319 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:40,319 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1639180015] [2022-02-21 04:23:40,319 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1639180015] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:40,319 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:40,319 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:40,319 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [546070099] [2022-02-21 04:23:40,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:40,320 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:40,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:40,320 INFO L85 PathProgramCache]: Analyzing trace with hash 1253897308, now seen corresponding path program 1 times [2022-02-21 04:23:40,321 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:40,321 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446299948] [2022-02-21 04:23:40,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:40,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:40,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:40,354 INFO L290 TraceCheckUtils]: 0: Hoare triple {107356#true} assume !false; {107356#true} is VALID [2022-02-21 04:23:40,354 INFO L290 TraceCheckUtils]: 1: Hoare triple {107356#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {107356#true} is VALID [2022-02-21 04:23:40,354 INFO L290 TraceCheckUtils]: 2: Hoare triple {107356#true} assume !false; {107356#true} is VALID [2022-02-21 04:23:40,354 INFO L290 TraceCheckUtils]: 3: Hoare triple {107356#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {107356#true} is VALID [2022-02-21 04:23:40,354 INFO L290 TraceCheckUtils]: 4: Hoare triple {107356#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {107356#true} is VALID [2022-02-21 04:23:40,354 INFO L290 TraceCheckUtils]: 5: Hoare triple {107356#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {107356#true} is VALID [2022-02-21 04:23:40,355 INFO L290 TraceCheckUtils]: 6: Hoare triple {107356#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {107356#true} is VALID [2022-02-21 04:23:40,355 INFO L290 TraceCheckUtils]: 7: Hoare triple {107356#true} assume !(0 != eval_~tmp~0#1); {107356#true} is VALID [2022-02-21 04:23:40,355 INFO L290 TraceCheckUtils]: 8: Hoare triple {107356#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {107356#true} is VALID [2022-02-21 04:23:40,355 INFO L290 TraceCheckUtils]: 9: Hoare triple {107356#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {107356#true} is VALID [2022-02-21 04:23:40,355 INFO L290 TraceCheckUtils]: 10: Hoare triple {107356#true} assume 0 == ~M_E~0;~M_E~0 := 1; {107356#true} is VALID [2022-02-21 04:23:40,355 INFO L290 TraceCheckUtils]: 11: Hoare triple {107356#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {107356#true} is VALID [2022-02-21 04:23:40,355 INFO L290 TraceCheckUtils]: 12: Hoare triple {107356#true} assume !(0 == ~T2_E~0); {107356#true} is VALID [2022-02-21 04:23:40,356 INFO L290 TraceCheckUtils]: 13: Hoare triple {107356#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {107356#true} is VALID [2022-02-21 04:23:40,356 INFO L290 TraceCheckUtils]: 14: Hoare triple {107356#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {107356#true} is VALID [2022-02-21 04:23:40,356 INFO L290 TraceCheckUtils]: 15: Hoare triple {107356#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,356 INFO L290 TraceCheckUtils]: 16: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,357 INFO L290 TraceCheckUtils]: 17: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,357 INFO L290 TraceCheckUtils]: 18: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,358 INFO L290 TraceCheckUtils]: 19: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,358 INFO L290 TraceCheckUtils]: 20: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,358 INFO L290 TraceCheckUtils]: 21: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,359 INFO L290 TraceCheckUtils]: 22: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,359 INFO L290 TraceCheckUtils]: 23: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,359 INFO L290 TraceCheckUtils]: 24: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,360 INFO L290 TraceCheckUtils]: 25: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,360 INFO L290 TraceCheckUtils]: 26: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,360 INFO L290 TraceCheckUtils]: 27: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,361 INFO L290 TraceCheckUtils]: 28: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,361 INFO L290 TraceCheckUtils]: 29: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,362 INFO L290 TraceCheckUtils]: 30: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,362 INFO L290 TraceCheckUtils]: 31: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,362 INFO L290 TraceCheckUtils]: 32: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,363 INFO L290 TraceCheckUtils]: 33: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,363 INFO L290 TraceCheckUtils]: 34: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,363 INFO L290 TraceCheckUtils]: 35: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,364 INFO L290 TraceCheckUtils]: 36: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,364 INFO L290 TraceCheckUtils]: 37: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,364 INFO L290 TraceCheckUtils]: 38: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,365 INFO L290 TraceCheckUtils]: 39: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,365 INFO L290 TraceCheckUtils]: 40: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,365 INFO L290 TraceCheckUtils]: 41: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,366 INFO L290 TraceCheckUtils]: 42: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,366 INFO L290 TraceCheckUtils]: 43: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,367 INFO L290 TraceCheckUtils]: 44: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,367 INFO L290 TraceCheckUtils]: 45: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,367 INFO L290 TraceCheckUtils]: 46: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,368 INFO L290 TraceCheckUtils]: 47: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,368 INFO L290 TraceCheckUtils]: 48: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,368 INFO L290 TraceCheckUtils]: 49: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,369 INFO L290 TraceCheckUtils]: 50: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,369 INFO L290 TraceCheckUtils]: 51: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,369 INFO L290 TraceCheckUtils]: 52: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,370 INFO L290 TraceCheckUtils]: 53: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,370 INFO L290 TraceCheckUtils]: 54: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,371 INFO L290 TraceCheckUtils]: 55: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,371 INFO L290 TraceCheckUtils]: 56: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,371 INFO L290 TraceCheckUtils]: 57: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,372 INFO L290 TraceCheckUtils]: 58: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,372 INFO L290 TraceCheckUtils]: 59: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,372 INFO L290 TraceCheckUtils]: 60: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,373 INFO L290 TraceCheckUtils]: 61: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,373 INFO L290 TraceCheckUtils]: 62: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,373 INFO L290 TraceCheckUtils]: 63: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,374 INFO L290 TraceCheckUtils]: 64: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,374 INFO L290 TraceCheckUtils]: 65: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,374 INFO L290 TraceCheckUtils]: 66: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,375 INFO L290 TraceCheckUtils]: 67: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,375 INFO L290 TraceCheckUtils]: 68: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,376 INFO L290 TraceCheckUtils]: 69: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,376 INFO L290 TraceCheckUtils]: 70: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,376 INFO L290 TraceCheckUtils]: 71: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,377 INFO L290 TraceCheckUtils]: 72: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,377 INFO L290 TraceCheckUtils]: 73: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,377 INFO L290 TraceCheckUtils]: 74: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,378 INFO L290 TraceCheckUtils]: 75: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,378 INFO L290 TraceCheckUtils]: 76: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,378 INFO L290 TraceCheckUtils]: 77: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,379 INFO L290 TraceCheckUtils]: 78: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,379 INFO L290 TraceCheckUtils]: 79: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,379 INFO L290 TraceCheckUtils]: 80: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,380 INFO L290 TraceCheckUtils]: 81: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,380 INFO L290 TraceCheckUtils]: 82: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,381 INFO L290 TraceCheckUtils]: 83: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,381 INFO L290 TraceCheckUtils]: 84: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,381 INFO L290 TraceCheckUtils]: 85: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,382 INFO L290 TraceCheckUtils]: 86: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,382 INFO L290 TraceCheckUtils]: 87: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,382 INFO L290 TraceCheckUtils]: 88: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,383 INFO L290 TraceCheckUtils]: 89: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,383 INFO L290 TraceCheckUtils]: 90: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,383 INFO L290 TraceCheckUtils]: 91: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,384 INFO L290 TraceCheckUtils]: 92: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,384 INFO L290 TraceCheckUtils]: 93: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,385 INFO L290 TraceCheckUtils]: 94: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,385 INFO L290 TraceCheckUtils]: 95: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,385 INFO L290 TraceCheckUtils]: 96: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,386 INFO L290 TraceCheckUtils]: 97: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,386 INFO L290 TraceCheckUtils]: 98: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,386 INFO L290 TraceCheckUtils]: 99: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,387 INFO L290 TraceCheckUtils]: 100: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,387 INFO L290 TraceCheckUtils]: 101: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,387 INFO L290 TraceCheckUtils]: 102: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,388 INFO L290 TraceCheckUtils]: 103: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,388 INFO L290 TraceCheckUtils]: 104: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,388 INFO L290 TraceCheckUtils]: 105: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,389 INFO L290 TraceCheckUtils]: 106: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,389 INFO L290 TraceCheckUtils]: 107: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,390 INFO L290 TraceCheckUtils]: 108: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,390 INFO L290 TraceCheckUtils]: 109: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,390 INFO L290 TraceCheckUtils]: 110: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,391 INFO L290 TraceCheckUtils]: 111: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,391 INFO L290 TraceCheckUtils]: 112: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,391 INFO L290 TraceCheckUtils]: 113: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,392 INFO L290 TraceCheckUtils]: 114: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,392 INFO L290 TraceCheckUtils]: 115: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,392 INFO L290 TraceCheckUtils]: 116: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,393 INFO L290 TraceCheckUtils]: 117: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,393 INFO L290 TraceCheckUtils]: 118: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,394 INFO L290 TraceCheckUtils]: 119: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,394 INFO L290 TraceCheckUtils]: 120: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,394 INFO L290 TraceCheckUtils]: 121: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,395 INFO L290 TraceCheckUtils]: 122: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,395 INFO L290 TraceCheckUtils]: 123: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,395 INFO L290 TraceCheckUtils]: 124: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,396 INFO L290 TraceCheckUtils]: 125: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,396 INFO L290 TraceCheckUtils]: 126: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,396 INFO L290 TraceCheckUtils]: 127: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {107358#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:40,397 INFO L290 TraceCheckUtils]: 128: Hoare triple {107358#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {107357#false} is VALID [2022-02-21 04:23:40,397 INFO L290 TraceCheckUtils]: 129: Hoare triple {107357#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,397 INFO L290 TraceCheckUtils]: 130: Hoare triple {107357#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,397 INFO L290 TraceCheckUtils]: 131: Hoare triple {107357#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,397 INFO L290 TraceCheckUtils]: 132: Hoare triple {107357#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,397 INFO L290 TraceCheckUtils]: 133: Hoare triple {107357#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,398 INFO L290 TraceCheckUtils]: 134: Hoare triple {107357#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,398 INFO L290 TraceCheckUtils]: 135: Hoare triple {107357#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,398 INFO L290 TraceCheckUtils]: 136: Hoare triple {107357#false} assume !(1 == ~T13_E~0); {107357#false} is VALID [2022-02-21 04:23:40,398 INFO L290 TraceCheckUtils]: 137: Hoare triple {107357#false} assume 1 == ~E_M~0;~E_M~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,398 INFO L290 TraceCheckUtils]: 138: Hoare triple {107357#false} assume 1 == ~E_1~0;~E_1~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,398 INFO L290 TraceCheckUtils]: 139: Hoare triple {107357#false} assume 1 == ~E_2~0;~E_2~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,398 INFO L290 TraceCheckUtils]: 140: Hoare triple {107357#false} assume 1 == ~E_3~0;~E_3~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,398 INFO L290 TraceCheckUtils]: 141: Hoare triple {107357#false} assume 1 == ~E_4~0;~E_4~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,399 INFO L290 TraceCheckUtils]: 142: Hoare triple {107357#false} assume 1 == ~E_5~0;~E_5~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,399 INFO L290 TraceCheckUtils]: 143: Hoare triple {107357#false} assume 1 == ~E_6~0;~E_6~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,399 INFO L290 TraceCheckUtils]: 144: Hoare triple {107357#false} assume !(1 == ~E_7~0); {107357#false} is VALID [2022-02-21 04:23:40,399 INFO L290 TraceCheckUtils]: 145: Hoare triple {107357#false} assume 1 == ~E_8~0;~E_8~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,399 INFO L290 TraceCheckUtils]: 146: Hoare triple {107357#false} assume 1 == ~E_9~0;~E_9~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,399 INFO L290 TraceCheckUtils]: 147: Hoare triple {107357#false} assume 1 == ~E_10~0;~E_10~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,399 INFO L290 TraceCheckUtils]: 148: Hoare triple {107357#false} assume 1 == ~E_11~0;~E_11~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,400 INFO L290 TraceCheckUtils]: 149: Hoare triple {107357#false} assume 1 == ~E_12~0;~E_12~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,400 INFO L290 TraceCheckUtils]: 150: Hoare triple {107357#false} assume 1 == ~E_13~0;~E_13~0 := 2; {107357#false} is VALID [2022-02-21 04:23:40,400 INFO L290 TraceCheckUtils]: 151: Hoare triple {107357#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {107357#false} is VALID [2022-02-21 04:23:40,400 INFO L290 TraceCheckUtils]: 152: Hoare triple {107357#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {107357#false} is VALID [2022-02-21 04:23:40,400 INFO L290 TraceCheckUtils]: 153: Hoare triple {107357#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {107357#false} is VALID [2022-02-21 04:23:40,400 INFO L290 TraceCheckUtils]: 154: Hoare triple {107357#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {107357#false} is VALID [2022-02-21 04:23:40,400 INFO L290 TraceCheckUtils]: 155: Hoare triple {107357#false} assume !(0 == start_simulation_~tmp~3#1); {107357#false} is VALID [2022-02-21 04:23:40,401 INFO L290 TraceCheckUtils]: 156: Hoare triple {107357#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {107357#false} is VALID [2022-02-21 04:23:40,401 INFO L290 TraceCheckUtils]: 157: Hoare triple {107357#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {107357#false} is VALID [2022-02-21 04:23:40,401 INFO L290 TraceCheckUtils]: 158: Hoare triple {107357#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {107357#false} is VALID [2022-02-21 04:23:40,401 INFO L290 TraceCheckUtils]: 159: Hoare triple {107357#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {107357#false} is VALID [2022-02-21 04:23:40,401 INFO L290 TraceCheckUtils]: 160: Hoare triple {107357#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {107357#false} is VALID [2022-02-21 04:23:40,401 INFO L290 TraceCheckUtils]: 161: Hoare triple {107357#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {107357#false} is VALID [2022-02-21 04:23:40,401 INFO L290 TraceCheckUtils]: 162: Hoare triple {107357#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {107357#false} is VALID [2022-02-21 04:23:40,401 INFO L290 TraceCheckUtils]: 163: Hoare triple {107357#false} assume !(0 != start_simulation_~tmp___0~1#1); {107357#false} is VALID [2022-02-21 04:23:40,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:40,402 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:40,402 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446299948] [2022-02-21 04:23:40,403 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446299948] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:40,403 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:40,403 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:40,403 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582197414] [2022-02-21 04:23:40,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:40,404 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:40,404 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:40,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:40,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:40,404 INFO L87 Difference]: Start difference. First operand 2023 states and 2984 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:43,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:43,071 INFO L93 Difference]: Finished difference Result 3771 states and 5546 transitions. [2022-02-21 04:23:43,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:43,071 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:43,182 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:43,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3771 states and 5546 transitions. [2022-02-21 04:23:43,611 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-02-21 04:23:43,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3771 states to 3771 states and 5546 transitions. [2022-02-21 04:23:43,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3771 [2022-02-21 04:23:43,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3771 [2022-02-21 04:23:43,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3771 states and 5546 transitions. [2022-02-21 04:23:43,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:43,937 INFO L681 BuchiCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2022-02-21 04:23:43,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states and 5546 transitions. [2022-02-21 04:23:43,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3771. [2022-02-21 04:23:43,976 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:43,980 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3771 states and 5546 transitions. Second operand has 3771 states, 3771 states have (on average 1.4706974277380005) internal successors, (5546), 3770 states have internal predecessors, (5546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:43,983 INFO L74 IsIncluded]: Start isIncluded. First operand 3771 states and 5546 transitions. Second operand has 3771 states, 3771 states have (on average 1.4706974277380005) internal successors, (5546), 3770 states have internal predecessors, (5546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:43,985 INFO L87 Difference]: Start difference. First operand 3771 states and 5546 transitions. Second operand has 3771 states, 3771 states have (on average 1.4706974277380005) internal successors, (5546), 3770 states have internal predecessors, (5546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:44,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:44,425 INFO L93 Difference]: Finished difference Result 3771 states and 5546 transitions. [2022-02-21 04:23:44,425 INFO L276 IsEmpty]: Start isEmpty. Operand 3771 states and 5546 transitions. [2022-02-21 04:23:44,428 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:44,428 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:44,432 INFO L74 IsIncluded]: Start isIncluded. First operand has 3771 states, 3771 states have (on average 1.4706974277380005) internal successors, (5546), 3770 states have internal predecessors, (5546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3771 states and 5546 transitions. [2022-02-21 04:23:44,435 INFO L87 Difference]: Start difference. First operand has 3771 states, 3771 states have (on average 1.4706974277380005) internal successors, (5546), 3770 states have internal predecessors, (5546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3771 states and 5546 transitions. [2022-02-21 04:23:44,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:44,725 INFO L93 Difference]: Finished difference Result 3771 states and 5546 transitions. [2022-02-21 04:23:44,726 INFO L276 IsEmpty]: Start isEmpty. Operand 3771 states and 5546 transitions. [2022-02-21 04:23:44,729 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:44,729 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:44,729 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:44,729 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:44,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4706974277380005) internal successors, (5546), 3770 states have internal predecessors, (5546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:45,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5546 transitions. [2022-02-21 04:23:45,045 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2022-02-21 04:23:45,045 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2022-02-21 04:23:45,045 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:23:45,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5546 transitions. [2022-02-21 04:23:45,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-02-21 04:23:45,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:45,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:45,053 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:45,053 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:45,054 INFO L791 eck$LassoCheckResult]: Stem: 112058#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 112059#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 113083#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113084#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 113180#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 112522#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111990#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111991#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112812#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112813#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112925#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 112926#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 111762#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 111763#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 112956#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 112299#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 112300#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 112869#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 112201#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112202#L1291 assume !(0 == ~M_E~0); 113181#L1291-2 assume !(0 == ~T1_E~0); 113179#L1296-1 assume !(0 == ~T2_E~0); 112358#L1301-1 assume !(0 == ~T3_E~0); 112359#L1306-1 assume !(0 == ~T4_E~0); 112877#L1311-1 assume !(0 == ~T5_E~0); 111605#L1316-1 assume !(0 == ~T6_E~0); 111606#L1321-1 assume !(0 == ~T7_E~0); 112371#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 111433#L1331-1 assume !(0 == ~T9_E~0); 111132#L1336-1 assume !(0 == ~T10_E~0); 111133#L1341-1 assume !(0 == ~T11_E~0); 111213#L1346-1 assume !(0 == ~T12_E~0); 111214#L1351-1 assume !(0 == ~T13_E~0); 111554#L1356-1 assume !(0 == ~E_M~0); 111555#L1361-1 assume !(0 == ~E_1~0); 113113#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 111595#L1371-1 assume !(0 == ~E_3~0); 111596#L1376-1 assume !(0 == ~E_4~0); 112418#L1381-1 assume !(0 == ~E_5~0); 112419#L1386-1 assume !(0 == ~E_6~0); 113145#L1391-1 assume !(0 == ~E_7~0); 113168#L1396-1 assume !(0 == ~E_8~0); 112331#L1401-1 assume !(0 == ~E_9~0); 112332#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 112611#L1411-1 assume !(0 == ~E_11~0); 112612#L1416-1 assume !(0 == ~E_12~0); 112243#L1421-1 assume !(0 == ~E_13~0); 111785#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111786#L640 assume !(1 == ~m_pc~0); 112296#L640-2 is_master_triggered_~__retres1~0#1 := 0; 112295#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112387#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112281#L1603 assume !(0 != activate_threads_~tmp~1#1); 112282#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111915#L659 assume 1 == ~t1_pc~0; 111916#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 112022#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112988#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112042#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 112043#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112056#L678 assume 1 == ~t2_pc~0; 113035#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 113036#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113141#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 112154#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 112155#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112276#L697 assume !(1 == ~t3_pc~0); 112277#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112399#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112207#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 112186#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112187#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113073#L716 assume 1 == ~t4_pc~0; 113058#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 111896#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111897#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 111396#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 111397#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112692#L735 assume !(1 == ~t5_pc~0); 111357#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 111358#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111808#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112719#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 112352#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112353#L754 assume 1 == ~t6_pc~0; 112106#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 112004#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112005#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111977#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 111978#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112803#L773 assume !(1 == ~t7_pc~0); 111558#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 111557#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112388#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112360#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 112361#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 112408#L792 assume 1 == ~t8_pc~0; 112581#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 112929#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112402#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 112355#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 112279#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 112280#L811 assume 1 == ~t9_pc~0; 112484#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 112967#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 112831#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 112480#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 112292#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 112293#L830 assume !(1 == ~t10_pc~0); 112014#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 111537#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111230#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111231#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111518#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112822#L849 assume 1 == ~t11_pc~0; 112823#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 111333#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 111334#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 111923#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 112726#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 112727#L868 assume !(1 == ~t12_pc~0); 112139#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 112138#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 111932#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 111933#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 111569#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 111570#L887 assume 1 == ~t13_pc~0; 112741#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 112180#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 112181#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 112618#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 111273#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111274#L1439 assume !(1 == ~M_E~0); 112348#L1439-2 assume !(1 == ~T1_E~0); 111445#L1444-1 assume !(1 == ~T2_E~0); 111446#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111919#L1454-1 assume !(1 == ~T4_E~0); 111920#L1459-1 assume !(1 == ~T5_E~0); 112477#L1464-1 assume !(1 == ~T6_E~0); 112478#L1469-1 assume !(1 == ~T7_E~0); 112550#L1474-1 assume !(1 == ~T8_E~0); 112244#L1479-1 assume !(1 == ~T9_E~0); 112245#L1484-1 assume !(1 == ~T10_E~0); 112481#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 112127#L1494-1 assume !(1 == ~T12_E~0); 112128#L1499-1 assume !(1 == ~T13_E~0); 112320#L1504-1 assume !(1 == ~E_M~0); 112321#L1509-1 assume !(1 == ~E_1~0); 112909#L1514-1 assume !(1 == ~E_2~0); 112583#L1519-1 assume !(1 == ~E_3~0); 112584#L1524-1 assume !(1 == ~E_4~0); 113127#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 113128#L1534-1 assume !(1 == ~E_6~0); 111266#L1539-1 assume !(1 == ~E_7~0); 111267#L1544-1 assume !(1 == ~E_8~0); 111681#L1549-1 assume !(1 == ~E_9~0); 113098#L1554-1 assume !(1 == ~E_10~0); 113094#L1559-1 assume !(1 == ~E_11~0); 112950#L1564-1 assume !(1 == ~E_12~0); 112951#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 113122#L1574-1 assume { :end_inline_reset_delta_events } true; 111443#L1940-2 [2022-02-21 04:23:45,054 INFO L793 eck$LassoCheckResult]: Loop: 111443#L1940-2 assume !false; 111444#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 111726#L1266 assume !false; 112749#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 111974#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 111707#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 112099#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 112100#L1079 assume !(0 != eval_~tmp~0#1); 112061#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112062#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 112667#L1291-3 assume !(0 == ~M_E~0); 112668#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 114533#L1296-3 assume !(0 == ~T2_E~0); 114532#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 114531#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 114530#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 114529#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 114528#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 114527#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 114526#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 114525#L1336-3 assume !(0 == ~T10_E~0); 114524#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 114523#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 114522#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 114521#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 114520#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 114519#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 114518#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 114517#L1376-3 assume !(0 == ~E_4~0); 114516#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 114515#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 114514#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 114513#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 114512#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 114511#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 114510#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 114509#L1416-3 assume !(0 == ~E_12~0); 114508#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 114507#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114505#L640-45 assume !(1 == ~m_pc~0); 112837#L640-47 is_master_triggered_~__retres1~0#1 := 0; 111642#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111643#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 111182#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 111183#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111281#L659-45 assume !(1 == ~t1_pc~0); 111283#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 111721#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112684#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112685#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 112706#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112707#L678-45 assume !(1 == ~t2_pc~0); 112649#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 112182#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112183#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 112335#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 114461#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114458#L697-45 assume 1 == ~t3_pc~0; 114455#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 114454#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114453#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 114451#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 114449#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114447#L716-45 assume !(1 == ~t4_pc~0); 114443#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 114442#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114441#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114440#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 114439#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114438#L735-45 assume !(1 == ~t5_pc~0); 114437#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 114435#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114433#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 114431#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 114429#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114427#L754-45 assume !(1 == ~t6_pc~0); 114423#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 114421#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111851#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111852#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 112426#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112158#L773-45 assume !(1 == ~t7_pc~0); 111714#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 111715#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112637#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112934#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 113006#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 114400#L792-45 assume 1 == ~t8_pc~0; 114397#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 114395#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 114393#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 114391#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 114389#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 114388#L811-45 assume 1 == ~t9_pc~0; 114385#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 114382#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 114380#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 114378#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 114376#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 114374#L830-45 assume !(1 == ~t10_pc~0); 114371#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 114368#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 114366#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 114364#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 112993#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111202#L849-45 assume !(1 == ~t11_pc~0); 111203#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 111662#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 111293#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 111190#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 111191#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 111449#L868-45 assume !(1 == ~t12_pc~0); 111451#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 111389#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 111390#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 112732#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 113001#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 113002#L887-45 assume 1 == ~t13_pc~0; 112816#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 111459#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 112745#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 113117#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 111421#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111422#L1439-3 assume !(1 == ~M_E~0); 112733#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 111441#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 111442#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111599#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 112531#L1459-3 assume !(1 == ~T5_E~0); 112532#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 113005#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 112938#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 112939#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 113007#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 112216#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 112217#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 112862#L1499-3 assume !(1 == ~T13_E~0); 112492#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 112493#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 112947#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 112981#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112135#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 112136#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 113027#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 112403#L1539-3 assume !(1 == ~E_7~0); 111878#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 111879#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 112375#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 111495#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 111496#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 112880#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 112857#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 111372#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 111143#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 111418#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 111379#L1959 assume !(0 == start_simulation_~tmp~3#1); 111381#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 111413#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 111363#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 112676#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 112798#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 113024#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 113040#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 113041#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 111443#L1940-2 [2022-02-21 04:23:45,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:45,055 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2022-02-21 04:23:45,055 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:45,055 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [887534416] [2022-02-21 04:23:45,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:45,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:45,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:45,090 INFO L290 TraceCheckUtils]: 0: Hoare triple {122446#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,090 INFO L290 TraceCheckUtils]: 1: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,090 INFO L290 TraceCheckUtils]: 2: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,091 INFO L290 TraceCheckUtils]: 3: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,091 INFO L290 TraceCheckUtils]: 4: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,092 INFO L290 TraceCheckUtils]: 5: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,092 INFO L290 TraceCheckUtils]: 6: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,092 INFO L290 TraceCheckUtils]: 7: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,092 INFO L290 TraceCheckUtils]: 8: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,093 INFO L290 TraceCheckUtils]: 9: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,093 INFO L290 TraceCheckUtils]: 10: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,093 INFO L290 TraceCheckUtils]: 11: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,094 INFO L290 TraceCheckUtils]: 12: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,094 INFO L290 TraceCheckUtils]: 13: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,094 INFO L290 TraceCheckUtils]: 14: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,095 INFO L290 TraceCheckUtils]: 15: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,095 INFO L290 TraceCheckUtils]: 16: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,096 INFO L290 TraceCheckUtils]: 17: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,096 INFO L290 TraceCheckUtils]: 18: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {122448#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:45,096 INFO L290 TraceCheckUtils]: 19: Hoare triple {122448#(= ~T8_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {122449#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:45,097 INFO L290 TraceCheckUtils]: 20: Hoare triple {122449#(not (= ~T8_E~0 0))} assume !(0 == ~T1_E~0); {122449#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:45,097 INFO L290 TraceCheckUtils]: 21: Hoare triple {122449#(not (= ~T8_E~0 0))} assume !(0 == ~T2_E~0); {122449#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:45,097 INFO L290 TraceCheckUtils]: 22: Hoare triple {122449#(not (= ~T8_E~0 0))} assume !(0 == ~T3_E~0); {122449#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:45,098 INFO L290 TraceCheckUtils]: 23: Hoare triple {122449#(not (= ~T8_E~0 0))} assume !(0 == ~T4_E~0); {122449#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:45,098 INFO L290 TraceCheckUtils]: 24: Hoare triple {122449#(not (= ~T8_E~0 0))} assume !(0 == ~T5_E~0); {122449#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:45,098 INFO L290 TraceCheckUtils]: 25: Hoare triple {122449#(not (= ~T8_E~0 0))} assume !(0 == ~T6_E~0); {122449#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:45,099 INFO L290 TraceCheckUtils]: 26: Hoare triple {122449#(not (= ~T8_E~0 0))} assume !(0 == ~T7_E~0); {122449#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:45,100 INFO L290 TraceCheckUtils]: 27: Hoare triple {122449#(not (= ~T8_E~0 0))} assume 0 == ~T8_E~0;~T8_E~0 := 1; {122447#false} is VALID [2022-02-21 04:23:45,100 INFO L290 TraceCheckUtils]: 28: Hoare triple {122447#false} assume !(0 == ~T9_E~0); {122447#false} is VALID [2022-02-21 04:23:45,100 INFO L290 TraceCheckUtils]: 29: Hoare triple {122447#false} assume !(0 == ~T10_E~0); {122447#false} is VALID [2022-02-21 04:23:45,101 INFO L290 TraceCheckUtils]: 30: Hoare triple {122447#false} assume !(0 == ~T11_E~0); {122447#false} is VALID [2022-02-21 04:23:45,101 INFO L290 TraceCheckUtils]: 31: Hoare triple {122447#false} assume !(0 == ~T12_E~0); {122447#false} is VALID [2022-02-21 04:23:45,101 INFO L290 TraceCheckUtils]: 32: Hoare triple {122447#false} assume !(0 == ~T13_E~0); {122447#false} is VALID [2022-02-21 04:23:45,101 INFO L290 TraceCheckUtils]: 33: Hoare triple {122447#false} assume !(0 == ~E_M~0); {122447#false} is VALID [2022-02-21 04:23:45,101 INFO L290 TraceCheckUtils]: 34: Hoare triple {122447#false} assume !(0 == ~E_1~0); {122447#false} is VALID [2022-02-21 04:23:45,101 INFO L290 TraceCheckUtils]: 35: Hoare triple {122447#false} assume 0 == ~E_2~0;~E_2~0 := 1; {122447#false} is VALID [2022-02-21 04:23:45,101 INFO L290 TraceCheckUtils]: 36: Hoare triple {122447#false} assume !(0 == ~E_3~0); {122447#false} is VALID [2022-02-21 04:23:45,102 INFO L290 TraceCheckUtils]: 37: Hoare triple {122447#false} assume !(0 == ~E_4~0); {122447#false} is VALID [2022-02-21 04:23:45,102 INFO L290 TraceCheckUtils]: 38: Hoare triple {122447#false} assume !(0 == ~E_5~0); {122447#false} is VALID [2022-02-21 04:23:45,102 INFO L290 TraceCheckUtils]: 39: Hoare triple {122447#false} assume !(0 == ~E_6~0); {122447#false} is VALID [2022-02-21 04:23:45,102 INFO L290 TraceCheckUtils]: 40: Hoare triple {122447#false} assume !(0 == ~E_7~0); {122447#false} is VALID [2022-02-21 04:23:45,102 INFO L290 TraceCheckUtils]: 41: Hoare triple {122447#false} assume !(0 == ~E_8~0); {122447#false} is VALID [2022-02-21 04:23:45,102 INFO L290 TraceCheckUtils]: 42: Hoare triple {122447#false} assume !(0 == ~E_9~0); {122447#false} is VALID [2022-02-21 04:23:45,102 INFO L290 TraceCheckUtils]: 43: Hoare triple {122447#false} assume 0 == ~E_10~0;~E_10~0 := 1; {122447#false} is VALID [2022-02-21 04:23:45,102 INFO L290 TraceCheckUtils]: 44: Hoare triple {122447#false} assume !(0 == ~E_11~0); {122447#false} is VALID [2022-02-21 04:23:45,103 INFO L290 TraceCheckUtils]: 45: Hoare triple {122447#false} assume !(0 == ~E_12~0); {122447#false} is VALID [2022-02-21 04:23:45,103 INFO L290 TraceCheckUtils]: 46: Hoare triple {122447#false} assume !(0 == ~E_13~0); {122447#false} is VALID [2022-02-21 04:23:45,103 INFO L290 TraceCheckUtils]: 47: Hoare triple {122447#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {122447#false} is VALID [2022-02-21 04:23:45,103 INFO L290 TraceCheckUtils]: 48: Hoare triple {122447#false} assume !(1 == ~m_pc~0); {122447#false} is VALID [2022-02-21 04:23:45,103 INFO L290 TraceCheckUtils]: 49: Hoare triple {122447#false} is_master_triggered_~__retres1~0#1 := 0; {122447#false} is VALID [2022-02-21 04:23:45,103 INFO L290 TraceCheckUtils]: 50: Hoare triple {122447#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {122447#false} is VALID [2022-02-21 04:23:45,103 INFO L290 TraceCheckUtils]: 51: Hoare triple {122447#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {122447#false} is VALID [2022-02-21 04:23:45,104 INFO L290 TraceCheckUtils]: 52: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp~1#1); {122447#false} is VALID [2022-02-21 04:23:45,104 INFO L290 TraceCheckUtils]: 53: Hoare triple {122447#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {122447#false} is VALID [2022-02-21 04:23:45,104 INFO L290 TraceCheckUtils]: 54: Hoare triple {122447#false} assume 1 == ~t1_pc~0; {122447#false} is VALID [2022-02-21 04:23:45,104 INFO L290 TraceCheckUtils]: 55: Hoare triple {122447#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {122447#false} is VALID [2022-02-21 04:23:45,104 INFO L290 TraceCheckUtils]: 56: Hoare triple {122447#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {122447#false} is VALID [2022-02-21 04:23:45,104 INFO L290 TraceCheckUtils]: 57: Hoare triple {122447#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {122447#false} is VALID [2022-02-21 04:23:45,104 INFO L290 TraceCheckUtils]: 58: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___0~0#1); {122447#false} is VALID [2022-02-21 04:23:45,105 INFO L290 TraceCheckUtils]: 59: Hoare triple {122447#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {122447#false} is VALID [2022-02-21 04:23:45,105 INFO L290 TraceCheckUtils]: 60: Hoare triple {122447#false} assume 1 == ~t2_pc~0; {122447#false} is VALID [2022-02-21 04:23:45,105 INFO L290 TraceCheckUtils]: 61: Hoare triple {122447#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {122447#false} is VALID [2022-02-21 04:23:45,105 INFO L290 TraceCheckUtils]: 62: Hoare triple {122447#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {122447#false} is VALID [2022-02-21 04:23:45,105 INFO L290 TraceCheckUtils]: 63: Hoare triple {122447#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {122447#false} is VALID [2022-02-21 04:23:45,105 INFO L290 TraceCheckUtils]: 64: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___1~0#1); {122447#false} is VALID [2022-02-21 04:23:45,105 INFO L290 TraceCheckUtils]: 65: Hoare triple {122447#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {122447#false} is VALID [2022-02-21 04:23:45,105 INFO L290 TraceCheckUtils]: 66: Hoare triple {122447#false} assume !(1 == ~t3_pc~0); {122447#false} is VALID [2022-02-21 04:23:45,106 INFO L290 TraceCheckUtils]: 67: Hoare triple {122447#false} is_transmit3_triggered_~__retres1~3#1 := 0; {122447#false} is VALID [2022-02-21 04:23:45,106 INFO L290 TraceCheckUtils]: 68: Hoare triple {122447#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {122447#false} is VALID [2022-02-21 04:23:45,106 INFO L290 TraceCheckUtils]: 69: Hoare triple {122447#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {122447#false} is VALID [2022-02-21 04:23:45,106 INFO L290 TraceCheckUtils]: 70: Hoare triple {122447#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {122447#false} is VALID [2022-02-21 04:23:45,106 INFO L290 TraceCheckUtils]: 71: Hoare triple {122447#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {122447#false} is VALID [2022-02-21 04:23:45,106 INFO L290 TraceCheckUtils]: 72: Hoare triple {122447#false} assume 1 == ~t4_pc~0; {122447#false} is VALID [2022-02-21 04:23:45,106 INFO L290 TraceCheckUtils]: 73: Hoare triple {122447#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {122447#false} is VALID [2022-02-21 04:23:45,107 INFO L290 TraceCheckUtils]: 74: Hoare triple {122447#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {122447#false} is VALID [2022-02-21 04:23:45,107 INFO L290 TraceCheckUtils]: 75: Hoare triple {122447#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {122447#false} is VALID [2022-02-21 04:23:45,107 INFO L290 TraceCheckUtils]: 76: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___3~0#1); {122447#false} is VALID [2022-02-21 04:23:45,107 INFO L290 TraceCheckUtils]: 77: Hoare triple {122447#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {122447#false} is VALID [2022-02-21 04:23:45,107 INFO L290 TraceCheckUtils]: 78: Hoare triple {122447#false} assume !(1 == ~t5_pc~0); {122447#false} is VALID [2022-02-21 04:23:45,107 INFO L290 TraceCheckUtils]: 79: Hoare triple {122447#false} is_transmit5_triggered_~__retres1~5#1 := 0; {122447#false} is VALID [2022-02-21 04:23:45,107 INFO L290 TraceCheckUtils]: 80: Hoare triple {122447#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {122447#false} is VALID [2022-02-21 04:23:45,108 INFO L290 TraceCheckUtils]: 81: Hoare triple {122447#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {122447#false} is VALID [2022-02-21 04:23:45,108 INFO L290 TraceCheckUtils]: 82: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___4~0#1); {122447#false} is VALID [2022-02-21 04:23:45,108 INFO L290 TraceCheckUtils]: 83: Hoare triple {122447#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {122447#false} is VALID [2022-02-21 04:23:45,108 INFO L290 TraceCheckUtils]: 84: Hoare triple {122447#false} assume 1 == ~t6_pc~0; {122447#false} is VALID [2022-02-21 04:23:45,108 INFO L290 TraceCheckUtils]: 85: Hoare triple {122447#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {122447#false} is VALID [2022-02-21 04:23:45,108 INFO L290 TraceCheckUtils]: 86: Hoare triple {122447#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {122447#false} is VALID [2022-02-21 04:23:45,108 INFO L290 TraceCheckUtils]: 87: Hoare triple {122447#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {122447#false} is VALID [2022-02-21 04:23:45,108 INFO L290 TraceCheckUtils]: 88: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___5~0#1); {122447#false} is VALID [2022-02-21 04:23:45,109 INFO L290 TraceCheckUtils]: 89: Hoare triple {122447#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {122447#false} is VALID [2022-02-21 04:23:45,109 INFO L290 TraceCheckUtils]: 90: Hoare triple {122447#false} assume !(1 == ~t7_pc~0); {122447#false} is VALID [2022-02-21 04:23:45,109 INFO L290 TraceCheckUtils]: 91: Hoare triple {122447#false} is_transmit7_triggered_~__retres1~7#1 := 0; {122447#false} is VALID [2022-02-21 04:23:45,109 INFO L290 TraceCheckUtils]: 92: Hoare triple {122447#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {122447#false} is VALID [2022-02-21 04:23:45,109 INFO L290 TraceCheckUtils]: 93: Hoare triple {122447#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {122447#false} is VALID [2022-02-21 04:23:45,109 INFO L290 TraceCheckUtils]: 94: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___6~0#1); {122447#false} is VALID [2022-02-21 04:23:45,109 INFO L290 TraceCheckUtils]: 95: Hoare triple {122447#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {122447#false} is VALID [2022-02-21 04:23:45,110 INFO L290 TraceCheckUtils]: 96: Hoare triple {122447#false} assume 1 == ~t8_pc~0; {122447#false} is VALID [2022-02-21 04:23:45,110 INFO L290 TraceCheckUtils]: 97: Hoare triple {122447#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {122447#false} is VALID [2022-02-21 04:23:45,110 INFO L290 TraceCheckUtils]: 98: Hoare triple {122447#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {122447#false} is VALID [2022-02-21 04:23:45,110 INFO L290 TraceCheckUtils]: 99: Hoare triple {122447#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {122447#false} is VALID [2022-02-21 04:23:45,110 INFO L290 TraceCheckUtils]: 100: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___7~0#1); {122447#false} is VALID [2022-02-21 04:23:45,110 INFO L290 TraceCheckUtils]: 101: Hoare triple {122447#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {122447#false} is VALID [2022-02-21 04:23:45,110 INFO L290 TraceCheckUtils]: 102: Hoare triple {122447#false} assume 1 == ~t9_pc~0; {122447#false} is VALID [2022-02-21 04:23:45,110 INFO L290 TraceCheckUtils]: 103: Hoare triple {122447#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {122447#false} is VALID [2022-02-21 04:23:45,111 INFO L290 TraceCheckUtils]: 104: Hoare triple {122447#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {122447#false} is VALID [2022-02-21 04:23:45,111 INFO L290 TraceCheckUtils]: 105: Hoare triple {122447#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {122447#false} is VALID [2022-02-21 04:23:45,111 INFO L290 TraceCheckUtils]: 106: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___8~0#1); {122447#false} is VALID [2022-02-21 04:23:45,111 INFO L290 TraceCheckUtils]: 107: Hoare triple {122447#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {122447#false} is VALID [2022-02-21 04:23:45,111 INFO L290 TraceCheckUtils]: 108: Hoare triple {122447#false} assume !(1 == ~t10_pc~0); {122447#false} is VALID [2022-02-21 04:23:45,111 INFO L290 TraceCheckUtils]: 109: Hoare triple {122447#false} is_transmit10_triggered_~__retres1~10#1 := 0; {122447#false} is VALID [2022-02-21 04:23:45,111 INFO L290 TraceCheckUtils]: 110: Hoare triple {122447#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {122447#false} is VALID [2022-02-21 04:23:45,112 INFO L290 TraceCheckUtils]: 111: Hoare triple {122447#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {122447#false} is VALID [2022-02-21 04:23:45,112 INFO L290 TraceCheckUtils]: 112: Hoare triple {122447#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {122447#false} is VALID [2022-02-21 04:23:45,112 INFO L290 TraceCheckUtils]: 113: Hoare triple {122447#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {122447#false} is VALID [2022-02-21 04:23:45,112 INFO L290 TraceCheckUtils]: 114: Hoare triple {122447#false} assume 1 == ~t11_pc~0; {122447#false} is VALID [2022-02-21 04:23:45,112 INFO L290 TraceCheckUtils]: 115: Hoare triple {122447#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {122447#false} is VALID [2022-02-21 04:23:45,112 INFO L290 TraceCheckUtils]: 116: Hoare triple {122447#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {122447#false} is VALID [2022-02-21 04:23:45,112 INFO L290 TraceCheckUtils]: 117: Hoare triple {122447#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {122447#false} is VALID [2022-02-21 04:23:45,113 INFO L290 TraceCheckUtils]: 118: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___10~0#1); {122447#false} is VALID [2022-02-21 04:23:45,113 INFO L290 TraceCheckUtils]: 119: Hoare triple {122447#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {122447#false} is VALID [2022-02-21 04:23:45,113 INFO L290 TraceCheckUtils]: 120: Hoare triple {122447#false} assume !(1 == ~t12_pc~0); {122447#false} is VALID [2022-02-21 04:23:45,113 INFO L290 TraceCheckUtils]: 121: Hoare triple {122447#false} is_transmit12_triggered_~__retres1~12#1 := 0; {122447#false} is VALID [2022-02-21 04:23:45,113 INFO L290 TraceCheckUtils]: 122: Hoare triple {122447#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {122447#false} is VALID [2022-02-21 04:23:45,113 INFO L290 TraceCheckUtils]: 123: Hoare triple {122447#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {122447#false} is VALID [2022-02-21 04:23:45,113 INFO L290 TraceCheckUtils]: 124: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___11~0#1); {122447#false} is VALID [2022-02-21 04:23:45,113 INFO L290 TraceCheckUtils]: 125: Hoare triple {122447#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {122447#false} is VALID [2022-02-21 04:23:45,114 INFO L290 TraceCheckUtils]: 126: Hoare triple {122447#false} assume 1 == ~t13_pc~0; {122447#false} is VALID [2022-02-21 04:23:45,114 INFO L290 TraceCheckUtils]: 127: Hoare triple {122447#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {122447#false} is VALID [2022-02-21 04:23:45,114 INFO L290 TraceCheckUtils]: 128: Hoare triple {122447#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {122447#false} is VALID [2022-02-21 04:23:45,114 INFO L290 TraceCheckUtils]: 129: Hoare triple {122447#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {122447#false} is VALID [2022-02-21 04:23:45,114 INFO L290 TraceCheckUtils]: 130: Hoare triple {122447#false} assume !(0 != activate_threads_~tmp___12~0#1); {122447#false} is VALID [2022-02-21 04:23:45,114 INFO L290 TraceCheckUtils]: 131: Hoare triple {122447#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {122447#false} is VALID [2022-02-21 04:23:45,114 INFO L290 TraceCheckUtils]: 132: Hoare triple {122447#false} assume !(1 == ~M_E~0); {122447#false} is VALID [2022-02-21 04:23:45,115 INFO L290 TraceCheckUtils]: 133: Hoare triple {122447#false} assume !(1 == ~T1_E~0); {122447#false} is VALID [2022-02-21 04:23:45,115 INFO L290 TraceCheckUtils]: 134: Hoare triple {122447#false} assume !(1 == ~T2_E~0); {122447#false} is VALID [2022-02-21 04:23:45,115 INFO L290 TraceCheckUtils]: 135: Hoare triple {122447#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {122447#false} is VALID [2022-02-21 04:23:45,115 INFO L290 TraceCheckUtils]: 136: Hoare triple {122447#false} assume !(1 == ~T4_E~0); {122447#false} is VALID [2022-02-21 04:23:45,115 INFO L290 TraceCheckUtils]: 137: Hoare triple {122447#false} assume !(1 == ~T5_E~0); {122447#false} is VALID [2022-02-21 04:23:45,115 INFO L290 TraceCheckUtils]: 138: Hoare triple {122447#false} assume !(1 == ~T6_E~0); {122447#false} is VALID [2022-02-21 04:23:45,115 INFO L290 TraceCheckUtils]: 139: Hoare triple {122447#false} assume !(1 == ~T7_E~0); {122447#false} is VALID [2022-02-21 04:23:45,116 INFO L290 TraceCheckUtils]: 140: Hoare triple {122447#false} assume !(1 == ~T8_E~0); {122447#false} is VALID [2022-02-21 04:23:45,116 INFO L290 TraceCheckUtils]: 141: Hoare triple {122447#false} assume !(1 == ~T9_E~0); {122447#false} is VALID [2022-02-21 04:23:45,116 INFO L290 TraceCheckUtils]: 142: Hoare triple {122447#false} assume !(1 == ~T10_E~0); {122447#false} is VALID [2022-02-21 04:23:45,116 INFO L290 TraceCheckUtils]: 143: Hoare triple {122447#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {122447#false} is VALID [2022-02-21 04:23:45,116 INFO L290 TraceCheckUtils]: 144: Hoare triple {122447#false} assume !(1 == ~T12_E~0); {122447#false} is VALID [2022-02-21 04:23:45,116 INFO L290 TraceCheckUtils]: 145: Hoare triple {122447#false} assume !(1 == ~T13_E~0); {122447#false} is VALID [2022-02-21 04:23:45,116 INFO L290 TraceCheckUtils]: 146: Hoare triple {122447#false} assume !(1 == ~E_M~0); {122447#false} is VALID [2022-02-21 04:23:45,117 INFO L290 TraceCheckUtils]: 147: Hoare triple {122447#false} assume !(1 == ~E_1~0); {122447#false} is VALID [2022-02-21 04:23:45,117 INFO L290 TraceCheckUtils]: 148: Hoare triple {122447#false} assume !(1 == ~E_2~0); {122447#false} is VALID [2022-02-21 04:23:45,117 INFO L290 TraceCheckUtils]: 149: Hoare triple {122447#false} assume !(1 == ~E_3~0); {122447#false} is VALID [2022-02-21 04:23:45,117 INFO L290 TraceCheckUtils]: 150: Hoare triple {122447#false} assume !(1 == ~E_4~0); {122447#false} is VALID [2022-02-21 04:23:45,117 INFO L290 TraceCheckUtils]: 151: Hoare triple {122447#false} assume 1 == ~E_5~0;~E_5~0 := 2; {122447#false} is VALID [2022-02-21 04:23:45,117 INFO L290 TraceCheckUtils]: 152: Hoare triple {122447#false} assume !(1 == ~E_6~0); {122447#false} is VALID [2022-02-21 04:23:45,117 INFO L290 TraceCheckUtils]: 153: Hoare triple {122447#false} assume !(1 == ~E_7~0); {122447#false} is VALID [2022-02-21 04:23:45,117 INFO L290 TraceCheckUtils]: 154: Hoare triple {122447#false} assume !(1 == ~E_8~0); {122447#false} is VALID [2022-02-21 04:23:45,118 INFO L290 TraceCheckUtils]: 155: Hoare triple {122447#false} assume !(1 == ~E_9~0); {122447#false} is VALID [2022-02-21 04:23:45,118 INFO L290 TraceCheckUtils]: 156: Hoare triple {122447#false} assume !(1 == ~E_10~0); {122447#false} is VALID [2022-02-21 04:23:45,118 INFO L290 TraceCheckUtils]: 157: Hoare triple {122447#false} assume !(1 == ~E_11~0); {122447#false} is VALID [2022-02-21 04:23:45,118 INFO L290 TraceCheckUtils]: 158: Hoare triple {122447#false} assume !(1 == ~E_12~0); {122447#false} is VALID [2022-02-21 04:23:45,118 INFO L290 TraceCheckUtils]: 159: Hoare triple {122447#false} assume 1 == ~E_13~0;~E_13~0 := 2; {122447#false} is VALID [2022-02-21 04:23:45,118 INFO L290 TraceCheckUtils]: 160: Hoare triple {122447#false} assume { :end_inline_reset_delta_events } true; {122447#false} is VALID [2022-02-21 04:23:45,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:45,119 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:45,119 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [887534416] [2022-02-21 04:23:45,119 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [887534416] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:45,119 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:45,119 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:45,120 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605367126] [2022-02-21 04:23:45,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:45,120 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:45,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:45,121 INFO L85 PathProgramCache]: Analyzing trace with hash -1289653276, now seen corresponding path program 1 times [2022-02-21 04:23:45,121 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:45,121 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534192875] [2022-02-21 04:23:45,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:45,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:45,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:45,160 INFO L290 TraceCheckUtils]: 0: Hoare triple {122450#true} assume !false; {122450#true} is VALID [2022-02-21 04:23:45,160 INFO L290 TraceCheckUtils]: 1: Hoare triple {122450#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {122450#true} is VALID [2022-02-21 04:23:45,160 INFO L290 TraceCheckUtils]: 2: Hoare triple {122450#true} assume !false; {122450#true} is VALID [2022-02-21 04:23:45,161 INFO L290 TraceCheckUtils]: 3: Hoare triple {122450#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {122450#true} is VALID [2022-02-21 04:23:45,161 INFO L290 TraceCheckUtils]: 4: Hoare triple {122450#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {122450#true} is VALID [2022-02-21 04:23:45,161 INFO L290 TraceCheckUtils]: 5: Hoare triple {122450#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {122450#true} is VALID [2022-02-21 04:23:45,161 INFO L290 TraceCheckUtils]: 6: Hoare triple {122450#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {122450#true} is VALID [2022-02-21 04:23:45,161 INFO L290 TraceCheckUtils]: 7: Hoare triple {122450#true} assume !(0 != eval_~tmp~0#1); {122450#true} is VALID [2022-02-21 04:23:45,161 INFO L290 TraceCheckUtils]: 8: Hoare triple {122450#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {122450#true} is VALID [2022-02-21 04:23:45,161 INFO L290 TraceCheckUtils]: 9: Hoare triple {122450#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {122450#true} is VALID [2022-02-21 04:23:45,162 INFO L290 TraceCheckUtils]: 10: Hoare triple {122450#true} assume !(0 == ~M_E~0); {122450#true} is VALID [2022-02-21 04:23:45,162 INFO L290 TraceCheckUtils]: 11: Hoare triple {122450#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {122450#true} is VALID [2022-02-21 04:23:45,162 INFO L290 TraceCheckUtils]: 12: Hoare triple {122450#true} assume !(0 == ~T2_E~0); {122450#true} is VALID [2022-02-21 04:23:45,162 INFO L290 TraceCheckUtils]: 13: Hoare triple {122450#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {122450#true} is VALID [2022-02-21 04:23:45,162 INFO L290 TraceCheckUtils]: 14: Hoare triple {122450#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {122450#true} is VALID [2022-02-21 04:23:45,162 INFO L290 TraceCheckUtils]: 15: Hoare triple {122450#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,163 INFO L290 TraceCheckUtils]: 16: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,163 INFO L290 TraceCheckUtils]: 17: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,164 INFO L290 TraceCheckUtils]: 18: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,164 INFO L290 TraceCheckUtils]: 19: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,164 INFO L290 TraceCheckUtils]: 20: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,165 INFO L290 TraceCheckUtils]: 21: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,165 INFO L290 TraceCheckUtils]: 22: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,166 INFO L290 TraceCheckUtils]: 23: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,166 INFO L290 TraceCheckUtils]: 24: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,166 INFO L290 TraceCheckUtils]: 25: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,167 INFO L290 TraceCheckUtils]: 26: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,167 INFO L290 TraceCheckUtils]: 27: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,168 INFO L290 TraceCheckUtils]: 28: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,168 INFO L290 TraceCheckUtils]: 29: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,168 INFO L290 TraceCheckUtils]: 30: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,169 INFO L290 TraceCheckUtils]: 31: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,169 INFO L290 TraceCheckUtils]: 32: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,169 INFO L290 TraceCheckUtils]: 33: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,170 INFO L290 TraceCheckUtils]: 34: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,170 INFO L290 TraceCheckUtils]: 35: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,171 INFO L290 TraceCheckUtils]: 36: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,171 INFO L290 TraceCheckUtils]: 37: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,171 INFO L290 TraceCheckUtils]: 38: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,172 INFO L290 TraceCheckUtils]: 39: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,172 INFO L290 TraceCheckUtils]: 40: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,173 INFO L290 TraceCheckUtils]: 41: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,173 INFO L290 TraceCheckUtils]: 42: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,173 INFO L290 TraceCheckUtils]: 43: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,174 INFO L290 TraceCheckUtils]: 44: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,174 INFO L290 TraceCheckUtils]: 45: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,174 INFO L290 TraceCheckUtils]: 46: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,175 INFO L290 TraceCheckUtils]: 47: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,175 INFO L290 TraceCheckUtils]: 48: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,176 INFO L290 TraceCheckUtils]: 49: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,176 INFO L290 TraceCheckUtils]: 50: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,179 INFO L290 TraceCheckUtils]: 51: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,180 INFO L290 TraceCheckUtils]: 52: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,180 INFO L290 TraceCheckUtils]: 53: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,181 INFO L290 TraceCheckUtils]: 54: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,181 INFO L290 TraceCheckUtils]: 55: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,181 INFO L290 TraceCheckUtils]: 56: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,182 INFO L290 TraceCheckUtils]: 57: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,182 INFO L290 TraceCheckUtils]: 58: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,183 INFO L290 TraceCheckUtils]: 59: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,183 INFO L290 TraceCheckUtils]: 60: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,183 INFO L290 TraceCheckUtils]: 61: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,184 INFO L290 TraceCheckUtils]: 62: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,184 INFO L290 TraceCheckUtils]: 63: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,185 INFO L290 TraceCheckUtils]: 64: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,185 INFO L290 TraceCheckUtils]: 65: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,185 INFO L290 TraceCheckUtils]: 66: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,186 INFO L290 TraceCheckUtils]: 67: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,186 INFO L290 TraceCheckUtils]: 68: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,187 INFO L290 TraceCheckUtils]: 69: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,187 INFO L290 TraceCheckUtils]: 70: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,187 INFO L290 TraceCheckUtils]: 71: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,188 INFO L290 TraceCheckUtils]: 72: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,188 INFO L290 TraceCheckUtils]: 73: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,188 INFO L290 TraceCheckUtils]: 74: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,189 INFO L290 TraceCheckUtils]: 75: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,189 INFO L290 TraceCheckUtils]: 76: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,190 INFO L290 TraceCheckUtils]: 77: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,190 INFO L290 TraceCheckUtils]: 78: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,190 INFO L290 TraceCheckUtils]: 79: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,191 INFO L290 TraceCheckUtils]: 80: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,191 INFO L290 TraceCheckUtils]: 81: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,191 INFO L290 TraceCheckUtils]: 82: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,192 INFO L290 TraceCheckUtils]: 83: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,192 INFO L290 TraceCheckUtils]: 84: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,193 INFO L290 TraceCheckUtils]: 85: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,193 INFO L290 TraceCheckUtils]: 86: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,193 INFO L290 TraceCheckUtils]: 87: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,194 INFO L290 TraceCheckUtils]: 88: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,194 INFO L290 TraceCheckUtils]: 89: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,194 INFO L290 TraceCheckUtils]: 90: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,195 INFO L290 TraceCheckUtils]: 91: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,195 INFO L290 TraceCheckUtils]: 92: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,196 INFO L290 TraceCheckUtils]: 93: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,196 INFO L290 TraceCheckUtils]: 94: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,196 INFO L290 TraceCheckUtils]: 95: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,197 INFO L290 TraceCheckUtils]: 96: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,197 INFO L290 TraceCheckUtils]: 97: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,198 INFO L290 TraceCheckUtils]: 98: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,198 INFO L290 TraceCheckUtils]: 99: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,198 INFO L290 TraceCheckUtils]: 100: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,199 INFO L290 TraceCheckUtils]: 101: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,199 INFO L290 TraceCheckUtils]: 102: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,199 INFO L290 TraceCheckUtils]: 103: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,200 INFO L290 TraceCheckUtils]: 104: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,200 INFO L290 TraceCheckUtils]: 105: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,201 INFO L290 TraceCheckUtils]: 106: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,201 INFO L290 TraceCheckUtils]: 107: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,201 INFO L290 TraceCheckUtils]: 108: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,202 INFO L290 TraceCheckUtils]: 109: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,202 INFO L290 TraceCheckUtils]: 110: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,202 INFO L290 TraceCheckUtils]: 111: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t12_pc~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,203 INFO L290 TraceCheckUtils]: 112: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,203 INFO L290 TraceCheckUtils]: 113: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,204 INFO L290 TraceCheckUtils]: 114: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,204 INFO L290 TraceCheckUtils]: 115: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,204 INFO L290 TraceCheckUtils]: 116: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,205 INFO L290 TraceCheckUtils]: 117: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,205 INFO L290 TraceCheckUtils]: 118: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,205 INFO L290 TraceCheckUtils]: 119: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,206 INFO L290 TraceCheckUtils]: 120: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,206 INFO L290 TraceCheckUtils]: 121: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,207 INFO L290 TraceCheckUtils]: 122: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,207 INFO L290 TraceCheckUtils]: 123: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~M_E~0); {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,207 INFO L290 TraceCheckUtils]: 124: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,208 INFO L290 TraceCheckUtils]: 125: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,208 INFO L290 TraceCheckUtils]: 126: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,209 INFO L290 TraceCheckUtils]: 127: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {122452#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:45,209 INFO L290 TraceCheckUtils]: 128: Hoare triple {122452#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {122451#false} is VALID [2022-02-21 04:23:45,209 INFO L290 TraceCheckUtils]: 129: Hoare triple {122451#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,209 INFO L290 TraceCheckUtils]: 130: Hoare triple {122451#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,209 INFO L290 TraceCheckUtils]: 131: Hoare triple {122451#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,209 INFO L290 TraceCheckUtils]: 132: Hoare triple {122451#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,210 INFO L290 TraceCheckUtils]: 133: Hoare triple {122451#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,210 INFO L290 TraceCheckUtils]: 134: Hoare triple {122451#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,210 INFO L290 TraceCheckUtils]: 135: Hoare triple {122451#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,210 INFO L290 TraceCheckUtils]: 136: Hoare triple {122451#false} assume !(1 == ~T13_E~0); {122451#false} is VALID [2022-02-21 04:23:45,210 INFO L290 TraceCheckUtils]: 137: Hoare triple {122451#false} assume 1 == ~E_M~0;~E_M~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,210 INFO L290 TraceCheckUtils]: 138: Hoare triple {122451#false} assume 1 == ~E_1~0;~E_1~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,210 INFO L290 TraceCheckUtils]: 139: Hoare triple {122451#false} assume 1 == ~E_2~0;~E_2~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,210 INFO L290 TraceCheckUtils]: 140: Hoare triple {122451#false} assume 1 == ~E_3~0;~E_3~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,211 INFO L290 TraceCheckUtils]: 141: Hoare triple {122451#false} assume 1 == ~E_4~0;~E_4~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,211 INFO L290 TraceCheckUtils]: 142: Hoare triple {122451#false} assume 1 == ~E_5~0;~E_5~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,211 INFO L290 TraceCheckUtils]: 143: Hoare triple {122451#false} assume 1 == ~E_6~0;~E_6~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,211 INFO L290 TraceCheckUtils]: 144: Hoare triple {122451#false} assume !(1 == ~E_7~0); {122451#false} is VALID [2022-02-21 04:23:45,211 INFO L290 TraceCheckUtils]: 145: Hoare triple {122451#false} assume 1 == ~E_8~0;~E_8~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,211 INFO L290 TraceCheckUtils]: 146: Hoare triple {122451#false} assume 1 == ~E_9~0;~E_9~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,211 INFO L290 TraceCheckUtils]: 147: Hoare triple {122451#false} assume 1 == ~E_10~0;~E_10~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,212 INFO L290 TraceCheckUtils]: 148: Hoare triple {122451#false} assume 1 == ~E_11~0;~E_11~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,212 INFO L290 TraceCheckUtils]: 149: Hoare triple {122451#false} assume 1 == ~E_12~0;~E_12~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,212 INFO L290 TraceCheckUtils]: 150: Hoare triple {122451#false} assume 1 == ~E_13~0;~E_13~0 := 2; {122451#false} is VALID [2022-02-21 04:23:45,212 INFO L290 TraceCheckUtils]: 151: Hoare triple {122451#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {122451#false} is VALID [2022-02-21 04:23:45,212 INFO L290 TraceCheckUtils]: 152: Hoare triple {122451#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {122451#false} is VALID [2022-02-21 04:23:45,212 INFO L290 TraceCheckUtils]: 153: Hoare triple {122451#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {122451#false} is VALID [2022-02-21 04:23:45,212 INFO L290 TraceCheckUtils]: 154: Hoare triple {122451#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {122451#false} is VALID [2022-02-21 04:23:45,212 INFO L290 TraceCheckUtils]: 155: Hoare triple {122451#false} assume !(0 == start_simulation_~tmp~3#1); {122451#false} is VALID [2022-02-21 04:23:45,213 INFO L290 TraceCheckUtils]: 156: Hoare triple {122451#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {122451#false} is VALID [2022-02-21 04:23:45,213 INFO L290 TraceCheckUtils]: 157: Hoare triple {122451#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {122451#false} is VALID [2022-02-21 04:23:45,213 INFO L290 TraceCheckUtils]: 158: Hoare triple {122451#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {122451#false} is VALID [2022-02-21 04:23:45,213 INFO L290 TraceCheckUtils]: 159: Hoare triple {122451#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {122451#false} is VALID [2022-02-21 04:23:45,213 INFO L290 TraceCheckUtils]: 160: Hoare triple {122451#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {122451#false} is VALID [2022-02-21 04:23:45,213 INFO L290 TraceCheckUtils]: 161: Hoare triple {122451#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {122451#false} is VALID [2022-02-21 04:23:45,213 INFO L290 TraceCheckUtils]: 162: Hoare triple {122451#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {122451#false} is VALID [2022-02-21 04:23:45,214 INFO L290 TraceCheckUtils]: 163: Hoare triple {122451#false} assume !(0 != start_simulation_~tmp___0~1#1); {122451#false} is VALID [2022-02-21 04:23:45,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:45,214 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:45,214 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534192875] [2022-02-21 04:23:45,215 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534192875] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:45,215 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:45,216 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:45,216 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442676183] [2022-02-21 04:23:45,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:45,216 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:45,216 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:45,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:45,217 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:45,217 INFO L87 Difference]: Start difference. First operand 3771 states and 5546 transitions. cyclomatic complexity: 1776 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:49,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:49,649 INFO L93 Difference]: Finished difference Result 5511 states and 8090 transitions. [2022-02-21 04:23:49,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:49,650 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:49,754 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:49,755 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5511 states and 8090 transitions. [2022-02-21 04:23:50,434 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5316 [2022-02-21 04:23:51,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5511 states to 5511 states and 8090 transitions. [2022-02-21 04:23:51,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5511 [2022-02-21 04:23:51,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5511 [2022-02-21 04:23:51,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5511 states and 8090 transitions. [2022-02-21 04:23:51,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:51,160 INFO L681 BuchiCegarLoop]: Abstraction has 5511 states and 8090 transitions. [2022-02-21 04:23:51,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5511 states and 8090 transitions. [2022-02-21 04:23:51,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5511 to 3771. [2022-02-21 04:23:51,227 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:51,231 INFO L82 GeneralOperation]: Start isEquivalent. First operand 5511 states and 8090 transitions. Second operand has 3771 states, 3771 states have (on average 1.469901882789711) internal successors, (5543), 3770 states have internal predecessors, (5543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:51,234 INFO L74 IsIncluded]: Start isIncluded. First operand 5511 states and 8090 transitions. Second operand has 3771 states, 3771 states have (on average 1.469901882789711) internal successors, (5543), 3770 states have internal predecessors, (5543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:51,236 INFO L87 Difference]: Start difference. First operand 5511 states and 8090 transitions. Second operand has 3771 states, 3771 states have (on average 1.469901882789711) internal successors, (5543), 3770 states have internal predecessors, (5543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:51,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:51,888 INFO L93 Difference]: Finished difference Result 5511 states and 8090 transitions. [2022-02-21 04:23:51,889 INFO L276 IsEmpty]: Start isEmpty. Operand 5511 states and 8090 transitions. [2022-02-21 04:23:51,894 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:51,894 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:51,898 INFO L74 IsIncluded]: Start isIncluded. First operand has 3771 states, 3771 states have (on average 1.469901882789711) internal successors, (5543), 3770 states have internal predecessors, (5543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5511 states and 8090 transitions. [2022-02-21 04:23:51,900 INFO L87 Difference]: Start difference. First operand has 3771 states, 3771 states have (on average 1.469901882789711) internal successors, (5543), 3770 states have internal predecessors, (5543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5511 states and 8090 transitions. [2022-02-21 04:23:52,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:52,517 INFO L93 Difference]: Finished difference Result 5511 states and 8090 transitions. [2022-02-21 04:23:52,517 INFO L276 IsEmpty]: Start isEmpty. Operand 5511 states and 8090 transitions. [2022-02-21 04:23:52,521 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:52,521 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:52,521 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:52,521 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:52,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.469901882789711) internal successors, (5543), 3770 states have internal predecessors, (5543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:52,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5543 transitions. [2022-02-21 04:23:52,841 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5543 transitions. [2022-02-21 04:23:52,841 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5543 transitions. [2022-02-21 04:23:52,841 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:23:52,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5543 transitions. [2022-02-21 04:23:52,847 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-02-21 04:23:52,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:52,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:52,848 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:52,848 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:52,849 INFO L791 eck$LassoCheckResult]: Stem: 128894#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 128895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 129896#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 129897#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 129984#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 129358#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 128826#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 128827#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 129646#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 129647#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 129747#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 129748#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 128601#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 128602#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 129777#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 129135#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 129136#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 129697#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 129038#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 129039#L1291 assume !(0 == ~M_E~0); 129985#L1291-2 assume !(0 == ~T1_E~0); 129983#L1296-1 assume !(0 == ~T2_E~0); 129194#L1301-1 assume !(0 == ~T3_E~0); 129195#L1306-1 assume !(0 == ~T4_E~0); 129706#L1311-1 assume !(0 == ~T5_E~0); 128441#L1316-1 assume !(0 == ~T6_E~0); 128442#L1321-1 assume !(0 == ~T7_E~0); 129207#L1326-1 assume !(0 == ~T8_E~0); 128269#L1331-1 assume !(0 == ~T9_E~0); 127968#L1336-1 assume !(0 == ~T10_E~0); 127969#L1341-1 assume !(0 == ~T11_E~0); 128049#L1346-1 assume !(0 == ~T12_E~0); 128050#L1351-1 assume !(0 == ~T13_E~0); 128390#L1356-1 assume !(0 == ~E_M~0); 128391#L1361-1 assume !(0 == ~E_1~0); 129924#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 128431#L1371-1 assume !(0 == ~E_3~0); 128432#L1376-1 assume !(0 == ~E_4~0); 129254#L1381-1 assume !(0 == ~E_5~0); 129255#L1386-1 assume !(0 == ~E_6~0); 129954#L1391-1 assume !(0 == ~E_7~0); 129972#L1396-1 assume !(0 == ~E_8~0); 129167#L1401-1 assume !(0 == ~E_9~0); 129168#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 129446#L1411-1 assume !(0 == ~E_11~0); 129447#L1416-1 assume !(0 == ~E_12~0); 129079#L1421-1 assume !(0 == ~E_13~0); 128625#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 128626#L640 assume !(1 == ~m_pc~0); 129132#L640-2 is_master_triggered_~__retres1~0#1 := 0; 129131#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 129223#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 129117#L1603 assume !(0 != activate_threads_~tmp~1#1); 129118#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 128751#L659 assume 1 == ~t1_pc~0; 128752#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 128858#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129806#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 128878#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 128879#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128892#L678 assume 1 == ~t2_pc~0; 129848#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 129849#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 129951#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 128990#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 128991#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 129112#L697 assume !(1 == ~t3_pc~0); 129113#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 129235#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 129043#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 129022#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 129023#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 129886#L716 assume 1 == ~t4_pc~0; 129872#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 128734#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 128735#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 128232#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 128233#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 129527#L735 assume !(1 == ~t5_pc~0); 128193#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 128194#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 128644#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 129555#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 129188#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 129189#L754 assume 1 == ~t6_pc~0; 128944#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 128840#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 128841#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 128813#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 128814#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 129636#L773 assume !(1 == ~t7_pc~0); 128394#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 128393#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 129224#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 129196#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 129197#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 129244#L792 assume 1 == ~t8_pc~0; 129419#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 129751#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 129238#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 129192#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 129115#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 129116#L811 assume 1 == ~t9_pc~0; 129321#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 129788#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 129663#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 129316#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 129128#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 129129#L830 assume !(1 == ~t10_pc~0); 128852#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 128373#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 128066#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 128067#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 128354#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 129654#L849 assume 1 == ~t11_pc~0; 129655#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 128169#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 128170#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 128761#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 129562#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 129563#L868 assume !(1 == ~t12_pc~0); 128975#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 128974#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 128768#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 128769#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 128405#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 128406#L887 assume 1 == ~t13_pc~0; 129575#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 129016#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 129017#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 129453#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 128109#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128110#L1439 assume !(1 == ~M_E~0); 129186#L1439-2 assume !(1 == ~T1_E~0); 128281#L1444-1 assume !(1 == ~T2_E~0); 128282#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 128757#L1454-1 assume !(1 == ~T4_E~0); 128758#L1459-1 assume !(1 == ~T5_E~0); 129313#L1464-1 assume !(1 == ~T6_E~0); 129314#L1469-1 assume !(1 == ~T7_E~0); 129389#L1474-1 assume !(1 == ~T8_E~0); 129080#L1479-1 assume !(1 == ~T9_E~0); 129081#L1484-1 assume !(1 == ~T10_E~0); 129317#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 128966#L1494-1 assume !(1 == ~T12_E~0); 128967#L1499-1 assume !(1 == ~T13_E~0); 129156#L1504-1 assume !(1 == ~E_M~0); 129157#L1509-1 assume !(1 == ~E_1~0); 129733#L1514-1 assume !(1 == ~E_2~0); 129421#L1519-1 assume !(1 == ~E_3~0); 129422#L1524-1 assume !(1 == ~E_4~0); 129937#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 129938#L1534-1 assume !(1 == ~E_6~0); 128102#L1539-1 assume !(1 == ~E_7~0); 128103#L1544-1 assume !(1 == ~E_8~0); 128517#L1549-1 assume !(1 == ~E_9~0); 129916#L1554-1 assume !(1 == ~E_10~0); 129909#L1559-1 assume !(1 == ~E_11~0); 129772#L1564-1 assume !(1 == ~E_12~0); 129773#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 129933#L1574-1 assume { :end_inline_reset_delta_events } true; 128279#L1940-2 [2022-02-21 04:23:52,849 INFO L793 eck$LassoCheckResult]: Loop: 128279#L1940-2 assume !false; 128280#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128562#L1266 assume !false; 129584#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 128810#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 128543#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 128937#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 128938#L1079 assume !(0 != eval_~tmp~0#1); 128897#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 128898#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 129503#L1291-3 assume !(0 == ~M_E~0); 129387#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 129388#L1296-3 assume !(0 == ~T2_E~0); 129965#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 129919#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 129045#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 128320#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 128321#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 128422#L1326-3 assume !(0 == ~T8_E~0); 129179#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 129428#L1336-3 assume !(0 == ~T10_E~0); 129429#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 128748#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 128728#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 128673#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 128674#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 129236#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 128024#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 128025#L1376-3 assume !(0 == ~E_4~0); 129757#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 129616#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 129617#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 129780#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 129781#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 128387#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 128241#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 128242#L1416-3 assume !(0 == ~E_12~0); 128904#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 128905#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129012#L640-45 assume !(1 == ~m_pc~0); 129013#L640-47 is_master_triggered_~__retres1~0#1 := 0; 128478#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128479#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 128018#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 128019#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 128117#L659-45 assume !(1 == ~t1_pc~0); 128119#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 128555#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129518#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 129519#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 129540#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129541#L678-45 assume !(1 == ~t2_pc~0); 129485#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 129018#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 129019#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 129171#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 129798#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 129918#L697-45 assume 1 == ~t3_pc~0; 129276#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 129277#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 129867#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 129435#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 129436#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 129466#L716-45 assume 1 == ~t4_pc~0; 129097#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 129098#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 129649#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 129103#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 129104#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128765#L735-45 assume !(1 == ~t5_pc~0); 128767#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 129310#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 129875#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 129876#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 129936#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 129931#L754-45 assume 1 == ~t6_pc~0; 129258#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 129259#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 128687#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 128688#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 129262#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 128994#L773-45 assume 1 == ~t7_pc~0; 128995#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 128551#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 129473#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 129756#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 129000#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 128669#L792-45 assume !(1 == ~t8_pc~0); 128671#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 129700#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 128272#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 128131#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 128132#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 128627#L811-45 assume !(1 == ~t9_pc~0); 128417#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 128418#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 129628#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 129462#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 129071#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 128863#L830-45 assume 1 == ~t10_pc~0; 128864#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 128060#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 129183#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 128292#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 128293#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 128038#L849-45 assume !(1 == ~t11_pc~0); 128039#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 128498#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 128129#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 128026#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 128027#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 128285#L868-45 assume !(1 == ~t12_pc~0); 128287#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 128225#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 128226#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 129566#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 129818#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 129819#L887-45 assume 1 == ~t13_pc~0; 129648#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 128295#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 129579#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 129928#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 128257#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128258#L1439-3 assume !(1 == ~M_E~0); 129567#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 128277#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 128278#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 128435#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 129367#L1459-3 assume !(1 == ~T5_E~0); 129368#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 129821#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 129760#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 129761#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 129822#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 129050#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 129051#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 129690#L1499-3 assume !(1 == ~T13_E~0); 129328#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 129329#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 129769#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 129799#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 128971#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 128972#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 129841#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 129239#L1539-3 assume !(1 == ~E_7~0); 128714#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 128715#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 129210#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 128331#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 128332#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 129467#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 129468#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 128208#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 127979#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 128254#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 128215#L1959 assume !(0 == start_simulation_~tmp~3#1); 128217#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 128249#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 128199#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 129510#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 129631#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 129839#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129853#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 129854#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 128279#L1940-2 [2022-02-21 04:23:52,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:52,850 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2022-02-21 04:23:52,850 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:52,850 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232721658] [2022-02-21 04:23:52,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:52,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:52,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:52,882 INFO L290 TraceCheckUtils]: 0: Hoare triple {142762#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,882 INFO L290 TraceCheckUtils]: 1: Hoare triple {142764#(<= 2 ~E_2~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,882 INFO L290 TraceCheckUtils]: 2: Hoare triple {142764#(<= 2 ~E_2~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,883 INFO L290 TraceCheckUtils]: 3: Hoare triple {142764#(<= 2 ~E_2~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,883 INFO L290 TraceCheckUtils]: 4: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,883 INFO L290 TraceCheckUtils]: 5: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,884 INFO L290 TraceCheckUtils]: 6: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,884 INFO L290 TraceCheckUtils]: 7: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,884 INFO L290 TraceCheckUtils]: 8: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,885 INFO L290 TraceCheckUtils]: 9: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,885 INFO L290 TraceCheckUtils]: 10: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,885 INFO L290 TraceCheckUtils]: 11: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,886 INFO L290 TraceCheckUtils]: 12: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,886 INFO L290 TraceCheckUtils]: 13: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,886 INFO L290 TraceCheckUtils]: 14: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,887 INFO L290 TraceCheckUtils]: 15: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,887 INFO L290 TraceCheckUtils]: 16: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,887 INFO L290 TraceCheckUtils]: 17: Hoare triple {142764#(<= 2 ~E_2~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,888 INFO L290 TraceCheckUtils]: 18: Hoare triple {142764#(<= 2 ~E_2~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,888 INFO L290 TraceCheckUtils]: 19: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~M_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,888 INFO L290 TraceCheckUtils]: 20: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T1_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,888 INFO L290 TraceCheckUtils]: 21: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T2_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,889 INFO L290 TraceCheckUtils]: 22: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T3_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,889 INFO L290 TraceCheckUtils]: 23: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T4_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,889 INFO L290 TraceCheckUtils]: 24: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T5_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,890 INFO L290 TraceCheckUtils]: 25: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T6_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,890 INFO L290 TraceCheckUtils]: 26: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T7_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,890 INFO L290 TraceCheckUtils]: 27: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T8_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,891 INFO L290 TraceCheckUtils]: 28: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T9_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,891 INFO L290 TraceCheckUtils]: 29: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T10_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,891 INFO L290 TraceCheckUtils]: 30: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T11_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,892 INFO L290 TraceCheckUtils]: 31: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T12_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,892 INFO L290 TraceCheckUtils]: 32: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~T13_E~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,892 INFO L290 TraceCheckUtils]: 33: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~E_M~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,893 INFO L290 TraceCheckUtils]: 34: Hoare triple {142764#(<= 2 ~E_2~0)} assume !(0 == ~E_1~0); {142764#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:52,893 INFO L290 TraceCheckUtils]: 35: Hoare triple {142764#(<= 2 ~E_2~0)} assume 0 == ~E_2~0;~E_2~0 := 1; {142763#false} is VALID [2022-02-21 04:23:52,893 INFO L290 TraceCheckUtils]: 36: Hoare triple {142763#false} assume !(0 == ~E_3~0); {142763#false} is VALID [2022-02-21 04:23:52,893 INFO L290 TraceCheckUtils]: 37: Hoare triple {142763#false} assume !(0 == ~E_4~0); {142763#false} is VALID [2022-02-21 04:23:52,893 INFO L290 TraceCheckUtils]: 38: Hoare triple {142763#false} assume !(0 == ~E_5~0); {142763#false} is VALID [2022-02-21 04:23:52,893 INFO L290 TraceCheckUtils]: 39: Hoare triple {142763#false} assume !(0 == ~E_6~0); {142763#false} is VALID [2022-02-21 04:23:52,894 INFO L290 TraceCheckUtils]: 40: Hoare triple {142763#false} assume !(0 == ~E_7~0); {142763#false} is VALID [2022-02-21 04:23:52,894 INFO L290 TraceCheckUtils]: 41: Hoare triple {142763#false} assume !(0 == ~E_8~0); {142763#false} is VALID [2022-02-21 04:23:52,894 INFO L290 TraceCheckUtils]: 42: Hoare triple {142763#false} assume !(0 == ~E_9~0); {142763#false} is VALID [2022-02-21 04:23:52,894 INFO L290 TraceCheckUtils]: 43: Hoare triple {142763#false} assume 0 == ~E_10~0;~E_10~0 := 1; {142763#false} is VALID [2022-02-21 04:23:52,894 INFO L290 TraceCheckUtils]: 44: Hoare triple {142763#false} assume !(0 == ~E_11~0); {142763#false} is VALID [2022-02-21 04:23:52,894 INFO L290 TraceCheckUtils]: 45: Hoare triple {142763#false} assume !(0 == ~E_12~0); {142763#false} is VALID [2022-02-21 04:23:52,894 INFO L290 TraceCheckUtils]: 46: Hoare triple {142763#false} assume !(0 == ~E_13~0); {142763#false} is VALID [2022-02-21 04:23:52,895 INFO L290 TraceCheckUtils]: 47: Hoare triple {142763#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {142763#false} is VALID [2022-02-21 04:23:52,895 INFO L290 TraceCheckUtils]: 48: Hoare triple {142763#false} assume !(1 == ~m_pc~0); {142763#false} is VALID [2022-02-21 04:23:52,895 INFO L290 TraceCheckUtils]: 49: Hoare triple {142763#false} is_master_triggered_~__retres1~0#1 := 0; {142763#false} is VALID [2022-02-21 04:23:52,895 INFO L290 TraceCheckUtils]: 50: Hoare triple {142763#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {142763#false} is VALID [2022-02-21 04:23:52,895 INFO L290 TraceCheckUtils]: 51: Hoare triple {142763#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {142763#false} is VALID [2022-02-21 04:23:52,895 INFO L290 TraceCheckUtils]: 52: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp~1#1); {142763#false} is VALID [2022-02-21 04:23:52,895 INFO L290 TraceCheckUtils]: 53: Hoare triple {142763#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {142763#false} is VALID [2022-02-21 04:23:52,896 INFO L290 TraceCheckUtils]: 54: Hoare triple {142763#false} assume 1 == ~t1_pc~0; {142763#false} is VALID [2022-02-21 04:23:52,896 INFO L290 TraceCheckUtils]: 55: Hoare triple {142763#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {142763#false} is VALID [2022-02-21 04:23:52,896 INFO L290 TraceCheckUtils]: 56: Hoare triple {142763#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {142763#false} is VALID [2022-02-21 04:23:52,896 INFO L290 TraceCheckUtils]: 57: Hoare triple {142763#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {142763#false} is VALID [2022-02-21 04:23:52,896 INFO L290 TraceCheckUtils]: 58: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___0~0#1); {142763#false} is VALID [2022-02-21 04:23:52,896 INFO L290 TraceCheckUtils]: 59: Hoare triple {142763#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {142763#false} is VALID [2022-02-21 04:23:52,896 INFO L290 TraceCheckUtils]: 60: Hoare triple {142763#false} assume 1 == ~t2_pc~0; {142763#false} is VALID [2022-02-21 04:23:52,896 INFO L290 TraceCheckUtils]: 61: Hoare triple {142763#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {142763#false} is VALID [2022-02-21 04:23:52,897 INFO L290 TraceCheckUtils]: 62: Hoare triple {142763#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {142763#false} is VALID [2022-02-21 04:23:52,897 INFO L290 TraceCheckUtils]: 63: Hoare triple {142763#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {142763#false} is VALID [2022-02-21 04:23:52,897 INFO L290 TraceCheckUtils]: 64: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___1~0#1); {142763#false} is VALID [2022-02-21 04:23:52,897 INFO L290 TraceCheckUtils]: 65: Hoare triple {142763#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {142763#false} is VALID [2022-02-21 04:23:52,897 INFO L290 TraceCheckUtils]: 66: Hoare triple {142763#false} assume !(1 == ~t3_pc~0); {142763#false} is VALID [2022-02-21 04:23:52,897 INFO L290 TraceCheckUtils]: 67: Hoare triple {142763#false} is_transmit3_triggered_~__retres1~3#1 := 0; {142763#false} is VALID [2022-02-21 04:23:52,897 INFO L290 TraceCheckUtils]: 68: Hoare triple {142763#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {142763#false} is VALID [2022-02-21 04:23:52,898 INFO L290 TraceCheckUtils]: 69: Hoare triple {142763#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {142763#false} is VALID [2022-02-21 04:23:52,898 INFO L290 TraceCheckUtils]: 70: Hoare triple {142763#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {142763#false} is VALID [2022-02-21 04:23:52,898 INFO L290 TraceCheckUtils]: 71: Hoare triple {142763#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {142763#false} is VALID [2022-02-21 04:23:52,898 INFO L290 TraceCheckUtils]: 72: Hoare triple {142763#false} assume 1 == ~t4_pc~0; {142763#false} is VALID [2022-02-21 04:23:52,898 INFO L290 TraceCheckUtils]: 73: Hoare triple {142763#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {142763#false} is VALID [2022-02-21 04:23:52,898 INFO L290 TraceCheckUtils]: 74: Hoare triple {142763#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {142763#false} is VALID [2022-02-21 04:23:52,898 INFO L290 TraceCheckUtils]: 75: Hoare triple {142763#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {142763#false} is VALID [2022-02-21 04:23:52,899 INFO L290 TraceCheckUtils]: 76: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___3~0#1); {142763#false} is VALID [2022-02-21 04:23:52,899 INFO L290 TraceCheckUtils]: 77: Hoare triple {142763#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {142763#false} is VALID [2022-02-21 04:23:52,899 INFO L290 TraceCheckUtils]: 78: Hoare triple {142763#false} assume !(1 == ~t5_pc~0); {142763#false} is VALID [2022-02-21 04:23:52,899 INFO L290 TraceCheckUtils]: 79: Hoare triple {142763#false} is_transmit5_triggered_~__retres1~5#1 := 0; {142763#false} is VALID [2022-02-21 04:23:52,899 INFO L290 TraceCheckUtils]: 80: Hoare triple {142763#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {142763#false} is VALID [2022-02-21 04:23:52,899 INFO L290 TraceCheckUtils]: 81: Hoare triple {142763#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {142763#false} is VALID [2022-02-21 04:23:52,899 INFO L290 TraceCheckUtils]: 82: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___4~0#1); {142763#false} is VALID [2022-02-21 04:23:52,900 INFO L290 TraceCheckUtils]: 83: Hoare triple {142763#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {142763#false} is VALID [2022-02-21 04:23:52,900 INFO L290 TraceCheckUtils]: 84: Hoare triple {142763#false} assume 1 == ~t6_pc~0; {142763#false} is VALID [2022-02-21 04:23:52,900 INFO L290 TraceCheckUtils]: 85: Hoare triple {142763#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {142763#false} is VALID [2022-02-21 04:23:52,900 INFO L290 TraceCheckUtils]: 86: Hoare triple {142763#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {142763#false} is VALID [2022-02-21 04:23:52,900 INFO L290 TraceCheckUtils]: 87: Hoare triple {142763#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {142763#false} is VALID [2022-02-21 04:23:52,900 INFO L290 TraceCheckUtils]: 88: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___5~0#1); {142763#false} is VALID [2022-02-21 04:23:52,900 INFO L290 TraceCheckUtils]: 89: Hoare triple {142763#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {142763#false} is VALID [2022-02-21 04:23:52,900 INFO L290 TraceCheckUtils]: 90: Hoare triple {142763#false} assume !(1 == ~t7_pc~0); {142763#false} is VALID [2022-02-21 04:23:52,901 INFO L290 TraceCheckUtils]: 91: Hoare triple {142763#false} is_transmit7_triggered_~__retres1~7#1 := 0; {142763#false} is VALID [2022-02-21 04:23:52,901 INFO L290 TraceCheckUtils]: 92: Hoare triple {142763#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {142763#false} is VALID [2022-02-21 04:23:52,901 INFO L290 TraceCheckUtils]: 93: Hoare triple {142763#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {142763#false} is VALID [2022-02-21 04:23:52,901 INFO L290 TraceCheckUtils]: 94: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___6~0#1); {142763#false} is VALID [2022-02-21 04:23:52,901 INFO L290 TraceCheckUtils]: 95: Hoare triple {142763#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {142763#false} is VALID [2022-02-21 04:23:52,901 INFO L290 TraceCheckUtils]: 96: Hoare triple {142763#false} assume 1 == ~t8_pc~0; {142763#false} is VALID [2022-02-21 04:23:52,901 INFO L290 TraceCheckUtils]: 97: Hoare triple {142763#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {142763#false} is VALID [2022-02-21 04:23:52,902 INFO L290 TraceCheckUtils]: 98: Hoare triple {142763#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {142763#false} is VALID [2022-02-21 04:23:52,902 INFO L290 TraceCheckUtils]: 99: Hoare triple {142763#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {142763#false} is VALID [2022-02-21 04:23:52,902 INFO L290 TraceCheckUtils]: 100: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___7~0#1); {142763#false} is VALID [2022-02-21 04:23:52,902 INFO L290 TraceCheckUtils]: 101: Hoare triple {142763#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {142763#false} is VALID [2022-02-21 04:23:52,902 INFO L290 TraceCheckUtils]: 102: Hoare triple {142763#false} assume 1 == ~t9_pc~0; {142763#false} is VALID [2022-02-21 04:23:52,902 INFO L290 TraceCheckUtils]: 103: Hoare triple {142763#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {142763#false} is VALID [2022-02-21 04:23:52,902 INFO L290 TraceCheckUtils]: 104: Hoare triple {142763#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {142763#false} is VALID [2022-02-21 04:23:52,903 INFO L290 TraceCheckUtils]: 105: Hoare triple {142763#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {142763#false} is VALID [2022-02-21 04:23:52,903 INFO L290 TraceCheckUtils]: 106: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___8~0#1); {142763#false} is VALID [2022-02-21 04:23:52,903 INFO L290 TraceCheckUtils]: 107: Hoare triple {142763#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {142763#false} is VALID [2022-02-21 04:23:52,903 INFO L290 TraceCheckUtils]: 108: Hoare triple {142763#false} assume !(1 == ~t10_pc~0); {142763#false} is VALID [2022-02-21 04:23:52,903 INFO L290 TraceCheckUtils]: 109: Hoare triple {142763#false} is_transmit10_triggered_~__retres1~10#1 := 0; {142763#false} is VALID [2022-02-21 04:23:52,903 INFO L290 TraceCheckUtils]: 110: Hoare triple {142763#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {142763#false} is VALID [2022-02-21 04:23:52,903 INFO L290 TraceCheckUtils]: 111: Hoare triple {142763#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {142763#false} is VALID [2022-02-21 04:23:52,903 INFO L290 TraceCheckUtils]: 112: Hoare triple {142763#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {142763#false} is VALID [2022-02-21 04:23:52,904 INFO L290 TraceCheckUtils]: 113: Hoare triple {142763#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {142763#false} is VALID [2022-02-21 04:23:52,904 INFO L290 TraceCheckUtils]: 114: Hoare triple {142763#false} assume 1 == ~t11_pc~0; {142763#false} is VALID [2022-02-21 04:23:52,904 INFO L290 TraceCheckUtils]: 115: Hoare triple {142763#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {142763#false} is VALID [2022-02-21 04:23:52,904 INFO L290 TraceCheckUtils]: 116: Hoare triple {142763#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {142763#false} is VALID [2022-02-21 04:23:52,904 INFO L290 TraceCheckUtils]: 117: Hoare triple {142763#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {142763#false} is VALID [2022-02-21 04:23:52,904 INFO L290 TraceCheckUtils]: 118: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___10~0#1); {142763#false} is VALID [2022-02-21 04:23:52,904 INFO L290 TraceCheckUtils]: 119: Hoare triple {142763#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {142763#false} is VALID [2022-02-21 04:23:52,905 INFO L290 TraceCheckUtils]: 120: Hoare triple {142763#false} assume !(1 == ~t12_pc~0); {142763#false} is VALID [2022-02-21 04:23:52,905 INFO L290 TraceCheckUtils]: 121: Hoare triple {142763#false} is_transmit12_triggered_~__retres1~12#1 := 0; {142763#false} is VALID [2022-02-21 04:23:52,905 INFO L290 TraceCheckUtils]: 122: Hoare triple {142763#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {142763#false} is VALID [2022-02-21 04:23:52,905 INFO L290 TraceCheckUtils]: 123: Hoare triple {142763#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {142763#false} is VALID [2022-02-21 04:23:52,905 INFO L290 TraceCheckUtils]: 124: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___11~0#1); {142763#false} is VALID [2022-02-21 04:23:52,905 INFO L290 TraceCheckUtils]: 125: Hoare triple {142763#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {142763#false} is VALID [2022-02-21 04:23:52,905 INFO L290 TraceCheckUtils]: 126: Hoare triple {142763#false} assume 1 == ~t13_pc~0; {142763#false} is VALID [2022-02-21 04:23:52,905 INFO L290 TraceCheckUtils]: 127: Hoare triple {142763#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {142763#false} is VALID [2022-02-21 04:23:52,905 INFO L290 TraceCheckUtils]: 128: Hoare triple {142763#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {142763#false} is VALID [2022-02-21 04:23:52,905 INFO L290 TraceCheckUtils]: 129: Hoare triple {142763#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 130: Hoare triple {142763#false} assume !(0 != activate_threads_~tmp___12~0#1); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 131: Hoare triple {142763#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 132: Hoare triple {142763#false} assume !(1 == ~M_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 133: Hoare triple {142763#false} assume !(1 == ~T1_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 134: Hoare triple {142763#false} assume !(1 == ~T2_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 135: Hoare triple {142763#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 136: Hoare triple {142763#false} assume !(1 == ~T4_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 137: Hoare triple {142763#false} assume !(1 == ~T5_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 138: Hoare triple {142763#false} assume !(1 == ~T6_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 139: Hoare triple {142763#false} assume !(1 == ~T7_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 140: Hoare triple {142763#false} assume !(1 == ~T8_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 141: Hoare triple {142763#false} assume !(1 == ~T9_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 142: Hoare triple {142763#false} assume !(1 == ~T10_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 143: Hoare triple {142763#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 144: Hoare triple {142763#false} assume !(1 == ~T12_E~0); {142763#false} is VALID [2022-02-21 04:23:52,906 INFO L290 TraceCheckUtils]: 145: Hoare triple {142763#false} assume !(1 == ~T13_E~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 146: Hoare triple {142763#false} assume !(1 == ~E_M~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 147: Hoare triple {142763#false} assume !(1 == ~E_1~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 148: Hoare triple {142763#false} assume !(1 == ~E_2~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 149: Hoare triple {142763#false} assume !(1 == ~E_3~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 150: Hoare triple {142763#false} assume !(1 == ~E_4~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 151: Hoare triple {142763#false} assume 1 == ~E_5~0;~E_5~0 := 2; {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 152: Hoare triple {142763#false} assume !(1 == ~E_6~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 153: Hoare triple {142763#false} assume !(1 == ~E_7~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 154: Hoare triple {142763#false} assume !(1 == ~E_8~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 155: Hoare triple {142763#false} assume !(1 == ~E_9~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 156: Hoare triple {142763#false} assume !(1 == ~E_10~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 157: Hoare triple {142763#false} assume !(1 == ~E_11~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 158: Hoare triple {142763#false} assume !(1 == ~E_12~0); {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 159: Hoare triple {142763#false} assume 1 == ~E_13~0;~E_13~0 := 2; {142763#false} is VALID [2022-02-21 04:23:52,907 INFO L290 TraceCheckUtils]: 160: Hoare triple {142763#false} assume { :end_inline_reset_delta_events } true; {142763#false} is VALID [2022-02-21 04:23:52,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:52,908 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:52,908 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232721658] [2022-02-21 04:23:52,908 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [232721658] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:52,908 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:52,908 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:52,908 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1173532195] [2022-02-21 04:23:52,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:52,909 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:52,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:52,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1323677984, now seen corresponding path program 1 times [2022-02-21 04:23:52,910 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:52,910 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313126532] [2022-02-21 04:23:52,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:52,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:52,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:52,944 INFO L290 TraceCheckUtils]: 0: Hoare triple {142765#true} assume !false; {142765#true} is VALID [2022-02-21 04:23:52,944 INFO L290 TraceCheckUtils]: 1: Hoare triple {142765#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {142765#true} is VALID [2022-02-21 04:23:52,944 INFO L290 TraceCheckUtils]: 2: Hoare triple {142765#true} assume !false; {142765#true} is VALID [2022-02-21 04:23:52,944 INFO L290 TraceCheckUtils]: 3: Hoare triple {142765#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {142765#true} is VALID [2022-02-21 04:23:52,944 INFO L290 TraceCheckUtils]: 4: Hoare triple {142765#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {142765#true} is VALID [2022-02-21 04:23:52,945 INFO L290 TraceCheckUtils]: 5: Hoare triple {142765#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {142765#true} is VALID [2022-02-21 04:23:52,945 INFO L290 TraceCheckUtils]: 6: Hoare triple {142765#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {142765#true} is VALID [2022-02-21 04:23:52,945 INFO L290 TraceCheckUtils]: 7: Hoare triple {142765#true} assume !(0 != eval_~tmp~0#1); {142765#true} is VALID [2022-02-21 04:23:52,945 INFO L290 TraceCheckUtils]: 8: Hoare triple {142765#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {142765#true} is VALID [2022-02-21 04:23:52,945 INFO L290 TraceCheckUtils]: 9: Hoare triple {142765#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {142765#true} is VALID [2022-02-21 04:23:52,945 INFO L290 TraceCheckUtils]: 10: Hoare triple {142765#true} assume !(0 == ~M_E~0); {142765#true} is VALID [2022-02-21 04:23:52,945 INFO L290 TraceCheckUtils]: 11: Hoare triple {142765#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {142765#true} is VALID [2022-02-21 04:23:52,946 INFO L290 TraceCheckUtils]: 12: Hoare triple {142765#true} assume !(0 == ~T2_E~0); {142765#true} is VALID [2022-02-21 04:23:52,946 INFO L290 TraceCheckUtils]: 13: Hoare triple {142765#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {142765#true} is VALID [2022-02-21 04:23:52,946 INFO L290 TraceCheckUtils]: 14: Hoare triple {142765#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {142765#true} is VALID [2022-02-21 04:23:52,946 INFO L290 TraceCheckUtils]: 15: Hoare triple {142765#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,947 INFO L290 TraceCheckUtils]: 16: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,947 INFO L290 TraceCheckUtils]: 17: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,947 INFO L290 TraceCheckUtils]: 18: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T8_E~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,948 INFO L290 TraceCheckUtils]: 19: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,948 INFO L290 TraceCheckUtils]: 20: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,948 INFO L290 TraceCheckUtils]: 21: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,949 INFO L290 TraceCheckUtils]: 22: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,949 INFO L290 TraceCheckUtils]: 23: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,950 INFO L290 TraceCheckUtils]: 24: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,950 INFO L290 TraceCheckUtils]: 25: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,950 INFO L290 TraceCheckUtils]: 26: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,951 INFO L290 TraceCheckUtils]: 27: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,951 INFO L290 TraceCheckUtils]: 28: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,951 INFO L290 TraceCheckUtils]: 29: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,952 INFO L290 TraceCheckUtils]: 30: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,952 INFO L290 TraceCheckUtils]: 31: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,953 INFO L290 TraceCheckUtils]: 32: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,953 INFO L290 TraceCheckUtils]: 33: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,953 INFO L290 TraceCheckUtils]: 34: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,954 INFO L290 TraceCheckUtils]: 35: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,954 INFO L290 TraceCheckUtils]: 36: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,954 INFO L290 TraceCheckUtils]: 37: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,955 INFO L290 TraceCheckUtils]: 38: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,955 INFO L290 TraceCheckUtils]: 39: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,955 INFO L290 TraceCheckUtils]: 40: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,956 INFO L290 TraceCheckUtils]: 41: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,956 INFO L290 TraceCheckUtils]: 42: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,957 INFO L290 TraceCheckUtils]: 43: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,957 INFO L290 TraceCheckUtils]: 44: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,957 INFO L290 TraceCheckUtils]: 45: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,958 INFO L290 TraceCheckUtils]: 46: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,958 INFO L290 TraceCheckUtils]: 47: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,958 INFO L290 TraceCheckUtils]: 48: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,959 INFO L290 TraceCheckUtils]: 49: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,959 INFO L290 TraceCheckUtils]: 50: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,959 INFO L290 TraceCheckUtils]: 51: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,960 INFO L290 TraceCheckUtils]: 52: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,960 INFO L290 TraceCheckUtils]: 53: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,961 INFO L290 TraceCheckUtils]: 54: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,961 INFO L290 TraceCheckUtils]: 55: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,961 INFO L290 TraceCheckUtils]: 56: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,962 INFO L290 TraceCheckUtils]: 57: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,962 INFO L290 TraceCheckUtils]: 58: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,962 INFO L290 TraceCheckUtils]: 59: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,963 INFO L290 TraceCheckUtils]: 60: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,963 INFO L290 TraceCheckUtils]: 61: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,964 INFO L290 TraceCheckUtils]: 62: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,964 INFO L290 TraceCheckUtils]: 63: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,964 INFO L290 TraceCheckUtils]: 64: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,965 INFO L290 TraceCheckUtils]: 65: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,965 INFO L290 TraceCheckUtils]: 66: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,965 INFO L290 TraceCheckUtils]: 67: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,966 INFO L290 TraceCheckUtils]: 68: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,966 INFO L290 TraceCheckUtils]: 69: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,966 INFO L290 TraceCheckUtils]: 70: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,967 INFO L290 TraceCheckUtils]: 71: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,967 INFO L290 TraceCheckUtils]: 72: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,968 INFO L290 TraceCheckUtils]: 73: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,968 INFO L290 TraceCheckUtils]: 74: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,968 INFO L290 TraceCheckUtils]: 75: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,969 INFO L290 TraceCheckUtils]: 76: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,969 INFO L290 TraceCheckUtils]: 77: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,969 INFO L290 TraceCheckUtils]: 78: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,970 INFO L290 TraceCheckUtils]: 79: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,970 INFO L290 TraceCheckUtils]: 80: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,970 INFO L290 TraceCheckUtils]: 81: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,971 INFO L290 TraceCheckUtils]: 82: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,971 INFO L290 TraceCheckUtils]: 83: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,972 INFO L290 TraceCheckUtils]: 84: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,972 INFO L290 TraceCheckUtils]: 85: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,972 INFO L290 TraceCheckUtils]: 86: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,973 INFO L290 TraceCheckUtils]: 87: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,973 INFO L290 TraceCheckUtils]: 88: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,973 INFO L290 TraceCheckUtils]: 89: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,974 INFO L290 TraceCheckUtils]: 90: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,974 INFO L290 TraceCheckUtils]: 91: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,974 INFO L290 TraceCheckUtils]: 92: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,975 INFO L290 TraceCheckUtils]: 93: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,975 INFO L290 TraceCheckUtils]: 94: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,976 INFO L290 TraceCheckUtils]: 95: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,976 INFO L290 TraceCheckUtils]: 96: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,976 INFO L290 TraceCheckUtils]: 97: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,977 INFO L290 TraceCheckUtils]: 98: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,977 INFO L290 TraceCheckUtils]: 99: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,977 INFO L290 TraceCheckUtils]: 100: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,978 INFO L290 TraceCheckUtils]: 101: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,978 INFO L290 TraceCheckUtils]: 102: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,978 INFO L290 TraceCheckUtils]: 103: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,979 INFO L290 TraceCheckUtils]: 104: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,979 INFO L290 TraceCheckUtils]: 105: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,980 INFO L290 TraceCheckUtils]: 106: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,980 INFO L290 TraceCheckUtils]: 107: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,980 INFO L290 TraceCheckUtils]: 108: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,981 INFO L290 TraceCheckUtils]: 109: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,981 INFO L290 TraceCheckUtils]: 110: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,981 INFO L290 TraceCheckUtils]: 111: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t12_pc~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,982 INFO L290 TraceCheckUtils]: 112: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,982 INFO L290 TraceCheckUtils]: 113: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,982 INFO L290 TraceCheckUtils]: 114: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,983 INFO L290 TraceCheckUtils]: 115: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,983 INFO L290 TraceCheckUtils]: 116: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,984 INFO L290 TraceCheckUtils]: 117: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,984 INFO L290 TraceCheckUtils]: 118: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,984 INFO L290 TraceCheckUtils]: 119: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,985 INFO L290 TraceCheckUtils]: 120: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,985 INFO L290 TraceCheckUtils]: 121: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,985 INFO L290 TraceCheckUtils]: 122: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,986 INFO L290 TraceCheckUtils]: 123: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~M_E~0); {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,986 INFO L290 TraceCheckUtils]: 124: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,987 INFO L290 TraceCheckUtils]: 125: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,987 INFO L290 TraceCheckUtils]: 126: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,987 INFO L290 TraceCheckUtils]: 127: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {142767#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:52,988 INFO L290 TraceCheckUtils]: 128: Hoare triple {142767#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {142766#false} is VALID [2022-02-21 04:23:52,988 INFO L290 TraceCheckUtils]: 129: Hoare triple {142766#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,988 INFO L290 TraceCheckUtils]: 130: Hoare triple {142766#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,988 INFO L290 TraceCheckUtils]: 131: Hoare triple {142766#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,988 INFO L290 TraceCheckUtils]: 132: Hoare triple {142766#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,988 INFO L290 TraceCheckUtils]: 133: Hoare triple {142766#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,989 INFO L290 TraceCheckUtils]: 134: Hoare triple {142766#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,989 INFO L290 TraceCheckUtils]: 135: Hoare triple {142766#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,989 INFO L290 TraceCheckUtils]: 136: Hoare triple {142766#false} assume !(1 == ~T13_E~0); {142766#false} is VALID [2022-02-21 04:23:52,989 INFO L290 TraceCheckUtils]: 137: Hoare triple {142766#false} assume 1 == ~E_M~0;~E_M~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,989 INFO L290 TraceCheckUtils]: 138: Hoare triple {142766#false} assume 1 == ~E_1~0;~E_1~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,989 INFO L290 TraceCheckUtils]: 139: Hoare triple {142766#false} assume 1 == ~E_2~0;~E_2~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,989 INFO L290 TraceCheckUtils]: 140: Hoare triple {142766#false} assume 1 == ~E_3~0;~E_3~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,989 INFO L290 TraceCheckUtils]: 141: Hoare triple {142766#false} assume 1 == ~E_4~0;~E_4~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,990 INFO L290 TraceCheckUtils]: 142: Hoare triple {142766#false} assume 1 == ~E_5~0;~E_5~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,990 INFO L290 TraceCheckUtils]: 143: Hoare triple {142766#false} assume 1 == ~E_6~0;~E_6~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,990 INFO L290 TraceCheckUtils]: 144: Hoare triple {142766#false} assume !(1 == ~E_7~0); {142766#false} is VALID [2022-02-21 04:23:52,990 INFO L290 TraceCheckUtils]: 145: Hoare triple {142766#false} assume 1 == ~E_8~0;~E_8~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,990 INFO L290 TraceCheckUtils]: 146: Hoare triple {142766#false} assume 1 == ~E_9~0;~E_9~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,990 INFO L290 TraceCheckUtils]: 147: Hoare triple {142766#false} assume 1 == ~E_10~0;~E_10~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,990 INFO L290 TraceCheckUtils]: 148: Hoare triple {142766#false} assume 1 == ~E_11~0;~E_11~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,991 INFO L290 TraceCheckUtils]: 149: Hoare triple {142766#false} assume 1 == ~E_12~0;~E_12~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,991 INFO L290 TraceCheckUtils]: 150: Hoare triple {142766#false} assume 1 == ~E_13~0;~E_13~0 := 2; {142766#false} is VALID [2022-02-21 04:23:52,991 INFO L290 TraceCheckUtils]: 151: Hoare triple {142766#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {142766#false} is VALID [2022-02-21 04:23:52,991 INFO L290 TraceCheckUtils]: 152: Hoare triple {142766#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {142766#false} is VALID [2022-02-21 04:23:52,991 INFO L290 TraceCheckUtils]: 153: Hoare triple {142766#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {142766#false} is VALID [2022-02-21 04:23:52,991 INFO L290 TraceCheckUtils]: 154: Hoare triple {142766#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {142766#false} is VALID [2022-02-21 04:23:52,991 INFO L290 TraceCheckUtils]: 155: Hoare triple {142766#false} assume !(0 == start_simulation_~tmp~3#1); {142766#false} is VALID [2022-02-21 04:23:52,992 INFO L290 TraceCheckUtils]: 156: Hoare triple {142766#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {142766#false} is VALID [2022-02-21 04:23:52,992 INFO L290 TraceCheckUtils]: 157: Hoare triple {142766#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {142766#false} is VALID [2022-02-21 04:23:52,992 INFO L290 TraceCheckUtils]: 158: Hoare triple {142766#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {142766#false} is VALID [2022-02-21 04:23:52,992 INFO L290 TraceCheckUtils]: 159: Hoare triple {142766#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {142766#false} is VALID [2022-02-21 04:23:52,992 INFO L290 TraceCheckUtils]: 160: Hoare triple {142766#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {142766#false} is VALID [2022-02-21 04:23:52,992 INFO L290 TraceCheckUtils]: 161: Hoare triple {142766#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {142766#false} is VALID [2022-02-21 04:23:52,992 INFO L290 TraceCheckUtils]: 162: Hoare triple {142766#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {142766#false} is VALID [2022-02-21 04:23:52,993 INFO L290 TraceCheckUtils]: 163: Hoare triple {142766#false} assume !(0 != start_simulation_~tmp___0~1#1); {142766#false} is VALID [2022-02-21 04:23:52,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:52,993 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:52,993 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1313126532] [2022-02-21 04:23:52,994 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1313126532] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:52,994 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:52,994 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:52,994 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060496313] [2022-02-21 04:23:52,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:52,995 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:52,995 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:52,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:52,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:52,995 INFO L87 Difference]: Start difference. First operand 3771 states and 5543 transitions. cyclomatic complexity: 1773 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:54,672 INFO L93 Difference]: Finished difference Result 3771 states and 5505 transitions. [2022-02-21 04:23:54,672 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:54,672 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,781 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:54,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3771 states and 5505 transitions. [2022-02-21 04:23:55,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-02-21 04:23:55,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3771 states to 3771 states and 5505 transitions. [2022-02-21 04:23:55,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3771 [2022-02-21 04:23:55,597 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3771 [2022-02-21 04:23:55,597 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3771 states and 5505 transitions. [2022-02-21 04:23:55,599 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:55,599 INFO L681 BuchiCegarLoop]: Abstraction has 3771 states and 5505 transitions. [2022-02-21 04:23:55,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states and 5505 transitions. [2022-02-21 04:23:55,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3771. [2022-02-21 04:23:55,665 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:55,669 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3771 states and 5505 transitions. Second operand has 3771 states, 3771 states have (on average 1.4598249801113763) internal successors, (5505), 3770 states have internal predecessors, (5505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:55,672 INFO L74 IsIncluded]: Start isIncluded. First operand 3771 states and 5505 transitions. Second operand has 3771 states, 3771 states have (on average 1.4598249801113763) internal successors, (5505), 3770 states have internal predecessors, (5505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:55,677 INFO L87 Difference]: Start difference. First operand 3771 states and 5505 transitions. Second operand has 3771 states, 3771 states have (on average 1.4598249801113763) internal successors, (5505), 3770 states have internal predecessors, (5505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:55,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:55,975 INFO L93 Difference]: Finished difference Result 3771 states and 5505 transitions. [2022-02-21 04:23:55,975 INFO L276 IsEmpty]: Start isEmpty. Operand 3771 states and 5505 transitions. [2022-02-21 04:23:55,978 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:55,978 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:55,981 INFO L74 IsIncluded]: Start isIncluded. First operand has 3771 states, 3771 states have (on average 1.4598249801113763) internal successors, (5505), 3770 states have internal predecessors, (5505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3771 states and 5505 transitions. [2022-02-21 04:23:55,983 INFO L87 Difference]: Start difference. First operand has 3771 states, 3771 states have (on average 1.4598249801113763) internal successors, (5505), 3770 states have internal predecessors, (5505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3771 states and 5505 transitions. [2022-02-21 04:23:56,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:56,276 INFO L93 Difference]: Finished difference Result 3771 states and 5505 transitions. [2022-02-21 04:23:56,276 INFO L276 IsEmpty]: Start isEmpty. Operand 3771 states and 5505 transitions. [2022-02-21 04:23:56,279 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:56,279 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:56,279 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:56,279 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:56,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4598249801113763) internal successors, (5505), 3770 states have internal predecessors, (5505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:56,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5505 transitions. [2022-02-21 04:23:56,586 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5505 transitions. [2022-02-21 04:23:56,586 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5505 transitions. [2022-02-21 04:23:56,586 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2022-02-21 04:23:56,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5505 transitions. [2022-02-21 04:23:56,591 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-02-21 04:23:56,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:56,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:56,593 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:56,593 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:56,593 INFO L791 eck$LassoCheckResult]: Stem: 147465#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 147466#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 148478#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 148479#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 148573#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 147929#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 147397#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 147398#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 148218#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 148219#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 148327#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 148328#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 147168#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 147169#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 148358#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 147705#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 147706#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 148272#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 147608#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 147609#L1291 assume !(0 == ~M_E~0); 148574#L1291-2 assume !(0 == ~T1_E~0); 148572#L1296-1 assume !(0 == ~T2_E~0); 147765#L1301-1 assume !(0 == ~T3_E~0); 147766#L1306-1 assume !(0 == ~T4_E~0); 148281#L1311-1 assume !(0 == ~T5_E~0); 147011#L1316-1 assume !(0 == ~T6_E~0); 147012#L1321-1 assume !(0 == ~T7_E~0); 147778#L1326-1 assume !(0 == ~T8_E~0); 146840#L1331-1 assume !(0 == ~T9_E~0); 146541#L1336-1 assume !(0 == ~T10_E~0); 146542#L1341-1 assume !(0 == ~T11_E~0); 146621#L1346-1 assume !(0 == ~T12_E~0); 146622#L1351-1 assume !(0 == ~T13_E~0); 146960#L1356-1 assume !(0 == ~E_M~0); 146961#L1361-1 assume !(0 == ~E_1~0); 148508#L1366-1 assume !(0 == ~E_2~0); 147001#L1371-1 assume !(0 == ~E_3~0); 147002#L1376-1 assume !(0 == ~E_4~0); 147825#L1381-1 assume !(0 == ~E_5~0); 147826#L1386-1 assume !(0 == ~E_6~0); 148540#L1391-1 assume !(0 == ~E_7~0); 148561#L1396-1 assume !(0 == ~E_8~0); 147737#L1401-1 assume !(0 == ~E_9~0); 147738#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 148018#L1411-1 assume !(0 == ~E_11~0); 148019#L1416-1 assume !(0 == ~E_12~0); 147650#L1421-1 assume !(0 == ~E_13~0); 147191#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 147192#L640 assume !(1 == ~m_pc~0); 147702#L640-2 is_master_triggered_~__retres1~0#1 := 0; 147701#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 147794#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 147687#L1603 assume !(0 != activate_threads_~tmp~1#1); 147688#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 147322#L659 assume 1 == ~t1_pc~0; 147323#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 147429#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148388#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 147449#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 147450#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 147463#L678 assume !(1 == ~t2_pc~0); 148432#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 148536#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 148537#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 147561#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 147562#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 147682#L697 assume !(1 == ~t3_pc~0); 147683#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 147806#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 147614#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 147593#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 147594#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 148468#L716 assume 1 == ~t4_pc~0; 148454#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 147303#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 147304#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 146803#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 146804#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 148098#L735 assume !(1 == ~t5_pc~0); 146765#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 146766#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 147214#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 148125#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 147758#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 147759#L754 assume 1 == ~t6_pc~0; 147513#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 147411#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 147412#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 147384#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 147385#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 148209#L773 assume !(1 == ~t7_pc~0); 146964#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 146963#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 147795#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 147767#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 147768#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 147815#L792 assume 1 == ~t8_pc~0; 147988#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 148331#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 147809#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 147761#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 147685#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 147686#L811 assume 1 == ~t9_pc~0; 147891#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 148369#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 148236#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 147887#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 147698#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 147699#L830 assume !(1 == ~t10_pc~0); 147421#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 146943#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 146638#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 146639#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 146924#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 148227#L849 assume 1 == ~t11_pc~0; 148228#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 146741#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 146742#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 147330#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 148132#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 148133#L868 assume !(1 == ~t12_pc~0); 147546#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 147545#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 147339#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 147340#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 146975#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 146976#L887 assume 1 == ~t13_pc~0; 148147#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 147587#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 147588#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 148025#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 146681#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 146682#L1439 assume !(1 == ~M_E~0); 147754#L1439-2 assume !(1 == ~T1_E~0); 146852#L1444-1 assume !(1 == ~T2_E~0); 146853#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 147326#L1454-1 assume !(1 == ~T4_E~0); 147327#L1459-1 assume !(1 == ~T5_E~0); 147884#L1464-1 assume !(1 == ~T6_E~0); 147885#L1469-1 assume !(1 == ~T7_E~0); 147957#L1474-1 assume !(1 == ~T8_E~0); 147651#L1479-1 assume !(1 == ~T9_E~0); 147652#L1484-1 assume !(1 == ~T10_E~0); 147888#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 147534#L1494-1 assume !(1 == ~T12_E~0); 147535#L1499-1 assume !(1 == ~T13_E~0); 147726#L1504-1 assume !(1 == ~E_M~0); 147727#L1509-1 assume !(1 == ~E_1~0); 148313#L1514-1 assume !(1 == ~E_2~0); 147990#L1519-1 assume !(1 == ~E_3~0); 147991#L1524-1 assume !(1 == ~E_4~0); 148522#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 148523#L1534-1 assume !(1 == ~E_6~0); 146674#L1539-1 assume !(1 == ~E_7~0); 146675#L1544-1 assume !(1 == ~E_8~0); 147087#L1549-1 assume !(1 == ~E_9~0); 148492#L1554-1 assume !(1 == ~E_10~0); 148488#L1559-1 assume !(1 == ~E_11~0); 148352#L1564-1 assume !(1 == ~E_12~0); 148353#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 148517#L1574-1 assume { :end_inline_reset_delta_events } true; 146850#L1940-2 [2022-02-21 04:23:56,594 INFO L793 eck$LassoCheckResult]: Loop: 146850#L1940-2 assume !false; 146851#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 147132#L1266 assume !false; 148155#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 147381#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 147113#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 147506#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 147507#L1079 assume !(0 != eval_~tmp~0#1); 147468#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 147469#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 148075#L1291-3 assume !(0 == ~M_E~0); 148076#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 150239#L1296-3 assume !(0 == ~T2_E~0); 150238#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 150237#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 150236#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 150235#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 150234#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 150233#L1326-3 assume !(0 == ~T8_E~0); 150232#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 150231#L1336-3 assume !(0 == ~T10_E~0); 150230#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 150229#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 150228#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 150227#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 150226#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 150225#L1366-3 assume !(0 == ~E_2~0); 150224#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 150223#L1376-3 assume !(0 == ~E_4~0); 150222#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 150221#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 150220#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 150219#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 150218#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 150217#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 150216#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 150215#L1416-3 assume !(0 == ~E_12~0); 150214#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 150213#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150212#L640-45 assume 1 == ~m_pc~0; 150210#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 150209#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 150208#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 150207#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 150206#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 150205#L659-45 assume 1 == ~t1_pc~0; 150203#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 150202#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 150201#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 150200#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 150199#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 150198#L678-45 assume !(1 == ~t2_pc~0); 150196#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 150195#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 150194#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 150193#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 150192#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150191#L697-45 assume !(1 == ~t3_pc~0); 150190#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 150188#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 150187#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 150186#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 150185#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 150184#L716-45 assume !(1 == ~t4_pc~0); 150182#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 150181#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 150180#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 150179#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 150178#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 150177#L735-45 assume !(1 == ~t5_pc~0); 150176#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 150174#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 150173#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 150172#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 150171#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 150170#L754-45 assume !(1 == ~t6_pc~0); 150168#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 150167#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 150166#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 150165#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 150164#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 150163#L773-45 assume !(1 == ~t7_pc~0); 150162#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 150160#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 150159#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 150158#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 150157#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 150156#L792-45 assume 1 == ~t8_pc~0; 150154#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 150153#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 146843#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 146703#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 146704#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 147197#L811-45 assume 1 == ~t9_pc~0; 146986#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 146988#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 148201#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 148034#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 147642#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 147434#L830-45 assume !(1 == ~t10_pc~0); 146631#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 146632#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 147753#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 146863#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 146864#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 146610#L849-45 assume !(1 == ~t11_pc~0); 146611#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 147068#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 146701#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 146598#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 146599#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 146856#L868-45 assume !(1 == ~t12_pc~0); 146858#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 146796#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 146797#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 148138#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 148400#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 148401#L887-45 assume !(1 == ~t13_pc~0); 146865#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 146866#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 148151#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 148512#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 146828#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 146829#L1439-3 assume !(1 == ~M_E~0); 148139#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 146848#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 146849#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 147005#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 147938#L1459-3 assume !(1 == ~T5_E~0); 147939#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 148404#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 148340#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 148341#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 148405#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 147623#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 147624#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 148265#L1499-3 assume !(1 == ~T13_E~0); 147899#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 147900#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 148349#L1514-3 assume !(1 == ~E_2~0); 148381#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 147542#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 147543#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 148424#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 147810#L1539-3 assume !(1 == ~E_7~0); 147285#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 147286#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 147782#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 146901#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 146902#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 148285#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 148260#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 146780#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 146552#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 146825#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 146786#L1959 assume !(0 == start_simulation_~tmp~3#1); 146788#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 146820#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 146771#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 148082#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 148204#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 148422#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 148435#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 148436#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 146850#L1940-2 [2022-02-21 04:23:56,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:56,595 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2022-02-21 04:23:56,595 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:56,595 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705404715] [2022-02-21 04:23:56,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:56,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:56,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:56,630 INFO L290 TraceCheckUtils]: 0: Hoare triple {157855#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,631 INFO L290 TraceCheckUtils]: 1: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,631 INFO L290 TraceCheckUtils]: 2: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,632 INFO L290 TraceCheckUtils]: 3: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,632 INFO L290 TraceCheckUtils]: 4: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,632 INFO L290 TraceCheckUtils]: 5: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,633 INFO L290 TraceCheckUtils]: 6: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,633 INFO L290 TraceCheckUtils]: 7: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,633 INFO L290 TraceCheckUtils]: 8: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,634 INFO L290 TraceCheckUtils]: 9: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,634 INFO L290 TraceCheckUtils]: 10: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,634 INFO L290 TraceCheckUtils]: 11: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,635 INFO L290 TraceCheckUtils]: 12: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,635 INFO L290 TraceCheckUtils]: 13: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,635 INFO L290 TraceCheckUtils]: 14: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,636 INFO L290 TraceCheckUtils]: 15: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,636 INFO L290 TraceCheckUtils]: 16: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,636 INFO L290 TraceCheckUtils]: 17: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,637 INFO L290 TraceCheckUtils]: 18: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {157857#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:56,637 INFO L290 TraceCheckUtils]: 19: Hoare triple {157857#(= ~E_10~0 ~M_E~0)} assume !(0 == ~M_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,637 INFO L290 TraceCheckUtils]: 20: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T1_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,638 INFO L290 TraceCheckUtils]: 21: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T2_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,638 INFO L290 TraceCheckUtils]: 22: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T3_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,638 INFO L290 TraceCheckUtils]: 23: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T4_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,639 INFO L290 TraceCheckUtils]: 24: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T5_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,639 INFO L290 TraceCheckUtils]: 25: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T6_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,639 INFO L290 TraceCheckUtils]: 26: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T7_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,640 INFO L290 TraceCheckUtils]: 27: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T8_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,640 INFO L290 TraceCheckUtils]: 28: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T9_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,640 INFO L290 TraceCheckUtils]: 29: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T10_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,641 INFO L290 TraceCheckUtils]: 30: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T11_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,641 INFO L290 TraceCheckUtils]: 31: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T12_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,641 INFO L290 TraceCheckUtils]: 32: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~T13_E~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,642 INFO L290 TraceCheckUtils]: 33: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~E_M~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,642 INFO L290 TraceCheckUtils]: 34: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~E_1~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,642 INFO L290 TraceCheckUtils]: 35: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~E_2~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,643 INFO L290 TraceCheckUtils]: 36: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~E_3~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,643 INFO L290 TraceCheckUtils]: 37: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~E_4~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,643 INFO L290 TraceCheckUtils]: 38: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~E_5~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,644 INFO L290 TraceCheckUtils]: 39: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~E_6~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,644 INFO L290 TraceCheckUtils]: 40: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~E_7~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,644 INFO L290 TraceCheckUtils]: 41: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~E_8~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,645 INFO L290 TraceCheckUtils]: 42: Hoare triple {157858#(not (= ~E_10~0 0))} assume !(0 == ~E_9~0); {157858#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:56,645 INFO L290 TraceCheckUtils]: 43: Hoare triple {157858#(not (= ~E_10~0 0))} assume 0 == ~E_10~0;~E_10~0 := 1; {157856#false} is VALID [2022-02-21 04:23:56,645 INFO L290 TraceCheckUtils]: 44: Hoare triple {157856#false} assume !(0 == ~E_11~0); {157856#false} is VALID [2022-02-21 04:23:56,645 INFO L290 TraceCheckUtils]: 45: Hoare triple {157856#false} assume !(0 == ~E_12~0); {157856#false} is VALID [2022-02-21 04:23:56,645 INFO L290 TraceCheckUtils]: 46: Hoare triple {157856#false} assume !(0 == ~E_13~0); {157856#false} is VALID [2022-02-21 04:23:56,645 INFO L290 TraceCheckUtils]: 47: Hoare triple {157856#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {157856#false} is VALID [2022-02-21 04:23:56,646 INFO L290 TraceCheckUtils]: 48: Hoare triple {157856#false} assume !(1 == ~m_pc~0); {157856#false} is VALID [2022-02-21 04:23:56,646 INFO L290 TraceCheckUtils]: 49: Hoare triple {157856#false} is_master_triggered_~__retres1~0#1 := 0; {157856#false} is VALID [2022-02-21 04:23:56,646 INFO L290 TraceCheckUtils]: 50: Hoare triple {157856#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {157856#false} is VALID [2022-02-21 04:23:56,646 INFO L290 TraceCheckUtils]: 51: Hoare triple {157856#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {157856#false} is VALID [2022-02-21 04:23:56,646 INFO L290 TraceCheckUtils]: 52: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp~1#1); {157856#false} is VALID [2022-02-21 04:23:56,646 INFO L290 TraceCheckUtils]: 53: Hoare triple {157856#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {157856#false} is VALID [2022-02-21 04:23:56,646 INFO L290 TraceCheckUtils]: 54: Hoare triple {157856#false} assume 1 == ~t1_pc~0; {157856#false} is VALID [2022-02-21 04:23:56,647 INFO L290 TraceCheckUtils]: 55: Hoare triple {157856#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {157856#false} is VALID [2022-02-21 04:23:56,647 INFO L290 TraceCheckUtils]: 56: Hoare triple {157856#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {157856#false} is VALID [2022-02-21 04:23:56,647 INFO L290 TraceCheckUtils]: 57: Hoare triple {157856#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {157856#false} is VALID [2022-02-21 04:23:56,647 INFO L290 TraceCheckUtils]: 58: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___0~0#1); {157856#false} is VALID [2022-02-21 04:23:56,647 INFO L290 TraceCheckUtils]: 59: Hoare triple {157856#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {157856#false} is VALID [2022-02-21 04:23:56,647 INFO L290 TraceCheckUtils]: 60: Hoare triple {157856#false} assume !(1 == ~t2_pc~0); {157856#false} is VALID [2022-02-21 04:23:56,647 INFO L290 TraceCheckUtils]: 61: Hoare triple {157856#false} is_transmit2_triggered_~__retres1~2#1 := 0; {157856#false} is VALID [2022-02-21 04:23:56,648 INFO L290 TraceCheckUtils]: 62: Hoare triple {157856#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {157856#false} is VALID [2022-02-21 04:23:56,648 INFO L290 TraceCheckUtils]: 63: Hoare triple {157856#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {157856#false} is VALID [2022-02-21 04:23:56,648 INFO L290 TraceCheckUtils]: 64: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___1~0#1); {157856#false} is VALID [2022-02-21 04:23:56,648 INFO L290 TraceCheckUtils]: 65: Hoare triple {157856#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {157856#false} is VALID [2022-02-21 04:23:56,648 INFO L290 TraceCheckUtils]: 66: Hoare triple {157856#false} assume !(1 == ~t3_pc~0); {157856#false} is VALID [2022-02-21 04:23:56,648 INFO L290 TraceCheckUtils]: 67: Hoare triple {157856#false} is_transmit3_triggered_~__retres1~3#1 := 0; {157856#false} is VALID [2022-02-21 04:23:56,648 INFO L290 TraceCheckUtils]: 68: Hoare triple {157856#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {157856#false} is VALID [2022-02-21 04:23:56,648 INFO L290 TraceCheckUtils]: 69: Hoare triple {157856#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {157856#false} is VALID [2022-02-21 04:23:56,649 INFO L290 TraceCheckUtils]: 70: Hoare triple {157856#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {157856#false} is VALID [2022-02-21 04:23:56,649 INFO L290 TraceCheckUtils]: 71: Hoare triple {157856#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {157856#false} is VALID [2022-02-21 04:23:56,649 INFO L290 TraceCheckUtils]: 72: Hoare triple {157856#false} assume 1 == ~t4_pc~0; {157856#false} is VALID [2022-02-21 04:23:56,649 INFO L290 TraceCheckUtils]: 73: Hoare triple {157856#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {157856#false} is VALID [2022-02-21 04:23:56,649 INFO L290 TraceCheckUtils]: 74: Hoare triple {157856#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {157856#false} is VALID [2022-02-21 04:23:56,649 INFO L290 TraceCheckUtils]: 75: Hoare triple {157856#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {157856#false} is VALID [2022-02-21 04:23:56,649 INFO L290 TraceCheckUtils]: 76: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___3~0#1); {157856#false} is VALID [2022-02-21 04:23:56,650 INFO L290 TraceCheckUtils]: 77: Hoare triple {157856#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {157856#false} is VALID [2022-02-21 04:23:56,650 INFO L290 TraceCheckUtils]: 78: Hoare triple {157856#false} assume !(1 == ~t5_pc~0); {157856#false} is VALID [2022-02-21 04:23:56,650 INFO L290 TraceCheckUtils]: 79: Hoare triple {157856#false} is_transmit5_triggered_~__retres1~5#1 := 0; {157856#false} is VALID [2022-02-21 04:23:56,650 INFO L290 TraceCheckUtils]: 80: Hoare triple {157856#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {157856#false} is VALID [2022-02-21 04:23:56,650 INFO L290 TraceCheckUtils]: 81: Hoare triple {157856#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {157856#false} is VALID [2022-02-21 04:23:56,650 INFO L290 TraceCheckUtils]: 82: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___4~0#1); {157856#false} is VALID [2022-02-21 04:23:56,650 INFO L290 TraceCheckUtils]: 83: Hoare triple {157856#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {157856#false} is VALID [2022-02-21 04:23:56,650 INFO L290 TraceCheckUtils]: 84: Hoare triple {157856#false} assume 1 == ~t6_pc~0; {157856#false} is VALID [2022-02-21 04:23:56,651 INFO L290 TraceCheckUtils]: 85: Hoare triple {157856#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {157856#false} is VALID [2022-02-21 04:23:56,651 INFO L290 TraceCheckUtils]: 86: Hoare triple {157856#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {157856#false} is VALID [2022-02-21 04:23:56,651 INFO L290 TraceCheckUtils]: 87: Hoare triple {157856#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {157856#false} is VALID [2022-02-21 04:23:56,651 INFO L290 TraceCheckUtils]: 88: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___5~0#1); {157856#false} is VALID [2022-02-21 04:23:56,651 INFO L290 TraceCheckUtils]: 89: Hoare triple {157856#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {157856#false} is VALID [2022-02-21 04:23:56,651 INFO L290 TraceCheckUtils]: 90: Hoare triple {157856#false} assume !(1 == ~t7_pc~0); {157856#false} is VALID [2022-02-21 04:23:56,651 INFO L290 TraceCheckUtils]: 91: Hoare triple {157856#false} is_transmit7_triggered_~__retres1~7#1 := 0; {157856#false} is VALID [2022-02-21 04:23:56,652 INFO L290 TraceCheckUtils]: 92: Hoare triple {157856#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {157856#false} is VALID [2022-02-21 04:23:56,652 INFO L290 TraceCheckUtils]: 93: Hoare triple {157856#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {157856#false} is VALID [2022-02-21 04:23:56,652 INFO L290 TraceCheckUtils]: 94: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___6~0#1); {157856#false} is VALID [2022-02-21 04:23:56,652 INFO L290 TraceCheckUtils]: 95: Hoare triple {157856#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {157856#false} is VALID [2022-02-21 04:23:56,652 INFO L290 TraceCheckUtils]: 96: Hoare triple {157856#false} assume 1 == ~t8_pc~0; {157856#false} is VALID [2022-02-21 04:23:56,652 INFO L290 TraceCheckUtils]: 97: Hoare triple {157856#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {157856#false} is VALID [2022-02-21 04:23:56,652 INFO L290 TraceCheckUtils]: 98: Hoare triple {157856#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {157856#false} is VALID [2022-02-21 04:23:56,653 INFO L290 TraceCheckUtils]: 99: Hoare triple {157856#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {157856#false} is VALID [2022-02-21 04:23:56,653 INFO L290 TraceCheckUtils]: 100: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___7~0#1); {157856#false} is VALID [2022-02-21 04:23:56,653 INFO L290 TraceCheckUtils]: 101: Hoare triple {157856#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {157856#false} is VALID [2022-02-21 04:23:56,653 INFO L290 TraceCheckUtils]: 102: Hoare triple {157856#false} assume 1 == ~t9_pc~0; {157856#false} is VALID [2022-02-21 04:23:56,653 INFO L290 TraceCheckUtils]: 103: Hoare triple {157856#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {157856#false} is VALID [2022-02-21 04:23:56,653 INFO L290 TraceCheckUtils]: 104: Hoare triple {157856#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {157856#false} is VALID [2022-02-21 04:23:56,653 INFO L290 TraceCheckUtils]: 105: Hoare triple {157856#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {157856#false} is VALID [2022-02-21 04:23:56,653 INFO L290 TraceCheckUtils]: 106: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___8~0#1); {157856#false} is VALID [2022-02-21 04:23:56,654 INFO L290 TraceCheckUtils]: 107: Hoare triple {157856#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {157856#false} is VALID [2022-02-21 04:23:56,654 INFO L290 TraceCheckUtils]: 108: Hoare triple {157856#false} assume !(1 == ~t10_pc~0); {157856#false} is VALID [2022-02-21 04:23:56,654 INFO L290 TraceCheckUtils]: 109: Hoare triple {157856#false} is_transmit10_triggered_~__retres1~10#1 := 0; {157856#false} is VALID [2022-02-21 04:23:56,654 INFO L290 TraceCheckUtils]: 110: Hoare triple {157856#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {157856#false} is VALID [2022-02-21 04:23:56,654 INFO L290 TraceCheckUtils]: 111: Hoare triple {157856#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {157856#false} is VALID [2022-02-21 04:23:56,654 INFO L290 TraceCheckUtils]: 112: Hoare triple {157856#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {157856#false} is VALID [2022-02-21 04:23:56,654 INFO L290 TraceCheckUtils]: 113: Hoare triple {157856#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {157856#false} is VALID [2022-02-21 04:23:56,655 INFO L290 TraceCheckUtils]: 114: Hoare triple {157856#false} assume 1 == ~t11_pc~0; {157856#false} is VALID [2022-02-21 04:23:56,655 INFO L290 TraceCheckUtils]: 115: Hoare triple {157856#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {157856#false} is VALID [2022-02-21 04:23:56,655 INFO L290 TraceCheckUtils]: 116: Hoare triple {157856#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {157856#false} is VALID [2022-02-21 04:23:56,655 INFO L290 TraceCheckUtils]: 117: Hoare triple {157856#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {157856#false} is VALID [2022-02-21 04:23:56,655 INFO L290 TraceCheckUtils]: 118: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___10~0#1); {157856#false} is VALID [2022-02-21 04:23:56,655 INFO L290 TraceCheckUtils]: 119: Hoare triple {157856#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {157856#false} is VALID [2022-02-21 04:23:56,655 INFO L290 TraceCheckUtils]: 120: Hoare triple {157856#false} assume !(1 == ~t12_pc~0); {157856#false} is VALID [2022-02-21 04:23:56,656 INFO L290 TraceCheckUtils]: 121: Hoare triple {157856#false} is_transmit12_triggered_~__retres1~12#1 := 0; {157856#false} is VALID [2022-02-21 04:23:56,656 INFO L290 TraceCheckUtils]: 122: Hoare triple {157856#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {157856#false} is VALID [2022-02-21 04:23:56,656 INFO L290 TraceCheckUtils]: 123: Hoare triple {157856#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {157856#false} is VALID [2022-02-21 04:23:56,656 INFO L290 TraceCheckUtils]: 124: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___11~0#1); {157856#false} is VALID [2022-02-21 04:23:56,656 INFO L290 TraceCheckUtils]: 125: Hoare triple {157856#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {157856#false} is VALID [2022-02-21 04:23:56,656 INFO L290 TraceCheckUtils]: 126: Hoare triple {157856#false} assume 1 == ~t13_pc~0; {157856#false} is VALID [2022-02-21 04:23:56,656 INFO L290 TraceCheckUtils]: 127: Hoare triple {157856#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {157856#false} is VALID [2022-02-21 04:23:56,656 INFO L290 TraceCheckUtils]: 128: Hoare triple {157856#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {157856#false} is VALID [2022-02-21 04:23:56,657 INFO L290 TraceCheckUtils]: 129: Hoare triple {157856#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {157856#false} is VALID [2022-02-21 04:23:56,657 INFO L290 TraceCheckUtils]: 130: Hoare triple {157856#false} assume !(0 != activate_threads_~tmp___12~0#1); {157856#false} is VALID [2022-02-21 04:23:56,657 INFO L290 TraceCheckUtils]: 131: Hoare triple {157856#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {157856#false} is VALID [2022-02-21 04:23:56,657 INFO L290 TraceCheckUtils]: 132: Hoare triple {157856#false} assume !(1 == ~M_E~0); {157856#false} is VALID [2022-02-21 04:23:56,657 INFO L290 TraceCheckUtils]: 133: Hoare triple {157856#false} assume !(1 == ~T1_E~0); {157856#false} is VALID [2022-02-21 04:23:56,657 INFO L290 TraceCheckUtils]: 134: Hoare triple {157856#false} assume !(1 == ~T2_E~0); {157856#false} is VALID [2022-02-21 04:23:56,657 INFO L290 TraceCheckUtils]: 135: Hoare triple {157856#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {157856#false} is VALID [2022-02-21 04:23:56,658 INFO L290 TraceCheckUtils]: 136: Hoare triple {157856#false} assume !(1 == ~T4_E~0); {157856#false} is VALID [2022-02-21 04:23:56,658 INFO L290 TraceCheckUtils]: 137: Hoare triple {157856#false} assume !(1 == ~T5_E~0); {157856#false} is VALID [2022-02-21 04:23:56,658 INFO L290 TraceCheckUtils]: 138: Hoare triple {157856#false} assume !(1 == ~T6_E~0); {157856#false} is VALID [2022-02-21 04:23:56,658 INFO L290 TraceCheckUtils]: 139: Hoare triple {157856#false} assume !(1 == ~T7_E~0); {157856#false} is VALID [2022-02-21 04:23:56,658 INFO L290 TraceCheckUtils]: 140: Hoare triple {157856#false} assume !(1 == ~T8_E~0); {157856#false} is VALID [2022-02-21 04:23:56,658 INFO L290 TraceCheckUtils]: 141: Hoare triple {157856#false} assume !(1 == ~T9_E~0); {157856#false} is VALID [2022-02-21 04:23:56,658 INFO L290 TraceCheckUtils]: 142: Hoare triple {157856#false} assume !(1 == ~T10_E~0); {157856#false} is VALID [2022-02-21 04:23:56,659 INFO L290 TraceCheckUtils]: 143: Hoare triple {157856#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {157856#false} is VALID [2022-02-21 04:23:56,659 INFO L290 TraceCheckUtils]: 144: Hoare triple {157856#false} assume !(1 == ~T12_E~0); {157856#false} is VALID [2022-02-21 04:23:56,659 INFO L290 TraceCheckUtils]: 145: Hoare triple {157856#false} assume !(1 == ~T13_E~0); {157856#false} is VALID [2022-02-21 04:23:56,659 INFO L290 TraceCheckUtils]: 146: Hoare triple {157856#false} assume !(1 == ~E_M~0); {157856#false} is VALID [2022-02-21 04:23:56,659 INFO L290 TraceCheckUtils]: 147: Hoare triple {157856#false} assume !(1 == ~E_1~0); {157856#false} is VALID [2022-02-21 04:23:56,659 INFO L290 TraceCheckUtils]: 148: Hoare triple {157856#false} assume !(1 == ~E_2~0); {157856#false} is VALID [2022-02-21 04:23:56,659 INFO L290 TraceCheckUtils]: 149: Hoare triple {157856#false} assume !(1 == ~E_3~0); {157856#false} is VALID [2022-02-21 04:23:56,660 INFO L290 TraceCheckUtils]: 150: Hoare triple {157856#false} assume !(1 == ~E_4~0); {157856#false} is VALID [2022-02-21 04:23:56,660 INFO L290 TraceCheckUtils]: 151: Hoare triple {157856#false} assume 1 == ~E_5~0;~E_5~0 := 2; {157856#false} is VALID [2022-02-21 04:23:56,660 INFO L290 TraceCheckUtils]: 152: Hoare triple {157856#false} assume !(1 == ~E_6~0); {157856#false} is VALID [2022-02-21 04:23:56,660 INFO L290 TraceCheckUtils]: 153: Hoare triple {157856#false} assume !(1 == ~E_7~0); {157856#false} is VALID [2022-02-21 04:23:56,660 INFO L290 TraceCheckUtils]: 154: Hoare triple {157856#false} assume !(1 == ~E_8~0); {157856#false} is VALID [2022-02-21 04:23:56,660 INFO L290 TraceCheckUtils]: 155: Hoare triple {157856#false} assume !(1 == ~E_9~0); {157856#false} is VALID [2022-02-21 04:23:56,660 INFO L290 TraceCheckUtils]: 156: Hoare triple {157856#false} assume !(1 == ~E_10~0); {157856#false} is VALID [2022-02-21 04:23:56,660 INFO L290 TraceCheckUtils]: 157: Hoare triple {157856#false} assume !(1 == ~E_11~0); {157856#false} is VALID [2022-02-21 04:23:56,661 INFO L290 TraceCheckUtils]: 158: Hoare triple {157856#false} assume !(1 == ~E_12~0); {157856#false} is VALID [2022-02-21 04:23:56,661 INFO L290 TraceCheckUtils]: 159: Hoare triple {157856#false} assume 1 == ~E_13~0;~E_13~0 := 2; {157856#false} is VALID [2022-02-21 04:23:56,661 INFO L290 TraceCheckUtils]: 160: Hoare triple {157856#false} assume { :end_inline_reset_delta_events } true; {157856#false} is VALID [2022-02-21 04:23:56,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:56,662 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:56,662 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [705404715] [2022-02-21 04:23:56,662 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [705404715] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:56,662 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:56,662 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:56,662 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1161030038] [2022-02-21 04:23:56,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:56,663 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:56,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:56,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1925993566, now seen corresponding path program 1 times [2022-02-21 04:23:56,664 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:56,664 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268781423] [2022-02-21 04:23:56,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:56,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:56,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:56,697 INFO L290 TraceCheckUtils]: 0: Hoare triple {157859#true} assume !false; {157859#true} is VALID [2022-02-21 04:23:56,697 INFO L290 TraceCheckUtils]: 1: Hoare triple {157859#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {157859#true} is VALID [2022-02-21 04:23:56,697 INFO L290 TraceCheckUtils]: 2: Hoare triple {157859#true} assume !false; {157859#true} is VALID [2022-02-21 04:23:56,698 INFO L290 TraceCheckUtils]: 3: Hoare triple {157859#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {157859#true} is VALID [2022-02-21 04:23:56,698 INFO L290 TraceCheckUtils]: 4: Hoare triple {157859#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {157859#true} is VALID [2022-02-21 04:23:56,698 INFO L290 TraceCheckUtils]: 5: Hoare triple {157859#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {157859#true} is VALID [2022-02-21 04:23:56,698 INFO L290 TraceCheckUtils]: 6: Hoare triple {157859#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {157859#true} is VALID [2022-02-21 04:23:56,698 INFO L290 TraceCheckUtils]: 7: Hoare triple {157859#true} assume !(0 != eval_~tmp~0#1); {157859#true} is VALID [2022-02-21 04:23:56,698 INFO L290 TraceCheckUtils]: 8: Hoare triple {157859#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {157859#true} is VALID [2022-02-21 04:23:56,698 INFO L290 TraceCheckUtils]: 9: Hoare triple {157859#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {157859#true} is VALID [2022-02-21 04:23:56,698 INFO L290 TraceCheckUtils]: 10: Hoare triple {157859#true} assume !(0 == ~M_E~0); {157859#true} is VALID [2022-02-21 04:23:56,699 INFO L290 TraceCheckUtils]: 11: Hoare triple {157859#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {157859#true} is VALID [2022-02-21 04:23:56,699 INFO L290 TraceCheckUtils]: 12: Hoare triple {157859#true} assume !(0 == ~T2_E~0); {157859#true} is VALID [2022-02-21 04:23:56,699 INFO L290 TraceCheckUtils]: 13: Hoare triple {157859#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {157859#true} is VALID [2022-02-21 04:23:56,699 INFO L290 TraceCheckUtils]: 14: Hoare triple {157859#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {157859#true} is VALID [2022-02-21 04:23:56,699 INFO L290 TraceCheckUtils]: 15: Hoare triple {157859#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,700 INFO L290 TraceCheckUtils]: 16: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,700 INFO L290 TraceCheckUtils]: 17: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,701 INFO L290 TraceCheckUtils]: 18: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T8_E~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,701 INFO L290 TraceCheckUtils]: 19: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,701 INFO L290 TraceCheckUtils]: 20: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,702 INFO L290 TraceCheckUtils]: 21: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,702 INFO L290 TraceCheckUtils]: 22: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,702 INFO L290 TraceCheckUtils]: 23: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,703 INFO L290 TraceCheckUtils]: 24: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,703 INFO L290 TraceCheckUtils]: 25: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,704 INFO L290 TraceCheckUtils]: 26: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_2~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,704 INFO L290 TraceCheckUtils]: 27: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,704 INFO L290 TraceCheckUtils]: 28: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,705 INFO L290 TraceCheckUtils]: 29: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,705 INFO L290 TraceCheckUtils]: 30: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,705 INFO L290 TraceCheckUtils]: 31: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,706 INFO L290 TraceCheckUtils]: 32: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,706 INFO L290 TraceCheckUtils]: 33: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,707 INFO L290 TraceCheckUtils]: 34: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,707 INFO L290 TraceCheckUtils]: 35: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,707 INFO L290 TraceCheckUtils]: 36: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,708 INFO L290 TraceCheckUtils]: 37: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,708 INFO L290 TraceCheckUtils]: 38: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,709 INFO L290 TraceCheckUtils]: 39: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,709 INFO L290 TraceCheckUtils]: 40: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,709 INFO L290 TraceCheckUtils]: 41: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,710 INFO L290 TraceCheckUtils]: 42: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,710 INFO L290 TraceCheckUtils]: 43: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,710 INFO L290 TraceCheckUtils]: 44: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,711 INFO L290 TraceCheckUtils]: 45: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,711 INFO L290 TraceCheckUtils]: 46: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,712 INFO L290 TraceCheckUtils]: 47: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,712 INFO L290 TraceCheckUtils]: 48: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,712 INFO L290 TraceCheckUtils]: 49: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,713 INFO L290 TraceCheckUtils]: 50: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,713 INFO L290 TraceCheckUtils]: 51: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,713 INFO L290 TraceCheckUtils]: 52: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,714 INFO L290 TraceCheckUtils]: 53: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,714 INFO L290 TraceCheckUtils]: 54: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,715 INFO L290 TraceCheckUtils]: 55: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,715 INFO L290 TraceCheckUtils]: 56: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,715 INFO L290 TraceCheckUtils]: 57: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,716 INFO L290 TraceCheckUtils]: 58: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,716 INFO L290 TraceCheckUtils]: 59: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,716 INFO L290 TraceCheckUtils]: 60: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,717 INFO L290 TraceCheckUtils]: 61: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,717 INFO L290 TraceCheckUtils]: 62: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,718 INFO L290 TraceCheckUtils]: 63: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,718 INFO L290 TraceCheckUtils]: 64: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,718 INFO L290 TraceCheckUtils]: 65: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,719 INFO L290 TraceCheckUtils]: 66: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,719 INFO L290 TraceCheckUtils]: 67: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,719 INFO L290 TraceCheckUtils]: 68: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,720 INFO L290 TraceCheckUtils]: 69: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,720 INFO L290 TraceCheckUtils]: 70: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,721 INFO L290 TraceCheckUtils]: 71: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,721 INFO L290 TraceCheckUtils]: 72: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,721 INFO L290 TraceCheckUtils]: 73: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,722 INFO L290 TraceCheckUtils]: 74: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,722 INFO L290 TraceCheckUtils]: 75: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,722 INFO L290 TraceCheckUtils]: 76: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,723 INFO L290 TraceCheckUtils]: 77: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,723 INFO L290 TraceCheckUtils]: 78: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,723 INFO L290 TraceCheckUtils]: 79: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,724 INFO L290 TraceCheckUtils]: 80: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,724 INFO L290 TraceCheckUtils]: 81: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,725 INFO L290 TraceCheckUtils]: 82: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,725 INFO L290 TraceCheckUtils]: 83: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,725 INFO L290 TraceCheckUtils]: 84: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,726 INFO L290 TraceCheckUtils]: 85: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,726 INFO L290 TraceCheckUtils]: 86: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,726 INFO L290 TraceCheckUtils]: 87: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,727 INFO L290 TraceCheckUtils]: 88: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,727 INFO L290 TraceCheckUtils]: 89: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,727 INFO L290 TraceCheckUtils]: 90: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,728 INFO L290 TraceCheckUtils]: 91: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,728 INFO L290 TraceCheckUtils]: 92: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,729 INFO L290 TraceCheckUtils]: 93: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,729 INFO L290 TraceCheckUtils]: 94: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,729 INFO L290 TraceCheckUtils]: 95: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,730 INFO L290 TraceCheckUtils]: 96: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,730 INFO L290 TraceCheckUtils]: 97: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,730 INFO L290 TraceCheckUtils]: 98: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,731 INFO L290 TraceCheckUtils]: 99: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,731 INFO L290 TraceCheckUtils]: 100: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,732 INFO L290 TraceCheckUtils]: 101: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,732 INFO L290 TraceCheckUtils]: 102: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,732 INFO L290 TraceCheckUtils]: 103: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,733 INFO L290 TraceCheckUtils]: 104: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,733 INFO L290 TraceCheckUtils]: 105: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,733 INFO L290 TraceCheckUtils]: 106: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,734 INFO L290 TraceCheckUtils]: 107: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,734 INFO L290 TraceCheckUtils]: 108: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,734 INFO L290 TraceCheckUtils]: 109: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,735 INFO L290 TraceCheckUtils]: 110: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,735 INFO L290 TraceCheckUtils]: 111: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t12_pc~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,736 INFO L290 TraceCheckUtils]: 112: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,736 INFO L290 TraceCheckUtils]: 113: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,736 INFO L290 TraceCheckUtils]: 114: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,737 INFO L290 TraceCheckUtils]: 115: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,737 INFO L290 TraceCheckUtils]: 116: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,737 INFO L290 TraceCheckUtils]: 117: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,738 INFO L290 TraceCheckUtils]: 118: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,738 INFO L290 TraceCheckUtils]: 119: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,738 INFO L290 TraceCheckUtils]: 120: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,739 INFO L290 TraceCheckUtils]: 121: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,739 INFO L290 TraceCheckUtils]: 122: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,740 INFO L290 TraceCheckUtils]: 123: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~M_E~0); {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,740 INFO L290 TraceCheckUtils]: 124: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,740 INFO L290 TraceCheckUtils]: 125: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,741 INFO L290 TraceCheckUtils]: 126: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,741 INFO L290 TraceCheckUtils]: 127: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {157861#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:23:56,741 INFO L290 TraceCheckUtils]: 128: Hoare triple {157861#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {157860#false} is VALID [2022-02-21 04:23:56,742 INFO L290 TraceCheckUtils]: 129: Hoare triple {157860#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,742 INFO L290 TraceCheckUtils]: 130: Hoare triple {157860#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,742 INFO L290 TraceCheckUtils]: 131: Hoare triple {157860#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,742 INFO L290 TraceCheckUtils]: 132: Hoare triple {157860#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,742 INFO L290 TraceCheckUtils]: 133: Hoare triple {157860#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,742 INFO L290 TraceCheckUtils]: 134: Hoare triple {157860#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,742 INFO L290 TraceCheckUtils]: 135: Hoare triple {157860#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,742 INFO L290 TraceCheckUtils]: 136: Hoare triple {157860#false} assume !(1 == ~T13_E~0); {157860#false} is VALID [2022-02-21 04:23:56,743 INFO L290 TraceCheckUtils]: 137: Hoare triple {157860#false} assume 1 == ~E_M~0;~E_M~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,743 INFO L290 TraceCheckUtils]: 138: Hoare triple {157860#false} assume 1 == ~E_1~0;~E_1~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,743 INFO L290 TraceCheckUtils]: 139: Hoare triple {157860#false} assume !(1 == ~E_2~0); {157860#false} is VALID [2022-02-21 04:23:56,743 INFO L290 TraceCheckUtils]: 140: Hoare triple {157860#false} assume 1 == ~E_3~0;~E_3~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,743 INFO L290 TraceCheckUtils]: 141: Hoare triple {157860#false} assume 1 == ~E_4~0;~E_4~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,743 INFO L290 TraceCheckUtils]: 142: Hoare triple {157860#false} assume 1 == ~E_5~0;~E_5~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,743 INFO L290 TraceCheckUtils]: 143: Hoare triple {157860#false} assume 1 == ~E_6~0;~E_6~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,743 INFO L290 TraceCheckUtils]: 144: Hoare triple {157860#false} assume !(1 == ~E_7~0); {157860#false} is VALID [2022-02-21 04:23:56,744 INFO L290 TraceCheckUtils]: 145: Hoare triple {157860#false} assume 1 == ~E_8~0;~E_8~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,744 INFO L290 TraceCheckUtils]: 146: Hoare triple {157860#false} assume 1 == ~E_9~0;~E_9~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,744 INFO L290 TraceCheckUtils]: 147: Hoare triple {157860#false} assume 1 == ~E_10~0;~E_10~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,744 INFO L290 TraceCheckUtils]: 148: Hoare triple {157860#false} assume 1 == ~E_11~0;~E_11~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,744 INFO L290 TraceCheckUtils]: 149: Hoare triple {157860#false} assume 1 == ~E_12~0;~E_12~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,744 INFO L290 TraceCheckUtils]: 150: Hoare triple {157860#false} assume 1 == ~E_13~0;~E_13~0 := 2; {157860#false} is VALID [2022-02-21 04:23:56,744 INFO L290 TraceCheckUtils]: 151: Hoare triple {157860#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {157860#false} is VALID [2022-02-21 04:23:56,745 INFO L290 TraceCheckUtils]: 152: Hoare triple {157860#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {157860#false} is VALID [2022-02-21 04:23:56,745 INFO L290 TraceCheckUtils]: 153: Hoare triple {157860#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {157860#false} is VALID [2022-02-21 04:23:56,745 INFO L290 TraceCheckUtils]: 154: Hoare triple {157860#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {157860#false} is VALID [2022-02-21 04:23:56,745 INFO L290 TraceCheckUtils]: 155: Hoare triple {157860#false} assume !(0 == start_simulation_~tmp~3#1); {157860#false} is VALID [2022-02-21 04:23:56,745 INFO L290 TraceCheckUtils]: 156: Hoare triple {157860#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {157860#false} is VALID [2022-02-21 04:23:56,745 INFO L290 TraceCheckUtils]: 157: Hoare triple {157860#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {157860#false} is VALID [2022-02-21 04:23:56,745 INFO L290 TraceCheckUtils]: 158: Hoare triple {157860#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {157860#false} is VALID [2022-02-21 04:23:56,746 INFO L290 TraceCheckUtils]: 159: Hoare triple {157860#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {157860#false} is VALID [2022-02-21 04:23:56,746 INFO L290 TraceCheckUtils]: 160: Hoare triple {157860#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {157860#false} is VALID [2022-02-21 04:23:56,746 INFO L290 TraceCheckUtils]: 161: Hoare triple {157860#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {157860#false} is VALID [2022-02-21 04:23:56,746 INFO L290 TraceCheckUtils]: 162: Hoare triple {157860#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {157860#false} is VALID [2022-02-21 04:23:56,746 INFO L290 TraceCheckUtils]: 163: Hoare triple {157860#false} assume !(0 != start_simulation_~tmp___0~1#1); {157860#false} is VALID [2022-02-21 04:23:56,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:56,747 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:56,747 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268781423] [2022-02-21 04:23:56,747 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268781423] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:56,747 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:56,748 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:56,748 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [522085976] [2022-02-21 04:23:56,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:56,748 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:56,748 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:56,749 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:56,749 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:56,749 INFO L87 Difference]: Start difference. First operand 3771 states and 5505 transitions. cyclomatic complexity: 1735 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)