./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.13.cil-2.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.13.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:23:05,301 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:23:05,304 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:23:05,327 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:23:05,331 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:23:05,332 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:23:05,333 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:23:05,335 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:23:05,336 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:23:05,336 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:23:05,337 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:23:05,338 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:23:05,338 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:23:05,338 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:23:05,339 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:23:05,340 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:23:05,341 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:23:05,341 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:23:05,342 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:23:05,343 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:23:05,348 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:23:05,352 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:23:05,353 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:23:05,354 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:23:05,355 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:23:05,359 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:23:05,359 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:23:05,360 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:23:05,360 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:23:05,361 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:23:05,361 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:23:05,361 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:23:05,362 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:23:05,363 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:23:05,364 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:23:05,364 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:23:05,365 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:23:05,365 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:23:05,366 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:23:05,366 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:23:05,367 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:23:05,368 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:23:05,390 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:23:05,393 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:23:05,394 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:23:05,394 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:23:05,395 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:23:05,396 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:23:05,396 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:23:05,396 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:23:05,396 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:23:05,396 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:23:05,397 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:23:05,397 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:23:05,397 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:23:05,397 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:23:05,398 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:23:05,398 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:23:05,398 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:23:05,398 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:23:05,398 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:23:05,398 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:23:05,398 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:23:05,398 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:23:05,399 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:23:05,399 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:23:05,399 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:23:05,399 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:23:05,399 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:23:05,399 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:23:05,400 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:23:05,400 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:23:05,400 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:23:05,401 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:23:05,401 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 [2022-02-21 04:23:05,600 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:23:05,614 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:23:05,616 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:23:05,617 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:23:05,617 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:23:05,618 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2022-02-21 04:23:05,657 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b1ad5a13c/606931c5769f45adadfae21a84e02538/FLAG868a8dbb7 [2022-02-21 04:23:06,047 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:23:06,048 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2022-02-21 04:23:06,058 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b1ad5a13c/606931c5769f45adadfae21a84e02538/FLAG868a8dbb7 [2022-02-21 04:23:06,067 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b1ad5a13c/606931c5769f45adadfae21a84e02538 [2022-02-21 04:23:06,071 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:23:06,073 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:23:06,075 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:06,075 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:23:06,077 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:23:06,078 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,079 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4c34b702 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06, skipping insertion in model container [2022-02-21 04:23:06,079 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,084 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:23:06,121 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:23:06,266 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-2.c[671,684] [2022-02-21 04:23:06,390 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:06,410 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:23:06,419 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-2.c[671,684] [2022-02-21 04:23:06,485 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:06,510 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:23:06,511 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06 WrapperNode [2022-02-21 04:23:06,511 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:06,512 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:06,513 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:23:06,513 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:23:06,519 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,534 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,659 INFO L137 Inliner]: procedures = 54, calls = 70, calls flagged for inlining = 65, calls inlined = 302, statements flattened = 4653 [2022-02-21 04:23:06,659 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:06,660 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:23:06,660 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:23:06,660 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:23:06,666 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,666 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,678 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,679 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,721 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,783 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,792 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,845 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:23:06,846 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:23:06,846 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:23:06,846 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:23:06,847 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,858 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:23:06,866 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:23:06,876 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:23:06,878 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:23:06,905 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:23:06,905 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:23:06,906 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:23:06,906 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:23:06,996 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:23:06,997 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:23:08,794 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:23:08,807 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:23:08,808 INFO L299 CfgBuilder]: Removed 16 assume(true) statements. [2022-02-21 04:23:08,810 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:08 BoogieIcfgContainer [2022-02-21 04:23:08,810 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:23:08,811 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:23:08,811 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:23:08,814 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:23:08,815 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:08,815 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:23:06" (1/3) ... [2022-02-21 04:23:08,816 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7bb17304 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:08, skipping insertion in model container [2022-02-21 04:23:08,816 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:08,816 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06" (2/3) ... [2022-02-21 04:23:08,816 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7bb17304 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:08, skipping insertion in model container [2022-02-21 04:23:08,817 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:08,817 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:08" (3/3) ... [2022-02-21 04:23:08,818 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-2.c [2022-02-21 04:23:08,848 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:23:08,848 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:23:08,848 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:23:08,849 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:23:08,849 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:23:08,849 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:23:08,849 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:23:08,849 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:23:08,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,257 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1845 [2022-02-21 04:23:09,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:09,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:09,269 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,269 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,270 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:23:09,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1845 [2022-02-21 04:23:09,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:09,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:09,500 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,506 INFO L791 eck$LassoCheckResult]: Stem: 473#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1943#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1566#L1891true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 827#L895true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1866#L902true assume !(1 == ~m_i~0);~m_st~0 := 2; 461#L902-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1625#L907-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 504#L912-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1550#L917-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 822#L922-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 985#L927-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 483#L932-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 375#L937-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1475#L942-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 658#L947-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1539#L952-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 574#L957-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 902#L962-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 357#L967-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1961#L1279true assume 0 == ~M_E~0;~M_E~0 := 1; 1551#L1279-2true assume !(0 == ~T1_E~0); 160#L1284-1true assume !(0 == ~T2_E~0); 1773#L1289-1true assume !(0 == ~T3_E~0); 571#L1294-1true assume !(0 == ~T4_E~0); 578#L1299-1true assume !(0 == ~T5_E~0); 1857#L1304-1true assume !(0 == ~T6_E~0); 1902#L1309-1true assume !(0 == ~T7_E~0); 1875#L1314-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 124#L1319-1true assume !(0 == ~T9_E~0); 1109#L1324-1true assume !(0 == ~T10_E~0); 214#L1329-1true assume !(0 == ~T11_E~0); 1365#L1334-1true assume !(0 == ~T12_E~0); 1804#L1339-1true assume !(0 == ~T13_E~0); 1527#L1344-1true assume !(0 == ~E_M~0); 1959#L1349-1true assume !(0 == ~E_1~0); 708#L1354-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1114#L1359-1true assume !(0 == ~E_3~0); 1778#L1364-1true assume !(0 == ~E_4~0); 282#L1369-1true assume !(0 == ~E_5~0); 1090#L1374-1true assume !(0 == ~E_6~0); 712#L1379-1true assume !(0 == ~E_7~0); 771#L1384-1true assume !(0 == ~E_8~0); 2001#L1389-1true assume !(0 == ~E_9~0); 1402#L1394-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1873#L1399-1true assume !(0 == ~E_11~0); 1642#L1404-1true assume !(0 == ~E_12~0); 329#L1409-1true assume !(0 == ~E_13~0); 1616#L1414-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1955#L628true assume !(1 == ~m_pc~0); 1413#L628-2true is_master_triggered_~__retres1~0#1 := 0; 935#L639true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 770#L640true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1660#L1591true assume !(0 != activate_threads_~tmp~1#1); 1890#L1591-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 606#L647true assume 1 == ~t1_pc~0; 239#L648true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 647#L658true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 383#L659true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1639#L1599true assume !(0 != activate_threads_~tmp___0~0#1); 1503#L1599-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1913#L666true assume 1 == ~t2_pc~0; 159#L667true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 246#L677true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1620#L678true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1532#L1607true assume !(0 != activate_threads_~tmp___1~0#1); 864#L1607-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1858#L685true assume !(1 == ~t3_pc~0); 1026#L685-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1686#L696true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 650#L697true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 747#L1615true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1065#L1615-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 402#L704true assume 1 == ~t4_pc~0; 1246#L705true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 758#L715true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1578#L716true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1774#L1623true assume !(0 != activate_threads_~tmp___3~0#1); 645#L1623-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 743#L723true assume !(1 == ~t5_pc~0); 947#L723-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1108#L734true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1533#L735true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 849#L1631true assume !(0 != activate_threads_~tmp___4~0#1); 868#L1631-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 273#L742true assume 1 == ~t6_pc~0; 959#L743true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 349#L753true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 897#L754true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 109#L1639true assume !(0 != activate_threads_~tmp___5~0#1); 1357#L1639-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 313#L761true assume !(1 == ~t7_pc~0); 318#L761-2true is_transmit7_triggered_~__retres1~7#1 := 0; 244#L772true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1948#L773true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 749#L1647true assume !(0 != activate_threads_~tmp___6~0#1); 1560#L1647-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 121#L780true assume 1 == ~t8_pc~0; 579#L781true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 266#L791true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 907#L792true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 719#L1655true assume !(0 != activate_threads_~tmp___7~0#1); 811#L1655-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1395#L799true assume 1 == ~t9_pc~0; 911#L800true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 122#L810true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 820#L811true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1001#L1663true assume !(0 != activate_threads_~tmp___8~0#1); 1920#L1663-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 836#L818true assume !(1 == ~t10_pc~0); 24#L818-2true is_transmit10_triggered_~__retres1~10#1 := 0; 904#L829true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1744#L830true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 840#L1671true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1096#L1671-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 873#L837true assume 1 == ~t11_pc~0; 1797#L838true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1577#L848true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1136#L849true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 806#L1679true assume !(0 != activate_threads_~tmp___10~0#1); 1861#L1679-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 613#L856true assume !(1 == ~t12_pc~0); 1443#L856-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1253#L867true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1795#L868true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1221#L1687true assume !(0 != activate_threads_~tmp___11~0#1); 1788#L1687-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1557#L875true assume 1 == ~t13_pc~0; 577#L876true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 351#L886true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1635#L887true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 321#L1695true assume !(0 != activate_threads_~tmp___12~0#1); 901#L1695-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1898#L1427true assume !(1 == ~M_E~0); 884#L1427-2true assume !(1 == ~T1_E~0); 306#L1432-1true assume !(1 == ~T2_E~0); 1561#L1437-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1124#L1442-1true assume !(1 == ~T4_E~0); 1485#L1447-1true assume !(1 == ~T5_E~0); 955#L1452-1true assume !(1 == ~T6_E~0); 84#L1457-1true assume !(1 == ~T7_E~0); 1160#L1462-1true assume !(1 == ~T8_E~0); 1844#L1467-1true assume !(1 == ~T9_E~0); 1185#L1472-1true assume !(1 == ~T10_E~0); 1371#L1477-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 900#L1482-1true assume !(1 == ~T12_E~0); 1299#L1487-1true assume !(1 == ~T13_E~0); 252#L1492-1true assume !(1 == ~E_M~0); 656#L1497-1true assume !(1 == ~E_1~0); 449#L1502-1true assume !(1 == ~E_2~0); 1297#L1507-1true assume !(1 == ~E_3~0); 189#L1512-1true assume !(1 == ~E_4~0); 1279#L1517-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1390#L1522-1true assume !(1 == ~E_6~0); 604#L1527-1true assume !(1 == ~E_7~0); 1755#L1532-1true assume !(1 == ~E_8~0); 2014#L1537-1true assume !(1 == ~E_9~0); 762#L1542-1true assume !(1 == ~E_10~0); 630#L1547-1true assume !(1 == ~E_11~0); 1782#L1552-1true assume !(1 == ~E_12~0); 42#L1557-1true assume 1 == ~E_13~0;~E_13~0 := 2; 344#L1562-1true assume { :end_inline_reset_delta_events } true; 742#L1928-2true [2022-02-21 04:23:09,509 INFO L793 eck$LassoCheckResult]: Loop: 742#L1928-2true assume !false; 653#L1929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 489#L1254true assume false; 442#L1269true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 212#L895-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1605#L1279-3true assume 0 == ~M_E~0;~M_E~0 := 1; 463#L1279-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 451#L1284-3true assume !(0 == ~T2_E~0); 1669#L1289-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 441#L1294-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1894#L1299-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 706#L1304-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1145#L1309-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 381#L1314-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1971#L1319-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1210#L1324-3true assume !(0 == ~T10_E~0); 187#L1329-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1823#L1334-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 636#L1339-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 928#L1344-3true assume 0 == ~E_M~0;~E_M~0 := 1; 870#L1349-3true assume 0 == ~E_1~0;~E_1~0 := 1; 369#L1354-3true assume 0 == ~E_2~0;~E_2~0 := 1; 881#L1359-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1856#L1364-3true assume !(0 == ~E_4~0); 1743#L1369-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1437#L1374-3true assume 0 == ~E_6~0;~E_6~0 := 1; 254#L1379-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1304#L1384-3true assume 0 == ~E_8~0;~E_8~0 := 1; 368#L1389-3true assume 0 == ~E_9~0;~E_9~0 := 1; 544#L1394-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1946#L1399-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1465#L1404-3true assume !(0 == ~E_12~0); 1389#L1409-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1549#L1414-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 782#L628-45true assume 1 == ~m_pc~0; 543#L629-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1737#L639-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 182#L640-15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 389#L1591-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1671#L1591-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 910#L647-45true assume !(1 == ~t1_pc~0); 1396#L647-47true is_transmit1_triggered_~__retres1~1#1 := 0; 718#L658-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 966#L659-15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 217#L1599-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1548#L1599-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 327#L666-45true assume 1 == ~t2_pc~0; 1919#L667-15true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1692#L677-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1144#L678-15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1016#L1607-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1011#L1607-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92#L685-45true assume !(1 == ~t3_pc~0); 1416#L685-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1531#L696-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1582#L697-15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1274#L1615-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1553#L1615-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1638#L704-45true assume 1 == ~t4_pc~0; 1311#L705-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 481#L715-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 721#L716-15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2017#L1623-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1980#L1623-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 808#L723-45true assume !(1 == ~t5_pc~0); 1404#L723-47true is_transmit5_triggered_~__retres1~5#1 := 0; 1703#L734-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 510#L735-15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 376#L1631-45true assume !(0 != activate_threads_~tmp___4~0#1); 1929#L1631-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1236#L742-45true assume !(1 == ~t6_pc~0); 526#L742-47true is_transmit6_triggered_~__retres1~6#1 := 0; 879#L753-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1088#L754-15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 915#L1639-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1278#L1639-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 990#L761-45true assume !(1 == ~t7_pc~0); 1167#L761-47true is_transmit7_triggered_~__retres1~7#1 := 0; 521#L772-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1042#L773-15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 191#L1647-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1954#L1647-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1393#L780-45true assume !(1 == ~t8_pc~0); 1179#L780-47true is_transmit8_triggered_~__retres1~8#1 := 0; 197#L791-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1956#L792-15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1754#L1655-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 179#L1655-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 634#L799-45true assume !(1 == ~t9_pc~0); 297#L799-47true is_transmit9_triggered_~__retres1~9#1 := 0; 2007#L810-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1502#L811-15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 956#L1663-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1817#L1663-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 149#L818-45true assume 1 == ~t10_pc~0; 1058#L819-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 934#L829-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1829#L830-15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 480#L1671-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1048#L1671-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1523#L837-45true assume 1 == ~t11_pc~0; 1764#L838-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 522#L848-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1070#L849-15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1848#L1679-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 221#L1679-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2026#L856-45true assume 1 == ~t12_pc~0; 1545#L857-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1273#L867-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 192#L868-15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1800#L1687-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 717#L1687-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1281#L875-45true assume !(1 == ~t13_pc~0); 701#L875-47true is_transmit13_triggered_~__retres1~13#1 := 0; 741#L886-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1851#L887-15true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1484#L1695-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1766#L1695-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1363#L1427-3true assume !(1 == ~M_E~0); 567#L1427-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1562#L1432-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 997#L1437-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 707#L1442-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1017#L1447-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 50#L1452-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1979#L1457-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1259#L1462-3true assume !(1 == ~T8_E~0); 1681#L1467-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1068#L1472-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1709#L1477-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 170#L1482-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 243#L1487-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1809#L1492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 332#L1497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1020#L1502-3true assume !(1 == ~E_2~0); 1208#L1507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1918#L1512-3true assume 1 == ~E_4~0;~E_4~0 := 2; 353#L1517-3true assume 1 == ~E_5~0;~E_5~0 := 2; 194#L1522-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1682#L1527-3true assume 1 == ~E_7~0;~E_7~0 := 2; 174#L1532-3true assume 1 == ~E_8~0;~E_8~0 := 2; 882#L1537-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1574#L1542-3true assume !(1 == ~E_10~0); 1004#L1547-3true assume 1 == ~E_11~0;~E_11~0 := 2; 697#L1552-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1398#L1557-3true assume 1 == ~E_13~0;~E_13~0 := 2; 286#L1562-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1970#L980-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1414#L1052-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 384#L1053-1true start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 799#L1947true assume !(0 == start_simulation_~tmp~3#1); 978#L1947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1129#L980-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1628#L1052-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1645#L1053-2true stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1451#L1902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1173#L1909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 894#L1910true start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1715#L1960true assume !(0 != start_simulation_~tmp___0~1#1); 742#L1928-2true [2022-02-21 04:23:09,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,514 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2022-02-21 04:23:09,523 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,524 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341359912] [2022-02-21 04:23:09,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,724 INFO L290 TraceCheckUtils]: 0: Hoare triple {2028#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {2028#true} is VALID [2022-02-21 04:23:09,726 INFO L290 TraceCheckUtils]: 1: Hoare triple {2028#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {2030#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:09,726 INFO L290 TraceCheckUtils]: 2: Hoare triple {2030#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {2030#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:09,727 INFO L290 TraceCheckUtils]: 3: Hoare triple {2030#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {2030#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:09,727 INFO L290 TraceCheckUtils]: 4: Hoare triple {2030#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,728 INFO L290 TraceCheckUtils]: 5: Hoare triple {2029#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {2029#false} is VALID [2022-02-21 04:23:09,728 INFO L290 TraceCheckUtils]: 6: Hoare triple {2029#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,729 INFO L290 TraceCheckUtils]: 7: Hoare triple {2029#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,729 INFO L290 TraceCheckUtils]: 8: Hoare triple {2029#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,729 INFO L290 TraceCheckUtils]: 9: Hoare triple {2029#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,729 INFO L290 TraceCheckUtils]: 10: Hoare triple {2029#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,730 INFO L290 TraceCheckUtils]: 11: Hoare triple {2029#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,730 INFO L290 TraceCheckUtils]: 12: Hoare triple {2029#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,730 INFO L290 TraceCheckUtils]: 13: Hoare triple {2029#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {2029#false} is VALID [2022-02-21 04:23:09,730 INFO L290 TraceCheckUtils]: 14: Hoare triple {2029#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,730 INFO L290 TraceCheckUtils]: 15: Hoare triple {2029#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,731 INFO L290 TraceCheckUtils]: 16: Hoare triple {2029#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,731 INFO L290 TraceCheckUtils]: 17: Hoare triple {2029#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,731 INFO L290 TraceCheckUtils]: 18: Hoare triple {2029#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {2029#false} is VALID [2022-02-21 04:23:09,731 INFO L290 TraceCheckUtils]: 19: Hoare triple {2029#false} assume 0 == ~M_E~0;~M_E~0 := 1; {2029#false} is VALID [2022-02-21 04:23:09,731 INFO L290 TraceCheckUtils]: 20: Hoare triple {2029#false} assume !(0 == ~T1_E~0); {2029#false} is VALID [2022-02-21 04:23:09,732 INFO L290 TraceCheckUtils]: 21: Hoare triple {2029#false} assume !(0 == ~T2_E~0); {2029#false} is VALID [2022-02-21 04:23:09,732 INFO L290 TraceCheckUtils]: 22: Hoare triple {2029#false} assume !(0 == ~T3_E~0); {2029#false} is VALID [2022-02-21 04:23:09,732 INFO L290 TraceCheckUtils]: 23: Hoare triple {2029#false} assume !(0 == ~T4_E~0); {2029#false} is VALID [2022-02-21 04:23:09,733 INFO L290 TraceCheckUtils]: 24: Hoare triple {2029#false} assume !(0 == ~T5_E~0); {2029#false} is VALID [2022-02-21 04:23:09,733 INFO L290 TraceCheckUtils]: 25: Hoare triple {2029#false} assume !(0 == ~T6_E~0); {2029#false} is VALID [2022-02-21 04:23:09,733 INFO L290 TraceCheckUtils]: 26: Hoare triple {2029#false} assume !(0 == ~T7_E~0); {2029#false} is VALID [2022-02-21 04:23:09,734 INFO L290 TraceCheckUtils]: 27: Hoare triple {2029#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {2029#false} is VALID [2022-02-21 04:23:09,734 INFO L290 TraceCheckUtils]: 28: Hoare triple {2029#false} assume !(0 == ~T9_E~0); {2029#false} is VALID [2022-02-21 04:23:09,734 INFO L290 TraceCheckUtils]: 29: Hoare triple {2029#false} assume !(0 == ~T10_E~0); {2029#false} is VALID [2022-02-21 04:23:09,734 INFO L290 TraceCheckUtils]: 30: Hoare triple {2029#false} assume !(0 == ~T11_E~0); {2029#false} is VALID [2022-02-21 04:23:09,735 INFO L290 TraceCheckUtils]: 31: Hoare triple {2029#false} assume !(0 == ~T12_E~0); {2029#false} is VALID [2022-02-21 04:23:09,735 INFO L290 TraceCheckUtils]: 32: Hoare triple {2029#false} assume !(0 == ~T13_E~0); {2029#false} is VALID [2022-02-21 04:23:09,735 INFO L290 TraceCheckUtils]: 33: Hoare triple {2029#false} assume !(0 == ~E_M~0); {2029#false} is VALID [2022-02-21 04:23:09,735 INFO L290 TraceCheckUtils]: 34: Hoare triple {2029#false} assume !(0 == ~E_1~0); {2029#false} is VALID [2022-02-21 04:23:09,735 INFO L290 TraceCheckUtils]: 35: Hoare triple {2029#false} assume 0 == ~E_2~0;~E_2~0 := 1; {2029#false} is VALID [2022-02-21 04:23:09,736 INFO L290 TraceCheckUtils]: 36: Hoare triple {2029#false} assume !(0 == ~E_3~0); {2029#false} is VALID [2022-02-21 04:23:09,736 INFO L290 TraceCheckUtils]: 37: Hoare triple {2029#false} assume !(0 == ~E_4~0); {2029#false} is VALID [2022-02-21 04:23:09,736 INFO L290 TraceCheckUtils]: 38: Hoare triple {2029#false} assume !(0 == ~E_5~0); {2029#false} is VALID [2022-02-21 04:23:09,736 INFO L290 TraceCheckUtils]: 39: Hoare triple {2029#false} assume !(0 == ~E_6~0); {2029#false} is VALID [2022-02-21 04:23:09,737 INFO L290 TraceCheckUtils]: 40: Hoare triple {2029#false} assume !(0 == ~E_7~0); {2029#false} is VALID [2022-02-21 04:23:09,737 INFO L290 TraceCheckUtils]: 41: Hoare triple {2029#false} assume !(0 == ~E_8~0); {2029#false} is VALID [2022-02-21 04:23:09,737 INFO L290 TraceCheckUtils]: 42: Hoare triple {2029#false} assume !(0 == ~E_9~0); {2029#false} is VALID [2022-02-21 04:23:09,737 INFO L290 TraceCheckUtils]: 43: Hoare triple {2029#false} assume 0 == ~E_10~0;~E_10~0 := 1; {2029#false} is VALID [2022-02-21 04:23:09,738 INFO L290 TraceCheckUtils]: 44: Hoare triple {2029#false} assume !(0 == ~E_11~0); {2029#false} is VALID [2022-02-21 04:23:09,738 INFO L290 TraceCheckUtils]: 45: Hoare triple {2029#false} assume !(0 == ~E_12~0); {2029#false} is VALID [2022-02-21 04:23:09,738 INFO L290 TraceCheckUtils]: 46: Hoare triple {2029#false} assume !(0 == ~E_13~0); {2029#false} is VALID [2022-02-21 04:23:09,738 INFO L290 TraceCheckUtils]: 47: Hoare triple {2029#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2029#false} is VALID [2022-02-21 04:23:09,739 INFO L290 TraceCheckUtils]: 48: Hoare triple {2029#false} assume !(1 == ~m_pc~0); {2029#false} is VALID [2022-02-21 04:23:09,739 INFO L290 TraceCheckUtils]: 49: Hoare triple {2029#false} is_master_triggered_~__retres1~0#1 := 0; {2029#false} is VALID [2022-02-21 04:23:09,742 INFO L290 TraceCheckUtils]: 50: Hoare triple {2029#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2029#false} is VALID [2022-02-21 04:23:09,742 INFO L290 TraceCheckUtils]: 51: Hoare triple {2029#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {2029#false} is VALID [2022-02-21 04:23:09,743 INFO L290 TraceCheckUtils]: 52: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp~1#1); {2029#false} is VALID [2022-02-21 04:23:09,743 INFO L290 TraceCheckUtils]: 53: Hoare triple {2029#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2029#false} is VALID [2022-02-21 04:23:09,743 INFO L290 TraceCheckUtils]: 54: Hoare triple {2029#false} assume 1 == ~t1_pc~0; {2029#false} is VALID [2022-02-21 04:23:09,745 INFO L290 TraceCheckUtils]: 55: Hoare triple {2029#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {2029#false} is VALID [2022-02-21 04:23:09,745 INFO L290 TraceCheckUtils]: 56: Hoare triple {2029#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2029#false} is VALID [2022-02-21 04:23:09,745 INFO L290 TraceCheckUtils]: 57: Hoare triple {2029#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {2029#false} is VALID [2022-02-21 04:23:09,746 INFO L290 TraceCheckUtils]: 58: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___0~0#1); {2029#false} is VALID [2022-02-21 04:23:09,746 INFO L290 TraceCheckUtils]: 59: Hoare triple {2029#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2029#false} is VALID [2022-02-21 04:23:09,746 INFO L290 TraceCheckUtils]: 60: Hoare triple {2029#false} assume 1 == ~t2_pc~0; {2029#false} is VALID [2022-02-21 04:23:09,747 INFO L290 TraceCheckUtils]: 61: Hoare triple {2029#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2029#false} is VALID [2022-02-21 04:23:09,747 INFO L290 TraceCheckUtils]: 62: Hoare triple {2029#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2029#false} is VALID [2022-02-21 04:23:09,748 INFO L290 TraceCheckUtils]: 63: Hoare triple {2029#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {2029#false} is VALID [2022-02-21 04:23:09,748 INFO L290 TraceCheckUtils]: 64: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___1~0#1); {2029#false} is VALID [2022-02-21 04:23:09,750 INFO L290 TraceCheckUtils]: 65: Hoare triple {2029#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2029#false} is VALID [2022-02-21 04:23:09,750 INFO L290 TraceCheckUtils]: 66: Hoare triple {2029#false} assume !(1 == ~t3_pc~0); {2029#false} is VALID [2022-02-21 04:23:09,750 INFO L290 TraceCheckUtils]: 67: Hoare triple {2029#false} is_transmit3_triggered_~__retres1~3#1 := 0; {2029#false} is VALID [2022-02-21 04:23:09,751 INFO L290 TraceCheckUtils]: 68: Hoare triple {2029#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2029#false} is VALID [2022-02-21 04:23:09,751 INFO L290 TraceCheckUtils]: 69: Hoare triple {2029#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {2029#false} is VALID [2022-02-21 04:23:09,752 INFO L290 TraceCheckUtils]: 70: Hoare triple {2029#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {2029#false} is VALID [2022-02-21 04:23:09,752 INFO L290 TraceCheckUtils]: 71: Hoare triple {2029#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2029#false} is VALID [2022-02-21 04:23:09,752 INFO L290 TraceCheckUtils]: 72: Hoare triple {2029#false} assume 1 == ~t4_pc~0; {2029#false} is VALID [2022-02-21 04:23:09,752 INFO L290 TraceCheckUtils]: 73: Hoare triple {2029#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {2029#false} is VALID [2022-02-21 04:23:09,757 INFO L290 TraceCheckUtils]: 74: Hoare triple {2029#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2029#false} is VALID [2022-02-21 04:23:09,758 INFO L290 TraceCheckUtils]: 75: Hoare triple {2029#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {2029#false} is VALID [2022-02-21 04:23:09,758 INFO L290 TraceCheckUtils]: 76: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___3~0#1); {2029#false} is VALID [2022-02-21 04:23:09,758 INFO L290 TraceCheckUtils]: 77: Hoare triple {2029#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {2029#false} is VALID [2022-02-21 04:23:09,758 INFO L290 TraceCheckUtils]: 78: Hoare triple {2029#false} assume !(1 == ~t5_pc~0); {2029#false} is VALID [2022-02-21 04:23:09,758 INFO L290 TraceCheckUtils]: 79: Hoare triple {2029#false} is_transmit5_triggered_~__retres1~5#1 := 0; {2029#false} is VALID [2022-02-21 04:23:09,759 INFO L290 TraceCheckUtils]: 80: Hoare triple {2029#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {2029#false} is VALID [2022-02-21 04:23:09,759 INFO L290 TraceCheckUtils]: 81: Hoare triple {2029#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {2029#false} is VALID [2022-02-21 04:23:09,759 INFO L290 TraceCheckUtils]: 82: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___4~0#1); {2029#false} is VALID [2022-02-21 04:23:09,759 INFO L290 TraceCheckUtils]: 83: Hoare triple {2029#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {2029#false} is VALID [2022-02-21 04:23:09,759 INFO L290 TraceCheckUtils]: 84: Hoare triple {2029#false} assume 1 == ~t6_pc~0; {2029#false} is VALID [2022-02-21 04:23:09,760 INFO L290 TraceCheckUtils]: 85: Hoare triple {2029#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {2029#false} is VALID [2022-02-21 04:23:09,760 INFO L290 TraceCheckUtils]: 86: Hoare triple {2029#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {2029#false} is VALID [2022-02-21 04:23:09,760 INFO L290 TraceCheckUtils]: 87: Hoare triple {2029#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {2029#false} is VALID [2022-02-21 04:23:09,760 INFO L290 TraceCheckUtils]: 88: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___5~0#1); {2029#false} is VALID [2022-02-21 04:23:09,761 INFO L290 TraceCheckUtils]: 89: Hoare triple {2029#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {2029#false} is VALID [2022-02-21 04:23:09,761 INFO L290 TraceCheckUtils]: 90: Hoare triple {2029#false} assume !(1 == ~t7_pc~0); {2029#false} is VALID [2022-02-21 04:23:09,761 INFO L290 TraceCheckUtils]: 91: Hoare triple {2029#false} is_transmit7_triggered_~__retres1~7#1 := 0; {2029#false} is VALID [2022-02-21 04:23:09,761 INFO L290 TraceCheckUtils]: 92: Hoare triple {2029#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {2029#false} is VALID [2022-02-21 04:23:09,761 INFO L290 TraceCheckUtils]: 93: Hoare triple {2029#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {2029#false} is VALID [2022-02-21 04:23:09,762 INFO L290 TraceCheckUtils]: 94: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___6~0#1); {2029#false} is VALID [2022-02-21 04:23:09,762 INFO L290 TraceCheckUtils]: 95: Hoare triple {2029#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {2029#false} is VALID [2022-02-21 04:23:09,762 INFO L290 TraceCheckUtils]: 96: Hoare triple {2029#false} assume 1 == ~t8_pc~0; {2029#false} is VALID [2022-02-21 04:23:09,762 INFO L290 TraceCheckUtils]: 97: Hoare triple {2029#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {2029#false} is VALID [2022-02-21 04:23:09,762 INFO L290 TraceCheckUtils]: 98: Hoare triple {2029#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {2029#false} is VALID [2022-02-21 04:23:09,763 INFO L290 TraceCheckUtils]: 99: Hoare triple {2029#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {2029#false} is VALID [2022-02-21 04:23:09,763 INFO L290 TraceCheckUtils]: 100: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___7~0#1); {2029#false} is VALID [2022-02-21 04:23:09,763 INFO L290 TraceCheckUtils]: 101: Hoare triple {2029#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {2029#false} is VALID [2022-02-21 04:23:09,763 INFO L290 TraceCheckUtils]: 102: Hoare triple {2029#false} assume 1 == ~t9_pc~0; {2029#false} is VALID [2022-02-21 04:23:09,763 INFO L290 TraceCheckUtils]: 103: Hoare triple {2029#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {2029#false} is VALID [2022-02-21 04:23:09,764 INFO L290 TraceCheckUtils]: 104: Hoare triple {2029#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {2029#false} is VALID [2022-02-21 04:23:09,764 INFO L290 TraceCheckUtils]: 105: Hoare triple {2029#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {2029#false} is VALID [2022-02-21 04:23:09,766 INFO L290 TraceCheckUtils]: 106: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___8~0#1); {2029#false} is VALID [2022-02-21 04:23:09,767 INFO L290 TraceCheckUtils]: 107: Hoare triple {2029#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {2029#false} is VALID [2022-02-21 04:23:09,767 INFO L290 TraceCheckUtils]: 108: Hoare triple {2029#false} assume !(1 == ~t10_pc~0); {2029#false} is VALID [2022-02-21 04:23:09,767 INFO L290 TraceCheckUtils]: 109: Hoare triple {2029#false} is_transmit10_triggered_~__retres1~10#1 := 0; {2029#false} is VALID [2022-02-21 04:23:09,767 INFO L290 TraceCheckUtils]: 110: Hoare triple {2029#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {2029#false} is VALID [2022-02-21 04:23:09,767 INFO L290 TraceCheckUtils]: 111: Hoare triple {2029#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {2029#false} is VALID [2022-02-21 04:23:09,768 INFO L290 TraceCheckUtils]: 112: Hoare triple {2029#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {2029#false} is VALID [2022-02-21 04:23:09,768 INFO L290 TraceCheckUtils]: 113: Hoare triple {2029#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {2029#false} is VALID [2022-02-21 04:23:09,769 INFO L290 TraceCheckUtils]: 114: Hoare triple {2029#false} assume 1 == ~t11_pc~0; {2029#false} is VALID [2022-02-21 04:23:09,769 INFO L290 TraceCheckUtils]: 115: Hoare triple {2029#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {2029#false} is VALID [2022-02-21 04:23:09,770 INFO L290 TraceCheckUtils]: 116: Hoare triple {2029#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {2029#false} is VALID [2022-02-21 04:23:09,771 INFO L290 TraceCheckUtils]: 117: Hoare triple {2029#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {2029#false} is VALID [2022-02-21 04:23:09,771 INFO L290 TraceCheckUtils]: 118: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___10~0#1); {2029#false} is VALID [2022-02-21 04:23:09,781 INFO L290 TraceCheckUtils]: 119: Hoare triple {2029#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {2029#false} is VALID [2022-02-21 04:23:09,782 INFO L290 TraceCheckUtils]: 120: Hoare triple {2029#false} assume !(1 == ~t12_pc~0); {2029#false} is VALID [2022-02-21 04:23:09,782 INFO L290 TraceCheckUtils]: 121: Hoare triple {2029#false} is_transmit12_triggered_~__retres1~12#1 := 0; {2029#false} is VALID [2022-02-21 04:23:09,782 INFO L290 TraceCheckUtils]: 122: Hoare triple {2029#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {2029#false} is VALID [2022-02-21 04:23:09,782 INFO L290 TraceCheckUtils]: 123: Hoare triple {2029#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {2029#false} is VALID [2022-02-21 04:23:09,783 INFO L290 TraceCheckUtils]: 124: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___11~0#1); {2029#false} is VALID [2022-02-21 04:23:09,783 INFO L290 TraceCheckUtils]: 125: Hoare triple {2029#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {2029#false} is VALID [2022-02-21 04:23:09,783 INFO L290 TraceCheckUtils]: 126: Hoare triple {2029#false} assume 1 == ~t13_pc~0; {2029#false} is VALID [2022-02-21 04:23:09,783 INFO L290 TraceCheckUtils]: 127: Hoare triple {2029#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {2029#false} is VALID [2022-02-21 04:23:09,783 INFO L290 TraceCheckUtils]: 128: Hoare triple {2029#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {2029#false} is VALID [2022-02-21 04:23:09,784 INFO L290 TraceCheckUtils]: 129: Hoare triple {2029#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {2029#false} is VALID [2022-02-21 04:23:09,784 INFO L290 TraceCheckUtils]: 130: Hoare triple {2029#false} assume !(0 != activate_threads_~tmp___12~0#1); {2029#false} is VALID [2022-02-21 04:23:09,784 INFO L290 TraceCheckUtils]: 131: Hoare triple {2029#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2029#false} is VALID [2022-02-21 04:23:09,784 INFO L290 TraceCheckUtils]: 132: Hoare triple {2029#false} assume !(1 == ~M_E~0); {2029#false} is VALID [2022-02-21 04:23:09,784 INFO L290 TraceCheckUtils]: 133: Hoare triple {2029#false} assume !(1 == ~T1_E~0); {2029#false} is VALID [2022-02-21 04:23:09,784 INFO L290 TraceCheckUtils]: 134: Hoare triple {2029#false} assume !(1 == ~T2_E~0); {2029#false} is VALID [2022-02-21 04:23:09,785 INFO L290 TraceCheckUtils]: 135: Hoare triple {2029#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,785 INFO L290 TraceCheckUtils]: 136: Hoare triple {2029#false} assume !(1 == ~T4_E~0); {2029#false} is VALID [2022-02-21 04:23:09,785 INFO L290 TraceCheckUtils]: 137: Hoare triple {2029#false} assume !(1 == ~T5_E~0); {2029#false} is VALID [2022-02-21 04:23:09,785 INFO L290 TraceCheckUtils]: 138: Hoare triple {2029#false} assume !(1 == ~T6_E~0); {2029#false} is VALID [2022-02-21 04:23:09,789 INFO L290 TraceCheckUtils]: 139: Hoare triple {2029#false} assume !(1 == ~T7_E~0); {2029#false} is VALID [2022-02-21 04:23:09,789 INFO L290 TraceCheckUtils]: 140: Hoare triple {2029#false} assume !(1 == ~T8_E~0); {2029#false} is VALID [2022-02-21 04:23:09,789 INFO L290 TraceCheckUtils]: 141: Hoare triple {2029#false} assume !(1 == ~T9_E~0); {2029#false} is VALID [2022-02-21 04:23:09,789 INFO L290 TraceCheckUtils]: 142: Hoare triple {2029#false} assume !(1 == ~T10_E~0); {2029#false} is VALID [2022-02-21 04:23:09,789 INFO L290 TraceCheckUtils]: 143: Hoare triple {2029#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,790 INFO L290 TraceCheckUtils]: 144: Hoare triple {2029#false} assume !(1 == ~T12_E~0); {2029#false} is VALID [2022-02-21 04:23:09,790 INFO L290 TraceCheckUtils]: 145: Hoare triple {2029#false} assume !(1 == ~T13_E~0); {2029#false} is VALID [2022-02-21 04:23:09,790 INFO L290 TraceCheckUtils]: 146: Hoare triple {2029#false} assume !(1 == ~E_M~0); {2029#false} is VALID [2022-02-21 04:23:09,790 INFO L290 TraceCheckUtils]: 147: Hoare triple {2029#false} assume !(1 == ~E_1~0); {2029#false} is VALID [2022-02-21 04:23:09,790 INFO L290 TraceCheckUtils]: 148: Hoare triple {2029#false} assume !(1 == ~E_2~0); {2029#false} is VALID [2022-02-21 04:23:09,790 INFO L290 TraceCheckUtils]: 149: Hoare triple {2029#false} assume !(1 == ~E_3~0); {2029#false} is VALID [2022-02-21 04:23:09,791 INFO L290 TraceCheckUtils]: 150: Hoare triple {2029#false} assume !(1 == ~E_4~0); {2029#false} is VALID [2022-02-21 04:23:09,791 INFO L290 TraceCheckUtils]: 151: Hoare triple {2029#false} assume 1 == ~E_5~0;~E_5~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,791 INFO L290 TraceCheckUtils]: 152: Hoare triple {2029#false} assume !(1 == ~E_6~0); {2029#false} is VALID [2022-02-21 04:23:09,791 INFO L290 TraceCheckUtils]: 153: Hoare triple {2029#false} assume !(1 == ~E_7~0); {2029#false} is VALID [2022-02-21 04:23:09,791 INFO L290 TraceCheckUtils]: 154: Hoare triple {2029#false} assume !(1 == ~E_8~0); {2029#false} is VALID [2022-02-21 04:23:09,792 INFO L290 TraceCheckUtils]: 155: Hoare triple {2029#false} assume !(1 == ~E_9~0); {2029#false} is VALID [2022-02-21 04:23:09,792 INFO L290 TraceCheckUtils]: 156: Hoare triple {2029#false} assume !(1 == ~E_10~0); {2029#false} is VALID [2022-02-21 04:23:09,792 INFO L290 TraceCheckUtils]: 157: Hoare triple {2029#false} assume !(1 == ~E_11~0); {2029#false} is VALID [2022-02-21 04:23:09,792 INFO L290 TraceCheckUtils]: 158: Hoare triple {2029#false} assume !(1 == ~E_12~0); {2029#false} is VALID [2022-02-21 04:23:09,792 INFO L290 TraceCheckUtils]: 159: Hoare triple {2029#false} assume 1 == ~E_13~0;~E_13~0 := 2; {2029#false} is VALID [2022-02-21 04:23:09,792 INFO L290 TraceCheckUtils]: 160: Hoare triple {2029#false} assume { :end_inline_reset_delta_events } true; {2029#false} is VALID [2022-02-21 04:23:09,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,795 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,795 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341359912] [2022-02-21 04:23:09,795 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341359912] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,796 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,796 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:09,797 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1417099847] [2022-02-21 04:23:09,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,801 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:09,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,804 INFO L85 PathProgramCache]: Analyzing trace with hash 1066176643, now seen corresponding path program 1 times [2022-02-21 04:23:09,805 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,805 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345323489] [2022-02-21 04:23:09,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,841 INFO L290 TraceCheckUtils]: 0: Hoare triple {2031#true} assume !false; {2031#true} is VALID [2022-02-21 04:23:09,842 INFO L290 TraceCheckUtils]: 1: Hoare triple {2031#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {2031#true} is VALID [2022-02-21 04:23:09,842 INFO L290 TraceCheckUtils]: 2: Hoare triple {2031#true} assume false; {2032#false} is VALID [2022-02-21 04:23:09,842 INFO L290 TraceCheckUtils]: 3: Hoare triple {2032#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {2032#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 4: Hoare triple {2032#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {2032#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 5: Hoare triple {2032#false} assume 0 == ~M_E~0;~M_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 6: Hoare triple {2032#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 7: Hoare triple {2032#false} assume !(0 == ~T2_E~0); {2032#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 8: Hoare triple {2032#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 9: Hoare triple {2032#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 10: Hoare triple {2032#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 11: Hoare triple {2032#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 12: Hoare triple {2032#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 13: Hoare triple {2032#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 14: Hoare triple {2032#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 15: Hoare triple {2032#false} assume !(0 == ~T10_E~0); {2032#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 16: Hoare triple {2032#false} assume 0 == ~T11_E~0;~T11_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 17: Hoare triple {2032#false} assume 0 == ~T12_E~0;~T12_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 18: Hoare triple {2032#false} assume 0 == ~T13_E~0;~T13_E~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 19: Hoare triple {2032#false} assume 0 == ~E_M~0;~E_M~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 20: Hoare triple {2032#false} assume 0 == ~E_1~0;~E_1~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 21: Hoare triple {2032#false} assume 0 == ~E_2~0;~E_2~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 22: Hoare triple {2032#false} assume 0 == ~E_3~0;~E_3~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 23: Hoare triple {2032#false} assume !(0 == ~E_4~0); {2032#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 24: Hoare triple {2032#false} assume 0 == ~E_5~0;~E_5~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 25: Hoare triple {2032#false} assume 0 == ~E_6~0;~E_6~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 26: Hoare triple {2032#false} assume 0 == ~E_7~0;~E_7~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 27: Hoare triple {2032#false} assume 0 == ~E_8~0;~E_8~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 28: Hoare triple {2032#false} assume 0 == ~E_9~0;~E_9~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 29: Hoare triple {2032#false} assume 0 == ~E_10~0;~E_10~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 30: Hoare triple {2032#false} assume 0 == ~E_11~0;~E_11~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 31: Hoare triple {2032#false} assume !(0 == ~E_12~0); {2032#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 32: Hoare triple {2032#false} assume 0 == ~E_13~0;~E_13~0 := 1; {2032#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 33: Hoare triple {2032#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2032#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 34: Hoare triple {2032#false} assume 1 == ~m_pc~0; {2032#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 35: Hoare triple {2032#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {2032#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 36: Hoare triple {2032#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2032#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 37: Hoare triple {2032#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {2032#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 38: Hoare triple {2032#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 39: Hoare triple {2032#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2032#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 40: Hoare triple {2032#false} assume !(1 == ~t1_pc~0); {2032#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 41: Hoare triple {2032#false} is_transmit1_triggered_~__retres1~1#1 := 0; {2032#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 42: Hoare triple {2032#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2032#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 43: Hoare triple {2032#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {2032#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 44: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 45: Hoare triple {2032#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2032#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 46: Hoare triple {2032#false} assume 1 == ~t2_pc~0; {2032#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 47: Hoare triple {2032#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2032#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 48: Hoare triple {2032#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2032#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 49: Hoare triple {2032#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {2032#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 50: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 51: Hoare triple {2032#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2032#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 52: Hoare triple {2032#false} assume !(1 == ~t3_pc~0); {2032#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 53: Hoare triple {2032#false} is_transmit3_triggered_~__retres1~3#1 := 0; {2032#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 54: Hoare triple {2032#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2032#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 55: Hoare triple {2032#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {2032#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 56: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 57: Hoare triple {2032#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2032#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 58: Hoare triple {2032#false} assume 1 == ~t4_pc~0; {2032#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 59: Hoare triple {2032#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {2032#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 60: Hoare triple {2032#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2032#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 61: Hoare triple {2032#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {2032#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 62: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 63: Hoare triple {2032#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {2032#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 64: Hoare triple {2032#false} assume !(1 == ~t5_pc~0); {2032#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 65: Hoare triple {2032#false} is_transmit5_triggered_~__retres1~5#1 := 0; {2032#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 66: Hoare triple {2032#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {2032#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 67: Hoare triple {2032#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {2032#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 68: Hoare triple {2032#false} assume !(0 != activate_threads_~tmp___4~0#1); {2032#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 69: Hoare triple {2032#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {2032#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 70: Hoare triple {2032#false} assume !(1 == ~t6_pc~0); {2032#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 71: Hoare triple {2032#false} is_transmit6_triggered_~__retres1~6#1 := 0; {2032#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 72: Hoare triple {2032#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {2032#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 73: Hoare triple {2032#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {2032#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 74: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 75: Hoare triple {2032#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {2032#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 76: Hoare triple {2032#false} assume !(1 == ~t7_pc~0); {2032#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 77: Hoare triple {2032#false} is_transmit7_triggered_~__retres1~7#1 := 0; {2032#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 78: Hoare triple {2032#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {2032#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 79: Hoare triple {2032#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {2032#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 80: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 81: Hoare triple {2032#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {2032#false} is VALID [2022-02-21 04:23:09,856 INFO L290 TraceCheckUtils]: 82: Hoare triple {2032#false} assume !(1 == ~t8_pc~0); {2032#false} is VALID [2022-02-21 04:23:09,856 INFO L290 TraceCheckUtils]: 83: Hoare triple {2032#false} is_transmit8_triggered_~__retres1~8#1 := 0; {2032#false} is VALID [2022-02-21 04:23:09,856 INFO L290 TraceCheckUtils]: 84: Hoare triple {2032#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {2032#false} is VALID [2022-02-21 04:23:09,856 INFO L290 TraceCheckUtils]: 85: Hoare triple {2032#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {2032#false} is VALID [2022-02-21 04:23:09,856 INFO L290 TraceCheckUtils]: 86: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 87: Hoare triple {2032#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {2032#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 88: Hoare triple {2032#false} assume !(1 == ~t9_pc~0); {2032#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 89: Hoare triple {2032#false} is_transmit9_triggered_~__retres1~9#1 := 0; {2032#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 90: Hoare triple {2032#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {2032#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 91: Hoare triple {2032#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {2032#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 92: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 93: Hoare triple {2032#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {2032#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 94: Hoare triple {2032#false} assume 1 == ~t10_pc~0; {2032#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 95: Hoare triple {2032#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {2032#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 96: Hoare triple {2032#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {2032#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 97: Hoare triple {2032#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {2032#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 98: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 99: Hoare triple {2032#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {2032#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 100: Hoare triple {2032#false} assume 1 == ~t11_pc~0; {2032#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 101: Hoare triple {2032#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {2032#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 102: Hoare triple {2032#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {2032#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 103: Hoare triple {2032#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {2032#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 104: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 105: Hoare triple {2032#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {2032#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 106: Hoare triple {2032#false} assume 1 == ~t12_pc~0; {2032#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 107: Hoare triple {2032#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {2032#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 108: Hoare triple {2032#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {2032#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 109: Hoare triple {2032#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {2032#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 110: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 111: Hoare triple {2032#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {2032#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 112: Hoare triple {2032#false} assume !(1 == ~t13_pc~0); {2032#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 113: Hoare triple {2032#false} is_transmit13_triggered_~__retres1~13#1 := 0; {2032#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 114: Hoare triple {2032#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {2032#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 115: Hoare triple {2032#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {2032#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 116: Hoare triple {2032#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {2032#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 117: Hoare triple {2032#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2032#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 118: Hoare triple {2032#false} assume !(1 == ~M_E~0); {2032#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 119: Hoare triple {2032#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 120: Hoare triple {2032#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 121: Hoare triple {2032#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,863 INFO L290 TraceCheckUtils]: 122: Hoare triple {2032#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,863 INFO L290 TraceCheckUtils]: 123: Hoare triple {2032#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,863 INFO L290 TraceCheckUtils]: 124: Hoare triple {2032#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,863 INFO L290 TraceCheckUtils]: 125: Hoare triple {2032#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,864 INFO L290 TraceCheckUtils]: 126: Hoare triple {2032#false} assume !(1 == ~T8_E~0); {2032#false} is VALID [2022-02-21 04:23:09,864 INFO L290 TraceCheckUtils]: 127: Hoare triple {2032#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,864 INFO L290 TraceCheckUtils]: 128: Hoare triple {2032#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,864 INFO L290 TraceCheckUtils]: 129: Hoare triple {2032#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,864 INFO L290 TraceCheckUtils]: 130: Hoare triple {2032#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 131: Hoare triple {2032#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 132: Hoare triple {2032#false} assume 1 == ~E_M~0;~E_M~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 133: Hoare triple {2032#false} assume 1 == ~E_1~0;~E_1~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 134: Hoare triple {2032#false} assume !(1 == ~E_2~0); {2032#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 135: Hoare triple {2032#false} assume 1 == ~E_3~0;~E_3~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 136: Hoare triple {2032#false} assume 1 == ~E_4~0;~E_4~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 137: Hoare triple {2032#false} assume 1 == ~E_5~0;~E_5~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 138: Hoare triple {2032#false} assume 1 == ~E_6~0;~E_6~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 139: Hoare triple {2032#false} assume 1 == ~E_7~0;~E_7~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 140: Hoare triple {2032#false} assume 1 == ~E_8~0;~E_8~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 141: Hoare triple {2032#false} assume 1 == ~E_9~0;~E_9~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 142: Hoare triple {2032#false} assume !(1 == ~E_10~0); {2032#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 143: Hoare triple {2032#false} assume 1 == ~E_11~0;~E_11~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 144: Hoare triple {2032#false} assume 1 == ~E_12~0;~E_12~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 145: Hoare triple {2032#false} assume 1 == ~E_13~0;~E_13~0 := 2; {2032#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 146: Hoare triple {2032#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {2032#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 147: Hoare triple {2032#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {2032#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 148: Hoare triple {2032#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {2032#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 149: Hoare triple {2032#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {2032#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 150: Hoare triple {2032#false} assume !(0 == start_simulation_~tmp~3#1); {2032#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 151: Hoare triple {2032#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {2032#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 152: Hoare triple {2032#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {2032#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 153: Hoare triple {2032#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {2032#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 154: Hoare triple {2032#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {2032#false} is VALID [2022-02-21 04:23:09,869 INFO L290 TraceCheckUtils]: 155: Hoare triple {2032#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {2032#false} is VALID [2022-02-21 04:23:09,869 INFO L290 TraceCheckUtils]: 156: Hoare triple {2032#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {2032#false} is VALID [2022-02-21 04:23:09,869 INFO L290 TraceCheckUtils]: 157: Hoare triple {2032#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {2032#false} is VALID [2022-02-21 04:23:09,869 INFO L290 TraceCheckUtils]: 158: Hoare triple {2032#false} assume !(0 != start_simulation_~tmp___0~1#1); {2032#false} is VALID [2022-02-21 04:23:09,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,870 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,870 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345323489] [2022-02-21 04:23:09,870 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345323489] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,871 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,871 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:09,871 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463348881] [2022-02-21 04:23:09,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,872 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:09,873 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:09,890 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-21 04:23:09,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-21 04:23:09,897 INFO L87 Difference]: Start difference. First operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,928 INFO L93 Difference]: Finished difference Result 2023 states and 2992 transitions. [2022-02-21 04:23:10,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-21 04:23:10,930 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,035 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:11,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2992 transitions. [2022-02-21 04:23:11,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:11,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2018 states and 2987 transitions. [2022-02-21 04:23:11,279 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:11,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:11,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2987 transitions. [2022-02-21 04:23:11,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:11,285 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2022-02-21 04:23:11,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2987 transitions. [2022-02-21 04:23:11,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:11,351 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:11,356 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2987 transitions. Second operand has 2018 states, 2018 states have (on average 1.4801783944499505) internal successors, (2987), 2017 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,359 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2987 transitions. Second operand has 2018 states, 2018 states have (on average 1.4801783944499505) internal successors, (2987), 2017 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,362 INFO L87 Difference]: Start difference. First operand 2018 states and 2987 transitions. Second operand has 2018 states, 2018 states have (on average 1.4801783944499505) internal successors, (2987), 2017 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,459 INFO L93 Difference]: Finished difference Result 2018 states and 2987 transitions. [2022-02-21 04:23:11,459 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2987 transitions. [2022-02-21 04:23:11,465 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:11,465 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:11,468 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.4801783944499505) internal successors, (2987), 2017 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2987 transitions. [2022-02-21 04:23:11,471 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.4801783944499505) internal successors, (2987), 2017 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2987 transitions. [2022-02-21 04:23:11,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,566 INFO L93 Difference]: Finished difference Result 2018 states and 2987 transitions. [2022-02-21 04:23:11,566 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2987 transitions. [2022-02-21 04:23:11,568 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:11,569 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:11,569 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:11,569 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:11,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4801783944499505) internal successors, (2987), 2017 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2987 transitions. [2022-02-21 04:23:11,673 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2022-02-21 04:23:11,673 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2022-02-21 04:23:11,673 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:23:11,673 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2987 transitions. [2022-02-21 04:23:11,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:11,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:11,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:11,682 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,682 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,682 INFO L791 eck$LassoCheckResult]: Stem: 4971#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 6008#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5463#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5464#L902 assume !(1 == ~m_i~0);~m_st~0 := 2; 4953#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4954#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5020#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5021#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5459#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5460#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4986#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4805#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4806#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5250#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5251#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5126#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5127#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4776#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4777#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 6000#L1279-2 assume !(0 == ~T1_E~0); 4399#L1284-1 assume !(0 == ~T2_E~0); 4400#L1289-1 assume !(0 == ~T3_E~0); 5123#L1294-1 assume !(0 == ~T4_E~0); 5124#L1299-1 assume !(0 == ~T5_E~0); 5135#L1304-1 assume !(0 == ~T6_E~0); 6066#L1309-1 assume !(0 == ~T7_E~0); 6067#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4329#L1319-1 assume !(0 == ~T9_E~0); 4330#L1324-1 assume !(0 == ~T10_E~0); 4502#L1329-1 assume !(0 == ~T11_E~0); 4503#L1334-1 assume !(0 == ~T12_E~0); 5907#L1339-1 assume !(0 == ~T13_E~0); 5988#L1344-1 assume !(0 == ~E_M~0); 5989#L1349-1 assume !(0 == ~E_1~0); 5310#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5311#L1359-1 assume !(0 == ~E_3~0); 5740#L1364-1 assume !(0 == ~E_4~0); 4631#L1369-1 assume !(0 == ~E_5~0); 4632#L1374-1 assume !(0 == ~E_6~0); 5315#L1379-1 assume !(0 == ~E_7~0); 5316#L1384-1 assume !(0 == ~E_8~0); 5393#L1389-1 assume !(0 == ~E_9~0); 5926#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5927#L1399-1 assume !(0 == ~E_11~0); 6030#L1404-1 assume !(0 == ~E_12~0); 4724#L1409-1 assume !(0 == ~E_13~0); 4725#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6022#L628 assume !(1 == ~m_pc~0); 4628#L628-2 is_master_triggered_~__retres1~0#1 := 0; 4627#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5391#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5392#L1591 assume !(0 != activate_threads_~tmp~1#1); 6035#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5179#L647 assume 1 == ~t1_pc~0; 4548#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4549#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4820#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4821#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 5975#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5976#L666 assume 1 == ~t2_pc~0; 4396#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4397#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4563#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5992#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 5511#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5512#L685 assume !(1 == ~t3_pc~0); 5617#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5616#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5239#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5240#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5361#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4847#L704 assume 1 == ~t4_pc~0; 4848#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5372#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5373#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6013#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 5232#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5233#L723 assume !(1 == ~t5_pc~0); 5355#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5591#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5735#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5490#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 5491#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4613#L742 assume 1 == ~t6_pc~0; 4614#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4762#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4763#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4298#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 4299#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4690#L761 assume !(1 == ~t7_pc~0); 4691#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4559#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4560#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5362#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 5363#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4323#L780 assume 1 == ~t8_pc~0; 4324#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4599#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4600#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5323#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 5324#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5443#L799 assume 1 == ~t9_pc~0; 5555#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4326#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4327#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5455#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 5662#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5473#L818 assume !(1 == ~t10_pc~0); 4107#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4108#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5548#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5477#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5478#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5518#L837 assume 1 == ~t11_pc~0; 5519#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5353#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5756#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5436#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 5437#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5188#L856 assume !(1 == ~t12_pc~0); 5189#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5842#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5843#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5823#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 5824#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 6003#L875 assume 1 == ~t13_pc~0; 5133#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4765#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4766#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4705#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 4706#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5545#L1427 assume !(1 == ~M_E~0); 5529#L1427-2 assume !(1 == ~T1_E~0); 4677#L1432-1 assume !(1 == ~T2_E~0); 4678#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5746#L1442-1 assume !(1 == ~T4_E~0); 5747#L1447-1 assume !(1 == ~T5_E~0); 5602#L1452-1 assume !(1 == ~T6_E~0); 4242#L1457-1 assume !(1 == ~T7_E~0); 4243#L1462-1 assume !(1 == ~T8_E~0); 5773#L1467-1 assume !(1 == ~T9_E~0); 5791#L1472-1 assume !(1 == ~T10_E~0); 5792#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5543#L1482-1 assume !(1 == ~T12_E~0); 5544#L1487-1 assume !(1 == ~T13_E~0); 4573#L1492-1 assume !(1 == ~E_M~0); 4574#L1497-1 assume !(1 == ~E_1~0); 4935#L1502-1 assume !(1 == ~E_2~0); 4936#L1507-1 assume !(1 == ~E_3~0); 4451#L1512-1 assume !(1 == ~E_4~0); 4452#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5862#L1522-1 assume !(1 == ~E_6~0); 5176#L1527-1 assume !(1 == ~E_7~0); 5177#L1532-1 assume !(1 == ~E_8~0); 6050#L1537-1 assume !(1 == ~E_9~0); 5379#L1542-1 assume !(1 == ~E_10~0); 5210#L1547-1 assume !(1 == ~E_11~0); 5211#L1552-1 assume !(1 == ~E_12~0); 4146#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 4147#L1562-1 assume { :end_inline_reset_delta_events } true; 4753#L1928-2 [2022-02-21 04:23:11,683 INFO L793 eck$LassoCheckResult]: Loop: 4753#L1928-2 assume !false; 5244#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4407#L1254 assume !false; 4994#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4481#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4482#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4679#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5850#L1067 assume !(0 != eval_~tmp~0#1); 4920#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4497#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4498#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4957#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4939#L1284-3 assume !(0 == ~T2_E~0); 4940#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4918#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4919#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5306#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5307#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4816#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4817#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5813#L1324-3 assume !(0 == ~T10_E~0); 4448#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4449#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5216#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5217#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5515#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4797#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4798#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5526#L1364-3 assume !(0 == ~E_4~0); 6048#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5944#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4577#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4578#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4795#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4796#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5086#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5954#L1404-3 assume !(0 == ~E_12~0); 5918#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5919#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5405#L628-45 assume 1 == ~m_pc~0; 5083#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5085#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4442#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4443#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4831#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5554#L647-45 assume 1 == ~t1_pc~0; 4393#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4394#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5322#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4507#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4508#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4719#L666-45 assume !(1 == ~t2_pc~0); 4720#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5201#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5763#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5678#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5672#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4257#L685-45 assume 1 == ~t3_pc~0; 4258#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5317#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5991#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5860#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5861#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6001#L704-45 assume 1 == ~t4_pc~0; 5880#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4124#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4983#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5326#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6073#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5438#L723-45 assume 1 == ~t5_pc~0; 5440#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5928#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5030#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4807#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 4808#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5832#L742-45 assume 1 == ~t6_pc~0; 5833#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5055#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5524#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5560#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5561#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5649#L761-45 assume !(1 == ~t7_pc~0); 5650#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 5048#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5049#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4455#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4456#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5922#L780-45 assume 1 == ~t8_pc~0; 4833#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4467#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4468#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6049#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4437#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4438#L799-45 assume !(1 == ~t9_pc~0); 4658#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 4659#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5974#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5603#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5604#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4375#L818-45 assume 1 == ~t10_pc~0; 4376#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4494#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5577#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4981#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4982#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5697#L837-45 assume !(1 == ~t11_pc~0); 4912#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4913#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5050#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5715#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4513#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4514#L856-45 assume !(1 == ~t12_pc~0); 4515#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 4516#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4457#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4458#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5320#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5321#L875-45 assume 1 == ~t13_pc~0; 5291#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5292#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5354#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5966#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5967#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5906#L1427-3 assume !(1 == ~M_E~0); 5117#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5118#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5656#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5308#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5309#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4165#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4166#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5848#L1462-3 assume !(1 == ~T8_E~0); 5849#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5712#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5713#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4416#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4417#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4558#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4731#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4732#L1502-3 assume !(1 == ~E_2~0); 5680#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5811#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4769#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4461#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4462#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4426#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4427#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5527#L1542-3 assume !(1 == ~E_10~0); 5665#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5294#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5295#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4637#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4638#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4057#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4822#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4823#L1947 assume !(0 == start_simulation_~tmp~3#1); 5428#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5633#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4694#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 6026#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 5950#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5780#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5539#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5540#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 4753#L1928-2 [2022-02-21 04:23:11,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,684 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2022-02-21 04:23:11,684 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,684 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187445402] [2022-02-21 04:23:11,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,725 INFO L290 TraceCheckUtils]: 0: Hoare triple {10113#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {10113#true} is VALID [2022-02-21 04:23:11,728 INFO L290 TraceCheckUtils]: 1: Hoare triple {10113#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {10115#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:11,728 INFO L290 TraceCheckUtils]: 2: Hoare triple {10115#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10115#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:11,728 INFO L290 TraceCheckUtils]: 3: Hoare triple {10115#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10115#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:11,729 INFO L290 TraceCheckUtils]: 4: Hoare triple {10115#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,729 INFO L290 TraceCheckUtils]: 5: Hoare triple {10114#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10114#false} is VALID [2022-02-21 04:23:11,729 INFO L290 TraceCheckUtils]: 6: Hoare triple {10114#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,729 INFO L290 TraceCheckUtils]: 7: Hoare triple {10114#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,729 INFO L290 TraceCheckUtils]: 8: Hoare triple {10114#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,730 INFO L290 TraceCheckUtils]: 9: Hoare triple {10114#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,730 INFO L290 TraceCheckUtils]: 10: Hoare triple {10114#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,730 INFO L290 TraceCheckUtils]: 11: Hoare triple {10114#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,730 INFO L290 TraceCheckUtils]: 12: Hoare triple {10114#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,730 INFO L290 TraceCheckUtils]: 13: Hoare triple {10114#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {10114#false} is VALID [2022-02-21 04:23:11,730 INFO L290 TraceCheckUtils]: 14: Hoare triple {10114#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,730 INFO L290 TraceCheckUtils]: 15: Hoare triple {10114#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,731 INFO L290 TraceCheckUtils]: 16: Hoare triple {10114#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,731 INFO L290 TraceCheckUtils]: 17: Hoare triple {10114#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,731 INFO L290 TraceCheckUtils]: 18: Hoare triple {10114#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10114#false} is VALID [2022-02-21 04:23:11,731 INFO L290 TraceCheckUtils]: 19: Hoare triple {10114#false} assume 0 == ~M_E~0;~M_E~0 := 1; {10114#false} is VALID [2022-02-21 04:23:11,731 INFO L290 TraceCheckUtils]: 20: Hoare triple {10114#false} assume !(0 == ~T1_E~0); {10114#false} is VALID [2022-02-21 04:23:11,731 INFO L290 TraceCheckUtils]: 21: Hoare triple {10114#false} assume !(0 == ~T2_E~0); {10114#false} is VALID [2022-02-21 04:23:11,732 INFO L290 TraceCheckUtils]: 22: Hoare triple {10114#false} assume !(0 == ~T3_E~0); {10114#false} is VALID [2022-02-21 04:23:11,732 INFO L290 TraceCheckUtils]: 23: Hoare triple {10114#false} assume !(0 == ~T4_E~0); {10114#false} is VALID [2022-02-21 04:23:11,732 INFO L290 TraceCheckUtils]: 24: Hoare triple {10114#false} assume !(0 == ~T5_E~0); {10114#false} is VALID [2022-02-21 04:23:11,732 INFO L290 TraceCheckUtils]: 25: Hoare triple {10114#false} assume !(0 == ~T6_E~0); {10114#false} is VALID [2022-02-21 04:23:11,732 INFO L290 TraceCheckUtils]: 26: Hoare triple {10114#false} assume !(0 == ~T7_E~0); {10114#false} is VALID [2022-02-21 04:23:11,732 INFO L290 TraceCheckUtils]: 27: Hoare triple {10114#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {10114#false} is VALID [2022-02-21 04:23:11,732 INFO L290 TraceCheckUtils]: 28: Hoare triple {10114#false} assume !(0 == ~T9_E~0); {10114#false} is VALID [2022-02-21 04:23:11,733 INFO L290 TraceCheckUtils]: 29: Hoare triple {10114#false} assume !(0 == ~T10_E~0); {10114#false} is VALID [2022-02-21 04:23:11,733 INFO L290 TraceCheckUtils]: 30: Hoare triple {10114#false} assume !(0 == ~T11_E~0); {10114#false} is VALID [2022-02-21 04:23:11,733 INFO L290 TraceCheckUtils]: 31: Hoare triple {10114#false} assume !(0 == ~T12_E~0); {10114#false} is VALID [2022-02-21 04:23:11,733 INFO L290 TraceCheckUtils]: 32: Hoare triple {10114#false} assume !(0 == ~T13_E~0); {10114#false} is VALID [2022-02-21 04:23:11,733 INFO L290 TraceCheckUtils]: 33: Hoare triple {10114#false} assume !(0 == ~E_M~0); {10114#false} is VALID [2022-02-21 04:23:11,733 INFO L290 TraceCheckUtils]: 34: Hoare triple {10114#false} assume !(0 == ~E_1~0); {10114#false} is VALID [2022-02-21 04:23:11,734 INFO L290 TraceCheckUtils]: 35: Hoare triple {10114#false} assume 0 == ~E_2~0;~E_2~0 := 1; {10114#false} is VALID [2022-02-21 04:23:11,734 INFO L290 TraceCheckUtils]: 36: Hoare triple {10114#false} assume !(0 == ~E_3~0); {10114#false} is VALID [2022-02-21 04:23:11,734 INFO L290 TraceCheckUtils]: 37: Hoare triple {10114#false} assume !(0 == ~E_4~0); {10114#false} is VALID [2022-02-21 04:23:11,734 INFO L290 TraceCheckUtils]: 38: Hoare triple {10114#false} assume !(0 == ~E_5~0); {10114#false} is VALID [2022-02-21 04:23:11,734 INFO L290 TraceCheckUtils]: 39: Hoare triple {10114#false} assume !(0 == ~E_6~0); {10114#false} is VALID [2022-02-21 04:23:11,734 INFO L290 TraceCheckUtils]: 40: Hoare triple {10114#false} assume !(0 == ~E_7~0); {10114#false} is VALID [2022-02-21 04:23:11,734 INFO L290 TraceCheckUtils]: 41: Hoare triple {10114#false} assume !(0 == ~E_8~0); {10114#false} is VALID [2022-02-21 04:23:11,735 INFO L290 TraceCheckUtils]: 42: Hoare triple {10114#false} assume !(0 == ~E_9~0); {10114#false} is VALID [2022-02-21 04:23:11,735 INFO L290 TraceCheckUtils]: 43: Hoare triple {10114#false} assume 0 == ~E_10~0;~E_10~0 := 1; {10114#false} is VALID [2022-02-21 04:23:11,735 INFO L290 TraceCheckUtils]: 44: Hoare triple {10114#false} assume !(0 == ~E_11~0); {10114#false} is VALID [2022-02-21 04:23:11,735 INFO L290 TraceCheckUtils]: 45: Hoare triple {10114#false} assume !(0 == ~E_12~0); {10114#false} is VALID [2022-02-21 04:23:11,735 INFO L290 TraceCheckUtils]: 46: Hoare triple {10114#false} assume !(0 == ~E_13~0); {10114#false} is VALID [2022-02-21 04:23:11,735 INFO L290 TraceCheckUtils]: 47: Hoare triple {10114#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10114#false} is VALID [2022-02-21 04:23:11,735 INFO L290 TraceCheckUtils]: 48: Hoare triple {10114#false} assume !(1 == ~m_pc~0); {10114#false} is VALID [2022-02-21 04:23:11,736 INFO L290 TraceCheckUtils]: 49: Hoare triple {10114#false} is_master_triggered_~__retres1~0#1 := 0; {10114#false} is VALID [2022-02-21 04:23:11,736 INFO L290 TraceCheckUtils]: 50: Hoare triple {10114#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10114#false} is VALID [2022-02-21 04:23:11,736 INFO L290 TraceCheckUtils]: 51: Hoare triple {10114#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10114#false} is VALID [2022-02-21 04:23:11,737 INFO L290 TraceCheckUtils]: 52: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp~1#1); {10114#false} is VALID [2022-02-21 04:23:11,737 INFO L290 TraceCheckUtils]: 53: Hoare triple {10114#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10114#false} is VALID [2022-02-21 04:23:11,739 INFO L290 TraceCheckUtils]: 54: Hoare triple {10114#false} assume 1 == ~t1_pc~0; {10114#false} is VALID [2022-02-21 04:23:11,743 INFO L290 TraceCheckUtils]: 55: Hoare triple {10114#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10114#false} is VALID [2022-02-21 04:23:11,743 INFO L290 TraceCheckUtils]: 56: Hoare triple {10114#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10114#false} is VALID [2022-02-21 04:23:11,743 INFO L290 TraceCheckUtils]: 57: Hoare triple {10114#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10114#false} is VALID [2022-02-21 04:23:11,743 INFO L290 TraceCheckUtils]: 58: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___0~0#1); {10114#false} is VALID [2022-02-21 04:23:11,743 INFO L290 TraceCheckUtils]: 59: Hoare triple {10114#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10114#false} is VALID [2022-02-21 04:23:11,744 INFO L290 TraceCheckUtils]: 60: Hoare triple {10114#false} assume 1 == ~t2_pc~0; {10114#false} is VALID [2022-02-21 04:23:11,744 INFO L290 TraceCheckUtils]: 61: Hoare triple {10114#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10114#false} is VALID [2022-02-21 04:23:11,745 INFO L290 TraceCheckUtils]: 62: Hoare triple {10114#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10114#false} is VALID [2022-02-21 04:23:11,745 INFO L290 TraceCheckUtils]: 63: Hoare triple {10114#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10114#false} is VALID [2022-02-21 04:23:11,746 INFO L290 TraceCheckUtils]: 64: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___1~0#1); {10114#false} is VALID [2022-02-21 04:23:11,746 INFO L290 TraceCheckUtils]: 65: Hoare triple {10114#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10114#false} is VALID [2022-02-21 04:23:11,746 INFO L290 TraceCheckUtils]: 66: Hoare triple {10114#false} assume !(1 == ~t3_pc~0); {10114#false} is VALID [2022-02-21 04:23:11,746 INFO L290 TraceCheckUtils]: 67: Hoare triple {10114#false} is_transmit3_triggered_~__retres1~3#1 := 0; {10114#false} is VALID [2022-02-21 04:23:11,746 INFO L290 TraceCheckUtils]: 68: Hoare triple {10114#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10114#false} is VALID [2022-02-21 04:23:11,746 INFO L290 TraceCheckUtils]: 69: Hoare triple {10114#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {10114#false} is VALID [2022-02-21 04:23:11,746 INFO L290 TraceCheckUtils]: 70: Hoare triple {10114#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10114#false} is VALID [2022-02-21 04:23:11,746 INFO L290 TraceCheckUtils]: 71: Hoare triple {10114#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10114#false} is VALID [2022-02-21 04:23:11,747 INFO L290 TraceCheckUtils]: 72: Hoare triple {10114#false} assume 1 == ~t4_pc~0; {10114#false} is VALID [2022-02-21 04:23:11,747 INFO L290 TraceCheckUtils]: 73: Hoare triple {10114#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10114#false} is VALID [2022-02-21 04:23:11,747 INFO L290 TraceCheckUtils]: 74: Hoare triple {10114#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10114#false} is VALID [2022-02-21 04:23:11,747 INFO L290 TraceCheckUtils]: 75: Hoare triple {10114#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {10114#false} is VALID [2022-02-21 04:23:11,752 INFO L290 TraceCheckUtils]: 76: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___3~0#1); {10114#false} is VALID [2022-02-21 04:23:11,752 INFO L290 TraceCheckUtils]: 77: Hoare triple {10114#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10114#false} is VALID [2022-02-21 04:23:11,752 INFO L290 TraceCheckUtils]: 78: Hoare triple {10114#false} assume !(1 == ~t5_pc~0); {10114#false} is VALID [2022-02-21 04:23:11,752 INFO L290 TraceCheckUtils]: 79: Hoare triple {10114#false} is_transmit5_triggered_~__retres1~5#1 := 0; {10114#false} is VALID [2022-02-21 04:23:11,752 INFO L290 TraceCheckUtils]: 80: Hoare triple {10114#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10114#false} is VALID [2022-02-21 04:23:11,752 INFO L290 TraceCheckUtils]: 81: Hoare triple {10114#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {10114#false} is VALID [2022-02-21 04:23:11,752 INFO L290 TraceCheckUtils]: 82: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___4~0#1); {10114#false} is VALID [2022-02-21 04:23:11,752 INFO L290 TraceCheckUtils]: 83: Hoare triple {10114#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10114#false} is VALID [2022-02-21 04:23:11,753 INFO L290 TraceCheckUtils]: 84: Hoare triple {10114#false} assume 1 == ~t6_pc~0; {10114#false} is VALID [2022-02-21 04:23:11,753 INFO L290 TraceCheckUtils]: 85: Hoare triple {10114#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10114#false} is VALID [2022-02-21 04:23:11,753 INFO L290 TraceCheckUtils]: 86: Hoare triple {10114#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10114#false} is VALID [2022-02-21 04:23:11,753 INFO L290 TraceCheckUtils]: 87: Hoare triple {10114#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {10114#false} is VALID [2022-02-21 04:23:11,753 INFO L290 TraceCheckUtils]: 88: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___5~0#1); {10114#false} is VALID [2022-02-21 04:23:11,753 INFO L290 TraceCheckUtils]: 89: Hoare triple {10114#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10114#false} is VALID [2022-02-21 04:23:11,753 INFO L290 TraceCheckUtils]: 90: Hoare triple {10114#false} assume !(1 == ~t7_pc~0); {10114#false} is VALID [2022-02-21 04:23:11,753 INFO L290 TraceCheckUtils]: 91: Hoare triple {10114#false} is_transmit7_triggered_~__retres1~7#1 := 0; {10114#false} is VALID [2022-02-21 04:23:11,753 INFO L290 TraceCheckUtils]: 92: Hoare triple {10114#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10114#false} is VALID [2022-02-21 04:23:11,754 INFO L290 TraceCheckUtils]: 93: Hoare triple {10114#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {10114#false} is VALID [2022-02-21 04:23:11,754 INFO L290 TraceCheckUtils]: 94: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___6~0#1); {10114#false} is VALID [2022-02-21 04:23:11,754 INFO L290 TraceCheckUtils]: 95: Hoare triple {10114#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {10114#false} is VALID [2022-02-21 04:23:11,754 INFO L290 TraceCheckUtils]: 96: Hoare triple {10114#false} assume 1 == ~t8_pc~0; {10114#false} is VALID [2022-02-21 04:23:11,754 INFO L290 TraceCheckUtils]: 97: Hoare triple {10114#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {10114#false} is VALID [2022-02-21 04:23:11,754 INFO L290 TraceCheckUtils]: 98: Hoare triple {10114#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {10114#false} is VALID [2022-02-21 04:23:11,754 INFO L290 TraceCheckUtils]: 99: Hoare triple {10114#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {10114#false} is VALID [2022-02-21 04:23:11,754 INFO L290 TraceCheckUtils]: 100: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___7~0#1); {10114#false} is VALID [2022-02-21 04:23:11,754 INFO L290 TraceCheckUtils]: 101: Hoare triple {10114#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {10114#false} is VALID [2022-02-21 04:23:11,755 INFO L290 TraceCheckUtils]: 102: Hoare triple {10114#false} assume 1 == ~t9_pc~0; {10114#false} is VALID [2022-02-21 04:23:11,755 INFO L290 TraceCheckUtils]: 103: Hoare triple {10114#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {10114#false} is VALID [2022-02-21 04:23:11,755 INFO L290 TraceCheckUtils]: 104: Hoare triple {10114#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {10114#false} is VALID [2022-02-21 04:23:11,755 INFO L290 TraceCheckUtils]: 105: Hoare triple {10114#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {10114#false} is VALID [2022-02-21 04:23:11,755 INFO L290 TraceCheckUtils]: 106: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___8~0#1); {10114#false} is VALID [2022-02-21 04:23:11,755 INFO L290 TraceCheckUtils]: 107: Hoare triple {10114#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {10114#false} is VALID [2022-02-21 04:23:11,755 INFO L290 TraceCheckUtils]: 108: Hoare triple {10114#false} assume !(1 == ~t10_pc~0); {10114#false} is VALID [2022-02-21 04:23:11,755 INFO L290 TraceCheckUtils]: 109: Hoare triple {10114#false} is_transmit10_triggered_~__retres1~10#1 := 0; {10114#false} is VALID [2022-02-21 04:23:11,756 INFO L290 TraceCheckUtils]: 110: Hoare triple {10114#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {10114#false} is VALID [2022-02-21 04:23:11,756 INFO L290 TraceCheckUtils]: 111: Hoare triple {10114#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {10114#false} is VALID [2022-02-21 04:23:11,756 INFO L290 TraceCheckUtils]: 112: Hoare triple {10114#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {10114#false} is VALID [2022-02-21 04:23:11,756 INFO L290 TraceCheckUtils]: 113: Hoare triple {10114#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {10114#false} is VALID [2022-02-21 04:23:11,756 INFO L290 TraceCheckUtils]: 114: Hoare triple {10114#false} assume 1 == ~t11_pc~0; {10114#false} is VALID [2022-02-21 04:23:11,756 INFO L290 TraceCheckUtils]: 115: Hoare triple {10114#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {10114#false} is VALID [2022-02-21 04:23:11,756 INFO L290 TraceCheckUtils]: 116: Hoare triple {10114#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {10114#false} is VALID [2022-02-21 04:23:11,756 INFO L290 TraceCheckUtils]: 117: Hoare triple {10114#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {10114#false} is VALID [2022-02-21 04:23:11,756 INFO L290 TraceCheckUtils]: 118: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___10~0#1); {10114#false} is VALID [2022-02-21 04:23:11,757 INFO L290 TraceCheckUtils]: 119: Hoare triple {10114#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {10114#false} is VALID [2022-02-21 04:23:11,757 INFO L290 TraceCheckUtils]: 120: Hoare triple {10114#false} assume !(1 == ~t12_pc~0); {10114#false} is VALID [2022-02-21 04:23:11,757 INFO L290 TraceCheckUtils]: 121: Hoare triple {10114#false} is_transmit12_triggered_~__retres1~12#1 := 0; {10114#false} is VALID [2022-02-21 04:23:11,757 INFO L290 TraceCheckUtils]: 122: Hoare triple {10114#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {10114#false} is VALID [2022-02-21 04:23:11,757 INFO L290 TraceCheckUtils]: 123: Hoare triple {10114#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {10114#false} is VALID [2022-02-21 04:23:11,757 INFO L290 TraceCheckUtils]: 124: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___11~0#1); {10114#false} is VALID [2022-02-21 04:23:11,757 INFO L290 TraceCheckUtils]: 125: Hoare triple {10114#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {10114#false} is VALID [2022-02-21 04:23:11,757 INFO L290 TraceCheckUtils]: 126: Hoare triple {10114#false} assume 1 == ~t13_pc~0; {10114#false} is VALID [2022-02-21 04:23:11,758 INFO L290 TraceCheckUtils]: 127: Hoare triple {10114#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {10114#false} is VALID [2022-02-21 04:23:11,758 INFO L290 TraceCheckUtils]: 128: Hoare triple {10114#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {10114#false} is VALID [2022-02-21 04:23:11,758 INFO L290 TraceCheckUtils]: 129: Hoare triple {10114#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {10114#false} is VALID [2022-02-21 04:23:11,759 INFO L290 TraceCheckUtils]: 130: Hoare triple {10114#false} assume !(0 != activate_threads_~tmp___12~0#1); {10114#false} is VALID [2022-02-21 04:23:11,759 INFO L290 TraceCheckUtils]: 131: Hoare triple {10114#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10114#false} is VALID [2022-02-21 04:23:11,759 INFO L290 TraceCheckUtils]: 132: Hoare triple {10114#false} assume !(1 == ~M_E~0); {10114#false} is VALID [2022-02-21 04:23:11,759 INFO L290 TraceCheckUtils]: 133: Hoare triple {10114#false} assume !(1 == ~T1_E~0); {10114#false} is VALID [2022-02-21 04:23:11,759 INFO L290 TraceCheckUtils]: 134: Hoare triple {10114#false} assume !(1 == ~T2_E~0); {10114#false} is VALID [2022-02-21 04:23:11,759 INFO L290 TraceCheckUtils]: 135: Hoare triple {10114#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,759 INFO L290 TraceCheckUtils]: 136: Hoare triple {10114#false} assume !(1 == ~T4_E~0); {10114#false} is VALID [2022-02-21 04:23:11,759 INFO L290 TraceCheckUtils]: 137: Hoare triple {10114#false} assume !(1 == ~T5_E~0); {10114#false} is VALID [2022-02-21 04:23:11,759 INFO L290 TraceCheckUtils]: 138: Hoare triple {10114#false} assume !(1 == ~T6_E~0); {10114#false} is VALID [2022-02-21 04:23:11,760 INFO L290 TraceCheckUtils]: 139: Hoare triple {10114#false} assume !(1 == ~T7_E~0); {10114#false} is VALID [2022-02-21 04:23:11,760 INFO L290 TraceCheckUtils]: 140: Hoare triple {10114#false} assume !(1 == ~T8_E~0); {10114#false} is VALID [2022-02-21 04:23:11,760 INFO L290 TraceCheckUtils]: 141: Hoare triple {10114#false} assume !(1 == ~T9_E~0); {10114#false} is VALID [2022-02-21 04:23:11,760 INFO L290 TraceCheckUtils]: 142: Hoare triple {10114#false} assume !(1 == ~T10_E~0); {10114#false} is VALID [2022-02-21 04:23:11,760 INFO L290 TraceCheckUtils]: 143: Hoare triple {10114#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,760 INFO L290 TraceCheckUtils]: 144: Hoare triple {10114#false} assume !(1 == ~T12_E~0); {10114#false} is VALID [2022-02-21 04:23:11,760 INFO L290 TraceCheckUtils]: 145: Hoare triple {10114#false} assume !(1 == ~T13_E~0); {10114#false} is VALID [2022-02-21 04:23:11,760 INFO L290 TraceCheckUtils]: 146: Hoare triple {10114#false} assume !(1 == ~E_M~0); {10114#false} is VALID [2022-02-21 04:23:11,760 INFO L290 TraceCheckUtils]: 147: Hoare triple {10114#false} assume !(1 == ~E_1~0); {10114#false} is VALID [2022-02-21 04:23:11,761 INFO L290 TraceCheckUtils]: 148: Hoare triple {10114#false} assume !(1 == ~E_2~0); {10114#false} is VALID [2022-02-21 04:23:11,761 INFO L290 TraceCheckUtils]: 149: Hoare triple {10114#false} assume !(1 == ~E_3~0); {10114#false} is VALID [2022-02-21 04:23:11,761 INFO L290 TraceCheckUtils]: 150: Hoare triple {10114#false} assume !(1 == ~E_4~0); {10114#false} is VALID [2022-02-21 04:23:11,761 INFO L290 TraceCheckUtils]: 151: Hoare triple {10114#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,761 INFO L290 TraceCheckUtils]: 152: Hoare triple {10114#false} assume !(1 == ~E_6~0); {10114#false} is VALID [2022-02-21 04:23:11,761 INFO L290 TraceCheckUtils]: 153: Hoare triple {10114#false} assume !(1 == ~E_7~0); {10114#false} is VALID [2022-02-21 04:23:11,761 INFO L290 TraceCheckUtils]: 154: Hoare triple {10114#false} assume !(1 == ~E_8~0); {10114#false} is VALID [2022-02-21 04:23:11,761 INFO L290 TraceCheckUtils]: 155: Hoare triple {10114#false} assume !(1 == ~E_9~0); {10114#false} is VALID [2022-02-21 04:23:11,761 INFO L290 TraceCheckUtils]: 156: Hoare triple {10114#false} assume !(1 == ~E_10~0); {10114#false} is VALID [2022-02-21 04:23:11,762 INFO L290 TraceCheckUtils]: 157: Hoare triple {10114#false} assume !(1 == ~E_11~0); {10114#false} is VALID [2022-02-21 04:23:11,762 INFO L290 TraceCheckUtils]: 158: Hoare triple {10114#false} assume !(1 == ~E_12~0); {10114#false} is VALID [2022-02-21 04:23:11,762 INFO L290 TraceCheckUtils]: 159: Hoare triple {10114#false} assume 1 == ~E_13~0;~E_13~0 := 2; {10114#false} is VALID [2022-02-21 04:23:11,762 INFO L290 TraceCheckUtils]: 160: Hoare triple {10114#false} assume { :end_inline_reset_delta_events } true; {10114#false} is VALID [2022-02-21 04:23:11,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,764 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,765 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187445402] [2022-02-21 04:23:11,765 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [187445402] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,765 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,765 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,765 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [371468965] [2022-02-21 04:23:11,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,766 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:11,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,770 INFO L85 PathProgramCache]: Analyzing trace with hash -1579703507, now seen corresponding path program 1 times [2022-02-21 04:23:11,770 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,771 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1285372557] [2022-02-21 04:23:11,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,863 INFO L290 TraceCheckUtils]: 0: Hoare triple {10116#true} assume !false; {10116#true} is VALID [2022-02-21 04:23:11,864 INFO L290 TraceCheckUtils]: 1: Hoare triple {10116#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10116#true} is VALID [2022-02-21 04:23:11,864 INFO L290 TraceCheckUtils]: 2: Hoare triple {10116#true} assume !false; {10116#true} is VALID [2022-02-21 04:23:11,864 INFO L290 TraceCheckUtils]: 3: Hoare triple {10116#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {10116#true} is VALID [2022-02-21 04:23:11,864 INFO L290 TraceCheckUtils]: 4: Hoare triple {10116#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {10116#true} is VALID [2022-02-21 04:23:11,864 INFO L290 TraceCheckUtils]: 5: Hoare triple {10116#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {10116#true} is VALID [2022-02-21 04:23:11,864 INFO L290 TraceCheckUtils]: 6: Hoare triple {10116#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {10116#true} is VALID [2022-02-21 04:23:11,864 INFO L290 TraceCheckUtils]: 7: Hoare triple {10116#true} assume !(0 != eval_~tmp~0#1); {10116#true} is VALID [2022-02-21 04:23:11,864 INFO L290 TraceCheckUtils]: 8: Hoare triple {10116#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10116#true} is VALID [2022-02-21 04:23:11,864 INFO L290 TraceCheckUtils]: 9: Hoare triple {10116#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10116#true} is VALID [2022-02-21 04:23:11,865 INFO L290 TraceCheckUtils]: 10: Hoare triple {10116#true} assume 0 == ~M_E~0;~M_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,865 INFO L290 TraceCheckUtils]: 11: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,865 INFO L290 TraceCheckUtils]: 12: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,866 INFO L290 TraceCheckUtils]: 13: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,866 INFO L290 TraceCheckUtils]: 14: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,866 INFO L290 TraceCheckUtils]: 15: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,867 INFO L290 TraceCheckUtils]: 16: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,867 INFO L290 TraceCheckUtils]: 17: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,867 INFO L290 TraceCheckUtils]: 18: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,868 INFO L290 TraceCheckUtils]: 19: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,868 INFO L290 TraceCheckUtils]: 20: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,868 INFO L290 TraceCheckUtils]: 21: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,868 INFO L290 TraceCheckUtils]: 22: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,869 INFO L290 TraceCheckUtils]: 23: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,869 INFO L290 TraceCheckUtils]: 24: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,869 INFO L290 TraceCheckUtils]: 25: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,870 INFO L290 TraceCheckUtils]: 26: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,870 INFO L290 TraceCheckUtils]: 27: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,870 INFO L290 TraceCheckUtils]: 28: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,871 INFO L290 TraceCheckUtils]: 29: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,871 INFO L290 TraceCheckUtils]: 30: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,871 INFO L290 TraceCheckUtils]: 31: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,871 INFO L290 TraceCheckUtils]: 32: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,872 INFO L290 TraceCheckUtils]: 33: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,872 INFO L290 TraceCheckUtils]: 34: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,872 INFO L290 TraceCheckUtils]: 35: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,873 INFO L290 TraceCheckUtils]: 36: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,873 INFO L290 TraceCheckUtils]: 37: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,873 INFO L290 TraceCheckUtils]: 38: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,873 INFO L290 TraceCheckUtils]: 39: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,874 INFO L290 TraceCheckUtils]: 40: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,874 INFO L290 TraceCheckUtils]: 41: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,874 INFO L290 TraceCheckUtils]: 42: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,874 INFO L290 TraceCheckUtils]: 43: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,875 INFO L290 TraceCheckUtils]: 44: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,875 INFO L290 TraceCheckUtils]: 45: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,875 INFO L290 TraceCheckUtils]: 46: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,876 INFO L290 TraceCheckUtils]: 47: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 48: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 49: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 50: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 51: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 52: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 53: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 54: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 55: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 56: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 57: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,891 INFO L290 TraceCheckUtils]: 58: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,891 INFO L290 TraceCheckUtils]: 59: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,891 INFO L290 TraceCheckUtils]: 60: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,891 INFO L290 TraceCheckUtils]: 61: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,892 INFO L290 TraceCheckUtils]: 62: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,892 INFO L290 TraceCheckUtils]: 63: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,892 INFO L290 TraceCheckUtils]: 64: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,893 INFO L290 TraceCheckUtils]: 65: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,893 INFO L290 TraceCheckUtils]: 66: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,893 INFO L290 TraceCheckUtils]: 67: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,894 INFO L290 TraceCheckUtils]: 68: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,894 INFO L290 TraceCheckUtils]: 69: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,894 INFO L290 TraceCheckUtils]: 70: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,895 INFO L290 TraceCheckUtils]: 71: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,895 INFO L290 TraceCheckUtils]: 72: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,895 INFO L290 TraceCheckUtils]: 73: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,895 INFO L290 TraceCheckUtils]: 74: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,896 INFO L290 TraceCheckUtils]: 75: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,896 INFO L290 TraceCheckUtils]: 76: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,896 INFO L290 TraceCheckUtils]: 77: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,897 INFO L290 TraceCheckUtils]: 78: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,897 INFO L290 TraceCheckUtils]: 79: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,897 INFO L290 TraceCheckUtils]: 80: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,898 INFO L290 TraceCheckUtils]: 81: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,898 INFO L290 TraceCheckUtils]: 82: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,898 INFO L290 TraceCheckUtils]: 83: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,898 INFO L290 TraceCheckUtils]: 84: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,899 INFO L290 TraceCheckUtils]: 85: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,899 INFO L290 TraceCheckUtils]: 86: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,899 INFO L290 TraceCheckUtils]: 87: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,900 INFO L290 TraceCheckUtils]: 88: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,900 INFO L290 TraceCheckUtils]: 89: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,900 INFO L290 TraceCheckUtils]: 90: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,900 INFO L290 TraceCheckUtils]: 91: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,901 INFO L290 TraceCheckUtils]: 92: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,901 INFO L290 TraceCheckUtils]: 93: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,901 INFO L290 TraceCheckUtils]: 94: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,902 INFO L290 TraceCheckUtils]: 95: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,902 INFO L290 TraceCheckUtils]: 96: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,902 INFO L290 TraceCheckUtils]: 97: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,902 INFO L290 TraceCheckUtils]: 98: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,903 INFO L290 TraceCheckUtils]: 99: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,903 INFO L290 TraceCheckUtils]: 100: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,903 INFO L290 TraceCheckUtils]: 101: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,904 INFO L290 TraceCheckUtils]: 102: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,904 INFO L290 TraceCheckUtils]: 103: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,904 INFO L290 TraceCheckUtils]: 104: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,904 INFO L290 TraceCheckUtils]: 105: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,905 INFO L290 TraceCheckUtils]: 106: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,905 INFO L290 TraceCheckUtils]: 107: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,905 INFO L290 TraceCheckUtils]: 108: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,905 INFO L290 TraceCheckUtils]: 109: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,906 INFO L290 TraceCheckUtils]: 110: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,906 INFO L290 TraceCheckUtils]: 111: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,906 INFO L290 TraceCheckUtils]: 112: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,907 INFO L290 TraceCheckUtils]: 113: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,907 INFO L290 TraceCheckUtils]: 114: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,919 INFO L290 TraceCheckUtils]: 115: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,920 INFO L290 TraceCheckUtils]: 116: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,920 INFO L290 TraceCheckUtils]: 117: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,920 INFO L290 TraceCheckUtils]: 118: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,921 INFO L290 TraceCheckUtils]: 119: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,921 INFO L290 TraceCheckUtils]: 120: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,921 INFO L290 TraceCheckUtils]: 121: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 122: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10118#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 123: Hoare triple {10118#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {10117#false} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 124: Hoare triple {10117#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 125: Hoare triple {10117#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 126: Hoare triple {10117#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 127: Hoare triple {10117#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 128: Hoare triple {10117#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 129: Hoare triple {10117#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 130: Hoare triple {10117#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 131: Hoare triple {10117#false} assume !(1 == ~T8_E~0); {10117#false} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 132: Hoare triple {10117#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,922 INFO L290 TraceCheckUtils]: 133: Hoare triple {10117#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 134: Hoare triple {10117#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 135: Hoare triple {10117#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 136: Hoare triple {10117#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 137: Hoare triple {10117#false} assume 1 == ~E_M~0;~E_M~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 138: Hoare triple {10117#false} assume 1 == ~E_1~0;~E_1~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 139: Hoare triple {10117#false} assume !(1 == ~E_2~0); {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 140: Hoare triple {10117#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 141: Hoare triple {10117#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 142: Hoare triple {10117#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 143: Hoare triple {10117#false} assume 1 == ~E_6~0;~E_6~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 144: Hoare triple {10117#false} assume 1 == ~E_7~0;~E_7~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 145: Hoare triple {10117#false} assume 1 == ~E_8~0;~E_8~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 146: Hoare triple {10117#false} assume 1 == ~E_9~0;~E_9~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 147: Hoare triple {10117#false} assume !(1 == ~E_10~0); {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 148: Hoare triple {10117#false} assume 1 == ~E_11~0;~E_11~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 149: Hoare triple {10117#false} assume 1 == ~E_12~0;~E_12~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,923 INFO L290 TraceCheckUtils]: 150: Hoare triple {10117#false} assume 1 == ~E_13~0;~E_13~0 := 2; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 151: Hoare triple {10117#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 152: Hoare triple {10117#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 153: Hoare triple {10117#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 154: Hoare triple {10117#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 155: Hoare triple {10117#false} assume !(0 == start_simulation_~tmp~3#1); {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 156: Hoare triple {10117#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 157: Hoare triple {10117#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 158: Hoare triple {10117#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 159: Hoare triple {10117#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 160: Hoare triple {10117#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 161: Hoare triple {10117#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 162: Hoare triple {10117#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {10117#false} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 163: Hoare triple {10117#false} assume !(0 != start_simulation_~tmp___0~1#1); {10117#false} is VALID [2022-02-21 04:23:11,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,925 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,925 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1285372557] [2022-02-21 04:23:11,926 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1285372557] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,926 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,926 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,926 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [276401654] [2022-02-21 04:23:11,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,927 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:11,927 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:11,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:11,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:11,928 INFO L87 Difference]: Start difference. First operand 2018 states and 2987 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,854 INFO L93 Difference]: Finished difference Result 2018 states and 2986 transitions. [2022-02-21 04:23:13,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:13,854 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,958 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:13,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2986 transitions. [2022-02-21 04:23:14,062 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:14,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2986 transitions. [2022-02-21 04:23:14,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:14,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:14,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2986 transitions. [2022-02-21 04:23:14,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:14,167 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2022-02-21 04:23:14,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2986 transitions. [2022-02-21 04:23:14,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:14,185 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:14,188 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2986 transitions. Second operand has 2018 states, 2018 states have (on average 1.4796828543111993) internal successors, (2986), 2017 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,191 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2986 transitions. Second operand has 2018 states, 2018 states have (on average 1.4796828543111993) internal successors, (2986), 2017 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,193 INFO L87 Difference]: Start difference. First operand 2018 states and 2986 transitions. Second operand has 2018 states, 2018 states have (on average 1.4796828543111993) internal successors, (2986), 2017 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,287 INFO L93 Difference]: Finished difference Result 2018 states and 2986 transitions. [2022-02-21 04:23:14,287 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2986 transitions. [2022-02-21 04:23:14,289 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,289 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,293 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.4796828543111993) internal successors, (2986), 2017 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2986 transitions. [2022-02-21 04:23:14,294 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.4796828543111993) internal successors, (2986), 2017 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2986 transitions. [2022-02-21 04:23:14,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,388 INFO L93 Difference]: Finished difference Result 2018 states and 2986 transitions. [2022-02-21 04:23:14,388 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2986 transitions. [2022-02-21 04:23:14,390 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,390 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,390 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:14,390 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:14,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4796828543111993) internal successors, (2986), 2017 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2986 transitions. [2022-02-21 04:23:14,481 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2022-02-21 04:23:14,481 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2022-02-21 04:23:14,481 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:23:14,481 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2986 transitions. [2022-02-21 04:23:14,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:14,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:14,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:14,489 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:14,489 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:14,489 INFO L791 eck$LassoCheckResult]: Stem: 13052#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 13053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 14089#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13544#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13545#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 13034#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13035#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 13101#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13102#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13540#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13541#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13067#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12886#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12887#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13331#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13332#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13207#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13208#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12857#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12858#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 14081#L1279-2 assume !(0 == ~T1_E~0); 12480#L1284-1 assume !(0 == ~T2_E~0); 12481#L1289-1 assume !(0 == ~T3_E~0); 13204#L1294-1 assume !(0 == ~T4_E~0); 13205#L1299-1 assume !(0 == ~T5_E~0); 13216#L1304-1 assume !(0 == ~T6_E~0); 14147#L1309-1 assume !(0 == ~T7_E~0); 14148#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12410#L1319-1 assume !(0 == ~T9_E~0); 12411#L1324-1 assume !(0 == ~T10_E~0); 12583#L1329-1 assume !(0 == ~T11_E~0); 12584#L1334-1 assume !(0 == ~T12_E~0); 13988#L1339-1 assume !(0 == ~T13_E~0); 14069#L1344-1 assume !(0 == ~E_M~0); 14070#L1349-1 assume !(0 == ~E_1~0); 13391#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 13392#L1359-1 assume !(0 == ~E_3~0); 13821#L1364-1 assume !(0 == ~E_4~0); 12712#L1369-1 assume !(0 == ~E_5~0); 12713#L1374-1 assume !(0 == ~E_6~0); 13396#L1379-1 assume !(0 == ~E_7~0); 13397#L1384-1 assume !(0 == ~E_8~0); 13474#L1389-1 assume !(0 == ~E_9~0); 14007#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 14008#L1399-1 assume !(0 == ~E_11~0); 14111#L1404-1 assume !(0 == ~E_12~0); 12805#L1409-1 assume !(0 == ~E_13~0); 12806#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14103#L628 assume !(1 == ~m_pc~0); 12709#L628-2 is_master_triggered_~__retres1~0#1 := 0; 12708#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13472#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13473#L1591 assume !(0 != activate_threads_~tmp~1#1); 14116#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13260#L647 assume 1 == ~t1_pc~0; 12629#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12630#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12901#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12902#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 14056#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14057#L666 assume 1 == ~t2_pc~0; 12477#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12478#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12644#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14073#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 13592#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13593#L685 assume !(1 == ~t3_pc~0); 13698#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13697#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13320#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13321#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13442#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12928#L704 assume 1 == ~t4_pc~0; 12929#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13453#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13454#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14094#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 13313#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13314#L723 assume !(1 == ~t5_pc~0); 13436#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13672#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13816#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13571#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 13572#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12694#L742 assume 1 == ~t6_pc~0; 12695#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12843#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12844#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12379#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 12380#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12771#L761 assume !(1 == ~t7_pc~0); 12772#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12640#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12641#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13443#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 13444#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12404#L780 assume 1 == ~t8_pc~0; 12405#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12680#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12681#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13404#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 13405#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13524#L799 assume 1 == ~t9_pc~0; 13636#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12407#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12408#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13536#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 13743#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13554#L818 assume !(1 == ~t10_pc~0); 12188#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12189#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13629#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13558#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13559#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13599#L837 assume 1 == ~t11_pc~0; 13600#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13434#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13837#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13517#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 13518#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13269#L856 assume !(1 == ~t12_pc~0); 13270#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 13923#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13924#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13904#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 13905#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14084#L875 assume 1 == ~t13_pc~0; 13214#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12846#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12847#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12786#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 12787#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13626#L1427 assume !(1 == ~M_E~0); 13610#L1427-2 assume !(1 == ~T1_E~0); 12758#L1432-1 assume !(1 == ~T2_E~0); 12759#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13827#L1442-1 assume !(1 == ~T4_E~0); 13828#L1447-1 assume !(1 == ~T5_E~0); 13683#L1452-1 assume !(1 == ~T6_E~0); 12323#L1457-1 assume !(1 == ~T7_E~0); 12324#L1462-1 assume !(1 == ~T8_E~0); 13854#L1467-1 assume !(1 == ~T9_E~0); 13872#L1472-1 assume !(1 == ~T10_E~0); 13873#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13624#L1482-1 assume !(1 == ~T12_E~0); 13625#L1487-1 assume !(1 == ~T13_E~0); 12654#L1492-1 assume !(1 == ~E_M~0); 12655#L1497-1 assume !(1 == ~E_1~0); 13016#L1502-1 assume !(1 == ~E_2~0); 13017#L1507-1 assume !(1 == ~E_3~0); 12532#L1512-1 assume !(1 == ~E_4~0); 12533#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 13943#L1522-1 assume !(1 == ~E_6~0); 13257#L1527-1 assume !(1 == ~E_7~0); 13258#L1532-1 assume !(1 == ~E_8~0); 14131#L1537-1 assume !(1 == ~E_9~0); 13460#L1542-1 assume !(1 == ~E_10~0); 13291#L1547-1 assume !(1 == ~E_11~0); 13292#L1552-1 assume !(1 == ~E_12~0); 12227#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 12228#L1562-1 assume { :end_inline_reset_delta_events } true; 12834#L1928-2 [2022-02-21 04:23:14,490 INFO L793 eck$LassoCheckResult]: Loop: 12834#L1928-2 assume !false; 13325#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12488#L1254 assume !false; 13075#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12562#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12563#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12760#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13931#L1067 assume !(0 != eval_~tmp~0#1); 13001#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12578#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12579#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13038#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13020#L1284-3 assume !(0 == ~T2_E~0); 13021#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12999#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13000#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13387#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13388#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12897#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12898#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13894#L1324-3 assume !(0 == ~T10_E~0); 12529#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12530#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13297#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13298#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13596#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12878#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12879#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13607#L1364-3 assume !(0 == ~E_4~0); 14129#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14025#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12658#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12659#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12876#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12877#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13167#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14035#L1404-3 assume !(0 == ~E_12~0); 13999#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 14000#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13486#L628-45 assume 1 == ~m_pc~0; 13164#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13166#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12523#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12524#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12912#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13635#L647-45 assume 1 == ~t1_pc~0; 12474#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12475#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13403#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12588#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12589#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12800#L666-45 assume !(1 == ~t2_pc~0); 12801#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 13282#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13844#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13759#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13753#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12338#L685-45 assume 1 == ~t3_pc~0; 12339#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13398#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14072#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13941#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13942#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14082#L704-45 assume 1 == ~t4_pc~0; 13961#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12205#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13064#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13407#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14154#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13519#L723-45 assume !(1 == ~t5_pc~0); 13520#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 14009#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13111#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12888#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 12889#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13913#L742-45 assume 1 == ~t6_pc~0; 13914#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13136#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13605#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13641#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13642#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13730#L761-45 assume !(1 == ~t7_pc~0); 13731#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 13129#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13130#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12536#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12537#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14003#L780-45 assume 1 == ~t8_pc~0; 12914#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12548#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12549#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14130#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12518#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12519#L799-45 assume !(1 == ~t9_pc~0); 12739#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 12740#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14055#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13684#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13685#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12456#L818-45 assume 1 == ~t10_pc~0; 12457#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12575#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13658#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13062#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13063#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13778#L837-45 assume !(1 == ~t11_pc~0); 12993#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 12994#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13131#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13796#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12594#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12595#L856-45 assume 1 == ~t12_pc~0; 14080#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12597#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12538#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12539#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13401#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13402#L875-45 assume 1 == ~t13_pc~0; 13372#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13373#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13435#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14047#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 14048#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13987#L1427-3 assume !(1 == ~M_E~0); 13198#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13199#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13737#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13389#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13390#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12246#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12247#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13929#L1462-3 assume !(1 == ~T8_E~0); 13930#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13793#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13794#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12497#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12498#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12639#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12812#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12813#L1502-3 assume !(1 == ~E_2~0); 13761#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13892#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12850#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12542#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12543#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12507#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12508#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13608#L1542-3 assume !(1 == ~E_10~0); 13746#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13375#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13376#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12718#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12719#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12138#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12903#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12904#L1947 assume !(0 == start_simulation_~tmp~3#1); 13509#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13714#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12775#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 14107#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 14031#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13861#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13620#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13621#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 12834#L1928-2 [2022-02-21 04:23:14,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:14,490 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2022-02-21 04:23:14,490 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:14,491 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517120452] [2022-02-21 04:23:14,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:14,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:14,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:14,518 INFO L290 TraceCheckUtils]: 0: Hoare triple {18194#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {18194#true} is VALID [2022-02-21 04:23:14,518 INFO L290 TraceCheckUtils]: 1: Hoare triple {18194#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {18196#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:14,518 INFO L290 TraceCheckUtils]: 2: Hoare triple {18196#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {18196#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:14,519 INFO L290 TraceCheckUtils]: 3: Hoare triple {18196#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {18196#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:14,519 INFO L290 TraceCheckUtils]: 4: Hoare triple {18196#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {18196#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:14,519 INFO L290 TraceCheckUtils]: 5: Hoare triple {18196#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {18196#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:14,520 INFO L290 TraceCheckUtils]: 6: Hoare triple {18196#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,520 INFO L290 TraceCheckUtils]: 7: Hoare triple {18195#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,520 INFO L290 TraceCheckUtils]: 8: Hoare triple {18195#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,520 INFO L290 TraceCheckUtils]: 9: Hoare triple {18195#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,520 INFO L290 TraceCheckUtils]: 10: Hoare triple {18195#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,520 INFO L290 TraceCheckUtils]: 11: Hoare triple {18195#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,520 INFO L290 TraceCheckUtils]: 12: Hoare triple {18195#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,520 INFO L290 TraceCheckUtils]: 13: Hoare triple {18195#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {18195#false} is VALID [2022-02-21 04:23:14,520 INFO L290 TraceCheckUtils]: 14: Hoare triple {18195#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,520 INFO L290 TraceCheckUtils]: 15: Hoare triple {18195#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 16: Hoare triple {18195#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 17: Hoare triple {18195#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 18: Hoare triple {18195#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {18195#false} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 19: Hoare triple {18195#false} assume 0 == ~M_E~0;~M_E~0 := 1; {18195#false} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 20: Hoare triple {18195#false} assume !(0 == ~T1_E~0); {18195#false} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 21: Hoare triple {18195#false} assume !(0 == ~T2_E~0); {18195#false} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 22: Hoare triple {18195#false} assume !(0 == ~T3_E~0); {18195#false} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 23: Hoare triple {18195#false} assume !(0 == ~T4_E~0); {18195#false} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 24: Hoare triple {18195#false} assume !(0 == ~T5_E~0); {18195#false} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 25: Hoare triple {18195#false} assume !(0 == ~T6_E~0); {18195#false} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 26: Hoare triple {18195#false} assume !(0 == ~T7_E~0); {18195#false} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 27: Hoare triple {18195#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {18195#false} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 28: Hoare triple {18195#false} assume !(0 == ~T9_E~0); {18195#false} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 29: Hoare triple {18195#false} assume !(0 == ~T10_E~0); {18195#false} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 30: Hoare triple {18195#false} assume !(0 == ~T11_E~0); {18195#false} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 31: Hoare triple {18195#false} assume !(0 == ~T12_E~0); {18195#false} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 32: Hoare triple {18195#false} assume !(0 == ~T13_E~0); {18195#false} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 33: Hoare triple {18195#false} assume !(0 == ~E_M~0); {18195#false} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 34: Hoare triple {18195#false} assume !(0 == ~E_1~0); {18195#false} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 35: Hoare triple {18195#false} assume 0 == ~E_2~0;~E_2~0 := 1; {18195#false} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 36: Hoare triple {18195#false} assume !(0 == ~E_3~0); {18195#false} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 37: Hoare triple {18195#false} assume !(0 == ~E_4~0); {18195#false} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 38: Hoare triple {18195#false} assume !(0 == ~E_5~0); {18195#false} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 39: Hoare triple {18195#false} assume !(0 == ~E_6~0); {18195#false} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 40: Hoare triple {18195#false} assume !(0 == ~E_7~0); {18195#false} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 41: Hoare triple {18195#false} assume !(0 == ~E_8~0); {18195#false} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 42: Hoare triple {18195#false} assume !(0 == ~E_9~0); {18195#false} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 43: Hoare triple {18195#false} assume 0 == ~E_10~0;~E_10~0 := 1; {18195#false} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 44: Hoare triple {18195#false} assume !(0 == ~E_11~0); {18195#false} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 45: Hoare triple {18195#false} assume !(0 == ~E_12~0); {18195#false} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 46: Hoare triple {18195#false} assume !(0 == ~E_13~0); {18195#false} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 47: Hoare triple {18195#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18195#false} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 48: Hoare triple {18195#false} assume !(1 == ~m_pc~0); {18195#false} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 49: Hoare triple {18195#false} is_master_triggered_~__retres1~0#1 := 0; {18195#false} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 50: Hoare triple {18195#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18195#false} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 51: Hoare triple {18195#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {18195#false} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 52: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp~1#1); {18195#false} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 53: Hoare triple {18195#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18195#false} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 54: Hoare triple {18195#false} assume 1 == ~t1_pc~0; {18195#false} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 55: Hoare triple {18195#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {18195#false} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 56: Hoare triple {18195#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18195#false} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 57: Hoare triple {18195#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {18195#false} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 58: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___0~0#1); {18195#false} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 59: Hoare triple {18195#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18195#false} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 60: Hoare triple {18195#false} assume 1 == ~t2_pc~0; {18195#false} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 61: Hoare triple {18195#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {18195#false} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 62: Hoare triple {18195#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18195#false} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 63: Hoare triple {18195#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {18195#false} is VALID [2022-02-21 04:23:14,526 INFO L290 TraceCheckUtils]: 64: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___1~0#1); {18195#false} is VALID [2022-02-21 04:23:14,526 INFO L290 TraceCheckUtils]: 65: Hoare triple {18195#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18195#false} is VALID [2022-02-21 04:23:14,526 INFO L290 TraceCheckUtils]: 66: Hoare triple {18195#false} assume !(1 == ~t3_pc~0); {18195#false} is VALID [2022-02-21 04:23:14,526 INFO L290 TraceCheckUtils]: 67: Hoare triple {18195#false} is_transmit3_triggered_~__retres1~3#1 := 0; {18195#false} is VALID [2022-02-21 04:23:14,526 INFO L290 TraceCheckUtils]: 68: Hoare triple {18195#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18195#false} is VALID [2022-02-21 04:23:14,526 INFO L290 TraceCheckUtils]: 69: Hoare triple {18195#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {18195#false} is VALID [2022-02-21 04:23:14,526 INFO L290 TraceCheckUtils]: 70: Hoare triple {18195#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {18195#false} is VALID [2022-02-21 04:23:14,526 INFO L290 TraceCheckUtils]: 71: Hoare triple {18195#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {18195#false} is VALID [2022-02-21 04:23:14,526 INFO L290 TraceCheckUtils]: 72: Hoare triple {18195#false} assume 1 == ~t4_pc~0; {18195#false} is VALID [2022-02-21 04:23:14,527 INFO L290 TraceCheckUtils]: 73: Hoare triple {18195#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {18195#false} is VALID [2022-02-21 04:23:14,527 INFO L290 TraceCheckUtils]: 74: Hoare triple {18195#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {18195#false} is VALID [2022-02-21 04:23:14,527 INFO L290 TraceCheckUtils]: 75: Hoare triple {18195#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {18195#false} is VALID [2022-02-21 04:23:14,527 INFO L290 TraceCheckUtils]: 76: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___3~0#1); {18195#false} is VALID [2022-02-21 04:23:14,527 INFO L290 TraceCheckUtils]: 77: Hoare triple {18195#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {18195#false} is VALID [2022-02-21 04:23:14,527 INFO L290 TraceCheckUtils]: 78: Hoare triple {18195#false} assume !(1 == ~t5_pc~0); {18195#false} is VALID [2022-02-21 04:23:14,527 INFO L290 TraceCheckUtils]: 79: Hoare triple {18195#false} is_transmit5_triggered_~__retres1~5#1 := 0; {18195#false} is VALID [2022-02-21 04:23:14,527 INFO L290 TraceCheckUtils]: 80: Hoare triple {18195#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {18195#false} is VALID [2022-02-21 04:23:14,527 INFO L290 TraceCheckUtils]: 81: Hoare triple {18195#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {18195#false} is VALID [2022-02-21 04:23:14,527 INFO L290 TraceCheckUtils]: 82: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___4~0#1); {18195#false} is VALID [2022-02-21 04:23:14,528 INFO L290 TraceCheckUtils]: 83: Hoare triple {18195#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {18195#false} is VALID [2022-02-21 04:23:14,528 INFO L290 TraceCheckUtils]: 84: Hoare triple {18195#false} assume 1 == ~t6_pc~0; {18195#false} is VALID [2022-02-21 04:23:14,528 INFO L290 TraceCheckUtils]: 85: Hoare triple {18195#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {18195#false} is VALID [2022-02-21 04:23:14,528 INFO L290 TraceCheckUtils]: 86: Hoare triple {18195#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {18195#false} is VALID [2022-02-21 04:23:14,528 INFO L290 TraceCheckUtils]: 87: Hoare triple {18195#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {18195#false} is VALID [2022-02-21 04:23:14,528 INFO L290 TraceCheckUtils]: 88: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___5~0#1); {18195#false} is VALID [2022-02-21 04:23:14,528 INFO L290 TraceCheckUtils]: 89: Hoare triple {18195#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {18195#false} is VALID [2022-02-21 04:23:14,528 INFO L290 TraceCheckUtils]: 90: Hoare triple {18195#false} assume !(1 == ~t7_pc~0); {18195#false} is VALID [2022-02-21 04:23:14,528 INFO L290 TraceCheckUtils]: 91: Hoare triple {18195#false} is_transmit7_triggered_~__retres1~7#1 := 0; {18195#false} is VALID [2022-02-21 04:23:14,528 INFO L290 TraceCheckUtils]: 92: Hoare triple {18195#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {18195#false} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 93: Hoare triple {18195#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {18195#false} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 94: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___6~0#1); {18195#false} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 95: Hoare triple {18195#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {18195#false} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 96: Hoare triple {18195#false} assume 1 == ~t8_pc~0; {18195#false} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 97: Hoare triple {18195#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {18195#false} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 98: Hoare triple {18195#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {18195#false} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 99: Hoare triple {18195#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {18195#false} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 100: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___7~0#1); {18195#false} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 101: Hoare triple {18195#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {18195#false} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 102: Hoare triple {18195#false} assume 1 == ~t9_pc~0; {18195#false} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 103: Hoare triple {18195#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {18195#false} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 104: Hoare triple {18195#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {18195#false} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 105: Hoare triple {18195#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {18195#false} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 106: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___8~0#1); {18195#false} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 107: Hoare triple {18195#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {18195#false} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 108: Hoare triple {18195#false} assume !(1 == ~t10_pc~0); {18195#false} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 109: Hoare triple {18195#false} is_transmit10_triggered_~__retres1~10#1 := 0; {18195#false} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 110: Hoare triple {18195#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {18195#false} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 111: Hoare triple {18195#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {18195#false} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 112: Hoare triple {18195#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {18195#false} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 113: Hoare triple {18195#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {18195#false} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 114: Hoare triple {18195#false} assume 1 == ~t11_pc~0; {18195#false} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 115: Hoare triple {18195#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {18195#false} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 116: Hoare triple {18195#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {18195#false} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 117: Hoare triple {18195#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {18195#false} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 118: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___10~0#1); {18195#false} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 119: Hoare triple {18195#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {18195#false} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 120: Hoare triple {18195#false} assume !(1 == ~t12_pc~0); {18195#false} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 121: Hoare triple {18195#false} is_transmit12_triggered_~__retres1~12#1 := 0; {18195#false} is VALID [2022-02-21 04:23:14,532 INFO L290 TraceCheckUtils]: 122: Hoare triple {18195#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {18195#false} is VALID [2022-02-21 04:23:14,532 INFO L290 TraceCheckUtils]: 123: Hoare triple {18195#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {18195#false} is VALID [2022-02-21 04:23:14,532 INFO L290 TraceCheckUtils]: 124: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___11~0#1); {18195#false} is VALID [2022-02-21 04:23:14,532 INFO L290 TraceCheckUtils]: 125: Hoare triple {18195#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {18195#false} is VALID [2022-02-21 04:23:14,532 INFO L290 TraceCheckUtils]: 126: Hoare triple {18195#false} assume 1 == ~t13_pc~0; {18195#false} is VALID [2022-02-21 04:23:14,532 INFO L290 TraceCheckUtils]: 127: Hoare triple {18195#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {18195#false} is VALID [2022-02-21 04:23:14,532 INFO L290 TraceCheckUtils]: 128: Hoare triple {18195#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {18195#false} is VALID [2022-02-21 04:23:14,532 INFO L290 TraceCheckUtils]: 129: Hoare triple {18195#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {18195#false} is VALID [2022-02-21 04:23:14,532 INFO L290 TraceCheckUtils]: 130: Hoare triple {18195#false} assume !(0 != activate_threads_~tmp___12~0#1); {18195#false} is VALID [2022-02-21 04:23:14,533 INFO L290 TraceCheckUtils]: 131: Hoare triple {18195#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18195#false} is VALID [2022-02-21 04:23:14,533 INFO L290 TraceCheckUtils]: 132: Hoare triple {18195#false} assume !(1 == ~M_E~0); {18195#false} is VALID [2022-02-21 04:23:14,533 INFO L290 TraceCheckUtils]: 133: Hoare triple {18195#false} assume !(1 == ~T1_E~0); {18195#false} is VALID [2022-02-21 04:23:14,533 INFO L290 TraceCheckUtils]: 134: Hoare triple {18195#false} assume !(1 == ~T2_E~0); {18195#false} is VALID [2022-02-21 04:23:14,533 INFO L290 TraceCheckUtils]: 135: Hoare triple {18195#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,533 INFO L290 TraceCheckUtils]: 136: Hoare triple {18195#false} assume !(1 == ~T4_E~0); {18195#false} is VALID [2022-02-21 04:23:14,533 INFO L290 TraceCheckUtils]: 137: Hoare triple {18195#false} assume !(1 == ~T5_E~0); {18195#false} is VALID [2022-02-21 04:23:14,533 INFO L290 TraceCheckUtils]: 138: Hoare triple {18195#false} assume !(1 == ~T6_E~0); {18195#false} is VALID [2022-02-21 04:23:14,533 INFO L290 TraceCheckUtils]: 139: Hoare triple {18195#false} assume !(1 == ~T7_E~0); {18195#false} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 140: Hoare triple {18195#false} assume !(1 == ~T8_E~0); {18195#false} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 141: Hoare triple {18195#false} assume !(1 == ~T9_E~0); {18195#false} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 142: Hoare triple {18195#false} assume !(1 == ~T10_E~0); {18195#false} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 143: Hoare triple {18195#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 144: Hoare triple {18195#false} assume !(1 == ~T12_E~0); {18195#false} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 145: Hoare triple {18195#false} assume !(1 == ~T13_E~0); {18195#false} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 146: Hoare triple {18195#false} assume !(1 == ~E_M~0); {18195#false} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 147: Hoare triple {18195#false} assume !(1 == ~E_1~0); {18195#false} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 148: Hoare triple {18195#false} assume !(1 == ~E_2~0); {18195#false} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 149: Hoare triple {18195#false} assume !(1 == ~E_3~0); {18195#false} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 150: Hoare triple {18195#false} assume !(1 == ~E_4~0); {18195#false} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 151: Hoare triple {18195#false} assume 1 == ~E_5~0;~E_5~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 152: Hoare triple {18195#false} assume !(1 == ~E_6~0); {18195#false} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 153: Hoare triple {18195#false} assume !(1 == ~E_7~0); {18195#false} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 154: Hoare triple {18195#false} assume !(1 == ~E_8~0); {18195#false} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 155: Hoare triple {18195#false} assume !(1 == ~E_9~0); {18195#false} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 156: Hoare triple {18195#false} assume !(1 == ~E_10~0); {18195#false} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 157: Hoare triple {18195#false} assume !(1 == ~E_11~0); {18195#false} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 158: Hoare triple {18195#false} assume !(1 == ~E_12~0); {18195#false} is VALID [2022-02-21 04:23:14,536 INFO L290 TraceCheckUtils]: 159: Hoare triple {18195#false} assume 1 == ~E_13~0;~E_13~0 := 2; {18195#false} is VALID [2022-02-21 04:23:14,536 INFO L290 TraceCheckUtils]: 160: Hoare triple {18195#false} assume { :end_inline_reset_delta_events } true; {18195#false} is VALID [2022-02-21 04:23:14,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:14,536 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:14,536 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517120452] [2022-02-21 04:23:14,536 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517120452] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:14,537 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:14,537 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:14,537 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [159195254] [2022-02-21 04:23:14,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:14,537 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:14,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:14,538 INFO L85 PathProgramCache]: Analyzing trace with hash -1433001491, now seen corresponding path program 1 times [2022-02-21 04:23:14,538 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:14,538 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717835321] [2022-02-21 04:23:14,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:14,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:14,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:14,584 INFO L290 TraceCheckUtils]: 0: Hoare triple {18197#true} assume !false; {18197#true} is VALID [2022-02-21 04:23:14,584 INFO L290 TraceCheckUtils]: 1: Hoare triple {18197#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {18197#true} is VALID [2022-02-21 04:23:14,584 INFO L290 TraceCheckUtils]: 2: Hoare triple {18197#true} assume !false; {18197#true} is VALID [2022-02-21 04:23:14,584 INFO L290 TraceCheckUtils]: 3: Hoare triple {18197#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {18197#true} is VALID [2022-02-21 04:23:14,585 INFO L290 TraceCheckUtils]: 4: Hoare triple {18197#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {18197#true} is VALID [2022-02-21 04:23:14,585 INFO L290 TraceCheckUtils]: 5: Hoare triple {18197#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {18197#true} is VALID [2022-02-21 04:23:14,585 INFO L290 TraceCheckUtils]: 6: Hoare triple {18197#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {18197#true} is VALID [2022-02-21 04:23:14,585 INFO L290 TraceCheckUtils]: 7: Hoare triple {18197#true} assume !(0 != eval_~tmp~0#1); {18197#true} is VALID [2022-02-21 04:23:14,585 INFO L290 TraceCheckUtils]: 8: Hoare triple {18197#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {18197#true} is VALID [2022-02-21 04:23:14,585 INFO L290 TraceCheckUtils]: 9: Hoare triple {18197#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {18197#true} is VALID [2022-02-21 04:23:14,585 INFO L290 TraceCheckUtils]: 10: Hoare triple {18197#true} assume 0 == ~M_E~0;~M_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,586 INFO L290 TraceCheckUtils]: 11: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,586 INFO L290 TraceCheckUtils]: 12: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,586 INFO L290 TraceCheckUtils]: 13: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,587 INFO L290 TraceCheckUtils]: 14: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,587 INFO L290 TraceCheckUtils]: 15: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,587 INFO L290 TraceCheckUtils]: 16: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,587 INFO L290 TraceCheckUtils]: 17: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,588 INFO L290 TraceCheckUtils]: 18: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,588 INFO L290 TraceCheckUtils]: 19: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,588 INFO L290 TraceCheckUtils]: 20: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,588 INFO L290 TraceCheckUtils]: 21: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,589 INFO L290 TraceCheckUtils]: 22: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,589 INFO L290 TraceCheckUtils]: 23: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,589 INFO L290 TraceCheckUtils]: 24: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,590 INFO L290 TraceCheckUtils]: 25: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,590 INFO L290 TraceCheckUtils]: 26: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,590 INFO L290 TraceCheckUtils]: 27: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,590 INFO L290 TraceCheckUtils]: 28: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,591 INFO L290 TraceCheckUtils]: 29: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,591 INFO L290 TraceCheckUtils]: 30: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,591 INFO L290 TraceCheckUtils]: 31: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,592 INFO L290 TraceCheckUtils]: 32: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,592 INFO L290 TraceCheckUtils]: 33: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,592 INFO L290 TraceCheckUtils]: 34: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,592 INFO L290 TraceCheckUtils]: 35: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,593 INFO L290 TraceCheckUtils]: 36: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,593 INFO L290 TraceCheckUtils]: 37: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,593 INFO L290 TraceCheckUtils]: 38: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,594 INFO L290 TraceCheckUtils]: 39: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,594 INFO L290 TraceCheckUtils]: 40: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,594 INFO L290 TraceCheckUtils]: 41: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,595 INFO L290 TraceCheckUtils]: 42: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,595 INFO L290 TraceCheckUtils]: 43: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,595 INFO L290 TraceCheckUtils]: 44: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,595 INFO L290 TraceCheckUtils]: 45: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,596 INFO L290 TraceCheckUtils]: 46: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,596 INFO L290 TraceCheckUtils]: 47: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,596 INFO L290 TraceCheckUtils]: 48: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,597 INFO L290 TraceCheckUtils]: 49: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,597 INFO L290 TraceCheckUtils]: 50: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,597 INFO L290 TraceCheckUtils]: 51: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,597 INFO L290 TraceCheckUtils]: 52: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,598 INFO L290 TraceCheckUtils]: 53: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,598 INFO L290 TraceCheckUtils]: 54: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,598 INFO L290 TraceCheckUtils]: 55: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,599 INFO L290 TraceCheckUtils]: 56: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,599 INFO L290 TraceCheckUtils]: 57: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,599 INFO L290 TraceCheckUtils]: 58: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,599 INFO L290 TraceCheckUtils]: 59: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,600 INFO L290 TraceCheckUtils]: 60: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,600 INFO L290 TraceCheckUtils]: 61: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,600 INFO L290 TraceCheckUtils]: 62: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,600 INFO L290 TraceCheckUtils]: 63: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,601 INFO L290 TraceCheckUtils]: 64: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,601 INFO L290 TraceCheckUtils]: 65: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,601 INFO L290 TraceCheckUtils]: 66: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,602 INFO L290 TraceCheckUtils]: 67: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,602 INFO L290 TraceCheckUtils]: 68: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,602 INFO L290 TraceCheckUtils]: 69: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,602 INFO L290 TraceCheckUtils]: 70: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,603 INFO L290 TraceCheckUtils]: 71: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,603 INFO L290 TraceCheckUtils]: 72: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,603 INFO L290 TraceCheckUtils]: 73: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,603 INFO L290 TraceCheckUtils]: 74: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,604 INFO L290 TraceCheckUtils]: 75: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,604 INFO L290 TraceCheckUtils]: 76: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,604 INFO L290 TraceCheckUtils]: 77: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,605 INFO L290 TraceCheckUtils]: 78: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,605 INFO L290 TraceCheckUtils]: 79: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,605 INFO L290 TraceCheckUtils]: 80: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,605 INFO L290 TraceCheckUtils]: 81: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,606 INFO L290 TraceCheckUtils]: 82: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,606 INFO L290 TraceCheckUtils]: 83: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,606 INFO L290 TraceCheckUtils]: 84: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,606 INFO L290 TraceCheckUtils]: 85: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,607 INFO L290 TraceCheckUtils]: 86: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,607 INFO L290 TraceCheckUtils]: 87: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,607 INFO L290 TraceCheckUtils]: 88: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,608 INFO L290 TraceCheckUtils]: 89: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,608 INFO L290 TraceCheckUtils]: 90: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,608 INFO L290 TraceCheckUtils]: 91: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,608 INFO L290 TraceCheckUtils]: 92: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,609 INFO L290 TraceCheckUtils]: 93: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,609 INFO L290 TraceCheckUtils]: 94: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,609 INFO L290 TraceCheckUtils]: 95: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,610 INFO L290 TraceCheckUtils]: 96: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,610 INFO L290 TraceCheckUtils]: 97: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,610 INFO L290 TraceCheckUtils]: 98: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,610 INFO L290 TraceCheckUtils]: 99: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,611 INFO L290 TraceCheckUtils]: 100: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,611 INFO L290 TraceCheckUtils]: 101: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,611 INFO L290 TraceCheckUtils]: 102: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,611 INFO L290 TraceCheckUtils]: 103: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,612 INFO L290 TraceCheckUtils]: 104: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,612 INFO L290 TraceCheckUtils]: 105: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,612 INFO L290 TraceCheckUtils]: 106: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,613 INFO L290 TraceCheckUtils]: 107: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,613 INFO L290 TraceCheckUtils]: 108: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,613 INFO L290 TraceCheckUtils]: 109: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,613 INFO L290 TraceCheckUtils]: 110: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,614 INFO L290 TraceCheckUtils]: 111: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,614 INFO L290 TraceCheckUtils]: 112: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,614 INFO L290 TraceCheckUtils]: 113: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,614 INFO L290 TraceCheckUtils]: 114: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,615 INFO L290 TraceCheckUtils]: 115: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,615 INFO L290 TraceCheckUtils]: 116: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,615 INFO L290 TraceCheckUtils]: 117: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,616 INFO L290 TraceCheckUtils]: 118: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,616 INFO L290 TraceCheckUtils]: 119: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,616 INFO L290 TraceCheckUtils]: 120: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,616 INFO L290 TraceCheckUtils]: 121: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,617 INFO L290 TraceCheckUtils]: 122: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18199#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:14,617 INFO L290 TraceCheckUtils]: 123: Hoare triple {18199#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {18198#false} is VALID [2022-02-21 04:23:14,617 INFO L290 TraceCheckUtils]: 124: Hoare triple {18198#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,617 INFO L290 TraceCheckUtils]: 125: Hoare triple {18198#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,617 INFO L290 TraceCheckUtils]: 126: Hoare triple {18198#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,618 INFO L290 TraceCheckUtils]: 127: Hoare triple {18198#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,618 INFO L290 TraceCheckUtils]: 128: Hoare triple {18198#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,618 INFO L290 TraceCheckUtils]: 129: Hoare triple {18198#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,618 INFO L290 TraceCheckUtils]: 130: Hoare triple {18198#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,618 INFO L290 TraceCheckUtils]: 131: Hoare triple {18198#false} assume !(1 == ~T8_E~0); {18198#false} is VALID [2022-02-21 04:23:14,618 INFO L290 TraceCheckUtils]: 132: Hoare triple {18198#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,618 INFO L290 TraceCheckUtils]: 133: Hoare triple {18198#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,618 INFO L290 TraceCheckUtils]: 134: Hoare triple {18198#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,618 INFO L290 TraceCheckUtils]: 135: Hoare triple {18198#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,618 INFO L290 TraceCheckUtils]: 136: Hoare triple {18198#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,619 INFO L290 TraceCheckUtils]: 137: Hoare triple {18198#false} assume 1 == ~E_M~0;~E_M~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,619 INFO L290 TraceCheckUtils]: 138: Hoare triple {18198#false} assume 1 == ~E_1~0;~E_1~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,619 INFO L290 TraceCheckUtils]: 139: Hoare triple {18198#false} assume !(1 == ~E_2~0); {18198#false} is VALID [2022-02-21 04:23:14,619 INFO L290 TraceCheckUtils]: 140: Hoare triple {18198#false} assume 1 == ~E_3~0;~E_3~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,619 INFO L290 TraceCheckUtils]: 141: Hoare triple {18198#false} assume 1 == ~E_4~0;~E_4~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,619 INFO L290 TraceCheckUtils]: 142: Hoare triple {18198#false} assume 1 == ~E_5~0;~E_5~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,619 INFO L290 TraceCheckUtils]: 143: Hoare triple {18198#false} assume 1 == ~E_6~0;~E_6~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,619 INFO L290 TraceCheckUtils]: 144: Hoare triple {18198#false} assume 1 == ~E_7~0;~E_7~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,619 INFO L290 TraceCheckUtils]: 145: Hoare triple {18198#false} assume 1 == ~E_8~0;~E_8~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,619 INFO L290 TraceCheckUtils]: 146: Hoare triple {18198#false} assume 1 == ~E_9~0;~E_9~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,620 INFO L290 TraceCheckUtils]: 147: Hoare triple {18198#false} assume !(1 == ~E_10~0); {18198#false} is VALID [2022-02-21 04:23:14,620 INFO L290 TraceCheckUtils]: 148: Hoare triple {18198#false} assume 1 == ~E_11~0;~E_11~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,620 INFO L290 TraceCheckUtils]: 149: Hoare triple {18198#false} assume 1 == ~E_12~0;~E_12~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,620 INFO L290 TraceCheckUtils]: 150: Hoare triple {18198#false} assume 1 == ~E_13~0;~E_13~0 := 2; {18198#false} is VALID [2022-02-21 04:23:14,620 INFO L290 TraceCheckUtils]: 151: Hoare triple {18198#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {18198#false} is VALID [2022-02-21 04:23:14,620 INFO L290 TraceCheckUtils]: 152: Hoare triple {18198#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {18198#false} is VALID [2022-02-21 04:23:14,620 INFO L290 TraceCheckUtils]: 153: Hoare triple {18198#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {18198#false} is VALID [2022-02-21 04:23:14,620 INFO L290 TraceCheckUtils]: 154: Hoare triple {18198#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {18198#false} is VALID [2022-02-21 04:23:14,620 INFO L290 TraceCheckUtils]: 155: Hoare triple {18198#false} assume !(0 == start_simulation_~tmp~3#1); {18198#false} is VALID [2022-02-21 04:23:14,621 INFO L290 TraceCheckUtils]: 156: Hoare triple {18198#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {18198#false} is VALID [2022-02-21 04:23:14,621 INFO L290 TraceCheckUtils]: 157: Hoare triple {18198#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {18198#false} is VALID [2022-02-21 04:23:14,621 INFO L290 TraceCheckUtils]: 158: Hoare triple {18198#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {18198#false} is VALID [2022-02-21 04:23:14,621 INFO L290 TraceCheckUtils]: 159: Hoare triple {18198#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {18198#false} is VALID [2022-02-21 04:23:14,621 INFO L290 TraceCheckUtils]: 160: Hoare triple {18198#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {18198#false} is VALID [2022-02-21 04:23:14,621 INFO L290 TraceCheckUtils]: 161: Hoare triple {18198#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {18198#false} is VALID [2022-02-21 04:23:14,621 INFO L290 TraceCheckUtils]: 162: Hoare triple {18198#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {18198#false} is VALID [2022-02-21 04:23:14,621 INFO L290 TraceCheckUtils]: 163: Hoare triple {18198#false} assume !(0 != start_simulation_~tmp___0~1#1); {18198#false} is VALID [2022-02-21 04:23:14,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:14,622 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:14,622 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717835321] [2022-02-21 04:23:14,622 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [717835321] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:14,622 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:14,622 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:14,623 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [298844365] [2022-02-21 04:23:14,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:14,623 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:14,623 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:14,624 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:14,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:14,625 INFO L87 Difference]: Start difference. First operand 2018 states and 2986 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,108 INFO L93 Difference]: Finished difference Result 2018 states and 2985 transitions. [2022-02-21 04:23:16,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:16,108 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,205 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:16,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2985 transitions. [2022-02-21 04:23:16,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:16,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2985 transitions. [2022-02-21 04:23:16,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:16,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:16,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2985 transitions. [2022-02-21 04:23:16,415 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:16,416 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2022-02-21 04:23:16,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2985 transitions. [2022-02-21 04:23:16,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:16,432 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:16,434 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2985 transitions. Second operand has 2018 states, 2018 states have (on average 1.4791873141724479) internal successors, (2985), 2017 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,436 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2985 transitions. Second operand has 2018 states, 2018 states have (on average 1.4791873141724479) internal successors, (2985), 2017 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,438 INFO L87 Difference]: Start difference. First operand 2018 states and 2985 transitions. Second operand has 2018 states, 2018 states have (on average 1.4791873141724479) internal successors, (2985), 2017 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,521 INFO L93 Difference]: Finished difference Result 2018 states and 2985 transitions. [2022-02-21 04:23:16,521 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2985 transitions. [2022-02-21 04:23:16,524 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:16,524 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:16,527 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.4791873141724479) internal successors, (2985), 2017 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2985 transitions. [2022-02-21 04:23:16,529 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.4791873141724479) internal successors, (2985), 2017 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2985 transitions. [2022-02-21 04:23:16,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,615 INFO L93 Difference]: Finished difference Result 2018 states and 2985 transitions. [2022-02-21 04:23:16,615 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2985 transitions. [2022-02-21 04:23:16,617 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:16,617 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:16,617 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:16,617 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:16,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4791873141724479) internal successors, (2985), 2017 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2985 transitions. [2022-02-21 04:23:16,708 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2022-02-21 04:23:16,708 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2022-02-21 04:23:16,708 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:23:16,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2985 transitions. [2022-02-21 04:23:16,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:16,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:16,714 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:16,716 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:16,716 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:16,716 INFO L791 eck$LassoCheckResult]: Stem: 21133#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 21134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 22170#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21625#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21626#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 21115#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21116#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21182#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 21183#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 21621#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21622#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21148#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20967#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20968#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21412#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21413#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21288#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21289#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 20938#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20939#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 22162#L1279-2 assume !(0 == ~T1_E~0); 20561#L1284-1 assume !(0 == ~T2_E~0); 20562#L1289-1 assume !(0 == ~T3_E~0); 21285#L1294-1 assume !(0 == ~T4_E~0); 21286#L1299-1 assume !(0 == ~T5_E~0); 21297#L1304-1 assume !(0 == ~T6_E~0); 22228#L1309-1 assume !(0 == ~T7_E~0); 22229#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20491#L1319-1 assume !(0 == ~T9_E~0); 20492#L1324-1 assume !(0 == ~T10_E~0); 20664#L1329-1 assume !(0 == ~T11_E~0); 20665#L1334-1 assume !(0 == ~T12_E~0); 22069#L1339-1 assume !(0 == ~T13_E~0); 22150#L1344-1 assume !(0 == ~E_M~0); 22151#L1349-1 assume !(0 == ~E_1~0); 21472#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 21473#L1359-1 assume !(0 == ~E_3~0); 21902#L1364-1 assume !(0 == ~E_4~0); 20793#L1369-1 assume !(0 == ~E_5~0); 20794#L1374-1 assume !(0 == ~E_6~0); 21477#L1379-1 assume !(0 == ~E_7~0); 21478#L1384-1 assume !(0 == ~E_8~0); 21555#L1389-1 assume !(0 == ~E_9~0); 22088#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 22089#L1399-1 assume !(0 == ~E_11~0); 22192#L1404-1 assume !(0 == ~E_12~0); 20886#L1409-1 assume !(0 == ~E_13~0); 20887#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22184#L628 assume !(1 == ~m_pc~0); 20790#L628-2 is_master_triggered_~__retres1~0#1 := 0; 20789#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21553#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21554#L1591 assume !(0 != activate_threads_~tmp~1#1); 22197#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21341#L647 assume 1 == ~t1_pc~0; 20710#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20711#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20982#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20983#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 22137#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22138#L666 assume 1 == ~t2_pc~0; 20558#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20559#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20725#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22154#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 21673#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21674#L685 assume !(1 == ~t3_pc~0); 21779#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21778#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21401#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21402#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21523#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21009#L704 assume 1 == ~t4_pc~0; 21010#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21534#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21535#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22175#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 21394#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21395#L723 assume !(1 == ~t5_pc~0); 21517#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21753#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21897#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21652#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 21653#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20775#L742 assume 1 == ~t6_pc~0; 20776#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20924#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20925#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20460#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 20461#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20852#L761 assume !(1 == ~t7_pc~0); 20853#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20721#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20722#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21524#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 21525#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20485#L780 assume 1 == ~t8_pc~0; 20486#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20761#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20762#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21485#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 21486#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21605#L799 assume 1 == ~t9_pc~0; 21717#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20488#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20489#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21617#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 21824#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21635#L818 assume !(1 == ~t10_pc~0); 20269#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20270#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21710#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21639#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21640#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21680#L837 assume 1 == ~t11_pc~0; 21681#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21515#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21918#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21598#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 21599#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21350#L856 assume !(1 == ~t12_pc~0); 21351#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22004#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22005#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21985#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 21986#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22165#L875 assume 1 == ~t13_pc~0; 21295#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20927#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20928#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20867#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 20868#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21707#L1427 assume !(1 == ~M_E~0); 21691#L1427-2 assume !(1 == ~T1_E~0); 20839#L1432-1 assume !(1 == ~T2_E~0); 20840#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21908#L1442-1 assume !(1 == ~T4_E~0); 21909#L1447-1 assume !(1 == ~T5_E~0); 21764#L1452-1 assume !(1 == ~T6_E~0); 20404#L1457-1 assume !(1 == ~T7_E~0); 20405#L1462-1 assume !(1 == ~T8_E~0); 21935#L1467-1 assume !(1 == ~T9_E~0); 21953#L1472-1 assume !(1 == ~T10_E~0); 21954#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21705#L1482-1 assume !(1 == ~T12_E~0); 21706#L1487-1 assume !(1 == ~T13_E~0); 20735#L1492-1 assume !(1 == ~E_M~0); 20736#L1497-1 assume !(1 == ~E_1~0); 21097#L1502-1 assume !(1 == ~E_2~0); 21098#L1507-1 assume !(1 == ~E_3~0); 20613#L1512-1 assume !(1 == ~E_4~0); 20614#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22024#L1522-1 assume !(1 == ~E_6~0); 21338#L1527-1 assume !(1 == ~E_7~0); 21339#L1532-1 assume !(1 == ~E_8~0); 22212#L1537-1 assume !(1 == ~E_9~0); 21541#L1542-1 assume !(1 == ~E_10~0); 21372#L1547-1 assume !(1 == ~E_11~0); 21373#L1552-1 assume !(1 == ~E_12~0); 20308#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 20309#L1562-1 assume { :end_inline_reset_delta_events } true; 20915#L1928-2 [2022-02-21 04:23:16,717 INFO L793 eck$LassoCheckResult]: Loop: 20915#L1928-2 assume !false; 21406#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20569#L1254 assume !false; 21156#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20643#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20644#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20841#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22012#L1067 assume !(0 != eval_~tmp~0#1); 21082#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20659#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20660#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21119#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21101#L1284-3 assume !(0 == ~T2_E~0); 21102#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21080#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21081#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21468#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21469#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20978#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20979#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21975#L1324-3 assume !(0 == ~T10_E~0); 20610#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20611#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21378#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21379#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21677#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20959#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20960#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21688#L1364-3 assume !(0 == ~E_4~0); 22210#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22106#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20739#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20740#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20957#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20958#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21248#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22116#L1404-3 assume !(0 == ~E_12~0); 22080#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22081#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21567#L628-45 assume 1 == ~m_pc~0; 21245#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21247#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20604#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20605#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20993#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21716#L647-45 assume 1 == ~t1_pc~0; 20555#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20556#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21484#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20669#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20670#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20881#L666-45 assume !(1 == ~t2_pc~0); 20882#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21363#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21925#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21840#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21834#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20419#L685-45 assume 1 == ~t3_pc~0; 20420#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21479#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22153#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22022#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22023#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22163#L704-45 assume 1 == ~t4_pc~0; 22042#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20286#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21145#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21488#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22235#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21600#L723-45 assume !(1 == ~t5_pc~0); 21601#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 22090#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21192#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20969#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 20970#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21994#L742-45 assume !(1 == ~t6_pc~0); 21216#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 21217#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21686#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21722#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21723#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21811#L761-45 assume !(1 == ~t7_pc~0); 21812#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 21210#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21211#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20617#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20618#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22084#L780-45 assume 1 == ~t8_pc~0; 20995#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20629#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20630#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22211#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20599#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20600#L799-45 assume 1 == ~t9_pc~0; 21376#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20821#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22136#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21765#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21766#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20537#L818-45 assume 1 == ~t10_pc~0; 20538#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20656#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21739#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21143#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21144#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21859#L837-45 assume !(1 == ~t11_pc~0); 21074#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 21075#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21212#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21877#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20675#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20676#L856-45 assume 1 == ~t12_pc~0; 22161#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20678#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20619#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20620#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21482#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21483#L875-45 assume 1 == ~t13_pc~0; 21453#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21454#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21516#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22128#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22129#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22068#L1427-3 assume !(1 == ~M_E~0); 21279#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21280#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21818#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21470#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21471#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20327#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20328#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22010#L1462-3 assume !(1 == ~T8_E~0); 22011#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21874#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21875#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20578#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20579#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 20720#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20893#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20894#L1502-3 assume !(1 == ~E_2~0); 21842#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21973#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20931#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20623#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20624#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20588#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20589#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21689#L1542-3 assume !(1 == ~E_10~0); 21827#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21456#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21457#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20799#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20800#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20219#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20984#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 20985#L1947 assume !(0 == start_simulation_~tmp~3#1); 21590#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21795#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20856#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 22188#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 22112#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21942#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21701#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 21702#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 20915#L1928-2 [2022-02-21 04:23:16,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:16,718 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2022-02-21 04:23:16,718 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:16,718 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [769935633] [2022-02-21 04:23:16,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:16,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:16,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:16,742 INFO L290 TraceCheckUtils]: 0: Hoare triple {26275#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {26275#true} is VALID [2022-02-21 04:23:16,742 INFO L290 TraceCheckUtils]: 1: Hoare triple {26275#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {26277#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:16,742 INFO L290 TraceCheckUtils]: 2: Hoare triple {26277#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {26277#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 3: Hoare triple {26277#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {26277#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 4: Hoare triple {26277#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {26277#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 5: Hoare triple {26277#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {26277#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 6: Hoare triple {26277#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {26277#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 7: Hoare triple {26277#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 8: Hoare triple {26276#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 9: Hoare triple {26276#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 10: Hoare triple {26276#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 11: Hoare triple {26276#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 12: Hoare triple {26276#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 13: Hoare triple {26276#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {26276#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 14: Hoare triple {26276#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 15: Hoare triple {26276#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 16: Hoare triple {26276#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 17: Hoare triple {26276#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 18: Hoare triple {26276#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {26276#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 19: Hoare triple {26276#false} assume 0 == ~M_E~0;~M_E~0 := 1; {26276#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 20: Hoare triple {26276#false} assume !(0 == ~T1_E~0); {26276#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 21: Hoare triple {26276#false} assume !(0 == ~T2_E~0); {26276#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 22: Hoare triple {26276#false} assume !(0 == ~T3_E~0); {26276#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 23: Hoare triple {26276#false} assume !(0 == ~T4_E~0); {26276#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 24: Hoare triple {26276#false} assume !(0 == ~T5_E~0); {26276#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 25: Hoare triple {26276#false} assume !(0 == ~T6_E~0); {26276#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 26: Hoare triple {26276#false} assume !(0 == ~T7_E~0); {26276#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 27: Hoare triple {26276#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {26276#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 28: Hoare triple {26276#false} assume !(0 == ~T9_E~0); {26276#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 29: Hoare triple {26276#false} assume !(0 == ~T10_E~0); {26276#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 30: Hoare triple {26276#false} assume !(0 == ~T11_E~0); {26276#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 31: Hoare triple {26276#false} assume !(0 == ~T12_E~0); {26276#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 32: Hoare triple {26276#false} assume !(0 == ~T13_E~0); {26276#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 33: Hoare triple {26276#false} assume !(0 == ~E_M~0); {26276#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 34: Hoare triple {26276#false} assume !(0 == ~E_1~0); {26276#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 35: Hoare triple {26276#false} assume 0 == ~E_2~0;~E_2~0 := 1; {26276#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 36: Hoare triple {26276#false} assume !(0 == ~E_3~0); {26276#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 37: Hoare triple {26276#false} assume !(0 == ~E_4~0); {26276#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 38: Hoare triple {26276#false} assume !(0 == ~E_5~0); {26276#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 39: Hoare triple {26276#false} assume !(0 == ~E_6~0); {26276#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 40: Hoare triple {26276#false} assume !(0 == ~E_7~0); {26276#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 41: Hoare triple {26276#false} assume !(0 == ~E_8~0); {26276#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 42: Hoare triple {26276#false} assume !(0 == ~E_9~0); {26276#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 43: Hoare triple {26276#false} assume 0 == ~E_10~0;~E_10~0 := 1; {26276#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 44: Hoare triple {26276#false} assume !(0 == ~E_11~0); {26276#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 45: Hoare triple {26276#false} assume !(0 == ~E_12~0); {26276#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 46: Hoare triple {26276#false} assume !(0 == ~E_13~0); {26276#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 47: Hoare triple {26276#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26276#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 48: Hoare triple {26276#false} assume !(1 == ~m_pc~0); {26276#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 49: Hoare triple {26276#false} is_master_triggered_~__retres1~0#1 := 0; {26276#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 50: Hoare triple {26276#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26276#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 51: Hoare triple {26276#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {26276#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 52: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp~1#1); {26276#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 53: Hoare triple {26276#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26276#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 54: Hoare triple {26276#false} assume 1 == ~t1_pc~0; {26276#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 55: Hoare triple {26276#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {26276#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 56: Hoare triple {26276#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26276#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 57: Hoare triple {26276#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26276#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 58: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___0~0#1); {26276#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 59: Hoare triple {26276#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26276#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 60: Hoare triple {26276#false} assume 1 == ~t2_pc~0; {26276#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 61: Hoare triple {26276#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26276#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 62: Hoare triple {26276#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26276#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 63: Hoare triple {26276#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26276#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 64: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___1~0#1); {26276#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 65: Hoare triple {26276#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26276#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 66: Hoare triple {26276#false} assume !(1 == ~t3_pc~0); {26276#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 67: Hoare triple {26276#false} is_transmit3_triggered_~__retres1~3#1 := 0; {26276#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 68: Hoare triple {26276#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26276#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 69: Hoare triple {26276#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26276#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 70: Hoare triple {26276#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26276#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 71: Hoare triple {26276#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26276#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 72: Hoare triple {26276#false} assume 1 == ~t4_pc~0; {26276#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 73: Hoare triple {26276#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26276#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 74: Hoare triple {26276#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26276#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 75: Hoare triple {26276#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26276#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 76: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___3~0#1); {26276#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 77: Hoare triple {26276#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26276#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 78: Hoare triple {26276#false} assume !(1 == ~t5_pc~0); {26276#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 79: Hoare triple {26276#false} is_transmit5_triggered_~__retres1~5#1 := 0; {26276#false} is VALID [2022-02-21 04:23:16,752 INFO L290 TraceCheckUtils]: 80: Hoare triple {26276#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26276#false} is VALID [2022-02-21 04:23:16,752 INFO L290 TraceCheckUtils]: 81: Hoare triple {26276#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26276#false} is VALID [2022-02-21 04:23:16,752 INFO L290 TraceCheckUtils]: 82: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___4~0#1); {26276#false} is VALID [2022-02-21 04:23:16,752 INFO L290 TraceCheckUtils]: 83: Hoare triple {26276#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26276#false} is VALID [2022-02-21 04:23:16,752 INFO L290 TraceCheckUtils]: 84: Hoare triple {26276#false} assume 1 == ~t6_pc~0; {26276#false} is VALID [2022-02-21 04:23:16,752 INFO L290 TraceCheckUtils]: 85: Hoare triple {26276#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {26276#false} is VALID [2022-02-21 04:23:16,752 INFO L290 TraceCheckUtils]: 86: Hoare triple {26276#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26276#false} is VALID [2022-02-21 04:23:16,752 INFO L290 TraceCheckUtils]: 87: Hoare triple {26276#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26276#false} is VALID [2022-02-21 04:23:16,752 INFO L290 TraceCheckUtils]: 88: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___5~0#1); {26276#false} is VALID [2022-02-21 04:23:16,752 INFO L290 TraceCheckUtils]: 89: Hoare triple {26276#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26276#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 90: Hoare triple {26276#false} assume !(1 == ~t7_pc~0); {26276#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 91: Hoare triple {26276#false} is_transmit7_triggered_~__retres1~7#1 := 0; {26276#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 92: Hoare triple {26276#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26276#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 93: Hoare triple {26276#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {26276#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 94: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___6~0#1); {26276#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 95: Hoare triple {26276#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26276#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 96: Hoare triple {26276#false} assume 1 == ~t8_pc~0; {26276#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 97: Hoare triple {26276#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {26276#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 98: Hoare triple {26276#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26276#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 99: Hoare triple {26276#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {26276#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 100: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___7~0#1); {26276#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 101: Hoare triple {26276#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26276#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 102: Hoare triple {26276#false} assume 1 == ~t9_pc~0; {26276#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 103: Hoare triple {26276#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26276#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 104: Hoare triple {26276#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26276#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 105: Hoare triple {26276#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {26276#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 106: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___8~0#1); {26276#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 107: Hoare triple {26276#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26276#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 108: Hoare triple {26276#false} assume !(1 == ~t10_pc~0); {26276#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 109: Hoare triple {26276#false} is_transmit10_triggered_~__retres1~10#1 := 0; {26276#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 110: Hoare triple {26276#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26276#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 111: Hoare triple {26276#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {26276#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 112: Hoare triple {26276#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {26276#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 113: Hoare triple {26276#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {26276#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 114: Hoare triple {26276#false} assume 1 == ~t11_pc~0; {26276#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 115: Hoare triple {26276#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {26276#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 116: Hoare triple {26276#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {26276#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 117: Hoare triple {26276#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {26276#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 118: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___10~0#1); {26276#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 119: Hoare triple {26276#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {26276#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 120: Hoare triple {26276#false} assume !(1 == ~t12_pc~0); {26276#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 121: Hoare triple {26276#false} is_transmit12_triggered_~__retres1~12#1 := 0; {26276#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 122: Hoare triple {26276#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {26276#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 123: Hoare triple {26276#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {26276#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 124: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___11~0#1); {26276#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 125: Hoare triple {26276#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {26276#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 126: Hoare triple {26276#false} assume 1 == ~t13_pc~0; {26276#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 127: Hoare triple {26276#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {26276#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 128: Hoare triple {26276#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {26276#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 129: Hoare triple {26276#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {26276#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 130: Hoare triple {26276#false} assume !(0 != activate_threads_~tmp___12~0#1); {26276#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 131: Hoare triple {26276#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26276#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 132: Hoare triple {26276#false} assume !(1 == ~M_E~0); {26276#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 133: Hoare triple {26276#false} assume !(1 == ~T1_E~0); {26276#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 134: Hoare triple {26276#false} assume !(1 == ~T2_E~0); {26276#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 135: Hoare triple {26276#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 136: Hoare triple {26276#false} assume !(1 == ~T4_E~0); {26276#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 137: Hoare triple {26276#false} assume !(1 == ~T5_E~0); {26276#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 138: Hoare triple {26276#false} assume !(1 == ~T6_E~0); {26276#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 139: Hoare triple {26276#false} assume !(1 == ~T7_E~0); {26276#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 140: Hoare triple {26276#false} assume !(1 == ~T8_E~0); {26276#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 141: Hoare triple {26276#false} assume !(1 == ~T9_E~0); {26276#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 142: Hoare triple {26276#false} assume !(1 == ~T10_E~0); {26276#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 143: Hoare triple {26276#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 144: Hoare triple {26276#false} assume !(1 == ~T12_E~0); {26276#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 145: Hoare triple {26276#false} assume !(1 == ~T13_E~0); {26276#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 146: Hoare triple {26276#false} assume !(1 == ~E_M~0); {26276#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 147: Hoare triple {26276#false} assume !(1 == ~E_1~0); {26276#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 148: Hoare triple {26276#false} assume !(1 == ~E_2~0); {26276#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 149: Hoare triple {26276#false} assume !(1 == ~E_3~0); {26276#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 150: Hoare triple {26276#false} assume !(1 == ~E_4~0); {26276#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 151: Hoare triple {26276#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 152: Hoare triple {26276#false} assume !(1 == ~E_6~0); {26276#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 153: Hoare triple {26276#false} assume !(1 == ~E_7~0); {26276#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 154: Hoare triple {26276#false} assume !(1 == ~E_8~0); {26276#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 155: Hoare triple {26276#false} assume !(1 == ~E_9~0); {26276#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 156: Hoare triple {26276#false} assume !(1 == ~E_10~0); {26276#false} is VALID [2022-02-21 04:23:16,760 INFO L290 TraceCheckUtils]: 157: Hoare triple {26276#false} assume !(1 == ~E_11~0); {26276#false} is VALID [2022-02-21 04:23:16,760 INFO L290 TraceCheckUtils]: 158: Hoare triple {26276#false} assume !(1 == ~E_12~0); {26276#false} is VALID [2022-02-21 04:23:16,760 INFO L290 TraceCheckUtils]: 159: Hoare triple {26276#false} assume 1 == ~E_13~0;~E_13~0 := 2; {26276#false} is VALID [2022-02-21 04:23:16,760 INFO L290 TraceCheckUtils]: 160: Hoare triple {26276#false} assume { :end_inline_reset_delta_events } true; {26276#false} is VALID [2022-02-21 04:23:16,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:16,760 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:16,761 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [769935633] [2022-02-21 04:23:16,761 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [769935633] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:16,761 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:16,761 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:16,761 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462138012] [2022-02-21 04:23:16,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:16,762 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:16,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:16,762 INFO L85 PathProgramCache]: Analyzing trace with hash -864361555, now seen corresponding path program 1 times [2022-02-21 04:23:16,762 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:16,765 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733583302] [2022-02-21 04:23:16,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:16,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:16,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:16,806 INFO L290 TraceCheckUtils]: 0: Hoare triple {26278#true} assume !false; {26278#true} is VALID [2022-02-21 04:23:16,807 INFO L290 TraceCheckUtils]: 1: Hoare triple {26278#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {26278#true} is VALID [2022-02-21 04:23:16,807 INFO L290 TraceCheckUtils]: 2: Hoare triple {26278#true} assume !false; {26278#true} is VALID [2022-02-21 04:23:16,807 INFO L290 TraceCheckUtils]: 3: Hoare triple {26278#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {26278#true} is VALID [2022-02-21 04:23:16,807 INFO L290 TraceCheckUtils]: 4: Hoare triple {26278#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {26278#true} is VALID [2022-02-21 04:23:16,807 INFO L290 TraceCheckUtils]: 5: Hoare triple {26278#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {26278#true} is VALID [2022-02-21 04:23:16,807 INFO L290 TraceCheckUtils]: 6: Hoare triple {26278#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {26278#true} is VALID [2022-02-21 04:23:16,807 INFO L290 TraceCheckUtils]: 7: Hoare triple {26278#true} assume !(0 != eval_~tmp~0#1); {26278#true} is VALID [2022-02-21 04:23:16,807 INFO L290 TraceCheckUtils]: 8: Hoare triple {26278#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {26278#true} is VALID [2022-02-21 04:23:16,807 INFO L290 TraceCheckUtils]: 9: Hoare triple {26278#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {26278#true} is VALID [2022-02-21 04:23:16,808 INFO L290 TraceCheckUtils]: 10: Hoare triple {26278#true} assume 0 == ~M_E~0;~M_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,808 INFO L290 TraceCheckUtils]: 11: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,808 INFO L290 TraceCheckUtils]: 12: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,809 INFO L290 TraceCheckUtils]: 13: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,809 INFO L290 TraceCheckUtils]: 14: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,809 INFO L290 TraceCheckUtils]: 15: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,809 INFO L290 TraceCheckUtils]: 16: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,810 INFO L290 TraceCheckUtils]: 17: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,810 INFO L290 TraceCheckUtils]: 18: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,810 INFO L290 TraceCheckUtils]: 19: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,810 INFO L290 TraceCheckUtils]: 20: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,811 INFO L290 TraceCheckUtils]: 21: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,811 INFO L290 TraceCheckUtils]: 22: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,811 INFO L290 TraceCheckUtils]: 23: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,811 INFO L290 TraceCheckUtils]: 24: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,812 INFO L290 TraceCheckUtils]: 25: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,812 INFO L290 TraceCheckUtils]: 26: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,812 INFO L290 TraceCheckUtils]: 27: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,813 INFO L290 TraceCheckUtils]: 28: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,813 INFO L290 TraceCheckUtils]: 29: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,813 INFO L290 TraceCheckUtils]: 30: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,813 INFO L290 TraceCheckUtils]: 31: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,814 INFO L290 TraceCheckUtils]: 32: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,814 INFO L290 TraceCheckUtils]: 33: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,814 INFO L290 TraceCheckUtils]: 34: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,814 INFO L290 TraceCheckUtils]: 35: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,815 INFO L290 TraceCheckUtils]: 36: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,815 INFO L290 TraceCheckUtils]: 37: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,815 INFO L290 TraceCheckUtils]: 38: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,816 INFO L290 TraceCheckUtils]: 39: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,816 INFO L290 TraceCheckUtils]: 40: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,816 INFO L290 TraceCheckUtils]: 41: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,816 INFO L290 TraceCheckUtils]: 42: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,817 INFO L290 TraceCheckUtils]: 43: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,817 INFO L290 TraceCheckUtils]: 44: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,817 INFO L290 TraceCheckUtils]: 45: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,817 INFO L290 TraceCheckUtils]: 46: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,818 INFO L290 TraceCheckUtils]: 47: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,818 INFO L290 TraceCheckUtils]: 48: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,818 INFO L290 TraceCheckUtils]: 49: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,819 INFO L290 TraceCheckUtils]: 50: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,819 INFO L290 TraceCheckUtils]: 51: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,819 INFO L290 TraceCheckUtils]: 52: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,819 INFO L290 TraceCheckUtils]: 53: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,820 INFO L290 TraceCheckUtils]: 54: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,820 INFO L290 TraceCheckUtils]: 55: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,820 INFO L290 TraceCheckUtils]: 56: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,820 INFO L290 TraceCheckUtils]: 57: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,821 INFO L290 TraceCheckUtils]: 58: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,821 INFO L290 TraceCheckUtils]: 59: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,821 INFO L290 TraceCheckUtils]: 60: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,821 INFO L290 TraceCheckUtils]: 61: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,822 INFO L290 TraceCheckUtils]: 62: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,822 INFO L290 TraceCheckUtils]: 63: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,822 INFO L290 TraceCheckUtils]: 64: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,823 INFO L290 TraceCheckUtils]: 65: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,823 INFO L290 TraceCheckUtils]: 66: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,823 INFO L290 TraceCheckUtils]: 67: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,823 INFO L290 TraceCheckUtils]: 68: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 69: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 70: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 71: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 72: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,825 INFO L290 TraceCheckUtils]: 73: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,825 INFO L290 TraceCheckUtils]: 74: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,825 INFO L290 TraceCheckUtils]: 75: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,826 INFO L290 TraceCheckUtils]: 76: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,826 INFO L290 TraceCheckUtils]: 77: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,826 INFO L290 TraceCheckUtils]: 78: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,827 INFO L290 TraceCheckUtils]: 79: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,827 INFO L290 TraceCheckUtils]: 80: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,827 INFO L290 TraceCheckUtils]: 81: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,828 INFO L290 TraceCheckUtils]: 82: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,828 INFO L290 TraceCheckUtils]: 83: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,828 INFO L290 TraceCheckUtils]: 84: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,829 INFO L290 TraceCheckUtils]: 85: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,829 INFO L290 TraceCheckUtils]: 86: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,829 INFO L290 TraceCheckUtils]: 87: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,829 INFO L290 TraceCheckUtils]: 88: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,830 INFO L290 TraceCheckUtils]: 89: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,830 INFO L290 TraceCheckUtils]: 90: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,830 INFO L290 TraceCheckUtils]: 91: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,831 INFO L290 TraceCheckUtils]: 92: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,831 INFO L290 TraceCheckUtils]: 93: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,831 INFO L290 TraceCheckUtils]: 94: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,831 INFO L290 TraceCheckUtils]: 95: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,832 INFO L290 TraceCheckUtils]: 96: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,832 INFO L290 TraceCheckUtils]: 97: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,832 INFO L290 TraceCheckUtils]: 98: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,833 INFO L290 TraceCheckUtils]: 99: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,833 INFO L290 TraceCheckUtils]: 100: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,833 INFO L290 TraceCheckUtils]: 101: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,833 INFO L290 TraceCheckUtils]: 102: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,834 INFO L290 TraceCheckUtils]: 103: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,834 INFO L290 TraceCheckUtils]: 104: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,834 INFO L290 TraceCheckUtils]: 105: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,835 INFO L290 TraceCheckUtils]: 106: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,835 INFO L290 TraceCheckUtils]: 107: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,835 INFO L290 TraceCheckUtils]: 108: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,836 INFO L290 TraceCheckUtils]: 109: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,836 INFO L290 TraceCheckUtils]: 110: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,836 INFO L290 TraceCheckUtils]: 111: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,836 INFO L290 TraceCheckUtils]: 112: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,837 INFO L290 TraceCheckUtils]: 113: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,837 INFO L290 TraceCheckUtils]: 114: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,837 INFO L290 TraceCheckUtils]: 115: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,838 INFO L290 TraceCheckUtils]: 116: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,838 INFO L290 TraceCheckUtils]: 117: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,838 INFO L290 TraceCheckUtils]: 118: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,838 INFO L290 TraceCheckUtils]: 119: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,839 INFO L290 TraceCheckUtils]: 120: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,839 INFO L290 TraceCheckUtils]: 121: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,839 INFO L290 TraceCheckUtils]: 122: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26280#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 123: Hoare triple {26280#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {26279#false} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 124: Hoare triple {26279#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 125: Hoare triple {26279#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 126: Hoare triple {26279#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 127: Hoare triple {26279#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 128: Hoare triple {26279#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 129: Hoare triple {26279#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 130: Hoare triple {26279#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 131: Hoare triple {26279#false} assume !(1 == ~T8_E~0); {26279#false} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 132: Hoare triple {26279#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 133: Hoare triple {26279#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 134: Hoare triple {26279#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 135: Hoare triple {26279#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 136: Hoare triple {26279#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 137: Hoare triple {26279#false} assume 1 == ~E_M~0;~E_M~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 138: Hoare triple {26279#false} assume 1 == ~E_1~0;~E_1~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 139: Hoare triple {26279#false} assume !(1 == ~E_2~0); {26279#false} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 140: Hoare triple {26279#false} assume 1 == ~E_3~0;~E_3~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 141: Hoare triple {26279#false} assume 1 == ~E_4~0;~E_4~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 142: Hoare triple {26279#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 143: Hoare triple {26279#false} assume 1 == ~E_6~0;~E_6~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 144: Hoare triple {26279#false} assume 1 == ~E_7~0;~E_7~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 145: Hoare triple {26279#false} assume 1 == ~E_8~0;~E_8~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 146: Hoare triple {26279#false} assume 1 == ~E_9~0;~E_9~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 147: Hoare triple {26279#false} assume !(1 == ~E_10~0); {26279#false} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 148: Hoare triple {26279#false} assume 1 == ~E_11~0;~E_11~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 149: Hoare triple {26279#false} assume 1 == ~E_12~0;~E_12~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 150: Hoare triple {26279#false} assume 1 == ~E_13~0;~E_13~0 := 2; {26279#false} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 151: Hoare triple {26279#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {26279#false} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 152: Hoare triple {26279#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {26279#false} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 153: Hoare triple {26279#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {26279#false} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 154: Hoare triple {26279#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {26279#false} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 155: Hoare triple {26279#false} assume !(0 == start_simulation_~tmp~3#1); {26279#false} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 156: Hoare triple {26279#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {26279#false} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 157: Hoare triple {26279#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {26279#false} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 158: Hoare triple {26279#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {26279#false} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 159: Hoare triple {26279#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {26279#false} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 160: Hoare triple {26279#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {26279#false} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 161: Hoare triple {26279#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {26279#false} is VALID [2022-02-21 04:23:16,844 INFO L290 TraceCheckUtils]: 162: Hoare triple {26279#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {26279#false} is VALID [2022-02-21 04:23:16,844 INFO L290 TraceCheckUtils]: 163: Hoare triple {26279#false} assume !(0 != start_simulation_~tmp___0~1#1); {26279#false} is VALID [2022-02-21 04:23:16,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:16,845 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:16,845 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733583302] [2022-02-21 04:23:16,845 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733583302] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:16,845 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:16,845 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:16,845 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [235589124] [2022-02-21 04:23:16,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:16,846 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:16,846 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:16,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:16,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:16,847 INFO L87 Difference]: Start difference. First operand 2018 states and 2985 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:18,372 INFO L93 Difference]: Finished difference Result 2018 states and 2984 transitions. [2022-02-21 04:23:18,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:18,373 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,435 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:18,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2984 transitions. [2022-02-21 04:23:18,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:18,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2984 transitions. [2022-02-21 04:23:18,668 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:18,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:18,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2984 transitions. [2022-02-21 04:23:18,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:18,671 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2022-02-21 04:23:18,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2984 transitions. [2022-02-21 04:23:18,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:18,697 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:18,700 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2984 transitions. Second operand has 2018 states, 2018 states have (on average 1.4786917740336967) internal successors, (2984), 2017 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,702 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2984 transitions. Second operand has 2018 states, 2018 states have (on average 1.4786917740336967) internal successors, (2984), 2017 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,704 INFO L87 Difference]: Start difference. First operand 2018 states and 2984 transitions. Second operand has 2018 states, 2018 states have (on average 1.4786917740336967) internal successors, (2984), 2017 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:18,790 INFO L93 Difference]: Finished difference Result 2018 states and 2984 transitions. [2022-02-21 04:23:18,790 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2984 transitions. [2022-02-21 04:23:18,792 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:18,792 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:18,795 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.4786917740336967) internal successors, (2984), 2017 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2984 transitions. [2022-02-21 04:23:18,796 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.4786917740336967) internal successors, (2984), 2017 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2984 transitions. [2022-02-21 04:23:18,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:18,881 INFO L93 Difference]: Finished difference Result 2018 states and 2984 transitions. [2022-02-21 04:23:18,881 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2984 transitions. [2022-02-21 04:23:18,882 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:18,882 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:18,882 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:18,882 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:18,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4786917740336967) internal successors, (2984), 2017 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2984 transitions. [2022-02-21 04:23:18,973 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2022-02-21 04:23:18,973 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2022-02-21 04:23:18,973 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:23:18,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2984 transitions. [2022-02-21 04:23:18,978 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:18,978 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:18,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:18,980 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:18,980 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:18,981 INFO L791 eck$LassoCheckResult]: Stem: 29214#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 29215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 30251#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29706#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29707#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 29196#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29197#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29263#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29264#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 29702#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 29703#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 29229#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29048#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29049#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29493#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29494#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29369#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29370#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29019#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29020#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 30243#L1279-2 assume !(0 == ~T1_E~0); 28642#L1284-1 assume !(0 == ~T2_E~0); 28643#L1289-1 assume !(0 == ~T3_E~0); 29366#L1294-1 assume !(0 == ~T4_E~0); 29367#L1299-1 assume !(0 == ~T5_E~0); 29378#L1304-1 assume !(0 == ~T6_E~0); 30309#L1309-1 assume !(0 == ~T7_E~0); 30310#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28572#L1319-1 assume !(0 == ~T9_E~0); 28573#L1324-1 assume !(0 == ~T10_E~0); 28745#L1329-1 assume !(0 == ~T11_E~0); 28746#L1334-1 assume !(0 == ~T12_E~0); 30150#L1339-1 assume !(0 == ~T13_E~0); 30231#L1344-1 assume !(0 == ~E_M~0); 30232#L1349-1 assume !(0 == ~E_1~0); 29553#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29554#L1359-1 assume !(0 == ~E_3~0); 29983#L1364-1 assume !(0 == ~E_4~0); 28874#L1369-1 assume !(0 == ~E_5~0); 28875#L1374-1 assume !(0 == ~E_6~0); 29558#L1379-1 assume !(0 == ~E_7~0); 29559#L1384-1 assume !(0 == ~E_8~0); 29636#L1389-1 assume !(0 == ~E_9~0); 30169#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 30170#L1399-1 assume !(0 == ~E_11~0); 30273#L1404-1 assume !(0 == ~E_12~0); 28967#L1409-1 assume !(0 == ~E_13~0); 28968#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30265#L628 assume !(1 == ~m_pc~0); 28871#L628-2 is_master_triggered_~__retres1~0#1 := 0; 28870#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29634#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29635#L1591 assume !(0 != activate_threads_~tmp~1#1); 30278#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29422#L647 assume 1 == ~t1_pc~0; 28791#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28792#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29063#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29064#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 30218#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30219#L666 assume 1 == ~t2_pc~0; 28639#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28640#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28806#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30235#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 29754#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29755#L685 assume !(1 == ~t3_pc~0); 29860#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29859#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29482#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29483#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29604#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29090#L704 assume 1 == ~t4_pc~0; 29091#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29615#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29616#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30256#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 29475#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29476#L723 assume !(1 == ~t5_pc~0); 29598#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29834#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29978#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29733#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 29734#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28856#L742 assume 1 == ~t6_pc~0; 28857#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29005#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29006#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28541#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 28542#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28933#L761 assume !(1 == ~t7_pc~0); 28934#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28802#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28803#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29605#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 29606#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28566#L780 assume 1 == ~t8_pc~0; 28567#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28842#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28843#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29566#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 29567#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29686#L799 assume 1 == ~t9_pc~0; 29798#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28569#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28570#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29698#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 29905#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29716#L818 assume !(1 == ~t10_pc~0); 28350#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28351#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29791#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29720#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29721#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29761#L837 assume 1 == ~t11_pc~0; 29762#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29596#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29999#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29679#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 29680#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29431#L856 assume !(1 == ~t12_pc~0); 29432#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 30085#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30086#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30066#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 30067#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30246#L875 assume 1 == ~t13_pc~0; 29376#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29008#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29009#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28948#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 28949#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29788#L1427 assume !(1 == ~M_E~0); 29772#L1427-2 assume !(1 == ~T1_E~0); 28920#L1432-1 assume !(1 == ~T2_E~0); 28921#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29989#L1442-1 assume !(1 == ~T4_E~0); 29990#L1447-1 assume !(1 == ~T5_E~0); 29845#L1452-1 assume !(1 == ~T6_E~0); 28485#L1457-1 assume !(1 == ~T7_E~0); 28486#L1462-1 assume !(1 == ~T8_E~0); 30016#L1467-1 assume !(1 == ~T9_E~0); 30034#L1472-1 assume !(1 == ~T10_E~0); 30035#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29786#L1482-1 assume !(1 == ~T12_E~0); 29787#L1487-1 assume !(1 == ~T13_E~0); 28816#L1492-1 assume !(1 == ~E_M~0); 28817#L1497-1 assume !(1 == ~E_1~0); 29178#L1502-1 assume !(1 == ~E_2~0); 29179#L1507-1 assume !(1 == ~E_3~0); 28694#L1512-1 assume !(1 == ~E_4~0); 28695#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30105#L1522-1 assume !(1 == ~E_6~0); 29419#L1527-1 assume !(1 == ~E_7~0); 29420#L1532-1 assume !(1 == ~E_8~0); 30293#L1537-1 assume !(1 == ~E_9~0); 29622#L1542-1 assume !(1 == ~E_10~0); 29453#L1547-1 assume !(1 == ~E_11~0); 29454#L1552-1 assume !(1 == ~E_12~0); 28389#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 28390#L1562-1 assume { :end_inline_reset_delta_events } true; 28996#L1928-2 [2022-02-21 04:23:18,981 INFO L793 eck$LassoCheckResult]: Loop: 28996#L1928-2 assume !false; 29487#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28650#L1254 assume !false; 29237#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28724#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28725#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28922#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30093#L1067 assume !(0 != eval_~tmp~0#1); 29163#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28740#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28741#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29200#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29182#L1284-3 assume !(0 == ~T2_E~0); 29183#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29161#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29162#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29549#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29550#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29059#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29060#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30056#L1324-3 assume !(0 == ~T10_E~0); 28691#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28692#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29459#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29460#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29758#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29040#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29041#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29769#L1364-3 assume !(0 == ~E_4~0); 30291#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30187#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28820#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28821#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29038#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29039#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29329#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30197#L1404-3 assume !(0 == ~E_12~0); 30161#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30162#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29648#L628-45 assume 1 == ~m_pc~0; 29326#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29328#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28685#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28686#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29074#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29797#L647-45 assume 1 == ~t1_pc~0; 28636#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28637#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29565#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28750#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28751#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28962#L666-45 assume !(1 == ~t2_pc~0); 28963#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29444#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30006#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29921#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29915#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28500#L685-45 assume 1 == ~t3_pc~0; 28501#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29560#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30234#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30103#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30104#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30244#L704-45 assume 1 == ~t4_pc~0; 30123#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28367#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29226#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29569#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30316#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29681#L723-45 assume !(1 == ~t5_pc~0); 29682#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 30171#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29273#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29050#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 29051#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30075#L742-45 assume !(1 == ~t6_pc~0); 29297#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 29298#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29767#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29803#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29804#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29892#L761-45 assume !(1 == ~t7_pc~0); 29893#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 29291#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29292#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28698#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28699#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30165#L780-45 assume 1 == ~t8_pc~0; 29076#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28710#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28711#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30292#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28680#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28681#L799-45 assume 1 == ~t9_pc~0; 29457#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28902#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30217#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29846#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29847#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28618#L818-45 assume 1 == ~t10_pc~0; 28619#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28737#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29820#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29224#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29225#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29940#L837-45 assume !(1 == ~t11_pc~0); 29155#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29156#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29293#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29958#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28756#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28757#L856-45 assume 1 == ~t12_pc~0; 30242#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28759#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28700#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28701#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29563#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29564#L875-45 assume !(1 == ~t13_pc~0); 29536#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 29535#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29597#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30209#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30210#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30149#L1427-3 assume !(1 == ~M_E~0); 29360#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29361#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29899#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29551#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29552#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28408#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28409#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30091#L1462-3 assume !(1 == ~T8_E~0); 30092#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29955#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29956#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28659#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28660#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 28801#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28974#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28975#L1502-3 assume !(1 == ~E_2~0); 29923#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30054#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29012#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28704#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28705#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28669#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28670#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29770#L1542-3 assume !(1 == ~E_10~0); 29908#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29537#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29538#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 28880#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28881#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28300#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29065#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29066#L1947 assume !(0 == start_simulation_~tmp~3#1); 29671#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29876#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28937#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30269#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 30193#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30023#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29782#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29783#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 28996#L1928-2 [2022-02-21 04:23:18,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:18,982 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2022-02-21 04:23:18,982 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:18,982 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488758945] [2022-02-21 04:23:18,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:18,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:18,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:19,010 INFO L290 TraceCheckUtils]: 0: Hoare triple {34356#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {34356#true} is VALID [2022-02-21 04:23:19,010 INFO L290 TraceCheckUtils]: 1: Hoare triple {34356#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {34358#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:19,010 INFO L290 TraceCheckUtils]: 2: Hoare triple {34358#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {34358#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:19,011 INFO L290 TraceCheckUtils]: 3: Hoare triple {34358#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {34358#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:19,011 INFO L290 TraceCheckUtils]: 4: Hoare triple {34358#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {34358#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:19,011 INFO L290 TraceCheckUtils]: 5: Hoare triple {34358#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {34358#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:19,011 INFO L290 TraceCheckUtils]: 6: Hoare triple {34358#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {34358#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:19,012 INFO L290 TraceCheckUtils]: 7: Hoare triple {34358#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {34358#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:19,012 INFO L290 TraceCheckUtils]: 8: Hoare triple {34358#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,012 INFO L290 TraceCheckUtils]: 9: Hoare triple {34357#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,012 INFO L290 TraceCheckUtils]: 10: Hoare triple {34357#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,012 INFO L290 TraceCheckUtils]: 11: Hoare triple {34357#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,012 INFO L290 TraceCheckUtils]: 12: Hoare triple {34357#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,012 INFO L290 TraceCheckUtils]: 13: Hoare triple {34357#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {34357#false} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 14: Hoare triple {34357#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 15: Hoare triple {34357#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 16: Hoare triple {34357#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 17: Hoare triple {34357#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 18: Hoare triple {34357#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {34357#false} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 19: Hoare triple {34357#false} assume 0 == ~M_E~0;~M_E~0 := 1; {34357#false} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 20: Hoare triple {34357#false} assume !(0 == ~T1_E~0); {34357#false} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 21: Hoare triple {34357#false} assume !(0 == ~T2_E~0); {34357#false} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 22: Hoare triple {34357#false} assume !(0 == ~T3_E~0); {34357#false} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 23: Hoare triple {34357#false} assume !(0 == ~T4_E~0); {34357#false} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 24: Hoare triple {34357#false} assume !(0 == ~T5_E~0); {34357#false} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 25: Hoare triple {34357#false} assume !(0 == ~T6_E~0); {34357#false} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 26: Hoare triple {34357#false} assume !(0 == ~T7_E~0); {34357#false} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 27: Hoare triple {34357#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {34357#false} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 28: Hoare triple {34357#false} assume !(0 == ~T9_E~0); {34357#false} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 29: Hoare triple {34357#false} assume !(0 == ~T10_E~0); {34357#false} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 30: Hoare triple {34357#false} assume !(0 == ~T11_E~0); {34357#false} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 31: Hoare triple {34357#false} assume !(0 == ~T12_E~0); {34357#false} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 32: Hoare triple {34357#false} assume !(0 == ~T13_E~0); {34357#false} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 33: Hoare triple {34357#false} assume !(0 == ~E_M~0); {34357#false} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 34: Hoare triple {34357#false} assume !(0 == ~E_1~0); {34357#false} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 35: Hoare triple {34357#false} assume 0 == ~E_2~0;~E_2~0 := 1; {34357#false} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 36: Hoare triple {34357#false} assume !(0 == ~E_3~0); {34357#false} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 37: Hoare triple {34357#false} assume !(0 == ~E_4~0); {34357#false} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 38: Hoare triple {34357#false} assume !(0 == ~E_5~0); {34357#false} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 39: Hoare triple {34357#false} assume !(0 == ~E_6~0); {34357#false} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 40: Hoare triple {34357#false} assume !(0 == ~E_7~0); {34357#false} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 41: Hoare triple {34357#false} assume !(0 == ~E_8~0); {34357#false} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 42: Hoare triple {34357#false} assume !(0 == ~E_9~0); {34357#false} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 43: Hoare triple {34357#false} assume 0 == ~E_10~0;~E_10~0 := 1; {34357#false} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 44: Hoare triple {34357#false} assume !(0 == ~E_11~0); {34357#false} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 45: Hoare triple {34357#false} assume !(0 == ~E_12~0); {34357#false} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 46: Hoare triple {34357#false} assume !(0 == ~E_13~0); {34357#false} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 47: Hoare triple {34357#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34357#false} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 48: Hoare triple {34357#false} assume !(1 == ~m_pc~0); {34357#false} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 49: Hoare triple {34357#false} is_master_triggered_~__retres1~0#1 := 0; {34357#false} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 50: Hoare triple {34357#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34357#false} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 51: Hoare triple {34357#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34357#false} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 52: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp~1#1); {34357#false} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 53: Hoare triple {34357#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34357#false} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 54: Hoare triple {34357#false} assume 1 == ~t1_pc~0; {34357#false} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 55: Hoare triple {34357#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34357#false} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 56: Hoare triple {34357#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34357#false} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 57: Hoare triple {34357#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34357#false} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 58: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___0~0#1); {34357#false} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 59: Hoare triple {34357#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34357#false} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 60: Hoare triple {34357#false} assume 1 == ~t2_pc~0; {34357#false} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 61: Hoare triple {34357#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34357#false} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 62: Hoare triple {34357#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34357#false} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 63: Hoare triple {34357#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34357#false} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 64: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___1~0#1); {34357#false} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 65: Hoare triple {34357#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34357#false} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 66: Hoare triple {34357#false} assume !(1 == ~t3_pc~0); {34357#false} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 67: Hoare triple {34357#false} is_transmit3_triggered_~__retres1~3#1 := 0; {34357#false} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 68: Hoare triple {34357#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34357#false} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 69: Hoare triple {34357#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34357#false} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 70: Hoare triple {34357#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34357#false} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 71: Hoare triple {34357#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34357#false} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 72: Hoare triple {34357#false} assume 1 == ~t4_pc~0; {34357#false} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 73: Hoare triple {34357#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34357#false} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 74: Hoare triple {34357#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34357#false} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 75: Hoare triple {34357#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34357#false} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 76: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___3~0#1); {34357#false} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 77: Hoare triple {34357#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34357#false} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 78: Hoare triple {34357#false} assume !(1 == ~t5_pc~0); {34357#false} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 79: Hoare triple {34357#false} is_transmit5_triggered_~__retres1~5#1 := 0; {34357#false} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 80: Hoare triple {34357#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34357#false} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 81: Hoare triple {34357#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34357#false} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 82: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___4~0#1); {34357#false} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 83: Hoare triple {34357#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34357#false} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 84: Hoare triple {34357#false} assume 1 == ~t6_pc~0; {34357#false} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 85: Hoare triple {34357#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {34357#false} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 86: Hoare triple {34357#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34357#false} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 87: Hoare triple {34357#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34357#false} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 88: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___5~0#1); {34357#false} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 89: Hoare triple {34357#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34357#false} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 90: Hoare triple {34357#false} assume !(1 == ~t7_pc~0); {34357#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 91: Hoare triple {34357#false} is_transmit7_triggered_~__retres1~7#1 := 0; {34357#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 92: Hoare triple {34357#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34357#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 93: Hoare triple {34357#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34357#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 94: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___6~0#1); {34357#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 95: Hoare triple {34357#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34357#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 96: Hoare triple {34357#false} assume 1 == ~t8_pc~0; {34357#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 97: Hoare triple {34357#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {34357#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 98: Hoare triple {34357#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34357#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 99: Hoare triple {34357#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {34357#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 100: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___7~0#1); {34357#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 101: Hoare triple {34357#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34357#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 102: Hoare triple {34357#false} assume 1 == ~t9_pc~0; {34357#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 103: Hoare triple {34357#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {34357#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 104: Hoare triple {34357#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34357#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 105: Hoare triple {34357#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {34357#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 106: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___8~0#1); {34357#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 107: Hoare triple {34357#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34357#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 108: Hoare triple {34357#false} assume !(1 == ~t10_pc~0); {34357#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 109: Hoare triple {34357#false} is_transmit10_triggered_~__retres1~10#1 := 0; {34357#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 110: Hoare triple {34357#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34357#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 111: Hoare triple {34357#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {34357#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 112: Hoare triple {34357#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {34357#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 113: Hoare triple {34357#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {34357#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 114: Hoare triple {34357#false} assume 1 == ~t11_pc~0; {34357#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 115: Hoare triple {34357#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {34357#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 116: Hoare triple {34357#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {34357#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 117: Hoare triple {34357#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {34357#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 118: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___10~0#1); {34357#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 119: Hoare triple {34357#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {34357#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 120: Hoare triple {34357#false} assume !(1 == ~t12_pc~0); {34357#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 121: Hoare triple {34357#false} is_transmit12_triggered_~__retres1~12#1 := 0; {34357#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 122: Hoare triple {34357#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {34357#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 123: Hoare triple {34357#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {34357#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 124: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___11~0#1); {34357#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 125: Hoare triple {34357#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {34357#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 126: Hoare triple {34357#false} assume 1 == ~t13_pc~0; {34357#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 127: Hoare triple {34357#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {34357#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 128: Hoare triple {34357#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {34357#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 129: Hoare triple {34357#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {34357#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 130: Hoare triple {34357#false} assume !(0 != activate_threads_~tmp___12~0#1); {34357#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 131: Hoare triple {34357#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34357#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 132: Hoare triple {34357#false} assume !(1 == ~M_E~0); {34357#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 133: Hoare triple {34357#false} assume !(1 == ~T1_E~0); {34357#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 134: Hoare triple {34357#false} assume !(1 == ~T2_E~0); {34357#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 135: Hoare triple {34357#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 136: Hoare triple {34357#false} assume !(1 == ~T4_E~0); {34357#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 137: Hoare triple {34357#false} assume !(1 == ~T5_E~0); {34357#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 138: Hoare triple {34357#false} assume !(1 == ~T6_E~0); {34357#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 139: Hoare triple {34357#false} assume !(1 == ~T7_E~0); {34357#false} is VALID [2022-02-21 04:23:19,026 INFO L290 TraceCheckUtils]: 140: Hoare triple {34357#false} assume !(1 == ~T8_E~0); {34357#false} is VALID [2022-02-21 04:23:19,026 INFO L290 TraceCheckUtils]: 141: Hoare triple {34357#false} assume !(1 == ~T9_E~0); {34357#false} is VALID [2022-02-21 04:23:19,026 INFO L290 TraceCheckUtils]: 142: Hoare triple {34357#false} assume !(1 == ~T10_E~0); {34357#false} is VALID [2022-02-21 04:23:19,026 INFO L290 TraceCheckUtils]: 143: Hoare triple {34357#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,026 INFO L290 TraceCheckUtils]: 144: Hoare triple {34357#false} assume !(1 == ~T12_E~0); {34357#false} is VALID [2022-02-21 04:23:19,026 INFO L290 TraceCheckUtils]: 145: Hoare triple {34357#false} assume !(1 == ~T13_E~0); {34357#false} is VALID [2022-02-21 04:23:19,026 INFO L290 TraceCheckUtils]: 146: Hoare triple {34357#false} assume !(1 == ~E_M~0); {34357#false} is VALID [2022-02-21 04:23:19,026 INFO L290 TraceCheckUtils]: 147: Hoare triple {34357#false} assume !(1 == ~E_1~0); {34357#false} is VALID [2022-02-21 04:23:19,026 INFO L290 TraceCheckUtils]: 148: Hoare triple {34357#false} assume !(1 == ~E_2~0); {34357#false} is VALID [2022-02-21 04:23:19,026 INFO L290 TraceCheckUtils]: 149: Hoare triple {34357#false} assume !(1 == ~E_3~0); {34357#false} is VALID [2022-02-21 04:23:19,027 INFO L290 TraceCheckUtils]: 150: Hoare triple {34357#false} assume !(1 == ~E_4~0); {34357#false} is VALID [2022-02-21 04:23:19,027 INFO L290 TraceCheckUtils]: 151: Hoare triple {34357#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,027 INFO L290 TraceCheckUtils]: 152: Hoare triple {34357#false} assume !(1 == ~E_6~0); {34357#false} is VALID [2022-02-21 04:23:19,027 INFO L290 TraceCheckUtils]: 153: Hoare triple {34357#false} assume !(1 == ~E_7~0); {34357#false} is VALID [2022-02-21 04:23:19,027 INFO L290 TraceCheckUtils]: 154: Hoare triple {34357#false} assume !(1 == ~E_8~0); {34357#false} is VALID [2022-02-21 04:23:19,027 INFO L290 TraceCheckUtils]: 155: Hoare triple {34357#false} assume !(1 == ~E_9~0); {34357#false} is VALID [2022-02-21 04:23:19,027 INFO L290 TraceCheckUtils]: 156: Hoare triple {34357#false} assume !(1 == ~E_10~0); {34357#false} is VALID [2022-02-21 04:23:19,027 INFO L290 TraceCheckUtils]: 157: Hoare triple {34357#false} assume !(1 == ~E_11~0); {34357#false} is VALID [2022-02-21 04:23:19,027 INFO L290 TraceCheckUtils]: 158: Hoare triple {34357#false} assume !(1 == ~E_12~0); {34357#false} is VALID [2022-02-21 04:23:19,028 INFO L290 TraceCheckUtils]: 159: Hoare triple {34357#false} assume 1 == ~E_13~0;~E_13~0 := 2; {34357#false} is VALID [2022-02-21 04:23:19,028 INFO L290 TraceCheckUtils]: 160: Hoare triple {34357#false} assume { :end_inline_reset_delta_events } true; {34357#false} is VALID [2022-02-21 04:23:19,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:19,028 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:19,028 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488758945] [2022-02-21 04:23:19,028 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1488758945] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:19,028 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:19,029 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:19,029 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [109057569] [2022-02-21 04:23:19,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:19,029 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:19,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:19,029 INFO L85 PathProgramCache]: Analyzing trace with hash 1537163566, now seen corresponding path program 1 times [2022-02-21 04:23:19,030 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:19,030 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652313709] [2022-02-21 04:23:19,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:19,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:19,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:19,071 INFO L290 TraceCheckUtils]: 0: Hoare triple {34359#true} assume !false; {34359#true} is VALID [2022-02-21 04:23:19,071 INFO L290 TraceCheckUtils]: 1: Hoare triple {34359#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {34359#true} is VALID [2022-02-21 04:23:19,071 INFO L290 TraceCheckUtils]: 2: Hoare triple {34359#true} assume !false; {34359#true} is VALID [2022-02-21 04:23:19,071 INFO L290 TraceCheckUtils]: 3: Hoare triple {34359#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {34359#true} is VALID [2022-02-21 04:23:19,071 INFO L290 TraceCheckUtils]: 4: Hoare triple {34359#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {34359#true} is VALID [2022-02-21 04:23:19,071 INFO L290 TraceCheckUtils]: 5: Hoare triple {34359#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {34359#true} is VALID [2022-02-21 04:23:19,072 INFO L290 TraceCheckUtils]: 6: Hoare triple {34359#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {34359#true} is VALID [2022-02-21 04:23:19,072 INFO L290 TraceCheckUtils]: 7: Hoare triple {34359#true} assume !(0 != eval_~tmp~0#1); {34359#true} is VALID [2022-02-21 04:23:19,072 INFO L290 TraceCheckUtils]: 8: Hoare triple {34359#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {34359#true} is VALID [2022-02-21 04:23:19,072 INFO L290 TraceCheckUtils]: 9: Hoare triple {34359#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {34359#true} is VALID [2022-02-21 04:23:19,072 INFO L290 TraceCheckUtils]: 10: Hoare triple {34359#true} assume 0 == ~M_E~0;~M_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,072 INFO L290 TraceCheckUtils]: 11: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,072 INFO L290 TraceCheckUtils]: 12: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,073 INFO L290 TraceCheckUtils]: 13: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,073 INFO L290 TraceCheckUtils]: 14: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,073 INFO L290 TraceCheckUtils]: 15: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,073 INFO L290 TraceCheckUtils]: 16: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,074 INFO L290 TraceCheckUtils]: 17: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,074 INFO L290 TraceCheckUtils]: 18: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,074 INFO L290 TraceCheckUtils]: 19: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,074 INFO L290 TraceCheckUtils]: 20: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,074 INFO L290 TraceCheckUtils]: 21: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,075 INFO L290 TraceCheckUtils]: 22: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,075 INFO L290 TraceCheckUtils]: 23: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,075 INFO L290 TraceCheckUtils]: 24: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,075 INFO L290 TraceCheckUtils]: 25: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,076 INFO L290 TraceCheckUtils]: 26: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,076 INFO L290 TraceCheckUtils]: 27: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,076 INFO L290 TraceCheckUtils]: 28: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,076 INFO L290 TraceCheckUtils]: 29: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,076 INFO L290 TraceCheckUtils]: 30: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,077 INFO L290 TraceCheckUtils]: 31: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,077 INFO L290 TraceCheckUtils]: 32: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,077 INFO L290 TraceCheckUtils]: 33: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,077 INFO L290 TraceCheckUtils]: 34: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,078 INFO L290 TraceCheckUtils]: 35: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,078 INFO L290 TraceCheckUtils]: 36: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,078 INFO L290 TraceCheckUtils]: 37: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,078 INFO L290 TraceCheckUtils]: 38: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,079 INFO L290 TraceCheckUtils]: 39: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,079 INFO L290 TraceCheckUtils]: 40: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,079 INFO L290 TraceCheckUtils]: 41: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,079 INFO L290 TraceCheckUtils]: 42: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,079 INFO L290 TraceCheckUtils]: 43: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,080 INFO L290 TraceCheckUtils]: 44: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,080 INFO L290 TraceCheckUtils]: 45: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,080 INFO L290 TraceCheckUtils]: 46: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,080 INFO L290 TraceCheckUtils]: 47: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,081 INFO L290 TraceCheckUtils]: 48: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,081 INFO L290 TraceCheckUtils]: 49: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,081 INFO L290 TraceCheckUtils]: 50: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,081 INFO L290 TraceCheckUtils]: 51: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,081 INFO L290 TraceCheckUtils]: 52: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,082 INFO L290 TraceCheckUtils]: 53: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,082 INFO L290 TraceCheckUtils]: 54: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,082 INFO L290 TraceCheckUtils]: 55: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,082 INFO L290 TraceCheckUtils]: 56: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,083 INFO L290 TraceCheckUtils]: 57: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,083 INFO L290 TraceCheckUtils]: 58: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,083 INFO L290 TraceCheckUtils]: 59: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,083 INFO L290 TraceCheckUtils]: 60: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,083 INFO L290 TraceCheckUtils]: 61: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,084 INFO L290 TraceCheckUtils]: 62: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,084 INFO L290 TraceCheckUtils]: 63: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,084 INFO L290 TraceCheckUtils]: 64: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,084 INFO L290 TraceCheckUtils]: 65: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,085 INFO L290 TraceCheckUtils]: 66: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,085 INFO L290 TraceCheckUtils]: 67: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,085 INFO L290 TraceCheckUtils]: 68: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,085 INFO L290 TraceCheckUtils]: 69: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,085 INFO L290 TraceCheckUtils]: 70: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,086 INFO L290 TraceCheckUtils]: 71: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,086 INFO L290 TraceCheckUtils]: 72: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,086 INFO L290 TraceCheckUtils]: 73: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,086 INFO L290 TraceCheckUtils]: 74: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,087 INFO L290 TraceCheckUtils]: 75: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,087 INFO L290 TraceCheckUtils]: 76: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,087 INFO L290 TraceCheckUtils]: 77: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,087 INFO L290 TraceCheckUtils]: 78: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,087 INFO L290 TraceCheckUtils]: 79: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,088 INFO L290 TraceCheckUtils]: 80: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,088 INFO L290 TraceCheckUtils]: 81: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,088 INFO L290 TraceCheckUtils]: 82: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,088 INFO L290 TraceCheckUtils]: 83: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,089 INFO L290 TraceCheckUtils]: 84: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,089 INFO L290 TraceCheckUtils]: 85: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,089 INFO L290 TraceCheckUtils]: 86: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,089 INFO L290 TraceCheckUtils]: 87: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,089 INFO L290 TraceCheckUtils]: 88: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,090 INFO L290 TraceCheckUtils]: 89: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,090 INFO L290 TraceCheckUtils]: 90: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,090 INFO L290 TraceCheckUtils]: 91: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,090 INFO L290 TraceCheckUtils]: 92: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,091 INFO L290 TraceCheckUtils]: 93: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,091 INFO L290 TraceCheckUtils]: 94: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,091 INFO L290 TraceCheckUtils]: 95: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,091 INFO L290 TraceCheckUtils]: 96: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,092 INFO L290 TraceCheckUtils]: 97: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,092 INFO L290 TraceCheckUtils]: 98: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,092 INFO L290 TraceCheckUtils]: 99: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,092 INFO L290 TraceCheckUtils]: 100: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,092 INFO L290 TraceCheckUtils]: 101: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,093 INFO L290 TraceCheckUtils]: 102: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,093 INFO L290 TraceCheckUtils]: 103: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,093 INFO L290 TraceCheckUtils]: 104: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,093 INFO L290 TraceCheckUtils]: 105: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,094 INFO L290 TraceCheckUtils]: 106: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,094 INFO L290 TraceCheckUtils]: 107: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,094 INFO L290 TraceCheckUtils]: 108: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,094 INFO L290 TraceCheckUtils]: 109: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,094 INFO L290 TraceCheckUtils]: 110: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,095 INFO L290 TraceCheckUtils]: 111: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,095 INFO L290 TraceCheckUtils]: 112: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,095 INFO L290 TraceCheckUtils]: 113: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,095 INFO L290 TraceCheckUtils]: 114: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,096 INFO L290 TraceCheckUtils]: 115: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,096 INFO L290 TraceCheckUtils]: 116: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,096 INFO L290 TraceCheckUtils]: 117: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t13_pc~0); {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,096 INFO L290 TraceCheckUtils]: 118: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,096 INFO L290 TraceCheckUtils]: 119: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,097 INFO L290 TraceCheckUtils]: 120: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,097 INFO L290 TraceCheckUtils]: 121: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,097 INFO L290 TraceCheckUtils]: 122: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34361#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,097 INFO L290 TraceCheckUtils]: 123: Hoare triple {34361#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {34360#false} is VALID [2022-02-21 04:23:19,097 INFO L290 TraceCheckUtils]: 124: Hoare triple {34360#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 125: Hoare triple {34360#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 126: Hoare triple {34360#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 127: Hoare triple {34360#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 128: Hoare triple {34360#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 129: Hoare triple {34360#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 130: Hoare triple {34360#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 131: Hoare triple {34360#false} assume !(1 == ~T8_E~0); {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 132: Hoare triple {34360#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 133: Hoare triple {34360#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 134: Hoare triple {34360#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 135: Hoare triple {34360#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 136: Hoare triple {34360#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 137: Hoare triple {34360#false} assume 1 == ~E_M~0;~E_M~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 138: Hoare triple {34360#false} assume 1 == ~E_1~0;~E_1~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 139: Hoare triple {34360#false} assume !(1 == ~E_2~0); {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 140: Hoare triple {34360#false} assume 1 == ~E_3~0;~E_3~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 141: Hoare triple {34360#false} assume 1 == ~E_4~0;~E_4~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 142: Hoare triple {34360#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 143: Hoare triple {34360#false} assume 1 == ~E_6~0;~E_6~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 144: Hoare triple {34360#false} assume 1 == ~E_7~0;~E_7~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 145: Hoare triple {34360#false} assume 1 == ~E_8~0;~E_8~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,098 INFO L290 TraceCheckUtils]: 146: Hoare triple {34360#false} assume 1 == ~E_9~0;~E_9~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 147: Hoare triple {34360#false} assume !(1 == ~E_10~0); {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 148: Hoare triple {34360#false} assume 1 == ~E_11~0;~E_11~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 149: Hoare triple {34360#false} assume 1 == ~E_12~0;~E_12~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 150: Hoare triple {34360#false} assume 1 == ~E_13~0;~E_13~0 := 2; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 151: Hoare triple {34360#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 152: Hoare triple {34360#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 153: Hoare triple {34360#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 154: Hoare triple {34360#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 155: Hoare triple {34360#false} assume !(0 == start_simulation_~tmp~3#1); {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 156: Hoare triple {34360#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 157: Hoare triple {34360#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 158: Hoare triple {34360#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 159: Hoare triple {34360#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 160: Hoare triple {34360#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 161: Hoare triple {34360#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 162: Hoare triple {34360#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {34360#false} is VALID [2022-02-21 04:23:19,099 INFO L290 TraceCheckUtils]: 163: Hoare triple {34360#false} assume !(0 != start_simulation_~tmp___0~1#1); {34360#false} is VALID [2022-02-21 04:23:19,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:19,100 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:19,100 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652313709] [2022-02-21 04:23:19,100 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1652313709] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:19,100 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:19,100 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:19,100 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380682109] [2022-02-21 04:23:19,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:19,100 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:19,100 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:19,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:19,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:19,101 INFO L87 Difference]: Start difference. First operand 2018 states and 2984 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:20,609 INFO L93 Difference]: Finished difference Result 2018 states and 2983 transitions. [2022-02-21 04:23:20,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:20,609 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,721 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:20,723 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2983 transitions. [2022-02-21 04:23:20,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:20,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2983 transitions. [2022-02-21 04:23:20,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:20,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:20,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2983 transitions. [2022-02-21 04:23:20,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:20,903 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2022-02-21 04:23:20,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2983 transitions. [2022-02-21 04:23:20,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:20,923 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:20,925 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2983 transitions. Second operand has 2018 states, 2018 states have (on average 1.4781962338949455) internal successors, (2983), 2017 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,927 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2983 transitions. Second operand has 2018 states, 2018 states have (on average 1.4781962338949455) internal successors, (2983), 2017 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,929 INFO L87 Difference]: Start difference. First operand 2018 states and 2983 transitions. Second operand has 2018 states, 2018 states have (on average 1.4781962338949455) internal successors, (2983), 2017 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:21,026 INFO L93 Difference]: Finished difference Result 2018 states and 2983 transitions. [2022-02-21 04:23:21,026 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2983 transitions. [2022-02-21 04:23:21,028 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:21,028 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:21,031 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.4781962338949455) internal successors, (2983), 2017 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2983 transitions. [2022-02-21 04:23:21,032 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.4781962338949455) internal successors, (2983), 2017 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2983 transitions. [2022-02-21 04:23:21,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:21,140 INFO L93 Difference]: Finished difference Result 2018 states and 2983 transitions. [2022-02-21 04:23:21,140 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2983 transitions. [2022-02-21 04:23:21,141 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:21,141 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:21,141 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:21,142 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:21,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4781962338949455) internal successors, (2983), 2017 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2983 transitions. [2022-02-21 04:23:21,228 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2022-02-21 04:23:21,228 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2022-02-21 04:23:21,228 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:23:21,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2983 transitions. [2022-02-21 04:23:21,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:21,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:21,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:21,233 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:21,233 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:21,234 INFO L791 eck$LassoCheckResult]: Stem: 37295#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37296#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 38332#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37787#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37788#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 37277#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37278#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37344#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37345#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37783#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 37784#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 37310#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 37129#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 37130#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37574#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37575#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37450#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37451#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37100#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37101#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 38324#L1279-2 assume !(0 == ~T1_E~0); 36723#L1284-1 assume !(0 == ~T2_E~0); 36724#L1289-1 assume !(0 == ~T3_E~0); 37447#L1294-1 assume !(0 == ~T4_E~0); 37448#L1299-1 assume !(0 == ~T5_E~0); 37459#L1304-1 assume !(0 == ~T6_E~0); 38390#L1309-1 assume !(0 == ~T7_E~0); 38391#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36653#L1319-1 assume !(0 == ~T9_E~0); 36654#L1324-1 assume !(0 == ~T10_E~0); 36826#L1329-1 assume !(0 == ~T11_E~0); 36827#L1334-1 assume !(0 == ~T12_E~0); 38231#L1339-1 assume !(0 == ~T13_E~0); 38312#L1344-1 assume !(0 == ~E_M~0); 38313#L1349-1 assume !(0 == ~E_1~0); 37634#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 37635#L1359-1 assume !(0 == ~E_3~0); 38064#L1364-1 assume !(0 == ~E_4~0); 36955#L1369-1 assume !(0 == ~E_5~0); 36956#L1374-1 assume !(0 == ~E_6~0); 37639#L1379-1 assume !(0 == ~E_7~0); 37640#L1384-1 assume !(0 == ~E_8~0); 37717#L1389-1 assume !(0 == ~E_9~0); 38250#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 38251#L1399-1 assume !(0 == ~E_11~0); 38354#L1404-1 assume !(0 == ~E_12~0); 37048#L1409-1 assume !(0 == ~E_13~0); 37049#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38346#L628 assume !(1 == ~m_pc~0); 36952#L628-2 is_master_triggered_~__retres1~0#1 := 0; 36951#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37715#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37716#L1591 assume !(0 != activate_threads_~tmp~1#1); 38359#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37503#L647 assume 1 == ~t1_pc~0; 36872#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36873#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37144#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37145#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 38299#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38300#L666 assume 1 == ~t2_pc~0; 36720#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36721#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36887#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38316#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 37835#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37836#L685 assume !(1 == ~t3_pc~0); 37941#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37940#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37563#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37564#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37685#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37171#L704 assume 1 == ~t4_pc~0; 37172#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37696#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37697#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38337#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 37556#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37557#L723 assume !(1 == ~t5_pc~0); 37679#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 37915#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38059#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37814#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 37815#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36937#L742 assume 1 == ~t6_pc~0; 36938#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37086#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37087#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36622#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 36623#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37014#L761 assume !(1 == ~t7_pc~0); 37015#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 36883#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36884#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37686#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 37687#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36647#L780 assume 1 == ~t8_pc~0; 36648#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36923#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36924#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37647#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 37648#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37767#L799 assume 1 == ~t9_pc~0; 37879#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36650#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36651#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37779#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 37986#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37797#L818 assume !(1 == ~t10_pc~0); 36431#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36432#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37872#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37801#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37802#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37842#L837 assume 1 == ~t11_pc~0; 37843#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37677#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38080#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37760#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 37761#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37512#L856 assume !(1 == ~t12_pc~0); 37513#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 38166#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38167#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38147#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 38148#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38327#L875 assume 1 == ~t13_pc~0; 37457#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37089#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37090#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37029#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 37030#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37869#L1427 assume !(1 == ~M_E~0); 37853#L1427-2 assume !(1 == ~T1_E~0); 37001#L1432-1 assume !(1 == ~T2_E~0); 37002#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38070#L1442-1 assume !(1 == ~T4_E~0); 38071#L1447-1 assume !(1 == ~T5_E~0); 37926#L1452-1 assume !(1 == ~T6_E~0); 36566#L1457-1 assume !(1 == ~T7_E~0); 36567#L1462-1 assume !(1 == ~T8_E~0); 38097#L1467-1 assume !(1 == ~T9_E~0); 38115#L1472-1 assume !(1 == ~T10_E~0); 38116#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37867#L1482-1 assume !(1 == ~T12_E~0); 37868#L1487-1 assume !(1 == ~T13_E~0); 36897#L1492-1 assume !(1 == ~E_M~0); 36898#L1497-1 assume !(1 == ~E_1~0); 37259#L1502-1 assume !(1 == ~E_2~0); 37260#L1507-1 assume !(1 == ~E_3~0); 36775#L1512-1 assume !(1 == ~E_4~0); 36776#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38186#L1522-1 assume !(1 == ~E_6~0); 37500#L1527-1 assume !(1 == ~E_7~0); 37501#L1532-1 assume !(1 == ~E_8~0); 38374#L1537-1 assume !(1 == ~E_9~0); 37703#L1542-1 assume !(1 == ~E_10~0); 37534#L1547-1 assume !(1 == ~E_11~0); 37535#L1552-1 assume !(1 == ~E_12~0); 36470#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 36471#L1562-1 assume { :end_inline_reset_delta_events } true; 37077#L1928-2 [2022-02-21 04:23:21,234 INFO L793 eck$LassoCheckResult]: Loop: 37077#L1928-2 assume !false; 37568#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36731#L1254 assume !false; 37318#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36805#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36806#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37003#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 38174#L1067 assume !(0 != eval_~tmp~0#1); 37244#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36821#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36822#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37281#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37263#L1284-3 assume !(0 == ~T2_E~0); 37264#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37242#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37243#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37630#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37631#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37140#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37141#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38137#L1324-3 assume !(0 == ~T10_E~0); 36772#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36773#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37540#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37541#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37839#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37121#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37122#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37850#L1364-3 assume !(0 == ~E_4~0); 38372#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38268#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36901#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36902#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37119#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37120#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37410#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38278#L1404-3 assume !(0 == ~E_12~0); 38242#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38243#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37729#L628-45 assume !(1 == ~m_pc~0); 37408#L628-47 is_master_triggered_~__retres1~0#1 := 0; 37409#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36766#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36767#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37155#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37878#L647-45 assume 1 == ~t1_pc~0; 36717#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36718#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37646#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36831#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36832#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37043#L666-45 assume !(1 == ~t2_pc~0); 37044#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 37525#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38087#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38002#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37996#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36581#L685-45 assume 1 == ~t3_pc~0; 36582#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37641#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38315#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38184#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38185#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38325#L704-45 assume 1 == ~t4_pc~0; 38204#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36448#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37307#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37650#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38397#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37762#L723-45 assume !(1 == ~t5_pc~0); 37763#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 38252#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37354#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37131#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 37132#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38156#L742-45 assume !(1 == ~t6_pc~0); 37378#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 37379#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37848#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37884#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37885#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37973#L761-45 assume !(1 == ~t7_pc~0); 37974#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 37372#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37373#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36779#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36780#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38246#L780-45 assume 1 == ~t8_pc~0; 37157#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36791#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36792#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38373#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36761#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36762#L799-45 assume 1 == ~t9_pc~0; 37538#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36983#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38298#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37927#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37928#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36699#L818-45 assume 1 == ~t10_pc~0; 36700#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36818#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37901#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37305#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37306#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38021#L837-45 assume !(1 == ~t11_pc~0); 37236#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37237#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37374#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38039#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36837#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36838#L856-45 assume 1 == ~t12_pc~0; 38323#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36840#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36781#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36782#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37644#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37645#L875-45 assume !(1 == ~t13_pc~0); 37617#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 37616#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37678#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38290#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38291#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38230#L1427-3 assume !(1 == ~M_E~0); 37441#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37442#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37980#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37632#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37633#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36489#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36490#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38172#L1462-3 assume !(1 == ~T8_E~0); 38173#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38036#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38037#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36740#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36741#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 36882#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37055#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37056#L1502-3 assume !(1 == ~E_2~0); 38004#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38135#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37093#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36785#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36786#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36750#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36751#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37851#L1542-3 assume !(1 == ~E_10~0); 37989#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37618#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37619#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 36961#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36962#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36381#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37146#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 37147#L1947 assume !(0 == start_simulation_~tmp~3#1); 37752#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37957#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37018#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38350#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 38274#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38104#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37863#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37864#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 37077#L1928-2 [2022-02-21 04:23:21,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:21,241 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2022-02-21 04:23:21,241 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:21,241 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53121041] [2022-02-21 04:23:21,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:21,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:21,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:21,264 INFO L290 TraceCheckUtils]: 0: Hoare triple {42437#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {42437#true} is VALID [2022-02-21 04:23:21,265 INFO L290 TraceCheckUtils]: 1: Hoare triple {42437#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {42439#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:21,265 INFO L290 TraceCheckUtils]: 2: Hoare triple {42439#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {42439#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:21,265 INFO L290 TraceCheckUtils]: 3: Hoare triple {42439#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {42439#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:21,266 INFO L290 TraceCheckUtils]: 4: Hoare triple {42439#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {42439#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:21,266 INFO L290 TraceCheckUtils]: 5: Hoare triple {42439#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {42439#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:21,266 INFO L290 TraceCheckUtils]: 6: Hoare triple {42439#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {42439#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:21,266 INFO L290 TraceCheckUtils]: 7: Hoare triple {42439#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {42439#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:21,267 INFO L290 TraceCheckUtils]: 8: Hoare triple {42439#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {42439#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:21,267 INFO L290 TraceCheckUtils]: 9: Hoare triple {42439#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,267 INFO L290 TraceCheckUtils]: 10: Hoare triple {42438#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,267 INFO L290 TraceCheckUtils]: 11: Hoare triple {42438#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,267 INFO L290 TraceCheckUtils]: 12: Hoare triple {42438#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,267 INFO L290 TraceCheckUtils]: 13: Hoare triple {42438#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {42438#false} is VALID [2022-02-21 04:23:21,267 INFO L290 TraceCheckUtils]: 14: Hoare triple {42438#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,268 INFO L290 TraceCheckUtils]: 15: Hoare triple {42438#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,268 INFO L290 TraceCheckUtils]: 16: Hoare triple {42438#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,268 INFO L290 TraceCheckUtils]: 17: Hoare triple {42438#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,268 INFO L290 TraceCheckUtils]: 18: Hoare triple {42438#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {42438#false} is VALID [2022-02-21 04:23:21,268 INFO L290 TraceCheckUtils]: 19: Hoare triple {42438#false} assume 0 == ~M_E~0;~M_E~0 := 1; {42438#false} is VALID [2022-02-21 04:23:21,268 INFO L290 TraceCheckUtils]: 20: Hoare triple {42438#false} assume !(0 == ~T1_E~0); {42438#false} is VALID [2022-02-21 04:23:21,268 INFO L290 TraceCheckUtils]: 21: Hoare triple {42438#false} assume !(0 == ~T2_E~0); {42438#false} is VALID [2022-02-21 04:23:21,268 INFO L290 TraceCheckUtils]: 22: Hoare triple {42438#false} assume !(0 == ~T3_E~0); {42438#false} is VALID [2022-02-21 04:23:21,268 INFO L290 TraceCheckUtils]: 23: Hoare triple {42438#false} assume !(0 == ~T4_E~0); {42438#false} is VALID [2022-02-21 04:23:21,268 INFO L290 TraceCheckUtils]: 24: Hoare triple {42438#false} assume !(0 == ~T5_E~0); {42438#false} is VALID [2022-02-21 04:23:21,269 INFO L290 TraceCheckUtils]: 25: Hoare triple {42438#false} assume !(0 == ~T6_E~0); {42438#false} is VALID [2022-02-21 04:23:21,269 INFO L290 TraceCheckUtils]: 26: Hoare triple {42438#false} assume !(0 == ~T7_E~0); {42438#false} is VALID [2022-02-21 04:23:21,269 INFO L290 TraceCheckUtils]: 27: Hoare triple {42438#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {42438#false} is VALID [2022-02-21 04:23:21,269 INFO L290 TraceCheckUtils]: 28: Hoare triple {42438#false} assume !(0 == ~T9_E~0); {42438#false} is VALID [2022-02-21 04:23:21,269 INFO L290 TraceCheckUtils]: 29: Hoare triple {42438#false} assume !(0 == ~T10_E~0); {42438#false} is VALID [2022-02-21 04:23:21,269 INFO L290 TraceCheckUtils]: 30: Hoare triple {42438#false} assume !(0 == ~T11_E~0); {42438#false} is VALID [2022-02-21 04:23:21,269 INFO L290 TraceCheckUtils]: 31: Hoare triple {42438#false} assume !(0 == ~T12_E~0); {42438#false} is VALID [2022-02-21 04:23:21,269 INFO L290 TraceCheckUtils]: 32: Hoare triple {42438#false} assume !(0 == ~T13_E~0); {42438#false} is VALID [2022-02-21 04:23:21,269 INFO L290 TraceCheckUtils]: 33: Hoare triple {42438#false} assume !(0 == ~E_M~0); {42438#false} is VALID [2022-02-21 04:23:21,269 INFO L290 TraceCheckUtils]: 34: Hoare triple {42438#false} assume !(0 == ~E_1~0); {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 35: Hoare triple {42438#false} assume 0 == ~E_2~0;~E_2~0 := 1; {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 36: Hoare triple {42438#false} assume !(0 == ~E_3~0); {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 37: Hoare triple {42438#false} assume !(0 == ~E_4~0); {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 38: Hoare triple {42438#false} assume !(0 == ~E_5~0); {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 39: Hoare triple {42438#false} assume !(0 == ~E_6~0); {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 40: Hoare triple {42438#false} assume !(0 == ~E_7~0); {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 41: Hoare triple {42438#false} assume !(0 == ~E_8~0); {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 42: Hoare triple {42438#false} assume !(0 == ~E_9~0); {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 43: Hoare triple {42438#false} assume 0 == ~E_10~0;~E_10~0 := 1; {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 44: Hoare triple {42438#false} assume !(0 == ~E_11~0); {42438#false} is VALID [2022-02-21 04:23:21,270 INFO L290 TraceCheckUtils]: 45: Hoare triple {42438#false} assume !(0 == ~E_12~0); {42438#false} is VALID [2022-02-21 04:23:21,271 INFO L290 TraceCheckUtils]: 46: Hoare triple {42438#false} assume !(0 == ~E_13~0); {42438#false} is VALID [2022-02-21 04:23:21,271 INFO L290 TraceCheckUtils]: 47: Hoare triple {42438#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {42438#false} is VALID [2022-02-21 04:23:21,271 INFO L290 TraceCheckUtils]: 48: Hoare triple {42438#false} assume !(1 == ~m_pc~0); {42438#false} is VALID [2022-02-21 04:23:21,271 INFO L290 TraceCheckUtils]: 49: Hoare triple {42438#false} is_master_triggered_~__retres1~0#1 := 0; {42438#false} is VALID [2022-02-21 04:23:21,271 INFO L290 TraceCheckUtils]: 50: Hoare triple {42438#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {42438#false} is VALID [2022-02-21 04:23:21,271 INFO L290 TraceCheckUtils]: 51: Hoare triple {42438#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {42438#false} is VALID [2022-02-21 04:23:21,271 INFO L290 TraceCheckUtils]: 52: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp~1#1); {42438#false} is VALID [2022-02-21 04:23:21,271 INFO L290 TraceCheckUtils]: 53: Hoare triple {42438#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {42438#false} is VALID [2022-02-21 04:23:21,271 INFO L290 TraceCheckUtils]: 54: Hoare triple {42438#false} assume 1 == ~t1_pc~0; {42438#false} is VALID [2022-02-21 04:23:21,272 INFO L290 TraceCheckUtils]: 55: Hoare triple {42438#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {42438#false} is VALID [2022-02-21 04:23:21,272 INFO L290 TraceCheckUtils]: 56: Hoare triple {42438#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {42438#false} is VALID [2022-02-21 04:23:21,272 INFO L290 TraceCheckUtils]: 57: Hoare triple {42438#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {42438#false} is VALID [2022-02-21 04:23:21,272 INFO L290 TraceCheckUtils]: 58: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___0~0#1); {42438#false} is VALID [2022-02-21 04:23:21,272 INFO L290 TraceCheckUtils]: 59: Hoare triple {42438#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {42438#false} is VALID [2022-02-21 04:23:21,272 INFO L290 TraceCheckUtils]: 60: Hoare triple {42438#false} assume 1 == ~t2_pc~0; {42438#false} is VALID [2022-02-21 04:23:21,272 INFO L290 TraceCheckUtils]: 61: Hoare triple {42438#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {42438#false} is VALID [2022-02-21 04:23:21,272 INFO L290 TraceCheckUtils]: 62: Hoare triple {42438#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {42438#false} is VALID [2022-02-21 04:23:21,272 INFO L290 TraceCheckUtils]: 63: Hoare triple {42438#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {42438#false} is VALID [2022-02-21 04:23:21,272 INFO L290 TraceCheckUtils]: 64: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___1~0#1); {42438#false} is VALID [2022-02-21 04:23:21,273 INFO L290 TraceCheckUtils]: 65: Hoare triple {42438#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {42438#false} is VALID [2022-02-21 04:23:21,273 INFO L290 TraceCheckUtils]: 66: Hoare triple {42438#false} assume !(1 == ~t3_pc~0); {42438#false} is VALID [2022-02-21 04:23:21,273 INFO L290 TraceCheckUtils]: 67: Hoare triple {42438#false} is_transmit3_triggered_~__retres1~3#1 := 0; {42438#false} is VALID [2022-02-21 04:23:21,273 INFO L290 TraceCheckUtils]: 68: Hoare triple {42438#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {42438#false} is VALID [2022-02-21 04:23:21,273 INFO L290 TraceCheckUtils]: 69: Hoare triple {42438#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {42438#false} is VALID [2022-02-21 04:23:21,273 INFO L290 TraceCheckUtils]: 70: Hoare triple {42438#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {42438#false} is VALID [2022-02-21 04:23:21,273 INFO L290 TraceCheckUtils]: 71: Hoare triple {42438#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {42438#false} is VALID [2022-02-21 04:23:21,273 INFO L290 TraceCheckUtils]: 72: Hoare triple {42438#false} assume 1 == ~t4_pc~0; {42438#false} is VALID [2022-02-21 04:23:21,273 INFO L290 TraceCheckUtils]: 73: Hoare triple {42438#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {42438#false} is VALID [2022-02-21 04:23:21,273 INFO L290 TraceCheckUtils]: 74: Hoare triple {42438#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {42438#false} is VALID [2022-02-21 04:23:21,274 INFO L290 TraceCheckUtils]: 75: Hoare triple {42438#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {42438#false} is VALID [2022-02-21 04:23:21,274 INFO L290 TraceCheckUtils]: 76: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___3~0#1); {42438#false} is VALID [2022-02-21 04:23:21,274 INFO L290 TraceCheckUtils]: 77: Hoare triple {42438#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {42438#false} is VALID [2022-02-21 04:23:21,274 INFO L290 TraceCheckUtils]: 78: Hoare triple {42438#false} assume !(1 == ~t5_pc~0); {42438#false} is VALID [2022-02-21 04:23:21,274 INFO L290 TraceCheckUtils]: 79: Hoare triple {42438#false} is_transmit5_triggered_~__retres1~5#1 := 0; {42438#false} is VALID [2022-02-21 04:23:21,274 INFO L290 TraceCheckUtils]: 80: Hoare triple {42438#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {42438#false} is VALID [2022-02-21 04:23:21,274 INFO L290 TraceCheckUtils]: 81: Hoare triple {42438#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {42438#false} is VALID [2022-02-21 04:23:21,274 INFO L290 TraceCheckUtils]: 82: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___4~0#1); {42438#false} is VALID [2022-02-21 04:23:21,274 INFO L290 TraceCheckUtils]: 83: Hoare triple {42438#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {42438#false} is VALID [2022-02-21 04:23:21,274 INFO L290 TraceCheckUtils]: 84: Hoare triple {42438#false} assume 1 == ~t6_pc~0; {42438#false} is VALID [2022-02-21 04:23:21,275 INFO L290 TraceCheckUtils]: 85: Hoare triple {42438#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {42438#false} is VALID [2022-02-21 04:23:21,275 INFO L290 TraceCheckUtils]: 86: Hoare triple {42438#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {42438#false} is VALID [2022-02-21 04:23:21,275 INFO L290 TraceCheckUtils]: 87: Hoare triple {42438#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {42438#false} is VALID [2022-02-21 04:23:21,275 INFO L290 TraceCheckUtils]: 88: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___5~0#1); {42438#false} is VALID [2022-02-21 04:23:21,275 INFO L290 TraceCheckUtils]: 89: Hoare triple {42438#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {42438#false} is VALID [2022-02-21 04:23:21,275 INFO L290 TraceCheckUtils]: 90: Hoare triple {42438#false} assume !(1 == ~t7_pc~0); {42438#false} is VALID [2022-02-21 04:23:21,275 INFO L290 TraceCheckUtils]: 91: Hoare triple {42438#false} is_transmit7_triggered_~__retres1~7#1 := 0; {42438#false} is VALID [2022-02-21 04:23:21,275 INFO L290 TraceCheckUtils]: 92: Hoare triple {42438#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {42438#false} is VALID [2022-02-21 04:23:21,275 INFO L290 TraceCheckUtils]: 93: Hoare triple {42438#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {42438#false} is VALID [2022-02-21 04:23:21,275 INFO L290 TraceCheckUtils]: 94: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___6~0#1); {42438#false} is VALID [2022-02-21 04:23:21,276 INFO L290 TraceCheckUtils]: 95: Hoare triple {42438#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {42438#false} is VALID [2022-02-21 04:23:21,276 INFO L290 TraceCheckUtils]: 96: Hoare triple {42438#false} assume 1 == ~t8_pc~0; {42438#false} is VALID [2022-02-21 04:23:21,276 INFO L290 TraceCheckUtils]: 97: Hoare triple {42438#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {42438#false} is VALID [2022-02-21 04:23:21,276 INFO L290 TraceCheckUtils]: 98: Hoare triple {42438#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {42438#false} is VALID [2022-02-21 04:23:21,276 INFO L290 TraceCheckUtils]: 99: Hoare triple {42438#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {42438#false} is VALID [2022-02-21 04:23:21,276 INFO L290 TraceCheckUtils]: 100: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___7~0#1); {42438#false} is VALID [2022-02-21 04:23:21,276 INFO L290 TraceCheckUtils]: 101: Hoare triple {42438#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {42438#false} is VALID [2022-02-21 04:23:21,276 INFO L290 TraceCheckUtils]: 102: Hoare triple {42438#false} assume 1 == ~t9_pc~0; {42438#false} is VALID [2022-02-21 04:23:21,276 INFO L290 TraceCheckUtils]: 103: Hoare triple {42438#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {42438#false} is VALID [2022-02-21 04:23:21,277 INFO L290 TraceCheckUtils]: 104: Hoare triple {42438#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {42438#false} is VALID [2022-02-21 04:23:21,277 INFO L290 TraceCheckUtils]: 105: Hoare triple {42438#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {42438#false} is VALID [2022-02-21 04:23:21,277 INFO L290 TraceCheckUtils]: 106: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___8~0#1); {42438#false} is VALID [2022-02-21 04:23:21,277 INFO L290 TraceCheckUtils]: 107: Hoare triple {42438#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {42438#false} is VALID [2022-02-21 04:23:21,277 INFO L290 TraceCheckUtils]: 108: Hoare triple {42438#false} assume !(1 == ~t10_pc~0); {42438#false} is VALID [2022-02-21 04:23:21,277 INFO L290 TraceCheckUtils]: 109: Hoare triple {42438#false} is_transmit10_triggered_~__retres1~10#1 := 0; {42438#false} is VALID [2022-02-21 04:23:21,277 INFO L290 TraceCheckUtils]: 110: Hoare triple {42438#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {42438#false} is VALID [2022-02-21 04:23:21,277 INFO L290 TraceCheckUtils]: 111: Hoare triple {42438#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {42438#false} is VALID [2022-02-21 04:23:21,277 INFO L290 TraceCheckUtils]: 112: Hoare triple {42438#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {42438#false} is VALID [2022-02-21 04:23:21,277 INFO L290 TraceCheckUtils]: 113: Hoare triple {42438#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {42438#false} is VALID [2022-02-21 04:23:21,278 INFO L290 TraceCheckUtils]: 114: Hoare triple {42438#false} assume 1 == ~t11_pc~0; {42438#false} is VALID [2022-02-21 04:23:21,278 INFO L290 TraceCheckUtils]: 115: Hoare triple {42438#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {42438#false} is VALID [2022-02-21 04:23:21,278 INFO L290 TraceCheckUtils]: 116: Hoare triple {42438#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {42438#false} is VALID [2022-02-21 04:23:21,278 INFO L290 TraceCheckUtils]: 117: Hoare triple {42438#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {42438#false} is VALID [2022-02-21 04:23:21,278 INFO L290 TraceCheckUtils]: 118: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___10~0#1); {42438#false} is VALID [2022-02-21 04:23:21,278 INFO L290 TraceCheckUtils]: 119: Hoare triple {42438#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {42438#false} is VALID [2022-02-21 04:23:21,278 INFO L290 TraceCheckUtils]: 120: Hoare triple {42438#false} assume !(1 == ~t12_pc~0); {42438#false} is VALID [2022-02-21 04:23:21,278 INFO L290 TraceCheckUtils]: 121: Hoare triple {42438#false} is_transmit12_triggered_~__retres1~12#1 := 0; {42438#false} is VALID [2022-02-21 04:23:21,278 INFO L290 TraceCheckUtils]: 122: Hoare triple {42438#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {42438#false} is VALID [2022-02-21 04:23:21,278 INFO L290 TraceCheckUtils]: 123: Hoare triple {42438#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {42438#false} is VALID [2022-02-21 04:23:21,279 INFO L290 TraceCheckUtils]: 124: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___11~0#1); {42438#false} is VALID [2022-02-21 04:23:21,279 INFO L290 TraceCheckUtils]: 125: Hoare triple {42438#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {42438#false} is VALID [2022-02-21 04:23:21,279 INFO L290 TraceCheckUtils]: 126: Hoare triple {42438#false} assume 1 == ~t13_pc~0; {42438#false} is VALID [2022-02-21 04:23:21,279 INFO L290 TraceCheckUtils]: 127: Hoare triple {42438#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {42438#false} is VALID [2022-02-21 04:23:21,279 INFO L290 TraceCheckUtils]: 128: Hoare triple {42438#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {42438#false} is VALID [2022-02-21 04:23:21,279 INFO L290 TraceCheckUtils]: 129: Hoare triple {42438#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {42438#false} is VALID [2022-02-21 04:23:21,279 INFO L290 TraceCheckUtils]: 130: Hoare triple {42438#false} assume !(0 != activate_threads_~tmp___12~0#1); {42438#false} is VALID [2022-02-21 04:23:21,279 INFO L290 TraceCheckUtils]: 131: Hoare triple {42438#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {42438#false} is VALID [2022-02-21 04:23:21,279 INFO L290 TraceCheckUtils]: 132: Hoare triple {42438#false} assume !(1 == ~M_E~0); {42438#false} is VALID [2022-02-21 04:23:21,279 INFO L290 TraceCheckUtils]: 133: Hoare triple {42438#false} assume !(1 == ~T1_E~0); {42438#false} is VALID [2022-02-21 04:23:21,280 INFO L290 TraceCheckUtils]: 134: Hoare triple {42438#false} assume !(1 == ~T2_E~0); {42438#false} is VALID [2022-02-21 04:23:21,280 INFO L290 TraceCheckUtils]: 135: Hoare triple {42438#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,280 INFO L290 TraceCheckUtils]: 136: Hoare triple {42438#false} assume !(1 == ~T4_E~0); {42438#false} is VALID [2022-02-21 04:23:21,280 INFO L290 TraceCheckUtils]: 137: Hoare triple {42438#false} assume !(1 == ~T5_E~0); {42438#false} is VALID [2022-02-21 04:23:21,280 INFO L290 TraceCheckUtils]: 138: Hoare triple {42438#false} assume !(1 == ~T6_E~0); {42438#false} is VALID [2022-02-21 04:23:21,280 INFO L290 TraceCheckUtils]: 139: Hoare triple {42438#false} assume !(1 == ~T7_E~0); {42438#false} is VALID [2022-02-21 04:23:21,280 INFO L290 TraceCheckUtils]: 140: Hoare triple {42438#false} assume !(1 == ~T8_E~0); {42438#false} is VALID [2022-02-21 04:23:21,280 INFO L290 TraceCheckUtils]: 141: Hoare triple {42438#false} assume !(1 == ~T9_E~0); {42438#false} is VALID [2022-02-21 04:23:21,280 INFO L290 TraceCheckUtils]: 142: Hoare triple {42438#false} assume !(1 == ~T10_E~0); {42438#false} is VALID [2022-02-21 04:23:21,280 INFO L290 TraceCheckUtils]: 143: Hoare triple {42438#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,281 INFO L290 TraceCheckUtils]: 144: Hoare triple {42438#false} assume !(1 == ~T12_E~0); {42438#false} is VALID [2022-02-21 04:23:21,281 INFO L290 TraceCheckUtils]: 145: Hoare triple {42438#false} assume !(1 == ~T13_E~0); {42438#false} is VALID [2022-02-21 04:23:21,281 INFO L290 TraceCheckUtils]: 146: Hoare triple {42438#false} assume !(1 == ~E_M~0); {42438#false} is VALID [2022-02-21 04:23:21,281 INFO L290 TraceCheckUtils]: 147: Hoare triple {42438#false} assume !(1 == ~E_1~0); {42438#false} is VALID [2022-02-21 04:23:21,281 INFO L290 TraceCheckUtils]: 148: Hoare triple {42438#false} assume !(1 == ~E_2~0); {42438#false} is VALID [2022-02-21 04:23:21,281 INFO L290 TraceCheckUtils]: 149: Hoare triple {42438#false} assume !(1 == ~E_3~0); {42438#false} is VALID [2022-02-21 04:23:21,281 INFO L290 TraceCheckUtils]: 150: Hoare triple {42438#false} assume !(1 == ~E_4~0); {42438#false} is VALID [2022-02-21 04:23:21,281 INFO L290 TraceCheckUtils]: 151: Hoare triple {42438#false} assume 1 == ~E_5~0;~E_5~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,281 INFO L290 TraceCheckUtils]: 152: Hoare triple {42438#false} assume !(1 == ~E_6~0); {42438#false} is VALID [2022-02-21 04:23:21,281 INFO L290 TraceCheckUtils]: 153: Hoare triple {42438#false} assume !(1 == ~E_7~0); {42438#false} is VALID [2022-02-21 04:23:21,282 INFO L290 TraceCheckUtils]: 154: Hoare triple {42438#false} assume !(1 == ~E_8~0); {42438#false} is VALID [2022-02-21 04:23:21,282 INFO L290 TraceCheckUtils]: 155: Hoare triple {42438#false} assume !(1 == ~E_9~0); {42438#false} is VALID [2022-02-21 04:23:21,282 INFO L290 TraceCheckUtils]: 156: Hoare triple {42438#false} assume !(1 == ~E_10~0); {42438#false} is VALID [2022-02-21 04:23:21,282 INFO L290 TraceCheckUtils]: 157: Hoare triple {42438#false} assume !(1 == ~E_11~0); {42438#false} is VALID [2022-02-21 04:23:21,282 INFO L290 TraceCheckUtils]: 158: Hoare triple {42438#false} assume !(1 == ~E_12~0); {42438#false} is VALID [2022-02-21 04:23:21,282 INFO L290 TraceCheckUtils]: 159: Hoare triple {42438#false} assume 1 == ~E_13~0;~E_13~0 := 2; {42438#false} is VALID [2022-02-21 04:23:21,282 INFO L290 TraceCheckUtils]: 160: Hoare triple {42438#false} assume { :end_inline_reset_delta_events } true; {42438#false} is VALID [2022-02-21 04:23:21,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,283 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,283 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53121041] [2022-02-21 04:23:21,283 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53121041] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,283 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,283 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,284 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239949176] [2022-02-21 04:23:21,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,284 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:21,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:21,284 INFO L85 PathProgramCache]: Analyzing trace with hash -242294545, now seen corresponding path program 1 times [2022-02-21 04:23:21,284 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:21,288 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475437927] [2022-02-21 04:23:21,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:21,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:21,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:21,316 INFO L290 TraceCheckUtils]: 0: Hoare triple {42440#true} assume !false; {42440#true} is VALID [2022-02-21 04:23:21,316 INFO L290 TraceCheckUtils]: 1: Hoare triple {42440#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {42440#true} is VALID [2022-02-21 04:23:21,316 INFO L290 TraceCheckUtils]: 2: Hoare triple {42440#true} assume !false; {42440#true} is VALID [2022-02-21 04:23:21,317 INFO L290 TraceCheckUtils]: 3: Hoare triple {42440#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {42440#true} is VALID [2022-02-21 04:23:21,317 INFO L290 TraceCheckUtils]: 4: Hoare triple {42440#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {42440#true} is VALID [2022-02-21 04:23:21,317 INFO L290 TraceCheckUtils]: 5: Hoare triple {42440#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {42440#true} is VALID [2022-02-21 04:23:21,317 INFO L290 TraceCheckUtils]: 6: Hoare triple {42440#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {42440#true} is VALID [2022-02-21 04:23:21,317 INFO L290 TraceCheckUtils]: 7: Hoare triple {42440#true} assume !(0 != eval_~tmp~0#1); {42440#true} is VALID [2022-02-21 04:23:21,317 INFO L290 TraceCheckUtils]: 8: Hoare triple {42440#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {42440#true} is VALID [2022-02-21 04:23:21,317 INFO L290 TraceCheckUtils]: 9: Hoare triple {42440#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {42440#true} is VALID [2022-02-21 04:23:21,318 INFO L290 TraceCheckUtils]: 10: Hoare triple {42440#true} assume 0 == ~M_E~0;~M_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,318 INFO L290 TraceCheckUtils]: 11: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,318 INFO L290 TraceCheckUtils]: 12: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,318 INFO L290 TraceCheckUtils]: 13: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,319 INFO L290 TraceCheckUtils]: 14: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,319 INFO L290 TraceCheckUtils]: 15: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,319 INFO L290 TraceCheckUtils]: 16: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,319 INFO L290 TraceCheckUtils]: 17: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,320 INFO L290 TraceCheckUtils]: 18: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,320 INFO L290 TraceCheckUtils]: 19: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,320 INFO L290 TraceCheckUtils]: 20: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,320 INFO L290 TraceCheckUtils]: 21: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,321 INFO L290 TraceCheckUtils]: 22: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,321 INFO L290 TraceCheckUtils]: 23: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,321 INFO L290 TraceCheckUtils]: 24: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,321 INFO L290 TraceCheckUtils]: 25: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,322 INFO L290 TraceCheckUtils]: 26: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,322 INFO L290 TraceCheckUtils]: 27: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,322 INFO L290 TraceCheckUtils]: 28: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,323 INFO L290 TraceCheckUtils]: 29: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,323 INFO L290 TraceCheckUtils]: 30: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,323 INFO L290 TraceCheckUtils]: 31: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,323 INFO L290 TraceCheckUtils]: 32: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,324 INFO L290 TraceCheckUtils]: 33: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,324 INFO L290 TraceCheckUtils]: 34: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,324 INFO L290 TraceCheckUtils]: 35: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,325 INFO L290 TraceCheckUtils]: 36: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,325 INFO L290 TraceCheckUtils]: 37: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,325 INFO L290 TraceCheckUtils]: 38: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,326 INFO L290 TraceCheckUtils]: 39: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,326 INFO L290 TraceCheckUtils]: 40: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,326 INFO L290 TraceCheckUtils]: 41: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,326 INFO L290 TraceCheckUtils]: 42: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,327 INFO L290 TraceCheckUtils]: 43: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,327 INFO L290 TraceCheckUtils]: 44: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,327 INFO L290 TraceCheckUtils]: 45: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,328 INFO L290 TraceCheckUtils]: 46: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,328 INFO L290 TraceCheckUtils]: 47: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,328 INFO L290 TraceCheckUtils]: 48: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,329 INFO L290 TraceCheckUtils]: 49: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,329 INFO L290 TraceCheckUtils]: 50: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,329 INFO L290 TraceCheckUtils]: 51: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,329 INFO L290 TraceCheckUtils]: 52: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,330 INFO L290 TraceCheckUtils]: 53: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,330 INFO L290 TraceCheckUtils]: 54: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,330 INFO L290 TraceCheckUtils]: 55: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,331 INFO L290 TraceCheckUtils]: 56: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,331 INFO L290 TraceCheckUtils]: 57: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,331 INFO L290 TraceCheckUtils]: 58: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,331 INFO L290 TraceCheckUtils]: 59: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,332 INFO L290 TraceCheckUtils]: 60: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,332 INFO L290 TraceCheckUtils]: 61: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,332 INFO L290 TraceCheckUtils]: 62: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,333 INFO L290 TraceCheckUtils]: 63: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,333 INFO L290 TraceCheckUtils]: 64: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,333 INFO L290 TraceCheckUtils]: 65: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,334 INFO L290 TraceCheckUtils]: 66: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,334 INFO L290 TraceCheckUtils]: 67: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,334 INFO L290 TraceCheckUtils]: 68: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,334 INFO L290 TraceCheckUtils]: 69: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,335 INFO L290 TraceCheckUtils]: 70: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,335 INFO L290 TraceCheckUtils]: 71: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,335 INFO L290 TraceCheckUtils]: 72: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,336 INFO L290 TraceCheckUtils]: 73: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,336 INFO L290 TraceCheckUtils]: 74: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,336 INFO L290 TraceCheckUtils]: 75: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,336 INFO L290 TraceCheckUtils]: 76: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,337 INFO L290 TraceCheckUtils]: 77: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,337 INFO L290 TraceCheckUtils]: 78: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,337 INFO L290 TraceCheckUtils]: 79: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,338 INFO L290 TraceCheckUtils]: 80: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,338 INFO L290 TraceCheckUtils]: 81: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,338 INFO L290 TraceCheckUtils]: 82: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,339 INFO L290 TraceCheckUtils]: 83: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,339 INFO L290 TraceCheckUtils]: 84: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,339 INFO L290 TraceCheckUtils]: 85: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,339 INFO L290 TraceCheckUtils]: 86: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,340 INFO L290 TraceCheckUtils]: 87: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,340 INFO L290 TraceCheckUtils]: 88: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,340 INFO L290 TraceCheckUtils]: 89: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,341 INFO L290 TraceCheckUtils]: 90: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,341 INFO L290 TraceCheckUtils]: 91: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,341 INFO L290 TraceCheckUtils]: 92: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,342 INFO L290 TraceCheckUtils]: 93: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,342 INFO L290 TraceCheckUtils]: 94: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,342 INFO L290 TraceCheckUtils]: 95: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,343 INFO L290 TraceCheckUtils]: 96: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,343 INFO L290 TraceCheckUtils]: 97: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,343 INFO L290 TraceCheckUtils]: 98: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,343 INFO L290 TraceCheckUtils]: 99: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,344 INFO L290 TraceCheckUtils]: 100: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,344 INFO L290 TraceCheckUtils]: 101: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,344 INFO L290 TraceCheckUtils]: 102: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,345 INFO L290 TraceCheckUtils]: 103: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,345 INFO L290 TraceCheckUtils]: 104: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,345 INFO L290 TraceCheckUtils]: 105: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,346 INFO L290 TraceCheckUtils]: 106: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,346 INFO L290 TraceCheckUtils]: 107: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,346 INFO L290 TraceCheckUtils]: 108: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,346 INFO L290 TraceCheckUtils]: 109: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,347 INFO L290 TraceCheckUtils]: 110: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,347 INFO L290 TraceCheckUtils]: 111: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,347 INFO L290 TraceCheckUtils]: 112: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,348 INFO L290 TraceCheckUtils]: 113: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,348 INFO L290 TraceCheckUtils]: 114: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,348 INFO L290 TraceCheckUtils]: 115: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,349 INFO L290 TraceCheckUtils]: 116: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,349 INFO L290 TraceCheckUtils]: 117: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t13_pc~0); {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,349 INFO L290 TraceCheckUtils]: 118: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,350 INFO L290 TraceCheckUtils]: 119: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,350 INFO L290 TraceCheckUtils]: 120: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,350 INFO L290 TraceCheckUtils]: 121: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,351 INFO L290 TraceCheckUtils]: 122: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {42442#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,351 INFO L290 TraceCheckUtils]: 123: Hoare triple {42442#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {42441#false} is VALID [2022-02-21 04:23:21,351 INFO L290 TraceCheckUtils]: 124: Hoare triple {42441#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,352 INFO L290 TraceCheckUtils]: 125: Hoare triple {42441#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,352 INFO L290 TraceCheckUtils]: 126: Hoare triple {42441#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,352 INFO L290 TraceCheckUtils]: 127: Hoare triple {42441#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,352 INFO L290 TraceCheckUtils]: 128: Hoare triple {42441#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,352 INFO L290 TraceCheckUtils]: 129: Hoare triple {42441#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,352 INFO L290 TraceCheckUtils]: 130: Hoare triple {42441#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,352 INFO L290 TraceCheckUtils]: 131: Hoare triple {42441#false} assume !(1 == ~T8_E~0); {42441#false} is VALID [2022-02-21 04:23:21,352 INFO L290 TraceCheckUtils]: 132: Hoare triple {42441#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,353 INFO L290 TraceCheckUtils]: 133: Hoare triple {42441#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,353 INFO L290 TraceCheckUtils]: 134: Hoare triple {42441#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,353 INFO L290 TraceCheckUtils]: 135: Hoare triple {42441#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,353 INFO L290 TraceCheckUtils]: 136: Hoare triple {42441#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,353 INFO L290 TraceCheckUtils]: 137: Hoare triple {42441#false} assume 1 == ~E_M~0;~E_M~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,353 INFO L290 TraceCheckUtils]: 138: Hoare triple {42441#false} assume 1 == ~E_1~0;~E_1~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,353 INFO L290 TraceCheckUtils]: 139: Hoare triple {42441#false} assume !(1 == ~E_2~0); {42441#false} is VALID [2022-02-21 04:23:21,353 INFO L290 TraceCheckUtils]: 140: Hoare triple {42441#false} assume 1 == ~E_3~0;~E_3~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,354 INFO L290 TraceCheckUtils]: 141: Hoare triple {42441#false} assume 1 == ~E_4~0;~E_4~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,354 INFO L290 TraceCheckUtils]: 142: Hoare triple {42441#false} assume 1 == ~E_5~0;~E_5~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,354 INFO L290 TraceCheckUtils]: 143: Hoare triple {42441#false} assume 1 == ~E_6~0;~E_6~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,354 INFO L290 TraceCheckUtils]: 144: Hoare triple {42441#false} assume 1 == ~E_7~0;~E_7~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,354 INFO L290 TraceCheckUtils]: 145: Hoare triple {42441#false} assume 1 == ~E_8~0;~E_8~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,354 INFO L290 TraceCheckUtils]: 146: Hoare triple {42441#false} assume 1 == ~E_9~0;~E_9~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,354 INFO L290 TraceCheckUtils]: 147: Hoare triple {42441#false} assume !(1 == ~E_10~0); {42441#false} is VALID [2022-02-21 04:23:21,354 INFO L290 TraceCheckUtils]: 148: Hoare triple {42441#false} assume 1 == ~E_11~0;~E_11~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,354 INFO L290 TraceCheckUtils]: 149: Hoare triple {42441#false} assume 1 == ~E_12~0;~E_12~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,355 INFO L290 TraceCheckUtils]: 150: Hoare triple {42441#false} assume 1 == ~E_13~0;~E_13~0 := 2; {42441#false} is VALID [2022-02-21 04:23:21,355 INFO L290 TraceCheckUtils]: 151: Hoare triple {42441#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {42441#false} is VALID [2022-02-21 04:23:21,355 INFO L290 TraceCheckUtils]: 152: Hoare triple {42441#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {42441#false} is VALID [2022-02-21 04:23:21,355 INFO L290 TraceCheckUtils]: 153: Hoare triple {42441#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {42441#false} is VALID [2022-02-21 04:23:21,355 INFO L290 TraceCheckUtils]: 154: Hoare triple {42441#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {42441#false} is VALID [2022-02-21 04:23:21,355 INFO L290 TraceCheckUtils]: 155: Hoare triple {42441#false} assume !(0 == start_simulation_~tmp~3#1); {42441#false} is VALID [2022-02-21 04:23:21,355 INFO L290 TraceCheckUtils]: 156: Hoare triple {42441#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {42441#false} is VALID [2022-02-21 04:23:21,355 INFO L290 TraceCheckUtils]: 157: Hoare triple {42441#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {42441#false} is VALID [2022-02-21 04:23:21,355 INFO L290 TraceCheckUtils]: 158: Hoare triple {42441#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {42441#false} is VALID [2022-02-21 04:23:21,356 INFO L290 TraceCheckUtils]: 159: Hoare triple {42441#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {42441#false} is VALID [2022-02-21 04:23:21,356 INFO L290 TraceCheckUtils]: 160: Hoare triple {42441#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {42441#false} is VALID [2022-02-21 04:23:21,356 INFO L290 TraceCheckUtils]: 161: Hoare triple {42441#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {42441#false} is VALID [2022-02-21 04:23:21,356 INFO L290 TraceCheckUtils]: 162: Hoare triple {42441#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {42441#false} is VALID [2022-02-21 04:23:21,356 INFO L290 TraceCheckUtils]: 163: Hoare triple {42441#false} assume !(0 != start_simulation_~tmp___0~1#1); {42441#false} is VALID [2022-02-21 04:23:21,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,357 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,357 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475437927] [2022-02-21 04:23:21,357 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475437927] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,357 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,357 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,357 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [871365069] [2022-02-21 04:23:21,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,358 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:21,358 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:21,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:21,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:21,359 INFO L87 Difference]: Start difference. First operand 2018 states and 2983 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:22,891 INFO L93 Difference]: Finished difference Result 2018 states and 2982 transitions. [2022-02-21 04:23:22,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:22,891 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,969 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:22,971 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2982 transitions. [2022-02-21 04:23:23,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:23,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2982 transitions. [2022-02-21 04:23:23,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:23,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:23,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2982 transitions. [2022-02-21 04:23:23,203 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:23,203 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2022-02-21 04:23:23,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2982 transitions. [2022-02-21 04:23:23,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:23,238 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:23,240 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2982 transitions. Second operand has 2018 states, 2018 states have (on average 1.4777006937561943) internal successors, (2982), 2017 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,241 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2982 transitions. Second operand has 2018 states, 2018 states have (on average 1.4777006937561943) internal successors, (2982), 2017 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,242 INFO L87 Difference]: Start difference. First operand 2018 states and 2982 transitions. Second operand has 2018 states, 2018 states have (on average 1.4777006937561943) internal successors, (2982), 2017 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:23,323 INFO L93 Difference]: Finished difference Result 2018 states and 2982 transitions. [2022-02-21 04:23:23,324 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2982 transitions. [2022-02-21 04:23:23,325 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:23,325 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:23,327 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.4777006937561943) internal successors, (2982), 2017 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2982 transitions. [2022-02-21 04:23:23,328 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.4777006937561943) internal successors, (2982), 2017 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2982 transitions. [2022-02-21 04:23:23,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:23,441 INFO L93 Difference]: Finished difference Result 2018 states and 2982 transitions. [2022-02-21 04:23:23,442 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2982 transitions. [2022-02-21 04:23:23,443 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:23,443 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:23,443 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:23,443 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:23,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4777006937561943) internal successors, (2982), 2017 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2982 transitions. [2022-02-21 04:23:23,530 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2022-02-21 04:23:23,530 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2022-02-21 04:23:23,530 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:23:23,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2982 transitions. [2022-02-21 04:23:23,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:23,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:23,534 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:23,535 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:23,535 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:23,535 INFO L791 eck$LassoCheckResult]: Stem: 45376#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46413#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45868#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45869#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 45358#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45359#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45425#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45426#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45864#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45865#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 45391#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 45210#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 45211#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45655#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 45656#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 45531#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45532#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45181#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45182#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 46405#L1279-2 assume !(0 == ~T1_E~0); 44804#L1284-1 assume !(0 == ~T2_E~0); 44805#L1289-1 assume !(0 == ~T3_E~0); 45528#L1294-1 assume !(0 == ~T4_E~0); 45529#L1299-1 assume !(0 == ~T5_E~0); 45540#L1304-1 assume !(0 == ~T6_E~0); 46471#L1309-1 assume !(0 == ~T7_E~0); 46472#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44734#L1319-1 assume !(0 == ~T9_E~0); 44735#L1324-1 assume !(0 == ~T10_E~0); 44907#L1329-1 assume !(0 == ~T11_E~0); 44908#L1334-1 assume !(0 == ~T12_E~0); 46312#L1339-1 assume !(0 == ~T13_E~0); 46393#L1344-1 assume !(0 == ~E_M~0); 46394#L1349-1 assume !(0 == ~E_1~0); 45715#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 45716#L1359-1 assume !(0 == ~E_3~0); 46145#L1364-1 assume !(0 == ~E_4~0); 45036#L1369-1 assume !(0 == ~E_5~0); 45037#L1374-1 assume !(0 == ~E_6~0); 45720#L1379-1 assume !(0 == ~E_7~0); 45721#L1384-1 assume !(0 == ~E_8~0); 45798#L1389-1 assume !(0 == ~E_9~0); 46331#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46332#L1399-1 assume !(0 == ~E_11~0); 46435#L1404-1 assume !(0 == ~E_12~0); 45129#L1409-1 assume !(0 == ~E_13~0); 45130#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46427#L628 assume !(1 == ~m_pc~0); 45033#L628-2 is_master_triggered_~__retres1~0#1 := 0; 45032#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45796#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45797#L1591 assume !(0 != activate_threads_~tmp~1#1); 46440#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45584#L647 assume 1 == ~t1_pc~0; 44953#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44954#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45225#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45226#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 46380#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46381#L666 assume 1 == ~t2_pc~0; 44801#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44802#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44968#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46397#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 45916#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45917#L685 assume !(1 == ~t3_pc~0); 46022#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46021#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45644#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45645#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45766#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45252#L704 assume 1 == ~t4_pc~0; 45253#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45777#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45778#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46418#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 45637#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45638#L723 assume !(1 == ~t5_pc~0); 45760#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 45996#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46140#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45895#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 45896#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45018#L742 assume 1 == ~t6_pc~0; 45019#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45167#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45168#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44703#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 44704#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45095#L761 assume !(1 == ~t7_pc~0); 45096#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 44964#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44965#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45767#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 45768#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44728#L780 assume 1 == ~t8_pc~0; 44729#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45004#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45005#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45728#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 45729#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45848#L799 assume 1 == ~t9_pc~0; 45960#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44731#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44732#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45860#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 46067#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45878#L818 assume !(1 == ~t10_pc~0); 44512#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44513#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45953#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45882#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45883#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45923#L837 assume 1 == ~t11_pc~0; 45924#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45758#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46161#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45841#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 45842#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45593#L856 assume !(1 == ~t12_pc~0); 45594#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 46247#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46248#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46228#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 46229#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46408#L875 assume 1 == ~t13_pc~0; 45538#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45170#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45171#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45110#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 45111#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45950#L1427 assume !(1 == ~M_E~0); 45934#L1427-2 assume !(1 == ~T1_E~0); 45082#L1432-1 assume !(1 == ~T2_E~0); 45083#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46151#L1442-1 assume !(1 == ~T4_E~0); 46152#L1447-1 assume !(1 == ~T5_E~0); 46007#L1452-1 assume !(1 == ~T6_E~0); 44647#L1457-1 assume !(1 == ~T7_E~0); 44648#L1462-1 assume !(1 == ~T8_E~0); 46178#L1467-1 assume !(1 == ~T9_E~0); 46196#L1472-1 assume !(1 == ~T10_E~0); 46197#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45948#L1482-1 assume !(1 == ~T12_E~0); 45949#L1487-1 assume !(1 == ~T13_E~0); 44978#L1492-1 assume !(1 == ~E_M~0); 44979#L1497-1 assume !(1 == ~E_1~0); 45340#L1502-1 assume !(1 == ~E_2~0); 45341#L1507-1 assume !(1 == ~E_3~0); 44856#L1512-1 assume !(1 == ~E_4~0); 44857#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46267#L1522-1 assume !(1 == ~E_6~0); 45581#L1527-1 assume !(1 == ~E_7~0); 45582#L1532-1 assume !(1 == ~E_8~0); 46455#L1537-1 assume !(1 == ~E_9~0); 45784#L1542-1 assume !(1 == ~E_10~0); 45615#L1547-1 assume !(1 == ~E_11~0); 45616#L1552-1 assume !(1 == ~E_12~0); 44551#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 44552#L1562-1 assume { :end_inline_reset_delta_events } true; 45158#L1928-2 [2022-02-21 04:23:23,536 INFO L793 eck$LassoCheckResult]: Loop: 45158#L1928-2 assume !false; 45649#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44812#L1254 assume !false; 45399#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44886#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44887#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45084#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46255#L1067 assume !(0 != eval_~tmp~0#1); 45325#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44902#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44903#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45362#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45344#L1284-3 assume !(0 == ~T2_E~0); 45345#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45323#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45324#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45711#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45712#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45221#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45222#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46218#L1324-3 assume !(0 == ~T10_E~0); 44853#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44854#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45621#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45622#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45920#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45202#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45203#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45931#L1364-3 assume !(0 == ~E_4~0); 46453#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46349#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44982#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44983#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45200#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45201#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45491#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46359#L1404-3 assume !(0 == ~E_12~0); 46323#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46324#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45810#L628-45 assume 1 == ~m_pc~0; 45488#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45490#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44847#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44848#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45236#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45959#L647-45 assume !(1 == ~t1_pc~0); 44800#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 44799#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45727#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44912#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44913#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45124#L666-45 assume !(1 == ~t2_pc~0); 45125#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 45606#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46168#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46083#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46077#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44662#L685-45 assume 1 == ~t3_pc~0; 44663#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45722#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46396#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46265#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46266#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46406#L704-45 assume !(1 == ~t4_pc~0); 44528#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 44529#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45388#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45731#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46478#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45843#L723-45 assume !(1 == ~t5_pc~0); 45844#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 46333#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45435#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45212#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 45213#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46237#L742-45 assume !(1 == ~t6_pc~0); 45459#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 45460#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45929#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45965#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45966#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46054#L761-45 assume !(1 == ~t7_pc~0); 46055#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 45453#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45454#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44860#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44861#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46327#L780-45 assume 1 == ~t8_pc~0; 45238#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44872#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44873#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46454#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44842#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44843#L799-45 assume 1 == ~t9_pc~0; 45619#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45064#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46379#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46008#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46009#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44780#L818-45 assume 1 == ~t10_pc~0; 44781#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44899#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45982#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45386#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45387#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46102#L837-45 assume !(1 == ~t11_pc~0); 45317#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45318#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45455#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46120#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44918#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44919#L856-45 assume 1 == ~t12_pc~0; 46404#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44921#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44862#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44863#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45725#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45726#L875-45 assume 1 == ~t13_pc~0; 45696#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45697#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45759#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46371#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46372#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46311#L1427-3 assume !(1 == ~M_E~0); 45522#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45523#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46061#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45713#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45714#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44570#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44571#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46253#L1462-3 assume !(1 == ~T8_E~0); 46254#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46117#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46118#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44821#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44822#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 44963#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45136#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45137#L1502-3 assume !(1 == ~E_2~0); 46085#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46216#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45174#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44866#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44867#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44831#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44832#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45932#L1542-3 assume !(1 == ~E_10~0); 46070#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45699#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 45700#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 45042#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45043#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44462#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45227#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 45228#L1947 assume !(0 == start_simulation_~tmp~3#1); 45833#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46038#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45099#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46431#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 46355#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46185#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45944#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 45945#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 45158#L1928-2 [2022-02-21 04:23:23,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:23,536 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2022-02-21 04:23:23,537 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:23,537 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73057555] [2022-02-21 04:23:23,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:23,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:23,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:23,558 INFO L290 TraceCheckUtils]: 0: Hoare triple {50518#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {50518#true} is VALID [2022-02-21 04:23:23,558 INFO L290 TraceCheckUtils]: 1: Hoare triple {50518#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {50520#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:23,558 INFO L290 TraceCheckUtils]: 2: Hoare triple {50520#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {50520#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:23,559 INFO L290 TraceCheckUtils]: 3: Hoare triple {50520#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {50520#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:23,559 INFO L290 TraceCheckUtils]: 4: Hoare triple {50520#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {50520#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:23,559 INFO L290 TraceCheckUtils]: 5: Hoare triple {50520#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {50520#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:23,559 INFO L290 TraceCheckUtils]: 6: Hoare triple {50520#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {50520#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:23,560 INFO L290 TraceCheckUtils]: 7: Hoare triple {50520#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {50520#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:23,560 INFO L290 TraceCheckUtils]: 8: Hoare triple {50520#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {50520#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:23,560 INFO L290 TraceCheckUtils]: 9: Hoare triple {50520#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {50520#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:23,560 INFO L290 TraceCheckUtils]: 10: Hoare triple {50520#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,561 INFO L290 TraceCheckUtils]: 11: Hoare triple {50519#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,561 INFO L290 TraceCheckUtils]: 12: Hoare triple {50519#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,561 INFO L290 TraceCheckUtils]: 13: Hoare triple {50519#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {50519#false} is VALID [2022-02-21 04:23:23,561 INFO L290 TraceCheckUtils]: 14: Hoare triple {50519#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,561 INFO L290 TraceCheckUtils]: 15: Hoare triple {50519#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,561 INFO L290 TraceCheckUtils]: 16: Hoare triple {50519#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,561 INFO L290 TraceCheckUtils]: 17: Hoare triple {50519#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,561 INFO L290 TraceCheckUtils]: 18: Hoare triple {50519#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {50519#false} is VALID [2022-02-21 04:23:23,561 INFO L290 TraceCheckUtils]: 19: Hoare triple {50519#false} assume 0 == ~M_E~0;~M_E~0 := 1; {50519#false} is VALID [2022-02-21 04:23:23,561 INFO L290 TraceCheckUtils]: 20: Hoare triple {50519#false} assume !(0 == ~T1_E~0); {50519#false} is VALID [2022-02-21 04:23:23,562 INFO L290 TraceCheckUtils]: 21: Hoare triple {50519#false} assume !(0 == ~T2_E~0); {50519#false} is VALID [2022-02-21 04:23:23,562 INFO L290 TraceCheckUtils]: 22: Hoare triple {50519#false} assume !(0 == ~T3_E~0); {50519#false} is VALID [2022-02-21 04:23:23,562 INFO L290 TraceCheckUtils]: 23: Hoare triple {50519#false} assume !(0 == ~T4_E~0); {50519#false} is VALID [2022-02-21 04:23:23,562 INFO L290 TraceCheckUtils]: 24: Hoare triple {50519#false} assume !(0 == ~T5_E~0); {50519#false} is VALID [2022-02-21 04:23:23,562 INFO L290 TraceCheckUtils]: 25: Hoare triple {50519#false} assume !(0 == ~T6_E~0); {50519#false} is VALID [2022-02-21 04:23:23,562 INFO L290 TraceCheckUtils]: 26: Hoare triple {50519#false} assume !(0 == ~T7_E~0); {50519#false} is VALID [2022-02-21 04:23:23,562 INFO L290 TraceCheckUtils]: 27: Hoare triple {50519#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {50519#false} is VALID [2022-02-21 04:23:23,562 INFO L290 TraceCheckUtils]: 28: Hoare triple {50519#false} assume !(0 == ~T9_E~0); {50519#false} is VALID [2022-02-21 04:23:23,562 INFO L290 TraceCheckUtils]: 29: Hoare triple {50519#false} assume !(0 == ~T10_E~0); {50519#false} is VALID [2022-02-21 04:23:23,562 INFO L290 TraceCheckUtils]: 30: Hoare triple {50519#false} assume !(0 == ~T11_E~0); {50519#false} is VALID [2022-02-21 04:23:23,563 INFO L290 TraceCheckUtils]: 31: Hoare triple {50519#false} assume !(0 == ~T12_E~0); {50519#false} is VALID [2022-02-21 04:23:23,563 INFO L290 TraceCheckUtils]: 32: Hoare triple {50519#false} assume !(0 == ~T13_E~0); {50519#false} is VALID [2022-02-21 04:23:23,563 INFO L290 TraceCheckUtils]: 33: Hoare triple {50519#false} assume !(0 == ~E_M~0); {50519#false} is VALID [2022-02-21 04:23:23,563 INFO L290 TraceCheckUtils]: 34: Hoare triple {50519#false} assume !(0 == ~E_1~0); {50519#false} is VALID [2022-02-21 04:23:23,563 INFO L290 TraceCheckUtils]: 35: Hoare triple {50519#false} assume 0 == ~E_2~0;~E_2~0 := 1; {50519#false} is VALID [2022-02-21 04:23:23,563 INFO L290 TraceCheckUtils]: 36: Hoare triple {50519#false} assume !(0 == ~E_3~0); {50519#false} is VALID [2022-02-21 04:23:23,563 INFO L290 TraceCheckUtils]: 37: Hoare triple {50519#false} assume !(0 == ~E_4~0); {50519#false} is VALID [2022-02-21 04:23:23,563 INFO L290 TraceCheckUtils]: 38: Hoare triple {50519#false} assume !(0 == ~E_5~0); {50519#false} is VALID [2022-02-21 04:23:23,563 INFO L290 TraceCheckUtils]: 39: Hoare triple {50519#false} assume !(0 == ~E_6~0); {50519#false} is VALID [2022-02-21 04:23:23,563 INFO L290 TraceCheckUtils]: 40: Hoare triple {50519#false} assume !(0 == ~E_7~0); {50519#false} is VALID [2022-02-21 04:23:23,564 INFO L290 TraceCheckUtils]: 41: Hoare triple {50519#false} assume !(0 == ~E_8~0); {50519#false} is VALID [2022-02-21 04:23:23,564 INFO L290 TraceCheckUtils]: 42: Hoare triple {50519#false} assume !(0 == ~E_9~0); {50519#false} is VALID [2022-02-21 04:23:23,564 INFO L290 TraceCheckUtils]: 43: Hoare triple {50519#false} assume 0 == ~E_10~0;~E_10~0 := 1; {50519#false} is VALID [2022-02-21 04:23:23,564 INFO L290 TraceCheckUtils]: 44: Hoare triple {50519#false} assume !(0 == ~E_11~0); {50519#false} is VALID [2022-02-21 04:23:23,564 INFO L290 TraceCheckUtils]: 45: Hoare triple {50519#false} assume !(0 == ~E_12~0); {50519#false} is VALID [2022-02-21 04:23:23,564 INFO L290 TraceCheckUtils]: 46: Hoare triple {50519#false} assume !(0 == ~E_13~0); {50519#false} is VALID [2022-02-21 04:23:23,564 INFO L290 TraceCheckUtils]: 47: Hoare triple {50519#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {50519#false} is VALID [2022-02-21 04:23:23,564 INFO L290 TraceCheckUtils]: 48: Hoare triple {50519#false} assume !(1 == ~m_pc~0); {50519#false} is VALID [2022-02-21 04:23:23,564 INFO L290 TraceCheckUtils]: 49: Hoare triple {50519#false} is_master_triggered_~__retres1~0#1 := 0; {50519#false} is VALID [2022-02-21 04:23:23,564 INFO L290 TraceCheckUtils]: 50: Hoare triple {50519#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {50519#false} is VALID [2022-02-21 04:23:23,565 INFO L290 TraceCheckUtils]: 51: Hoare triple {50519#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {50519#false} is VALID [2022-02-21 04:23:23,565 INFO L290 TraceCheckUtils]: 52: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp~1#1); {50519#false} is VALID [2022-02-21 04:23:23,565 INFO L290 TraceCheckUtils]: 53: Hoare triple {50519#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {50519#false} is VALID [2022-02-21 04:23:23,565 INFO L290 TraceCheckUtils]: 54: Hoare triple {50519#false} assume 1 == ~t1_pc~0; {50519#false} is VALID [2022-02-21 04:23:23,565 INFO L290 TraceCheckUtils]: 55: Hoare triple {50519#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {50519#false} is VALID [2022-02-21 04:23:23,565 INFO L290 TraceCheckUtils]: 56: Hoare triple {50519#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {50519#false} is VALID [2022-02-21 04:23:23,565 INFO L290 TraceCheckUtils]: 57: Hoare triple {50519#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {50519#false} is VALID [2022-02-21 04:23:23,565 INFO L290 TraceCheckUtils]: 58: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___0~0#1); {50519#false} is VALID [2022-02-21 04:23:23,565 INFO L290 TraceCheckUtils]: 59: Hoare triple {50519#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {50519#false} is VALID [2022-02-21 04:23:23,565 INFO L290 TraceCheckUtils]: 60: Hoare triple {50519#false} assume 1 == ~t2_pc~0; {50519#false} is VALID [2022-02-21 04:23:23,566 INFO L290 TraceCheckUtils]: 61: Hoare triple {50519#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {50519#false} is VALID [2022-02-21 04:23:23,566 INFO L290 TraceCheckUtils]: 62: Hoare triple {50519#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {50519#false} is VALID [2022-02-21 04:23:23,566 INFO L290 TraceCheckUtils]: 63: Hoare triple {50519#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {50519#false} is VALID [2022-02-21 04:23:23,566 INFO L290 TraceCheckUtils]: 64: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___1~0#1); {50519#false} is VALID [2022-02-21 04:23:23,566 INFO L290 TraceCheckUtils]: 65: Hoare triple {50519#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {50519#false} is VALID [2022-02-21 04:23:23,566 INFO L290 TraceCheckUtils]: 66: Hoare triple {50519#false} assume !(1 == ~t3_pc~0); {50519#false} is VALID [2022-02-21 04:23:23,566 INFO L290 TraceCheckUtils]: 67: Hoare triple {50519#false} is_transmit3_triggered_~__retres1~3#1 := 0; {50519#false} is VALID [2022-02-21 04:23:23,566 INFO L290 TraceCheckUtils]: 68: Hoare triple {50519#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {50519#false} is VALID [2022-02-21 04:23:23,566 INFO L290 TraceCheckUtils]: 69: Hoare triple {50519#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {50519#false} is VALID [2022-02-21 04:23:23,566 INFO L290 TraceCheckUtils]: 70: Hoare triple {50519#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {50519#false} is VALID [2022-02-21 04:23:23,567 INFO L290 TraceCheckUtils]: 71: Hoare triple {50519#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {50519#false} is VALID [2022-02-21 04:23:23,567 INFO L290 TraceCheckUtils]: 72: Hoare triple {50519#false} assume 1 == ~t4_pc~0; {50519#false} is VALID [2022-02-21 04:23:23,567 INFO L290 TraceCheckUtils]: 73: Hoare triple {50519#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {50519#false} is VALID [2022-02-21 04:23:23,567 INFO L290 TraceCheckUtils]: 74: Hoare triple {50519#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {50519#false} is VALID [2022-02-21 04:23:23,567 INFO L290 TraceCheckUtils]: 75: Hoare triple {50519#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {50519#false} is VALID [2022-02-21 04:23:23,567 INFO L290 TraceCheckUtils]: 76: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___3~0#1); {50519#false} is VALID [2022-02-21 04:23:23,567 INFO L290 TraceCheckUtils]: 77: Hoare triple {50519#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {50519#false} is VALID [2022-02-21 04:23:23,567 INFO L290 TraceCheckUtils]: 78: Hoare triple {50519#false} assume !(1 == ~t5_pc~0); {50519#false} is VALID [2022-02-21 04:23:23,567 INFO L290 TraceCheckUtils]: 79: Hoare triple {50519#false} is_transmit5_triggered_~__retres1~5#1 := 0; {50519#false} is VALID [2022-02-21 04:23:23,567 INFO L290 TraceCheckUtils]: 80: Hoare triple {50519#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {50519#false} is VALID [2022-02-21 04:23:23,568 INFO L290 TraceCheckUtils]: 81: Hoare triple {50519#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {50519#false} is VALID [2022-02-21 04:23:23,568 INFO L290 TraceCheckUtils]: 82: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___4~0#1); {50519#false} is VALID [2022-02-21 04:23:23,568 INFO L290 TraceCheckUtils]: 83: Hoare triple {50519#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {50519#false} is VALID [2022-02-21 04:23:23,568 INFO L290 TraceCheckUtils]: 84: Hoare triple {50519#false} assume 1 == ~t6_pc~0; {50519#false} is VALID [2022-02-21 04:23:23,568 INFO L290 TraceCheckUtils]: 85: Hoare triple {50519#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {50519#false} is VALID [2022-02-21 04:23:23,568 INFO L290 TraceCheckUtils]: 86: Hoare triple {50519#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {50519#false} is VALID [2022-02-21 04:23:23,568 INFO L290 TraceCheckUtils]: 87: Hoare triple {50519#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {50519#false} is VALID [2022-02-21 04:23:23,568 INFO L290 TraceCheckUtils]: 88: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___5~0#1); {50519#false} is VALID [2022-02-21 04:23:23,568 INFO L290 TraceCheckUtils]: 89: Hoare triple {50519#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {50519#false} is VALID [2022-02-21 04:23:23,568 INFO L290 TraceCheckUtils]: 90: Hoare triple {50519#false} assume !(1 == ~t7_pc~0); {50519#false} is VALID [2022-02-21 04:23:23,569 INFO L290 TraceCheckUtils]: 91: Hoare triple {50519#false} is_transmit7_triggered_~__retres1~7#1 := 0; {50519#false} is VALID [2022-02-21 04:23:23,569 INFO L290 TraceCheckUtils]: 92: Hoare triple {50519#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {50519#false} is VALID [2022-02-21 04:23:23,569 INFO L290 TraceCheckUtils]: 93: Hoare triple {50519#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {50519#false} is VALID [2022-02-21 04:23:23,569 INFO L290 TraceCheckUtils]: 94: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___6~0#1); {50519#false} is VALID [2022-02-21 04:23:23,569 INFO L290 TraceCheckUtils]: 95: Hoare triple {50519#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {50519#false} is VALID [2022-02-21 04:23:23,569 INFO L290 TraceCheckUtils]: 96: Hoare triple {50519#false} assume 1 == ~t8_pc~0; {50519#false} is VALID [2022-02-21 04:23:23,569 INFO L290 TraceCheckUtils]: 97: Hoare triple {50519#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {50519#false} is VALID [2022-02-21 04:23:23,569 INFO L290 TraceCheckUtils]: 98: Hoare triple {50519#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {50519#false} is VALID [2022-02-21 04:23:23,569 INFO L290 TraceCheckUtils]: 99: Hoare triple {50519#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {50519#false} is VALID [2022-02-21 04:23:23,569 INFO L290 TraceCheckUtils]: 100: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___7~0#1); {50519#false} is VALID [2022-02-21 04:23:23,570 INFO L290 TraceCheckUtils]: 101: Hoare triple {50519#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {50519#false} is VALID [2022-02-21 04:23:23,570 INFO L290 TraceCheckUtils]: 102: Hoare triple {50519#false} assume 1 == ~t9_pc~0; {50519#false} is VALID [2022-02-21 04:23:23,570 INFO L290 TraceCheckUtils]: 103: Hoare triple {50519#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {50519#false} is VALID [2022-02-21 04:23:23,570 INFO L290 TraceCheckUtils]: 104: Hoare triple {50519#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {50519#false} is VALID [2022-02-21 04:23:23,570 INFO L290 TraceCheckUtils]: 105: Hoare triple {50519#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {50519#false} is VALID [2022-02-21 04:23:23,570 INFO L290 TraceCheckUtils]: 106: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___8~0#1); {50519#false} is VALID [2022-02-21 04:23:23,570 INFO L290 TraceCheckUtils]: 107: Hoare triple {50519#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {50519#false} is VALID [2022-02-21 04:23:23,570 INFO L290 TraceCheckUtils]: 108: Hoare triple {50519#false} assume !(1 == ~t10_pc~0); {50519#false} is VALID [2022-02-21 04:23:23,570 INFO L290 TraceCheckUtils]: 109: Hoare triple {50519#false} is_transmit10_triggered_~__retres1~10#1 := 0; {50519#false} is VALID [2022-02-21 04:23:23,571 INFO L290 TraceCheckUtils]: 110: Hoare triple {50519#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {50519#false} is VALID [2022-02-21 04:23:23,571 INFO L290 TraceCheckUtils]: 111: Hoare triple {50519#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {50519#false} is VALID [2022-02-21 04:23:23,571 INFO L290 TraceCheckUtils]: 112: Hoare triple {50519#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {50519#false} is VALID [2022-02-21 04:23:23,571 INFO L290 TraceCheckUtils]: 113: Hoare triple {50519#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {50519#false} is VALID [2022-02-21 04:23:23,571 INFO L290 TraceCheckUtils]: 114: Hoare triple {50519#false} assume 1 == ~t11_pc~0; {50519#false} is VALID [2022-02-21 04:23:23,571 INFO L290 TraceCheckUtils]: 115: Hoare triple {50519#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {50519#false} is VALID [2022-02-21 04:23:23,571 INFO L290 TraceCheckUtils]: 116: Hoare triple {50519#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {50519#false} is VALID [2022-02-21 04:23:23,571 INFO L290 TraceCheckUtils]: 117: Hoare triple {50519#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {50519#false} is VALID [2022-02-21 04:23:23,571 INFO L290 TraceCheckUtils]: 118: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___10~0#1); {50519#false} is VALID [2022-02-21 04:23:23,571 INFO L290 TraceCheckUtils]: 119: Hoare triple {50519#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {50519#false} is VALID [2022-02-21 04:23:23,572 INFO L290 TraceCheckUtils]: 120: Hoare triple {50519#false} assume !(1 == ~t12_pc~0); {50519#false} is VALID [2022-02-21 04:23:23,572 INFO L290 TraceCheckUtils]: 121: Hoare triple {50519#false} is_transmit12_triggered_~__retres1~12#1 := 0; {50519#false} is VALID [2022-02-21 04:23:23,572 INFO L290 TraceCheckUtils]: 122: Hoare triple {50519#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {50519#false} is VALID [2022-02-21 04:23:23,572 INFO L290 TraceCheckUtils]: 123: Hoare triple {50519#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {50519#false} is VALID [2022-02-21 04:23:23,572 INFO L290 TraceCheckUtils]: 124: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___11~0#1); {50519#false} is VALID [2022-02-21 04:23:23,572 INFO L290 TraceCheckUtils]: 125: Hoare triple {50519#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {50519#false} is VALID [2022-02-21 04:23:23,572 INFO L290 TraceCheckUtils]: 126: Hoare triple {50519#false} assume 1 == ~t13_pc~0; {50519#false} is VALID [2022-02-21 04:23:23,572 INFO L290 TraceCheckUtils]: 127: Hoare triple {50519#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {50519#false} is VALID [2022-02-21 04:23:23,572 INFO L290 TraceCheckUtils]: 128: Hoare triple {50519#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {50519#false} is VALID [2022-02-21 04:23:23,572 INFO L290 TraceCheckUtils]: 129: Hoare triple {50519#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {50519#false} is VALID [2022-02-21 04:23:23,573 INFO L290 TraceCheckUtils]: 130: Hoare triple {50519#false} assume !(0 != activate_threads_~tmp___12~0#1); {50519#false} is VALID [2022-02-21 04:23:23,573 INFO L290 TraceCheckUtils]: 131: Hoare triple {50519#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {50519#false} is VALID [2022-02-21 04:23:23,573 INFO L290 TraceCheckUtils]: 132: Hoare triple {50519#false} assume !(1 == ~M_E~0); {50519#false} is VALID [2022-02-21 04:23:23,573 INFO L290 TraceCheckUtils]: 133: Hoare triple {50519#false} assume !(1 == ~T1_E~0); {50519#false} is VALID [2022-02-21 04:23:23,573 INFO L290 TraceCheckUtils]: 134: Hoare triple {50519#false} assume !(1 == ~T2_E~0); {50519#false} is VALID [2022-02-21 04:23:23,573 INFO L290 TraceCheckUtils]: 135: Hoare triple {50519#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,573 INFO L290 TraceCheckUtils]: 136: Hoare triple {50519#false} assume !(1 == ~T4_E~0); {50519#false} is VALID [2022-02-21 04:23:23,573 INFO L290 TraceCheckUtils]: 137: Hoare triple {50519#false} assume !(1 == ~T5_E~0); {50519#false} is VALID [2022-02-21 04:23:23,573 INFO L290 TraceCheckUtils]: 138: Hoare triple {50519#false} assume !(1 == ~T6_E~0); {50519#false} is VALID [2022-02-21 04:23:23,573 INFO L290 TraceCheckUtils]: 139: Hoare triple {50519#false} assume !(1 == ~T7_E~0); {50519#false} is VALID [2022-02-21 04:23:23,574 INFO L290 TraceCheckUtils]: 140: Hoare triple {50519#false} assume !(1 == ~T8_E~0); {50519#false} is VALID [2022-02-21 04:23:23,574 INFO L290 TraceCheckUtils]: 141: Hoare triple {50519#false} assume !(1 == ~T9_E~0); {50519#false} is VALID [2022-02-21 04:23:23,574 INFO L290 TraceCheckUtils]: 142: Hoare triple {50519#false} assume !(1 == ~T10_E~0); {50519#false} is VALID [2022-02-21 04:23:23,574 INFO L290 TraceCheckUtils]: 143: Hoare triple {50519#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,574 INFO L290 TraceCheckUtils]: 144: Hoare triple {50519#false} assume !(1 == ~T12_E~0); {50519#false} is VALID [2022-02-21 04:23:23,574 INFO L290 TraceCheckUtils]: 145: Hoare triple {50519#false} assume !(1 == ~T13_E~0); {50519#false} is VALID [2022-02-21 04:23:23,574 INFO L290 TraceCheckUtils]: 146: Hoare triple {50519#false} assume !(1 == ~E_M~0); {50519#false} is VALID [2022-02-21 04:23:23,574 INFO L290 TraceCheckUtils]: 147: Hoare triple {50519#false} assume !(1 == ~E_1~0); {50519#false} is VALID [2022-02-21 04:23:23,574 INFO L290 TraceCheckUtils]: 148: Hoare triple {50519#false} assume !(1 == ~E_2~0); {50519#false} is VALID [2022-02-21 04:23:23,574 INFO L290 TraceCheckUtils]: 149: Hoare triple {50519#false} assume !(1 == ~E_3~0); {50519#false} is VALID [2022-02-21 04:23:23,575 INFO L290 TraceCheckUtils]: 150: Hoare triple {50519#false} assume !(1 == ~E_4~0); {50519#false} is VALID [2022-02-21 04:23:23,575 INFO L290 TraceCheckUtils]: 151: Hoare triple {50519#false} assume 1 == ~E_5~0;~E_5~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,575 INFO L290 TraceCheckUtils]: 152: Hoare triple {50519#false} assume !(1 == ~E_6~0); {50519#false} is VALID [2022-02-21 04:23:23,575 INFO L290 TraceCheckUtils]: 153: Hoare triple {50519#false} assume !(1 == ~E_7~0); {50519#false} is VALID [2022-02-21 04:23:23,575 INFO L290 TraceCheckUtils]: 154: Hoare triple {50519#false} assume !(1 == ~E_8~0); {50519#false} is VALID [2022-02-21 04:23:23,575 INFO L290 TraceCheckUtils]: 155: Hoare triple {50519#false} assume !(1 == ~E_9~0); {50519#false} is VALID [2022-02-21 04:23:23,575 INFO L290 TraceCheckUtils]: 156: Hoare triple {50519#false} assume !(1 == ~E_10~0); {50519#false} is VALID [2022-02-21 04:23:23,575 INFO L290 TraceCheckUtils]: 157: Hoare triple {50519#false} assume !(1 == ~E_11~0); {50519#false} is VALID [2022-02-21 04:23:23,575 INFO L290 TraceCheckUtils]: 158: Hoare triple {50519#false} assume !(1 == ~E_12~0); {50519#false} is VALID [2022-02-21 04:23:23,575 INFO L290 TraceCheckUtils]: 159: Hoare triple {50519#false} assume 1 == ~E_13~0;~E_13~0 := 2; {50519#false} is VALID [2022-02-21 04:23:23,576 INFO L290 TraceCheckUtils]: 160: Hoare triple {50519#false} assume { :end_inline_reset_delta_events } true; {50519#false} is VALID [2022-02-21 04:23:23,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:23,576 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:23,576 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73057555] [2022-02-21 04:23:23,576 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [73057555] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:23,576 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:23,576 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:23,577 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538240411] [2022-02-21 04:23:23,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:23,577 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:23,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:23,577 INFO L85 PathProgramCache]: Analyzing trace with hash 975518447, now seen corresponding path program 1 times [2022-02-21 04:23:23,577 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:23,578 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160802128] [2022-02-21 04:23:23,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:23,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:23,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:23,602 INFO L290 TraceCheckUtils]: 0: Hoare triple {50521#true} assume !false; {50521#true} is VALID [2022-02-21 04:23:23,602 INFO L290 TraceCheckUtils]: 1: Hoare triple {50521#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {50521#true} is VALID [2022-02-21 04:23:23,602 INFO L290 TraceCheckUtils]: 2: Hoare triple {50521#true} assume !false; {50521#true} is VALID [2022-02-21 04:23:23,602 INFO L290 TraceCheckUtils]: 3: Hoare triple {50521#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {50521#true} is VALID [2022-02-21 04:23:23,602 INFO L290 TraceCheckUtils]: 4: Hoare triple {50521#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {50521#true} is VALID [2022-02-21 04:23:23,602 INFO L290 TraceCheckUtils]: 5: Hoare triple {50521#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {50521#true} is VALID [2022-02-21 04:23:23,602 INFO L290 TraceCheckUtils]: 6: Hoare triple {50521#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {50521#true} is VALID [2022-02-21 04:23:23,603 INFO L290 TraceCheckUtils]: 7: Hoare triple {50521#true} assume !(0 != eval_~tmp~0#1); {50521#true} is VALID [2022-02-21 04:23:23,603 INFO L290 TraceCheckUtils]: 8: Hoare triple {50521#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {50521#true} is VALID [2022-02-21 04:23:23,603 INFO L290 TraceCheckUtils]: 9: Hoare triple {50521#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {50521#true} is VALID [2022-02-21 04:23:23,603 INFO L290 TraceCheckUtils]: 10: Hoare triple {50521#true} assume 0 == ~M_E~0;~M_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,603 INFO L290 TraceCheckUtils]: 11: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,604 INFO L290 TraceCheckUtils]: 12: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,604 INFO L290 TraceCheckUtils]: 13: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,604 INFO L290 TraceCheckUtils]: 14: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,604 INFO L290 TraceCheckUtils]: 15: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,605 INFO L290 TraceCheckUtils]: 16: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,605 INFO L290 TraceCheckUtils]: 17: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,605 INFO L290 TraceCheckUtils]: 18: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,605 INFO L290 TraceCheckUtils]: 19: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,606 INFO L290 TraceCheckUtils]: 20: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,606 INFO L290 TraceCheckUtils]: 21: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,606 INFO L290 TraceCheckUtils]: 22: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,606 INFO L290 TraceCheckUtils]: 23: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,607 INFO L290 TraceCheckUtils]: 24: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,607 INFO L290 TraceCheckUtils]: 25: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,607 INFO L290 TraceCheckUtils]: 26: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,607 INFO L290 TraceCheckUtils]: 27: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,608 INFO L290 TraceCheckUtils]: 28: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,608 INFO L290 TraceCheckUtils]: 29: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,608 INFO L290 TraceCheckUtils]: 30: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,608 INFO L290 TraceCheckUtils]: 31: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,609 INFO L290 TraceCheckUtils]: 32: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,609 INFO L290 TraceCheckUtils]: 33: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,609 INFO L290 TraceCheckUtils]: 34: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,610 INFO L290 TraceCheckUtils]: 35: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,610 INFO L290 TraceCheckUtils]: 36: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,610 INFO L290 TraceCheckUtils]: 37: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,610 INFO L290 TraceCheckUtils]: 38: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,611 INFO L290 TraceCheckUtils]: 39: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,611 INFO L290 TraceCheckUtils]: 40: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,611 INFO L290 TraceCheckUtils]: 41: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,611 INFO L290 TraceCheckUtils]: 42: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,612 INFO L290 TraceCheckUtils]: 43: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,612 INFO L290 TraceCheckUtils]: 44: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,612 INFO L290 TraceCheckUtils]: 45: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,612 INFO L290 TraceCheckUtils]: 46: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,613 INFO L290 TraceCheckUtils]: 47: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,613 INFO L290 TraceCheckUtils]: 48: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,613 INFO L290 TraceCheckUtils]: 49: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,613 INFO L290 TraceCheckUtils]: 50: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,614 INFO L290 TraceCheckUtils]: 51: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,614 INFO L290 TraceCheckUtils]: 52: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,614 INFO L290 TraceCheckUtils]: 53: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,614 INFO L290 TraceCheckUtils]: 54: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,615 INFO L290 TraceCheckUtils]: 55: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,615 INFO L290 TraceCheckUtils]: 56: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,615 INFO L290 TraceCheckUtils]: 57: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,615 INFO L290 TraceCheckUtils]: 58: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,616 INFO L290 TraceCheckUtils]: 59: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,616 INFO L290 TraceCheckUtils]: 60: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,616 INFO L290 TraceCheckUtils]: 61: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,617 INFO L290 TraceCheckUtils]: 62: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,617 INFO L290 TraceCheckUtils]: 63: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,617 INFO L290 TraceCheckUtils]: 64: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,617 INFO L290 TraceCheckUtils]: 65: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,618 INFO L290 TraceCheckUtils]: 66: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,618 INFO L290 TraceCheckUtils]: 67: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,618 INFO L290 TraceCheckUtils]: 68: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,618 INFO L290 TraceCheckUtils]: 69: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,619 INFO L290 TraceCheckUtils]: 70: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,619 INFO L290 TraceCheckUtils]: 71: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,619 INFO L290 TraceCheckUtils]: 72: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,619 INFO L290 TraceCheckUtils]: 73: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,620 INFO L290 TraceCheckUtils]: 74: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,620 INFO L290 TraceCheckUtils]: 75: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,620 INFO L290 TraceCheckUtils]: 76: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,620 INFO L290 TraceCheckUtils]: 77: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,621 INFO L290 TraceCheckUtils]: 78: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,621 INFO L290 TraceCheckUtils]: 79: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,621 INFO L290 TraceCheckUtils]: 80: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,621 INFO L290 TraceCheckUtils]: 81: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,622 INFO L290 TraceCheckUtils]: 82: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,622 INFO L290 TraceCheckUtils]: 83: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,622 INFO L290 TraceCheckUtils]: 84: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,622 INFO L290 TraceCheckUtils]: 85: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,623 INFO L290 TraceCheckUtils]: 86: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,623 INFO L290 TraceCheckUtils]: 87: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,623 INFO L290 TraceCheckUtils]: 88: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,623 INFO L290 TraceCheckUtils]: 89: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,624 INFO L290 TraceCheckUtils]: 90: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,624 INFO L290 TraceCheckUtils]: 91: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,624 INFO L290 TraceCheckUtils]: 92: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,624 INFO L290 TraceCheckUtils]: 93: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,625 INFO L290 TraceCheckUtils]: 94: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,625 INFO L290 TraceCheckUtils]: 95: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,625 INFO L290 TraceCheckUtils]: 96: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,625 INFO L290 TraceCheckUtils]: 97: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,626 INFO L290 TraceCheckUtils]: 98: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,626 INFO L290 TraceCheckUtils]: 99: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,626 INFO L290 TraceCheckUtils]: 100: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,626 INFO L290 TraceCheckUtils]: 101: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,627 INFO L290 TraceCheckUtils]: 102: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,627 INFO L290 TraceCheckUtils]: 103: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,627 INFO L290 TraceCheckUtils]: 104: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,627 INFO L290 TraceCheckUtils]: 105: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,628 INFO L290 TraceCheckUtils]: 106: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,628 INFO L290 TraceCheckUtils]: 107: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,628 INFO L290 TraceCheckUtils]: 108: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,628 INFO L290 TraceCheckUtils]: 109: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,629 INFO L290 TraceCheckUtils]: 110: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,629 INFO L290 TraceCheckUtils]: 111: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,629 INFO L290 TraceCheckUtils]: 112: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,629 INFO L290 TraceCheckUtils]: 113: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,630 INFO L290 TraceCheckUtils]: 114: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,630 INFO L290 TraceCheckUtils]: 115: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,630 INFO L290 TraceCheckUtils]: 116: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,630 INFO L290 TraceCheckUtils]: 117: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,631 INFO L290 TraceCheckUtils]: 118: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,631 INFO L290 TraceCheckUtils]: 119: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,631 INFO L290 TraceCheckUtils]: 120: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,631 INFO L290 TraceCheckUtils]: 121: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,632 INFO L290 TraceCheckUtils]: 122: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {50523#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,632 INFO L290 TraceCheckUtils]: 123: Hoare triple {50523#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {50522#false} is VALID [2022-02-21 04:23:23,632 INFO L290 TraceCheckUtils]: 124: Hoare triple {50522#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,632 INFO L290 TraceCheckUtils]: 125: Hoare triple {50522#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,632 INFO L290 TraceCheckUtils]: 126: Hoare triple {50522#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,632 INFO L290 TraceCheckUtils]: 127: Hoare triple {50522#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,632 INFO L290 TraceCheckUtils]: 128: Hoare triple {50522#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,633 INFO L290 TraceCheckUtils]: 129: Hoare triple {50522#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,633 INFO L290 TraceCheckUtils]: 130: Hoare triple {50522#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,633 INFO L290 TraceCheckUtils]: 131: Hoare triple {50522#false} assume !(1 == ~T8_E~0); {50522#false} is VALID [2022-02-21 04:23:23,633 INFO L290 TraceCheckUtils]: 132: Hoare triple {50522#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,633 INFO L290 TraceCheckUtils]: 133: Hoare triple {50522#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,633 INFO L290 TraceCheckUtils]: 134: Hoare triple {50522#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,633 INFO L290 TraceCheckUtils]: 135: Hoare triple {50522#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,633 INFO L290 TraceCheckUtils]: 136: Hoare triple {50522#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,633 INFO L290 TraceCheckUtils]: 137: Hoare triple {50522#false} assume 1 == ~E_M~0;~E_M~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,633 INFO L290 TraceCheckUtils]: 138: Hoare triple {50522#false} assume 1 == ~E_1~0;~E_1~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,634 INFO L290 TraceCheckUtils]: 139: Hoare triple {50522#false} assume !(1 == ~E_2~0); {50522#false} is VALID [2022-02-21 04:23:23,634 INFO L290 TraceCheckUtils]: 140: Hoare triple {50522#false} assume 1 == ~E_3~0;~E_3~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,634 INFO L290 TraceCheckUtils]: 141: Hoare triple {50522#false} assume 1 == ~E_4~0;~E_4~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,634 INFO L290 TraceCheckUtils]: 142: Hoare triple {50522#false} assume 1 == ~E_5~0;~E_5~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,634 INFO L290 TraceCheckUtils]: 143: Hoare triple {50522#false} assume 1 == ~E_6~0;~E_6~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,634 INFO L290 TraceCheckUtils]: 144: Hoare triple {50522#false} assume 1 == ~E_7~0;~E_7~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,634 INFO L290 TraceCheckUtils]: 145: Hoare triple {50522#false} assume 1 == ~E_8~0;~E_8~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,634 INFO L290 TraceCheckUtils]: 146: Hoare triple {50522#false} assume 1 == ~E_9~0;~E_9~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,634 INFO L290 TraceCheckUtils]: 147: Hoare triple {50522#false} assume !(1 == ~E_10~0); {50522#false} is VALID [2022-02-21 04:23:23,634 INFO L290 TraceCheckUtils]: 148: Hoare triple {50522#false} assume 1 == ~E_11~0;~E_11~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,635 INFO L290 TraceCheckUtils]: 149: Hoare triple {50522#false} assume 1 == ~E_12~0;~E_12~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,635 INFO L290 TraceCheckUtils]: 150: Hoare triple {50522#false} assume 1 == ~E_13~0;~E_13~0 := 2; {50522#false} is VALID [2022-02-21 04:23:23,635 INFO L290 TraceCheckUtils]: 151: Hoare triple {50522#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {50522#false} is VALID [2022-02-21 04:23:23,635 INFO L290 TraceCheckUtils]: 152: Hoare triple {50522#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {50522#false} is VALID [2022-02-21 04:23:23,635 INFO L290 TraceCheckUtils]: 153: Hoare triple {50522#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {50522#false} is VALID [2022-02-21 04:23:23,635 INFO L290 TraceCheckUtils]: 154: Hoare triple {50522#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {50522#false} is VALID [2022-02-21 04:23:23,635 INFO L290 TraceCheckUtils]: 155: Hoare triple {50522#false} assume !(0 == start_simulation_~tmp~3#1); {50522#false} is VALID [2022-02-21 04:23:23,635 INFO L290 TraceCheckUtils]: 156: Hoare triple {50522#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {50522#false} is VALID [2022-02-21 04:23:23,635 INFO L290 TraceCheckUtils]: 157: Hoare triple {50522#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {50522#false} is VALID [2022-02-21 04:23:23,635 INFO L290 TraceCheckUtils]: 158: Hoare triple {50522#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {50522#false} is VALID [2022-02-21 04:23:23,636 INFO L290 TraceCheckUtils]: 159: Hoare triple {50522#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {50522#false} is VALID [2022-02-21 04:23:23,636 INFO L290 TraceCheckUtils]: 160: Hoare triple {50522#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {50522#false} is VALID [2022-02-21 04:23:23,636 INFO L290 TraceCheckUtils]: 161: Hoare triple {50522#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {50522#false} is VALID [2022-02-21 04:23:23,636 INFO L290 TraceCheckUtils]: 162: Hoare triple {50522#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {50522#false} is VALID [2022-02-21 04:23:23,636 INFO L290 TraceCheckUtils]: 163: Hoare triple {50522#false} assume !(0 != start_simulation_~tmp___0~1#1); {50522#false} is VALID [2022-02-21 04:23:23,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:23,636 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:23,637 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160802128] [2022-02-21 04:23:23,637 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1160802128] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:23,637 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:23,637 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:23,637 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234356072] [2022-02-21 04:23:23,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:23,637 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:23,638 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:23,638 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:23,638 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:23,638 INFO L87 Difference]: Start difference. First operand 2018 states and 2982 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:25,111 INFO L93 Difference]: Finished difference Result 2018 states and 2981 transitions. [2022-02-21 04:23:25,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:25,112 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,202 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:25,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2981 transitions. [2022-02-21 04:23:25,318 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:25,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2981 transitions. [2022-02-21 04:23:25,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:25,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:25,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2981 transitions. [2022-02-21 04:23:25,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:25,444 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2022-02-21 04:23:25,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2981 transitions. [2022-02-21 04:23:25,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:25,460 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:25,462 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2981 transitions. Second operand has 2018 states, 2018 states have (on average 1.477205153617443) internal successors, (2981), 2017 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,463 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2981 transitions. Second operand has 2018 states, 2018 states have (on average 1.477205153617443) internal successors, (2981), 2017 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,464 INFO L87 Difference]: Start difference. First operand 2018 states and 2981 transitions. Second operand has 2018 states, 2018 states have (on average 1.477205153617443) internal successors, (2981), 2017 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:25,545 INFO L93 Difference]: Finished difference Result 2018 states and 2981 transitions. [2022-02-21 04:23:25,545 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2981 transitions. [2022-02-21 04:23:25,547 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:25,547 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:25,548 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.477205153617443) internal successors, (2981), 2017 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2981 transitions. [2022-02-21 04:23:25,549 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.477205153617443) internal successors, (2981), 2017 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2981 transitions. [2022-02-21 04:23:25,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:25,633 INFO L93 Difference]: Finished difference Result 2018 states and 2981 transitions. [2022-02-21 04:23:25,633 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2981 transitions. [2022-02-21 04:23:25,635 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:25,635 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:25,635 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:25,635 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:25,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.477205153617443) internal successors, (2981), 2017 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2981 transitions. [2022-02-21 04:23:25,718 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2022-02-21 04:23:25,718 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2022-02-21 04:23:25,718 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:23:25,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2981 transitions. [2022-02-21 04:23:25,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:25,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:25,721 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:25,722 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:25,723 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:25,723 INFO L791 eck$LassoCheckResult]: Stem: 53457#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54494#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53949#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53950#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 53439#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53440#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53506#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53507#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53945#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53946#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53472#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 53291#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 53292#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53736#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 53737#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 53612#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 53613#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 53262#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53263#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 54486#L1279-2 assume !(0 == ~T1_E~0); 52885#L1284-1 assume !(0 == ~T2_E~0); 52886#L1289-1 assume !(0 == ~T3_E~0); 53609#L1294-1 assume !(0 == ~T4_E~0); 53610#L1299-1 assume !(0 == ~T5_E~0); 53621#L1304-1 assume !(0 == ~T6_E~0); 54552#L1309-1 assume !(0 == ~T7_E~0); 54553#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52815#L1319-1 assume !(0 == ~T9_E~0); 52816#L1324-1 assume !(0 == ~T10_E~0); 52988#L1329-1 assume !(0 == ~T11_E~0); 52989#L1334-1 assume !(0 == ~T12_E~0); 54393#L1339-1 assume !(0 == ~T13_E~0); 54474#L1344-1 assume !(0 == ~E_M~0); 54475#L1349-1 assume !(0 == ~E_1~0); 53796#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 53797#L1359-1 assume !(0 == ~E_3~0); 54226#L1364-1 assume !(0 == ~E_4~0); 53117#L1369-1 assume !(0 == ~E_5~0); 53118#L1374-1 assume !(0 == ~E_6~0); 53801#L1379-1 assume !(0 == ~E_7~0); 53802#L1384-1 assume !(0 == ~E_8~0); 53879#L1389-1 assume !(0 == ~E_9~0); 54412#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54413#L1399-1 assume !(0 == ~E_11~0); 54516#L1404-1 assume !(0 == ~E_12~0); 53210#L1409-1 assume !(0 == ~E_13~0); 53211#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54508#L628 assume !(1 == ~m_pc~0); 53114#L628-2 is_master_triggered_~__retres1~0#1 := 0; 53113#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53877#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53878#L1591 assume !(0 != activate_threads_~tmp~1#1); 54521#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53665#L647 assume 1 == ~t1_pc~0; 53034#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53035#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53306#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53307#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 54461#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54462#L666 assume 1 == ~t2_pc~0; 52882#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52883#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53049#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54478#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 53997#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53998#L685 assume !(1 == ~t3_pc~0); 54103#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54102#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53725#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53726#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53847#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53333#L704 assume 1 == ~t4_pc~0; 53334#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53858#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53859#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54499#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 53718#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53719#L723 assume !(1 == ~t5_pc~0); 53841#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54077#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54221#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53976#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 53977#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53099#L742 assume 1 == ~t6_pc~0; 53100#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53248#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53249#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52784#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 52785#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53176#L761 assume !(1 == ~t7_pc~0); 53177#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53045#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53046#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53848#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 53849#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52809#L780 assume 1 == ~t8_pc~0; 52810#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53085#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53086#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53809#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 53810#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53929#L799 assume 1 == ~t9_pc~0; 54041#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52812#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52813#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53941#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 54148#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53959#L818 assume !(1 == ~t10_pc~0); 52593#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52594#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54034#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53963#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53964#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54004#L837 assume 1 == ~t11_pc~0; 54005#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53839#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54242#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53922#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 53923#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53674#L856 assume !(1 == ~t12_pc~0); 53675#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54328#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54329#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54309#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 54310#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54489#L875 assume 1 == ~t13_pc~0; 53619#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53251#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53252#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53191#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 53192#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54031#L1427 assume !(1 == ~M_E~0); 54015#L1427-2 assume !(1 == ~T1_E~0); 53163#L1432-1 assume !(1 == ~T2_E~0); 53164#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54232#L1442-1 assume !(1 == ~T4_E~0); 54233#L1447-1 assume !(1 == ~T5_E~0); 54088#L1452-1 assume !(1 == ~T6_E~0); 52728#L1457-1 assume !(1 == ~T7_E~0); 52729#L1462-1 assume !(1 == ~T8_E~0); 54259#L1467-1 assume !(1 == ~T9_E~0); 54277#L1472-1 assume !(1 == ~T10_E~0); 54278#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54029#L1482-1 assume !(1 == ~T12_E~0); 54030#L1487-1 assume !(1 == ~T13_E~0); 53059#L1492-1 assume !(1 == ~E_M~0); 53060#L1497-1 assume !(1 == ~E_1~0); 53421#L1502-1 assume !(1 == ~E_2~0); 53422#L1507-1 assume !(1 == ~E_3~0); 52937#L1512-1 assume !(1 == ~E_4~0); 52938#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54348#L1522-1 assume !(1 == ~E_6~0); 53662#L1527-1 assume !(1 == ~E_7~0); 53663#L1532-1 assume !(1 == ~E_8~0); 54536#L1537-1 assume !(1 == ~E_9~0); 53865#L1542-1 assume !(1 == ~E_10~0); 53696#L1547-1 assume !(1 == ~E_11~0); 53697#L1552-1 assume !(1 == ~E_12~0); 52632#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 52633#L1562-1 assume { :end_inline_reset_delta_events } true; 53239#L1928-2 [2022-02-21 04:23:25,723 INFO L793 eck$LassoCheckResult]: Loop: 53239#L1928-2 assume !false; 53730#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52893#L1254 assume !false; 53480#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52967#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52968#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53165#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54336#L1067 assume !(0 != eval_~tmp~0#1); 53406#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52983#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52984#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53443#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53425#L1284-3 assume !(0 == ~T2_E~0); 53426#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53404#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53405#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53792#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53793#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53302#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53303#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54299#L1324-3 assume !(0 == ~T10_E~0); 52934#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52935#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53702#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53703#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54001#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53283#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53284#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54012#L1364-3 assume !(0 == ~E_4~0); 54534#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54430#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53063#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53064#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53281#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53282#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53572#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54440#L1404-3 assume !(0 == ~E_12~0); 54404#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54405#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53891#L628-45 assume 1 == ~m_pc~0; 53569#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53571#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52928#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52929#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53317#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54040#L647-45 assume !(1 == ~t1_pc~0); 52881#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 52880#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53808#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52993#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52994#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53205#L666-45 assume !(1 == ~t2_pc~0); 53206#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 53687#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54249#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54164#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54158#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52743#L685-45 assume 1 == ~t3_pc~0; 52744#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53803#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54477#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54346#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54347#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54487#L704-45 assume !(1 == ~t4_pc~0); 52609#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 52610#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53469#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53812#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54559#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53924#L723-45 assume !(1 == ~t5_pc~0); 53925#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 54414#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53516#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53293#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 53294#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54318#L742-45 assume !(1 == ~t6_pc~0); 53540#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 53541#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54010#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54046#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54047#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54135#L761-45 assume !(1 == ~t7_pc~0); 54136#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 53534#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53535#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52941#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52942#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54408#L780-45 assume 1 == ~t8_pc~0; 53319#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52953#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52954#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54535#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52923#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52924#L799-45 assume 1 == ~t9_pc~0; 53700#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53145#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54460#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54089#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54090#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52861#L818-45 assume 1 == ~t10_pc~0; 52862#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52980#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54063#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53467#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53468#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54183#L837-45 assume !(1 == ~t11_pc~0); 53398#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53399#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53536#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54201#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52999#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53000#L856-45 assume 1 == ~t12_pc~0; 54485#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 53002#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52943#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52944#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53806#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53807#L875-45 assume 1 == ~t13_pc~0; 53777#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53778#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53840#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54452#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54453#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54392#L1427-3 assume !(1 == ~M_E~0); 53603#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53604#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54142#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53794#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53795#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52651#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52652#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54334#L1462-3 assume !(1 == ~T8_E~0); 54335#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54198#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54199#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52902#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52903#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 53044#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53217#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53218#L1502-3 assume !(1 == ~E_2~0); 54166#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54297#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53255#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52947#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52948#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52912#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52913#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54013#L1542-3 assume !(1 == ~E_10~0); 54151#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53780#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53781#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 53123#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53124#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52543#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53308#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53309#L1947 assume !(0 == start_simulation_~tmp~3#1); 53914#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54119#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53180#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54512#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 54436#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54266#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54025#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54026#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 53239#L1928-2 [2022-02-21 04:23:25,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:25,724 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2022-02-21 04:23:25,724 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:25,724 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347608400] [2022-02-21 04:23:25,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:25,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:25,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:25,742 INFO L290 TraceCheckUtils]: 0: Hoare triple {58599#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {58599#true} is VALID [2022-02-21 04:23:25,743 INFO L290 TraceCheckUtils]: 1: Hoare triple {58599#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {58601#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:25,743 INFO L290 TraceCheckUtils]: 2: Hoare triple {58601#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {58601#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:25,743 INFO L290 TraceCheckUtils]: 3: Hoare triple {58601#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {58601#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:25,744 INFO L290 TraceCheckUtils]: 4: Hoare triple {58601#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {58601#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:25,744 INFO L290 TraceCheckUtils]: 5: Hoare triple {58601#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {58601#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:25,744 INFO L290 TraceCheckUtils]: 6: Hoare triple {58601#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {58601#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:25,744 INFO L290 TraceCheckUtils]: 7: Hoare triple {58601#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {58601#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:25,745 INFO L290 TraceCheckUtils]: 8: Hoare triple {58601#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {58601#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:25,745 INFO L290 TraceCheckUtils]: 9: Hoare triple {58601#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {58601#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:25,745 INFO L290 TraceCheckUtils]: 10: Hoare triple {58601#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {58601#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:25,745 INFO L290 TraceCheckUtils]: 11: Hoare triple {58601#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {58600#false} is VALID [2022-02-21 04:23:25,745 INFO L290 TraceCheckUtils]: 12: Hoare triple {58600#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {58600#false} is VALID [2022-02-21 04:23:25,745 INFO L290 TraceCheckUtils]: 13: Hoare triple {58600#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {58600#false} is VALID [2022-02-21 04:23:25,746 INFO L290 TraceCheckUtils]: 14: Hoare triple {58600#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {58600#false} is VALID [2022-02-21 04:23:25,746 INFO L290 TraceCheckUtils]: 15: Hoare triple {58600#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {58600#false} is VALID [2022-02-21 04:23:25,746 INFO L290 TraceCheckUtils]: 16: Hoare triple {58600#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {58600#false} is VALID [2022-02-21 04:23:25,746 INFO L290 TraceCheckUtils]: 17: Hoare triple {58600#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {58600#false} is VALID [2022-02-21 04:23:25,746 INFO L290 TraceCheckUtils]: 18: Hoare triple {58600#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {58600#false} is VALID [2022-02-21 04:23:25,746 INFO L290 TraceCheckUtils]: 19: Hoare triple {58600#false} assume 0 == ~M_E~0;~M_E~0 := 1; {58600#false} is VALID [2022-02-21 04:23:25,746 INFO L290 TraceCheckUtils]: 20: Hoare triple {58600#false} assume !(0 == ~T1_E~0); {58600#false} is VALID [2022-02-21 04:23:25,746 INFO L290 TraceCheckUtils]: 21: Hoare triple {58600#false} assume !(0 == ~T2_E~0); {58600#false} is VALID [2022-02-21 04:23:25,746 INFO L290 TraceCheckUtils]: 22: Hoare triple {58600#false} assume !(0 == ~T3_E~0); {58600#false} is VALID [2022-02-21 04:23:25,746 INFO L290 TraceCheckUtils]: 23: Hoare triple {58600#false} assume !(0 == ~T4_E~0); {58600#false} is VALID [2022-02-21 04:23:25,747 INFO L290 TraceCheckUtils]: 24: Hoare triple {58600#false} assume !(0 == ~T5_E~0); {58600#false} is VALID [2022-02-21 04:23:25,747 INFO L290 TraceCheckUtils]: 25: Hoare triple {58600#false} assume !(0 == ~T6_E~0); {58600#false} is VALID [2022-02-21 04:23:25,747 INFO L290 TraceCheckUtils]: 26: Hoare triple {58600#false} assume !(0 == ~T7_E~0); {58600#false} is VALID [2022-02-21 04:23:25,747 INFO L290 TraceCheckUtils]: 27: Hoare triple {58600#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {58600#false} is VALID [2022-02-21 04:23:25,747 INFO L290 TraceCheckUtils]: 28: Hoare triple {58600#false} assume !(0 == ~T9_E~0); {58600#false} is VALID [2022-02-21 04:23:25,747 INFO L290 TraceCheckUtils]: 29: Hoare triple {58600#false} assume !(0 == ~T10_E~0); {58600#false} is VALID [2022-02-21 04:23:25,747 INFO L290 TraceCheckUtils]: 30: Hoare triple {58600#false} assume !(0 == ~T11_E~0); {58600#false} is VALID [2022-02-21 04:23:25,747 INFO L290 TraceCheckUtils]: 31: Hoare triple {58600#false} assume !(0 == ~T12_E~0); {58600#false} is VALID [2022-02-21 04:23:25,747 INFO L290 TraceCheckUtils]: 32: Hoare triple {58600#false} assume !(0 == ~T13_E~0); {58600#false} is VALID [2022-02-21 04:23:25,747 INFO L290 TraceCheckUtils]: 33: Hoare triple {58600#false} assume !(0 == ~E_M~0); {58600#false} is VALID [2022-02-21 04:23:25,748 INFO L290 TraceCheckUtils]: 34: Hoare triple {58600#false} assume !(0 == ~E_1~0); {58600#false} is VALID [2022-02-21 04:23:25,748 INFO L290 TraceCheckUtils]: 35: Hoare triple {58600#false} assume 0 == ~E_2~0;~E_2~0 := 1; {58600#false} is VALID [2022-02-21 04:23:25,748 INFO L290 TraceCheckUtils]: 36: Hoare triple {58600#false} assume !(0 == ~E_3~0); {58600#false} is VALID [2022-02-21 04:23:25,748 INFO L290 TraceCheckUtils]: 37: Hoare triple {58600#false} assume !(0 == ~E_4~0); {58600#false} is VALID [2022-02-21 04:23:25,748 INFO L290 TraceCheckUtils]: 38: Hoare triple {58600#false} assume !(0 == ~E_5~0); {58600#false} is VALID [2022-02-21 04:23:25,748 INFO L290 TraceCheckUtils]: 39: Hoare triple {58600#false} assume !(0 == ~E_6~0); {58600#false} is VALID [2022-02-21 04:23:25,748 INFO L290 TraceCheckUtils]: 40: Hoare triple {58600#false} assume !(0 == ~E_7~0); {58600#false} is VALID [2022-02-21 04:23:25,748 INFO L290 TraceCheckUtils]: 41: Hoare triple {58600#false} assume !(0 == ~E_8~0); {58600#false} is VALID [2022-02-21 04:23:25,748 INFO L290 TraceCheckUtils]: 42: Hoare triple {58600#false} assume !(0 == ~E_9~0); {58600#false} is VALID [2022-02-21 04:23:25,748 INFO L290 TraceCheckUtils]: 43: Hoare triple {58600#false} assume 0 == ~E_10~0;~E_10~0 := 1; {58600#false} is VALID [2022-02-21 04:23:25,749 INFO L290 TraceCheckUtils]: 44: Hoare triple {58600#false} assume !(0 == ~E_11~0); {58600#false} is VALID [2022-02-21 04:23:25,749 INFO L290 TraceCheckUtils]: 45: Hoare triple {58600#false} assume !(0 == ~E_12~0); {58600#false} is VALID [2022-02-21 04:23:25,749 INFO L290 TraceCheckUtils]: 46: Hoare triple {58600#false} assume !(0 == ~E_13~0); {58600#false} is VALID [2022-02-21 04:23:25,749 INFO L290 TraceCheckUtils]: 47: Hoare triple {58600#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {58600#false} is VALID [2022-02-21 04:23:25,749 INFO L290 TraceCheckUtils]: 48: Hoare triple {58600#false} assume !(1 == ~m_pc~0); {58600#false} is VALID [2022-02-21 04:23:25,749 INFO L290 TraceCheckUtils]: 49: Hoare triple {58600#false} is_master_triggered_~__retres1~0#1 := 0; {58600#false} is VALID [2022-02-21 04:23:25,749 INFO L290 TraceCheckUtils]: 50: Hoare triple {58600#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {58600#false} is VALID [2022-02-21 04:23:25,749 INFO L290 TraceCheckUtils]: 51: Hoare triple {58600#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {58600#false} is VALID [2022-02-21 04:23:25,749 INFO L290 TraceCheckUtils]: 52: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp~1#1); {58600#false} is VALID [2022-02-21 04:23:25,749 INFO L290 TraceCheckUtils]: 53: Hoare triple {58600#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 54: Hoare triple {58600#false} assume 1 == ~t1_pc~0; {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 55: Hoare triple {58600#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 56: Hoare triple {58600#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 57: Hoare triple {58600#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 58: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___0~0#1); {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 59: Hoare triple {58600#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 60: Hoare triple {58600#false} assume 1 == ~t2_pc~0; {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 61: Hoare triple {58600#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 62: Hoare triple {58600#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 63: Hoare triple {58600#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {58600#false} is VALID [2022-02-21 04:23:25,750 INFO L290 TraceCheckUtils]: 64: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___1~0#1); {58600#false} is VALID [2022-02-21 04:23:25,751 INFO L290 TraceCheckUtils]: 65: Hoare triple {58600#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {58600#false} is VALID [2022-02-21 04:23:25,751 INFO L290 TraceCheckUtils]: 66: Hoare triple {58600#false} assume !(1 == ~t3_pc~0); {58600#false} is VALID [2022-02-21 04:23:25,751 INFO L290 TraceCheckUtils]: 67: Hoare triple {58600#false} is_transmit3_triggered_~__retres1~3#1 := 0; {58600#false} is VALID [2022-02-21 04:23:25,751 INFO L290 TraceCheckUtils]: 68: Hoare triple {58600#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {58600#false} is VALID [2022-02-21 04:23:25,751 INFO L290 TraceCheckUtils]: 69: Hoare triple {58600#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {58600#false} is VALID [2022-02-21 04:23:25,751 INFO L290 TraceCheckUtils]: 70: Hoare triple {58600#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {58600#false} is VALID [2022-02-21 04:23:25,751 INFO L290 TraceCheckUtils]: 71: Hoare triple {58600#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {58600#false} is VALID [2022-02-21 04:23:25,751 INFO L290 TraceCheckUtils]: 72: Hoare triple {58600#false} assume 1 == ~t4_pc~0; {58600#false} is VALID [2022-02-21 04:23:25,751 INFO L290 TraceCheckUtils]: 73: Hoare triple {58600#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {58600#false} is VALID [2022-02-21 04:23:25,751 INFO L290 TraceCheckUtils]: 74: Hoare triple {58600#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {58600#false} is VALID [2022-02-21 04:23:25,752 INFO L290 TraceCheckUtils]: 75: Hoare triple {58600#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {58600#false} is VALID [2022-02-21 04:23:25,752 INFO L290 TraceCheckUtils]: 76: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___3~0#1); {58600#false} is VALID [2022-02-21 04:23:25,752 INFO L290 TraceCheckUtils]: 77: Hoare triple {58600#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {58600#false} is VALID [2022-02-21 04:23:25,752 INFO L290 TraceCheckUtils]: 78: Hoare triple {58600#false} assume !(1 == ~t5_pc~0); {58600#false} is VALID [2022-02-21 04:23:25,752 INFO L290 TraceCheckUtils]: 79: Hoare triple {58600#false} is_transmit5_triggered_~__retres1~5#1 := 0; {58600#false} is VALID [2022-02-21 04:23:25,752 INFO L290 TraceCheckUtils]: 80: Hoare triple {58600#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {58600#false} is VALID [2022-02-21 04:23:25,752 INFO L290 TraceCheckUtils]: 81: Hoare triple {58600#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {58600#false} is VALID [2022-02-21 04:23:25,752 INFO L290 TraceCheckUtils]: 82: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___4~0#1); {58600#false} is VALID [2022-02-21 04:23:25,752 INFO L290 TraceCheckUtils]: 83: Hoare triple {58600#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {58600#false} is VALID [2022-02-21 04:23:25,752 INFO L290 TraceCheckUtils]: 84: Hoare triple {58600#false} assume 1 == ~t6_pc~0; {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 85: Hoare triple {58600#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 86: Hoare triple {58600#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 87: Hoare triple {58600#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 88: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___5~0#1); {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 89: Hoare triple {58600#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 90: Hoare triple {58600#false} assume !(1 == ~t7_pc~0); {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 91: Hoare triple {58600#false} is_transmit7_triggered_~__retres1~7#1 := 0; {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 92: Hoare triple {58600#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 93: Hoare triple {58600#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 94: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___6~0#1); {58600#false} is VALID [2022-02-21 04:23:25,753 INFO L290 TraceCheckUtils]: 95: Hoare triple {58600#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {58600#false} is VALID [2022-02-21 04:23:25,754 INFO L290 TraceCheckUtils]: 96: Hoare triple {58600#false} assume 1 == ~t8_pc~0; {58600#false} is VALID [2022-02-21 04:23:25,754 INFO L290 TraceCheckUtils]: 97: Hoare triple {58600#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {58600#false} is VALID [2022-02-21 04:23:25,754 INFO L290 TraceCheckUtils]: 98: Hoare triple {58600#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {58600#false} is VALID [2022-02-21 04:23:25,754 INFO L290 TraceCheckUtils]: 99: Hoare triple {58600#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {58600#false} is VALID [2022-02-21 04:23:25,754 INFO L290 TraceCheckUtils]: 100: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___7~0#1); {58600#false} is VALID [2022-02-21 04:23:25,754 INFO L290 TraceCheckUtils]: 101: Hoare triple {58600#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {58600#false} is VALID [2022-02-21 04:23:25,754 INFO L290 TraceCheckUtils]: 102: Hoare triple {58600#false} assume 1 == ~t9_pc~0; {58600#false} is VALID [2022-02-21 04:23:25,754 INFO L290 TraceCheckUtils]: 103: Hoare triple {58600#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {58600#false} is VALID [2022-02-21 04:23:25,754 INFO L290 TraceCheckUtils]: 104: Hoare triple {58600#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {58600#false} is VALID [2022-02-21 04:23:25,754 INFO L290 TraceCheckUtils]: 105: Hoare triple {58600#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {58600#false} is VALID [2022-02-21 04:23:25,755 INFO L290 TraceCheckUtils]: 106: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___8~0#1); {58600#false} is VALID [2022-02-21 04:23:25,755 INFO L290 TraceCheckUtils]: 107: Hoare triple {58600#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {58600#false} is VALID [2022-02-21 04:23:25,755 INFO L290 TraceCheckUtils]: 108: Hoare triple {58600#false} assume !(1 == ~t10_pc~0); {58600#false} is VALID [2022-02-21 04:23:25,755 INFO L290 TraceCheckUtils]: 109: Hoare triple {58600#false} is_transmit10_triggered_~__retres1~10#1 := 0; {58600#false} is VALID [2022-02-21 04:23:25,755 INFO L290 TraceCheckUtils]: 110: Hoare triple {58600#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {58600#false} is VALID [2022-02-21 04:23:25,755 INFO L290 TraceCheckUtils]: 111: Hoare triple {58600#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {58600#false} is VALID [2022-02-21 04:23:25,755 INFO L290 TraceCheckUtils]: 112: Hoare triple {58600#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {58600#false} is VALID [2022-02-21 04:23:25,755 INFO L290 TraceCheckUtils]: 113: Hoare triple {58600#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {58600#false} is VALID [2022-02-21 04:23:25,755 INFO L290 TraceCheckUtils]: 114: Hoare triple {58600#false} assume 1 == ~t11_pc~0; {58600#false} is VALID [2022-02-21 04:23:25,755 INFO L290 TraceCheckUtils]: 115: Hoare triple {58600#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {58600#false} is VALID [2022-02-21 04:23:25,756 INFO L290 TraceCheckUtils]: 116: Hoare triple {58600#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {58600#false} is VALID [2022-02-21 04:23:25,756 INFO L290 TraceCheckUtils]: 117: Hoare triple {58600#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {58600#false} is VALID [2022-02-21 04:23:25,756 INFO L290 TraceCheckUtils]: 118: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___10~0#1); {58600#false} is VALID [2022-02-21 04:23:25,756 INFO L290 TraceCheckUtils]: 119: Hoare triple {58600#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {58600#false} is VALID [2022-02-21 04:23:25,756 INFO L290 TraceCheckUtils]: 120: Hoare triple {58600#false} assume !(1 == ~t12_pc~0); {58600#false} is VALID [2022-02-21 04:23:25,756 INFO L290 TraceCheckUtils]: 121: Hoare triple {58600#false} is_transmit12_triggered_~__retres1~12#1 := 0; {58600#false} is VALID [2022-02-21 04:23:25,756 INFO L290 TraceCheckUtils]: 122: Hoare triple {58600#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {58600#false} is VALID [2022-02-21 04:23:25,756 INFO L290 TraceCheckUtils]: 123: Hoare triple {58600#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {58600#false} is VALID [2022-02-21 04:23:25,756 INFO L290 TraceCheckUtils]: 124: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___11~0#1); {58600#false} is VALID [2022-02-21 04:23:25,756 INFO L290 TraceCheckUtils]: 125: Hoare triple {58600#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 126: Hoare triple {58600#false} assume 1 == ~t13_pc~0; {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 127: Hoare triple {58600#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 128: Hoare triple {58600#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 129: Hoare triple {58600#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 130: Hoare triple {58600#false} assume !(0 != activate_threads_~tmp___12~0#1); {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 131: Hoare triple {58600#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 132: Hoare triple {58600#false} assume !(1 == ~M_E~0); {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 133: Hoare triple {58600#false} assume !(1 == ~T1_E~0); {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 134: Hoare triple {58600#false} assume !(1 == ~T2_E~0); {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 135: Hoare triple {58600#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {58600#false} is VALID [2022-02-21 04:23:25,757 INFO L290 TraceCheckUtils]: 136: Hoare triple {58600#false} assume !(1 == ~T4_E~0); {58600#false} is VALID [2022-02-21 04:23:25,758 INFO L290 TraceCheckUtils]: 137: Hoare triple {58600#false} assume !(1 == ~T5_E~0); {58600#false} is VALID [2022-02-21 04:23:25,758 INFO L290 TraceCheckUtils]: 138: Hoare triple {58600#false} assume !(1 == ~T6_E~0); {58600#false} is VALID [2022-02-21 04:23:25,758 INFO L290 TraceCheckUtils]: 139: Hoare triple {58600#false} assume !(1 == ~T7_E~0); {58600#false} is VALID [2022-02-21 04:23:25,758 INFO L290 TraceCheckUtils]: 140: Hoare triple {58600#false} assume !(1 == ~T8_E~0); {58600#false} is VALID [2022-02-21 04:23:25,758 INFO L290 TraceCheckUtils]: 141: Hoare triple {58600#false} assume !(1 == ~T9_E~0); {58600#false} is VALID [2022-02-21 04:23:25,758 INFO L290 TraceCheckUtils]: 142: Hoare triple {58600#false} assume !(1 == ~T10_E~0); {58600#false} is VALID [2022-02-21 04:23:25,758 INFO L290 TraceCheckUtils]: 143: Hoare triple {58600#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {58600#false} is VALID [2022-02-21 04:23:25,758 INFO L290 TraceCheckUtils]: 144: Hoare triple {58600#false} assume !(1 == ~T12_E~0); {58600#false} is VALID [2022-02-21 04:23:25,758 INFO L290 TraceCheckUtils]: 145: Hoare triple {58600#false} assume !(1 == ~T13_E~0); {58600#false} is VALID [2022-02-21 04:23:25,758 INFO L290 TraceCheckUtils]: 146: Hoare triple {58600#false} assume !(1 == ~E_M~0); {58600#false} is VALID [2022-02-21 04:23:25,759 INFO L290 TraceCheckUtils]: 147: Hoare triple {58600#false} assume !(1 == ~E_1~0); {58600#false} is VALID [2022-02-21 04:23:25,759 INFO L290 TraceCheckUtils]: 148: Hoare triple {58600#false} assume !(1 == ~E_2~0); {58600#false} is VALID [2022-02-21 04:23:25,759 INFO L290 TraceCheckUtils]: 149: Hoare triple {58600#false} assume !(1 == ~E_3~0); {58600#false} is VALID [2022-02-21 04:23:25,759 INFO L290 TraceCheckUtils]: 150: Hoare triple {58600#false} assume !(1 == ~E_4~0); {58600#false} is VALID [2022-02-21 04:23:25,759 INFO L290 TraceCheckUtils]: 151: Hoare triple {58600#false} assume 1 == ~E_5~0;~E_5~0 := 2; {58600#false} is VALID [2022-02-21 04:23:25,759 INFO L290 TraceCheckUtils]: 152: Hoare triple {58600#false} assume !(1 == ~E_6~0); {58600#false} is VALID [2022-02-21 04:23:25,759 INFO L290 TraceCheckUtils]: 153: Hoare triple {58600#false} assume !(1 == ~E_7~0); {58600#false} is VALID [2022-02-21 04:23:25,759 INFO L290 TraceCheckUtils]: 154: Hoare triple {58600#false} assume !(1 == ~E_8~0); {58600#false} is VALID [2022-02-21 04:23:25,759 INFO L290 TraceCheckUtils]: 155: Hoare triple {58600#false} assume !(1 == ~E_9~0); {58600#false} is VALID [2022-02-21 04:23:25,759 INFO L290 TraceCheckUtils]: 156: Hoare triple {58600#false} assume !(1 == ~E_10~0); {58600#false} is VALID [2022-02-21 04:23:25,760 INFO L290 TraceCheckUtils]: 157: Hoare triple {58600#false} assume !(1 == ~E_11~0); {58600#false} is VALID [2022-02-21 04:23:25,760 INFO L290 TraceCheckUtils]: 158: Hoare triple {58600#false} assume !(1 == ~E_12~0); {58600#false} is VALID [2022-02-21 04:23:25,760 INFO L290 TraceCheckUtils]: 159: Hoare triple {58600#false} assume 1 == ~E_13~0;~E_13~0 := 2; {58600#false} is VALID [2022-02-21 04:23:25,760 INFO L290 TraceCheckUtils]: 160: Hoare triple {58600#false} assume { :end_inline_reset_delta_events } true; {58600#false} is VALID [2022-02-21 04:23:25,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:25,760 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:25,760 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347608400] [2022-02-21 04:23:25,760 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1347608400] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:25,761 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:25,761 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:25,761 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134018645] [2022-02-21 04:23:25,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:25,761 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:25,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:25,761 INFO L85 PathProgramCache]: Analyzing trace with hash 975518447, now seen corresponding path program 2 times [2022-02-21 04:23:25,762 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:25,762 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855025070] [2022-02-21 04:23:25,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:25,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:25,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:25,785 INFO L290 TraceCheckUtils]: 0: Hoare triple {58602#true} assume !false; {58602#true} is VALID [2022-02-21 04:23:25,785 INFO L290 TraceCheckUtils]: 1: Hoare triple {58602#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {58602#true} is VALID [2022-02-21 04:23:25,785 INFO L290 TraceCheckUtils]: 2: Hoare triple {58602#true} assume !false; {58602#true} is VALID [2022-02-21 04:23:25,785 INFO L290 TraceCheckUtils]: 3: Hoare triple {58602#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {58602#true} is VALID [2022-02-21 04:23:25,786 INFO L290 TraceCheckUtils]: 4: Hoare triple {58602#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {58602#true} is VALID [2022-02-21 04:23:25,786 INFO L290 TraceCheckUtils]: 5: Hoare triple {58602#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {58602#true} is VALID [2022-02-21 04:23:25,786 INFO L290 TraceCheckUtils]: 6: Hoare triple {58602#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {58602#true} is VALID [2022-02-21 04:23:25,786 INFO L290 TraceCheckUtils]: 7: Hoare triple {58602#true} assume !(0 != eval_~tmp~0#1); {58602#true} is VALID [2022-02-21 04:23:25,786 INFO L290 TraceCheckUtils]: 8: Hoare triple {58602#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {58602#true} is VALID [2022-02-21 04:23:25,786 INFO L290 TraceCheckUtils]: 9: Hoare triple {58602#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {58602#true} is VALID [2022-02-21 04:23:25,786 INFO L290 TraceCheckUtils]: 10: Hoare triple {58602#true} assume 0 == ~M_E~0;~M_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,787 INFO L290 TraceCheckUtils]: 11: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,787 INFO L290 TraceCheckUtils]: 12: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,787 INFO L290 TraceCheckUtils]: 13: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,787 INFO L290 TraceCheckUtils]: 14: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,788 INFO L290 TraceCheckUtils]: 15: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,788 INFO L290 TraceCheckUtils]: 16: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,788 INFO L290 TraceCheckUtils]: 17: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,788 INFO L290 TraceCheckUtils]: 18: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,789 INFO L290 TraceCheckUtils]: 19: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,789 INFO L290 TraceCheckUtils]: 20: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,789 INFO L290 TraceCheckUtils]: 21: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,789 INFO L290 TraceCheckUtils]: 22: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,790 INFO L290 TraceCheckUtils]: 23: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,790 INFO L290 TraceCheckUtils]: 24: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,790 INFO L290 TraceCheckUtils]: 25: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,790 INFO L290 TraceCheckUtils]: 26: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,791 INFO L290 TraceCheckUtils]: 27: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,791 INFO L290 TraceCheckUtils]: 28: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,791 INFO L290 TraceCheckUtils]: 29: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,792 INFO L290 TraceCheckUtils]: 30: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,792 INFO L290 TraceCheckUtils]: 31: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,792 INFO L290 TraceCheckUtils]: 32: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,792 INFO L290 TraceCheckUtils]: 33: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,793 INFO L290 TraceCheckUtils]: 34: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,793 INFO L290 TraceCheckUtils]: 35: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,793 INFO L290 TraceCheckUtils]: 36: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,793 INFO L290 TraceCheckUtils]: 37: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,794 INFO L290 TraceCheckUtils]: 38: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,794 INFO L290 TraceCheckUtils]: 39: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,794 INFO L290 TraceCheckUtils]: 40: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,794 INFO L290 TraceCheckUtils]: 41: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,795 INFO L290 TraceCheckUtils]: 42: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,795 INFO L290 TraceCheckUtils]: 43: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,795 INFO L290 TraceCheckUtils]: 44: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,796 INFO L290 TraceCheckUtils]: 45: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,796 INFO L290 TraceCheckUtils]: 46: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,796 INFO L290 TraceCheckUtils]: 47: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,796 INFO L290 TraceCheckUtils]: 48: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,797 INFO L290 TraceCheckUtils]: 49: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,797 INFO L290 TraceCheckUtils]: 50: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,797 INFO L290 TraceCheckUtils]: 51: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,797 INFO L290 TraceCheckUtils]: 52: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,798 INFO L290 TraceCheckUtils]: 53: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,798 INFO L290 TraceCheckUtils]: 54: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,798 INFO L290 TraceCheckUtils]: 55: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,798 INFO L290 TraceCheckUtils]: 56: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,799 INFO L290 TraceCheckUtils]: 57: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,799 INFO L290 TraceCheckUtils]: 58: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,799 INFO L290 TraceCheckUtils]: 59: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,800 INFO L290 TraceCheckUtils]: 60: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,800 INFO L290 TraceCheckUtils]: 61: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,800 INFO L290 TraceCheckUtils]: 62: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,800 INFO L290 TraceCheckUtils]: 63: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,801 INFO L290 TraceCheckUtils]: 64: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,801 INFO L290 TraceCheckUtils]: 65: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,801 INFO L290 TraceCheckUtils]: 66: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,801 INFO L290 TraceCheckUtils]: 67: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,802 INFO L290 TraceCheckUtils]: 68: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,802 INFO L290 TraceCheckUtils]: 69: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,802 INFO L290 TraceCheckUtils]: 70: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,802 INFO L290 TraceCheckUtils]: 71: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,803 INFO L290 TraceCheckUtils]: 72: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,803 INFO L290 TraceCheckUtils]: 73: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,803 INFO L290 TraceCheckUtils]: 74: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,804 INFO L290 TraceCheckUtils]: 75: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,804 INFO L290 TraceCheckUtils]: 76: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,804 INFO L290 TraceCheckUtils]: 77: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,804 INFO L290 TraceCheckUtils]: 78: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,805 INFO L290 TraceCheckUtils]: 79: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,805 INFO L290 TraceCheckUtils]: 80: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,805 INFO L290 TraceCheckUtils]: 81: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,805 INFO L290 TraceCheckUtils]: 82: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,806 INFO L290 TraceCheckUtils]: 83: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,806 INFO L290 TraceCheckUtils]: 84: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,806 INFO L290 TraceCheckUtils]: 85: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,806 INFO L290 TraceCheckUtils]: 86: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,807 INFO L290 TraceCheckUtils]: 87: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,807 INFO L290 TraceCheckUtils]: 88: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,807 INFO L290 TraceCheckUtils]: 89: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,808 INFO L290 TraceCheckUtils]: 90: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,808 INFO L290 TraceCheckUtils]: 91: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,808 INFO L290 TraceCheckUtils]: 92: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,808 INFO L290 TraceCheckUtils]: 93: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,809 INFO L290 TraceCheckUtils]: 94: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,809 INFO L290 TraceCheckUtils]: 95: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,809 INFO L290 TraceCheckUtils]: 96: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,809 INFO L290 TraceCheckUtils]: 97: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,810 INFO L290 TraceCheckUtils]: 98: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,810 INFO L290 TraceCheckUtils]: 99: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,810 INFO L290 TraceCheckUtils]: 100: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,810 INFO L290 TraceCheckUtils]: 101: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,811 INFO L290 TraceCheckUtils]: 102: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,811 INFO L290 TraceCheckUtils]: 103: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,811 INFO L290 TraceCheckUtils]: 104: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,812 INFO L290 TraceCheckUtils]: 105: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,812 INFO L290 TraceCheckUtils]: 106: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,812 INFO L290 TraceCheckUtils]: 107: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,812 INFO L290 TraceCheckUtils]: 108: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,813 INFO L290 TraceCheckUtils]: 109: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,813 INFO L290 TraceCheckUtils]: 110: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,813 INFO L290 TraceCheckUtils]: 111: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,813 INFO L290 TraceCheckUtils]: 112: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,814 INFO L290 TraceCheckUtils]: 113: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,814 INFO L290 TraceCheckUtils]: 114: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,814 INFO L290 TraceCheckUtils]: 115: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,814 INFO L290 TraceCheckUtils]: 116: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,815 INFO L290 TraceCheckUtils]: 117: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,815 INFO L290 TraceCheckUtils]: 118: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,815 INFO L290 TraceCheckUtils]: 119: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,816 INFO L290 TraceCheckUtils]: 120: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,816 INFO L290 TraceCheckUtils]: 121: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,816 INFO L290 TraceCheckUtils]: 122: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {58604#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:25,816 INFO L290 TraceCheckUtils]: 123: Hoare triple {58604#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {58603#false} is VALID [2022-02-21 04:23:25,816 INFO L290 TraceCheckUtils]: 124: Hoare triple {58603#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,817 INFO L290 TraceCheckUtils]: 125: Hoare triple {58603#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,817 INFO L290 TraceCheckUtils]: 126: Hoare triple {58603#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,817 INFO L290 TraceCheckUtils]: 127: Hoare triple {58603#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,817 INFO L290 TraceCheckUtils]: 128: Hoare triple {58603#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,817 INFO L290 TraceCheckUtils]: 129: Hoare triple {58603#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,817 INFO L290 TraceCheckUtils]: 130: Hoare triple {58603#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,817 INFO L290 TraceCheckUtils]: 131: Hoare triple {58603#false} assume !(1 == ~T8_E~0); {58603#false} is VALID [2022-02-21 04:23:25,817 INFO L290 TraceCheckUtils]: 132: Hoare triple {58603#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,817 INFO L290 TraceCheckUtils]: 133: Hoare triple {58603#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,817 INFO L290 TraceCheckUtils]: 134: Hoare triple {58603#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,818 INFO L290 TraceCheckUtils]: 135: Hoare triple {58603#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,818 INFO L290 TraceCheckUtils]: 136: Hoare triple {58603#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,818 INFO L290 TraceCheckUtils]: 137: Hoare triple {58603#false} assume 1 == ~E_M~0;~E_M~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,818 INFO L290 TraceCheckUtils]: 138: Hoare triple {58603#false} assume 1 == ~E_1~0;~E_1~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,818 INFO L290 TraceCheckUtils]: 139: Hoare triple {58603#false} assume !(1 == ~E_2~0); {58603#false} is VALID [2022-02-21 04:23:25,818 INFO L290 TraceCheckUtils]: 140: Hoare triple {58603#false} assume 1 == ~E_3~0;~E_3~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,818 INFO L290 TraceCheckUtils]: 141: Hoare triple {58603#false} assume 1 == ~E_4~0;~E_4~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,818 INFO L290 TraceCheckUtils]: 142: Hoare triple {58603#false} assume 1 == ~E_5~0;~E_5~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,818 INFO L290 TraceCheckUtils]: 143: Hoare triple {58603#false} assume 1 == ~E_6~0;~E_6~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,818 INFO L290 TraceCheckUtils]: 144: Hoare triple {58603#false} assume 1 == ~E_7~0;~E_7~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 145: Hoare triple {58603#false} assume 1 == ~E_8~0;~E_8~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 146: Hoare triple {58603#false} assume 1 == ~E_9~0;~E_9~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 147: Hoare triple {58603#false} assume !(1 == ~E_10~0); {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 148: Hoare triple {58603#false} assume 1 == ~E_11~0;~E_11~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 149: Hoare triple {58603#false} assume 1 == ~E_12~0;~E_12~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 150: Hoare triple {58603#false} assume 1 == ~E_13~0;~E_13~0 := 2; {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 151: Hoare triple {58603#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 152: Hoare triple {58603#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 153: Hoare triple {58603#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 154: Hoare triple {58603#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {58603#false} is VALID [2022-02-21 04:23:25,819 INFO L290 TraceCheckUtils]: 155: Hoare triple {58603#false} assume !(0 == start_simulation_~tmp~3#1); {58603#false} is VALID [2022-02-21 04:23:25,820 INFO L290 TraceCheckUtils]: 156: Hoare triple {58603#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {58603#false} is VALID [2022-02-21 04:23:25,820 INFO L290 TraceCheckUtils]: 157: Hoare triple {58603#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {58603#false} is VALID [2022-02-21 04:23:25,820 INFO L290 TraceCheckUtils]: 158: Hoare triple {58603#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {58603#false} is VALID [2022-02-21 04:23:25,820 INFO L290 TraceCheckUtils]: 159: Hoare triple {58603#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {58603#false} is VALID [2022-02-21 04:23:25,820 INFO L290 TraceCheckUtils]: 160: Hoare triple {58603#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {58603#false} is VALID [2022-02-21 04:23:25,820 INFO L290 TraceCheckUtils]: 161: Hoare triple {58603#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {58603#false} is VALID [2022-02-21 04:23:25,820 INFO L290 TraceCheckUtils]: 162: Hoare triple {58603#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {58603#false} is VALID [2022-02-21 04:23:25,820 INFO L290 TraceCheckUtils]: 163: Hoare triple {58603#false} assume !(0 != start_simulation_~tmp___0~1#1); {58603#false} is VALID [2022-02-21 04:23:25,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:25,821 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:25,821 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855025070] [2022-02-21 04:23:25,821 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855025070] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:25,821 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:25,821 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:25,821 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535489751] [2022-02-21 04:23:25,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:25,822 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:25,822 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:25,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:25,822 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:25,823 INFO L87 Difference]: Start difference. First operand 2018 states and 2981 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:27,312 INFO L93 Difference]: Finished difference Result 2018 states and 2980 transitions. [2022-02-21 04:23:27,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:27,312 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,412 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:27,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2980 transitions. [2022-02-21 04:23:27,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:27,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2980 transitions. [2022-02-21 04:23:27,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:27,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:27,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2980 transitions. [2022-02-21 04:23:27,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:27,622 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2022-02-21 04:23:27,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2980 transitions. [2022-02-21 04:23:27,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:27,638 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:27,639 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2980 transitions. Second operand has 2018 states, 2018 states have (on average 1.4767096134786917) internal successors, (2980), 2017 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,640 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2980 transitions. Second operand has 2018 states, 2018 states have (on average 1.4767096134786917) internal successors, (2980), 2017 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,641 INFO L87 Difference]: Start difference. First operand 2018 states and 2980 transitions. Second operand has 2018 states, 2018 states have (on average 1.4767096134786917) internal successors, (2980), 2017 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:27,726 INFO L93 Difference]: Finished difference Result 2018 states and 2980 transitions. [2022-02-21 04:23:27,726 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2980 transitions. [2022-02-21 04:23:27,727 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:27,728 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:27,730 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.4767096134786917) internal successors, (2980), 2017 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2980 transitions. [2022-02-21 04:23:27,731 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.4767096134786917) internal successors, (2980), 2017 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2980 transitions. [2022-02-21 04:23:27,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:27,812 INFO L93 Difference]: Finished difference Result 2018 states and 2980 transitions. [2022-02-21 04:23:27,812 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2980 transitions. [2022-02-21 04:23:27,814 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:27,814 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:27,814 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:27,814 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:27,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4767096134786917) internal successors, (2980), 2017 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2980 transitions. [2022-02-21 04:23:27,899 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2022-02-21 04:23:27,899 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2022-02-21 04:23:27,899 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:23:27,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2980 transitions. [2022-02-21 04:23:27,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:27,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:27,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:27,903 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:27,903 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:27,904 INFO L791 eck$LassoCheckResult]: Stem: 61538#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 61539#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 62575#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62030#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62031#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 61520#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61521#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61587#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61588#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62026#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62027#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 61553#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61372#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 61373#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 61817#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 61818#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 61693#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 61694#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 61343#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61344#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 62567#L1279-2 assume !(0 == ~T1_E~0); 60966#L1284-1 assume !(0 == ~T2_E~0); 60967#L1289-1 assume !(0 == ~T3_E~0); 61690#L1294-1 assume !(0 == ~T4_E~0); 61691#L1299-1 assume !(0 == ~T5_E~0); 61702#L1304-1 assume !(0 == ~T6_E~0); 62633#L1309-1 assume !(0 == ~T7_E~0); 62634#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60896#L1319-1 assume !(0 == ~T9_E~0); 60897#L1324-1 assume !(0 == ~T10_E~0); 61069#L1329-1 assume !(0 == ~T11_E~0); 61070#L1334-1 assume !(0 == ~T12_E~0); 62474#L1339-1 assume !(0 == ~T13_E~0); 62555#L1344-1 assume !(0 == ~E_M~0); 62556#L1349-1 assume !(0 == ~E_1~0); 61877#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 61878#L1359-1 assume !(0 == ~E_3~0); 62307#L1364-1 assume !(0 == ~E_4~0); 61198#L1369-1 assume !(0 == ~E_5~0); 61199#L1374-1 assume !(0 == ~E_6~0); 61882#L1379-1 assume !(0 == ~E_7~0); 61883#L1384-1 assume !(0 == ~E_8~0); 61960#L1389-1 assume !(0 == ~E_9~0); 62493#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 62494#L1399-1 assume !(0 == ~E_11~0); 62597#L1404-1 assume !(0 == ~E_12~0); 61291#L1409-1 assume !(0 == ~E_13~0); 61292#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62589#L628 assume !(1 == ~m_pc~0); 61195#L628-2 is_master_triggered_~__retres1~0#1 := 0; 61194#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61958#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61959#L1591 assume !(0 != activate_threads_~tmp~1#1); 62602#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61746#L647 assume 1 == ~t1_pc~0; 61115#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 61116#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61387#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61388#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 62542#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62543#L666 assume 1 == ~t2_pc~0; 60963#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60964#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61130#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62559#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 62078#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62079#L685 assume !(1 == ~t3_pc~0); 62184#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62183#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61806#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61807#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61928#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61414#L704 assume 1 == ~t4_pc~0; 61415#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61939#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61940#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62580#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 61799#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61800#L723 assume !(1 == ~t5_pc~0); 61922#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62158#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62302#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62057#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 62058#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61180#L742 assume 1 == ~t6_pc~0; 61181#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61329#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61330#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60865#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 60866#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61257#L761 assume !(1 == ~t7_pc~0); 61258#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 61126#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61127#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61929#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 61930#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60890#L780 assume 1 == ~t8_pc~0; 60891#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61166#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61167#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61890#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 61891#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62010#L799 assume 1 == ~t9_pc~0; 62122#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60893#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60894#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62022#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 62229#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62040#L818 assume !(1 == ~t10_pc~0); 60674#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 60675#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62115#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62044#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 62045#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62085#L837 assume 1 == ~t11_pc~0; 62086#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61920#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62323#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62003#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 62004#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61755#L856 assume !(1 == ~t12_pc~0); 61756#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62409#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62410#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 62390#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 62391#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 62570#L875 assume 1 == ~t13_pc~0; 61700#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 61332#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 61333#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 61272#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 61273#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62112#L1427 assume !(1 == ~M_E~0); 62096#L1427-2 assume !(1 == ~T1_E~0); 61244#L1432-1 assume !(1 == ~T2_E~0); 61245#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62313#L1442-1 assume !(1 == ~T4_E~0); 62314#L1447-1 assume !(1 == ~T5_E~0); 62169#L1452-1 assume !(1 == ~T6_E~0); 60809#L1457-1 assume !(1 == ~T7_E~0); 60810#L1462-1 assume !(1 == ~T8_E~0); 62340#L1467-1 assume !(1 == ~T9_E~0); 62358#L1472-1 assume !(1 == ~T10_E~0); 62359#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 62110#L1482-1 assume !(1 == ~T12_E~0); 62111#L1487-1 assume !(1 == ~T13_E~0); 61140#L1492-1 assume !(1 == ~E_M~0); 61141#L1497-1 assume !(1 == ~E_1~0); 61502#L1502-1 assume !(1 == ~E_2~0); 61503#L1507-1 assume !(1 == ~E_3~0); 61018#L1512-1 assume !(1 == ~E_4~0); 61019#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 62429#L1522-1 assume !(1 == ~E_6~0); 61743#L1527-1 assume !(1 == ~E_7~0); 61744#L1532-1 assume !(1 == ~E_8~0); 62617#L1537-1 assume !(1 == ~E_9~0); 61946#L1542-1 assume !(1 == ~E_10~0); 61777#L1547-1 assume !(1 == ~E_11~0); 61778#L1552-1 assume !(1 == ~E_12~0); 60713#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 60714#L1562-1 assume { :end_inline_reset_delta_events } true; 61320#L1928-2 [2022-02-21 04:23:27,904 INFO L793 eck$LassoCheckResult]: Loop: 61320#L1928-2 assume !false; 61811#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60974#L1254 assume !false; 61561#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61048#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61049#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61246#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 62417#L1067 assume !(0 != eval_~tmp~0#1); 61487#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61064#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61065#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 61524#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 61506#L1284-3 assume !(0 == ~T2_E~0); 61507#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61485#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61486#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61873#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61874#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61383#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 61384#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62380#L1324-3 assume !(0 == ~T10_E~0); 61015#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 61016#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 61783#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 61784#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62082#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61364#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61365#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62093#L1364-3 assume !(0 == ~E_4~0); 62615#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62511#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61144#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 61145#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61362#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 61363#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 61653#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62521#L1404-3 assume !(0 == ~E_12~0); 62485#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 62486#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61972#L628-45 assume 1 == ~m_pc~0; 61650#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61652#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61009#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61010#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61398#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62121#L647-45 assume 1 == ~t1_pc~0; 60960#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 60961#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61889#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61074#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61075#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61286#L666-45 assume !(1 == ~t2_pc~0); 61287#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 61768#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62330#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62245#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62239#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60824#L685-45 assume 1 == ~t3_pc~0; 60825#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 61884#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62558#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62427#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62428#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62568#L704-45 assume !(1 == ~t4_pc~0); 60690#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 60691#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61550#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61893#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62640#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62005#L723-45 assume !(1 == ~t5_pc~0); 62006#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 62495#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61597#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61374#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 61375#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62399#L742-45 assume 1 == ~t6_pc~0; 62400#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61622#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62091#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62127#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62128#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62216#L761-45 assume !(1 == ~t7_pc~0); 62217#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 61615#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61616#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61022#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 61023#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62489#L780-45 assume 1 == ~t8_pc~0; 61400#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61034#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61035#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62616#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61004#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61005#L799-45 assume 1 == ~t9_pc~0; 61781#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61226#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62541#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62170#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 62171#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60942#L818-45 assume !(1 == ~t10_pc~0); 60944#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 61061#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62144#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61548#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61549#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62264#L837-45 assume !(1 == ~t11_pc~0); 61479#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 61480#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61617#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62282#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 61080#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61081#L856-45 assume 1 == ~t12_pc~0; 62566#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61083#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61024#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61025#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61887#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61888#L875-45 assume 1 == ~t13_pc~0; 61858#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 61859#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 61921#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 62533#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 62534#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62473#L1427-3 assume !(1 == ~M_E~0); 61684#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61685#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62223#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61875#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61876#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 60732#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60733#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62415#L1462-3 assume !(1 == ~T8_E~0); 62416#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62279#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62280#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 60983#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 60984#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 61125#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 61298#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 61299#L1502-3 assume !(1 == ~E_2~0); 62247#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62378#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61336#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61028#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61029#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60993#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60994#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 62094#L1542-3 assume !(1 == ~E_10~0); 62232#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 61861#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 61862#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 61204#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61205#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60624#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61389#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 61390#L1947 assume !(0 == start_simulation_~tmp~3#1); 61995#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 62200#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61261#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 62593#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 62517#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 62347#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 62106#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 62107#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 61320#L1928-2 [2022-02-21 04:23:27,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:27,905 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2022-02-21 04:23:27,905 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:27,905 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079571359] [2022-02-21 04:23:27,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:27,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:27,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:27,924 INFO L290 TraceCheckUtils]: 0: Hoare triple {66680#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {66680#true} is VALID [2022-02-21 04:23:27,924 INFO L290 TraceCheckUtils]: 1: Hoare triple {66680#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,925 INFO L290 TraceCheckUtils]: 2: Hoare triple {66682#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,925 INFO L290 TraceCheckUtils]: 3: Hoare triple {66682#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,925 INFO L290 TraceCheckUtils]: 4: Hoare triple {66682#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,925 INFO L290 TraceCheckUtils]: 5: Hoare triple {66682#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,926 INFO L290 TraceCheckUtils]: 6: Hoare triple {66682#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,926 INFO L290 TraceCheckUtils]: 7: Hoare triple {66682#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,926 INFO L290 TraceCheckUtils]: 8: Hoare triple {66682#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,926 INFO L290 TraceCheckUtils]: 9: Hoare triple {66682#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,927 INFO L290 TraceCheckUtils]: 10: Hoare triple {66682#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,927 INFO L290 TraceCheckUtils]: 11: Hoare triple {66682#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {66682#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:27,927 INFO L290 TraceCheckUtils]: 12: Hoare triple {66682#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {66681#false} is VALID [2022-02-21 04:23:27,927 INFO L290 TraceCheckUtils]: 13: Hoare triple {66681#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {66681#false} is VALID [2022-02-21 04:23:27,927 INFO L290 TraceCheckUtils]: 14: Hoare triple {66681#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {66681#false} is VALID [2022-02-21 04:23:27,927 INFO L290 TraceCheckUtils]: 15: Hoare triple {66681#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {66681#false} is VALID [2022-02-21 04:23:27,928 INFO L290 TraceCheckUtils]: 16: Hoare triple {66681#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {66681#false} is VALID [2022-02-21 04:23:27,928 INFO L290 TraceCheckUtils]: 17: Hoare triple {66681#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {66681#false} is VALID [2022-02-21 04:23:27,928 INFO L290 TraceCheckUtils]: 18: Hoare triple {66681#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {66681#false} is VALID [2022-02-21 04:23:27,928 INFO L290 TraceCheckUtils]: 19: Hoare triple {66681#false} assume 0 == ~M_E~0;~M_E~0 := 1; {66681#false} is VALID [2022-02-21 04:23:27,928 INFO L290 TraceCheckUtils]: 20: Hoare triple {66681#false} assume !(0 == ~T1_E~0); {66681#false} is VALID [2022-02-21 04:23:27,928 INFO L290 TraceCheckUtils]: 21: Hoare triple {66681#false} assume !(0 == ~T2_E~0); {66681#false} is VALID [2022-02-21 04:23:27,928 INFO L290 TraceCheckUtils]: 22: Hoare triple {66681#false} assume !(0 == ~T3_E~0); {66681#false} is VALID [2022-02-21 04:23:27,928 INFO L290 TraceCheckUtils]: 23: Hoare triple {66681#false} assume !(0 == ~T4_E~0); {66681#false} is VALID [2022-02-21 04:23:27,928 INFO L290 TraceCheckUtils]: 24: Hoare triple {66681#false} assume !(0 == ~T5_E~0); {66681#false} is VALID [2022-02-21 04:23:27,928 INFO L290 TraceCheckUtils]: 25: Hoare triple {66681#false} assume !(0 == ~T6_E~0); {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 26: Hoare triple {66681#false} assume !(0 == ~T7_E~0); {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 27: Hoare triple {66681#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 28: Hoare triple {66681#false} assume !(0 == ~T9_E~0); {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 29: Hoare triple {66681#false} assume !(0 == ~T10_E~0); {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 30: Hoare triple {66681#false} assume !(0 == ~T11_E~0); {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 31: Hoare triple {66681#false} assume !(0 == ~T12_E~0); {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 32: Hoare triple {66681#false} assume !(0 == ~T13_E~0); {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 33: Hoare triple {66681#false} assume !(0 == ~E_M~0); {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 34: Hoare triple {66681#false} assume !(0 == ~E_1~0); {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 35: Hoare triple {66681#false} assume 0 == ~E_2~0;~E_2~0 := 1; {66681#false} is VALID [2022-02-21 04:23:27,929 INFO L290 TraceCheckUtils]: 36: Hoare triple {66681#false} assume !(0 == ~E_3~0); {66681#false} is VALID [2022-02-21 04:23:27,930 INFO L290 TraceCheckUtils]: 37: Hoare triple {66681#false} assume !(0 == ~E_4~0); {66681#false} is VALID [2022-02-21 04:23:27,930 INFO L290 TraceCheckUtils]: 38: Hoare triple {66681#false} assume !(0 == ~E_5~0); {66681#false} is VALID [2022-02-21 04:23:27,930 INFO L290 TraceCheckUtils]: 39: Hoare triple {66681#false} assume !(0 == ~E_6~0); {66681#false} is VALID [2022-02-21 04:23:27,930 INFO L290 TraceCheckUtils]: 40: Hoare triple {66681#false} assume !(0 == ~E_7~0); {66681#false} is VALID [2022-02-21 04:23:27,930 INFO L290 TraceCheckUtils]: 41: Hoare triple {66681#false} assume !(0 == ~E_8~0); {66681#false} is VALID [2022-02-21 04:23:27,930 INFO L290 TraceCheckUtils]: 42: Hoare triple {66681#false} assume !(0 == ~E_9~0); {66681#false} is VALID [2022-02-21 04:23:27,930 INFO L290 TraceCheckUtils]: 43: Hoare triple {66681#false} assume 0 == ~E_10~0;~E_10~0 := 1; {66681#false} is VALID [2022-02-21 04:23:27,930 INFO L290 TraceCheckUtils]: 44: Hoare triple {66681#false} assume !(0 == ~E_11~0); {66681#false} is VALID [2022-02-21 04:23:27,930 INFO L290 TraceCheckUtils]: 45: Hoare triple {66681#false} assume !(0 == ~E_12~0); {66681#false} is VALID [2022-02-21 04:23:27,930 INFO L290 TraceCheckUtils]: 46: Hoare triple {66681#false} assume !(0 == ~E_13~0); {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 47: Hoare triple {66681#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 48: Hoare triple {66681#false} assume !(1 == ~m_pc~0); {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 49: Hoare triple {66681#false} is_master_triggered_~__retres1~0#1 := 0; {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 50: Hoare triple {66681#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 51: Hoare triple {66681#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 52: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp~1#1); {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 53: Hoare triple {66681#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 54: Hoare triple {66681#false} assume 1 == ~t1_pc~0; {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 55: Hoare triple {66681#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 56: Hoare triple {66681#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66681#false} is VALID [2022-02-21 04:23:27,931 INFO L290 TraceCheckUtils]: 57: Hoare triple {66681#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {66681#false} is VALID [2022-02-21 04:23:27,932 INFO L290 TraceCheckUtils]: 58: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___0~0#1); {66681#false} is VALID [2022-02-21 04:23:27,932 INFO L290 TraceCheckUtils]: 59: Hoare triple {66681#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66681#false} is VALID [2022-02-21 04:23:27,932 INFO L290 TraceCheckUtils]: 60: Hoare triple {66681#false} assume 1 == ~t2_pc~0; {66681#false} is VALID [2022-02-21 04:23:27,932 INFO L290 TraceCheckUtils]: 61: Hoare triple {66681#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {66681#false} is VALID [2022-02-21 04:23:27,932 INFO L290 TraceCheckUtils]: 62: Hoare triple {66681#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66681#false} is VALID [2022-02-21 04:23:27,932 INFO L290 TraceCheckUtils]: 63: Hoare triple {66681#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {66681#false} is VALID [2022-02-21 04:23:27,932 INFO L290 TraceCheckUtils]: 64: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___1~0#1); {66681#false} is VALID [2022-02-21 04:23:27,932 INFO L290 TraceCheckUtils]: 65: Hoare triple {66681#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66681#false} is VALID [2022-02-21 04:23:27,932 INFO L290 TraceCheckUtils]: 66: Hoare triple {66681#false} assume !(1 == ~t3_pc~0); {66681#false} is VALID [2022-02-21 04:23:27,932 INFO L290 TraceCheckUtils]: 67: Hoare triple {66681#false} is_transmit3_triggered_~__retres1~3#1 := 0; {66681#false} is VALID [2022-02-21 04:23:27,933 INFO L290 TraceCheckUtils]: 68: Hoare triple {66681#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66681#false} is VALID [2022-02-21 04:23:27,933 INFO L290 TraceCheckUtils]: 69: Hoare triple {66681#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {66681#false} is VALID [2022-02-21 04:23:27,933 INFO L290 TraceCheckUtils]: 70: Hoare triple {66681#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {66681#false} is VALID [2022-02-21 04:23:27,933 INFO L290 TraceCheckUtils]: 71: Hoare triple {66681#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66681#false} is VALID [2022-02-21 04:23:27,933 INFO L290 TraceCheckUtils]: 72: Hoare triple {66681#false} assume 1 == ~t4_pc~0; {66681#false} is VALID [2022-02-21 04:23:27,933 INFO L290 TraceCheckUtils]: 73: Hoare triple {66681#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {66681#false} is VALID [2022-02-21 04:23:27,933 INFO L290 TraceCheckUtils]: 74: Hoare triple {66681#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66681#false} is VALID [2022-02-21 04:23:27,933 INFO L290 TraceCheckUtils]: 75: Hoare triple {66681#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {66681#false} is VALID [2022-02-21 04:23:27,933 INFO L290 TraceCheckUtils]: 76: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___3~0#1); {66681#false} is VALID [2022-02-21 04:23:27,933 INFO L290 TraceCheckUtils]: 77: Hoare triple {66681#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 78: Hoare triple {66681#false} assume !(1 == ~t5_pc~0); {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 79: Hoare triple {66681#false} is_transmit5_triggered_~__retres1~5#1 := 0; {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 80: Hoare triple {66681#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 81: Hoare triple {66681#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 82: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___4~0#1); {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 83: Hoare triple {66681#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 84: Hoare triple {66681#false} assume 1 == ~t6_pc~0; {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 85: Hoare triple {66681#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 86: Hoare triple {66681#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 87: Hoare triple {66681#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {66681#false} is VALID [2022-02-21 04:23:27,934 INFO L290 TraceCheckUtils]: 88: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___5~0#1); {66681#false} is VALID [2022-02-21 04:23:27,935 INFO L290 TraceCheckUtils]: 89: Hoare triple {66681#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {66681#false} is VALID [2022-02-21 04:23:27,935 INFO L290 TraceCheckUtils]: 90: Hoare triple {66681#false} assume !(1 == ~t7_pc~0); {66681#false} is VALID [2022-02-21 04:23:27,935 INFO L290 TraceCheckUtils]: 91: Hoare triple {66681#false} is_transmit7_triggered_~__retres1~7#1 := 0; {66681#false} is VALID [2022-02-21 04:23:27,935 INFO L290 TraceCheckUtils]: 92: Hoare triple {66681#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {66681#false} is VALID [2022-02-21 04:23:27,935 INFO L290 TraceCheckUtils]: 93: Hoare triple {66681#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {66681#false} is VALID [2022-02-21 04:23:27,935 INFO L290 TraceCheckUtils]: 94: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___6~0#1); {66681#false} is VALID [2022-02-21 04:23:27,935 INFO L290 TraceCheckUtils]: 95: Hoare triple {66681#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {66681#false} is VALID [2022-02-21 04:23:27,935 INFO L290 TraceCheckUtils]: 96: Hoare triple {66681#false} assume 1 == ~t8_pc~0; {66681#false} is VALID [2022-02-21 04:23:27,935 INFO L290 TraceCheckUtils]: 97: Hoare triple {66681#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {66681#false} is VALID [2022-02-21 04:23:27,935 INFO L290 TraceCheckUtils]: 98: Hoare triple {66681#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 99: Hoare triple {66681#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 100: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___7~0#1); {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 101: Hoare triple {66681#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 102: Hoare triple {66681#false} assume 1 == ~t9_pc~0; {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 103: Hoare triple {66681#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 104: Hoare triple {66681#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 105: Hoare triple {66681#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 106: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___8~0#1); {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 107: Hoare triple {66681#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 108: Hoare triple {66681#false} assume !(1 == ~t10_pc~0); {66681#false} is VALID [2022-02-21 04:23:27,936 INFO L290 TraceCheckUtils]: 109: Hoare triple {66681#false} is_transmit10_triggered_~__retres1~10#1 := 0; {66681#false} is VALID [2022-02-21 04:23:27,937 INFO L290 TraceCheckUtils]: 110: Hoare triple {66681#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {66681#false} is VALID [2022-02-21 04:23:27,937 INFO L290 TraceCheckUtils]: 111: Hoare triple {66681#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {66681#false} is VALID [2022-02-21 04:23:27,937 INFO L290 TraceCheckUtils]: 112: Hoare triple {66681#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {66681#false} is VALID [2022-02-21 04:23:27,937 INFO L290 TraceCheckUtils]: 113: Hoare triple {66681#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {66681#false} is VALID [2022-02-21 04:23:27,937 INFO L290 TraceCheckUtils]: 114: Hoare triple {66681#false} assume 1 == ~t11_pc~0; {66681#false} is VALID [2022-02-21 04:23:27,937 INFO L290 TraceCheckUtils]: 115: Hoare triple {66681#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {66681#false} is VALID [2022-02-21 04:23:27,937 INFO L290 TraceCheckUtils]: 116: Hoare triple {66681#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {66681#false} is VALID [2022-02-21 04:23:27,937 INFO L290 TraceCheckUtils]: 117: Hoare triple {66681#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {66681#false} is VALID [2022-02-21 04:23:27,937 INFO L290 TraceCheckUtils]: 118: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___10~0#1); {66681#false} is VALID [2022-02-21 04:23:27,937 INFO L290 TraceCheckUtils]: 119: Hoare triple {66681#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {66681#false} is VALID [2022-02-21 04:23:27,938 INFO L290 TraceCheckUtils]: 120: Hoare triple {66681#false} assume !(1 == ~t12_pc~0); {66681#false} is VALID [2022-02-21 04:23:27,938 INFO L290 TraceCheckUtils]: 121: Hoare triple {66681#false} is_transmit12_triggered_~__retres1~12#1 := 0; {66681#false} is VALID [2022-02-21 04:23:27,938 INFO L290 TraceCheckUtils]: 122: Hoare triple {66681#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {66681#false} is VALID [2022-02-21 04:23:27,938 INFO L290 TraceCheckUtils]: 123: Hoare triple {66681#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {66681#false} is VALID [2022-02-21 04:23:27,938 INFO L290 TraceCheckUtils]: 124: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___11~0#1); {66681#false} is VALID [2022-02-21 04:23:27,938 INFO L290 TraceCheckUtils]: 125: Hoare triple {66681#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {66681#false} is VALID [2022-02-21 04:23:27,938 INFO L290 TraceCheckUtils]: 126: Hoare triple {66681#false} assume 1 == ~t13_pc~0; {66681#false} is VALID [2022-02-21 04:23:27,938 INFO L290 TraceCheckUtils]: 127: Hoare triple {66681#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {66681#false} is VALID [2022-02-21 04:23:27,938 INFO L290 TraceCheckUtils]: 128: Hoare triple {66681#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {66681#false} is VALID [2022-02-21 04:23:27,938 INFO L290 TraceCheckUtils]: 129: Hoare triple {66681#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {66681#false} is VALID [2022-02-21 04:23:27,939 INFO L290 TraceCheckUtils]: 130: Hoare triple {66681#false} assume !(0 != activate_threads_~tmp___12~0#1); {66681#false} is VALID [2022-02-21 04:23:27,939 INFO L290 TraceCheckUtils]: 131: Hoare triple {66681#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66681#false} is VALID [2022-02-21 04:23:27,939 INFO L290 TraceCheckUtils]: 132: Hoare triple {66681#false} assume !(1 == ~M_E~0); {66681#false} is VALID [2022-02-21 04:23:27,939 INFO L290 TraceCheckUtils]: 133: Hoare triple {66681#false} assume !(1 == ~T1_E~0); {66681#false} is VALID [2022-02-21 04:23:27,939 INFO L290 TraceCheckUtils]: 134: Hoare triple {66681#false} assume !(1 == ~T2_E~0); {66681#false} is VALID [2022-02-21 04:23:27,939 INFO L290 TraceCheckUtils]: 135: Hoare triple {66681#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {66681#false} is VALID [2022-02-21 04:23:27,939 INFO L290 TraceCheckUtils]: 136: Hoare triple {66681#false} assume !(1 == ~T4_E~0); {66681#false} is VALID [2022-02-21 04:23:27,939 INFO L290 TraceCheckUtils]: 137: Hoare triple {66681#false} assume !(1 == ~T5_E~0); {66681#false} is VALID [2022-02-21 04:23:27,939 INFO L290 TraceCheckUtils]: 138: Hoare triple {66681#false} assume !(1 == ~T6_E~0); {66681#false} is VALID [2022-02-21 04:23:27,939 INFO L290 TraceCheckUtils]: 139: Hoare triple {66681#false} assume !(1 == ~T7_E~0); {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 140: Hoare triple {66681#false} assume !(1 == ~T8_E~0); {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 141: Hoare triple {66681#false} assume !(1 == ~T9_E~0); {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 142: Hoare triple {66681#false} assume !(1 == ~T10_E~0); {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 143: Hoare triple {66681#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 144: Hoare triple {66681#false} assume !(1 == ~T12_E~0); {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 145: Hoare triple {66681#false} assume !(1 == ~T13_E~0); {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 146: Hoare triple {66681#false} assume !(1 == ~E_M~0); {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 147: Hoare triple {66681#false} assume !(1 == ~E_1~0); {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 148: Hoare triple {66681#false} assume !(1 == ~E_2~0); {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 149: Hoare triple {66681#false} assume !(1 == ~E_3~0); {66681#false} is VALID [2022-02-21 04:23:27,940 INFO L290 TraceCheckUtils]: 150: Hoare triple {66681#false} assume !(1 == ~E_4~0); {66681#false} is VALID [2022-02-21 04:23:27,941 INFO L290 TraceCheckUtils]: 151: Hoare triple {66681#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66681#false} is VALID [2022-02-21 04:23:27,941 INFO L290 TraceCheckUtils]: 152: Hoare triple {66681#false} assume !(1 == ~E_6~0); {66681#false} is VALID [2022-02-21 04:23:27,941 INFO L290 TraceCheckUtils]: 153: Hoare triple {66681#false} assume !(1 == ~E_7~0); {66681#false} is VALID [2022-02-21 04:23:27,941 INFO L290 TraceCheckUtils]: 154: Hoare triple {66681#false} assume !(1 == ~E_8~0); {66681#false} is VALID [2022-02-21 04:23:27,941 INFO L290 TraceCheckUtils]: 155: Hoare triple {66681#false} assume !(1 == ~E_9~0); {66681#false} is VALID [2022-02-21 04:23:27,941 INFO L290 TraceCheckUtils]: 156: Hoare triple {66681#false} assume !(1 == ~E_10~0); {66681#false} is VALID [2022-02-21 04:23:27,941 INFO L290 TraceCheckUtils]: 157: Hoare triple {66681#false} assume !(1 == ~E_11~0); {66681#false} is VALID [2022-02-21 04:23:27,941 INFO L290 TraceCheckUtils]: 158: Hoare triple {66681#false} assume !(1 == ~E_12~0); {66681#false} is VALID [2022-02-21 04:23:27,941 INFO L290 TraceCheckUtils]: 159: Hoare triple {66681#false} assume 1 == ~E_13~0;~E_13~0 := 2; {66681#false} is VALID [2022-02-21 04:23:27,941 INFO L290 TraceCheckUtils]: 160: Hoare triple {66681#false} assume { :end_inline_reset_delta_events } true; {66681#false} is VALID [2022-02-21 04:23:27,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:27,942 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:27,942 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079571359] [2022-02-21 04:23:27,942 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079571359] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:27,942 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:27,942 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:27,942 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366069344] [2022-02-21 04:23:27,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:27,943 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:27,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:27,943 INFO L85 PathProgramCache]: Analyzing trace with hash -130029202, now seen corresponding path program 1 times [2022-02-21 04:23:27,943 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:27,943 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267338797] [2022-02-21 04:23:27,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:27,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:27,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:27,969 INFO L290 TraceCheckUtils]: 0: Hoare triple {66683#true} assume !false; {66683#true} is VALID [2022-02-21 04:23:27,969 INFO L290 TraceCheckUtils]: 1: Hoare triple {66683#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {66683#true} is VALID [2022-02-21 04:23:27,969 INFO L290 TraceCheckUtils]: 2: Hoare triple {66683#true} assume !false; {66683#true} is VALID [2022-02-21 04:23:27,969 INFO L290 TraceCheckUtils]: 3: Hoare triple {66683#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {66683#true} is VALID [2022-02-21 04:23:27,970 INFO L290 TraceCheckUtils]: 4: Hoare triple {66683#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {66683#true} is VALID [2022-02-21 04:23:27,970 INFO L290 TraceCheckUtils]: 5: Hoare triple {66683#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {66683#true} is VALID [2022-02-21 04:23:27,970 INFO L290 TraceCheckUtils]: 6: Hoare triple {66683#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {66683#true} is VALID [2022-02-21 04:23:27,970 INFO L290 TraceCheckUtils]: 7: Hoare triple {66683#true} assume !(0 != eval_~tmp~0#1); {66683#true} is VALID [2022-02-21 04:23:27,970 INFO L290 TraceCheckUtils]: 8: Hoare triple {66683#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {66683#true} is VALID [2022-02-21 04:23:27,970 INFO L290 TraceCheckUtils]: 9: Hoare triple {66683#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {66683#true} is VALID [2022-02-21 04:23:27,970 INFO L290 TraceCheckUtils]: 10: Hoare triple {66683#true} assume 0 == ~M_E~0;~M_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,971 INFO L290 TraceCheckUtils]: 11: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,971 INFO L290 TraceCheckUtils]: 12: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,971 INFO L290 TraceCheckUtils]: 13: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,971 INFO L290 TraceCheckUtils]: 14: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,972 INFO L290 TraceCheckUtils]: 15: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,972 INFO L290 TraceCheckUtils]: 16: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,972 INFO L290 TraceCheckUtils]: 17: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,973 INFO L290 TraceCheckUtils]: 18: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,973 INFO L290 TraceCheckUtils]: 19: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,973 INFO L290 TraceCheckUtils]: 20: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,973 INFO L290 TraceCheckUtils]: 21: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,974 INFO L290 TraceCheckUtils]: 22: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,974 INFO L290 TraceCheckUtils]: 23: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,974 INFO L290 TraceCheckUtils]: 24: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,974 INFO L290 TraceCheckUtils]: 25: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,975 INFO L290 TraceCheckUtils]: 26: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,975 INFO L290 TraceCheckUtils]: 27: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,975 INFO L290 TraceCheckUtils]: 28: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,975 INFO L290 TraceCheckUtils]: 29: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,976 INFO L290 TraceCheckUtils]: 30: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,976 INFO L290 TraceCheckUtils]: 31: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,976 INFO L290 TraceCheckUtils]: 32: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,976 INFO L290 TraceCheckUtils]: 33: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,977 INFO L290 TraceCheckUtils]: 34: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,977 INFO L290 TraceCheckUtils]: 35: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,977 INFO L290 TraceCheckUtils]: 36: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,978 INFO L290 TraceCheckUtils]: 37: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,978 INFO L290 TraceCheckUtils]: 38: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,978 INFO L290 TraceCheckUtils]: 39: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,978 INFO L290 TraceCheckUtils]: 40: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,979 INFO L290 TraceCheckUtils]: 41: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,979 INFO L290 TraceCheckUtils]: 42: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,979 INFO L290 TraceCheckUtils]: 43: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,979 INFO L290 TraceCheckUtils]: 44: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,980 INFO L290 TraceCheckUtils]: 45: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,980 INFO L290 TraceCheckUtils]: 46: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,980 INFO L290 TraceCheckUtils]: 47: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,980 INFO L290 TraceCheckUtils]: 48: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,981 INFO L290 TraceCheckUtils]: 49: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,981 INFO L290 TraceCheckUtils]: 50: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,981 INFO L290 TraceCheckUtils]: 51: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,982 INFO L290 TraceCheckUtils]: 52: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,982 INFO L290 TraceCheckUtils]: 53: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,982 INFO L290 TraceCheckUtils]: 54: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,982 INFO L290 TraceCheckUtils]: 55: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,983 INFO L290 TraceCheckUtils]: 56: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,983 INFO L290 TraceCheckUtils]: 57: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,983 INFO L290 TraceCheckUtils]: 58: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,983 INFO L290 TraceCheckUtils]: 59: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,984 INFO L290 TraceCheckUtils]: 60: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,984 INFO L290 TraceCheckUtils]: 61: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,984 INFO L290 TraceCheckUtils]: 62: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,984 INFO L290 TraceCheckUtils]: 63: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,985 INFO L290 TraceCheckUtils]: 64: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,985 INFO L290 TraceCheckUtils]: 65: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,985 INFO L290 TraceCheckUtils]: 66: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,986 INFO L290 TraceCheckUtils]: 67: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,986 INFO L290 TraceCheckUtils]: 68: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,986 INFO L290 TraceCheckUtils]: 69: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,986 INFO L290 TraceCheckUtils]: 70: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,987 INFO L290 TraceCheckUtils]: 71: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,987 INFO L290 TraceCheckUtils]: 72: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,987 INFO L290 TraceCheckUtils]: 73: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,987 INFO L290 TraceCheckUtils]: 74: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,988 INFO L290 TraceCheckUtils]: 75: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,988 INFO L290 TraceCheckUtils]: 76: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,988 INFO L290 TraceCheckUtils]: 77: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,988 INFO L290 TraceCheckUtils]: 78: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,989 INFO L290 TraceCheckUtils]: 79: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,989 INFO L290 TraceCheckUtils]: 80: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,989 INFO L290 TraceCheckUtils]: 81: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,990 INFO L290 TraceCheckUtils]: 82: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,990 INFO L290 TraceCheckUtils]: 83: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,990 INFO L290 TraceCheckUtils]: 84: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,991 INFO L290 TraceCheckUtils]: 85: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,991 INFO L290 TraceCheckUtils]: 86: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,991 INFO L290 TraceCheckUtils]: 87: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,991 INFO L290 TraceCheckUtils]: 88: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,992 INFO L290 TraceCheckUtils]: 89: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,992 INFO L290 TraceCheckUtils]: 90: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,992 INFO L290 TraceCheckUtils]: 91: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,992 INFO L290 TraceCheckUtils]: 92: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,993 INFO L290 TraceCheckUtils]: 93: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,993 INFO L290 TraceCheckUtils]: 94: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,993 INFO L290 TraceCheckUtils]: 95: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,994 INFO L290 TraceCheckUtils]: 96: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,994 INFO L290 TraceCheckUtils]: 97: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,994 INFO L290 TraceCheckUtils]: 98: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,994 INFO L290 TraceCheckUtils]: 99: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,995 INFO L290 TraceCheckUtils]: 100: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,995 INFO L290 TraceCheckUtils]: 101: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,995 INFO L290 TraceCheckUtils]: 102: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,995 INFO L290 TraceCheckUtils]: 103: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,996 INFO L290 TraceCheckUtils]: 104: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,996 INFO L290 TraceCheckUtils]: 105: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,996 INFO L290 TraceCheckUtils]: 106: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,996 INFO L290 TraceCheckUtils]: 107: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,997 INFO L290 TraceCheckUtils]: 108: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,997 INFO L290 TraceCheckUtils]: 109: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,997 INFO L290 TraceCheckUtils]: 110: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,998 INFO L290 TraceCheckUtils]: 111: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,998 INFO L290 TraceCheckUtils]: 112: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,998 INFO L290 TraceCheckUtils]: 113: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,998 INFO L290 TraceCheckUtils]: 114: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,999 INFO L290 TraceCheckUtils]: 115: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,999 INFO L290 TraceCheckUtils]: 116: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,999 INFO L290 TraceCheckUtils]: 117: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:27,999 INFO L290 TraceCheckUtils]: 118: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,000 INFO L290 TraceCheckUtils]: 119: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,000 INFO L290 TraceCheckUtils]: 120: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,000 INFO L290 TraceCheckUtils]: 121: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,000 INFO L290 TraceCheckUtils]: 122: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66685#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,001 INFO L290 TraceCheckUtils]: 123: Hoare triple {66685#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {66684#false} is VALID [2022-02-21 04:23:28,001 INFO L290 TraceCheckUtils]: 124: Hoare triple {66684#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,001 INFO L290 TraceCheckUtils]: 125: Hoare triple {66684#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,001 INFO L290 TraceCheckUtils]: 126: Hoare triple {66684#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,001 INFO L290 TraceCheckUtils]: 127: Hoare triple {66684#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,001 INFO L290 TraceCheckUtils]: 128: Hoare triple {66684#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,001 INFO L290 TraceCheckUtils]: 129: Hoare triple {66684#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,001 INFO L290 TraceCheckUtils]: 130: Hoare triple {66684#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,002 INFO L290 TraceCheckUtils]: 131: Hoare triple {66684#false} assume !(1 == ~T8_E~0); {66684#false} is VALID [2022-02-21 04:23:28,002 INFO L290 TraceCheckUtils]: 132: Hoare triple {66684#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,002 INFO L290 TraceCheckUtils]: 133: Hoare triple {66684#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,002 INFO L290 TraceCheckUtils]: 134: Hoare triple {66684#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,002 INFO L290 TraceCheckUtils]: 135: Hoare triple {66684#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,002 INFO L290 TraceCheckUtils]: 136: Hoare triple {66684#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,002 INFO L290 TraceCheckUtils]: 137: Hoare triple {66684#false} assume 1 == ~E_M~0;~E_M~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,002 INFO L290 TraceCheckUtils]: 138: Hoare triple {66684#false} assume 1 == ~E_1~0;~E_1~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,002 INFO L290 TraceCheckUtils]: 139: Hoare triple {66684#false} assume !(1 == ~E_2~0); {66684#false} is VALID [2022-02-21 04:23:28,002 INFO L290 TraceCheckUtils]: 140: Hoare triple {66684#false} assume 1 == ~E_3~0;~E_3~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,003 INFO L290 TraceCheckUtils]: 141: Hoare triple {66684#false} assume 1 == ~E_4~0;~E_4~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,003 INFO L290 TraceCheckUtils]: 142: Hoare triple {66684#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,003 INFO L290 TraceCheckUtils]: 143: Hoare triple {66684#false} assume 1 == ~E_6~0;~E_6~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,003 INFO L290 TraceCheckUtils]: 144: Hoare triple {66684#false} assume 1 == ~E_7~0;~E_7~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,003 INFO L290 TraceCheckUtils]: 145: Hoare triple {66684#false} assume 1 == ~E_8~0;~E_8~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,003 INFO L290 TraceCheckUtils]: 146: Hoare triple {66684#false} assume 1 == ~E_9~0;~E_9~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,003 INFO L290 TraceCheckUtils]: 147: Hoare triple {66684#false} assume !(1 == ~E_10~0); {66684#false} is VALID [2022-02-21 04:23:28,003 INFO L290 TraceCheckUtils]: 148: Hoare triple {66684#false} assume 1 == ~E_11~0;~E_11~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,003 INFO L290 TraceCheckUtils]: 149: Hoare triple {66684#false} assume 1 == ~E_12~0;~E_12~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,004 INFO L290 TraceCheckUtils]: 150: Hoare triple {66684#false} assume 1 == ~E_13~0;~E_13~0 := 2; {66684#false} is VALID [2022-02-21 04:23:28,004 INFO L290 TraceCheckUtils]: 151: Hoare triple {66684#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {66684#false} is VALID [2022-02-21 04:23:28,004 INFO L290 TraceCheckUtils]: 152: Hoare triple {66684#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {66684#false} is VALID [2022-02-21 04:23:28,004 INFO L290 TraceCheckUtils]: 153: Hoare triple {66684#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {66684#false} is VALID [2022-02-21 04:23:28,004 INFO L290 TraceCheckUtils]: 154: Hoare triple {66684#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {66684#false} is VALID [2022-02-21 04:23:28,004 INFO L290 TraceCheckUtils]: 155: Hoare triple {66684#false} assume !(0 == start_simulation_~tmp~3#1); {66684#false} is VALID [2022-02-21 04:23:28,004 INFO L290 TraceCheckUtils]: 156: Hoare triple {66684#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {66684#false} is VALID [2022-02-21 04:23:28,004 INFO L290 TraceCheckUtils]: 157: Hoare triple {66684#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {66684#false} is VALID [2022-02-21 04:23:28,004 INFO L290 TraceCheckUtils]: 158: Hoare triple {66684#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {66684#false} is VALID [2022-02-21 04:23:28,004 INFO L290 TraceCheckUtils]: 159: Hoare triple {66684#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {66684#false} is VALID [2022-02-21 04:23:28,005 INFO L290 TraceCheckUtils]: 160: Hoare triple {66684#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {66684#false} is VALID [2022-02-21 04:23:28,005 INFO L290 TraceCheckUtils]: 161: Hoare triple {66684#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {66684#false} is VALID [2022-02-21 04:23:28,005 INFO L290 TraceCheckUtils]: 162: Hoare triple {66684#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {66684#false} is VALID [2022-02-21 04:23:28,005 INFO L290 TraceCheckUtils]: 163: Hoare triple {66684#false} assume !(0 != start_simulation_~tmp___0~1#1); {66684#false} is VALID [2022-02-21 04:23:28,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:28,006 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:28,006 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267338797] [2022-02-21 04:23:28,006 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267338797] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:28,006 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:28,006 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:28,006 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529170506] [2022-02-21 04:23:28,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:28,006 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:28,007 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:28,007 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:28,007 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:28,007 INFO L87 Difference]: Start difference. First operand 2018 states and 2980 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,476 INFO L93 Difference]: Finished difference Result 2018 states and 2979 transitions. [2022-02-21 04:23:29,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:29,477 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,583 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:29,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2979 transitions. [2022-02-21 04:23:29,670 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:29,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2979 transitions. [2022-02-21 04:23:29,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:29,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:29,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2979 transitions. [2022-02-21 04:23:29,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:29,768 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2022-02-21 04:23:29,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2979 transitions. [2022-02-21 04:23:29,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:29,784 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:29,785 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2979 transitions. Second operand has 2018 states, 2018 states have (on average 1.4762140733399405) internal successors, (2979), 2017 states have internal predecessors, (2979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,786 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2979 transitions. Second operand has 2018 states, 2018 states have (on average 1.4762140733399405) internal successors, (2979), 2017 states have internal predecessors, (2979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,787 INFO L87 Difference]: Start difference. First operand 2018 states and 2979 transitions. Second operand has 2018 states, 2018 states have (on average 1.4762140733399405) internal successors, (2979), 2017 states have internal predecessors, (2979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,871 INFO L93 Difference]: Finished difference Result 2018 states and 2979 transitions. [2022-02-21 04:23:29,871 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2979 transitions. [2022-02-21 04:23:29,873 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:29,873 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:29,876 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.4762140733399405) internal successors, (2979), 2017 states have internal predecessors, (2979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2979 transitions. [2022-02-21 04:23:29,877 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.4762140733399405) internal successors, (2979), 2017 states have internal predecessors, (2979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2979 transitions. [2022-02-21 04:23:29,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,968 INFO L93 Difference]: Finished difference Result 2018 states and 2979 transitions. [2022-02-21 04:23:29,968 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2979 transitions. [2022-02-21 04:23:29,970 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:29,970 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:29,970 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:29,970 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:29,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4762140733399405) internal successors, (2979), 2017 states have internal predecessors, (2979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:30,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2979 transitions. [2022-02-21 04:23:30,064 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2022-02-21 04:23:30,064 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2022-02-21 04:23:30,064 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:23:30,064 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2979 transitions. [2022-02-21 04:23:30,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:30,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:30,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:30,069 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:30,069 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:30,070 INFO L791 eck$LassoCheckResult]: Stem: 69619#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 69620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 70656#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70111#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70112#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 69601#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69602#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69668#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69669#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 70107#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 70108#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69634#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69453#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 69454#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 69898#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 69899#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 69774#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 69775#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 69424#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69425#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 70648#L1279-2 assume !(0 == ~T1_E~0); 69047#L1284-1 assume !(0 == ~T2_E~0); 69048#L1289-1 assume !(0 == ~T3_E~0); 69771#L1294-1 assume !(0 == ~T4_E~0); 69772#L1299-1 assume !(0 == ~T5_E~0); 69783#L1304-1 assume !(0 == ~T6_E~0); 70714#L1309-1 assume !(0 == ~T7_E~0); 70715#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 68977#L1319-1 assume !(0 == ~T9_E~0); 68978#L1324-1 assume !(0 == ~T10_E~0); 69150#L1329-1 assume !(0 == ~T11_E~0); 69151#L1334-1 assume !(0 == ~T12_E~0); 70555#L1339-1 assume !(0 == ~T13_E~0); 70636#L1344-1 assume !(0 == ~E_M~0); 70637#L1349-1 assume !(0 == ~E_1~0); 69958#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 69959#L1359-1 assume !(0 == ~E_3~0); 70388#L1364-1 assume !(0 == ~E_4~0); 69279#L1369-1 assume !(0 == ~E_5~0); 69280#L1374-1 assume !(0 == ~E_6~0); 69963#L1379-1 assume !(0 == ~E_7~0); 69964#L1384-1 assume !(0 == ~E_8~0); 70041#L1389-1 assume !(0 == ~E_9~0); 70574#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 70575#L1399-1 assume !(0 == ~E_11~0); 70678#L1404-1 assume !(0 == ~E_12~0); 69372#L1409-1 assume !(0 == ~E_13~0); 69373#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70670#L628 assume !(1 == ~m_pc~0); 69276#L628-2 is_master_triggered_~__retres1~0#1 := 0; 69275#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70039#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70040#L1591 assume !(0 != activate_threads_~tmp~1#1); 70683#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69827#L647 assume 1 == ~t1_pc~0; 69196#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 69197#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69468#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69469#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 70623#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70624#L666 assume 1 == ~t2_pc~0; 69044#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69045#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69211#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70640#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 70159#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70160#L685 assume !(1 == ~t3_pc~0); 70265#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 70264#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69887#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69888#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70009#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69495#L704 assume 1 == ~t4_pc~0; 69496#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70020#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70021#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70661#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 69880#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69881#L723 assume !(1 == ~t5_pc~0); 70003#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 70239#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70383#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70138#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 70139#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69261#L742 assume 1 == ~t6_pc~0; 69262#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69410#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69411#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 68946#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 68947#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69338#L761 assume !(1 == ~t7_pc~0); 69339#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 69207#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69208#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70010#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 70011#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68971#L780 assume 1 == ~t8_pc~0; 68972#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69247#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69248#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69971#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 69972#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70091#L799 assume 1 == ~t9_pc~0; 70203#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68974#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68975#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70103#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 70310#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70121#L818 assume !(1 == ~t10_pc~0); 68755#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 68756#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70196#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 70125#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 70126#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 70166#L837 assume 1 == ~t11_pc~0; 70167#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 70001#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70404#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 70084#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 70085#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69836#L856 assume !(1 == ~t12_pc~0); 69837#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 70490#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70491#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 70471#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 70472#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70651#L875 assume 1 == ~t13_pc~0; 69781#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69413#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69414#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69353#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 69354#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70193#L1427 assume !(1 == ~M_E~0); 70177#L1427-2 assume !(1 == ~T1_E~0); 69325#L1432-1 assume !(1 == ~T2_E~0); 69326#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70394#L1442-1 assume !(1 == ~T4_E~0); 70395#L1447-1 assume !(1 == ~T5_E~0); 70250#L1452-1 assume !(1 == ~T6_E~0); 68890#L1457-1 assume !(1 == ~T7_E~0); 68891#L1462-1 assume !(1 == ~T8_E~0); 70421#L1467-1 assume !(1 == ~T9_E~0); 70439#L1472-1 assume !(1 == ~T10_E~0); 70440#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 70191#L1482-1 assume !(1 == ~T12_E~0); 70192#L1487-1 assume !(1 == ~T13_E~0); 69221#L1492-1 assume !(1 == ~E_M~0); 69222#L1497-1 assume !(1 == ~E_1~0); 69583#L1502-1 assume !(1 == ~E_2~0); 69584#L1507-1 assume !(1 == ~E_3~0); 69099#L1512-1 assume !(1 == ~E_4~0); 69100#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 70510#L1522-1 assume !(1 == ~E_6~0); 69824#L1527-1 assume !(1 == ~E_7~0); 69825#L1532-1 assume !(1 == ~E_8~0); 70698#L1537-1 assume !(1 == ~E_9~0); 70027#L1542-1 assume !(1 == ~E_10~0); 69858#L1547-1 assume !(1 == ~E_11~0); 69859#L1552-1 assume !(1 == ~E_12~0); 68794#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 68795#L1562-1 assume { :end_inline_reset_delta_events } true; 69401#L1928-2 [2022-02-21 04:23:30,070 INFO L793 eck$LassoCheckResult]: Loop: 69401#L1928-2 assume !false; 69892#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69055#L1254 assume !false; 69642#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69129#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69130#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69327#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 70498#L1067 assume !(0 != eval_~tmp~0#1); 69568#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69145#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69146#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 69605#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69587#L1284-3 assume !(0 == ~T2_E~0); 69588#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69566#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69567#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69954#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69955#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69464#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 69465#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 70461#L1324-3 assume !(0 == ~T10_E~0); 69096#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 69097#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 69864#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 69865#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 70163#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69445#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69446#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70174#L1364-3 assume !(0 == ~E_4~0); 70696#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70592#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69225#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 69226#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69443#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 69444#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 69734#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 70602#L1404-3 assume !(0 == ~E_12~0); 70566#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 70567#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70053#L628-45 assume 1 == ~m_pc~0; 69731#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 69733#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69090#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69091#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69479#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70202#L647-45 assume 1 == ~t1_pc~0; 69041#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 69042#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69970#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69155#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69156#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69367#L666-45 assume 1 == ~t2_pc~0; 69369#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69849#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70411#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70326#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70320#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68905#L685-45 assume !(1 == ~t3_pc~0); 68907#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 69965#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70639#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70508#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70509#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70649#L704-45 assume 1 == ~t4_pc~0; 70528#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68772#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69631#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69974#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70721#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70086#L723-45 assume !(1 == ~t5_pc~0); 70087#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 70576#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69678#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69455#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 69456#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70480#L742-45 assume 1 == ~t6_pc~0; 70481#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69703#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70172#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70208#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 70209#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70297#L761-45 assume 1 == ~t7_pc~0; 70299#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69696#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69697#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69103#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69104#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70570#L780-45 assume 1 == ~t8_pc~0; 69481#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69115#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69116#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70697#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 69085#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69086#L799-45 assume 1 == ~t9_pc~0; 69862#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69307#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70622#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70251#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70252#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69023#L818-45 assume !(1 == ~t10_pc~0); 69025#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 69142#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70225#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69629#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69630#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 70345#L837-45 assume !(1 == ~t11_pc~0); 69560#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 69561#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69698#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 70363#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 69161#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69162#L856-45 assume 1 == ~t12_pc~0; 70647#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 69164#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69105#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69106#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69968#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69969#L875-45 assume 1 == ~t13_pc~0; 69939#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69940#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 70002#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 70614#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 70615#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70554#L1427-3 assume !(1 == ~M_E~0); 69765#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69766#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70304#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69956#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69957#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 68813#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 68814#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70496#L1462-3 assume !(1 == ~T8_E~0); 70497#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70360#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 70361#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69064#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 69065#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 69206#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69379#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69380#L1502-3 assume !(1 == ~E_2~0); 70328#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70459#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69417#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69109#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69110#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 69074#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 69075#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70175#L1542-3 assume !(1 == ~E_10~0); 70313#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69942#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69943#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 69285#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69286#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68705#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69470#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 69471#L1947 assume !(0 == start_simulation_~tmp~3#1); 70076#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 70281#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69342#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 70674#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 70598#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70428#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70187#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 70188#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 69401#L1928-2 [2022-02-21 04:23:30,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:30,071 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2022-02-21 04:23:30,071 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:30,072 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006424984] [2022-02-21 04:23:30,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:30,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:30,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:30,105 INFO L290 TraceCheckUtils]: 0: Hoare triple {74761#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {74761#true} is VALID [2022-02-21 04:23:30,105 INFO L290 TraceCheckUtils]: 1: Hoare triple {74761#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,105 INFO L290 TraceCheckUtils]: 2: Hoare triple {74763#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,106 INFO L290 TraceCheckUtils]: 3: Hoare triple {74763#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,106 INFO L290 TraceCheckUtils]: 4: Hoare triple {74763#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,106 INFO L290 TraceCheckUtils]: 5: Hoare triple {74763#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,107 INFO L290 TraceCheckUtils]: 6: Hoare triple {74763#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,107 INFO L290 TraceCheckUtils]: 7: Hoare triple {74763#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,107 INFO L290 TraceCheckUtils]: 8: Hoare triple {74763#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,107 INFO L290 TraceCheckUtils]: 9: Hoare triple {74763#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,108 INFO L290 TraceCheckUtils]: 10: Hoare triple {74763#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,108 INFO L290 TraceCheckUtils]: 11: Hoare triple {74763#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,108 INFO L290 TraceCheckUtils]: 12: Hoare triple {74763#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,109 INFO L290 TraceCheckUtils]: 13: Hoare triple {74763#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {74763#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:30,109 INFO L290 TraceCheckUtils]: 14: Hoare triple {74763#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {74762#false} is VALID [2022-02-21 04:23:30,109 INFO L290 TraceCheckUtils]: 15: Hoare triple {74762#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {74762#false} is VALID [2022-02-21 04:23:30,109 INFO L290 TraceCheckUtils]: 16: Hoare triple {74762#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {74762#false} is VALID [2022-02-21 04:23:30,109 INFO L290 TraceCheckUtils]: 17: Hoare triple {74762#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {74762#false} is VALID [2022-02-21 04:23:30,109 INFO L290 TraceCheckUtils]: 18: Hoare triple {74762#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {74762#false} is VALID [2022-02-21 04:23:30,109 INFO L290 TraceCheckUtils]: 19: Hoare triple {74762#false} assume 0 == ~M_E~0;~M_E~0 := 1; {74762#false} is VALID [2022-02-21 04:23:30,110 INFO L290 TraceCheckUtils]: 20: Hoare triple {74762#false} assume !(0 == ~T1_E~0); {74762#false} is VALID [2022-02-21 04:23:30,110 INFO L290 TraceCheckUtils]: 21: Hoare triple {74762#false} assume !(0 == ~T2_E~0); {74762#false} is VALID [2022-02-21 04:23:30,110 INFO L290 TraceCheckUtils]: 22: Hoare triple {74762#false} assume !(0 == ~T3_E~0); {74762#false} is VALID [2022-02-21 04:23:30,110 INFO L290 TraceCheckUtils]: 23: Hoare triple {74762#false} assume !(0 == ~T4_E~0); {74762#false} is VALID [2022-02-21 04:23:30,110 INFO L290 TraceCheckUtils]: 24: Hoare triple {74762#false} assume !(0 == ~T5_E~0); {74762#false} is VALID [2022-02-21 04:23:30,110 INFO L290 TraceCheckUtils]: 25: Hoare triple {74762#false} assume !(0 == ~T6_E~0); {74762#false} is VALID [2022-02-21 04:23:30,110 INFO L290 TraceCheckUtils]: 26: Hoare triple {74762#false} assume !(0 == ~T7_E~0); {74762#false} is VALID [2022-02-21 04:23:30,110 INFO L290 TraceCheckUtils]: 27: Hoare triple {74762#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {74762#false} is VALID [2022-02-21 04:23:30,111 INFO L290 TraceCheckUtils]: 28: Hoare triple {74762#false} assume !(0 == ~T9_E~0); {74762#false} is VALID [2022-02-21 04:23:30,111 INFO L290 TraceCheckUtils]: 29: Hoare triple {74762#false} assume !(0 == ~T10_E~0); {74762#false} is VALID [2022-02-21 04:23:30,111 INFO L290 TraceCheckUtils]: 30: Hoare triple {74762#false} assume !(0 == ~T11_E~0); {74762#false} is VALID [2022-02-21 04:23:30,111 INFO L290 TraceCheckUtils]: 31: Hoare triple {74762#false} assume !(0 == ~T12_E~0); {74762#false} is VALID [2022-02-21 04:23:30,111 INFO L290 TraceCheckUtils]: 32: Hoare triple {74762#false} assume !(0 == ~T13_E~0); {74762#false} is VALID [2022-02-21 04:23:30,111 INFO L290 TraceCheckUtils]: 33: Hoare triple {74762#false} assume !(0 == ~E_M~0); {74762#false} is VALID [2022-02-21 04:23:30,111 INFO L290 TraceCheckUtils]: 34: Hoare triple {74762#false} assume !(0 == ~E_1~0); {74762#false} is VALID [2022-02-21 04:23:30,111 INFO L290 TraceCheckUtils]: 35: Hoare triple {74762#false} assume 0 == ~E_2~0;~E_2~0 := 1; {74762#false} is VALID [2022-02-21 04:23:30,112 INFO L290 TraceCheckUtils]: 36: Hoare triple {74762#false} assume !(0 == ~E_3~0); {74762#false} is VALID [2022-02-21 04:23:30,112 INFO L290 TraceCheckUtils]: 37: Hoare triple {74762#false} assume !(0 == ~E_4~0); {74762#false} is VALID [2022-02-21 04:23:30,112 INFO L290 TraceCheckUtils]: 38: Hoare triple {74762#false} assume !(0 == ~E_5~0); {74762#false} is VALID [2022-02-21 04:23:30,112 INFO L290 TraceCheckUtils]: 39: Hoare triple {74762#false} assume !(0 == ~E_6~0); {74762#false} is VALID [2022-02-21 04:23:30,112 INFO L290 TraceCheckUtils]: 40: Hoare triple {74762#false} assume !(0 == ~E_7~0); {74762#false} is VALID [2022-02-21 04:23:30,112 INFO L290 TraceCheckUtils]: 41: Hoare triple {74762#false} assume !(0 == ~E_8~0); {74762#false} is VALID [2022-02-21 04:23:30,112 INFO L290 TraceCheckUtils]: 42: Hoare triple {74762#false} assume !(0 == ~E_9~0); {74762#false} is VALID [2022-02-21 04:23:30,112 INFO L290 TraceCheckUtils]: 43: Hoare triple {74762#false} assume 0 == ~E_10~0;~E_10~0 := 1; {74762#false} is VALID [2022-02-21 04:23:30,112 INFO L290 TraceCheckUtils]: 44: Hoare triple {74762#false} assume !(0 == ~E_11~0); {74762#false} is VALID [2022-02-21 04:23:30,113 INFO L290 TraceCheckUtils]: 45: Hoare triple {74762#false} assume !(0 == ~E_12~0); {74762#false} is VALID [2022-02-21 04:23:30,113 INFO L290 TraceCheckUtils]: 46: Hoare triple {74762#false} assume !(0 == ~E_13~0); {74762#false} is VALID [2022-02-21 04:23:30,113 INFO L290 TraceCheckUtils]: 47: Hoare triple {74762#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {74762#false} is VALID [2022-02-21 04:23:30,113 INFO L290 TraceCheckUtils]: 48: Hoare triple {74762#false} assume !(1 == ~m_pc~0); {74762#false} is VALID [2022-02-21 04:23:30,113 INFO L290 TraceCheckUtils]: 49: Hoare triple {74762#false} is_master_triggered_~__retres1~0#1 := 0; {74762#false} is VALID [2022-02-21 04:23:30,113 INFO L290 TraceCheckUtils]: 50: Hoare triple {74762#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {74762#false} is VALID [2022-02-21 04:23:30,113 INFO L290 TraceCheckUtils]: 51: Hoare triple {74762#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {74762#false} is VALID [2022-02-21 04:23:30,113 INFO L290 TraceCheckUtils]: 52: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp~1#1); {74762#false} is VALID [2022-02-21 04:23:30,113 INFO L290 TraceCheckUtils]: 53: Hoare triple {74762#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {74762#false} is VALID [2022-02-21 04:23:30,114 INFO L290 TraceCheckUtils]: 54: Hoare triple {74762#false} assume 1 == ~t1_pc~0; {74762#false} is VALID [2022-02-21 04:23:30,114 INFO L290 TraceCheckUtils]: 55: Hoare triple {74762#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {74762#false} is VALID [2022-02-21 04:23:30,114 INFO L290 TraceCheckUtils]: 56: Hoare triple {74762#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {74762#false} is VALID [2022-02-21 04:23:30,114 INFO L290 TraceCheckUtils]: 57: Hoare triple {74762#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {74762#false} is VALID [2022-02-21 04:23:30,114 INFO L290 TraceCheckUtils]: 58: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___0~0#1); {74762#false} is VALID [2022-02-21 04:23:30,114 INFO L290 TraceCheckUtils]: 59: Hoare triple {74762#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {74762#false} is VALID [2022-02-21 04:23:30,114 INFO L290 TraceCheckUtils]: 60: Hoare triple {74762#false} assume 1 == ~t2_pc~0; {74762#false} is VALID [2022-02-21 04:23:30,114 INFO L290 TraceCheckUtils]: 61: Hoare triple {74762#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {74762#false} is VALID [2022-02-21 04:23:30,115 INFO L290 TraceCheckUtils]: 62: Hoare triple {74762#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {74762#false} is VALID [2022-02-21 04:23:30,115 INFO L290 TraceCheckUtils]: 63: Hoare triple {74762#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {74762#false} is VALID [2022-02-21 04:23:30,115 INFO L290 TraceCheckUtils]: 64: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___1~0#1); {74762#false} is VALID [2022-02-21 04:23:30,115 INFO L290 TraceCheckUtils]: 65: Hoare triple {74762#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {74762#false} is VALID [2022-02-21 04:23:30,115 INFO L290 TraceCheckUtils]: 66: Hoare triple {74762#false} assume !(1 == ~t3_pc~0); {74762#false} is VALID [2022-02-21 04:23:30,115 INFO L290 TraceCheckUtils]: 67: Hoare triple {74762#false} is_transmit3_triggered_~__retres1~3#1 := 0; {74762#false} is VALID [2022-02-21 04:23:30,115 INFO L290 TraceCheckUtils]: 68: Hoare triple {74762#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {74762#false} is VALID [2022-02-21 04:23:30,115 INFO L290 TraceCheckUtils]: 69: Hoare triple {74762#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {74762#false} is VALID [2022-02-21 04:23:30,115 INFO L290 TraceCheckUtils]: 70: Hoare triple {74762#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {74762#false} is VALID [2022-02-21 04:23:30,116 INFO L290 TraceCheckUtils]: 71: Hoare triple {74762#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {74762#false} is VALID [2022-02-21 04:23:30,116 INFO L290 TraceCheckUtils]: 72: Hoare triple {74762#false} assume 1 == ~t4_pc~0; {74762#false} is VALID [2022-02-21 04:23:30,116 INFO L290 TraceCheckUtils]: 73: Hoare triple {74762#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {74762#false} is VALID [2022-02-21 04:23:30,116 INFO L290 TraceCheckUtils]: 74: Hoare triple {74762#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {74762#false} is VALID [2022-02-21 04:23:30,116 INFO L290 TraceCheckUtils]: 75: Hoare triple {74762#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {74762#false} is VALID [2022-02-21 04:23:30,116 INFO L290 TraceCheckUtils]: 76: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___3~0#1); {74762#false} is VALID [2022-02-21 04:23:30,116 INFO L290 TraceCheckUtils]: 77: Hoare triple {74762#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {74762#false} is VALID [2022-02-21 04:23:30,116 INFO L290 TraceCheckUtils]: 78: Hoare triple {74762#false} assume !(1 == ~t5_pc~0); {74762#false} is VALID [2022-02-21 04:23:30,116 INFO L290 TraceCheckUtils]: 79: Hoare triple {74762#false} is_transmit5_triggered_~__retres1~5#1 := 0; {74762#false} is VALID [2022-02-21 04:23:30,117 INFO L290 TraceCheckUtils]: 80: Hoare triple {74762#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {74762#false} is VALID [2022-02-21 04:23:30,117 INFO L290 TraceCheckUtils]: 81: Hoare triple {74762#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {74762#false} is VALID [2022-02-21 04:23:30,117 INFO L290 TraceCheckUtils]: 82: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___4~0#1); {74762#false} is VALID [2022-02-21 04:23:30,117 INFO L290 TraceCheckUtils]: 83: Hoare triple {74762#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {74762#false} is VALID [2022-02-21 04:23:30,117 INFO L290 TraceCheckUtils]: 84: Hoare triple {74762#false} assume 1 == ~t6_pc~0; {74762#false} is VALID [2022-02-21 04:23:30,117 INFO L290 TraceCheckUtils]: 85: Hoare triple {74762#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {74762#false} is VALID [2022-02-21 04:23:30,117 INFO L290 TraceCheckUtils]: 86: Hoare triple {74762#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {74762#false} is VALID [2022-02-21 04:23:30,117 INFO L290 TraceCheckUtils]: 87: Hoare triple {74762#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {74762#false} is VALID [2022-02-21 04:23:30,117 INFO L290 TraceCheckUtils]: 88: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___5~0#1); {74762#false} is VALID [2022-02-21 04:23:30,118 INFO L290 TraceCheckUtils]: 89: Hoare triple {74762#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {74762#false} is VALID [2022-02-21 04:23:30,118 INFO L290 TraceCheckUtils]: 90: Hoare triple {74762#false} assume !(1 == ~t7_pc~0); {74762#false} is VALID [2022-02-21 04:23:30,118 INFO L290 TraceCheckUtils]: 91: Hoare triple {74762#false} is_transmit7_triggered_~__retres1~7#1 := 0; {74762#false} is VALID [2022-02-21 04:23:30,118 INFO L290 TraceCheckUtils]: 92: Hoare triple {74762#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {74762#false} is VALID [2022-02-21 04:23:30,118 INFO L290 TraceCheckUtils]: 93: Hoare triple {74762#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {74762#false} is VALID [2022-02-21 04:23:30,118 INFO L290 TraceCheckUtils]: 94: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___6~0#1); {74762#false} is VALID [2022-02-21 04:23:30,118 INFO L290 TraceCheckUtils]: 95: Hoare triple {74762#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {74762#false} is VALID [2022-02-21 04:23:30,118 INFO L290 TraceCheckUtils]: 96: Hoare triple {74762#false} assume 1 == ~t8_pc~0; {74762#false} is VALID [2022-02-21 04:23:30,118 INFO L290 TraceCheckUtils]: 97: Hoare triple {74762#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {74762#false} is VALID [2022-02-21 04:23:30,119 INFO L290 TraceCheckUtils]: 98: Hoare triple {74762#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {74762#false} is VALID [2022-02-21 04:23:30,119 INFO L290 TraceCheckUtils]: 99: Hoare triple {74762#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {74762#false} is VALID [2022-02-21 04:23:30,119 INFO L290 TraceCheckUtils]: 100: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___7~0#1); {74762#false} is VALID [2022-02-21 04:23:30,119 INFO L290 TraceCheckUtils]: 101: Hoare triple {74762#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {74762#false} is VALID [2022-02-21 04:23:30,119 INFO L290 TraceCheckUtils]: 102: Hoare triple {74762#false} assume 1 == ~t9_pc~0; {74762#false} is VALID [2022-02-21 04:23:30,119 INFO L290 TraceCheckUtils]: 103: Hoare triple {74762#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {74762#false} is VALID [2022-02-21 04:23:30,119 INFO L290 TraceCheckUtils]: 104: Hoare triple {74762#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {74762#false} is VALID [2022-02-21 04:23:30,119 INFO L290 TraceCheckUtils]: 105: Hoare triple {74762#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {74762#false} is VALID [2022-02-21 04:23:30,119 INFO L290 TraceCheckUtils]: 106: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___8~0#1); {74762#false} is VALID [2022-02-21 04:23:30,120 INFO L290 TraceCheckUtils]: 107: Hoare triple {74762#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {74762#false} is VALID [2022-02-21 04:23:30,120 INFO L290 TraceCheckUtils]: 108: Hoare triple {74762#false} assume !(1 == ~t10_pc~0); {74762#false} is VALID [2022-02-21 04:23:30,120 INFO L290 TraceCheckUtils]: 109: Hoare triple {74762#false} is_transmit10_triggered_~__retres1~10#1 := 0; {74762#false} is VALID [2022-02-21 04:23:30,120 INFO L290 TraceCheckUtils]: 110: Hoare triple {74762#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {74762#false} is VALID [2022-02-21 04:23:30,120 INFO L290 TraceCheckUtils]: 111: Hoare triple {74762#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {74762#false} is VALID [2022-02-21 04:23:30,120 INFO L290 TraceCheckUtils]: 112: Hoare triple {74762#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {74762#false} is VALID [2022-02-21 04:23:30,120 INFO L290 TraceCheckUtils]: 113: Hoare triple {74762#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {74762#false} is VALID [2022-02-21 04:23:30,120 INFO L290 TraceCheckUtils]: 114: Hoare triple {74762#false} assume 1 == ~t11_pc~0; {74762#false} is VALID [2022-02-21 04:23:30,121 INFO L290 TraceCheckUtils]: 115: Hoare triple {74762#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {74762#false} is VALID [2022-02-21 04:23:30,121 INFO L290 TraceCheckUtils]: 116: Hoare triple {74762#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {74762#false} is VALID [2022-02-21 04:23:30,121 INFO L290 TraceCheckUtils]: 117: Hoare triple {74762#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {74762#false} is VALID [2022-02-21 04:23:30,121 INFO L290 TraceCheckUtils]: 118: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___10~0#1); {74762#false} is VALID [2022-02-21 04:23:30,121 INFO L290 TraceCheckUtils]: 119: Hoare triple {74762#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {74762#false} is VALID [2022-02-21 04:23:30,121 INFO L290 TraceCheckUtils]: 120: Hoare triple {74762#false} assume !(1 == ~t12_pc~0); {74762#false} is VALID [2022-02-21 04:23:30,121 INFO L290 TraceCheckUtils]: 121: Hoare triple {74762#false} is_transmit12_triggered_~__retres1~12#1 := 0; {74762#false} is VALID [2022-02-21 04:23:30,121 INFO L290 TraceCheckUtils]: 122: Hoare triple {74762#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {74762#false} is VALID [2022-02-21 04:23:30,121 INFO L290 TraceCheckUtils]: 123: Hoare triple {74762#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {74762#false} is VALID [2022-02-21 04:23:30,122 INFO L290 TraceCheckUtils]: 124: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___11~0#1); {74762#false} is VALID [2022-02-21 04:23:30,122 INFO L290 TraceCheckUtils]: 125: Hoare triple {74762#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {74762#false} is VALID [2022-02-21 04:23:30,122 INFO L290 TraceCheckUtils]: 126: Hoare triple {74762#false} assume 1 == ~t13_pc~0; {74762#false} is VALID [2022-02-21 04:23:30,122 INFO L290 TraceCheckUtils]: 127: Hoare triple {74762#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {74762#false} is VALID [2022-02-21 04:23:30,122 INFO L290 TraceCheckUtils]: 128: Hoare triple {74762#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {74762#false} is VALID [2022-02-21 04:23:30,122 INFO L290 TraceCheckUtils]: 129: Hoare triple {74762#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {74762#false} is VALID [2022-02-21 04:23:30,122 INFO L290 TraceCheckUtils]: 130: Hoare triple {74762#false} assume !(0 != activate_threads_~tmp___12~0#1); {74762#false} is VALID [2022-02-21 04:23:30,122 INFO L290 TraceCheckUtils]: 131: Hoare triple {74762#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {74762#false} is VALID [2022-02-21 04:23:30,122 INFO L290 TraceCheckUtils]: 132: Hoare triple {74762#false} assume !(1 == ~M_E~0); {74762#false} is VALID [2022-02-21 04:23:30,123 INFO L290 TraceCheckUtils]: 133: Hoare triple {74762#false} assume !(1 == ~T1_E~0); {74762#false} is VALID [2022-02-21 04:23:30,123 INFO L290 TraceCheckUtils]: 134: Hoare triple {74762#false} assume !(1 == ~T2_E~0); {74762#false} is VALID [2022-02-21 04:23:30,123 INFO L290 TraceCheckUtils]: 135: Hoare triple {74762#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {74762#false} is VALID [2022-02-21 04:23:30,123 INFO L290 TraceCheckUtils]: 136: Hoare triple {74762#false} assume !(1 == ~T4_E~0); {74762#false} is VALID [2022-02-21 04:23:30,123 INFO L290 TraceCheckUtils]: 137: Hoare triple {74762#false} assume !(1 == ~T5_E~0); {74762#false} is VALID [2022-02-21 04:23:30,123 INFO L290 TraceCheckUtils]: 138: Hoare triple {74762#false} assume !(1 == ~T6_E~0); {74762#false} is VALID [2022-02-21 04:23:30,123 INFO L290 TraceCheckUtils]: 139: Hoare triple {74762#false} assume !(1 == ~T7_E~0); {74762#false} is VALID [2022-02-21 04:23:30,123 INFO L290 TraceCheckUtils]: 140: Hoare triple {74762#false} assume !(1 == ~T8_E~0); {74762#false} is VALID [2022-02-21 04:23:30,123 INFO L290 TraceCheckUtils]: 141: Hoare triple {74762#false} assume !(1 == ~T9_E~0); {74762#false} is VALID [2022-02-21 04:23:30,124 INFO L290 TraceCheckUtils]: 142: Hoare triple {74762#false} assume !(1 == ~T10_E~0); {74762#false} is VALID [2022-02-21 04:23:30,124 INFO L290 TraceCheckUtils]: 143: Hoare triple {74762#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {74762#false} is VALID [2022-02-21 04:23:30,124 INFO L290 TraceCheckUtils]: 144: Hoare triple {74762#false} assume !(1 == ~T12_E~0); {74762#false} is VALID [2022-02-21 04:23:30,124 INFO L290 TraceCheckUtils]: 145: Hoare triple {74762#false} assume !(1 == ~T13_E~0); {74762#false} is VALID [2022-02-21 04:23:30,124 INFO L290 TraceCheckUtils]: 146: Hoare triple {74762#false} assume !(1 == ~E_M~0); {74762#false} is VALID [2022-02-21 04:23:30,124 INFO L290 TraceCheckUtils]: 147: Hoare triple {74762#false} assume !(1 == ~E_1~0); {74762#false} is VALID [2022-02-21 04:23:30,124 INFO L290 TraceCheckUtils]: 148: Hoare triple {74762#false} assume !(1 == ~E_2~0); {74762#false} is VALID [2022-02-21 04:23:30,124 INFO L290 TraceCheckUtils]: 149: Hoare triple {74762#false} assume !(1 == ~E_3~0); {74762#false} is VALID [2022-02-21 04:23:30,124 INFO L290 TraceCheckUtils]: 150: Hoare triple {74762#false} assume !(1 == ~E_4~0); {74762#false} is VALID [2022-02-21 04:23:30,125 INFO L290 TraceCheckUtils]: 151: Hoare triple {74762#false} assume 1 == ~E_5~0;~E_5~0 := 2; {74762#false} is VALID [2022-02-21 04:23:30,125 INFO L290 TraceCheckUtils]: 152: Hoare triple {74762#false} assume !(1 == ~E_6~0); {74762#false} is VALID [2022-02-21 04:23:30,125 INFO L290 TraceCheckUtils]: 153: Hoare triple {74762#false} assume !(1 == ~E_7~0); {74762#false} is VALID [2022-02-21 04:23:30,125 INFO L290 TraceCheckUtils]: 154: Hoare triple {74762#false} assume !(1 == ~E_8~0); {74762#false} is VALID [2022-02-21 04:23:30,125 INFO L290 TraceCheckUtils]: 155: Hoare triple {74762#false} assume !(1 == ~E_9~0); {74762#false} is VALID [2022-02-21 04:23:30,125 INFO L290 TraceCheckUtils]: 156: Hoare triple {74762#false} assume !(1 == ~E_10~0); {74762#false} is VALID [2022-02-21 04:23:30,125 INFO L290 TraceCheckUtils]: 157: Hoare triple {74762#false} assume !(1 == ~E_11~0); {74762#false} is VALID [2022-02-21 04:23:30,125 INFO L290 TraceCheckUtils]: 158: Hoare triple {74762#false} assume !(1 == ~E_12~0); {74762#false} is VALID [2022-02-21 04:23:30,125 INFO L290 TraceCheckUtils]: 159: Hoare triple {74762#false} assume 1 == ~E_13~0;~E_13~0 := 2; {74762#false} is VALID [2022-02-21 04:23:30,126 INFO L290 TraceCheckUtils]: 160: Hoare triple {74762#false} assume { :end_inline_reset_delta_events } true; {74762#false} is VALID [2022-02-21 04:23:30,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:30,126 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:30,126 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1006424984] [2022-02-21 04:23:30,126 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1006424984] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:30,126 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:30,127 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:30,127 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374672853] [2022-02-21 04:23:30,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:30,128 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:30,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:30,128 INFO L85 PathProgramCache]: Analyzing trace with hash -1640420756, now seen corresponding path program 1 times [2022-02-21 04:23:30,129 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:30,129 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167978997] [2022-02-21 04:23:30,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:30,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:30,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:30,153 INFO L290 TraceCheckUtils]: 0: Hoare triple {74764#true} assume !false; {74764#true} is VALID [2022-02-21 04:23:30,153 INFO L290 TraceCheckUtils]: 1: Hoare triple {74764#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {74764#true} is VALID [2022-02-21 04:23:30,153 INFO L290 TraceCheckUtils]: 2: Hoare triple {74764#true} assume !false; {74764#true} is VALID [2022-02-21 04:23:30,154 INFO L290 TraceCheckUtils]: 3: Hoare triple {74764#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {74764#true} is VALID [2022-02-21 04:23:30,154 INFO L290 TraceCheckUtils]: 4: Hoare triple {74764#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {74764#true} is VALID [2022-02-21 04:23:30,154 INFO L290 TraceCheckUtils]: 5: Hoare triple {74764#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {74764#true} is VALID [2022-02-21 04:23:30,154 INFO L290 TraceCheckUtils]: 6: Hoare triple {74764#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {74764#true} is VALID [2022-02-21 04:23:30,154 INFO L290 TraceCheckUtils]: 7: Hoare triple {74764#true} assume !(0 != eval_~tmp~0#1); {74764#true} is VALID [2022-02-21 04:23:30,154 INFO L290 TraceCheckUtils]: 8: Hoare triple {74764#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {74764#true} is VALID [2022-02-21 04:23:30,154 INFO L290 TraceCheckUtils]: 9: Hoare triple {74764#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {74764#true} is VALID [2022-02-21 04:23:30,154 INFO L290 TraceCheckUtils]: 10: Hoare triple {74764#true} assume 0 == ~M_E~0;~M_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,155 INFO L290 TraceCheckUtils]: 11: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,155 INFO L290 TraceCheckUtils]: 12: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,155 INFO L290 TraceCheckUtils]: 13: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,156 INFO L290 TraceCheckUtils]: 14: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,156 INFO L290 TraceCheckUtils]: 15: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,156 INFO L290 TraceCheckUtils]: 16: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,156 INFO L290 TraceCheckUtils]: 17: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,157 INFO L290 TraceCheckUtils]: 18: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,157 INFO L290 TraceCheckUtils]: 19: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,157 INFO L290 TraceCheckUtils]: 20: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,157 INFO L290 TraceCheckUtils]: 21: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,158 INFO L290 TraceCheckUtils]: 22: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,158 INFO L290 TraceCheckUtils]: 23: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,158 INFO L290 TraceCheckUtils]: 24: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,158 INFO L290 TraceCheckUtils]: 25: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,159 INFO L290 TraceCheckUtils]: 26: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,159 INFO L290 TraceCheckUtils]: 27: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,159 INFO L290 TraceCheckUtils]: 28: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,160 INFO L290 TraceCheckUtils]: 29: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,160 INFO L290 TraceCheckUtils]: 30: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,160 INFO L290 TraceCheckUtils]: 31: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,160 INFO L290 TraceCheckUtils]: 32: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,161 INFO L290 TraceCheckUtils]: 33: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,161 INFO L290 TraceCheckUtils]: 34: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,161 INFO L290 TraceCheckUtils]: 35: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,161 INFO L290 TraceCheckUtils]: 36: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,162 INFO L290 TraceCheckUtils]: 37: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,162 INFO L290 TraceCheckUtils]: 38: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,162 INFO L290 TraceCheckUtils]: 39: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,162 INFO L290 TraceCheckUtils]: 40: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,163 INFO L290 TraceCheckUtils]: 41: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,163 INFO L290 TraceCheckUtils]: 42: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,163 INFO L290 TraceCheckUtils]: 43: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,164 INFO L290 TraceCheckUtils]: 44: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,164 INFO L290 TraceCheckUtils]: 45: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,164 INFO L290 TraceCheckUtils]: 46: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,164 INFO L290 TraceCheckUtils]: 47: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,165 INFO L290 TraceCheckUtils]: 48: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,165 INFO L290 TraceCheckUtils]: 49: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,165 INFO L290 TraceCheckUtils]: 50: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,165 INFO L290 TraceCheckUtils]: 51: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,166 INFO L290 TraceCheckUtils]: 52: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,166 INFO L290 TraceCheckUtils]: 53: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,166 INFO L290 TraceCheckUtils]: 54: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,166 INFO L290 TraceCheckUtils]: 55: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,167 INFO L290 TraceCheckUtils]: 56: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,167 INFO L290 TraceCheckUtils]: 57: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,167 INFO L290 TraceCheckUtils]: 58: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,168 INFO L290 TraceCheckUtils]: 59: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,168 INFO L290 TraceCheckUtils]: 60: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,168 INFO L290 TraceCheckUtils]: 61: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,168 INFO L290 TraceCheckUtils]: 62: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,169 INFO L290 TraceCheckUtils]: 63: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,169 INFO L290 TraceCheckUtils]: 64: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,169 INFO L290 TraceCheckUtils]: 65: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,169 INFO L290 TraceCheckUtils]: 66: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,170 INFO L290 TraceCheckUtils]: 67: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,170 INFO L290 TraceCheckUtils]: 68: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,170 INFO L290 TraceCheckUtils]: 69: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,170 INFO L290 TraceCheckUtils]: 70: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,171 INFO L290 TraceCheckUtils]: 71: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,171 INFO L290 TraceCheckUtils]: 72: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,171 INFO L290 TraceCheckUtils]: 73: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,171 INFO L290 TraceCheckUtils]: 74: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,172 INFO L290 TraceCheckUtils]: 75: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,172 INFO L290 TraceCheckUtils]: 76: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,172 INFO L290 TraceCheckUtils]: 77: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,173 INFO L290 TraceCheckUtils]: 78: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,173 INFO L290 TraceCheckUtils]: 79: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,173 INFO L290 TraceCheckUtils]: 80: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,173 INFO L290 TraceCheckUtils]: 81: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,174 INFO L290 TraceCheckUtils]: 82: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,174 INFO L290 TraceCheckUtils]: 83: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,174 INFO L290 TraceCheckUtils]: 84: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,174 INFO L290 TraceCheckUtils]: 85: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,175 INFO L290 TraceCheckUtils]: 86: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,175 INFO L290 TraceCheckUtils]: 87: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,175 INFO L290 TraceCheckUtils]: 88: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,175 INFO L290 TraceCheckUtils]: 89: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,176 INFO L290 TraceCheckUtils]: 90: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,176 INFO L290 TraceCheckUtils]: 91: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,176 INFO L290 TraceCheckUtils]: 92: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,176 INFO L290 TraceCheckUtils]: 93: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,177 INFO L290 TraceCheckUtils]: 94: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,177 INFO L290 TraceCheckUtils]: 95: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,177 INFO L290 TraceCheckUtils]: 96: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,178 INFO L290 TraceCheckUtils]: 97: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,178 INFO L290 TraceCheckUtils]: 98: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,178 INFO L290 TraceCheckUtils]: 99: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,178 INFO L290 TraceCheckUtils]: 100: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,179 INFO L290 TraceCheckUtils]: 101: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,179 INFO L290 TraceCheckUtils]: 102: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,179 INFO L290 TraceCheckUtils]: 103: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,179 INFO L290 TraceCheckUtils]: 104: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,180 INFO L290 TraceCheckUtils]: 105: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,180 INFO L290 TraceCheckUtils]: 106: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,180 INFO L290 TraceCheckUtils]: 107: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,180 INFO L290 TraceCheckUtils]: 108: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,181 INFO L290 TraceCheckUtils]: 109: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,181 INFO L290 TraceCheckUtils]: 110: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,181 INFO L290 TraceCheckUtils]: 111: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,181 INFO L290 TraceCheckUtils]: 112: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,182 INFO L290 TraceCheckUtils]: 113: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,182 INFO L290 TraceCheckUtils]: 114: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,182 INFO L290 TraceCheckUtils]: 115: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,183 INFO L290 TraceCheckUtils]: 116: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,183 INFO L290 TraceCheckUtils]: 117: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,183 INFO L290 TraceCheckUtils]: 118: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,183 INFO L290 TraceCheckUtils]: 119: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,184 INFO L290 TraceCheckUtils]: 120: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,184 INFO L290 TraceCheckUtils]: 121: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,184 INFO L290 TraceCheckUtils]: 122: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {74766#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:30,184 INFO L290 TraceCheckUtils]: 123: Hoare triple {74766#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {74765#false} is VALID [2022-02-21 04:23:30,184 INFO L290 TraceCheckUtils]: 124: Hoare triple {74765#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,185 INFO L290 TraceCheckUtils]: 125: Hoare triple {74765#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,185 INFO L290 TraceCheckUtils]: 126: Hoare triple {74765#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,185 INFO L290 TraceCheckUtils]: 127: Hoare triple {74765#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,185 INFO L290 TraceCheckUtils]: 128: Hoare triple {74765#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,185 INFO L290 TraceCheckUtils]: 129: Hoare triple {74765#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,185 INFO L290 TraceCheckUtils]: 130: Hoare triple {74765#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,185 INFO L290 TraceCheckUtils]: 131: Hoare triple {74765#false} assume !(1 == ~T8_E~0); {74765#false} is VALID [2022-02-21 04:23:30,185 INFO L290 TraceCheckUtils]: 132: Hoare triple {74765#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,185 INFO L290 TraceCheckUtils]: 133: Hoare triple {74765#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,185 INFO L290 TraceCheckUtils]: 134: Hoare triple {74765#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,186 INFO L290 TraceCheckUtils]: 135: Hoare triple {74765#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,186 INFO L290 TraceCheckUtils]: 136: Hoare triple {74765#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,186 INFO L290 TraceCheckUtils]: 137: Hoare triple {74765#false} assume 1 == ~E_M~0;~E_M~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,186 INFO L290 TraceCheckUtils]: 138: Hoare triple {74765#false} assume 1 == ~E_1~0;~E_1~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,186 INFO L290 TraceCheckUtils]: 139: Hoare triple {74765#false} assume !(1 == ~E_2~0); {74765#false} is VALID [2022-02-21 04:23:30,186 INFO L290 TraceCheckUtils]: 140: Hoare triple {74765#false} assume 1 == ~E_3~0;~E_3~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,186 INFO L290 TraceCheckUtils]: 141: Hoare triple {74765#false} assume 1 == ~E_4~0;~E_4~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,186 INFO L290 TraceCheckUtils]: 142: Hoare triple {74765#false} assume 1 == ~E_5~0;~E_5~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,186 INFO L290 TraceCheckUtils]: 143: Hoare triple {74765#false} assume 1 == ~E_6~0;~E_6~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,186 INFO L290 TraceCheckUtils]: 144: Hoare triple {74765#false} assume 1 == ~E_7~0;~E_7~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,187 INFO L290 TraceCheckUtils]: 145: Hoare triple {74765#false} assume 1 == ~E_8~0;~E_8~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,187 INFO L290 TraceCheckUtils]: 146: Hoare triple {74765#false} assume 1 == ~E_9~0;~E_9~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,187 INFO L290 TraceCheckUtils]: 147: Hoare triple {74765#false} assume !(1 == ~E_10~0); {74765#false} is VALID [2022-02-21 04:23:30,187 INFO L290 TraceCheckUtils]: 148: Hoare triple {74765#false} assume 1 == ~E_11~0;~E_11~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,187 INFO L290 TraceCheckUtils]: 149: Hoare triple {74765#false} assume 1 == ~E_12~0;~E_12~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,187 INFO L290 TraceCheckUtils]: 150: Hoare triple {74765#false} assume 1 == ~E_13~0;~E_13~0 := 2; {74765#false} is VALID [2022-02-21 04:23:30,187 INFO L290 TraceCheckUtils]: 151: Hoare triple {74765#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {74765#false} is VALID [2022-02-21 04:23:30,187 INFO L290 TraceCheckUtils]: 152: Hoare triple {74765#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {74765#false} is VALID [2022-02-21 04:23:30,187 INFO L290 TraceCheckUtils]: 153: Hoare triple {74765#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {74765#false} is VALID [2022-02-21 04:23:30,187 INFO L290 TraceCheckUtils]: 154: Hoare triple {74765#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {74765#false} is VALID [2022-02-21 04:23:30,188 INFO L290 TraceCheckUtils]: 155: Hoare triple {74765#false} assume !(0 == start_simulation_~tmp~3#1); {74765#false} is VALID [2022-02-21 04:23:30,188 INFO L290 TraceCheckUtils]: 156: Hoare triple {74765#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {74765#false} is VALID [2022-02-21 04:23:30,188 INFO L290 TraceCheckUtils]: 157: Hoare triple {74765#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {74765#false} is VALID [2022-02-21 04:23:30,188 INFO L290 TraceCheckUtils]: 158: Hoare triple {74765#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {74765#false} is VALID [2022-02-21 04:23:30,188 INFO L290 TraceCheckUtils]: 159: Hoare triple {74765#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {74765#false} is VALID [2022-02-21 04:23:30,188 INFO L290 TraceCheckUtils]: 160: Hoare triple {74765#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {74765#false} is VALID [2022-02-21 04:23:30,188 INFO L290 TraceCheckUtils]: 161: Hoare triple {74765#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {74765#false} is VALID [2022-02-21 04:23:30,188 INFO L290 TraceCheckUtils]: 162: Hoare triple {74765#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {74765#false} is VALID [2022-02-21 04:23:30,188 INFO L290 TraceCheckUtils]: 163: Hoare triple {74765#false} assume !(0 != start_simulation_~tmp___0~1#1); {74765#false} is VALID [2022-02-21 04:23:30,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:30,189 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:30,189 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [167978997] [2022-02-21 04:23:30,189 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [167978997] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:30,189 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:30,189 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:30,190 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319231073] [2022-02-21 04:23:30,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:30,190 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:30,190 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:30,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:30,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:30,191 INFO L87 Difference]: Start difference. First operand 2018 states and 2979 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:31,678 INFO L93 Difference]: Finished difference Result 2018 states and 2978 transitions. [2022-02-21 04:23:31,678 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:31,678 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,778 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:31,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2978 transitions. [2022-02-21 04:23:31,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:32,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2978 transitions. [2022-02-21 04:23:32,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:32,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:32,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2978 transitions. [2022-02-21 04:23:32,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:32,005 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2022-02-21 04:23:32,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2978 transitions. [2022-02-21 04:23:32,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:32,023 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:32,024 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2978 transitions. Second operand has 2018 states, 2018 states have (on average 1.4757185332011893) internal successors, (2978), 2017 states have internal predecessors, (2978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,026 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2978 transitions. Second operand has 2018 states, 2018 states have (on average 1.4757185332011893) internal successors, (2978), 2017 states have internal predecessors, (2978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,026 INFO L87 Difference]: Start difference. First operand 2018 states and 2978 transitions. Second operand has 2018 states, 2018 states have (on average 1.4757185332011893) internal successors, (2978), 2017 states have internal predecessors, (2978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:32,112 INFO L93 Difference]: Finished difference Result 2018 states and 2978 transitions. [2022-02-21 04:23:32,112 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2978 transitions. [2022-02-21 04:23:32,114 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:32,114 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:32,116 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.4757185332011893) internal successors, (2978), 2017 states have internal predecessors, (2978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2978 transitions. [2022-02-21 04:23:32,117 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.4757185332011893) internal successors, (2978), 2017 states have internal predecessors, (2978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2978 transitions. [2022-02-21 04:23:32,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:32,208 INFO L93 Difference]: Finished difference Result 2018 states and 2978 transitions. [2022-02-21 04:23:32,208 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2978 transitions. [2022-02-21 04:23:32,210 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:32,210 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:32,210 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:32,210 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:32,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4757185332011893) internal successors, (2978), 2017 states have internal predecessors, (2978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2978 transitions. [2022-02-21 04:23:32,303 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2022-02-21 04:23:32,303 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2022-02-21 04:23:32,303 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:23:32,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2978 transitions. [2022-02-21 04:23:32,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:32,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:32,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:32,307 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:32,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:32,308 INFO L791 eck$LassoCheckResult]: Stem: 77700#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 77701#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 78737#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 78192#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78193#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 77682#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77683#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77749#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77750#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78188#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78189#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77715#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77534#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77535#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77979#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77980#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 77855#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 77856#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 77505#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77506#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 78729#L1279-2 assume !(0 == ~T1_E~0); 77128#L1284-1 assume !(0 == ~T2_E~0); 77129#L1289-1 assume !(0 == ~T3_E~0); 77852#L1294-1 assume !(0 == ~T4_E~0); 77853#L1299-1 assume !(0 == ~T5_E~0); 77864#L1304-1 assume !(0 == ~T6_E~0); 78795#L1309-1 assume !(0 == ~T7_E~0); 78796#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 77058#L1319-1 assume !(0 == ~T9_E~0); 77059#L1324-1 assume !(0 == ~T10_E~0); 77231#L1329-1 assume !(0 == ~T11_E~0); 77232#L1334-1 assume !(0 == ~T12_E~0); 78636#L1339-1 assume !(0 == ~T13_E~0); 78717#L1344-1 assume !(0 == ~E_M~0); 78718#L1349-1 assume !(0 == ~E_1~0); 78039#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 78040#L1359-1 assume !(0 == ~E_3~0); 78469#L1364-1 assume !(0 == ~E_4~0); 77360#L1369-1 assume !(0 == ~E_5~0); 77361#L1374-1 assume !(0 == ~E_6~0); 78044#L1379-1 assume !(0 == ~E_7~0); 78045#L1384-1 assume !(0 == ~E_8~0); 78122#L1389-1 assume !(0 == ~E_9~0); 78655#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 78656#L1399-1 assume !(0 == ~E_11~0); 78759#L1404-1 assume !(0 == ~E_12~0); 77453#L1409-1 assume !(0 == ~E_13~0); 77454#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78751#L628 assume !(1 == ~m_pc~0); 77357#L628-2 is_master_triggered_~__retres1~0#1 := 0; 77356#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78120#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78121#L1591 assume !(0 != activate_threads_~tmp~1#1); 78764#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77908#L647 assume 1 == ~t1_pc~0; 77277#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77278#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77549#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77550#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 78704#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78705#L666 assume 1 == ~t2_pc~0; 77125#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 77126#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77292#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78721#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 78240#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78241#L685 assume !(1 == ~t3_pc~0); 78346#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 78345#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77968#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77969#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78090#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77576#L704 assume 1 == ~t4_pc~0; 77577#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78101#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78102#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78742#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 77961#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77962#L723 assume !(1 == ~t5_pc~0); 78084#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 78320#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78464#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78219#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 78220#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77342#L742 assume 1 == ~t6_pc~0; 77343#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77491#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77492#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77027#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 77028#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77419#L761 assume !(1 == ~t7_pc~0); 77420#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 77288#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77289#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78091#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 78092#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77052#L780 assume 1 == ~t8_pc~0; 77053#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77328#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77329#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78052#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 78053#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78172#L799 assume 1 == ~t9_pc~0; 78284#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77055#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77056#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78184#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 78391#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78202#L818 assume !(1 == ~t10_pc~0); 76836#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76837#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78277#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78206#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78207#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78247#L837 assume 1 == ~t11_pc~0; 78248#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 78082#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78485#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78165#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 78166#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77917#L856 assume !(1 == ~t12_pc~0); 77918#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 78571#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 78572#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 78552#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 78553#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78732#L875 assume 1 == ~t13_pc~0; 77862#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 77494#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 77495#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77434#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 77435#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78274#L1427 assume !(1 == ~M_E~0); 78258#L1427-2 assume !(1 == ~T1_E~0); 77406#L1432-1 assume !(1 == ~T2_E~0); 77407#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78475#L1442-1 assume !(1 == ~T4_E~0); 78476#L1447-1 assume !(1 == ~T5_E~0); 78331#L1452-1 assume !(1 == ~T6_E~0); 76971#L1457-1 assume !(1 == ~T7_E~0); 76972#L1462-1 assume !(1 == ~T8_E~0); 78502#L1467-1 assume !(1 == ~T9_E~0); 78520#L1472-1 assume !(1 == ~T10_E~0); 78521#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78272#L1482-1 assume !(1 == ~T12_E~0); 78273#L1487-1 assume !(1 == ~T13_E~0); 77302#L1492-1 assume !(1 == ~E_M~0); 77303#L1497-1 assume !(1 == ~E_1~0); 77664#L1502-1 assume !(1 == ~E_2~0); 77665#L1507-1 assume !(1 == ~E_3~0); 77180#L1512-1 assume !(1 == ~E_4~0); 77181#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 78591#L1522-1 assume !(1 == ~E_6~0); 77905#L1527-1 assume !(1 == ~E_7~0); 77906#L1532-1 assume !(1 == ~E_8~0); 78779#L1537-1 assume !(1 == ~E_9~0); 78108#L1542-1 assume !(1 == ~E_10~0); 77939#L1547-1 assume !(1 == ~E_11~0); 77940#L1552-1 assume !(1 == ~E_12~0); 76875#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 76876#L1562-1 assume { :end_inline_reset_delta_events } true; 77482#L1928-2 [2022-02-21 04:23:32,308 INFO L793 eck$LassoCheckResult]: Loop: 77482#L1928-2 assume !false; 77973#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77136#L1254 assume !false; 77723#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77210#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77211#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77408#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 78579#L1067 assume !(0 != eval_~tmp~0#1); 77649#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77226#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77227#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77686#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77668#L1284-3 assume !(0 == ~T2_E~0); 77669#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77647#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77648#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78035#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 78036#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 77545#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 77546#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78542#L1324-3 assume !(0 == ~T10_E~0); 77177#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 77178#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 77945#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 77946#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 78244#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77526#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 77527#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78255#L1364-3 assume !(0 == ~E_4~0); 78777#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78673#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77306#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 77307#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 77524#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 77525#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77815#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 78683#L1404-3 assume !(0 == ~E_12~0); 78647#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 78648#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78134#L628-45 assume !(1 == ~m_pc~0); 77813#L628-47 is_master_triggered_~__retres1~0#1 := 0; 77814#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77171#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77172#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77560#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78283#L647-45 assume 1 == ~t1_pc~0; 77122#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77123#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78051#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77236#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77237#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77448#L666-45 assume !(1 == ~t2_pc~0); 77449#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 77930#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78492#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78407#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78401#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76986#L685-45 assume 1 == ~t3_pc~0; 76987#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78046#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78720#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78589#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78590#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78730#L704-45 assume 1 == ~t4_pc~0; 78609#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76853#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77712#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78055#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78802#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78167#L723-45 assume 1 == ~t5_pc~0; 78169#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78657#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77759#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77536#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 77537#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78561#L742-45 assume 1 == ~t6_pc~0; 78562#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77784#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78253#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78289#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78290#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78378#L761-45 assume !(1 == ~t7_pc~0); 78379#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 77777#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77778#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77184#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 77185#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78651#L780-45 assume !(1 == ~t8_pc~0); 77563#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 77196#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77197#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78778#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77166#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77167#L799-45 assume 1 == ~t9_pc~0; 77943#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77388#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78703#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78332#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78333#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77104#L818-45 assume 1 == ~t10_pc~0; 77105#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 77223#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78306#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77710#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77711#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78426#L837-45 assume !(1 == ~t11_pc~0); 77641#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 77642#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77779#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78444#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 77242#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77243#L856-45 assume 1 == ~t12_pc~0; 78728#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 77245#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77186#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77187#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 78049#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78050#L875-45 assume 1 == ~t13_pc~0; 78020#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 78021#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78083#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 78695#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 78696#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78635#L1427-3 assume !(1 == ~M_E~0); 77846#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77847#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78385#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78037#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78038#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76894#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76895#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78577#L1462-3 assume !(1 == ~T8_E~0); 78578#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78441#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78442#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77145#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 77146#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 77287#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77460#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77461#L1502-3 assume !(1 == ~E_2~0); 78409#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78540#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77498#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77190#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77191#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77155#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77156#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78256#L1542-3 assume !(1 == ~E_10~0); 78394#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78023#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78024#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 77366#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77367#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76786#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77551#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 77552#L1947 assume !(0 == start_simulation_~tmp~3#1); 78157#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 78362#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77423#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 78755#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 78679#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78509#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78268#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 78269#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 77482#L1928-2 [2022-02-21 04:23:32,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:32,309 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2022-02-21 04:23:32,309 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:32,309 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673018831] [2022-02-21 04:23:32,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:32,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:32,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:32,337 INFO L290 TraceCheckUtils]: 0: Hoare triple {82842#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {82842#true} is VALID [2022-02-21 04:23:32,338 INFO L290 TraceCheckUtils]: 1: Hoare triple {82842#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,338 INFO L290 TraceCheckUtils]: 2: Hoare triple {82844#(= ~t11_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,338 INFO L290 TraceCheckUtils]: 3: Hoare triple {82844#(= ~t11_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,339 INFO L290 TraceCheckUtils]: 4: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,339 INFO L290 TraceCheckUtils]: 5: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,339 INFO L290 TraceCheckUtils]: 6: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,339 INFO L290 TraceCheckUtils]: 7: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,340 INFO L290 TraceCheckUtils]: 8: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,340 INFO L290 TraceCheckUtils]: 9: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,340 INFO L290 TraceCheckUtils]: 10: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,340 INFO L290 TraceCheckUtils]: 11: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,341 INFO L290 TraceCheckUtils]: 12: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,341 INFO L290 TraceCheckUtils]: 13: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,341 INFO L290 TraceCheckUtils]: 14: Hoare triple {82844#(= ~t11_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {82844#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 15: Hoare triple {82844#(= ~t11_i~0 1)} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {82843#false} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 16: Hoare triple {82843#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {82843#false} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 17: Hoare triple {82843#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {82843#false} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 18: Hoare triple {82843#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {82843#false} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 19: Hoare triple {82843#false} assume 0 == ~M_E~0;~M_E~0 := 1; {82843#false} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 20: Hoare triple {82843#false} assume !(0 == ~T1_E~0); {82843#false} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 21: Hoare triple {82843#false} assume !(0 == ~T2_E~0); {82843#false} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 22: Hoare triple {82843#false} assume !(0 == ~T3_E~0); {82843#false} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 23: Hoare triple {82843#false} assume !(0 == ~T4_E~0); {82843#false} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 24: Hoare triple {82843#false} assume !(0 == ~T5_E~0); {82843#false} is VALID [2022-02-21 04:23:32,342 INFO L290 TraceCheckUtils]: 25: Hoare triple {82843#false} assume !(0 == ~T6_E~0); {82843#false} is VALID [2022-02-21 04:23:32,343 INFO L290 TraceCheckUtils]: 26: Hoare triple {82843#false} assume !(0 == ~T7_E~0); {82843#false} is VALID [2022-02-21 04:23:32,343 INFO L290 TraceCheckUtils]: 27: Hoare triple {82843#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {82843#false} is VALID [2022-02-21 04:23:32,343 INFO L290 TraceCheckUtils]: 28: Hoare triple {82843#false} assume !(0 == ~T9_E~0); {82843#false} is VALID [2022-02-21 04:23:32,343 INFO L290 TraceCheckUtils]: 29: Hoare triple {82843#false} assume !(0 == ~T10_E~0); {82843#false} is VALID [2022-02-21 04:23:32,343 INFO L290 TraceCheckUtils]: 30: Hoare triple {82843#false} assume !(0 == ~T11_E~0); {82843#false} is VALID [2022-02-21 04:23:32,349 INFO L290 TraceCheckUtils]: 31: Hoare triple {82843#false} assume !(0 == ~T12_E~0); {82843#false} is VALID [2022-02-21 04:23:32,349 INFO L290 TraceCheckUtils]: 32: Hoare triple {82843#false} assume !(0 == ~T13_E~0); {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 33: Hoare triple {82843#false} assume !(0 == ~E_M~0); {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 34: Hoare triple {82843#false} assume !(0 == ~E_1~0); {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 35: Hoare triple {82843#false} assume 0 == ~E_2~0;~E_2~0 := 1; {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 36: Hoare triple {82843#false} assume !(0 == ~E_3~0); {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 37: Hoare triple {82843#false} assume !(0 == ~E_4~0); {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 38: Hoare triple {82843#false} assume !(0 == ~E_5~0); {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 39: Hoare triple {82843#false} assume !(0 == ~E_6~0); {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 40: Hoare triple {82843#false} assume !(0 == ~E_7~0); {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 41: Hoare triple {82843#false} assume !(0 == ~E_8~0); {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 42: Hoare triple {82843#false} assume !(0 == ~E_9~0); {82843#false} is VALID [2022-02-21 04:23:32,350 INFO L290 TraceCheckUtils]: 43: Hoare triple {82843#false} assume 0 == ~E_10~0;~E_10~0 := 1; {82843#false} is VALID [2022-02-21 04:23:32,351 INFO L290 TraceCheckUtils]: 44: Hoare triple {82843#false} assume !(0 == ~E_11~0); {82843#false} is VALID [2022-02-21 04:23:32,351 INFO L290 TraceCheckUtils]: 45: Hoare triple {82843#false} assume !(0 == ~E_12~0); {82843#false} is VALID [2022-02-21 04:23:32,351 INFO L290 TraceCheckUtils]: 46: Hoare triple {82843#false} assume !(0 == ~E_13~0); {82843#false} is VALID [2022-02-21 04:23:32,351 INFO L290 TraceCheckUtils]: 47: Hoare triple {82843#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {82843#false} is VALID [2022-02-21 04:23:32,351 INFO L290 TraceCheckUtils]: 48: Hoare triple {82843#false} assume !(1 == ~m_pc~0); {82843#false} is VALID [2022-02-21 04:23:32,351 INFO L290 TraceCheckUtils]: 49: Hoare triple {82843#false} is_master_triggered_~__retres1~0#1 := 0; {82843#false} is VALID [2022-02-21 04:23:32,351 INFO L290 TraceCheckUtils]: 50: Hoare triple {82843#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {82843#false} is VALID [2022-02-21 04:23:32,351 INFO L290 TraceCheckUtils]: 51: Hoare triple {82843#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {82843#false} is VALID [2022-02-21 04:23:32,351 INFO L290 TraceCheckUtils]: 52: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp~1#1); {82843#false} is VALID [2022-02-21 04:23:32,351 INFO L290 TraceCheckUtils]: 53: Hoare triple {82843#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {82843#false} is VALID [2022-02-21 04:23:32,352 INFO L290 TraceCheckUtils]: 54: Hoare triple {82843#false} assume 1 == ~t1_pc~0; {82843#false} is VALID [2022-02-21 04:23:32,352 INFO L290 TraceCheckUtils]: 55: Hoare triple {82843#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {82843#false} is VALID [2022-02-21 04:23:32,352 INFO L290 TraceCheckUtils]: 56: Hoare triple {82843#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {82843#false} is VALID [2022-02-21 04:23:32,352 INFO L290 TraceCheckUtils]: 57: Hoare triple {82843#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {82843#false} is VALID [2022-02-21 04:23:32,352 INFO L290 TraceCheckUtils]: 58: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___0~0#1); {82843#false} is VALID [2022-02-21 04:23:32,352 INFO L290 TraceCheckUtils]: 59: Hoare triple {82843#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {82843#false} is VALID [2022-02-21 04:23:32,352 INFO L290 TraceCheckUtils]: 60: Hoare triple {82843#false} assume 1 == ~t2_pc~0; {82843#false} is VALID [2022-02-21 04:23:32,352 INFO L290 TraceCheckUtils]: 61: Hoare triple {82843#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {82843#false} is VALID [2022-02-21 04:23:32,352 INFO L290 TraceCheckUtils]: 62: Hoare triple {82843#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {82843#false} is VALID [2022-02-21 04:23:32,352 INFO L290 TraceCheckUtils]: 63: Hoare triple {82843#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 64: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___1~0#1); {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 65: Hoare triple {82843#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 66: Hoare triple {82843#false} assume !(1 == ~t3_pc~0); {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 67: Hoare triple {82843#false} is_transmit3_triggered_~__retres1~3#1 := 0; {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 68: Hoare triple {82843#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 69: Hoare triple {82843#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 70: Hoare triple {82843#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 71: Hoare triple {82843#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 72: Hoare triple {82843#false} assume 1 == ~t4_pc~0; {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 73: Hoare triple {82843#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {82843#false} is VALID [2022-02-21 04:23:32,353 INFO L290 TraceCheckUtils]: 74: Hoare triple {82843#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {82843#false} is VALID [2022-02-21 04:23:32,354 INFO L290 TraceCheckUtils]: 75: Hoare triple {82843#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {82843#false} is VALID [2022-02-21 04:23:32,354 INFO L290 TraceCheckUtils]: 76: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___3~0#1); {82843#false} is VALID [2022-02-21 04:23:32,354 INFO L290 TraceCheckUtils]: 77: Hoare triple {82843#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {82843#false} is VALID [2022-02-21 04:23:32,354 INFO L290 TraceCheckUtils]: 78: Hoare triple {82843#false} assume !(1 == ~t5_pc~0); {82843#false} is VALID [2022-02-21 04:23:32,354 INFO L290 TraceCheckUtils]: 79: Hoare triple {82843#false} is_transmit5_triggered_~__retres1~5#1 := 0; {82843#false} is VALID [2022-02-21 04:23:32,354 INFO L290 TraceCheckUtils]: 80: Hoare triple {82843#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {82843#false} is VALID [2022-02-21 04:23:32,354 INFO L290 TraceCheckUtils]: 81: Hoare triple {82843#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {82843#false} is VALID [2022-02-21 04:23:32,354 INFO L290 TraceCheckUtils]: 82: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___4~0#1); {82843#false} is VALID [2022-02-21 04:23:32,354 INFO L290 TraceCheckUtils]: 83: Hoare triple {82843#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {82843#false} is VALID [2022-02-21 04:23:32,354 INFO L290 TraceCheckUtils]: 84: Hoare triple {82843#false} assume 1 == ~t6_pc~0; {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 85: Hoare triple {82843#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 86: Hoare triple {82843#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 87: Hoare triple {82843#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 88: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___5~0#1); {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 89: Hoare triple {82843#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 90: Hoare triple {82843#false} assume !(1 == ~t7_pc~0); {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 91: Hoare triple {82843#false} is_transmit7_triggered_~__retres1~7#1 := 0; {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 92: Hoare triple {82843#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 93: Hoare triple {82843#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 94: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___6~0#1); {82843#false} is VALID [2022-02-21 04:23:32,355 INFO L290 TraceCheckUtils]: 95: Hoare triple {82843#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {82843#false} is VALID [2022-02-21 04:23:32,356 INFO L290 TraceCheckUtils]: 96: Hoare triple {82843#false} assume 1 == ~t8_pc~0; {82843#false} is VALID [2022-02-21 04:23:32,356 INFO L290 TraceCheckUtils]: 97: Hoare triple {82843#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {82843#false} is VALID [2022-02-21 04:23:32,356 INFO L290 TraceCheckUtils]: 98: Hoare triple {82843#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {82843#false} is VALID [2022-02-21 04:23:32,356 INFO L290 TraceCheckUtils]: 99: Hoare triple {82843#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {82843#false} is VALID [2022-02-21 04:23:32,356 INFO L290 TraceCheckUtils]: 100: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___7~0#1); {82843#false} is VALID [2022-02-21 04:23:32,356 INFO L290 TraceCheckUtils]: 101: Hoare triple {82843#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {82843#false} is VALID [2022-02-21 04:23:32,356 INFO L290 TraceCheckUtils]: 102: Hoare triple {82843#false} assume 1 == ~t9_pc~0; {82843#false} is VALID [2022-02-21 04:23:32,356 INFO L290 TraceCheckUtils]: 103: Hoare triple {82843#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {82843#false} is VALID [2022-02-21 04:23:32,356 INFO L290 TraceCheckUtils]: 104: Hoare triple {82843#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {82843#false} is VALID [2022-02-21 04:23:32,356 INFO L290 TraceCheckUtils]: 105: Hoare triple {82843#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {82843#false} is VALID [2022-02-21 04:23:32,357 INFO L290 TraceCheckUtils]: 106: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___8~0#1); {82843#false} is VALID [2022-02-21 04:23:32,357 INFO L290 TraceCheckUtils]: 107: Hoare triple {82843#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {82843#false} is VALID [2022-02-21 04:23:32,357 INFO L290 TraceCheckUtils]: 108: Hoare triple {82843#false} assume !(1 == ~t10_pc~0); {82843#false} is VALID [2022-02-21 04:23:32,357 INFO L290 TraceCheckUtils]: 109: Hoare triple {82843#false} is_transmit10_triggered_~__retres1~10#1 := 0; {82843#false} is VALID [2022-02-21 04:23:32,357 INFO L290 TraceCheckUtils]: 110: Hoare triple {82843#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {82843#false} is VALID [2022-02-21 04:23:32,357 INFO L290 TraceCheckUtils]: 111: Hoare triple {82843#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {82843#false} is VALID [2022-02-21 04:23:32,357 INFO L290 TraceCheckUtils]: 112: Hoare triple {82843#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {82843#false} is VALID [2022-02-21 04:23:32,357 INFO L290 TraceCheckUtils]: 113: Hoare triple {82843#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {82843#false} is VALID [2022-02-21 04:23:32,357 INFO L290 TraceCheckUtils]: 114: Hoare triple {82843#false} assume 1 == ~t11_pc~0; {82843#false} is VALID [2022-02-21 04:23:32,357 INFO L290 TraceCheckUtils]: 115: Hoare triple {82843#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 116: Hoare triple {82843#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 117: Hoare triple {82843#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 118: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___10~0#1); {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 119: Hoare triple {82843#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 120: Hoare triple {82843#false} assume !(1 == ~t12_pc~0); {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 121: Hoare triple {82843#false} is_transmit12_triggered_~__retres1~12#1 := 0; {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 122: Hoare triple {82843#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 123: Hoare triple {82843#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 124: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___11~0#1); {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 125: Hoare triple {82843#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {82843#false} is VALID [2022-02-21 04:23:32,358 INFO L290 TraceCheckUtils]: 126: Hoare triple {82843#false} assume 1 == ~t13_pc~0; {82843#false} is VALID [2022-02-21 04:23:32,359 INFO L290 TraceCheckUtils]: 127: Hoare triple {82843#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {82843#false} is VALID [2022-02-21 04:23:32,359 INFO L290 TraceCheckUtils]: 128: Hoare triple {82843#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {82843#false} is VALID [2022-02-21 04:23:32,359 INFO L290 TraceCheckUtils]: 129: Hoare triple {82843#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {82843#false} is VALID [2022-02-21 04:23:32,359 INFO L290 TraceCheckUtils]: 130: Hoare triple {82843#false} assume !(0 != activate_threads_~tmp___12~0#1); {82843#false} is VALID [2022-02-21 04:23:32,359 INFO L290 TraceCheckUtils]: 131: Hoare triple {82843#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {82843#false} is VALID [2022-02-21 04:23:32,359 INFO L290 TraceCheckUtils]: 132: Hoare triple {82843#false} assume !(1 == ~M_E~0); {82843#false} is VALID [2022-02-21 04:23:32,359 INFO L290 TraceCheckUtils]: 133: Hoare triple {82843#false} assume !(1 == ~T1_E~0); {82843#false} is VALID [2022-02-21 04:23:32,359 INFO L290 TraceCheckUtils]: 134: Hoare triple {82843#false} assume !(1 == ~T2_E~0); {82843#false} is VALID [2022-02-21 04:23:32,359 INFO L290 TraceCheckUtils]: 135: Hoare triple {82843#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {82843#false} is VALID [2022-02-21 04:23:32,359 INFO L290 TraceCheckUtils]: 136: Hoare triple {82843#false} assume !(1 == ~T4_E~0); {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 137: Hoare triple {82843#false} assume !(1 == ~T5_E~0); {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 138: Hoare triple {82843#false} assume !(1 == ~T6_E~0); {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 139: Hoare triple {82843#false} assume !(1 == ~T7_E~0); {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 140: Hoare triple {82843#false} assume !(1 == ~T8_E~0); {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 141: Hoare triple {82843#false} assume !(1 == ~T9_E~0); {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 142: Hoare triple {82843#false} assume !(1 == ~T10_E~0); {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 143: Hoare triple {82843#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 144: Hoare triple {82843#false} assume !(1 == ~T12_E~0); {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 145: Hoare triple {82843#false} assume !(1 == ~T13_E~0); {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 146: Hoare triple {82843#false} assume !(1 == ~E_M~0); {82843#false} is VALID [2022-02-21 04:23:32,360 INFO L290 TraceCheckUtils]: 147: Hoare triple {82843#false} assume !(1 == ~E_1~0); {82843#false} is VALID [2022-02-21 04:23:32,361 INFO L290 TraceCheckUtils]: 148: Hoare triple {82843#false} assume !(1 == ~E_2~0); {82843#false} is VALID [2022-02-21 04:23:32,361 INFO L290 TraceCheckUtils]: 149: Hoare triple {82843#false} assume !(1 == ~E_3~0); {82843#false} is VALID [2022-02-21 04:23:32,361 INFO L290 TraceCheckUtils]: 150: Hoare triple {82843#false} assume !(1 == ~E_4~0); {82843#false} is VALID [2022-02-21 04:23:32,361 INFO L290 TraceCheckUtils]: 151: Hoare triple {82843#false} assume 1 == ~E_5~0;~E_5~0 := 2; {82843#false} is VALID [2022-02-21 04:23:32,361 INFO L290 TraceCheckUtils]: 152: Hoare triple {82843#false} assume !(1 == ~E_6~0); {82843#false} is VALID [2022-02-21 04:23:32,362 INFO L290 TraceCheckUtils]: 153: Hoare triple {82843#false} assume !(1 == ~E_7~0); {82843#false} is VALID [2022-02-21 04:23:32,362 INFO L290 TraceCheckUtils]: 154: Hoare triple {82843#false} assume !(1 == ~E_8~0); {82843#false} is VALID [2022-02-21 04:23:32,362 INFO L290 TraceCheckUtils]: 155: Hoare triple {82843#false} assume !(1 == ~E_9~0); {82843#false} is VALID [2022-02-21 04:23:32,362 INFO L290 TraceCheckUtils]: 156: Hoare triple {82843#false} assume !(1 == ~E_10~0); {82843#false} is VALID [2022-02-21 04:23:32,362 INFO L290 TraceCheckUtils]: 157: Hoare triple {82843#false} assume !(1 == ~E_11~0); {82843#false} is VALID [2022-02-21 04:23:32,362 INFO L290 TraceCheckUtils]: 158: Hoare triple {82843#false} assume !(1 == ~E_12~0); {82843#false} is VALID [2022-02-21 04:23:32,362 INFO L290 TraceCheckUtils]: 159: Hoare triple {82843#false} assume 1 == ~E_13~0;~E_13~0 := 2; {82843#false} is VALID [2022-02-21 04:23:32,362 INFO L290 TraceCheckUtils]: 160: Hoare triple {82843#false} assume { :end_inline_reset_delta_events } true; {82843#false} is VALID [2022-02-21 04:23:32,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:32,363 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:32,363 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673018831] [2022-02-21 04:23:32,363 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673018831] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:32,363 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:32,363 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:32,363 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [165965151] [2022-02-21 04:23:32,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:32,364 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:32,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:32,364 INFO L85 PathProgramCache]: Analyzing trace with hash 1322591597, now seen corresponding path program 1 times [2022-02-21 04:23:32,364 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:32,364 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130645543] [2022-02-21 04:23:32,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:32,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:32,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:32,405 INFO L290 TraceCheckUtils]: 0: Hoare triple {82845#true} assume !false; {82845#true} is VALID [2022-02-21 04:23:32,406 INFO L290 TraceCheckUtils]: 1: Hoare triple {82845#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {82845#true} is VALID [2022-02-21 04:23:32,406 INFO L290 TraceCheckUtils]: 2: Hoare triple {82845#true} assume !false; {82845#true} is VALID [2022-02-21 04:23:32,406 INFO L290 TraceCheckUtils]: 3: Hoare triple {82845#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {82845#true} is VALID [2022-02-21 04:23:32,406 INFO L290 TraceCheckUtils]: 4: Hoare triple {82845#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {82845#true} is VALID [2022-02-21 04:23:32,406 INFO L290 TraceCheckUtils]: 5: Hoare triple {82845#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {82845#true} is VALID [2022-02-21 04:23:32,406 INFO L290 TraceCheckUtils]: 6: Hoare triple {82845#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {82845#true} is VALID [2022-02-21 04:23:32,406 INFO L290 TraceCheckUtils]: 7: Hoare triple {82845#true} assume !(0 != eval_~tmp~0#1); {82845#true} is VALID [2022-02-21 04:23:32,406 INFO L290 TraceCheckUtils]: 8: Hoare triple {82845#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {82845#true} is VALID [2022-02-21 04:23:32,407 INFO L290 TraceCheckUtils]: 9: Hoare triple {82845#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {82845#true} is VALID [2022-02-21 04:23:32,407 INFO L290 TraceCheckUtils]: 10: Hoare triple {82845#true} assume 0 == ~M_E~0;~M_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,407 INFO L290 TraceCheckUtils]: 11: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,407 INFO L290 TraceCheckUtils]: 12: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,408 INFO L290 TraceCheckUtils]: 13: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,408 INFO L290 TraceCheckUtils]: 14: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,408 INFO L290 TraceCheckUtils]: 15: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,408 INFO L290 TraceCheckUtils]: 16: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,409 INFO L290 TraceCheckUtils]: 17: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,409 INFO L290 TraceCheckUtils]: 18: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,409 INFO L290 TraceCheckUtils]: 19: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,409 INFO L290 TraceCheckUtils]: 20: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,410 INFO L290 TraceCheckUtils]: 21: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,410 INFO L290 TraceCheckUtils]: 22: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,410 INFO L290 TraceCheckUtils]: 23: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,410 INFO L290 TraceCheckUtils]: 24: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,411 INFO L290 TraceCheckUtils]: 25: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,411 INFO L290 TraceCheckUtils]: 26: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,411 INFO L290 TraceCheckUtils]: 27: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,412 INFO L290 TraceCheckUtils]: 28: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,412 INFO L290 TraceCheckUtils]: 29: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,412 INFO L290 TraceCheckUtils]: 30: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,412 INFO L290 TraceCheckUtils]: 31: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,413 INFO L290 TraceCheckUtils]: 32: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,413 INFO L290 TraceCheckUtils]: 33: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,413 INFO L290 TraceCheckUtils]: 34: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,413 INFO L290 TraceCheckUtils]: 35: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,414 INFO L290 TraceCheckUtils]: 36: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,414 INFO L290 TraceCheckUtils]: 37: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,414 INFO L290 TraceCheckUtils]: 38: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,414 INFO L290 TraceCheckUtils]: 39: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,415 INFO L290 TraceCheckUtils]: 40: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,415 INFO L290 TraceCheckUtils]: 41: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,415 INFO L290 TraceCheckUtils]: 42: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,416 INFO L290 TraceCheckUtils]: 43: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,416 INFO L290 TraceCheckUtils]: 44: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,416 INFO L290 TraceCheckUtils]: 45: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,416 INFO L290 TraceCheckUtils]: 46: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,417 INFO L290 TraceCheckUtils]: 47: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,417 INFO L290 TraceCheckUtils]: 48: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,417 INFO L290 TraceCheckUtils]: 49: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,417 INFO L290 TraceCheckUtils]: 50: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,418 INFO L290 TraceCheckUtils]: 51: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,418 INFO L290 TraceCheckUtils]: 52: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,418 INFO L290 TraceCheckUtils]: 53: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,418 INFO L290 TraceCheckUtils]: 54: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,419 INFO L290 TraceCheckUtils]: 55: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,419 INFO L290 TraceCheckUtils]: 56: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,419 INFO L290 TraceCheckUtils]: 57: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,419 INFO L290 TraceCheckUtils]: 58: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,420 INFO L290 TraceCheckUtils]: 59: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,420 INFO L290 TraceCheckUtils]: 60: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,420 INFO L290 TraceCheckUtils]: 61: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,420 INFO L290 TraceCheckUtils]: 62: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,421 INFO L290 TraceCheckUtils]: 63: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,421 INFO L290 TraceCheckUtils]: 64: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,421 INFO L290 TraceCheckUtils]: 65: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,422 INFO L290 TraceCheckUtils]: 66: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,422 INFO L290 TraceCheckUtils]: 67: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,422 INFO L290 TraceCheckUtils]: 68: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,422 INFO L290 TraceCheckUtils]: 69: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,423 INFO L290 TraceCheckUtils]: 70: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,423 INFO L290 TraceCheckUtils]: 71: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,423 INFO L290 TraceCheckUtils]: 72: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,423 INFO L290 TraceCheckUtils]: 73: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,424 INFO L290 TraceCheckUtils]: 74: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,424 INFO L290 TraceCheckUtils]: 75: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,424 INFO L290 TraceCheckUtils]: 76: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,424 INFO L290 TraceCheckUtils]: 77: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,425 INFO L290 TraceCheckUtils]: 78: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,425 INFO L290 TraceCheckUtils]: 79: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,425 INFO L290 TraceCheckUtils]: 80: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,425 INFO L290 TraceCheckUtils]: 81: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,426 INFO L290 TraceCheckUtils]: 82: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,426 INFO L290 TraceCheckUtils]: 83: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,426 INFO L290 TraceCheckUtils]: 84: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,426 INFO L290 TraceCheckUtils]: 85: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,427 INFO L290 TraceCheckUtils]: 86: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,427 INFO L290 TraceCheckUtils]: 87: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,427 INFO L290 TraceCheckUtils]: 88: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,427 INFO L290 TraceCheckUtils]: 89: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,428 INFO L290 TraceCheckUtils]: 90: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,428 INFO L290 TraceCheckUtils]: 91: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,428 INFO L290 TraceCheckUtils]: 92: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,429 INFO L290 TraceCheckUtils]: 93: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,429 INFO L290 TraceCheckUtils]: 94: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,429 INFO L290 TraceCheckUtils]: 95: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,429 INFO L290 TraceCheckUtils]: 96: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,430 INFO L290 TraceCheckUtils]: 97: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,430 INFO L290 TraceCheckUtils]: 98: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,430 INFO L290 TraceCheckUtils]: 99: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,430 INFO L290 TraceCheckUtils]: 100: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,431 INFO L290 TraceCheckUtils]: 101: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,431 INFO L290 TraceCheckUtils]: 102: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,431 INFO L290 TraceCheckUtils]: 103: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,431 INFO L290 TraceCheckUtils]: 104: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,432 INFO L290 TraceCheckUtils]: 105: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,432 INFO L290 TraceCheckUtils]: 106: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,432 INFO L290 TraceCheckUtils]: 107: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,433 INFO L290 TraceCheckUtils]: 108: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,433 INFO L290 TraceCheckUtils]: 109: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,433 INFO L290 TraceCheckUtils]: 110: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,433 INFO L290 TraceCheckUtils]: 111: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,434 INFO L290 TraceCheckUtils]: 112: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,434 INFO L290 TraceCheckUtils]: 113: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,434 INFO L290 TraceCheckUtils]: 114: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,434 INFO L290 TraceCheckUtils]: 115: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,435 INFO L290 TraceCheckUtils]: 116: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,435 INFO L290 TraceCheckUtils]: 117: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,435 INFO L290 TraceCheckUtils]: 118: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,435 INFO L290 TraceCheckUtils]: 119: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,436 INFO L290 TraceCheckUtils]: 120: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,436 INFO L290 TraceCheckUtils]: 121: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,436 INFO L290 TraceCheckUtils]: 122: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {82847#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:32,436 INFO L290 TraceCheckUtils]: 123: Hoare triple {82847#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {82846#false} is VALID [2022-02-21 04:23:32,437 INFO L290 TraceCheckUtils]: 124: Hoare triple {82846#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,437 INFO L290 TraceCheckUtils]: 125: Hoare triple {82846#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,437 INFO L290 TraceCheckUtils]: 126: Hoare triple {82846#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,437 INFO L290 TraceCheckUtils]: 127: Hoare triple {82846#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,437 INFO L290 TraceCheckUtils]: 128: Hoare triple {82846#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,437 INFO L290 TraceCheckUtils]: 129: Hoare triple {82846#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,437 INFO L290 TraceCheckUtils]: 130: Hoare triple {82846#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,437 INFO L290 TraceCheckUtils]: 131: Hoare triple {82846#false} assume !(1 == ~T8_E~0); {82846#false} is VALID [2022-02-21 04:23:32,437 INFO L290 TraceCheckUtils]: 132: Hoare triple {82846#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,437 INFO L290 TraceCheckUtils]: 133: Hoare triple {82846#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 134: Hoare triple {82846#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 135: Hoare triple {82846#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 136: Hoare triple {82846#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 137: Hoare triple {82846#false} assume 1 == ~E_M~0;~E_M~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 138: Hoare triple {82846#false} assume 1 == ~E_1~0;~E_1~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 139: Hoare triple {82846#false} assume !(1 == ~E_2~0); {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 140: Hoare triple {82846#false} assume 1 == ~E_3~0;~E_3~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 141: Hoare triple {82846#false} assume 1 == ~E_4~0;~E_4~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 142: Hoare triple {82846#false} assume 1 == ~E_5~0;~E_5~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 143: Hoare triple {82846#false} assume 1 == ~E_6~0;~E_6~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,438 INFO L290 TraceCheckUtils]: 144: Hoare triple {82846#false} assume 1 == ~E_7~0;~E_7~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,439 INFO L290 TraceCheckUtils]: 145: Hoare triple {82846#false} assume 1 == ~E_8~0;~E_8~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,439 INFO L290 TraceCheckUtils]: 146: Hoare triple {82846#false} assume 1 == ~E_9~0;~E_9~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,439 INFO L290 TraceCheckUtils]: 147: Hoare triple {82846#false} assume !(1 == ~E_10~0); {82846#false} is VALID [2022-02-21 04:23:32,439 INFO L290 TraceCheckUtils]: 148: Hoare triple {82846#false} assume 1 == ~E_11~0;~E_11~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,439 INFO L290 TraceCheckUtils]: 149: Hoare triple {82846#false} assume 1 == ~E_12~0;~E_12~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,439 INFO L290 TraceCheckUtils]: 150: Hoare triple {82846#false} assume 1 == ~E_13~0;~E_13~0 := 2; {82846#false} is VALID [2022-02-21 04:23:32,439 INFO L290 TraceCheckUtils]: 151: Hoare triple {82846#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {82846#false} is VALID [2022-02-21 04:23:32,439 INFO L290 TraceCheckUtils]: 152: Hoare triple {82846#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {82846#false} is VALID [2022-02-21 04:23:32,439 INFO L290 TraceCheckUtils]: 153: Hoare triple {82846#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {82846#false} is VALID [2022-02-21 04:23:32,440 INFO L290 TraceCheckUtils]: 154: Hoare triple {82846#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {82846#false} is VALID [2022-02-21 04:23:32,440 INFO L290 TraceCheckUtils]: 155: Hoare triple {82846#false} assume !(0 == start_simulation_~tmp~3#1); {82846#false} is VALID [2022-02-21 04:23:32,440 INFO L290 TraceCheckUtils]: 156: Hoare triple {82846#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {82846#false} is VALID [2022-02-21 04:23:32,440 INFO L290 TraceCheckUtils]: 157: Hoare triple {82846#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {82846#false} is VALID [2022-02-21 04:23:32,440 INFO L290 TraceCheckUtils]: 158: Hoare triple {82846#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {82846#false} is VALID [2022-02-21 04:23:32,440 INFO L290 TraceCheckUtils]: 159: Hoare triple {82846#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {82846#false} is VALID [2022-02-21 04:23:32,440 INFO L290 TraceCheckUtils]: 160: Hoare triple {82846#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {82846#false} is VALID [2022-02-21 04:23:32,440 INFO L290 TraceCheckUtils]: 161: Hoare triple {82846#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {82846#false} is VALID [2022-02-21 04:23:32,440 INFO L290 TraceCheckUtils]: 162: Hoare triple {82846#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {82846#false} is VALID [2022-02-21 04:23:32,440 INFO L290 TraceCheckUtils]: 163: Hoare triple {82846#false} assume !(0 != start_simulation_~tmp___0~1#1); {82846#false} is VALID [2022-02-21 04:23:32,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:32,441 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:32,441 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130645543] [2022-02-21 04:23:32,441 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130645543] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:32,441 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:32,441 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:32,441 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126416683] [2022-02-21 04:23:32,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:32,442 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:32,442 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:32,442 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:32,442 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:32,443 INFO L87 Difference]: Start difference. First operand 2018 states and 2978 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:33,992 INFO L93 Difference]: Finished difference Result 2018 states and 2977 transitions. [2022-02-21 04:23:33,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:33,992 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,096 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:34,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2977 transitions. [2022-02-21 04:23:34,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:34,317 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2977 transitions. [2022-02-21 04:23:34,317 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:34,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:34,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2977 transitions. [2022-02-21 04:23:34,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:34,320 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2022-02-21 04:23:34,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2977 transitions. [2022-02-21 04:23:34,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:34,337 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:34,339 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2977 transitions. Second operand has 2018 states, 2018 states have (on average 1.475222993062438) internal successors, (2977), 2017 states have internal predecessors, (2977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,340 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2977 transitions. Second operand has 2018 states, 2018 states have (on average 1.475222993062438) internal successors, (2977), 2017 states have internal predecessors, (2977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,341 INFO L87 Difference]: Start difference. First operand 2018 states and 2977 transitions. Second operand has 2018 states, 2018 states have (on average 1.475222993062438) internal successors, (2977), 2017 states have internal predecessors, (2977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:34,428 INFO L93 Difference]: Finished difference Result 2018 states and 2977 transitions. [2022-02-21 04:23:34,428 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2977 transitions. [2022-02-21 04:23:34,430 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:34,430 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:34,432 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.475222993062438) internal successors, (2977), 2017 states have internal predecessors, (2977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2977 transitions. [2022-02-21 04:23:34,433 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.475222993062438) internal successors, (2977), 2017 states have internal predecessors, (2977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2977 transitions. [2022-02-21 04:23:34,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:34,517 INFO L93 Difference]: Finished difference Result 2018 states and 2977 transitions. [2022-02-21 04:23:34,517 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2977 transitions. [2022-02-21 04:23:34,519 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:34,519 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:34,519 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:34,519 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:34,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.475222993062438) internal successors, (2977), 2017 states have internal predecessors, (2977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2977 transitions. [2022-02-21 04:23:34,605 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2022-02-21 04:23:34,605 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2022-02-21 04:23:34,605 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:23:34,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2977 transitions. [2022-02-21 04:23:34,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:34,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:34,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:34,610 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:34,610 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:34,611 INFO L791 eck$LassoCheckResult]: Stem: 85781#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85782#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86818#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86273#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86274#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 85763#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85764#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85830#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85831#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86269#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86270#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 85796#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85615#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85616#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 86060#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86061#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 85936#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 85937#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 85586#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85587#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 86810#L1279-2 assume !(0 == ~T1_E~0); 85209#L1284-1 assume !(0 == ~T2_E~0); 85210#L1289-1 assume !(0 == ~T3_E~0); 85933#L1294-1 assume !(0 == ~T4_E~0); 85934#L1299-1 assume !(0 == ~T5_E~0); 85945#L1304-1 assume !(0 == ~T6_E~0); 86876#L1309-1 assume !(0 == ~T7_E~0); 86877#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 85139#L1319-1 assume !(0 == ~T9_E~0); 85140#L1324-1 assume !(0 == ~T10_E~0); 85312#L1329-1 assume !(0 == ~T11_E~0); 85313#L1334-1 assume !(0 == ~T12_E~0); 86717#L1339-1 assume !(0 == ~T13_E~0); 86798#L1344-1 assume !(0 == ~E_M~0); 86799#L1349-1 assume !(0 == ~E_1~0); 86120#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 86121#L1359-1 assume !(0 == ~E_3~0); 86550#L1364-1 assume !(0 == ~E_4~0); 85441#L1369-1 assume !(0 == ~E_5~0); 85442#L1374-1 assume !(0 == ~E_6~0); 86125#L1379-1 assume !(0 == ~E_7~0); 86126#L1384-1 assume !(0 == ~E_8~0); 86203#L1389-1 assume !(0 == ~E_9~0); 86736#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 86737#L1399-1 assume !(0 == ~E_11~0); 86840#L1404-1 assume !(0 == ~E_12~0); 85534#L1409-1 assume !(0 == ~E_13~0); 85535#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86832#L628 assume !(1 == ~m_pc~0); 85438#L628-2 is_master_triggered_~__retres1~0#1 := 0; 85437#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86201#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86202#L1591 assume !(0 != activate_threads_~tmp~1#1); 86845#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85989#L647 assume 1 == ~t1_pc~0; 85358#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85359#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85630#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85631#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 86785#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86786#L666 assume 1 == ~t2_pc~0; 85206#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 85207#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85373#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86802#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 86321#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86322#L685 assume !(1 == ~t3_pc~0); 86427#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86426#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86049#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86050#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86171#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85657#L704 assume 1 == ~t4_pc~0; 85658#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 86182#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86183#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86823#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 86042#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86043#L723 assume !(1 == ~t5_pc~0); 86165#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86401#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86545#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86300#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 86301#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85423#L742 assume 1 == ~t6_pc~0; 85424#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85572#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85573#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85108#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 85109#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85500#L761 assume !(1 == ~t7_pc~0); 85501#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85369#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85370#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86172#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 86173#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85133#L780 assume 1 == ~t8_pc~0; 85134#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85409#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85410#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86133#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 86134#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86253#L799 assume 1 == ~t9_pc~0; 86365#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85136#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85137#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86265#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 86472#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86283#L818 assume !(1 == ~t10_pc~0); 84917#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 84918#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86358#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86287#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86288#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86328#L837 assume 1 == ~t11_pc~0; 86329#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86163#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86566#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86246#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 86247#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85998#L856 assume !(1 == ~t12_pc~0); 85999#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 86652#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86653#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86633#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 86634#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86813#L875 assume 1 == ~t13_pc~0; 85943#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85575#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85576#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85515#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 85516#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86355#L1427 assume !(1 == ~M_E~0); 86339#L1427-2 assume !(1 == ~T1_E~0); 85487#L1432-1 assume !(1 == ~T2_E~0); 85488#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86556#L1442-1 assume !(1 == ~T4_E~0); 86557#L1447-1 assume !(1 == ~T5_E~0); 86412#L1452-1 assume !(1 == ~T6_E~0); 85052#L1457-1 assume !(1 == ~T7_E~0); 85053#L1462-1 assume !(1 == ~T8_E~0); 86583#L1467-1 assume !(1 == ~T9_E~0); 86601#L1472-1 assume !(1 == ~T10_E~0); 86602#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86353#L1482-1 assume !(1 == ~T12_E~0); 86354#L1487-1 assume !(1 == ~T13_E~0); 85383#L1492-1 assume !(1 == ~E_M~0); 85384#L1497-1 assume !(1 == ~E_1~0); 85745#L1502-1 assume !(1 == ~E_2~0); 85746#L1507-1 assume !(1 == ~E_3~0); 85261#L1512-1 assume !(1 == ~E_4~0); 85262#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86672#L1522-1 assume !(1 == ~E_6~0); 85986#L1527-1 assume !(1 == ~E_7~0); 85987#L1532-1 assume !(1 == ~E_8~0); 86860#L1537-1 assume !(1 == ~E_9~0); 86189#L1542-1 assume !(1 == ~E_10~0); 86020#L1547-1 assume !(1 == ~E_11~0); 86021#L1552-1 assume !(1 == ~E_12~0); 84956#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 84957#L1562-1 assume { :end_inline_reset_delta_events } true; 85563#L1928-2 [2022-02-21 04:23:34,611 INFO L793 eck$LassoCheckResult]: Loop: 85563#L1928-2 assume !false; 86054#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85217#L1254 assume !false; 85804#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85291#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85292#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85489#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 86660#L1067 assume !(0 != eval_~tmp~0#1); 85730#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85307#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85308#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 85767#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85749#L1284-3 assume !(0 == ~T2_E~0); 85750#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85728#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85729#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86116#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 86117#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85626#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 85627#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86623#L1324-3 assume !(0 == ~T10_E~0); 85258#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85259#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 86026#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 86027#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 86325#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85607#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 85608#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 86336#L1364-3 assume !(0 == ~E_4~0); 86858#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86754#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 85387#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 85388#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 85605#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 85606#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 85896#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 86764#L1404-3 assume !(0 == ~E_12~0); 86728#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 86729#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86215#L628-45 assume 1 == ~m_pc~0; 85893#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 85895#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85252#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85253#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85641#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86364#L647-45 assume 1 == ~t1_pc~0; 85203#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85204#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86132#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85317#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 85318#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85529#L666-45 assume 1 == ~t2_pc~0; 85531#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86011#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86573#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86488#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86482#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85067#L685-45 assume !(1 == ~t3_pc~0); 85069#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 86127#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86801#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86670#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86671#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86811#L704-45 assume 1 == ~t4_pc~0; 86690#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 84934#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85793#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86136#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86883#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86248#L723-45 assume !(1 == ~t5_pc~0); 86249#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 86738#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85840#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85617#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 85618#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86642#L742-45 assume 1 == ~t6_pc~0; 86643#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85865#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86334#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86370#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86371#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86459#L761-45 assume 1 == ~t7_pc~0; 86461#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85858#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85859#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85265#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 85266#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86732#L780-45 assume 1 == ~t8_pc~0; 85643#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85277#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85278#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86859#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85247#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85248#L799-45 assume 1 == ~t9_pc~0; 86024#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85469#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86784#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86413#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 86414#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85185#L818-45 assume !(1 == ~t10_pc~0); 85187#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 85304#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86387#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85791#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85792#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86507#L837-45 assume !(1 == ~t11_pc~0); 85722#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 85723#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85860#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86525#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 85323#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85324#L856-45 assume 1 == ~t12_pc~0; 86809#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 85326#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85267#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85268#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 86130#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86131#L875-45 assume 1 == ~t13_pc~0; 86101#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86102#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86164#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86776#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86777#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86716#L1427-3 assume !(1 == ~M_E~0); 85927#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85928#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86466#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86118#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86119#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84975#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84976#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86658#L1462-3 assume !(1 == ~T8_E~0); 86659#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86522#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86523#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85226#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 85227#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 85368#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 85541#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 85542#L1502-3 assume !(1 == ~E_2~0); 86490#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86621#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85579#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85271#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 85272#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 85236#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85237#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86337#L1542-3 assume !(1 == ~E_10~0); 86475#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 86104#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 86105#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 85447#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85448#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84867#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85632#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 85633#L1947 assume !(0 == start_simulation_~tmp~3#1); 86238#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86443#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85504#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86836#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 86760#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86590#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86349#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 86350#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 85563#L1928-2 [2022-02-21 04:23:34,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:34,612 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2022-02-21 04:23:34,612 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:34,612 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969004186] [2022-02-21 04:23:34,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:34,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:34,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:34,632 INFO L290 TraceCheckUtils]: 0: Hoare triple {90923#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {90923#true} is VALID [2022-02-21 04:23:34,633 INFO L290 TraceCheckUtils]: 1: Hoare triple {90923#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,633 INFO L290 TraceCheckUtils]: 2: Hoare triple {90925#(= ~t12_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,633 INFO L290 TraceCheckUtils]: 3: Hoare triple {90925#(= ~t12_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,634 INFO L290 TraceCheckUtils]: 4: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,634 INFO L290 TraceCheckUtils]: 5: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,634 INFO L290 TraceCheckUtils]: 6: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,635 INFO L290 TraceCheckUtils]: 7: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,635 INFO L290 TraceCheckUtils]: 8: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,635 INFO L290 TraceCheckUtils]: 9: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,635 INFO L290 TraceCheckUtils]: 10: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,636 INFO L290 TraceCheckUtils]: 11: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,636 INFO L290 TraceCheckUtils]: 12: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,636 INFO L290 TraceCheckUtils]: 13: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,636 INFO L290 TraceCheckUtils]: 14: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 15: Hoare triple {90925#(= ~t12_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {90925#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 16: Hoare triple {90925#(= ~t12_i~0 1)} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {90924#false} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 17: Hoare triple {90924#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {90924#false} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 18: Hoare triple {90924#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {90924#false} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 19: Hoare triple {90924#false} assume 0 == ~M_E~0;~M_E~0 := 1; {90924#false} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 20: Hoare triple {90924#false} assume !(0 == ~T1_E~0); {90924#false} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 21: Hoare triple {90924#false} assume !(0 == ~T2_E~0); {90924#false} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 22: Hoare triple {90924#false} assume !(0 == ~T3_E~0); {90924#false} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 23: Hoare triple {90924#false} assume !(0 == ~T4_E~0); {90924#false} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 24: Hoare triple {90924#false} assume !(0 == ~T5_E~0); {90924#false} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 25: Hoare triple {90924#false} assume !(0 == ~T6_E~0); {90924#false} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 26: Hoare triple {90924#false} assume !(0 == ~T7_E~0); {90924#false} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 27: Hoare triple {90924#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {90924#false} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 28: Hoare triple {90924#false} assume !(0 == ~T9_E~0); {90924#false} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 29: Hoare triple {90924#false} assume !(0 == ~T10_E~0); {90924#false} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 30: Hoare triple {90924#false} assume !(0 == ~T11_E~0); {90924#false} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 31: Hoare triple {90924#false} assume !(0 == ~T12_E~0); {90924#false} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 32: Hoare triple {90924#false} assume !(0 == ~T13_E~0); {90924#false} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 33: Hoare triple {90924#false} assume !(0 == ~E_M~0); {90924#false} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 34: Hoare triple {90924#false} assume !(0 == ~E_1~0); {90924#false} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 35: Hoare triple {90924#false} assume 0 == ~E_2~0;~E_2~0 := 1; {90924#false} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 36: Hoare triple {90924#false} assume !(0 == ~E_3~0); {90924#false} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 37: Hoare triple {90924#false} assume !(0 == ~E_4~0); {90924#false} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 38: Hoare triple {90924#false} assume !(0 == ~E_5~0); {90924#false} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 39: Hoare triple {90924#false} assume !(0 == ~E_6~0); {90924#false} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 40: Hoare triple {90924#false} assume !(0 == ~E_7~0); {90924#false} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 41: Hoare triple {90924#false} assume !(0 == ~E_8~0); {90924#false} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 42: Hoare triple {90924#false} assume !(0 == ~E_9~0); {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 43: Hoare triple {90924#false} assume 0 == ~E_10~0;~E_10~0 := 1; {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 44: Hoare triple {90924#false} assume !(0 == ~E_11~0); {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 45: Hoare triple {90924#false} assume !(0 == ~E_12~0); {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 46: Hoare triple {90924#false} assume !(0 == ~E_13~0); {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 47: Hoare triple {90924#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 48: Hoare triple {90924#false} assume !(1 == ~m_pc~0); {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 49: Hoare triple {90924#false} is_master_triggered_~__retres1~0#1 := 0; {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 50: Hoare triple {90924#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 51: Hoare triple {90924#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 52: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp~1#1); {90924#false} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 53: Hoare triple {90924#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {90924#false} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 54: Hoare triple {90924#false} assume 1 == ~t1_pc~0; {90924#false} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 55: Hoare triple {90924#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {90924#false} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 56: Hoare triple {90924#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {90924#false} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 57: Hoare triple {90924#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {90924#false} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 58: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___0~0#1); {90924#false} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 59: Hoare triple {90924#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {90924#false} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 60: Hoare triple {90924#false} assume 1 == ~t2_pc~0; {90924#false} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 61: Hoare triple {90924#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {90924#false} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 62: Hoare triple {90924#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {90924#false} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 63: Hoare triple {90924#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {90924#false} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 64: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___1~0#1); {90924#false} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 65: Hoare triple {90924#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {90924#false} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 66: Hoare triple {90924#false} assume !(1 == ~t3_pc~0); {90924#false} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 67: Hoare triple {90924#false} is_transmit3_triggered_~__retres1~3#1 := 0; {90924#false} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 68: Hoare triple {90924#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {90924#false} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 69: Hoare triple {90924#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {90924#false} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 70: Hoare triple {90924#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {90924#false} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 71: Hoare triple {90924#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {90924#false} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 72: Hoare triple {90924#false} assume 1 == ~t4_pc~0; {90924#false} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 73: Hoare triple {90924#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {90924#false} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 74: Hoare triple {90924#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {90924#false} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 75: Hoare triple {90924#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {90924#false} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 76: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___3~0#1); {90924#false} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 77: Hoare triple {90924#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {90924#false} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 78: Hoare triple {90924#false} assume !(1 == ~t5_pc~0); {90924#false} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 79: Hoare triple {90924#false} is_transmit5_triggered_~__retres1~5#1 := 0; {90924#false} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 80: Hoare triple {90924#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {90924#false} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 81: Hoare triple {90924#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {90924#false} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 82: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___4~0#1); {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 83: Hoare triple {90924#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 84: Hoare triple {90924#false} assume 1 == ~t6_pc~0; {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 85: Hoare triple {90924#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 86: Hoare triple {90924#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 87: Hoare triple {90924#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 88: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___5~0#1); {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 89: Hoare triple {90924#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 90: Hoare triple {90924#false} assume !(1 == ~t7_pc~0); {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 91: Hoare triple {90924#false} is_transmit7_triggered_~__retres1~7#1 := 0; {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 92: Hoare triple {90924#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {90924#false} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 93: Hoare triple {90924#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {90924#false} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 94: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___6~0#1); {90924#false} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 95: Hoare triple {90924#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {90924#false} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 96: Hoare triple {90924#false} assume 1 == ~t8_pc~0; {90924#false} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 97: Hoare triple {90924#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {90924#false} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 98: Hoare triple {90924#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {90924#false} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 99: Hoare triple {90924#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {90924#false} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 100: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___7~0#1); {90924#false} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 101: Hoare triple {90924#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {90924#false} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 102: Hoare triple {90924#false} assume 1 == ~t9_pc~0; {90924#false} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 103: Hoare triple {90924#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 104: Hoare triple {90924#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 105: Hoare triple {90924#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 106: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___8~0#1); {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 107: Hoare triple {90924#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 108: Hoare triple {90924#false} assume !(1 == ~t10_pc~0); {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 109: Hoare triple {90924#false} is_transmit10_triggered_~__retres1~10#1 := 0; {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 110: Hoare triple {90924#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 111: Hoare triple {90924#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 112: Hoare triple {90924#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 113: Hoare triple {90924#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {90924#false} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 114: Hoare triple {90924#false} assume 1 == ~t11_pc~0; {90924#false} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 115: Hoare triple {90924#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {90924#false} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 116: Hoare triple {90924#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {90924#false} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 117: Hoare triple {90924#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {90924#false} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 118: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___10~0#1); {90924#false} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 119: Hoare triple {90924#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {90924#false} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 120: Hoare triple {90924#false} assume !(1 == ~t12_pc~0); {90924#false} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 121: Hoare triple {90924#false} is_transmit12_triggered_~__retres1~12#1 := 0; {90924#false} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 122: Hoare triple {90924#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {90924#false} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 123: Hoare triple {90924#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {90924#false} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 124: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___11~0#1); {90924#false} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 125: Hoare triple {90924#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {90924#false} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 126: Hoare triple {90924#false} assume 1 == ~t13_pc~0; {90924#false} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 127: Hoare triple {90924#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {90924#false} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 128: Hoare triple {90924#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {90924#false} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 129: Hoare triple {90924#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {90924#false} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 130: Hoare triple {90924#false} assume !(0 != activate_threads_~tmp___12~0#1); {90924#false} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 131: Hoare triple {90924#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {90924#false} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 132: Hoare triple {90924#false} assume !(1 == ~M_E~0); {90924#false} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 133: Hoare triple {90924#false} assume !(1 == ~T1_E~0); {90924#false} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 134: Hoare triple {90924#false} assume !(1 == ~T2_E~0); {90924#false} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 135: Hoare triple {90924#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {90924#false} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 136: Hoare triple {90924#false} assume !(1 == ~T4_E~0); {90924#false} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 137: Hoare triple {90924#false} assume !(1 == ~T5_E~0); {90924#false} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 138: Hoare triple {90924#false} assume !(1 == ~T6_E~0); {90924#false} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 139: Hoare triple {90924#false} assume !(1 == ~T7_E~0); {90924#false} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 140: Hoare triple {90924#false} assume !(1 == ~T8_E~0); {90924#false} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 141: Hoare triple {90924#false} assume !(1 == ~T9_E~0); {90924#false} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 142: Hoare triple {90924#false} assume !(1 == ~T10_E~0); {90924#false} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 143: Hoare triple {90924#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {90924#false} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 144: Hoare triple {90924#false} assume !(1 == ~T12_E~0); {90924#false} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 145: Hoare triple {90924#false} assume !(1 == ~T13_E~0); {90924#false} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 146: Hoare triple {90924#false} assume !(1 == ~E_M~0); {90924#false} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 147: Hoare triple {90924#false} assume !(1 == ~E_1~0); {90924#false} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 148: Hoare triple {90924#false} assume !(1 == ~E_2~0); {90924#false} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 149: Hoare triple {90924#false} assume !(1 == ~E_3~0); {90924#false} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 150: Hoare triple {90924#false} assume !(1 == ~E_4~0); {90924#false} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 151: Hoare triple {90924#false} assume 1 == ~E_5~0;~E_5~0 := 2; {90924#false} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 152: Hoare triple {90924#false} assume !(1 == ~E_6~0); {90924#false} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 153: Hoare triple {90924#false} assume !(1 == ~E_7~0); {90924#false} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 154: Hoare triple {90924#false} assume !(1 == ~E_8~0); {90924#false} is VALID [2022-02-21 04:23:34,651 INFO L290 TraceCheckUtils]: 155: Hoare triple {90924#false} assume !(1 == ~E_9~0); {90924#false} is VALID [2022-02-21 04:23:34,651 INFO L290 TraceCheckUtils]: 156: Hoare triple {90924#false} assume !(1 == ~E_10~0); {90924#false} is VALID [2022-02-21 04:23:34,651 INFO L290 TraceCheckUtils]: 157: Hoare triple {90924#false} assume !(1 == ~E_11~0); {90924#false} is VALID [2022-02-21 04:23:34,651 INFO L290 TraceCheckUtils]: 158: Hoare triple {90924#false} assume !(1 == ~E_12~0); {90924#false} is VALID [2022-02-21 04:23:34,651 INFO L290 TraceCheckUtils]: 159: Hoare triple {90924#false} assume 1 == ~E_13~0;~E_13~0 := 2; {90924#false} is VALID [2022-02-21 04:23:34,651 INFO L290 TraceCheckUtils]: 160: Hoare triple {90924#false} assume { :end_inline_reset_delta_events } true; {90924#false} is VALID [2022-02-21 04:23:34,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:34,651 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:34,652 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [969004186] [2022-02-21 04:23:34,652 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [969004186] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:34,652 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:34,652 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:34,652 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191884064] [2022-02-21 04:23:34,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:34,652 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:34,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:34,653 INFO L85 PathProgramCache]: Analyzing trace with hash -1640420756, now seen corresponding path program 2 times [2022-02-21 04:23:34,653 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:34,653 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716396746] [2022-02-21 04:23:34,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:34,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:34,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:34,678 INFO L290 TraceCheckUtils]: 0: Hoare triple {90926#true} assume !false; {90926#true} is VALID [2022-02-21 04:23:34,678 INFO L290 TraceCheckUtils]: 1: Hoare triple {90926#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {90926#true} is VALID [2022-02-21 04:23:34,678 INFO L290 TraceCheckUtils]: 2: Hoare triple {90926#true} assume !false; {90926#true} is VALID [2022-02-21 04:23:34,678 INFO L290 TraceCheckUtils]: 3: Hoare triple {90926#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {90926#true} is VALID [2022-02-21 04:23:34,678 INFO L290 TraceCheckUtils]: 4: Hoare triple {90926#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {90926#true} is VALID [2022-02-21 04:23:34,679 INFO L290 TraceCheckUtils]: 5: Hoare triple {90926#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {90926#true} is VALID [2022-02-21 04:23:34,679 INFO L290 TraceCheckUtils]: 6: Hoare triple {90926#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {90926#true} is VALID [2022-02-21 04:23:34,679 INFO L290 TraceCheckUtils]: 7: Hoare triple {90926#true} assume !(0 != eval_~tmp~0#1); {90926#true} is VALID [2022-02-21 04:23:34,679 INFO L290 TraceCheckUtils]: 8: Hoare triple {90926#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {90926#true} is VALID [2022-02-21 04:23:34,679 INFO L290 TraceCheckUtils]: 9: Hoare triple {90926#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {90926#true} is VALID [2022-02-21 04:23:34,679 INFO L290 TraceCheckUtils]: 10: Hoare triple {90926#true} assume 0 == ~M_E~0;~M_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,679 INFO L290 TraceCheckUtils]: 11: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,680 INFO L290 TraceCheckUtils]: 12: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,680 INFO L290 TraceCheckUtils]: 13: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,680 INFO L290 TraceCheckUtils]: 14: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,681 INFO L290 TraceCheckUtils]: 15: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,681 INFO L290 TraceCheckUtils]: 16: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,681 INFO L290 TraceCheckUtils]: 17: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,681 INFO L290 TraceCheckUtils]: 18: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,682 INFO L290 TraceCheckUtils]: 19: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,682 INFO L290 TraceCheckUtils]: 20: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,682 INFO L290 TraceCheckUtils]: 21: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,682 INFO L290 TraceCheckUtils]: 22: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,683 INFO L290 TraceCheckUtils]: 23: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,683 INFO L290 TraceCheckUtils]: 24: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,683 INFO L290 TraceCheckUtils]: 25: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,683 INFO L290 TraceCheckUtils]: 26: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,684 INFO L290 TraceCheckUtils]: 27: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,684 INFO L290 TraceCheckUtils]: 28: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,684 INFO L290 TraceCheckUtils]: 29: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,684 INFO L290 TraceCheckUtils]: 30: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,685 INFO L290 TraceCheckUtils]: 31: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,685 INFO L290 TraceCheckUtils]: 32: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,685 INFO L290 TraceCheckUtils]: 33: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,685 INFO L290 TraceCheckUtils]: 34: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,686 INFO L290 TraceCheckUtils]: 35: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,686 INFO L290 TraceCheckUtils]: 36: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,686 INFO L290 TraceCheckUtils]: 37: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,686 INFO L290 TraceCheckUtils]: 38: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,687 INFO L290 TraceCheckUtils]: 39: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,687 INFO L290 TraceCheckUtils]: 40: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,687 INFO L290 TraceCheckUtils]: 41: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,687 INFO L290 TraceCheckUtils]: 42: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,688 INFO L290 TraceCheckUtils]: 43: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,688 INFO L290 TraceCheckUtils]: 44: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,688 INFO L290 TraceCheckUtils]: 45: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,689 INFO L290 TraceCheckUtils]: 46: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,689 INFO L290 TraceCheckUtils]: 47: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,689 INFO L290 TraceCheckUtils]: 48: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,689 INFO L290 TraceCheckUtils]: 49: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,690 INFO L290 TraceCheckUtils]: 50: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,690 INFO L290 TraceCheckUtils]: 51: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,690 INFO L290 TraceCheckUtils]: 52: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,690 INFO L290 TraceCheckUtils]: 53: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,691 INFO L290 TraceCheckUtils]: 54: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,691 INFO L290 TraceCheckUtils]: 55: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,691 INFO L290 TraceCheckUtils]: 56: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,691 INFO L290 TraceCheckUtils]: 57: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,692 INFO L290 TraceCheckUtils]: 58: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,692 INFO L290 TraceCheckUtils]: 59: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,692 INFO L290 TraceCheckUtils]: 60: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,692 INFO L290 TraceCheckUtils]: 61: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,693 INFO L290 TraceCheckUtils]: 62: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,693 INFO L290 TraceCheckUtils]: 63: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,693 INFO L290 TraceCheckUtils]: 64: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,693 INFO L290 TraceCheckUtils]: 65: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,694 INFO L290 TraceCheckUtils]: 66: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,694 INFO L290 TraceCheckUtils]: 67: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,694 INFO L290 TraceCheckUtils]: 68: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,695 INFO L290 TraceCheckUtils]: 69: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,695 INFO L290 TraceCheckUtils]: 70: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,695 INFO L290 TraceCheckUtils]: 71: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,695 INFO L290 TraceCheckUtils]: 72: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,696 INFO L290 TraceCheckUtils]: 73: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,696 INFO L290 TraceCheckUtils]: 74: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,696 INFO L290 TraceCheckUtils]: 75: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,696 INFO L290 TraceCheckUtils]: 76: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,697 INFO L290 TraceCheckUtils]: 77: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,697 INFO L290 TraceCheckUtils]: 78: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,697 INFO L290 TraceCheckUtils]: 79: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,698 INFO L290 TraceCheckUtils]: 80: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,698 INFO L290 TraceCheckUtils]: 81: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,698 INFO L290 TraceCheckUtils]: 82: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,698 INFO L290 TraceCheckUtils]: 83: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,699 INFO L290 TraceCheckUtils]: 84: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,699 INFO L290 TraceCheckUtils]: 85: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,699 INFO L290 TraceCheckUtils]: 86: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,699 INFO L290 TraceCheckUtils]: 87: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,700 INFO L290 TraceCheckUtils]: 88: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,700 INFO L290 TraceCheckUtils]: 89: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,700 INFO L290 TraceCheckUtils]: 90: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,700 INFO L290 TraceCheckUtils]: 91: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,701 INFO L290 TraceCheckUtils]: 92: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,701 INFO L290 TraceCheckUtils]: 93: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,701 INFO L290 TraceCheckUtils]: 94: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,701 INFO L290 TraceCheckUtils]: 95: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,702 INFO L290 TraceCheckUtils]: 96: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,702 INFO L290 TraceCheckUtils]: 97: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,702 INFO L290 TraceCheckUtils]: 98: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,703 INFO L290 TraceCheckUtils]: 99: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,703 INFO L290 TraceCheckUtils]: 100: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,703 INFO L290 TraceCheckUtils]: 101: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,703 INFO L290 TraceCheckUtils]: 102: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,704 INFO L290 TraceCheckUtils]: 103: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,704 INFO L290 TraceCheckUtils]: 104: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,704 INFO L290 TraceCheckUtils]: 105: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,704 INFO L290 TraceCheckUtils]: 106: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,705 INFO L290 TraceCheckUtils]: 107: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,705 INFO L290 TraceCheckUtils]: 108: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,705 INFO L290 TraceCheckUtils]: 109: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,705 INFO L290 TraceCheckUtils]: 110: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,706 INFO L290 TraceCheckUtils]: 111: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,706 INFO L290 TraceCheckUtils]: 112: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,706 INFO L290 TraceCheckUtils]: 113: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,706 INFO L290 TraceCheckUtils]: 114: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,707 INFO L290 TraceCheckUtils]: 115: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,707 INFO L290 TraceCheckUtils]: 116: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,707 INFO L290 TraceCheckUtils]: 117: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,708 INFO L290 TraceCheckUtils]: 118: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,708 INFO L290 TraceCheckUtils]: 119: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,708 INFO L290 TraceCheckUtils]: 120: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,708 INFO L290 TraceCheckUtils]: 121: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,709 INFO L290 TraceCheckUtils]: 122: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {90928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:34,709 INFO L290 TraceCheckUtils]: 123: Hoare triple {90928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {90927#false} is VALID [2022-02-21 04:23:34,709 INFO L290 TraceCheckUtils]: 124: Hoare triple {90927#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,709 INFO L290 TraceCheckUtils]: 125: Hoare triple {90927#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,709 INFO L290 TraceCheckUtils]: 126: Hoare triple {90927#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,709 INFO L290 TraceCheckUtils]: 127: Hoare triple {90927#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,709 INFO L290 TraceCheckUtils]: 128: Hoare triple {90927#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,709 INFO L290 TraceCheckUtils]: 129: Hoare triple {90927#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 130: Hoare triple {90927#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 131: Hoare triple {90927#false} assume !(1 == ~T8_E~0); {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 132: Hoare triple {90927#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 133: Hoare triple {90927#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 134: Hoare triple {90927#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 135: Hoare triple {90927#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 136: Hoare triple {90927#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 137: Hoare triple {90927#false} assume 1 == ~E_M~0;~E_M~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 138: Hoare triple {90927#false} assume 1 == ~E_1~0;~E_1~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 139: Hoare triple {90927#false} assume !(1 == ~E_2~0); {90927#false} is VALID [2022-02-21 04:23:34,710 INFO L290 TraceCheckUtils]: 140: Hoare triple {90927#false} assume 1 == ~E_3~0;~E_3~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,711 INFO L290 TraceCheckUtils]: 141: Hoare triple {90927#false} assume 1 == ~E_4~0;~E_4~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,711 INFO L290 TraceCheckUtils]: 142: Hoare triple {90927#false} assume 1 == ~E_5~0;~E_5~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,711 INFO L290 TraceCheckUtils]: 143: Hoare triple {90927#false} assume 1 == ~E_6~0;~E_6~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,711 INFO L290 TraceCheckUtils]: 144: Hoare triple {90927#false} assume 1 == ~E_7~0;~E_7~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,711 INFO L290 TraceCheckUtils]: 145: Hoare triple {90927#false} assume 1 == ~E_8~0;~E_8~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,711 INFO L290 TraceCheckUtils]: 146: Hoare triple {90927#false} assume 1 == ~E_9~0;~E_9~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,711 INFO L290 TraceCheckUtils]: 147: Hoare triple {90927#false} assume !(1 == ~E_10~0); {90927#false} is VALID [2022-02-21 04:23:34,711 INFO L290 TraceCheckUtils]: 148: Hoare triple {90927#false} assume 1 == ~E_11~0;~E_11~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,711 INFO L290 TraceCheckUtils]: 149: Hoare triple {90927#false} assume 1 == ~E_12~0;~E_12~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,711 INFO L290 TraceCheckUtils]: 150: Hoare triple {90927#false} assume 1 == ~E_13~0;~E_13~0 := 2; {90927#false} is VALID [2022-02-21 04:23:34,712 INFO L290 TraceCheckUtils]: 151: Hoare triple {90927#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {90927#false} is VALID [2022-02-21 04:23:34,712 INFO L290 TraceCheckUtils]: 152: Hoare triple {90927#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {90927#false} is VALID [2022-02-21 04:23:34,712 INFO L290 TraceCheckUtils]: 153: Hoare triple {90927#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {90927#false} is VALID [2022-02-21 04:23:34,712 INFO L290 TraceCheckUtils]: 154: Hoare triple {90927#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {90927#false} is VALID [2022-02-21 04:23:34,712 INFO L290 TraceCheckUtils]: 155: Hoare triple {90927#false} assume !(0 == start_simulation_~tmp~3#1); {90927#false} is VALID [2022-02-21 04:23:34,712 INFO L290 TraceCheckUtils]: 156: Hoare triple {90927#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {90927#false} is VALID [2022-02-21 04:23:34,712 INFO L290 TraceCheckUtils]: 157: Hoare triple {90927#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {90927#false} is VALID [2022-02-21 04:23:34,712 INFO L290 TraceCheckUtils]: 158: Hoare triple {90927#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {90927#false} is VALID [2022-02-21 04:23:34,712 INFO L290 TraceCheckUtils]: 159: Hoare triple {90927#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {90927#false} is VALID [2022-02-21 04:23:34,712 INFO L290 TraceCheckUtils]: 160: Hoare triple {90927#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {90927#false} is VALID [2022-02-21 04:23:34,713 INFO L290 TraceCheckUtils]: 161: Hoare triple {90927#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {90927#false} is VALID [2022-02-21 04:23:34,713 INFO L290 TraceCheckUtils]: 162: Hoare triple {90927#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {90927#false} is VALID [2022-02-21 04:23:34,713 INFO L290 TraceCheckUtils]: 163: Hoare triple {90927#false} assume !(0 != start_simulation_~tmp___0~1#1); {90927#false} is VALID [2022-02-21 04:23:34,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:34,713 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:34,713 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716396746] [2022-02-21 04:23:34,713 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716396746] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:34,714 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:34,714 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:34,714 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527716558] [2022-02-21 04:23:34,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:34,714 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:34,714 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:34,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:34,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:34,715 INFO L87 Difference]: Start difference. First operand 2018 states and 2977 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:36,185 INFO L93 Difference]: Finished difference Result 2018 states and 2976 transitions. [2022-02-21 04:23:36,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:36,185 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,272 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:36,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2976 transitions. [2022-02-21 04:23:36,377 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:36,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2976 transitions. [2022-02-21 04:23:36,482 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:36,482 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:36,482 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2976 transitions. [2022-02-21 04:23:36,484 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:36,484 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2022-02-21 04:23:36,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2976 transitions. [2022-02-21 04:23:36,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:36,499 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:36,500 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2976 transitions. Second operand has 2018 states, 2018 states have (on average 1.474727452923687) internal successors, (2976), 2017 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,502 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2976 transitions. Second operand has 2018 states, 2018 states have (on average 1.474727452923687) internal successors, (2976), 2017 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,503 INFO L87 Difference]: Start difference. First operand 2018 states and 2976 transitions. Second operand has 2018 states, 2018 states have (on average 1.474727452923687) internal successors, (2976), 2017 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:36,610 INFO L93 Difference]: Finished difference Result 2018 states and 2976 transitions. [2022-02-21 04:23:36,610 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2976 transitions. [2022-02-21 04:23:36,612 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:36,612 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:36,614 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.474727452923687) internal successors, (2976), 2017 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2976 transitions. [2022-02-21 04:23:36,615 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.474727452923687) internal successors, (2976), 2017 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2976 transitions. [2022-02-21 04:23:36,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:36,698 INFO L93 Difference]: Finished difference Result 2018 states and 2976 transitions. [2022-02-21 04:23:36,698 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2976 transitions. [2022-02-21 04:23:36,700 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:36,700 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:36,700 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:36,700 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:36,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.474727452923687) internal successors, (2976), 2017 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2976 transitions. [2022-02-21 04:23:36,786 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2022-02-21 04:23:36,786 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2022-02-21 04:23:36,787 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:23:36,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2976 transitions. [2022-02-21 04:23:36,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:36,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:36,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:36,791 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:36,791 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:36,792 INFO L791 eck$LassoCheckResult]: Stem: 93862#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 93863#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 94899#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94354#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94355#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 93844#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93845#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93911#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93912#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94350#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94351#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 93877#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 93696#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 93697#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 94141#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 94142#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 94017#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 94018#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 93667#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93668#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 94891#L1279-2 assume !(0 == ~T1_E~0); 93290#L1284-1 assume !(0 == ~T2_E~0); 93291#L1289-1 assume !(0 == ~T3_E~0); 94014#L1294-1 assume !(0 == ~T4_E~0); 94015#L1299-1 assume !(0 == ~T5_E~0); 94026#L1304-1 assume !(0 == ~T6_E~0); 94957#L1309-1 assume !(0 == ~T7_E~0); 94958#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 93220#L1319-1 assume !(0 == ~T9_E~0); 93221#L1324-1 assume !(0 == ~T10_E~0); 93393#L1329-1 assume !(0 == ~T11_E~0); 93394#L1334-1 assume !(0 == ~T12_E~0); 94798#L1339-1 assume !(0 == ~T13_E~0); 94879#L1344-1 assume !(0 == ~E_M~0); 94880#L1349-1 assume !(0 == ~E_1~0); 94201#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 94202#L1359-1 assume !(0 == ~E_3~0); 94631#L1364-1 assume !(0 == ~E_4~0); 93522#L1369-1 assume !(0 == ~E_5~0); 93523#L1374-1 assume !(0 == ~E_6~0); 94206#L1379-1 assume !(0 == ~E_7~0); 94207#L1384-1 assume !(0 == ~E_8~0); 94284#L1389-1 assume !(0 == ~E_9~0); 94817#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 94818#L1399-1 assume !(0 == ~E_11~0); 94921#L1404-1 assume !(0 == ~E_12~0); 93615#L1409-1 assume !(0 == ~E_13~0); 93616#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94913#L628 assume !(1 == ~m_pc~0); 93519#L628-2 is_master_triggered_~__retres1~0#1 := 0; 93518#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94282#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 94283#L1591 assume !(0 != activate_threads_~tmp~1#1); 94926#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94070#L647 assume 1 == ~t1_pc~0; 93439#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 93440#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93711#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 93712#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 94866#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94867#L666 assume 1 == ~t2_pc~0; 93287#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 93288#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 93454#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94883#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 94402#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94403#L685 assume !(1 == ~t3_pc~0); 94508#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94507#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94130#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94131#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 94252#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93738#L704 assume 1 == ~t4_pc~0; 93739#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 94263#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94264#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94904#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 94123#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94124#L723 assume !(1 == ~t5_pc~0); 94246#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 94482#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94626#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 94381#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 94382#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 93504#L742 assume 1 == ~t6_pc~0; 93505#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 93653#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 93654#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 93189#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 93190#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 93581#L761 assume !(1 == ~t7_pc~0); 93582#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 93450#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 93451#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94253#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 94254#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 93214#L780 assume 1 == ~t8_pc~0; 93215#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 93490#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 93491#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94214#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 94215#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94334#L799 assume 1 == ~t9_pc~0; 94446#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 93217#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 93218#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 94346#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 94553#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 94364#L818 assume !(1 == ~t10_pc~0); 92998#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 92999#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94439#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 94368#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 94369#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 94409#L837 assume 1 == ~t11_pc~0; 94410#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 94244#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 94647#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 94327#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 94328#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 94079#L856 assume !(1 == ~t12_pc~0); 94080#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 94733#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 94734#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 94714#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 94715#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 94894#L875 assume 1 == ~t13_pc~0; 94024#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 93656#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 93657#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 93596#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 93597#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94436#L1427 assume !(1 == ~M_E~0); 94420#L1427-2 assume !(1 == ~T1_E~0); 93568#L1432-1 assume !(1 == ~T2_E~0); 93569#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94637#L1442-1 assume !(1 == ~T4_E~0); 94638#L1447-1 assume !(1 == ~T5_E~0); 94493#L1452-1 assume !(1 == ~T6_E~0); 93133#L1457-1 assume !(1 == ~T7_E~0); 93134#L1462-1 assume !(1 == ~T8_E~0); 94664#L1467-1 assume !(1 == ~T9_E~0); 94682#L1472-1 assume !(1 == ~T10_E~0); 94683#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94434#L1482-1 assume !(1 == ~T12_E~0); 94435#L1487-1 assume !(1 == ~T13_E~0); 93464#L1492-1 assume !(1 == ~E_M~0); 93465#L1497-1 assume !(1 == ~E_1~0); 93826#L1502-1 assume !(1 == ~E_2~0); 93827#L1507-1 assume !(1 == ~E_3~0); 93342#L1512-1 assume !(1 == ~E_4~0); 93343#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 94753#L1522-1 assume !(1 == ~E_6~0); 94067#L1527-1 assume !(1 == ~E_7~0); 94068#L1532-1 assume !(1 == ~E_8~0); 94941#L1537-1 assume !(1 == ~E_9~0); 94270#L1542-1 assume !(1 == ~E_10~0); 94101#L1547-1 assume !(1 == ~E_11~0); 94102#L1552-1 assume !(1 == ~E_12~0); 93037#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 93038#L1562-1 assume { :end_inline_reset_delta_events } true; 93644#L1928-2 [2022-02-21 04:23:36,792 INFO L793 eck$LassoCheckResult]: Loop: 93644#L1928-2 assume !false; 94135#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93298#L1254 assume !false; 93885#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 93372#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93373#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 93570#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 94741#L1067 assume !(0 != eval_~tmp~0#1); 93811#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 93388#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 93389#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 93848#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 93830#L1284-3 assume !(0 == ~T2_E~0); 93831#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 93809#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 93810#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94197#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 94198#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 93707#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 93708#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 94704#L1324-3 assume !(0 == ~T10_E~0); 93339#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 93340#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 94107#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 94108#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 94406#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 93688#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 93689#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 94417#L1364-3 assume !(0 == ~E_4~0); 94939#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 94835#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 93468#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 93469#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 93686#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 93687#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 93977#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 94845#L1404-3 assume !(0 == ~E_12~0); 94809#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 94810#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94296#L628-45 assume !(1 == ~m_pc~0); 93975#L628-47 is_master_triggered_~__retres1~0#1 := 0; 93976#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93333#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 93334#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 93722#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94445#L647-45 assume 1 == ~t1_pc~0; 93284#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 93285#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94213#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 93398#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 93399#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93610#L666-45 assume !(1 == ~t2_pc~0); 93611#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 94092#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94654#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94569#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 94563#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 93148#L685-45 assume 1 == ~t3_pc~0; 93149#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94208#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94882#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94751#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 94752#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94892#L704-45 assume 1 == ~t4_pc~0; 94771#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 93015#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93874#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94217#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94964#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94329#L723-45 assume 1 == ~t5_pc~0; 94331#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 94819#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 93921#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 93698#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 93699#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94723#L742-45 assume 1 == ~t6_pc~0; 94724#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 93946#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94415#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 94451#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 94452#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94540#L761-45 assume !(1 == ~t7_pc~0); 94541#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 93939#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 93940#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93346#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 93347#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94813#L780-45 assume !(1 == ~t8_pc~0); 93725#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 93358#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 93359#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94940#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 93328#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 93329#L799-45 assume 1 == ~t9_pc~0; 94105#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 93550#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94865#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 94494#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 94495#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 93266#L818-45 assume 1 == ~t10_pc~0; 93267#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 93385#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94468#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 93872#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 93873#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 94588#L837-45 assume !(1 == ~t11_pc~0); 93803#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 93804#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 93941#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 94606#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 93404#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 93405#L856-45 assume 1 == ~t12_pc~0; 94890#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 93407#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 93348#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 93349#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 94211#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 94212#L875-45 assume 1 == ~t13_pc~0; 94182#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 94183#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 94245#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 94857#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 94858#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94797#L1427-3 assume !(1 == ~M_E~0); 94008#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 94009#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94547#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94199#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94200#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 93056#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 93057#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 94739#L1462-3 assume !(1 == ~T8_E~0); 94740#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 94603#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 94604#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 93307#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 93308#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 93449#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 93622#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 93623#L1502-3 assume !(1 == ~E_2~0); 94571#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94702#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 93660#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 93352#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 93353#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 93317#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 93318#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 94418#L1542-3 assume !(1 == ~E_10~0); 94556#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 94185#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 94186#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 93528#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 93529#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 92948#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 93713#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 93714#L1947 assume !(0 == start_simulation_~tmp~3#1); 94319#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 94524#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93585#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 94917#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 94841#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 94671#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 94430#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 94431#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 93644#L1928-2 [2022-02-21 04:23:36,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:36,793 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2022-02-21 04:23:36,793 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:36,793 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993074323] [2022-02-21 04:23:36,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:36,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:36,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:36,814 INFO L290 TraceCheckUtils]: 0: Hoare triple {99004#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {99004#true} is VALID [2022-02-21 04:23:36,815 INFO L290 TraceCheckUtils]: 1: Hoare triple {99004#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,815 INFO L290 TraceCheckUtils]: 2: Hoare triple {99006#(= ~t13_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,815 INFO L290 TraceCheckUtils]: 3: Hoare triple {99006#(= ~t13_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,815 INFO L290 TraceCheckUtils]: 4: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,816 INFO L290 TraceCheckUtils]: 5: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,816 INFO L290 TraceCheckUtils]: 6: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,816 INFO L290 TraceCheckUtils]: 7: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,816 INFO L290 TraceCheckUtils]: 8: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,817 INFO L290 TraceCheckUtils]: 9: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,817 INFO L290 TraceCheckUtils]: 10: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,817 INFO L290 TraceCheckUtils]: 11: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,817 INFO L290 TraceCheckUtils]: 12: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,818 INFO L290 TraceCheckUtils]: 13: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,818 INFO L290 TraceCheckUtils]: 14: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,818 INFO L290 TraceCheckUtils]: 15: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,818 INFO L290 TraceCheckUtils]: 16: Hoare triple {99006#(= ~t13_i~0 1)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {99006#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,819 INFO L290 TraceCheckUtils]: 17: Hoare triple {99006#(= ~t13_i~0 1)} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {99005#false} is VALID [2022-02-21 04:23:36,819 INFO L290 TraceCheckUtils]: 18: Hoare triple {99005#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {99005#false} is VALID [2022-02-21 04:23:36,819 INFO L290 TraceCheckUtils]: 19: Hoare triple {99005#false} assume 0 == ~M_E~0;~M_E~0 := 1; {99005#false} is VALID [2022-02-21 04:23:36,819 INFO L290 TraceCheckUtils]: 20: Hoare triple {99005#false} assume !(0 == ~T1_E~0); {99005#false} is VALID [2022-02-21 04:23:36,819 INFO L290 TraceCheckUtils]: 21: Hoare triple {99005#false} assume !(0 == ~T2_E~0); {99005#false} is VALID [2022-02-21 04:23:36,819 INFO L290 TraceCheckUtils]: 22: Hoare triple {99005#false} assume !(0 == ~T3_E~0); {99005#false} is VALID [2022-02-21 04:23:36,819 INFO L290 TraceCheckUtils]: 23: Hoare triple {99005#false} assume !(0 == ~T4_E~0); {99005#false} is VALID [2022-02-21 04:23:36,819 INFO L290 TraceCheckUtils]: 24: Hoare triple {99005#false} assume !(0 == ~T5_E~0); {99005#false} is VALID [2022-02-21 04:23:36,819 INFO L290 TraceCheckUtils]: 25: Hoare triple {99005#false} assume !(0 == ~T6_E~0); {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 26: Hoare triple {99005#false} assume !(0 == ~T7_E~0); {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 27: Hoare triple {99005#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 28: Hoare triple {99005#false} assume !(0 == ~T9_E~0); {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 29: Hoare triple {99005#false} assume !(0 == ~T10_E~0); {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 30: Hoare triple {99005#false} assume !(0 == ~T11_E~0); {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 31: Hoare triple {99005#false} assume !(0 == ~T12_E~0); {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 32: Hoare triple {99005#false} assume !(0 == ~T13_E~0); {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 33: Hoare triple {99005#false} assume !(0 == ~E_M~0); {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 34: Hoare triple {99005#false} assume !(0 == ~E_1~0); {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 35: Hoare triple {99005#false} assume 0 == ~E_2~0;~E_2~0 := 1; {99005#false} is VALID [2022-02-21 04:23:36,820 INFO L290 TraceCheckUtils]: 36: Hoare triple {99005#false} assume !(0 == ~E_3~0); {99005#false} is VALID [2022-02-21 04:23:36,821 INFO L290 TraceCheckUtils]: 37: Hoare triple {99005#false} assume !(0 == ~E_4~0); {99005#false} is VALID [2022-02-21 04:23:36,821 INFO L290 TraceCheckUtils]: 38: Hoare triple {99005#false} assume !(0 == ~E_5~0); {99005#false} is VALID [2022-02-21 04:23:36,821 INFO L290 TraceCheckUtils]: 39: Hoare triple {99005#false} assume !(0 == ~E_6~0); {99005#false} is VALID [2022-02-21 04:23:36,821 INFO L290 TraceCheckUtils]: 40: Hoare triple {99005#false} assume !(0 == ~E_7~0); {99005#false} is VALID [2022-02-21 04:23:36,821 INFO L290 TraceCheckUtils]: 41: Hoare triple {99005#false} assume !(0 == ~E_8~0); {99005#false} is VALID [2022-02-21 04:23:36,821 INFO L290 TraceCheckUtils]: 42: Hoare triple {99005#false} assume !(0 == ~E_9~0); {99005#false} is VALID [2022-02-21 04:23:36,821 INFO L290 TraceCheckUtils]: 43: Hoare triple {99005#false} assume 0 == ~E_10~0;~E_10~0 := 1; {99005#false} is VALID [2022-02-21 04:23:36,821 INFO L290 TraceCheckUtils]: 44: Hoare triple {99005#false} assume !(0 == ~E_11~0); {99005#false} is VALID [2022-02-21 04:23:36,821 INFO L290 TraceCheckUtils]: 45: Hoare triple {99005#false} assume !(0 == ~E_12~0); {99005#false} is VALID [2022-02-21 04:23:36,821 INFO L290 TraceCheckUtils]: 46: Hoare triple {99005#false} assume !(0 == ~E_13~0); {99005#false} is VALID [2022-02-21 04:23:36,822 INFO L290 TraceCheckUtils]: 47: Hoare triple {99005#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {99005#false} is VALID [2022-02-21 04:23:36,822 INFO L290 TraceCheckUtils]: 48: Hoare triple {99005#false} assume !(1 == ~m_pc~0); {99005#false} is VALID [2022-02-21 04:23:36,822 INFO L290 TraceCheckUtils]: 49: Hoare triple {99005#false} is_master_triggered_~__retres1~0#1 := 0; {99005#false} is VALID [2022-02-21 04:23:36,822 INFO L290 TraceCheckUtils]: 50: Hoare triple {99005#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {99005#false} is VALID [2022-02-21 04:23:36,822 INFO L290 TraceCheckUtils]: 51: Hoare triple {99005#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {99005#false} is VALID [2022-02-21 04:23:36,822 INFO L290 TraceCheckUtils]: 52: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp~1#1); {99005#false} is VALID [2022-02-21 04:23:36,822 INFO L290 TraceCheckUtils]: 53: Hoare triple {99005#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {99005#false} is VALID [2022-02-21 04:23:36,822 INFO L290 TraceCheckUtils]: 54: Hoare triple {99005#false} assume 1 == ~t1_pc~0; {99005#false} is VALID [2022-02-21 04:23:36,822 INFO L290 TraceCheckUtils]: 55: Hoare triple {99005#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {99005#false} is VALID [2022-02-21 04:23:36,822 INFO L290 TraceCheckUtils]: 56: Hoare triple {99005#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 57: Hoare triple {99005#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 58: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___0~0#1); {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 59: Hoare triple {99005#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 60: Hoare triple {99005#false} assume 1 == ~t2_pc~0; {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 61: Hoare triple {99005#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 62: Hoare triple {99005#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 63: Hoare triple {99005#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 64: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___1~0#1); {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 65: Hoare triple {99005#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 66: Hoare triple {99005#false} assume !(1 == ~t3_pc~0); {99005#false} is VALID [2022-02-21 04:23:36,823 INFO L290 TraceCheckUtils]: 67: Hoare triple {99005#false} is_transmit3_triggered_~__retres1~3#1 := 0; {99005#false} is VALID [2022-02-21 04:23:36,824 INFO L290 TraceCheckUtils]: 68: Hoare triple {99005#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {99005#false} is VALID [2022-02-21 04:23:36,824 INFO L290 TraceCheckUtils]: 69: Hoare triple {99005#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {99005#false} is VALID [2022-02-21 04:23:36,824 INFO L290 TraceCheckUtils]: 70: Hoare triple {99005#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {99005#false} is VALID [2022-02-21 04:23:36,824 INFO L290 TraceCheckUtils]: 71: Hoare triple {99005#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {99005#false} is VALID [2022-02-21 04:23:36,824 INFO L290 TraceCheckUtils]: 72: Hoare triple {99005#false} assume 1 == ~t4_pc~0; {99005#false} is VALID [2022-02-21 04:23:36,824 INFO L290 TraceCheckUtils]: 73: Hoare triple {99005#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {99005#false} is VALID [2022-02-21 04:23:36,824 INFO L290 TraceCheckUtils]: 74: Hoare triple {99005#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {99005#false} is VALID [2022-02-21 04:23:36,824 INFO L290 TraceCheckUtils]: 75: Hoare triple {99005#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {99005#false} is VALID [2022-02-21 04:23:36,824 INFO L290 TraceCheckUtils]: 76: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___3~0#1); {99005#false} is VALID [2022-02-21 04:23:36,824 INFO L290 TraceCheckUtils]: 77: Hoare triple {99005#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 78: Hoare triple {99005#false} assume !(1 == ~t5_pc~0); {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 79: Hoare triple {99005#false} is_transmit5_triggered_~__retres1~5#1 := 0; {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 80: Hoare triple {99005#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 81: Hoare triple {99005#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 82: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___4~0#1); {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 83: Hoare triple {99005#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 84: Hoare triple {99005#false} assume 1 == ~t6_pc~0; {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 85: Hoare triple {99005#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 86: Hoare triple {99005#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 87: Hoare triple {99005#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {99005#false} is VALID [2022-02-21 04:23:36,825 INFO L290 TraceCheckUtils]: 88: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___5~0#1); {99005#false} is VALID [2022-02-21 04:23:36,826 INFO L290 TraceCheckUtils]: 89: Hoare triple {99005#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {99005#false} is VALID [2022-02-21 04:23:36,826 INFO L290 TraceCheckUtils]: 90: Hoare triple {99005#false} assume !(1 == ~t7_pc~0); {99005#false} is VALID [2022-02-21 04:23:36,826 INFO L290 TraceCheckUtils]: 91: Hoare triple {99005#false} is_transmit7_triggered_~__retres1~7#1 := 0; {99005#false} is VALID [2022-02-21 04:23:36,826 INFO L290 TraceCheckUtils]: 92: Hoare triple {99005#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {99005#false} is VALID [2022-02-21 04:23:36,826 INFO L290 TraceCheckUtils]: 93: Hoare triple {99005#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {99005#false} is VALID [2022-02-21 04:23:36,826 INFO L290 TraceCheckUtils]: 94: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___6~0#1); {99005#false} is VALID [2022-02-21 04:23:36,826 INFO L290 TraceCheckUtils]: 95: Hoare triple {99005#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {99005#false} is VALID [2022-02-21 04:23:36,826 INFO L290 TraceCheckUtils]: 96: Hoare triple {99005#false} assume 1 == ~t8_pc~0; {99005#false} is VALID [2022-02-21 04:23:36,826 INFO L290 TraceCheckUtils]: 97: Hoare triple {99005#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {99005#false} is VALID [2022-02-21 04:23:36,826 INFO L290 TraceCheckUtils]: 98: Hoare triple {99005#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {99005#false} is VALID [2022-02-21 04:23:36,827 INFO L290 TraceCheckUtils]: 99: Hoare triple {99005#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {99005#false} is VALID [2022-02-21 04:23:36,827 INFO L290 TraceCheckUtils]: 100: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___7~0#1); {99005#false} is VALID [2022-02-21 04:23:36,827 INFO L290 TraceCheckUtils]: 101: Hoare triple {99005#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {99005#false} is VALID [2022-02-21 04:23:36,827 INFO L290 TraceCheckUtils]: 102: Hoare triple {99005#false} assume 1 == ~t9_pc~0; {99005#false} is VALID [2022-02-21 04:23:36,827 INFO L290 TraceCheckUtils]: 103: Hoare triple {99005#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {99005#false} is VALID [2022-02-21 04:23:36,827 INFO L290 TraceCheckUtils]: 104: Hoare triple {99005#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {99005#false} is VALID [2022-02-21 04:23:36,827 INFO L290 TraceCheckUtils]: 105: Hoare triple {99005#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {99005#false} is VALID [2022-02-21 04:23:36,827 INFO L290 TraceCheckUtils]: 106: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___8~0#1); {99005#false} is VALID [2022-02-21 04:23:36,827 INFO L290 TraceCheckUtils]: 107: Hoare triple {99005#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {99005#false} is VALID [2022-02-21 04:23:36,827 INFO L290 TraceCheckUtils]: 108: Hoare triple {99005#false} assume !(1 == ~t10_pc~0); {99005#false} is VALID [2022-02-21 04:23:36,828 INFO L290 TraceCheckUtils]: 109: Hoare triple {99005#false} is_transmit10_triggered_~__retres1~10#1 := 0; {99005#false} is VALID [2022-02-21 04:23:36,828 INFO L290 TraceCheckUtils]: 110: Hoare triple {99005#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {99005#false} is VALID [2022-02-21 04:23:36,828 INFO L290 TraceCheckUtils]: 111: Hoare triple {99005#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {99005#false} is VALID [2022-02-21 04:23:36,828 INFO L290 TraceCheckUtils]: 112: Hoare triple {99005#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {99005#false} is VALID [2022-02-21 04:23:36,828 INFO L290 TraceCheckUtils]: 113: Hoare triple {99005#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {99005#false} is VALID [2022-02-21 04:23:36,828 INFO L290 TraceCheckUtils]: 114: Hoare triple {99005#false} assume 1 == ~t11_pc~0; {99005#false} is VALID [2022-02-21 04:23:36,828 INFO L290 TraceCheckUtils]: 115: Hoare triple {99005#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {99005#false} is VALID [2022-02-21 04:23:36,828 INFO L290 TraceCheckUtils]: 116: Hoare triple {99005#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {99005#false} is VALID [2022-02-21 04:23:36,828 INFO L290 TraceCheckUtils]: 117: Hoare triple {99005#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {99005#false} is VALID [2022-02-21 04:23:36,828 INFO L290 TraceCheckUtils]: 118: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___10~0#1); {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 119: Hoare triple {99005#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 120: Hoare triple {99005#false} assume !(1 == ~t12_pc~0); {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 121: Hoare triple {99005#false} is_transmit12_triggered_~__retres1~12#1 := 0; {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 122: Hoare triple {99005#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 123: Hoare triple {99005#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 124: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___11~0#1); {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 125: Hoare triple {99005#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 126: Hoare triple {99005#false} assume 1 == ~t13_pc~0; {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 127: Hoare triple {99005#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 128: Hoare triple {99005#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {99005#false} is VALID [2022-02-21 04:23:36,829 INFO L290 TraceCheckUtils]: 129: Hoare triple {99005#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {99005#false} is VALID [2022-02-21 04:23:36,830 INFO L290 TraceCheckUtils]: 130: Hoare triple {99005#false} assume !(0 != activate_threads_~tmp___12~0#1); {99005#false} is VALID [2022-02-21 04:23:36,830 INFO L290 TraceCheckUtils]: 131: Hoare triple {99005#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {99005#false} is VALID [2022-02-21 04:23:36,830 INFO L290 TraceCheckUtils]: 132: Hoare triple {99005#false} assume !(1 == ~M_E~0); {99005#false} is VALID [2022-02-21 04:23:36,830 INFO L290 TraceCheckUtils]: 133: Hoare triple {99005#false} assume !(1 == ~T1_E~0); {99005#false} is VALID [2022-02-21 04:23:36,830 INFO L290 TraceCheckUtils]: 134: Hoare triple {99005#false} assume !(1 == ~T2_E~0); {99005#false} is VALID [2022-02-21 04:23:36,830 INFO L290 TraceCheckUtils]: 135: Hoare triple {99005#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {99005#false} is VALID [2022-02-21 04:23:36,830 INFO L290 TraceCheckUtils]: 136: Hoare triple {99005#false} assume !(1 == ~T4_E~0); {99005#false} is VALID [2022-02-21 04:23:36,830 INFO L290 TraceCheckUtils]: 137: Hoare triple {99005#false} assume !(1 == ~T5_E~0); {99005#false} is VALID [2022-02-21 04:23:36,830 INFO L290 TraceCheckUtils]: 138: Hoare triple {99005#false} assume !(1 == ~T6_E~0); {99005#false} is VALID [2022-02-21 04:23:36,830 INFO L290 TraceCheckUtils]: 139: Hoare triple {99005#false} assume !(1 == ~T7_E~0); {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 140: Hoare triple {99005#false} assume !(1 == ~T8_E~0); {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 141: Hoare triple {99005#false} assume !(1 == ~T9_E~0); {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 142: Hoare triple {99005#false} assume !(1 == ~T10_E~0); {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 143: Hoare triple {99005#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 144: Hoare triple {99005#false} assume !(1 == ~T12_E~0); {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 145: Hoare triple {99005#false} assume !(1 == ~T13_E~0); {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 146: Hoare triple {99005#false} assume !(1 == ~E_M~0); {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 147: Hoare triple {99005#false} assume !(1 == ~E_1~0); {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 148: Hoare triple {99005#false} assume !(1 == ~E_2~0); {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 149: Hoare triple {99005#false} assume !(1 == ~E_3~0); {99005#false} is VALID [2022-02-21 04:23:36,831 INFO L290 TraceCheckUtils]: 150: Hoare triple {99005#false} assume !(1 == ~E_4~0); {99005#false} is VALID [2022-02-21 04:23:36,832 INFO L290 TraceCheckUtils]: 151: Hoare triple {99005#false} assume 1 == ~E_5~0;~E_5~0 := 2; {99005#false} is VALID [2022-02-21 04:23:36,832 INFO L290 TraceCheckUtils]: 152: Hoare triple {99005#false} assume !(1 == ~E_6~0); {99005#false} is VALID [2022-02-21 04:23:36,832 INFO L290 TraceCheckUtils]: 153: Hoare triple {99005#false} assume !(1 == ~E_7~0); {99005#false} is VALID [2022-02-21 04:23:36,832 INFO L290 TraceCheckUtils]: 154: Hoare triple {99005#false} assume !(1 == ~E_8~0); {99005#false} is VALID [2022-02-21 04:23:36,832 INFO L290 TraceCheckUtils]: 155: Hoare triple {99005#false} assume !(1 == ~E_9~0); {99005#false} is VALID [2022-02-21 04:23:36,832 INFO L290 TraceCheckUtils]: 156: Hoare triple {99005#false} assume !(1 == ~E_10~0); {99005#false} is VALID [2022-02-21 04:23:36,832 INFO L290 TraceCheckUtils]: 157: Hoare triple {99005#false} assume !(1 == ~E_11~0); {99005#false} is VALID [2022-02-21 04:23:36,832 INFO L290 TraceCheckUtils]: 158: Hoare triple {99005#false} assume !(1 == ~E_12~0); {99005#false} is VALID [2022-02-21 04:23:36,832 INFO L290 TraceCheckUtils]: 159: Hoare triple {99005#false} assume 1 == ~E_13~0;~E_13~0 := 2; {99005#false} is VALID [2022-02-21 04:23:36,832 INFO L290 TraceCheckUtils]: 160: Hoare triple {99005#false} assume { :end_inline_reset_delta_events } true; {99005#false} is VALID [2022-02-21 04:23:36,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:36,833 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:36,833 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [993074323] [2022-02-21 04:23:36,833 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [993074323] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:36,833 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:36,833 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:36,833 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [947454769] [2022-02-21 04:23:36,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:36,834 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:36,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:36,834 INFO L85 PathProgramCache]: Analyzing trace with hash 1322591597, now seen corresponding path program 2 times [2022-02-21 04:23:36,834 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:36,835 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158664541] [2022-02-21 04:23:36,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:36,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:36,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:36,860 INFO L290 TraceCheckUtils]: 0: Hoare triple {99007#true} assume !false; {99007#true} is VALID [2022-02-21 04:23:36,860 INFO L290 TraceCheckUtils]: 1: Hoare triple {99007#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {99007#true} is VALID [2022-02-21 04:23:36,860 INFO L290 TraceCheckUtils]: 2: Hoare triple {99007#true} assume !false; {99007#true} is VALID [2022-02-21 04:23:36,860 INFO L290 TraceCheckUtils]: 3: Hoare triple {99007#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {99007#true} is VALID [2022-02-21 04:23:36,860 INFO L290 TraceCheckUtils]: 4: Hoare triple {99007#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {99007#true} is VALID [2022-02-21 04:23:36,860 INFO L290 TraceCheckUtils]: 5: Hoare triple {99007#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {99007#true} is VALID [2022-02-21 04:23:36,860 INFO L290 TraceCheckUtils]: 6: Hoare triple {99007#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {99007#true} is VALID [2022-02-21 04:23:36,860 INFO L290 TraceCheckUtils]: 7: Hoare triple {99007#true} assume !(0 != eval_~tmp~0#1); {99007#true} is VALID [2022-02-21 04:23:36,861 INFO L290 TraceCheckUtils]: 8: Hoare triple {99007#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {99007#true} is VALID [2022-02-21 04:23:36,861 INFO L290 TraceCheckUtils]: 9: Hoare triple {99007#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {99007#true} is VALID [2022-02-21 04:23:36,861 INFO L290 TraceCheckUtils]: 10: Hoare triple {99007#true} assume 0 == ~M_E~0;~M_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,861 INFO L290 TraceCheckUtils]: 11: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,861 INFO L290 TraceCheckUtils]: 12: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,862 INFO L290 TraceCheckUtils]: 13: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,862 INFO L290 TraceCheckUtils]: 14: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,862 INFO L290 TraceCheckUtils]: 15: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,863 INFO L290 TraceCheckUtils]: 16: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,863 INFO L290 TraceCheckUtils]: 17: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,863 INFO L290 TraceCheckUtils]: 18: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,863 INFO L290 TraceCheckUtils]: 19: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,864 INFO L290 TraceCheckUtils]: 20: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,864 INFO L290 TraceCheckUtils]: 21: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,864 INFO L290 TraceCheckUtils]: 22: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,864 INFO L290 TraceCheckUtils]: 23: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,865 INFO L290 TraceCheckUtils]: 24: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,865 INFO L290 TraceCheckUtils]: 25: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,865 INFO L290 TraceCheckUtils]: 26: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,865 INFO L290 TraceCheckUtils]: 27: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,866 INFO L290 TraceCheckUtils]: 28: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,866 INFO L290 TraceCheckUtils]: 29: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,866 INFO L290 TraceCheckUtils]: 30: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,866 INFO L290 TraceCheckUtils]: 31: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,867 INFO L290 TraceCheckUtils]: 32: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,867 INFO L290 TraceCheckUtils]: 33: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,867 INFO L290 TraceCheckUtils]: 34: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,868 INFO L290 TraceCheckUtils]: 35: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,868 INFO L290 TraceCheckUtils]: 36: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,868 INFO L290 TraceCheckUtils]: 37: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,868 INFO L290 TraceCheckUtils]: 38: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,869 INFO L290 TraceCheckUtils]: 39: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,869 INFO L290 TraceCheckUtils]: 40: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,869 INFO L290 TraceCheckUtils]: 41: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,870 INFO L290 TraceCheckUtils]: 42: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,870 INFO L290 TraceCheckUtils]: 43: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,870 INFO L290 TraceCheckUtils]: 44: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,870 INFO L290 TraceCheckUtils]: 45: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,871 INFO L290 TraceCheckUtils]: 46: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,871 INFO L290 TraceCheckUtils]: 47: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,871 INFO L290 TraceCheckUtils]: 48: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,871 INFO L290 TraceCheckUtils]: 49: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,872 INFO L290 TraceCheckUtils]: 50: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,872 INFO L290 TraceCheckUtils]: 51: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,872 INFO L290 TraceCheckUtils]: 52: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,872 INFO L290 TraceCheckUtils]: 53: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,873 INFO L290 TraceCheckUtils]: 54: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,873 INFO L290 TraceCheckUtils]: 55: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,873 INFO L290 TraceCheckUtils]: 56: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,874 INFO L290 TraceCheckUtils]: 57: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,874 INFO L290 TraceCheckUtils]: 58: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,874 INFO L290 TraceCheckUtils]: 59: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,874 INFO L290 TraceCheckUtils]: 60: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,875 INFO L290 TraceCheckUtils]: 61: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,875 INFO L290 TraceCheckUtils]: 62: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,875 INFO L290 TraceCheckUtils]: 63: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,875 INFO L290 TraceCheckUtils]: 64: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,876 INFO L290 TraceCheckUtils]: 65: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,876 INFO L290 TraceCheckUtils]: 66: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,876 INFO L290 TraceCheckUtils]: 67: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,876 INFO L290 TraceCheckUtils]: 68: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,877 INFO L290 TraceCheckUtils]: 69: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,877 INFO L290 TraceCheckUtils]: 70: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,877 INFO L290 TraceCheckUtils]: 71: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,877 INFO L290 TraceCheckUtils]: 72: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,878 INFO L290 TraceCheckUtils]: 73: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,878 INFO L290 TraceCheckUtils]: 74: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,878 INFO L290 TraceCheckUtils]: 75: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,878 INFO L290 TraceCheckUtils]: 76: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,879 INFO L290 TraceCheckUtils]: 77: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,879 INFO L290 TraceCheckUtils]: 78: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,879 INFO L290 TraceCheckUtils]: 79: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,879 INFO L290 TraceCheckUtils]: 80: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,880 INFO L290 TraceCheckUtils]: 81: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,880 INFO L290 TraceCheckUtils]: 82: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,880 INFO L290 TraceCheckUtils]: 83: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,880 INFO L290 TraceCheckUtils]: 84: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,881 INFO L290 TraceCheckUtils]: 85: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,881 INFO L290 TraceCheckUtils]: 86: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,881 INFO L290 TraceCheckUtils]: 87: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,882 INFO L290 TraceCheckUtils]: 88: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,882 INFO L290 TraceCheckUtils]: 89: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,882 INFO L290 TraceCheckUtils]: 90: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,882 INFO L290 TraceCheckUtils]: 91: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,883 INFO L290 TraceCheckUtils]: 92: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,883 INFO L290 TraceCheckUtils]: 93: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,883 INFO L290 TraceCheckUtils]: 94: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,883 INFO L290 TraceCheckUtils]: 95: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,884 INFO L290 TraceCheckUtils]: 96: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,884 INFO L290 TraceCheckUtils]: 97: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,884 INFO L290 TraceCheckUtils]: 98: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,884 INFO L290 TraceCheckUtils]: 99: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,885 INFO L290 TraceCheckUtils]: 100: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,885 INFO L290 TraceCheckUtils]: 101: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,885 INFO L290 TraceCheckUtils]: 102: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,885 INFO L290 TraceCheckUtils]: 103: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,886 INFO L290 TraceCheckUtils]: 104: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,886 INFO L290 TraceCheckUtils]: 105: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,886 INFO L290 TraceCheckUtils]: 106: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,887 INFO L290 TraceCheckUtils]: 107: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,887 INFO L290 TraceCheckUtils]: 108: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,887 INFO L290 TraceCheckUtils]: 109: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,887 INFO L290 TraceCheckUtils]: 110: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,888 INFO L290 TraceCheckUtils]: 111: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,888 INFO L290 TraceCheckUtils]: 112: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,888 INFO L290 TraceCheckUtils]: 113: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,888 INFO L290 TraceCheckUtils]: 114: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,889 INFO L290 TraceCheckUtils]: 115: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,889 INFO L290 TraceCheckUtils]: 116: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,889 INFO L290 TraceCheckUtils]: 117: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,889 INFO L290 TraceCheckUtils]: 118: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,890 INFO L290 TraceCheckUtils]: 119: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,890 INFO L290 TraceCheckUtils]: 120: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,890 INFO L290 TraceCheckUtils]: 121: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,890 INFO L290 TraceCheckUtils]: 122: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {99009#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:36,891 INFO L290 TraceCheckUtils]: 123: Hoare triple {99009#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {99008#false} is VALID [2022-02-21 04:23:36,891 INFO L290 TraceCheckUtils]: 124: Hoare triple {99008#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,891 INFO L290 TraceCheckUtils]: 125: Hoare triple {99008#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,891 INFO L290 TraceCheckUtils]: 126: Hoare triple {99008#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,891 INFO L290 TraceCheckUtils]: 127: Hoare triple {99008#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,891 INFO L290 TraceCheckUtils]: 128: Hoare triple {99008#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,891 INFO L290 TraceCheckUtils]: 129: Hoare triple {99008#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,891 INFO L290 TraceCheckUtils]: 130: Hoare triple {99008#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,891 INFO L290 TraceCheckUtils]: 131: Hoare triple {99008#false} assume !(1 == ~T8_E~0); {99008#false} is VALID [2022-02-21 04:23:36,892 INFO L290 TraceCheckUtils]: 132: Hoare triple {99008#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,892 INFO L290 TraceCheckUtils]: 133: Hoare triple {99008#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,892 INFO L290 TraceCheckUtils]: 134: Hoare triple {99008#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,892 INFO L290 TraceCheckUtils]: 135: Hoare triple {99008#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,892 INFO L290 TraceCheckUtils]: 136: Hoare triple {99008#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,892 INFO L290 TraceCheckUtils]: 137: Hoare triple {99008#false} assume 1 == ~E_M~0;~E_M~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,892 INFO L290 TraceCheckUtils]: 138: Hoare triple {99008#false} assume 1 == ~E_1~0;~E_1~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,892 INFO L290 TraceCheckUtils]: 139: Hoare triple {99008#false} assume !(1 == ~E_2~0); {99008#false} is VALID [2022-02-21 04:23:36,892 INFO L290 TraceCheckUtils]: 140: Hoare triple {99008#false} assume 1 == ~E_3~0;~E_3~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,892 INFO L290 TraceCheckUtils]: 141: Hoare triple {99008#false} assume 1 == ~E_4~0;~E_4~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 142: Hoare triple {99008#false} assume 1 == ~E_5~0;~E_5~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 143: Hoare triple {99008#false} assume 1 == ~E_6~0;~E_6~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 144: Hoare triple {99008#false} assume 1 == ~E_7~0;~E_7~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 145: Hoare triple {99008#false} assume 1 == ~E_8~0;~E_8~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 146: Hoare triple {99008#false} assume 1 == ~E_9~0;~E_9~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 147: Hoare triple {99008#false} assume !(1 == ~E_10~0); {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 148: Hoare triple {99008#false} assume 1 == ~E_11~0;~E_11~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 149: Hoare triple {99008#false} assume 1 == ~E_12~0;~E_12~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 150: Hoare triple {99008#false} assume 1 == ~E_13~0;~E_13~0 := 2; {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 151: Hoare triple {99008#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {99008#false} is VALID [2022-02-21 04:23:36,893 INFO L290 TraceCheckUtils]: 152: Hoare triple {99008#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {99008#false} is VALID [2022-02-21 04:23:36,894 INFO L290 TraceCheckUtils]: 153: Hoare triple {99008#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {99008#false} is VALID [2022-02-21 04:23:36,894 INFO L290 TraceCheckUtils]: 154: Hoare triple {99008#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {99008#false} is VALID [2022-02-21 04:23:36,894 INFO L290 TraceCheckUtils]: 155: Hoare triple {99008#false} assume !(0 == start_simulation_~tmp~3#1); {99008#false} is VALID [2022-02-21 04:23:36,894 INFO L290 TraceCheckUtils]: 156: Hoare triple {99008#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {99008#false} is VALID [2022-02-21 04:23:36,894 INFO L290 TraceCheckUtils]: 157: Hoare triple {99008#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {99008#false} is VALID [2022-02-21 04:23:36,894 INFO L290 TraceCheckUtils]: 158: Hoare triple {99008#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {99008#false} is VALID [2022-02-21 04:23:36,894 INFO L290 TraceCheckUtils]: 159: Hoare triple {99008#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {99008#false} is VALID [2022-02-21 04:23:36,894 INFO L290 TraceCheckUtils]: 160: Hoare triple {99008#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {99008#false} is VALID [2022-02-21 04:23:36,894 INFO L290 TraceCheckUtils]: 161: Hoare triple {99008#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {99008#false} is VALID [2022-02-21 04:23:36,894 INFO L290 TraceCheckUtils]: 162: Hoare triple {99008#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {99008#false} is VALID [2022-02-21 04:23:36,895 INFO L290 TraceCheckUtils]: 163: Hoare triple {99008#false} assume !(0 != start_simulation_~tmp___0~1#1); {99008#false} is VALID [2022-02-21 04:23:36,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:36,895 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:36,895 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158664541] [2022-02-21 04:23:36,895 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158664541] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:36,895 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:36,896 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:36,896 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [46419130] [2022-02-21 04:23:36,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:36,896 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:36,896 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:36,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:36,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:36,897 INFO L87 Difference]: Start difference. First operand 2018 states and 2976 transitions. cyclomatic complexity: 959 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:38,432 INFO L93 Difference]: Finished difference Result 2018 states and 2975 transitions. [2022-02-21 04:23:38,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:38,433 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,521 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:38,521 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2975 transitions. [2022-02-21 04:23:38,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:38,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2975 transitions. [2022-02-21 04:23:38,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-02-21 04:23:38,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-02-21 04:23:38,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2975 transitions. [2022-02-21 04:23:38,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:38,770 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2022-02-21 04:23:38,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2975 transitions. [2022-02-21 04:23:38,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-02-21 04:23:38,786 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:38,788 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2018 states and 2975 transitions. Second operand has 2018 states, 2018 states have (on average 1.4742319127849355) internal successors, (2975), 2017 states have internal predecessors, (2975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,789 INFO L74 IsIncluded]: Start isIncluded. First operand 2018 states and 2975 transitions. Second operand has 2018 states, 2018 states have (on average 1.4742319127849355) internal successors, (2975), 2017 states have internal predecessors, (2975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,790 INFO L87 Difference]: Start difference. First operand 2018 states and 2975 transitions. Second operand has 2018 states, 2018 states have (on average 1.4742319127849355) internal successors, (2975), 2017 states have internal predecessors, (2975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:38,893 INFO L93 Difference]: Finished difference Result 2018 states and 2975 transitions. [2022-02-21 04:23:38,893 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2975 transitions. [2022-02-21 04:23:38,895 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:38,895 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:38,898 INFO L74 IsIncluded]: Start isIncluded. First operand has 2018 states, 2018 states have (on average 1.4742319127849355) internal successors, (2975), 2017 states have internal predecessors, (2975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2975 transitions. [2022-02-21 04:23:38,899 INFO L87 Difference]: Start difference. First operand has 2018 states, 2018 states have (on average 1.4742319127849355) internal successors, (2975), 2017 states have internal predecessors, (2975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2018 states and 2975 transitions. [2022-02-21 04:23:39,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:39,002 INFO L93 Difference]: Finished difference Result 2018 states and 2975 transitions. [2022-02-21 04:23:39,002 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states and 2975 transitions. [2022-02-21 04:23:39,004 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:39,004 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:39,004 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:39,004 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:39,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4742319127849355) internal successors, (2975), 2017 states have internal predecessors, (2975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:39,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2975 transitions. [2022-02-21 04:23:39,109 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2022-02-21 04:23:39,109 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2022-02-21 04:23:39,109 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:23:39,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2975 transitions. [2022-02-21 04:23:39,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-02-21 04:23:39,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:39,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:39,117 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:39,117 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:39,117 INFO L791 eck$LassoCheckResult]: Stem: 101943#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 101944#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 102980#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 102435#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 102436#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 101925#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 101926#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 101992#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101993#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102431#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 102432#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 101958#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 101777#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 101778#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 102222#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 102223#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 102098#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 102099#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 101748#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 101749#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 102972#L1279-2 assume !(0 == ~T1_E~0); 101371#L1284-1 assume !(0 == ~T2_E~0); 101372#L1289-1 assume !(0 == ~T3_E~0); 102095#L1294-1 assume !(0 == ~T4_E~0); 102096#L1299-1 assume !(0 == ~T5_E~0); 102107#L1304-1 assume !(0 == ~T6_E~0); 103038#L1309-1 assume !(0 == ~T7_E~0); 103039#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 101301#L1319-1 assume !(0 == ~T9_E~0); 101302#L1324-1 assume !(0 == ~T10_E~0); 101474#L1329-1 assume !(0 == ~T11_E~0); 101475#L1334-1 assume !(0 == ~T12_E~0); 102879#L1339-1 assume !(0 == ~T13_E~0); 102960#L1344-1 assume !(0 == ~E_M~0); 102961#L1349-1 assume !(0 == ~E_1~0); 102282#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 102283#L1359-1 assume !(0 == ~E_3~0); 102712#L1364-1 assume !(0 == ~E_4~0); 101603#L1369-1 assume !(0 == ~E_5~0); 101604#L1374-1 assume !(0 == ~E_6~0); 102287#L1379-1 assume !(0 == ~E_7~0); 102288#L1384-1 assume !(0 == ~E_8~0); 102365#L1389-1 assume !(0 == ~E_9~0); 102898#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 102899#L1399-1 assume !(0 == ~E_11~0); 103002#L1404-1 assume !(0 == ~E_12~0); 101696#L1409-1 assume !(0 == ~E_13~0); 101697#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102994#L628 assume !(1 == ~m_pc~0); 101600#L628-2 is_master_triggered_~__retres1~0#1 := 0; 101599#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102363#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 102364#L1591 assume !(0 != activate_threads_~tmp~1#1); 103007#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102151#L647 assume 1 == ~t1_pc~0; 101520#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 101521#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101792#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101793#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 102947#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102948#L666 assume 1 == ~t2_pc~0; 101368#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 101369#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101535#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102964#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 102483#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102484#L685 assume !(1 == ~t3_pc~0); 102589#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102588#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102211#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102212#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 102333#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101819#L704 assume 1 == ~t4_pc~0; 101820#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 102344#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102345#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 102985#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 102204#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102205#L723 assume !(1 == ~t5_pc~0); 102327#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 102563#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102707#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 102462#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 102463#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101585#L742 assume 1 == ~t6_pc~0; 101586#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 101734#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101735#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 101270#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 101271#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101662#L761 assume !(1 == ~t7_pc~0); 101663#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 101531#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101532#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 102334#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 102335#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 101295#L780 assume 1 == ~t8_pc~0; 101296#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 101571#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101572#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 102295#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 102296#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102415#L799 assume 1 == ~t9_pc~0; 102527#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 101298#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 101299#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 102427#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 102634#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 102445#L818 assume !(1 == ~t10_pc~0); 101079#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 101080#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 102520#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 102449#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 102450#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 102490#L837 assume 1 == ~t11_pc~0; 102491#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 102325#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 102728#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 102408#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 102409#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 102160#L856 assume !(1 == ~t12_pc~0); 102161#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 102814#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 102815#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 102795#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 102796#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 102975#L875 assume 1 == ~t13_pc~0; 102105#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 101737#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 101738#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 101677#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 101678#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102517#L1427 assume !(1 == ~M_E~0); 102501#L1427-2 assume !(1 == ~T1_E~0); 101649#L1432-1 assume !(1 == ~T2_E~0); 101650#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102718#L1442-1 assume !(1 == ~T4_E~0); 102719#L1447-1 assume !(1 == ~T5_E~0); 102574#L1452-1 assume !(1 == ~T6_E~0); 101214#L1457-1 assume !(1 == ~T7_E~0); 101215#L1462-1 assume !(1 == ~T8_E~0); 102745#L1467-1 assume !(1 == ~T9_E~0); 102763#L1472-1 assume !(1 == ~T10_E~0); 102764#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 102515#L1482-1 assume !(1 == ~T12_E~0); 102516#L1487-1 assume !(1 == ~T13_E~0); 101545#L1492-1 assume !(1 == ~E_M~0); 101546#L1497-1 assume !(1 == ~E_1~0); 101907#L1502-1 assume !(1 == ~E_2~0); 101908#L1507-1 assume !(1 == ~E_3~0); 101423#L1512-1 assume !(1 == ~E_4~0); 101424#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 102834#L1522-1 assume !(1 == ~E_6~0); 102148#L1527-1 assume !(1 == ~E_7~0); 102149#L1532-1 assume !(1 == ~E_8~0); 103022#L1537-1 assume !(1 == ~E_9~0); 102351#L1542-1 assume !(1 == ~E_10~0); 102182#L1547-1 assume !(1 == ~E_11~0); 102183#L1552-1 assume !(1 == ~E_12~0); 101118#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 101119#L1562-1 assume { :end_inline_reset_delta_events } true; 101725#L1928-2 [2022-02-21 04:23:39,118 INFO L793 eck$LassoCheckResult]: Loop: 101725#L1928-2 assume !false; 102216#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 101379#L1254 assume !false; 101966#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 101453#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101454#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 101651#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 102822#L1067 assume !(0 != eval_~tmp~0#1); 101892#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 101469#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 101470#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 101929#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 101911#L1284-3 assume !(0 == ~T2_E~0); 101912#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 101890#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 101891#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 102278#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 102279#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 101788#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 101789#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 102785#L1324-3 assume !(0 == ~T10_E~0); 101420#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 101421#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 102188#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 102189#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 102487#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 101769#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 101770#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 102498#L1364-3 assume !(0 == ~E_4~0); 103020#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102916#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 101549#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 101550#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 101767#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 101768#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 102058#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 102926#L1404-3 assume !(0 == ~E_12~0); 102890#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 102891#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102377#L628-45 assume 1 == ~m_pc~0; 102055#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 102057#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101414#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 101415#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 101803#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102526#L647-45 assume 1 == ~t1_pc~0; 101365#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 101366#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102294#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101479#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 101480#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101691#L666-45 assume 1 == ~t2_pc~0; 101693#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 102173#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102735#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102650#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 102644#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101229#L685-45 assume !(1 == ~t3_pc~0); 101231#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 102289#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102963#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102832#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 102833#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102973#L704-45 assume 1 == ~t4_pc~0; 102852#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 101096#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101955#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 102298#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103045#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102410#L723-45 assume !(1 == ~t5_pc~0); 102411#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 102900#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102002#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 101779#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 101780#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102804#L742-45 assume 1 == ~t6_pc~0; 102805#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 102027#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102496#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 102532#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 102533#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 102621#L761-45 assume 1 == ~t7_pc~0; 102623#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 102020#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102021#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 101427#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 101428#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102894#L780-45 assume 1 == ~t8_pc~0; 101805#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 101439#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101440#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 103021#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101409#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 101410#L799-45 assume 1 == ~t9_pc~0; 102186#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 101631#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 102946#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 102575#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 102576#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 101347#L818-45 assume !(1 == ~t10_pc~0); 101349#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 101466#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 102549#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 101953#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101954#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 102669#L837-45 assume !(1 == ~t11_pc~0); 101884#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 101885#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 102022#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 102687#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 101485#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 101486#L856-45 assume 1 == ~t12_pc~0; 102971#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 101488#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 101429#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 101430#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 102292#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 102293#L875-45 assume 1 == ~t13_pc~0; 102263#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 102264#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 102326#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 102938#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 102939#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102878#L1427-3 assume !(1 == ~M_E~0); 102089#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 102090#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 102628#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102280#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 102281#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101137#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101138#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 102820#L1462-3 assume !(1 == ~T8_E~0); 102821#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 102684#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 102685#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 101388#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 101389#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 101530#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 101703#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 101704#L1502-3 assume !(1 == ~E_2~0); 102652#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 102783#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 101741#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101433#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 101434#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 101398#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101399#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 102499#L1542-3 assume !(1 == ~E_10~0); 102637#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 102266#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 102267#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 101609#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 101610#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101029#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 101794#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 101795#L1947 assume !(0 == start_simulation_~tmp~3#1); 102400#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 102605#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101666#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 102998#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 102922#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 102752#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102511#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 102512#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 101725#L1928-2 [2022-02-21 04:23:39,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:39,119 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2022-02-21 04:23:39,119 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:39,120 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307200605] [2022-02-21 04:23:39,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:39,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:39,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:39,188 INFO L290 TraceCheckUtils]: 0: Hoare triple {107085#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,188 INFO L290 TraceCheckUtils]: 1: Hoare triple {107087#(= ~M_E~0 2)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,188 INFO L290 TraceCheckUtils]: 2: Hoare triple {107087#(= ~M_E~0 2)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,189 INFO L290 TraceCheckUtils]: 3: Hoare triple {107087#(= ~M_E~0 2)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,189 INFO L290 TraceCheckUtils]: 4: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~m_i~0;~m_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,189 INFO L290 TraceCheckUtils]: 5: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,190 INFO L290 TraceCheckUtils]: 6: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,190 INFO L290 TraceCheckUtils]: 7: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,190 INFO L290 TraceCheckUtils]: 8: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,190 INFO L290 TraceCheckUtils]: 9: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,191 INFO L290 TraceCheckUtils]: 10: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,191 INFO L290 TraceCheckUtils]: 11: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,191 INFO L290 TraceCheckUtils]: 12: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,192 INFO L290 TraceCheckUtils]: 13: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,192 INFO L290 TraceCheckUtils]: 14: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,192 INFO L290 TraceCheckUtils]: 15: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,193 INFO L290 TraceCheckUtils]: 16: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,193 INFO L290 TraceCheckUtils]: 17: Hoare triple {107087#(= ~M_E~0 2)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,193 INFO L290 TraceCheckUtils]: 18: Hoare triple {107087#(= ~M_E~0 2)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {107087#(= ~M_E~0 2)} is VALID [2022-02-21 04:23:39,193 INFO L290 TraceCheckUtils]: 19: Hoare triple {107087#(= ~M_E~0 2)} assume 0 == ~M_E~0;~M_E~0 := 1; {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 20: Hoare triple {107086#false} assume !(0 == ~T1_E~0); {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 21: Hoare triple {107086#false} assume !(0 == ~T2_E~0); {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 22: Hoare triple {107086#false} assume !(0 == ~T3_E~0); {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 23: Hoare triple {107086#false} assume !(0 == ~T4_E~0); {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 24: Hoare triple {107086#false} assume !(0 == ~T5_E~0); {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 25: Hoare triple {107086#false} assume !(0 == ~T6_E~0); {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 26: Hoare triple {107086#false} assume !(0 == ~T7_E~0); {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 27: Hoare triple {107086#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 28: Hoare triple {107086#false} assume !(0 == ~T9_E~0); {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 29: Hoare triple {107086#false} assume !(0 == ~T10_E~0); {107086#false} is VALID [2022-02-21 04:23:39,194 INFO L290 TraceCheckUtils]: 30: Hoare triple {107086#false} assume !(0 == ~T11_E~0); {107086#false} is VALID [2022-02-21 04:23:39,195 INFO L290 TraceCheckUtils]: 31: Hoare triple {107086#false} assume !(0 == ~T12_E~0); {107086#false} is VALID [2022-02-21 04:23:39,195 INFO L290 TraceCheckUtils]: 32: Hoare triple {107086#false} assume !(0 == ~T13_E~0); {107086#false} is VALID [2022-02-21 04:23:39,195 INFO L290 TraceCheckUtils]: 33: Hoare triple {107086#false} assume !(0 == ~E_M~0); {107086#false} is VALID [2022-02-21 04:23:39,195 INFO L290 TraceCheckUtils]: 34: Hoare triple {107086#false} assume !(0 == ~E_1~0); {107086#false} is VALID [2022-02-21 04:23:39,195 INFO L290 TraceCheckUtils]: 35: Hoare triple {107086#false} assume 0 == ~E_2~0;~E_2~0 := 1; {107086#false} is VALID [2022-02-21 04:23:39,195 INFO L290 TraceCheckUtils]: 36: Hoare triple {107086#false} assume !(0 == ~E_3~0); {107086#false} is VALID [2022-02-21 04:23:39,195 INFO L290 TraceCheckUtils]: 37: Hoare triple {107086#false} assume !(0 == ~E_4~0); {107086#false} is VALID [2022-02-21 04:23:39,195 INFO L290 TraceCheckUtils]: 38: Hoare triple {107086#false} assume !(0 == ~E_5~0); {107086#false} is VALID [2022-02-21 04:23:39,195 INFO L290 TraceCheckUtils]: 39: Hoare triple {107086#false} assume !(0 == ~E_6~0); {107086#false} is VALID [2022-02-21 04:23:39,195 INFO L290 TraceCheckUtils]: 40: Hoare triple {107086#false} assume !(0 == ~E_7~0); {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 41: Hoare triple {107086#false} assume !(0 == ~E_8~0); {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 42: Hoare triple {107086#false} assume !(0 == ~E_9~0); {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 43: Hoare triple {107086#false} assume 0 == ~E_10~0;~E_10~0 := 1; {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 44: Hoare triple {107086#false} assume !(0 == ~E_11~0); {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 45: Hoare triple {107086#false} assume !(0 == ~E_12~0); {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 46: Hoare triple {107086#false} assume !(0 == ~E_13~0); {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 47: Hoare triple {107086#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 48: Hoare triple {107086#false} assume !(1 == ~m_pc~0); {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 49: Hoare triple {107086#false} is_master_triggered_~__retres1~0#1 := 0; {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 50: Hoare triple {107086#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {107086#false} is VALID [2022-02-21 04:23:39,196 INFO L290 TraceCheckUtils]: 51: Hoare triple {107086#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {107086#false} is VALID [2022-02-21 04:23:39,197 INFO L290 TraceCheckUtils]: 52: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp~1#1); {107086#false} is VALID [2022-02-21 04:23:39,197 INFO L290 TraceCheckUtils]: 53: Hoare triple {107086#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {107086#false} is VALID [2022-02-21 04:23:39,197 INFO L290 TraceCheckUtils]: 54: Hoare triple {107086#false} assume 1 == ~t1_pc~0; {107086#false} is VALID [2022-02-21 04:23:39,197 INFO L290 TraceCheckUtils]: 55: Hoare triple {107086#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {107086#false} is VALID [2022-02-21 04:23:39,197 INFO L290 TraceCheckUtils]: 56: Hoare triple {107086#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {107086#false} is VALID [2022-02-21 04:23:39,197 INFO L290 TraceCheckUtils]: 57: Hoare triple {107086#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {107086#false} is VALID [2022-02-21 04:23:39,197 INFO L290 TraceCheckUtils]: 58: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___0~0#1); {107086#false} is VALID [2022-02-21 04:23:39,197 INFO L290 TraceCheckUtils]: 59: Hoare triple {107086#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {107086#false} is VALID [2022-02-21 04:23:39,197 INFO L290 TraceCheckUtils]: 60: Hoare triple {107086#false} assume 1 == ~t2_pc~0; {107086#false} is VALID [2022-02-21 04:23:39,197 INFO L290 TraceCheckUtils]: 61: Hoare triple {107086#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {107086#false} is VALID [2022-02-21 04:23:39,198 INFO L290 TraceCheckUtils]: 62: Hoare triple {107086#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {107086#false} is VALID [2022-02-21 04:23:39,198 INFO L290 TraceCheckUtils]: 63: Hoare triple {107086#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {107086#false} is VALID [2022-02-21 04:23:39,198 INFO L290 TraceCheckUtils]: 64: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___1~0#1); {107086#false} is VALID [2022-02-21 04:23:39,198 INFO L290 TraceCheckUtils]: 65: Hoare triple {107086#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {107086#false} is VALID [2022-02-21 04:23:39,198 INFO L290 TraceCheckUtils]: 66: Hoare triple {107086#false} assume !(1 == ~t3_pc~0); {107086#false} is VALID [2022-02-21 04:23:39,198 INFO L290 TraceCheckUtils]: 67: Hoare triple {107086#false} is_transmit3_triggered_~__retres1~3#1 := 0; {107086#false} is VALID [2022-02-21 04:23:39,198 INFO L290 TraceCheckUtils]: 68: Hoare triple {107086#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {107086#false} is VALID [2022-02-21 04:23:39,198 INFO L290 TraceCheckUtils]: 69: Hoare triple {107086#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {107086#false} is VALID [2022-02-21 04:23:39,198 INFO L290 TraceCheckUtils]: 70: Hoare triple {107086#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {107086#false} is VALID [2022-02-21 04:23:39,198 INFO L290 TraceCheckUtils]: 71: Hoare triple {107086#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 72: Hoare triple {107086#false} assume 1 == ~t4_pc~0; {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 73: Hoare triple {107086#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 74: Hoare triple {107086#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 75: Hoare triple {107086#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 76: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___3~0#1); {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 77: Hoare triple {107086#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 78: Hoare triple {107086#false} assume !(1 == ~t5_pc~0); {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 79: Hoare triple {107086#false} is_transmit5_triggered_~__retres1~5#1 := 0; {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 80: Hoare triple {107086#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 81: Hoare triple {107086#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {107086#false} is VALID [2022-02-21 04:23:39,199 INFO L290 TraceCheckUtils]: 82: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___4~0#1); {107086#false} is VALID [2022-02-21 04:23:39,200 INFO L290 TraceCheckUtils]: 83: Hoare triple {107086#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {107086#false} is VALID [2022-02-21 04:23:39,200 INFO L290 TraceCheckUtils]: 84: Hoare triple {107086#false} assume 1 == ~t6_pc~0; {107086#false} is VALID [2022-02-21 04:23:39,200 INFO L290 TraceCheckUtils]: 85: Hoare triple {107086#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {107086#false} is VALID [2022-02-21 04:23:39,200 INFO L290 TraceCheckUtils]: 86: Hoare triple {107086#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {107086#false} is VALID [2022-02-21 04:23:39,200 INFO L290 TraceCheckUtils]: 87: Hoare triple {107086#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {107086#false} is VALID [2022-02-21 04:23:39,200 INFO L290 TraceCheckUtils]: 88: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___5~0#1); {107086#false} is VALID [2022-02-21 04:23:39,200 INFO L290 TraceCheckUtils]: 89: Hoare triple {107086#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {107086#false} is VALID [2022-02-21 04:23:39,200 INFO L290 TraceCheckUtils]: 90: Hoare triple {107086#false} assume !(1 == ~t7_pc~0); {107086#false} is VALID [2022-02-21 04:23:39,200 INFO L290 TraceCheckUtils]: 91: Hoare triple {107086#false} is_transmit7_triggered_~__retres1~7#1 := 0; {107086#false} is VALID [2022-02-21 04:23:39,200 INFO L290 TraceCheckUtils]: 92: Hoare triple {107086#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 93: Hoare triple {107086#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 94: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___6~0#1); {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 95: Hoare triple {107086#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 96: Hoare triple {107086#false} assume 1 == ~t8_pc~0; {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 97: Hoare triple {107086#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 98: Hoare triple {107086#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 99: Hoare triple {107086#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 100: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___7~0#1); {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 101: Hoare triple {107086#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 102: Hoare triple {107086#false} assume 1 == ~t9_pc~0; {107086#false} is VALID [2022-02-21 04:23:39,201 INFO L290 TraceCheckUtils]: 103: Hoare triple {107086#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {107086#false} is VALID [2022-02-21 04:23:39,202 INFO L290 TraceCheckUtils]: 104: Hoare triple {107086#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {107086#false} is VALID [2022-02-21 04:23:39,202 INFO L290 TraceCheckUtils]: 105: Hoare triple {107086#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {107086#false} is VALID [2022-02-21 04:23:39,202 INFO L290 TraceCheckUtils]: 106: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___8~0#1); {107086#false} is VALID [2022-02-21 04:23:39,202 INFO L290 TraceCheckUtils]: 107: Hoare triple {107086#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {107086#false} is VALID [2022-02-21 04:23:39,202 INFO L290 TraceCheckUtils]: 108: Hoare triple {107086#false} assume !(1 == ~t10_pc~0); {107086#false} is VALID [2022-02-21 04:23:39,202 INFO L290 TraceCheckUtils]: 109: Hoare triple {107086#false} is_transmit10_triggered_~__retres1~10#1 := 0; {107086#false} is VALID [2022-02-21 04:23:39,202 INFO L290 TraceCheckUtils]: 110: Hoare triple {107086#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {107086#false} is VALID [2022-02-21 04:23:39,202 INFO L290 TraceCheckUtils]: 111: Hoare triple {107086#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {107086#false} is VALID [2022-02-21 04:23:39,202 INFO L290 TraceCheckUtils]: 112: Hoare triple {107086#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {107086#false} is VALID [2022-02-21 04:23:39,202 INFO L290 TraceCheckUtils]: 113: Hoare triple {107086#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {107086#false} is VALID [2022-02-21 04:23:39,203 INFO L290 TraceCheckUtils]: 114: Hoare triple {107086#false} assume 1 == ~t11_pc~0; {107086#false} is VALID [2022-02-21 04:23:39,203 INFO L290 TraceCheckUtils]: 115: Hoare triple {107086#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {107086#false} is VALID [2022-02-21 04:23:39,203 INFO L290 TraceCheckUtils]: 116: Hoare triple {107086#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {107086#false} is VALID [2022-02-21 04:23:39,203 INFO L290 TraceCheckUtils]: 117: Hoare triple {107086#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {107086#false} is VALID [2022-02-21 04:23:39,203 INFO L290 TraceCheckUtils]: 118: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___10~0#1); {107086#false} is VALID [2022-02-21 04:23:39,203 INFO L290 TraceCheckUtils]: 119: Hoare triple {107086#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {107086#false} is VALID [2022-02-21 04:23:39,203 INFO L290 TraceCheckUtils]: 120: Hoare triple {107086#false} assume !(1 == ~t12_pc~0); {107086#false} is VALID [2022-02-21 04:23:39,203 INFO L290 TraceCheckUtils]: 121: Hoare triple {107086#false} is_transmit12_triggered_~__retres1~12#1 := 0; {107086#false} is VALID [2022-02-21 04:23:39,203 INFO L290 TraceCheckUtils]: 122: Hoare triple {107086#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {107086#false} is VALID [2022-02-21 04:23:39,203 INFO L290 TraceCheckUtils]: 123: Hoare triple {107086#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 124: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___11~0#1); {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 125: Hoare triple {107086#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 126: Hoare triple {107086#false} assume 1 == ~t13_pc~0; {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 127: Hoare triple {107086#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 128: Hoare triple {107086#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 129: Hoare triple {107086#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 130: Hoare triple {107086#false} assume !(0 != activate_threads_~tmp___12~0#1); {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 131: Hoare triple {107086#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 132: Hoare triple {107086#false} assume !(1 == ~M_E~0); {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 133: Hoare triple {107086#false} assume !(1 == ~T1_E~0); {107086#false} is VALID [2022-02-21 04:23:39,204 INFO L290 TraceCheckUtils]: 134: Hoare triple {107086#false} assume !(1 == ~T2_E~0); {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 135: Hoare triple {107086#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 136: Hoare triple {107086#false} assume !(1 == ~T4_E~0); {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 137: Hoare triple {107086#false} assume !(1 == ~T5_E~0); {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 138: Hoare triple {107086#false} assume !(1 == ~T6_E~0); {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 139: Hoare triple {107086#false} assume !(1 == ~T7_E~0); {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 140: Hoare triple {107086#false} assume !(1 == ~T8_E~0); {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 141: Hoare triple {107086#false} assume !(1 == ~T9_E~0); {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 142: Hoare triple {107086#false} assume !(1 == ~T10_E~0); {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 143: Hoare triple {107086#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 144: Hoare triple {107086#false} assume !(1 == ~T12_E~0); {107086#false} is VALID [2022-02-21 04:23:39,205 INFO L290 TraceCheckUtils]: 145: Hoare triple {107086#false} assume !(1 == ~T13_E~0); {107086#false} is VALID [2022-02-21 04:23:39,206 INFO L290 TraceCheckUtils]: 146: Hoare triple {107086#false} assume !(1 == ~E_M~0); {107086#false} is VALID [2022-02-21 04:23:39,206 INFO L290 TraceCheckUtils]: 147: Hoare triple {107086#false} assume !(1 == ~E_1~0); {107086#false} is VALID [2022-02-21 04:23:39,206 INFO L290 TraceCheckUtils]: 148: Hoare triple {107086#false} assume !(1 == ~E_2~0); {107086#false} is VALID [2022-02-21 04:23:39,206 INFO L290 TraceCheckUtils]: 149: Hoare triple {107086#false} assume !(1 == ~E_3~0); {107086#false} is VALID [2022-02-21 04:23:39,206 INFO L290 TraceCheckUtils]: 150: Hoare triple {107086#false} assume !(1 == ~E_4~0); {107086#false} is VALID [2022-02-21 04:23:39,206 INFO L290 TraceCheckUtils]: 151: Hoare triple {107086#false} assume 1 == ~E_5~0;~E_5~0 := 2; {107086#false} is VALID [2022-02-21 04:23:39,206 INFO L290 TraceCheckUtils]: 152: Hoare triple {107086#false} assume !(1 == ~E_6~0); {107086#false} is VALID [2022-02-21 04:23:39,206 INFO L290 TraceCheckUtils]: 153: Hoare triple {107086#false} assume !(1 == ~E_7~0); {107086#false} is VALID [2022-02-21 04:23:39,206 INFO L290 TraceCheckUtils]: 154: Hoare triple {107086#false} assume !(1 == ~E_8~0); {107086#false} is VALID [2022-02-21 04:23:39,206 INFO L290 TraceCheckUtils]: 155: Hoare triple {107086#false} assume !(1 == ~E_9~0); {107086#false} is VALID [2022-02-21 04:23:39,207 INFO L290 TraceCheckUtils]: 156: Hoare triple {107086#false} assume !(1 == ~E_10~0); {107086#false} is VALID [2022-02-21 04:23:39,207 INFO L290 TraceCheckUtils]: 157: Hoare triple {107086#false} assume !(1 == ~E_11~0); {107086#false} is VALID [2022-02-21 04:23:39,207 INFO L290 TraceCheckUtils]: 158: Hoare triple {107086#false} assume !(1 == ~E_12~0); {107086#false} is VALID [2022-02-21 04:23:39,207 INFO L290 TraceCheckUtils]: 159: Hoare triple {107086#false} assume 1 == ~E_13~0;~E_13~0 := 2; {107086#false} is VALID [2022-02-21 04:23:39,207 INFO L290 TraceCheckUtils]: 160: Hoare triple {107086#false} assume { :end_inline_reset_delta_events } true; {107086#false} is VALID [2022-02-21 04:23:39,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:39,207 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:39,207 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307200605] [2022-02-21 04:23:39,208 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307200605] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:39,208 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:39,208 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:39,208 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50817176] [2022-02-21 04:23:39,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:39,209 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:39,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:39,209 INFO L85 PathProgramCache]: Analyzing trace with hash -1640420756, now seen corresponding path program 3 times [2022-02-21 04:23:39,209 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:39,209 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548453828] [2022-02-21 04:23:39,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:39,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:39,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:39,233 INFO L290 TraceCheckUtils]: 0: Hoare triple {107088#true} assume !false; {107088#true} is VALID [2022-02-21 04:23:39,233 INFO L290 TraceCheckUtils]: 1: Hoare triple {107088#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {107088#true} is VALID [2022-02-21 04:23:39,233 INFO L290 TraceCheckUtils]: 2: Hoare triple {107088#true} assume !false; {107088#true} is VALID [2022-02-21 04:23:39,233 INFO L290 TraceCheckUtils]: 3: Hoare triple {107088#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {107088#true} is VALID [2022-02-21 04:23:39,233 INFO L290 TraceCheckUtils]: 4: Hoare triple {107088#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {107088#true} is VALID [2022-02-21 04:23:39,233 INFO L290 TraceCheckUtils]: 5: Hoare triple {107088#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {107088#true} is VALID [2022-02-21 04:23:39,233 INFO L290 TraceCheckUtils]: 6: Hoare triple {107088#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {107088#true} is VALID [2022-02-21 04:23:39,234 INFO L290 TraceCheckUtils]: 7: Hoare triple {107088#true} assume !(0 != eval_~tmp~0#1); {107088#true} is VALID [2022-02-21 04:23:39,234 INFO L290 TraceCheckUtils]: 8: Hoare triple {107088#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {107088#true} is VALID [2022-02-21 04:23:39,234 INFO L290 TraceCheckUtils]: 9: Hoare triple {107088#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {107088#true} is VALID [2022-02-21 04:23:39,234 INFO L290 TraceCheckUtils]: 10: Hoare triple {107088#true} assume 0 == ~M_E~0;~M_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,234 INFO L290 TraceCheckUtils]: 11: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,235 INFO L290 TraceCheckUtils]: 12: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T2_E~0); {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,235 INFO L290 TraceCheckUtils]: 13: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,235 INFO L290 TraceCheckUtils]: 14: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,235 INFO L290 TraceCheckUtils]: 15: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,236 INFO L290 TraceCheckUtils]: 16: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,236 INFO L290 TraceCheckUtils]: 17: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,236 INFO L290 TraceCheckUtils]: 18: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,236 INFO L290 TraceCheckUtils]: 19: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,237 INFO L290 TraceCheckUtils]: 20: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T10_E~0); {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,237 INFO L290 TraceCheckUtils]: 21: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,237 INFO L290 TraceCheckUtils]: 22: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,237 INFO L290 TraceCheckUtils]: 23: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,238 INFO L290 TraceCheckUtils]: 24: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,238 INFO L290 TraceCheckUtils]: 25: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,238 INFO L290 TraceCheckUtils]: 26: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,238 INFO L290 TraceCheckUtils]: 27: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,239 INFO L290 TraceCheckUtils]: 28: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,239 INFO L290 TraceCheckUtils]: 29: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,239 INFO L290 TraceCheckUtils]: 30: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,239 INFO L290 TraceCheckUtils]: 31: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,240 INFO L290 TraceCheckUtils]: 32: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,240 INFO L290 TraceCheckUtils]: 33: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,240 INFO L290 TraceCheckUtils]: 34: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,240 INFO L290 TraceCheckUtils]: 35: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,241 INFO L290 TraceCheckUtils]: 36: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,241 INFO L290 TraceCheckUtils]: 37: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,241 INFO L290 TraceCheckUtils]: 38: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,242 INFO L290 TraceCheckUtils]: 39: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,242 INFO L290 TraceCheckUtils]: 40: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,242 INFO L290 TraceCheckUtils]: 41: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,242 INFO L290 TraceCheckUtils]: 42: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,243 INFO L290 TraceCheckUtils]: 43: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,243 INFO L290 TraceCheckUtils]: 44: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,243 INFO L290 TraceCheckUtils]: 45: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,243 INFO L290 TraceCheckUtils]: 46: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,244 INFO L290 TraceCheckUtils]: 47: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,244 INFO L290 TraceCheckUtils]: 48: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,244 INFO L290 TraceCheckUtils]: 49: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,244 INFO L290 TraceCheckUtils]: 50: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,245 INFO L290 TraceCheckUtils]: 51: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,245 INFO L290 TraceCheckUtils]: 52: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,245 INFO L290 TraceCheckUtils]: 53: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,245 INFO L290 TraceCheckUtils]: 54: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,246 INFO L290 TraceCheckUtils]: 55: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,246 INFO L290 TraceCheckUtils]: 56: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,246 INFO L290 TraceCheckUtils]: 57: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,246 INFO L290 TraceCheckUtils]: 58: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,247 INFO L290 TraceCheckUtils]: 59: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,247 INFO L290 TraceCheckUtils]: 60: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,247 INFO L290 TraceCheckUtils]: 61: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,247 INFO L290 TraceCheckUtils]: 62: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,248 INFO L290 TraceCheckUtils]: 63: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,248 INFO L290 TraceCheckUtils]: 64: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,248 INFO L290 TraceCheckUtils]: 65: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,248 INFO L290 TraceCheckUtils]: 66: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,249 INFO L290 TraceCheckUtils]: 67: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,249 INFO L290 TraceCheckUtils]: 68: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,249 INFO L290 TraceCheckUtils]: 69: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,250 INFO L290 TraceCheckUtils]: 70: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,250 INFO L290 TraceCheckUtils]: 71: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,250 INFO L290 TraceCheckUtils]: 72: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,250 INFO L290 TraceCheckUtils]: 73: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,251 INFO L290 TraceCheckUtils]: 74: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,251 INFO L290 TraceCheckUtils]: 75: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,251 INFO L290 TraceCheckUtils]: 76: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,251 INFO L290 TraceCheckUtils]: 77: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,252 INFO L290 TraceCheckUtils]: 78: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,252 INFO L290 TraceCheckUtils]: 79: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,252 INFO L290 TraceCheckUtils]: 80: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,252 INFO L290 TraceCheckUtils]: 81: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,253 INFO L290 TraceCheckUtils]: 82: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,253 INFO L290 TraceCheckUtils]: 83: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,253 INFO L290 TraceCheckUtils]: 84: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,253 INFO L290 TraceCheckUtils]: 85: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,254 INFO L290 TraceCheckUtils]: 86: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,254 INFO L290 TraceCheckUtils]: 87: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,254 INFO L290 TraceCheckUtils]: 88: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,254 INFO L290 TraceCheckUtils]: 89: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,255 INFO L290 TraceCheckUtils]: 90: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,255 INFO L290 TraceCheckUtils]: 91: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,255 INFO L290 TraceCheckUtils]: 92: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,255 INFO L290 TraceCheckUtils]: 93: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,256 INFO L290 TraceCheckUtils]: 94: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,256 INFO L290 TraceCheckUtils]: 95: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,256 INFO L290 TraceCheckUtils]: 96: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,256 INFO L290 TraceCheckUtils]: 97: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,257 INFO L290 TraceCheckUtils]: 98: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,257 INFO L290 TraceCheckUtils]: 99: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,257 INFO L290 TraceCheckUtils]: 100: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,257 INFO L290 TraceCheckUtils]: 101: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,258 INFO L290 TraceCheckUtils]: 102: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,258 INFO L290 TraceCheckUtils]: 103: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,258 INFO L290 TraceCheckUtils]: 104: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,258 INFO L290 TraceCheckUtils]: 105: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,259 INFO L290 TraceCheckUtils]: 106: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,259 INFO L290 TraceCheckUtils]: 107: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,259 INFO L290 TraceCheckUtils]: 108: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,259 INFO L290 TraceCheckUtils]: 109: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,260 INFO L290 TraceCheckUtils]: 110: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,260 INFO L290 TraceCheckUtils]: 111: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,260 INFO L290 TraceCheckUtils]: 112: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,260 INFO L290 TraceCheckUtils]: 113: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,261 INFO L290 TraceCheckUtils]: 114: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,261 INFO L290 TraceCheckUtils]: 115: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,261 INFO L290 TraceCheckUtils]: 116: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,262 INFO L290 TraceCheckUtils]: 117: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,262 INFO L290 TraceCheckUtils]: 118: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,262 INFO L290 TraceCheckUtils]: 119: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,262 INFO L290 TraceCheckUtils]: 120: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,263 INFO L290 TraceCheckUtils]: 121: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,263 INFO L290 TraceCheckUtils]: 122: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {107090#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:39,263 INFO L290 TraceCheckUtils]: 123: Hoare triple {107090#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {107089#false} is VALID [2022-02-21 04:23:39,263 INFO L290 TraceCheckUtils]: 124: Hoare triple {107089#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,263 INFO L290 TraceCheckUtils]: 125: Hoare triple {107089#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,263 INFO L290 TraceCheckUtils]: 126: Hoare triple {107089#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,263 INFO L290 TraceCheckUtils]: 127: Hoare triple {107089#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 128: Hoare triple {107089#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 129: Hoare triple {107089#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 130: Hoare triple {107089#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 131: Hoare triple {107089#false} assume !(1 == ~T8_E~0); {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 132: Hoare triple {107089#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 133: Hoare triple {107089#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 134: Hoare triple {107089#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 135: Hoare triple {107089#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 136: Hoare triple {107089#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 137: Hoare triple {107089#false} assume 1 == ~E_M~0;~E_M~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,264 INFO L290 TraceCheckUtils]: 138: Hoare triple {107089#false} assume 1 == ~E_1~0;~E_1~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,265 INFO L290 TraceCheckUtils]: 139: Hoare triple {107089#false} assume !(1 == ~E_2~0); {107089#false} is VALID [2022-02-21 04:23:39,265 INFO L290 TraceCheckUtils]: 140: Hoare triple {107089#false} assume 1 == ~E_3~0;~E_3~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,265 INFO L290 TraceCheckUtils]: 141: Hoare triple {107089#false} assume 1 == ~E_4~0;~E_4~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,265 INFO L290 TraceCheckUtils]: 142: Hoare triple {107089#false} assume 1 == ~E_5~0;~E_5~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,265 INFO L290 TraceCheckUtils]: 143: Hoare triple {107089#false} assume 1 == ~E_6~0;~E_6~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,265 INFO L290 TraceCheckUtils]: 144: Hoare triple {107089#false} assume 1 == ~E_7~0;~E_7~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,265 INFO L290 TraceCheckUtils]: 145: Hoare triple {107089#false} assume 1 == ~E_8~0;~E_8~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,265 INFO L290 TraceCheckUtils]: 146: Hoare triple {107089#false} assume 1 == ~E_9~0;~E_9~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,265 INFO L290 TraceCheckUtils]: 147: Hoare triple {107089#false} assume !(1 == ~E_10~0); {107089#false} is VALID [2022-02-21 04:23:39,265 INFO L290 TraceCheckUtils]: 148: Hoare triple {107089#false} assume 1 == ~E_11~0;~E_11~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,266 INFO L290 TraceCheckUtils]: 149: Hoare triple {107089#false} assume 1 == ~E_12~0;~E_12~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,266 INFO L290 TraceCheckUtils]: 150: Hoare triple {107089#false} assume 1 == ~E_13~0;~E_13~0 := 2; {107089#false} is VALID [2022-02-21 04:23:39,266 INFO L290 TraceCheckUtils]: 151: Hoare triple {107089#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {107089#false} is VALID [2022-02-21 04:23:39,266 INFO L290 TraceCheckUtils]: 152: Hoare triple {107089#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {107089#false} is VALID [2022-02-21 04:23:39,266 INFO L290 TraceCheckUtils]: 153: Hoare triple {107089#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {107089#false} is VALID [2022-02-21 04:23:39,266 INFO L290 TraceCheckUtils]: 154: Hoare triple {107089#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {107089#false} is VALID [2022-02-21 04:23:39,266 INFO L290 TraceCheckUtils]: 155: Hoare triple {107089#false} assume !(0 == start_simulation_~tmp~3#1); {107089#false} is VALID [2022-02-21 04:23:39,266 INFO L290 TraceCheckUtils]: 156: Hoare triple {107089#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {107089#false} is VALID [2022-02-21 04:23:39,267 INFO L290 TraceCheckUtils]: 157: Hoare triple {107089#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {107089#false} is VALID [2022-02-21 04:23:39,267 INFO L290 TraceCheckUtils]: 158: Hoare triple {107089#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {107089#false} is VALID [2022-02-21 04:23:39,267 INFO L290 TraceCheckUtils]: 159: Hoare triple {107089#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {107089#false} is VALID [2022-02-21 04:23:39,267 INFO L290 TraceCheckUtils]: 160: Hoare triple {107089#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {107089#false} is VALID [2022-02-21 04:23:39,267 INFO L290 TraceCheckUtils]: 161: Hoare triple {107089#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {107089#false} is VALID [2022-02-21 04:23:39,267 INFO L290 TraceCheckUtils]: 162: Hoare triple {107089#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {107089#false} is VALID [2022-02-21 04:23:39,267 INFO L290 TraceCheckUtils]: 163: Hoare triple {107089#false} assume !(0 != start_simulation_~tmp___0~1#1); {107089#false} is VALID [2022-02-21 04:23:39,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:39,268 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:39,268 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [548453828] [2022-02-21 04:23:39,268 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [548453828] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:39,268 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:39,268 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:39,269 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1555076152] [2022-02-21 04:23:39,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:39,269 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:39,269 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:39,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:39,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:39,270 INFO L87 Difference]: Start difference. First operand 2018 states and 2975 transitions. cyclomatic complexity: 958 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:41,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:41,705 INFO L93 Difference]: Finished difference Result 3761 states and 5528 transitions. [2022-02-21 04:23:41,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:41,705 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:41,804 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:41,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3761 states and 5528 transitions. [2022-02-21 04:23:42,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-02-21 04:23:42,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3761 states to 3761 states and 5528 transitions. [2022-02-21 04:23:42,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3761 [2022-02-21 04:23:42,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3761 [2022-02-21 04:23:42,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3761 states and 5528 transitions. [2022-02-21 04:23:42,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:42,698 INFO L681 BuchiCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2022-02-21 04:23:42,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3761 states and 5528 transitions. [2022-02-21 04:23:42,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3761 to 3761. [2022-02-21 04:23:42,747 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:42,750 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3761 states and 5528 transitions. Second operand has 3761 states, 3761 states have (on average 1.4698218558893912) internal successors, (5528), 3760 states have internal predecessors, (5528), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:42,752 INFO L74 IsIncluded]: Start isIncluded. First operand 3761 states and 5528 transitions. Second operand has 3761 states, 3761 states have (on average 1.4698218558893912) internal successors, (5528), 3760 states have internal predecessors, (5528), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:42,754 INFO L87 Difference]: Start difference. First operand 3761 states and 5528 transitions. Second operand has 3761 states, 3761 states have (on average 1.4698218558893912) internal successors, (5528), 3760 states have internal predecessors, (5528), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:43,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:43,082 INFO L93 Difference]: Finished difference Result 3761 states and 5528 transitions. [2022-02-21 04:23:43,082 INFO L276 IsEmpty]: Start isEmpty. Operand 3761 states and 5528 transitions. [2022-02-21 04:23:43,086 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:43,086 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:43,089 INFO L74 IsIncluded]: Start isIncluded. First operand has 3761 states, 3761 states have (on average 1.4698218558893912) internal successors, (5528), 3760 states have internal predecessors, (5528), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3761 states and 5528 transitions. [2022-02-21 04:23:43,091 INFO L87 Difference]: Start difference. First operand has 3761 states, 3761 states have (on average 1.4698218558893912) internal successors, (5528), 3760 states have internal predecessors, (5528), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3761 states and 5528 transitions. [2022-02-21 04:23:43,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:43,416 INFO L93 Difference]: Finished difference Result 3761 states and 5528 transitions. [2022-02-21 04:23:43,416 INFO L276 IsEmpty]: Start isEmpty. Operand 3761 states and 5528 transitions. [2022-02-21 04:23:43,419 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:43,419 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:43,420 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:43,420 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:43,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4698218558893912) internal successors, (5528), 3760 states have internal predecessors, (5528), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:43,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5528 transitions. [2022-02-21 04:23:43,776 INFO L704 BuchiCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2022-02-21 04:23:43,777 INFO L587 BuchiCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2022-02-21 04:23:43,777 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:23:43,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5528 transitions. [2022-02-21 04:23:43,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-02-21 04:23:43,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:43,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:43,784 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:43,784 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:43,785 INFO L791 eck$LassoCheckResult]: Stem: 111767#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 111768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 112851#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112263#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112264#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 111749#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111750#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111816#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111817#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112259#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112260#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111782#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 111601#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 111602#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 112047#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 112048#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 111922#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 111923#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 111572#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111573#L1279 assume !(0 == ~M_E~0); 112841#L1279-2 assume !(0 == ~T1_E~0); 111195#L1284-1 assume !(0 == ~T2_E~0); 111196#L1289-1 assume !(0 == ~T3_E~0); 111919#L1294-1 assume !(0 == ~T4_E~0); 111920#L1299-1 assume !(0 == ~T5_E~0); 111931#L1304-1 assume !(0 == ~T6_E~0); 112941#L1309-1 assume !(0 == ~T7_E~0); 112942#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 111125#L1319-1 assume !(0 == ~T9_E~0); 111126#L1324-1 assume !(0 == ~T10_E~0); 111298#L1329-1 assume !(0 == ~T11_E~0); 111299#L1334-1 assume !(0 == ~T12_E~0); 112731#L1339-1 assume !(0 == ~T13_E~0); 112824#L1344-1 assume !(0 == ~E_M~0); 112825#L1349-1 assume !(0 == ~E_1~0); 112107#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 112108#L1359-1 assume !(0 == ~E_3~0); 112545#L1364-1 assume !(0 == ~E_4~0); 111427#L1369-1 assume !(0 == ~E_5~0); 111428#L1374-1 assume !(0 == ~E_6~0); 112112#L1379-1 assume !(0 == ~E_7~0); 112113#L1384-1 assume !(0 == ~E_8~0); 112191#L1389-1 assume !(0 == ~E_9~0); 112754#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 112755#L1399-1 assume !(0 == ~E_11~0); 112882#L1404-1 assume !(0 == ~E_12~0); 111520#L1409-1 assume !(0 == ~E_13~0); 111521#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112871#L628 assume !(1 == ~m_pc~0); 111424#L628-2 is_master_triggered_~__retres1~0#1 := 0; 111423#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112189#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 112190#L1591 assume !(0 != activate_threads_~tmp~1#1); 112890#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111976#L647 assume 1 == ~t1_pc~0; 111344#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 111345#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111616#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 111617#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 112810#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112811#L666 assume 1 == ~t2_pc~0; 111192#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 111193#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111359#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112830#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 112313#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112314#L685 assume !(1 == ~t3_pc~0); 112420#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112419#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112036#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 112037#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112159#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111643#L704 assume 1 == ~t4_pc~0; 111644#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 112170#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112171#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 112856#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 112029#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112030#L723 assume !(1 == ~t5_pc~0); 112153#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 112394#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112540#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 112292#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 112293#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 111409#L742 assume 1 == ~t6_pc~0; 111410#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111558#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111559#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 111094#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 111095#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 111486#L761 assume !(1 == ~t7_pc~0); 111487#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 111355#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 111356#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 112160#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 112161#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 111119#L780 assume 1 == ~t8_pc~0; 111120#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 111395#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 111396#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112120#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 112121#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 112243#L799 assume 1 == ~t9_pc~0; 112357#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 111122#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111123#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 112255#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 112467#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 112275#L818 assume !(1 == ~t10_pc~0); 110903#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 110904#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112350#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 112279#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 112280#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112320#L837 assume 1 == ~t11_pc~0; 112321#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 112150#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112561#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 112236#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 112237#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 111985#L856 assume !(1 == ~t12_pc~0); 111986#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 112653#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 112654#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 112633#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 112634#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 112845#L875 assume 1 == ~t13_pc~0; 111929#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 111561#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 111562#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 111501#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 111502#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112347#L1427 assume !(1 == ~M_E~0); 112331#L1427-2 assume !(1 == ~T1_E~0); 111473#L1432-1 assume !(1 == ~T2_E~0); 111474#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112551#L1442-1 assume !(1 == ~T4_E~0); 112552#L1447-1 assume !(1 == ~T5_E~0); 112405#L1452-1 assume !(1 == ~T6_E~0); 111038#L1457-1 assume !(1 == ~T7_E~0); 111039#L1462-1 assume !(1 == ~T8_E~0); 112581#L1467-1 assume !(1 == ~T9_E~0); 112601#L1472-1 assume !(1 == ~T10_E~0); 112602#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 112345#L1482-1 assume !(1 == ~T12_E~0); 112346#L1487-1 assume !(1 == ~T13_E~0); 111369#L1492-1 assume !(1 == ~E_M~0); 111370#L1497-1 assume !(1 == ~E_1~0); 111731#L1502-1 assume !(1 == ~E_2~0); 111732#L1507-1 assume !(1 == ~E_3~0); 111247#L1512-1 assume !(1 == ~E_4~0); 111248#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 112678#L1522-1 assume !(1 == ~E_6~0); 111973#L1527-1 assume !(1 == ~E_7~0); 111974#L1532-1 assume !(1 == ~E_8~0); 112921#L1537-1 assume !(1 == ~E_9~0); 112177#L1542-1 assume !(1 == ~E_10~0); 112007#L1547-1 assume !(1 == ~E_11~0); 112008#L1552-1 assume !(1 == ~E_12~0); 110942#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 110943#L1562-1 assume { :end_inline_reset_delta_events } true; 111549#L1928-2 [2022-02-21 04:23:43,785 INFO L793 eck$LassoCheckResult]: Loop: 111549#L1928-2 assume !false; 113074#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 113070#L1254 assume !false; 113069#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 113062#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 113054#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 112858#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 112859#L1067 assume !(0 != eval_~tmp~0#1); 113053#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 113052#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 112869#L1279-3 assume !(0 == ~M_E~0); 111753#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 111735#L1284-3 assume !(0 == ~T2_E~0); 111736#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 113049#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 113048#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 113047#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 112569#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 112570#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 113046#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 112623#L1324-3 assume !(0 == ~T10_E~0); 111244#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 111245#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 112013#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 112014#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 112317#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 111593#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 111594#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 112328#L1364-3 assume !(0 == ~E_4~0); 112940#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 112773#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 111373#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 111374#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 113036#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 113035#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 113034#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 112784#L1404-3 assume !(0 == ~E_12~0); 112785#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 112840#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112203#L628-45 assume 1 == ~m_pc~0; 112205#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 112917#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111238#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 111239#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 111627#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113030#L647-45 assume !(1 == ~t1_pc~0); 113029#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 113027#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 113026#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 113025#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 112838#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112839#L666-45 assume 1 == ~t2_pc~0; 113024#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 112902#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112903#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 113022#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 113021#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 113020#L685-45 assume !(1 == ~t3_pc~0); 113019#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 112828#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112829#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 112675#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112676#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112881#L704-45 assume !(1 == ~t4_pc~0); 110919#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 110920#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111779#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 112123#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 112957#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112238#L723-45 assume 1 == ~t5_pc~0; 112240#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 112756#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 113008#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 113007#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 113006#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112642#L742-45 assume 1 == ~t6_pc~0; 112643#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111851#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112326#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112362#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 112363#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 113000#L761-45 assume !(1 == ~t7_pc~0); 112999#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 112997#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112996#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 112995#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 112994#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 112747#L780-45 assume !(1 == ~t8_pc~0); 112749#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 112993#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112992#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112991#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 112990#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 112989#L799-45 assume !(1 == ~t9_pc~0); 112987#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 112986#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 112809#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 112406#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 112407#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 111171#L818-45 assume !(1 == ~t10_pc~0); 111173#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 111290#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112380#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111777#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111778#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112502#L837-45 assume 1 == ~t11_pc~0; 112976#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 112974#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112973#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 112972#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 112971#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 112970#L856-45 assume 1 == ~t12_pc~0; 112837#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 111312#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 112969#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 112968#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 112967#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 112679#L875-45 assume 1 == ~t13_pc~0; 112088#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 112089#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 112151#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 112939#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 112962#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112729#L1427-3 assume !(1 == ~M_E~0); 112730#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 114447#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 114446#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 114445#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 114444#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 114443#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 114442#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 114441#L1462-3 assume !(1 == ~T8_E~0); 114440#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 114439#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 114438#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 114437#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 114436#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 114259#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 114258#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 114257#L1502-3 assume !(1 == ~E_2~0); 114256#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 114255#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 114254#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 114253#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 114252#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 114251#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 114250#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 114249#L1542-3 assume !(1 == ~E_10~0); 114248#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 114247#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 114246#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 111433#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 111434#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 110853#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 111618#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 111619#L1947 assume !(0 == start_simulation_~tmp~3#1); 112228#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 112437#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 111490#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 112877#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 113108#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 112588#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112341#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 112342#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 111549#L1928-2 [2022-02-21 04:23:43,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:43,786 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2022-02-21 04:23:43,786 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:43,786 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788830288] [2022-02-21 04:23:43,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:43,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:43,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:43,811 INFO L290 TraceCheckUtils]: 0: Hoare triple {122138#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,812 INFO L290 TraceCheckUtils]: 1: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,812 INFO L290 TraceCheckUtils]: 2: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,812 INFO L290 TraceCheckUtils]: 3: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,813 INFO L290 TraceCheckUtils]: 4: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,813 INFO L290 TraceCheckUtils]: 5: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,813 INFO L290 TraceCheckUtils]: 6: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,814 INFO L290 TraceCheckUtils]: 7: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,814 INFO L290 TraceCheckUtils]: 8: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,814 INFO L290 TraceCheckUtils]: 9: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,814 INFO L290 TraceCheckUtils]: 10: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,815 INFO L290 TraceCheckUtils]: 11: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,815 INFO L290 TraceCheckUtils]: 12: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,815 INFO L290 TraceCheckUtils]: 13: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,816 INFO L290 TraceCheckUtils]: 14: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,816 INFO L290 TraceCheckUtils]: 15: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,816 INFO L290 TraceCheckUtils]: 16: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,816 INFO L290 TraceCheckUtils]: 17: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,817 INFO L290 TraceCheckUtils]: 18: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {122140#(= ~T8_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:43,817 INFO L290 TraceCheckUtils]: 19: Hoare triple {122140#(= ~T8_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {122141#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,817 INFO L290 TraceCheckUtils]: 20: Hoare triple {122141#(not (= ~T8_E~0 0))} assume !(0 == ~T1_E~0); {122141#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,818 INFO L290 TraceCheckUtils]: 21: Hoare triple {122141#(not (= ~T8_E~0 0))} assume !(0 == ~T2_E~0); {122141#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,818 INFO L290 TraceCheckUtils]: 22: Hoare triple {122141#(not (= ~T8_E~0 0))} assume !(0 == ~T3_E~0); {122141#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,818 INFO L290 TraceCheckUtils]: 23: Hoare triple {122141#(not (= ~T8_E~0 0))} assume !(0 == ~T4_E~0); {122141#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,819 INFO L290 TraceCheckUtils]: 24: Hoare triple {122141#(not (= ~T8_E~0 0))} assume !(0 == ~T5_E~0); {122141#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,819 INFO L290 TraceCheckUtils]: 25: Hoare triple {122141#(not (= ~T8_E~0 0))} assume !(0 == ~T6_E~0); {122141#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,819 INFO L290 TraceCheckUtils]: 26: Hoare triple {122141#(not (= ~T8_E~0 0))} assume !(0 == ~T7_E~0); {122141#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,820 INFO L290 TraceCheckUtils]: 27: Hoare triple {122141#(not (= ~T8_E~0 0))} assume 0 == ~T8_E~0;~T8_E~0 := 1; {122139#false} is VALID [2022-02-21 04:23:43,820 INFO L290 TraceCheckUtils]: 28: Hoare triple {122139#false} assume !(0 == ~T9_E~0); {122139#false} is VALID [2022-02-21 04:23:43,820 INFO L290 TraceCheckUtils]: 29: Hoare triple {122139#false} assume !(0 == ~T10_E~0); {122139#false} is VALID [2022-02-21 04:23:43,820 INFO L290 TraceCheckUtils]: 30: Hoare triple {122139#false} assume !(0 == ~T11_E~0); {122139#false} is VALID [2022-02-21 04:23:43,820 INFO L290 TraceCheckUtils]: 31: Hoare triple {122139#false} assume !(0 == ~T12_E~0); {122139#false} is VALID [2022-02-21 04:23:43,820 INFO L290 TraceCheckUtils]: 32: Hoare triple {122139#false} assume !(0 == ~T13_E~0); {122139#false} is VALID [2022-02-21 04:23:43,820 INFO L290 TraceCheckUtils]: 33: Hoare triple {122139#false} assume !(0 == ~E_M~0); {122139#false} is VALID [2022-02-21 04:23:43,820 INFO L290 TraceCheckUtils]: 34: Hoare triple {122139#false} assume !(0 == ~E_1~0); {122139#false} is VALID [2022-02-21 04:23:43,820 INFO L290 TraceCheckUtils]: 35: Hoare triple {122139#false} assume 0 == ~E_2~0;~E_2~0 := 1; {122139#false} is VALID [2022-02-21 04:23:43,821 INFO L290 TraceCheckUtils]: 36: Hoare triple {122139#false} assume !(0 == ~E_3~0); {122139#false} is VALID [2022-02-21 04:23:43,821 INFO L290 TraceCheckUtils]: 37: Hoare triple {122139#false} assume !(0 == ~E_4~0); {122139#false} is VALID [2022-02-21 04:23:43,821 INFO L290 TraceCheckUtils]: 38: Hoare triple {122139#false} assume !(0 == ~E_5~0); {122139#false} is VALID [2022-02-21 04:23:43,821 INFO L290 TraceCheckUtils]: 39: Hoare triple {122139#false} assume !(0 == ~E_6~0); {122139#false} is VALID [2022-02-21 04:23:43,821 INFO L290 TraceCheckUtils]: 40: Hoare triple {122139#false} assume !(0 == ~E_7~0); {122139#false} is VALID [2022-02-21 04:23:43,821 INFO L290 TraceCheckUtils]: 41: Hoare triple {122139#false} assume !(0 == ~E_8~0); {122139#false} is VALID [2022-02-21 04:23:43,821 INFO L290 TraceCheckUtils]: 42: Hoare triple {122139#false} assume !(0 == ~E_9~0); {122139#false} is VALID [2022-02-21 04:23:43,821 INFO L290 TraceCheckUtils]: 43: Hoare triple {122139#false} assume 0 == ~E_10~0;~E_10~0 := 1; {122139#false} is VALID [2022-02-21 04:23:43,821 INFO L290 TraceCheckUtils]: 44: Hoare triple {122139#false} assume !(0 == ~E_11~0); {122139#false} is VALID [2022-02-21 04:23:43,821 INFO L290 TraceCheckUtils]: 45: Hoare triple {122139#false} assume !(0 == ~E_12~0); {122139#false} is VALID [2022-02-21 04:23:43,822 INFO L290 TraceCheckUtils]: 46: Hoare triple {122139#false} assume !(0 == ~E_13~0); {122139#false} is VALID [2022-02-21 04:23:43,822 INFO L290 TraceCheckUtils]: 47: Hoare triple {122139#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {122139#false} is VALID [2022-02-21 04:23:43,822 INFO L290 TraceCheckUtils]: 48: Hoare triple {122139#false} assume !(1 == ~m_pc~0); {122139#false} is VALID [2022-02-21 04:23:43,822 INFO L290 TraceCheckUtils]: 49: Hoare triple {122139#false} is_master_triggered_~__retres1~0#1 := 0; {122139#false} is VALID [2022-02-21 04:23:43,822 INFO L290 TraceCheckUtils]: 50: Hoare triple {122139#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {122139#false} is VALID [2022-02-21 04:23:43,822 INFO L290 TraceCheckUtils]: 51: Hoare triple {122139#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {122139#false} is VALID [2022-02-21 04:23:43,822 INFO L290 TraceCheckUtils]: 52: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp~1#1); {122139#false} is VALID [2022-02-21 04:23:43,822 INFO L290 TraceCheckUtils]: 53: Hoare triple {122139#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {122139#false} is VALID [2022-02-21 04:23:43,822 INFO L290 TraceCheckUtils]: 54: Hoare triple {122139#false} assume 1 == ~t1_pc~0; {122139#false} is VALID [2022-02-21 04:23:43,822 INFO L290 TraceCheckUtils]: 55: Hoare triple {122139#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {122139#false} is VALID [2022-02-21 04:23:43,823 INFO L290 TraceCheckUtils]: 56: Hoare triple {122139#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {122139#false} is VALID [2022-02-21 04:23:43,823 INFO L290 TraceCheckUtils]: 57: Hoare triple {122139#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {122139#false} is VALID [2022-02-21 04:23:43,823 INFO L290 TraceCheckUtils]: 58: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___0~0#1); {122139#false} is VALID [2022-02-21 04:23:43,823 INFO L290 TraceCheckUtils]: 59: Hoare triple {122139#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {122139#false} is VALID [2022-02-21 04:23:43,823 INFO L290 TraceCheckUtils]: 60: Hoare triple {122139#false} assume 1 == ~t2_pc~0; {122139#false} is VALID [2022-02-21 04:23:43,823 INFO L290 TraceCheckUtils]: 61: Hoare triple {122139#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {122139#false} is VALID [2022-02-21 04:23:43,823 INFO L290 TraceCheckUtils]: 62: Hoare triple {122139#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {122139#false} is VALID [2022-02-21 04:23:43,823 INFO L290 TraceCheckUtils]: 63: Hoare triple {122139#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {122139#false} is VALID [2022-02-21 04:23:43,823 INFO L290 TraceCheckUtils]: 64: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___1~0#1); {122139#false} is VALID [2022-02-21 04:23:43,823 INFO L290 TraceCheckUtils]: 65: Hoare triple {122139#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {122139#false} is VALID [2022-02-21 04:23:43,824 INFO L290 TraceCheckUtils]: 66: Hoare triple {122139#false} assume !(1 == ~t3_pc~0); {122139#false} is VALID [2022-02-21 04:23:43,824 INFO L290 TraceCheckUtils]: 67: Hoare triple {122139#false} is_transmit3_triggered_~__retres1~3#1 := 0; {122139#false} is VALID [2022-02-21 04:23:43,824 INFO L290 TraceCheckUtils]: 68: Hoare triple {122139#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {122139#false} is VALID [2022-02-21 04:23:43,824 INFO L290 TraceCheckUtils]: 69: Hoare triple {122139#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {122139#false} is VALID [2022-02-21 04:23:43,824 INFO L290 TraceCheckUtils]: 70: Hoare triple {122139#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {122139#false} is VALID [2022-02-21 04:23:43,824 INFO L290 TraceCheckUtils]: 71: Hoare triple {122139#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {122139#false} is VALID [2022-02-21 04:23:43,824 INFO L290 TraceCheckUtils]: 72: Hoare triple {122139#false} assume 1 == ~t4_pc~0; {122139#false} is VALID [2022-02-21 04:23:43,824 INFO L290 TraceCheckUtils]: 73: Hoare triple {122139#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {122139#false} is VALID [2022-02-21 04:23:43,824 INFO L290 TraceCheckUtils]: 74: Hoare triple {122139#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {122139#false} is VALID [2022-02-21 04:23:43,824 INFO L290 TraceCheckUtils]: 75: Hoare triple {122139#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 76: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___3~0#1); {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 77: Hoare triple {122139#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 78: Hoare triple {122139#false} assume !(1 == ~t5_pc~0); {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 79: Hoare triple {122139#false} is_transmit5_triggered_~__retres1~5#1 := 0; {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 80: Hoare triple {122139#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 81: Hoare triple {122139#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 82: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___4~0#1); {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 83: Hoare triple {122139#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 84: Hoare triple {122139#false} assume 1 == ~t6_pc~0; {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 85: Hoare triple {122139#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {122139#false} is VALID [2022-02-21 04:23:43,825 INFO L290 TraceCheckUtils]: 86: Hoare triple {122139#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {122139#false} is VALID [2022-02-21 04:23:43,826 INFO L290 TraceCheckUtils]: 87: Hoare triple {122139#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {122139#false} is VALID [2022-02-21 04:23:43,826 INFO L290 TraceCheckUtils]: 88: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___5~0#1); {122139#false} is VALID [2022-02-21 04:23:43,826 INFO L290 TraceCheckUtils]: 89: Hoare triple {122139#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {122139#false} is VALID [2022-02-21 04:23:43,826 INFO L290 TraceCheckUtils]: 90: Hoare triple {122139#false} assume !(1 == ~t7_pc~0); {122139#false} is VALID [2022-02-21 04:23:43,826 INFO L290 TraceCheckUtils]: 91: Hoare triple {122139#false} is_transmit7_triggered_~__retres1~7#1 := 0; {122139#false} is VALID [2022-02-21 04:23:43,826 INFO L290 TraceCheckUtils]: 92: Hoare triple {122139#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {122139#false} is VALID [2022-02-21 04:23:43,826 INFO L290 TraceCheckUtils]: 93: Hoare triple {122139#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {122139#false} is VALID [2022-02-21 04:23:43,826 INFO L290 TraceCheckUtils]: 94: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___6~0#1); {122139#false} is VALID [2022-02-21 04:23:43,826 INFO L290 TraceCheckUtils]: 95: Hoare triple {122139#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {122139#false} is VALID [2022-02-21 04:23:43,826 INFO L290 TraceCheckUtils]: 96: Hoare triple {122139#false} assume 1 == ~t8_pc~0; {122139#false} is VALID [2022-02-21 04:23:43,827 INFO L290 TraceCheckUtils]: 97: Hoare triple {122139#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {122139#false} is VALID [2022-02-21 04:23:43,827 INFO L290 TraceCheckUtils]: 98: Hoare triple {122139#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {122139#false} is VALID [2022-02-21 04:23:43,827 INFO L290 TraceCheckUtils]: 99: Hoare triple {122139#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {122139#false} is VALID [2022-02-21 04:23:43,827 INFO L290 TraceCheckUtils]: 100: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___7~0#1); {122139#false} is VALID [2022-02-21 04:23:43,827 INFO L290 TraceCheckUtils]: 101: Hoare triple {122139#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {122139#false} is VALID [2022-02-21 04:23:43,827 INFO L290 TraceCheckUtils]: 102: Hoare triple {122139#false} assume 1 == ~t9_pc~0; {122139#false} is VALID [2022-02-21 04:23:43,827 INFO L290 TraceCheckUtils]: 103: Hoare triple {122139#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {122139#false} is VALID [2022-02-21 04:23:43,827 INFO L290 TraceCheckUtils]: 104: Hoare triple {122139#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {122139#false} is VALID [2022-02-21 04:23:43,827 INFO L290 TraceCheckUtils]: 105: Hoare triple {122139#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {122139#false} is VALID [2022-02-21 04:23:43,827 INFO L290 TraceCheckUtils]: 106: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___8~0#1); {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 107: Hoare triple {122139#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 108: Hoare triple {122139#false} assume !(1 == ~t10_pc~0); {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 109: Hoare triple {122139#false} is_transmit10_triggered_~__retres1~10#1 := 0; {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 110: Hoare triple {122139#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 111: Hoare triple {122139#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 112: Hoare triple {122139#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 113: Hoare triple {122139#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 114: Hoare triple {122139#false} assume 1 == ~t11_pc~0; {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 115: Hoare triple {122139#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 116: Hoare triple {122139#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {122139#false} is VALID [2022-02-21 04:23:43,828 INFO L290 TraceCheckUtils]: 117: Hoare triple {122139#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {122139#false} is VALID [2022-02-21 04:23:43,829 INFO L290 TraceCheckUtils]: 118: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___10~0#1); {122139#false} is VALID [2022-02-21 04:23:43,829 INFO L290 TraceCheckUtils]: 119: Hoare triple {122139#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {122139#false} is VALID [2022-02-21 04:23:43,829 INFO L290 TraceCheckUtils]: 120: Hoare triple {122139#false} assume !(1 == ~t12_pc~0); {122139#false} is VALID [2022-02-21 04:23:43,829 INFO L290 TraceCheckUtils]: 121: Hoare triple {122139#false} is_transmit12_triggered_~__retres1~12#1 := 0; {122139#false} is VALID [2022-02-21 04:23:43,829 INFO L290 TraceCheckUtils]: 122: Hoare triple {122139#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {122139#false} is VALID [2022-02-21 04:23:43,829 INFO L290 TraceCheckUtils]: 123: Hoare triple {122139#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {122139#false} is VALID [2022-02-21 04:23:43,829 INFO L290 TraceCheckUtils]: 124: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___11~0#1); {122139#false} is VALID [2022-02-21 04:23:43,829 INFO L290 TraceCheckUtils]: 125: Hoare triple {122139#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {122139#false} is VALID [2022-02-21 04:23:43,829 INFO L290 TraceCheckUtils]: 126: Hoare triple {122139#false} assume 1 == ~t13_pc~0; {122139#false} is VALID [2022-02-21 04:23:43,829 INFO L290 TraceCheckUtils]: 127: Hoare triple {122139#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {122139#false} is VALID [2022-02-21 04:23:43,830 INFO L290 TraceCheckUtils]: 128: Hoare triple {122139#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {122139#false} is VALID [2022-02-21 04:23:43,830 INFO L290 TraceCheckUtils]: 129: Hoare triple {122139#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {122139#false} is VALID [2022-02-21 04:23:43,830 INFO L290 TraceCheckUtils]: 130: Hoare triple {122139#false} assume !(0 != activate_threads_~tmp___12~0#1); {122139#false} is VALID [2022-02-21 04:23:43,830 INFO L290 TraceCheckUtils]: 131: Hoare triple {122139#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {122139#false} is VALID [2022-02-21 04:23:43,830 INFO L290 TraceCheckUtils]: 132: Hoare triple {122139#false} assume !(1 == ~M_E~0); {122139#false} is VALID [2022-02-21 04:23:43,830 INFO L290 TraceCheckUtils]: 133: Hoare triple {122139#false} assume !(1 == ~T1_E~0); {122139#false} is VALID [2022-02-21 04:23:43,830 INFO L290 TraceCheckUtils]: 134: Hoare triple {122139#false} assume !(1 == ~T2_E~0); {122139#false} is VALID [2022-02-21 04:23:43,830 INFO L290 TraceCheckUtils]: 135: Hoare triple {122139#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {122139#false} is VALID [2022-02-21 04:23:43,830 INFO L290 TraceCheckUtils]: 136: Hoare triple {122139#false} assume !(1 == ~T4_E~0); {122139#false} is VALID [2022-02-21 04:23:43,830 INFO L290 TraceCheckUtils]: 137: Hoare triple {122139#false} assume !(1 == ~T5_E~0); {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 138: Hoare triple {122139#false} assume !(1 == ~T6_E~0); {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 139: Hoare triple {122139#false} assume !(1 == ~T7_E~0); {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 140: Hoare triple {122139#false} assume !(1 == ~T8_E~0); {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 141: Hoare triple {122139#false} assume !(1 == ~T9_E~0); {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 142: Hoare triple {122139#false} assume !(1 == ~T10_E~0); {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 143: Hoare triple {122139#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 144: Hoare triple {122139#false} assume !(1 == ~T12_E~0); {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 145: Hoare triple {122139#false} assume !(1 == ~T13_E~0); {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 146: Hoare triple {122139#false} assume !(1 == ~E_M~0); {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 147: Hoare triple {122139#false} assume !(1 == ~E_1~0); {122139#false} is VALID [2022-02-21 04:23:43,831 INFO L290 TraceCheckUtils]: 148: Hoare triple {122139#false} assume !(1 == ~E_2~0); {122139#false} is VALID [2022-02-21 04:23:43,832 INFO L290 TraceCheckUtils]: 149: Hoare triple {122139#false} assume !(1 == ~E_3~0); {122139#false} is VALID [2022-02-21 04:23:43,832 INFO L290 TraceCheckUtils]: 150: Hoare triple {122139#false} assume !(1 == ~E_4~0); {122139#false} is VALID [2022-02-21 04:23:43,832 INFO L290 TraceCheckUtils]: 151: Hoare triple {122139#false} assume 1 == ~E_5~0;~E_5~0 := 2; {122139#false} is VALID [2022-02-21 04:23:43,832 INFO L290 TraceCheckUtils]: 152: Hoare triple {122139#false} assume !(1 == ~E_6~0); {122139#false} is VALID [2022-02-21 04:23:43,832 INFO L290 TraceCheckUtils]: 153: Hoare triple {122139#false} assume !(1 == ~E_7~0); {122139#false} is VALID [2022-02-21 04:23:43,832 INFO L290 TraceCheckUtils]: 154: Hoare triple {122139#false} assume !(1 == ~E_8~0); {122139#false} is VALID [2022-02-21 04:23:43,832 INFO L290 TraceCheckUtils]: 155: Hoare triple {122139#false} assume !(1 == ~E_9~0); {122139#false} is VALID [2022-02-21 04:23:43,832 INFO L290 TraceCheckUtils]: 156: Hoare triple {122139#false} assume !(1 == ~E_10~0); {122139#false} is VALID [2022-02-21 04:23:43,832 INFO L290 TraceCheckUtils]: 157: Hoare triple {122139#false} assume !(1 == ~E_11~0); {122139#false} is VALID [2022-02-21 04:23:43,832 INFO L290 TraceCheckUtils]: 158: Hoare triple {122139#false} assume !(1 == ~E_12~0); {122139#false} is VALID [2022-02-21 04:23:43,833 INFO L290 TraceCheckUtils]: 159: Hoare triple {122139#false} assume 1 == ~E_13~0;~E_13~0 := 2; {122139#false} is VALID [2022-02-21 04:23:43,833 INFO L290 TraceCheckUtils]: 160: Hoare triple {122139#false} assume { :end_inline_reset_delta_events } true; {122139#false} is VALID [2022-02-21 04:23:43,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:43,833 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:43,833 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788830288] [2022-02-21 04:23:43,833 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788830288] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:43,833 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:43,834 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:43,834 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351043508] [2022-02-21 04:23:43,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:43,834 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:43,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:43,834 INFO L85 PathProgramCache]: Analyzing trace with hash -156217939, now seen corresponding path program 1 times [2022-02-21 04:23:43,835 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:43,835 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668841264] [2022-02-21 04:23:43,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:43,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:43,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:43,864 INFO L290 TraceCheckUtils]: 0: Hoare triple {122142#true} assume !false; {122142#true} is VALID [2022-02-21 04:23:43,864 INFO L290 TraceCheckUtils]: 1: Hoare triple {122142#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {122142#true} is VALID [2022-02-21 04:23:43,864 INFO L290 TraceCheckUtils]: 2: Hoare triple {122142#true} assume !false; {122142#true} is VALID [2022-02-21 04:23:43,864 INFO L290 TraceCheckUtils]: 3: Hoare triple {122142#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {122142#true} is VALID [2022-02-21 04:23:43,864 INFO L290 TraceCheckUtils]: 4: Hoare triple {122142#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {122142#true} is VALID [2022-02-21 04:23:43,864 INFO L290 TraceCheckUtils]: 5: Hoare triple {122142#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {122142#true} is VALID [2022-02-21 04:23:43,864 INFO L290 TraceCheckUtils]: 6: Hoare triple {122142#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {122142#true} is VALID [2022-02-21 04:23:43,865 INFO L290 TraceCheckUtils]: 7: Hoare triple {122142#true} assume !(0 != eval_~tmp~0#1); {122142#true} is VALID [2022-02-21 04:23:43,865 INFO L290 TraceCheckUtils]: 8: Hoare triple {122142#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {122142#true} is VALID [2022-02-21 04:23:43,865 INFO L290 TraceCheckUtils]: 9: Hoare triple {122142#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {122142#true} is VALID [2022-02-21 04:23:43,865 INFO L290 TraceCheckUtils]: 10: Hoare triple {122142#true} assume !(0 == ~M_E~0); {122142#true} is VALID [2022-02-21 04:23:43,865 INFO L290 TraceCheckUtils]: 11: Hoare triple {122142#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {122142#true} is VALID [2022-02-21 04:23:43,865 INFO L290 TraceCheckUtils]: 12: Hoare triple {122142#true} assume !(0 == ~T2_E~0); {122142#true} is VALID [2022-02-21 04:23:43,865 INFO L290 TraceCheckUtils]: 13: Hoare triple {122142#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {122142#true} is VALID [2022-02-21 04:23:43,865 INFO L290 TraceCheckUtils]: 14: Hoare triple {122142#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {122142#true} is VALID [2022-02-21 04:23:43,865 INFO L290 TraceCheckUtils]: 15: Hoare triple {122142#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {122142#true} is VALID [2022-02-21 04:23:43,866 INFO L290 TraceCheckUtils]: 16: Hoare triple {122142#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {122142#true} is VALID [2022-02-21 04:23:43,866 INFO L290 TraceCheckUtils]: 17: Hoare triple {122142#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {122142#true} is VALID [2022-02-21 04:23:43,866 INFO L290 TraceCheckUtils]: 18: Hoare triple {122142#true} assume 0 == ~T8_E~0;~T8_E~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,866 INFO L290 TraceCheckUtils]: 19: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,867 INFO L290 TraceCheckUtils]: 20: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(0 == ~T10_E~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,867 INFO L290 TraceCheckUtils]: 21: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,867 INFO L290 TraceCheckUtils]: 22: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,867 INFO L290 TraceCheckUtils]: 23: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,868 INFO L290 TraceCheckUtils]: 24: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,868 INFO L290 TraceCheckUtils]: 25: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,868 INFO L290 TraceCheckUtils]: 26: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,869 INFO L290 TraceCheckUtils]: 27: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,869 INFO L290 TraceCheckUtils]: 28: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(0 == ~E_4~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,869 INFO L290 TraceCheckUtils]: 29: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,870 INFO L290 TraceCheckUtils]: 30: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,870 INFO L290 TraceCheckUtils]: 31: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,870 INFO L290 TraceCheckUtils]: 32: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,870 INFO L290 TraceCheckUtils]: 33: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,871 INFO L290 TraceCheckUtils]: 34: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,871 INFO L290 TraceCheckUtils]: 35: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,871 INFO L290 TraceCheckUtils]: 36: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(0 == ~E_12~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,872 INFO L290 TraceCheckUtils]: 37: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,872 INFO L290 TraceCheckUtils]: 38: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,872 INFO L290 TraceCheckUtils]: 39: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~m_pc~0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,873 INFO L290 TraceCheckUtils]: 40: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,873 INFO L290 TraceCheckUtils]: 41: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,873 INFO L290 TraceCheckUtils]: 42: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,873 INFO L290 TraceCheckUtils]: 43: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,874 INFO L290 TraceCheckUtils]: 44: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,874 INFO L290 TraceCheckUtils]: 45: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t1_pc~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,874 INFO L290 TraceCheckUtils]: 46: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,875 INFO L290 TraceCheckUtils]: 47: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,875 INFO L290 TraceCheckUtils]: 48: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,875 INFO L290 TraceCheckUtils]: 49: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,875 INFO L290 TraceCheckUtils]: 50: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,876 INFO L290 TraceCheckUtils]: 51: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t2_pc~0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,876 INFO L290 TraceCheckUtils]: 52: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,876 INFO L290 TraceCheckUtils]: 53: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,877 INFO L290 TraceCheckUtils]: 54: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,877 INFO L290 TraceCheckUtils]: 55: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,877 INFO L290 TraceCheckUtils]: 56: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,877 INFO L290 TraceCheckUtils]: 57: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t3_pc~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,878 INFO L290 TraceCheckUtils]: 58: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,878 INFO L290 TraceCheckUtils]: 59: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,878 INFO L290 TraceCheckUtils]: 60: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,879 INFO L290 TraceCheckUtils]: 61: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,879 INFO L290 TraceCheckUtils]: 62: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,879 INFO L290 TraceCheckUtils]: 63: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t4_pc~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,879 INFO L290 TraceCheckUtils]: 64: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,880 INFO L290 TraceCheckUtils]: 65: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,880 INFO L290 TraceCheckUtils]: 66: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,880 INFO L290 TraceCheckUtils]: 67: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,881 INFO L290 TraceCheckUtils]: 68: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,881 INFO L290 TraceCheckUtils]: 69: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t5_pc~0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,881 INFO L290 TraceCheckUtils]: 70: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,881 INFO L290 TraceCheckUtils]: 71: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,882 INFO L290 TraceCheckUtils]: 72: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,882 INFO L290 TraceCheckUtils]: 73: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,882 INFO L290 TraceCheckUtils]: 74: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,882 INFO L290 TraceCheckUtils]: 75: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t6_pc~0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,883 INFO L290 TraceCheckUtils]: 76: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,883 INFO L290 TraceCheckUtils]: 77: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,883 INFO L290 TraceCheckUtils]: 78: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,884 INFO L290 TraceCheckUtils]: 79: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,884 INFO L290 TraceCheckUtils]: 80: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,884 INFO L290 TraceCheckUtils]: 81: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t7_pc~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,884 INFO L290 TraceCheckUtils]: 82: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,885 INFO L290 TraceCheckUtils]: 83: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,885 INFO L290 TraceCheckUtils]: 84: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,885 INFO L290 TraceCheckUtils]: 85: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,886 INFO L290 TraceCheckUtils]: 86: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,886 INFO L290 TraceCheckUtils]: 87: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t8_pc~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,886 INFO L290 TraceCheckUtils]: 88: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,886 INFO L290 TraceCheckUtils]: 89: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,887 INFO L290 TraceCheckUtils]: 90: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,887 INFO L290 TraceCheckUtils]: 91: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,887 INFO L290 TraceCheckUtils]: 92: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,888 INFO L290 TraceCheckUtils]: 93: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t9_pc~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,888 INFO L290 TraceCheckUtils]: 94: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,888 INFO L290 TraceCheckUtils]: 95: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,888 INFO L290 TraceCheckUtils]: 96: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,889 INFO L290 TraceCheckUtils]: 97: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,889 INFO L290 TraceCheckUtils]: 98: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,889 INFO L290 TraceCheckUtils]: 99: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t10_pc~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,890 INFO L290 TraceCheckUtils]: 100: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,890 INFO L290 TraceCheckUtils]: 101: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,890 INFO L290 TraceCheckUtils]: 102: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,890 INFO L290 TraceCheckUtils]: 103: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,891 INFO L290 TraceCheckUtils]: 104: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,891 INFO L290 TraceCheckUtils]: 105: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t11_pc~0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,891 INFO L290 TraceCheckUtils]: 106: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,892 INFO L290 TraceCheckUtils]: 107: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,892 INFO L290 TraceCheckUtils]: 108: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,892 INFO L290 TraceCheckUtils]: 109: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,892 INFO L290 TraceCheckUtils]: 110: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,893 INFO L290 TraceCheckUtils]: 111: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t12_pc~0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,893 INFO L290 TraceCheckUtils]: 112: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,893 INFO L290 TraceCheckUtils]: 113: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,907 INFO L290 TraceCheckUtils]: 114: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,907 INFO L290 TraceCheckUtils]: 115: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,908 INFO L290 TraceCheckUtils]: 116: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,908 INFO L290 TraceCheckUtils]: 117: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t13_pc~0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,908 INFO L290 TraceCheckUtils]: 118: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,909 INFO L290 TraceCheckUtils]: 119: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,909 INFO L290 TraceCheckUtils]: 120: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,909 INFO L290 TraceCheckUtils]: 121: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,909 INFO L290 TraceCheckUtils]: 122: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,910 INFO L290 TraceCheckUtils]: 123: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~M_E~0); {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,910 INFO L290 TraceCheckUtils]: 124: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,910 INFO L290 TraceCheckUtils]: 125: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,910 INFO L290 TraceCheckUtils]: 126: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,911 INFO L290 TraceCheckUtils]: 127: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,911 INFO L290 TraceCheckUtils]: 128: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,911 INFO L290 TraceCheckUtils]: 129: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,911 INFO L290 TraceCheckUtils]: 130: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {122144#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:23:43,912 INFO L290 TraceCheckUtils]: 131: Hoare triple {122144#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~T8_E~0); {122143#false} is VALID [2022-02-21 04:23:43,912 INFO L290 TraceCheckUtils]: 132: Hoare triple {122143#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,912 INFO L290 TraceCheckUtils]: 133: Hoare triple {122143#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,912 INFO L290 TraceCheckUtils]: 134: Hoare triple {122143#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,912 INFO L290 TraceCheckUtils]: 135: Hoare triple {122143#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,912 INFO L290 TraceCheckUtils]: 136: Hoare triple {122143#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,912 INFO L290 TraceCheckUtils]: 137: Hoare triple {122143#false} assume 1 == ~E_M~0;~E_M~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,912 INFO L290 TraceCheckUtils]: 138: Hoare triple {122143#false} assume 1 == ~E_1~0;~E_1~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,913 INFO L290 TraceCheckUtils]: 139: Hoare triple {122143#false} assume !(1 == ~E_2~0); {122143#false} is VALID [2022-02-21 04:23:43,913 INFO L290 TraceCheckUtils]: 140: Hoare triple {122143#false} assume 1 == ~E_3~0;~E_3~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,913 INFO L290 TraceCheckUtils]: 141: Hoare triple {122143#false} assume 1 == ~E_4~0;~E_4~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,913 INFO L290 TraceCheckUtils]: 142: Hoare triple {122143#false} assume 1 == ~E_5~0;~E_5~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,913 INFO L290 TraceCheckUtils]: 143: Hoare triple {122143#false} assume 1 == ~E_6~0;~E_6~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,913 INFO L290 TraceCheckUtils]: 144: Hoare triple {122143#false} assume 1 == ~E_7~0;~E_7~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,913 INFO L290 TraceCheckUtils]: 145: Hoare triple {122143#false} assume 1 == ~E_8~0;~E_8~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,913 INFO L290 TraceCheckUtils]: 146: Hoare triple {122143#false} assume 1 == ~E_9~0;~E_9~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,913 INFO L290 TraceCheckUtils]: 147: Hoare triple {122143#false} assume !(1 == ~E_10~0); {122143#false} is VALID [2022-02-21 04:23:43,913 INFO L290 TraceCheckUtils]: 148: Hoare triple {122143#false} assume 1 == ~E_11~0;~E_11~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,914 INFO L290 TraceCheckUtils]: 149: Hoare triple {122143#false} assume 1 == ~E_12~0;~E_12~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,914 INFO L290 TraceCheckUtils]: 150: Hoare triple {122143#false} assume 1 == ~E_13~0;~E_13~0 := 2; {122143#false} is VALID [2022-02-21 04:23:43,914 INFO L290 TraceCheckUtils]: 151: Hoare triple {122143#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {122143#false} is VALID [2022-02-21 04:23:43,914 INFO L290 TraceCheckUtils]: 152: Hoare triple {122143#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {122143#false} is VALID [2022-02-21 04:23:43,914 INFO L290 TraceCheckUtils]: 153: Hoare triple {122143#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {122143#false} is VALID [2022-02-21 04:23:43,914 INFO L290 TraceCheckUtils]: 154: Hoare triple {122143#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {122143#false} is VALID [2022-02-21 04:23:43,914 INFO L290 TraceCheckUtils]: 155: Hoare triple {122143#false} assume !(0 == start_simulation_~tmp~3#1); {122143#false} is VALID [2022-02-21 04:23:43,914 INFO L290 TraceCheckUtils]: 156: Hoare triple {122143#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {122143#false} is VALID [2022-02-21 04:23:43,914 INFO L290 TraceCheckUtils]: 157: Hoare triple {122143#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {122143#false} is VALID [2022-02-21 04:23:43,914 INFO L290 TraceCheckUtils]: 158: Hoare triple {122143#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {122143#false} is VALID [2022-02-21 04:23:43,915 INFO L290 TraceCheckUtils]: 159: Hoare triple {122143#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {122143#false} is VALID [2022-02-21 04:23:43,915 INFO L290 TraceCheckUtils]: 160: Hoare triple {122143#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {122143#false} is VALID [2022-02-21 04:23:43,915 INFO L290 TraceCheckUtils]: 161: Hoare triple {122143#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {122143#false} is VALID [2022-02-21 04:23:43,915 INFO L290 TraceCheckUtils]: 162: Hoare triple {122143#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {122143#false} is VALID [2022-02-21 04:23:43,915 INFO L290 TraceCheckUtils]: 163: Hoare triple {122143#false} assume !(0 != start_simulation_~tmp___0~1#1); {122143#false} is VALID [2022-02-21 04:23:43,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:43,915 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:43,916 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668841264] [2022-02-21 04:23:43,916 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668841264] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:43,917 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:43,917 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:43,917 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175148116] [2022-02-21 04:23:43,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:43,917 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:43,917 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:43,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:43,918 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:43,918 INFO L87 Difference]: Start difference. First operand 3761 states and 5528 transitions. cyclomatic complexity: 1768 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:48,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:48,091 INFO L93 Difference]: Finished difference Result 5496 states and 8063 transitions. [2022-02-21 04:23:48,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:48,092 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:48,149 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:48,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5496 states and 8063 transitions. [2022-02-21 04:23:49,063 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5301 [2022-02-21 04:23:49,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5496 states to 5496 states and 8063 transitions. [2022-02-21 04:23:49,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5496 [2022-02-21 04:23:49,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5496 [2022-02-21 04:23:49,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5496 states and 8063 transitions. [2022-02-21 04:23:49,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:49,956 INFO L681 BuchiCegarLoop]: Abstraction has 5496 states and 8063 transitions. [2022-02-21 04:23:49,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5496 states and 8063 transitions. [2022-02-21 04:23:49,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5496 to 3761. [2022-02-21 04:23:49,993 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:49,996 INFO L82 GeneralOperation]: Start isEquivalent. First operand 5496 states and 8063 transitions. Second operand has 3761 states, 3761 states have (on average 1.4690241956926349) internal successors, (5525), 3760 states have internal predecessors, (5525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:49,997 INFO L74 IsIncluded]: Start isIncluded. First operand 5496 states and 8063 transitions. Second operand has 3761 states, 3761 states have (on average 1.4690241956926349) internal successors, (5525), 3760 states have internal predecessors, (5525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:49,999 INFO L87 Difference]: Start difference. First operand 5496 states and 8063 transitions. Second operand has 3761 states, 3761 states have (on average 1.4690241956926349) internal successors, (5525), 3760 states have internal predecessors, (5525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:50,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:50,669 INFO L93 Difference]: Finished difference Result 5496 states and 8063 transitions. [2022-02-21 04:23:50,669 INFO L276 IsEmpty]: Start isEmpty. Operand 5496 states and 8063 transitions. [2022-02-21 04:23:50,673 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:50,673 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:50,676 INFO L74 IsIncluded]: Start isIncluded. First operand has 3761 states, 3761 states have (on average 1.4690241956926349) internal successors, (5525), 3760 states have internal predecessors, (5525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5496 states and 8063 transitions. [2022-02-21 04:23:50,678 INFO L87 Difference]: Start difference. First operand has 3761 states, 3761 states have (on average 1.4690241956926349) internal successors, (5525), 3760 states have internal predecessors, (5525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5496 states and 8063 transitions. [2022-02-21 04:23:51,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:51,403 INFO L93 Difference]: Finished difference Result 5496 states and 8063 transitions. [2022-02-21 04:23:51,403 INFO L276 IsEmpty]: Start isEmpty. Operand 5496 states and 8063 transitions. [2022-02-21 04:23:51,407 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:51,407 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:51,407 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:51,407 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:51,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4690241956926349) internal successors, (5525), 3760 states have internal predecessors, (5525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:51,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5525 transitions. [2022-02-21 04:23:51,737 INFO L704 BuchiCegarLoop]: Abstraction has 3761 states and 5525 transitions. [2022-02-21 04:23:51,737 INFO L587 BuchiCegarLoop]: Abstraction has 3761 states and 5525 transitions. [2022-02-21 04:23:51,737 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:23:51,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5525 transitions. [2022-02-21 04:23:51,742 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-02-21 04:23:51,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:51,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:51,744 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:51,744 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:51,744 INFO L791 eck$LassoCheckResult]: Stem: 128560#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 128561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 129597#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 129051#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 129052#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 128542#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 128543#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 128607#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 128608#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 129049#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 129050#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 128575#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 128392#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 128393#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 128837#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 128838#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 128718#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 128719#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 128363#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 128364#L1279 assume !(0 == ~M_E~0); 129589#L1279-2 assume !(0 == ~T1_E~0); 127986#L1284-1 assume !(0 == ~T2_E~0); 127987#L1289-1 assume !(0 == ~T3_E~0); 128710#L1294-1 assume !(0 == ~T4_E~0); 128711#L1299-1 assume !(0 == ~T5_E~0); 128722#L1304-1 assume !(0 == ~T6_E~0); 129656#L1309-1 assume !(0 == ~T7_E~0); 129657#L1314-1 assume !(0 == ~T8_E~0); 127918#L1319-1 assume !(0 == ~T9_E~0); 127919#L1324-1 assume !(0 == ~T10_E~0); 128089#L1329-1 assume !(0 == ~T11_E~0); 128090#L1334-1 assume !(0 == ~T12_E~0); 129495#L1339-1 assume !(0 == ~T13_E~0); 129578#L1344-1 assume !(0 == ~E_M~0); 129579#L1349-1 assume !(0 == ~E_1~0); 128899#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 128900#L1359-1 assume !(0 == ~E_3~0); 129328#L1364-1 assume !(0 == ~E_4~0); 128218#L1369-1 assume !(0 == ~E_5~0); 128219#L1374-1 assume !(0 == ~E_6~0); 128905#L1379-1 assume !(0 == ~E_7~0); 128906#L1384-1 assume !(0 == ~E_8~0); 128981#L1389-1 assume !(0 == ~E_9~0); 129515#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 129516#L1399-1 assume !(0 == ~E_11~0); 129619#L1404-1 assume !(0 == ~E_12~0); 128311#L1409-1 assume !(0 == ~E_13~0); 128312#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129611#L628 assume !(1 == ~m_pc~0); 128215#L628-2 is_master_triggered_~__retres1~0#1 := 0; 128214#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128979#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 128980#L1591 assume !(0 != activate_threads_~tmp~1#1); 129624#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 128766#L647 assume 1 == ~t1_pc~0; 128135#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 128136#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 128407#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 128408#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 129564#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129565#L666 assume 1 == ~t2_pc~0; 127983#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 127984#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 128154#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 129581#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 129099#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 129100#L685 assume !(1 == ~t3_pc~0); 129207#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 129206#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 128828#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 128829#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 128949#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128434#L704 assume 1 == ~t4_pc~0; 128435#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 128960#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 128961#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 129602#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 128819#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128820#L723 assume !(1 == ~t5_pc~0); 128945#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 129181#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 129323#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 129081#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 129082#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 128201#L742 assume 1 == ~t6_pc~0; 128202#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 128349#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 128350#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 127887#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 127888#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 128277#L761 assume !(1 == ~t7_pc~0); 128278#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 128148#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 128149#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 128951#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 128952#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 127910#L780 assume 1 == ~t8_pc~0; 127911#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 128187#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 128188#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 128912#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 128913#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 129034#L799 assume 1 == ~t9_pc~0; 129146#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 127913#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 127914#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 129043#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 129252#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 129062#L818 assume !(1 == ~t10_pc~0); 127696#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 127697#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 129138#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 129065#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 129066#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 129106#L837 assume 1 == ~t11_pc~0; 129107#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 128942#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 129344#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 129024#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 129025#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 128780#L856 assume !(1 == ~t12_pc~0); 128781#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 129430#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 129431#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 129412#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 129413#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 129592#L875 assume 1 == ~t13_pc~0; 128720#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 128352#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 128353#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 128292#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 128293#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129133#L1427 assume !(1 == ~M_E~0); 129119#L1427-2 assume !(1 == ~T1_E~0); 128264#L1432-1 assume !(1 == ~T2_E~0); 128265#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 129334#L1442-1 assume !(1 == ~T4_E~0); 129335#L1447-1 assume !(1 == ~T5_E~0); 129192#L1452-1 assume !(1 == ~T6_E~0); 127829#L1457-1 assume !(1 == ~T7_E~0); 127830#L1462-1 assume !(1 == ~T8_E~0); 129361#L1467-1 assume !(1 == ~T9_E~0); 129379#L1472-1 assume !(1 == ~T10_E~0); 129380#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 129131#L1482-1 assume !(1 == ~T12_E~0); 129132#L1487-1 assume !(1 == ~T13_E~0); 128162#L1492-1 assume !(1 == ~E_M~0); 128163#L1497-1 assume !(1 == ~E_1~0); 128522#L1502-1 assume !(1 == ~E_2~0); 128523#L1507-1 assume !(1 == ~E_3~0); 128038#L1512-1 assume !(1 == ~E_4~0); 128039#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 129450#L1522-1 assume !(1 == ~E_6~0); 128764#L1527-1 assume !(1 == ~E_7~0); 128765#L1532-1 assume !(1 == ~E_8~0); 129641#L1537-1 assume !(1 == ~E_9~0); 128969#L1542-1 assume !(1 == ~E_10~0); 128798#L1547-1 assume !(1 == ~E_11~0); 128799#L1552-1 assume !(1 == ~E_12~0); 127735#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 127736#L1562-1 assume { :end_inline_reset_delta_events } true; 128340#L1928-2 [2022-02-21 04:23:51,744 INFO L793 eck$LassoCheckResult]: Loop: 128340#L1928-2 assume !false; 128831#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 127994#L1254 assume !false; 128584#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 128068#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 128069#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 128266#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 129438#L1067 assume !(0 != eval_~tmp~0#1); 128509#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 128087#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 128088#L1279-3 assume !(0 == ~M_E~0); 128544#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 128527#L1284-3 assume !(0 == ~T2_E~0); 128528#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 128505#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 128506#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 128894#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 128895#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 128403#L1314-3 assume !(0 == ~T8_E~0); 128404#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 129401#L1324-3 assume !(0 == ~T10_E~0); 128035#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 128036#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 128807#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 128808#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 129103#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 128384#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 128385#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 129113#L1364-3 assume !(0 == ~E_4~0); 129638#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 129533#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 128164#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 128165#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 128382#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 128383#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 128673#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 129543#L1404-3 assume !(0 == ~E_12~0); 129507#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 129508#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 128993#L628-45 assume !(1 == ~m_pc~0); 128671#L628-47 is_master_triggered_~__retres1~0#1 := 0; 128672#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128029#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 128030#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 128418#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129142#L647-45 assume 1 == ~t1_pc~0; 127980#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 127981#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 128910#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 128094#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 128095#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128306#L666-45 assume !(1 == ~t2_pc~0); 128307#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 128788#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 129351#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 129266#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 129260#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127844#L685-45 assume 1 == ~t3_pc~0; 127845#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 128903#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 129580#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 129448#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 129449#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 129590#L704-45 assume 1 == ~t4_pc~0; 129468#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 127711#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 128570#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 128914#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 129663#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 129026#L723-45 assume !(1 == ~t5_pc~0); 129027#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 129517#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 128617#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 128394#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 128395#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 129420#L742-45 assume !(1 == ~t6_pc~0); 128641#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 128642#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 129112#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 129148#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 129149#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 129237#L761-45 assume 1 == ~t7_pc~0; 129239#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 128635#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 128636#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 128042#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 128043#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 129511#L780-45 assume !(1 == ~t8_pc~0); 128421#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 128054#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 128055#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 129639#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 128024#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 128025#L799-45 assume 1 == ~t9_pc~0; 128801#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 128246#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 129563#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 129190#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 129191#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 127962#L818-45 assume 1 == ~t10_pc~0; 127963#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 128081#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 129165#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 128567#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 128568#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 129285#L837-45 assume !(1 == ~t11_pc~0); 128498#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 128499#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 128637#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 129303#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 128100#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 128101#L856-45 assume 1 == ~t12_pc~0; 129588#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 128103#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 128044#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 128045#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 128907#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 128908#L875-45 assume !(1 == ~t13_pc~0); 128881#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 128880#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 128940#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 129555#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 129556#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129494#L1427-3 assume !(1 == ~M_E~0); 128704#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 128705#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 129244#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 128896#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 128897#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 127752#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 127753#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 129436#L1462-3 assume !(1 == ~T8_E~0); 129437#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 129300#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 129301#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 128003#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 128004#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 128145#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 128318#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 128319#L1502-3 assume !(1 == ~E_2~0); 129268#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 129399#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 128356#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 128048#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 128049#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 128013#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 128014#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 129115#L1542-3 assume !(1 == ~E_10~0); 129253#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 128882#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 128883#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 128224#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 128225#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 127644#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 128409#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 128410#L1947 assume !(0 == start_simulation_~tmp~3#1); 129016#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 129221#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 128281#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 129615#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 129539#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 129368#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129127#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 129128#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 128340#L1928-2 [2022-02-21 04:23:51,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:51,745 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2022-02-21 04:23:51,745 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:51,745 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549790184] [2022-02-21 04:23:51,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:51,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:51,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:51,773 INFO L290 TraceCheckUtils]: 0: Hoare triple {142399#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,773 INFO L290 TraceCheckUtils]: 1: Hoare triple {142401#(<= 2 ~E_2~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,773 INFO L290 TraceCheckUtils]: 2: Hoare triple {142401#(<= 2 ~E_2~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,774 INFO L290 TraceCheckUtils]: 3: Hoare triple {142401#(<= 2 ~E_2~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,774 INFO L290 TraceCheckUtils]: 4: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,774 INFO L290 TraceCheckUtils]: 5: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,775 INFO L290 TraceCheckUtils]: 6: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,775 INFO L290 TraceCheckUtils]: 7: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,775 INFO L290 TraceCheckUtils]: 8: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,775 INFO L290 TraceCheckUtils]: 9: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,776 INFO L290 TraceCheckUtils]: 10: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,776 INFO L290 TraceCheckUtils]: 11: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,776 INFO L290 TraceCheckUtils]: 12: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,776 INFO L290 TraceCheckUtils]: 13: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,777 INFO L290 TraceCheckUtils]: 14: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,777 INFO L290 TraceCheckUtils]: 15: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,777 INFO L290 TraceCheckUtils]: 16: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,777 INFO L290 TraceCheckUtils]: 17: Hoare triple {142401#(<= 2 ~E_2~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,778 INFO L290 TraceCheckUtils]: 18: Hoare triple {142401#(<= 2 ~E_2~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,778 INFO L290 TraceCheckUtils]: 19: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~M_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,778 INFO L290 TraceCheckUtils]: 20: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T1_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,778 INFO L290 TraceCheckUtils]: 21: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T2_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,779 INFO L290 TraceCheckUtils]: 22: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T3_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,779 INFO L290 TraceCheckUtils]: 23: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T4_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,779 INFO L290 TraceCheckUtils]: 24: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T5_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,779 INFO L290 TraceCheckUtils]: 25: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T6_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,780 INFO L290 TraceCheckUtils]: 26: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T7_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,780 INFO L290 TraceCheckUtils]: 27: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T8_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,780 INFO L290 TraceCheckUtils]: 28: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T9_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,780 INFO L290 TraceCheckUtils]: 29: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T10_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,781 INFO L290 TraceCheckUtils]: 30: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T11_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,781 INFO L290 TraceCheckUtils]: 31: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T12_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,781 INFO L290 TraceCheckUtils]: 32: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~T13_E~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,781 INFO L290 TraceCheckUtils]: 33: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~E_M~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,782 INFO L290 TraceCheckUtils]: 34: Hoare triple {142401#(<= 2 ~E_2~0)} assume !(0 == ~E_1~0); {142401#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:51,782 INFO L290 TraceCheckUtils]: 35: Hoare triple {142401#(<= 2 ~E_2~0)} assume 0 == ~E_2~0;~E_2~0 := 1; {142400#false} is VALID [2022-02-21 04:23:51,782 INFO L290 TraceCheckUtils]: 36: Hoare triple {142400#false} assume !(0 == ~E_3~0); {142400#false} is VALID [2022-02-21 04:23:51,782 INFO L290 TraceCheckUtils]: 37: Hoare triple {142400#false} assume !(0 == ~E_4~0); {142400#false} is VALID [2022-02-21 04:23:51,782 INFO L290 TraceCheckUtils]: 38: Hoare triple {142400#false} assume !(0 == ~E_5~0); {142400#false} is VALID [2022-02-21 04:23:51,782 INFO L290 TraceCheckUtils]: 39: Hoare triple {142400#false} assume !(0 == ~E_6~0); {142400#false} is VALID [2022-02-21 04:23:51,782 INFO L290 TraceCheckUtils]: 40: Hoare triple {142400#false} assume !(0 == ~E_7~0); {142400#false} is VALID [2022-02-21 04:23:51,783 INFO L290 TraceCheckUtils]: 41: Hoare triple {142400#false} assume !(0 == ~E_8~0); {142400#false} is VALID [2022-02-21 04:23:51,783 INFO L290 TraceCheckUtils]: 42: Hoare triple {142400#false} assume !(0 == ~E_9~0); {142400#false} is VALID [2022-02-21 04:23:51,783 INFO L290 TraceCheckUtils]: 43: Hoare triple {142400#false} assume 0 == ~E_10~0;~E_10~0 := 1; {142400#false} is VALID [2022-02-21 04:23:51,783 INFO L290 TraceCheckUtils]: 44: Hoare triple {142400#false} assume !(0 == ~E_11~0); {142400#false} is VALID [2022-02-21 04:23:51,783 INFO L290 TraceCheckUtils]: 45: Hoare triple {142400#false} assume !(0 == ~E_12~0); {142400#false} is VALID [2022-02-21 04:23:51,783 INFO L290 TraceCheckUtils]: 46: Hoare triple {142400#false} assume !(0 == ~E_13~0); {142400#false} is VALID [2022-02-21 04:23:51,783 INFO L290 TraceCheckUtils]: 47: Hoare triple {142400#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {142400#false} is VALID [2022-02-21 04:23:51,783 INFO L290 TraceCheckUtils]: 48: Hoare triple {142400#false} assume !(1 == ~m_pc~0); {142400#false} is VALID [2022-02-21 04:23:51,783 INFO L290 TraceCheckUtils]: 49: Hoare triple {142400#false} is_master_triggered_~__retres1~0#1 := 0; {142400#false} is VALID [2022-02-21 04:23:51,783 INFO L290 TraceCheckUtils]: 50: Hoare triple {142400#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 51: Hoare triple {142400#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 52: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp~1#1); {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 53: Hoare triple {142400#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 54: Hoare triple {142400#false} assume 1 == ~t1_pc~0; {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 55: Hoare triple {142400#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 56: Hoare triple {142400#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 57: Hoare triple {142400#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 58: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___0~0#1); {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 59: Hoare triple {142400#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 60: Hoare triple {142400#false} assume 1 == ~t2_pc~0; {142400#false} is VALID [2022-02-21 04:23:51,784 INFO L290 TraceCheckUtils]: 61: Hoare triple {142400#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 62: Hoare triple {142400#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 63: Hoare triple {142400#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 64: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___1~0#1); {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 65: Hoare triple {142400#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 66: Hoare triple {142400#false} assume !(1 == ~t3_pc~0); {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 67: Hoare triple {142400#false} is_transmit3_triggered_~__retres1~3#1 := 0; {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 68: Hoare triple {142400#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 69: Hoare triple {142400#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 70: Hoare triple {142400#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 71: Hoare triple {142400#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {142400#false} is VALID [2022-02-21 04:23:51,785 INFO L290 TraceCheckUtils]: 72: Hoare triple {142400#false} assume 1 == ~t4_pc~0; {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 73: Hoare triple {142400#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 74: Hoare triple {142400#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 75: Hoare triple {142400#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 76: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___3~0#1); {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 77: Hoare triple {142400#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 78: Hoare triple {142400#false} assume !(1 == ~t5_pc~0); {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 79: Hoare triple {142400#false} is_transmit5_triggered_~__retres1~5#1 := 0; {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 80: Hoare triple {142400#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 81: Hoare triple {142400#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 82: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___4~0#1); {142400#false} is VALID [2022-02-21 04:23:51,786 INFO L290 TraceCheckUtils]: 83: Hoare triple {142400#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {142400#false} is VALID [2022-02-21 04:23:51,787 INFO L290 TraceCheckUtils]: 84: Hoare triple {142400#false} assume 1 == ~t6_pc~0; {142400#false} is VALID [2022-02-21 04:23:51,787 INFO L290 TraceCheckUtils]: 85: Hoare triple {142400#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {142400#false} is VALID [2022-02-21 04:23:51,787 INFO L290 TraceCheckUtils]: 86: Hoare triple {142400#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {142400#false} is VALID [2022-02-21 04:23:51,787 INFO L290 TraceCheckUtils]: 87: Hoare triple {142400#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {142400#false} is VALID [2022-02-21 04:23:51,787 INFO L290 TraceCheckUtils]: 88: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___5~0#1); {142400#false} is VALID [2022-02-21 04:23:51,787 INFO L290 TraceCheckUtils]: 89: Hoare triple {142400#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {142400#false} is VALID [2022-02-21 04:23:51,787 INFO L290 TraceCheckUtils]: 90: Hoare triple {142400#false} assume !(1 == ~t7_pc~0); {142400#false} is VALID [2022-02-21 04:23:51,787 INFO L290 TraceCheckUtils]: 91: Hoare triple {142400#false} is_transmit7_triggered_~__retres1~7#1 := 0; {142400#false} is VALID [2022-02-21 04:23:51,787 INFO L290 TraceCheckUtils]: 92: Hoare triple {142400#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 93: Hoare triple {142400#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 94: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___6~0#1); {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 95: Hoare triple {142400#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 96: Hoare triple {142400#false} assume 1 == ~t8_pc~0; {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 97: Hoare triple {142400#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 98: Hoare triple {142400#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 99: Hoare triple {142400#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 100: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___7~0#1); {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 101: Hoare triple {142400#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 102: Hoare triple {142400#false} assume 1 == ~t9_pc~0; {142400#false} is VALID [2022-02-21 04:23:51,788 INFO L290 TraceCheckUtils]: 103: Hoare triple {142400#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {142400#false} is VALID [2022-02-21 04:23:51,789 INFO L290 TraceCheckUtils]: 104: Hoare triple {142400#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {142400#false} is VALID [2022-02-21 04:23:51,789 INFO L290 TraceCheckUtils]: 105: Hoare triple {142400#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {142400#false} is VALID [2022-02-21 04:23:51,789 INFO L290 TraceCheckUtils]: 106: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___8~0#1); {142400#false} is VALID [2022-02-21 04:23:51,789 INFO L290 TraceCheckUtils]: 107: Hoare triple {142400#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {142400#false} is VALID [2022-02-21 04:23:51,789 INFO L290 TraceCheckUtils]: 108: Hoare triple {142400#false} assume !(1 == ~t10_pc~0); {142400#false} is VALID [2022-02-21 04:23:51,789 INFO L290 TraceCheckUtils]: 109: Hoare triple {142400#false} is_transmit10_triggered_~__retres1~10#1 := 0; {142400#false} is VALID [2022-02-21 04:23:51,789 INFO L290 TraceCheckUtils]: 110: Hoare triple {142400#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {142400#false} is VALID [2022-02-21 04:23:51,789 INFO L290 TraceCheckUtils]: 111: Hoare triple {142400#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {142400#false} is VALID [2022-02-21 04:23:51,789 INFO L290 TraceCheckUtils]: 112: Hoare triple {142400#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {142400#false} is VALID [2022-02-21 04:23:51,789 INFO L290 TraceCheckUtils]: 113: Hoare triple {142400#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 114: Hoare triple {142400#false} assume 1 == ~t11_pc~0; {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 115: Hoare triple {142400#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 116: Hoare triple {142400#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 117: Hoare triple {142400#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 118: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___10~0#1); {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 119: Hoare triple {142400#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 120: Hoare triple {142400#false} assume !(1 == ~t12_pc~0); {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 121: Hoare triple {142400#false} is_transmit12_triggered_~__retres1~12#1 := 0; {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 122: Hoare triple {142400#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 123: Hoare triple {142400#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {142400#false} is VALID [2022-02-21 04:23:51,790 INFO L290 TraceCheckUtils]: 124: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___11~0#1); {142400#false} is VALID [2022-02-21 04:23:51,791 INFO L290 TraceCheckUtils]: 125: Hoare triple {142400#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {142400#false} is VALID [2022-02-21 04:23:51,791 INFO L290 TraceCheckUtils]: 126: Hoare triple {142400#false} assume 1 == ~t13_pc~0; {142400#false} is VALID [2022-02-21 04:23:51,791 INFO L290 TraceCheckUtils]: 127: Hoare triple {142400#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {142400#false} is VALID [2022-02-21 04:23:51,791 INFO L290 TraceCheckUtils]: 128: Hoare triple {142400#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {142400#false} is VALID [2022-02-21 04:23:51,791 INFO L290 TraceCheckUtils]: 129: Hoare triple {142400#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {142400#false} is VALID [2022-02-21 04:23:51,791 INFO L290 TraceCheckUtils]: 130: Hoare triple {142400#false} assume !(0 != activate_threads_~tmp___12~0#1); {142400#false} is VALID [2022-02-21 04:23:51,791 INFO L290 TraceCheckUtils]: 131: Hoare triple {142400#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {142400#false} is VALID [2022-02-21 04:23:51,791 INFO L290 TraceCheckUtils]: 132: Hoare triple {142400#false} assume !(1 == ~M_E~0); {142400#false} is VALID [2022-02-21 04:23:51,791 INFO L290 TraceCheckUtils]: 133: Hoare triple {142400#false} assume !(1 == ~T1_E~0); {142400#false} is VALID [2022-02-21 04:23:51,791 INFO L290 TraceCheckUtils]: 134: Hoare triple {142400#false} assume !(1 == ~T2_E~0); {142400#false} is VALID [2022-02-21 04:23:51,792 INFO L290 TraceCheckUtils]: 135: Hoare triple {142400#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {142400#false} is VALID [2022-02-21 04:23:51,792 INFO L290 TraceCheckUtils]: 136: Hoare triple {142400#false} assume !(1 == ~T4_E~0); {142400#false} is VALID [2022-02-21 04:23:51,792 INFO L290 TraceCheckUtils]: 137: Hoare triple {142400#false} assume !(1 == ~T5_E~0); {142400#false} is VALID [2022-02-21 04:23:51,792 INFO L290 TraceCheckUtils]: 138: Hoare triple {142400#false} assume !(1 == ~T6_E~0); {142400#false} is VALID [2022-02-21 04:23:51,792 INFO L290 TraceCheckUtils]: 139: Hoare triple {142400#false} assume !(1 == ~T7_E~0); {142400#false} is VALID [2022-02-21 04:23:51,792 INFO L290 TraceCheckUtils]: 140: Hoare triple {142400#false} assume !(1 == ~T8_E~0); {142400#false} is VALID [2022-02-21 04:23:51,792 INFO L290 TraceCheckUtils]: 141: Hoare triple {142400#false} assume !(1 == ~T9_E~0); {142400#false} is VALID [2022-02-21 04:23:51,792 INFO L290 TraceCheckUtils]: 142: Hoare triple {142400#false} assume !(1 == ~T10_E~0); {142400#false} is VALID [2022-02-21 04:23:51,792 INFO L290 TraceCheckUtils]: 143: Hoare triple {142400#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {142400#false} is VALID [2022-02-21 04:23:51,792 INFO L290 TraceCheckUtils]: 144: Hoare triple {142400#false} assume !(1 == ~T12_E~0); {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 145: Hoare triple {142400#false} assume !(1 == ~T13_E~0); {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 146: Hoare triple {142400#false} assume !(1 == ~E_M~0); {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 147: Hoare triple {142400#false} assume !(1 == ~E_1~0); {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 148: Hoare triple {142400#false} assume !(1 == ~E_2~0); {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 149: Hoare triple {142400#false} assume !(1 == ~E_3~0); {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 150: Hoare triple {142400#false} assume !(1 == ~E_4~0); {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 151: Hoare triple {142400#false} assume 1 == ~E_5~0;~E_5~0 := 2; {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 152: Hoare triple {142400#false} assume !(1 == ~E_6~0); {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 153: Hoare triple {142400#false} assume !(1 == ~E_7~0); {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 154: Hoare triple {142400#false} assume !(1 == ~E_8~0); {142400#false} is VALID [2022-02-21 04:23:51,793 INFO L290 TraceCheckUtils]: 155: Hoare triple {142400#false} assume !(1 == ~E_9~0); {142400#false} is VALID [2022-02-21 04:23:51,794 INFO L290 TraceCheckUtils]: 156: Hoare triple {142400#false} assume !(1 == ~E_10~0); {142400#false} is VALID [2022-02-21 04:23:51,794 INFO L290 TraceCheckUtils]: 157: Hoare triple {142400#false} assume !(1 == ~E_11~0); {142400#false} is VALID [2022-02-21 04:23:51,794 INFO L290 TraceCheckUtils]: 158: Hoare triple {142400#false} assume !(1 == ~E_12~0); {142400#false} is VALID [2022-02-21 04:23:51,794 INFO L290 TraceCheckUtils]: 159: Hoare triple {142400#false} assume 1 == ~E_13~0;~E_13~0 := 2; {142400#false} is VALID [2022-02-21 04:23:51,794 INFO L290 TraceCheckUtils]: 160: Hoare triple {142400#false} assume { :end_inline_reset_delta_events } true; {142400#false} is VALID [2022-02-21 04:23:51,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:51,794 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:51,795 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549790184] [2022-02-21 04:23:51,795 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549790184] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:51,795 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:51,795 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:51,795 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243780437] [2022-02-21 04:23:51,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:51,795 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:51,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:51,796 INFO L85 PathProgramCache]: Analyzing trace with hash 1676058667, now seen corresponding path program 1 times [2022-02-21 04:23:51,796 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:51,796 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [283783696] [2022-02-21 04:23:51,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:51,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:51,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:51,824 INFO L290 TraceCheckUtils]: 0: Hoare triple {142402#true} assume !false; {142402#true} is VALID [2022-02-21 04:23:51,825 INFO L290 TraceCheckUtils]: 1: Hoare triple {142402#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {142402#true} is VALID [2022-02-21 04:23:51,825 INFO L290 TraceCheckUtils]: 2: Hoare triple {142402#true} assume !false; {142402#true} is VALID [2022-02-21 04:23:51,825 INFO L290 TraceCheckUtils]: 3: Hoare triple {142402#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {142402#true} is VALID [2022-02-21 04:23:51,825 INFO L290 TraceCheckUtils]: 4: Hoare triple {142402#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {142402#true} is VALID [2022-02-21 04:23:51,825 INFO L290 TraceCheckUtils]: 5: Hoare triple {142402#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {142402#true} is VALID [2022-02-21 04:23:51,825 INFO L290 TraceCheckUtils]: 6: Hoare triple {142402#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {142402#true} is VALID [2022-02-21 04:23:51,825 INFO L290 TraceCheckUtils]: 7: Hoare triple {142402#true} assume !(0 != eval_~tmp~0#1); {142402#true} is VALID [2022-02-21 04:23:51,825 INFO L290 TraceCheckUtils]: 8: Hoare triple {142402#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {142402#true} is VALID [2022-02-21 04:23:51,825 INFO L290 TraceCheckUtils]: 9: Hoare triple {142402#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 10: Hoare triple {142402#true} assume !(0 == ~M_E~0); {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 11: Hoare triple {142402#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 12: Hoare triple {142402#true} assume !(0 == ~T2_E~0); {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 13: Hoare triple {142402#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 14: Hoare triple {142402#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 15: Hoare triple {142402#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 16: Hoare triple {142402#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 17: Hoare triple {142402#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 18: Hoare triple {142402#true} assume !(0 == ~T8_E~0); {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 19: Hoare triple {142402#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,826 INFO L290 TraceCheckUtils]: 20: Hoare triple {142402#true} assume !(0 == ~T10_E~0); {142402#true} is VALID [2022-02-21 04:23:51,827 INFO L290 TraceCheckUtils]: 21: Hoare triple {142402#true} assume 0 == ~T11_E~0;~T11_E~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,827 INFO L290 TraceCheckUtils]: 22: Hoare triple {142402#true} assume 0 == ~T12_E~0;~T12_E~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,827 INFO L290 TraceCheckUtils]: 23: Hoare triple {142402#true} assume 0 == ~T13_E~0;~T13_E~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,827 INFO L290 TraceCheckUtils]: 24: Hoare triple {142402#true} assume 0 == ~E_M~0;~E_M~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,827 INFO L290 TraceCheckUtils]: 25: Hoare triple {142402#true} assume 0 == ~E_1~0;~E_1~0 := 1; {142402#true} is VALID [2022-02-21 04:23:51,827 INFO L290 TraceCheckUtils]: 26: Hoare triple {142402#true} assume 0 == ~E_2~0;~E_2~0 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,828 INFO L290 TraceCheckUtils]: 27: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,828 INFO L290 TraceCheckUtils]: 28: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,828 INFO L290 TraceCheckUtils]: 29: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,828 INFO L290 TraceCheckUtils]: 30: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,829 INFO L290 TraceCheckUtils]: 31: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,829 INFO L290 TraceCheckUtils]: 32: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,829 INFO L290 TraceCheckUtils]: 33: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,829 INFO L290 TraceCheckUtils]: 34: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,830 INFO L290 TraceCheckUtils]: 35: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,830 INFO L290 TraceCheckUtils]: 36: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_12~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,830 INFO L290 TraceCheckUtils]: 37: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,830 INFO L290 TraceCheckUtils]: 38: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,831 INFO L290 TraceCheckUtils]: 39: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~m_pc~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,831 INFO L290 TraceCheckUtils]: 40: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,831 INFO L290 TraceCheckUtils]: 41: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,831 INFO L290 TraceCheckUtils]: 42: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,832 INFO L290 TraceCheckUtils]: 43: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,832 INFO L290 TraceCheckUtils]: 44: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,832 INFO L290 TraceCheckUtils]: 45: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t1_pc~0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,832 INFO L290 TraceCheckUtils]: 46: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,833 INFO L290 TraceCheckUtils]: 47: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,833 INFO L290 TraceCheckUtils]: 48: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,833 INFO L290 TraceCheckUtils]: 49: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,833 INFO L290 TraceCheckUtils]: 50: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,834 INFO L290 TraceCheckUtils]: 51: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t2_pc~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,834 INFO L290 TraceCheckUtils]: 52: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,834 INFO L290 TraceCheckUtils]: 53: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,834 INFO L290 TraceCheckUtils]: 54: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,835 INFO L290 TraceCheckUtils]: 55: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,835 INFO L290 TraceCheckUtils]: 56: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,835 INFO L290 TraceCheckUtils]: 57: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t3_pc~0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,836 INFO L290 TraceCheckUtils]: 58: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,836 INFO L290 TraceCheckUtils]: 59: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,836 INFO L290 TraceCheckUtils]: 60: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,836 INFO L290 TraceCheckUtils]: 61: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,837 INFO L290 TraceCheckUtils]: 62: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,837 INFO L290 TraceCheckUtils]: 63: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,837 INFO L290 TraceCheckUtils]: 64: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,837 INFO L290 TraceCheckUtils]: 65: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,838 INFO L290 TraceCheckUtils]: 66: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,838 INFO L290 TraceCheckUtils]: 67: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,838 INFO L290 TraceCheckUtils]: 68: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,838 INFO L290 TraceCheckUtils]: 69: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t5_pc~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,839 INFO L290 TraceCheckUtils]: 70: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,839 INFO L290 TraceCheckUtils]: 71: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,839 INFO L290 TraceCheckUtils]: 72: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,840 INFO L290 TraceCheckUtils]: 73: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,840 INFO L290 TraceCheckUtils]: 74: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,840 INFO L290 TraceCheckUtils]: 75: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t6_pc~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,841 INFO L290 TraceCheckUtils]: 76: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,841 INFO L290 TraceCheckUtils]: 77: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,841 INFO L290 TraceCheckUtils]: 78: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,841 INFO L290 TraceCheckUtils]: 79: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,842 INFO L290 TraceCheckUtils]: 80: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,842 INFO L290 TraceCheckUtils]: 81: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t7_pc~0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,842 INFO L290 TraceCheckUtils]: 82: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,842 INFO L290 TraceCheckUtils]: 83: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,843 INFO L290 TraceCheckUtils]: 84: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,843 INFO L290 TraceCheckUtils]: 85: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,843 INFO L290 TraceCheckUtils]: 86: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,844 INFO L290 TraceCheckUtils]: 87: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t8_pc~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,844 INFO L290 TraceCheckUtils]: 88: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,844 INFO L290 TraceCheckUtils]: 89: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,844 INFO L290 TraceCheckUtils]: 90: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,845 INFO L290 TraceCheckUtils]: 91: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,845 INFO L290 TraceCheckUtils]: 92: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,845 INFO L290 TraceCheckUtils]: 93: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t9_pc~0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,845 INFO L290 TraceCheckUtils]: 94: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,846 INFO L290 TraceCheckUtils]: 95: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,846 INFO L290 TraceCheckUtils]: 96: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,846 INFO L290 TraceCheckUtils]: 97: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,846 INFO L290 TraceCheckUtils]: 98: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,847 INFO L290 TraceCheckUtils]: 99: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t10_pc~0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,847 INFO L290 TraceCheckUtils]: 100: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,847 INFO L290 TraceCheckUtils]: 101: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,847 INFO L290 TraceCheckUtils]: 102: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,848 INFO L290 TraceCheckUtils]: 103: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,848 INFO L290 TraceCheckUtils]: 104: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,848 INFO L290 TraceCheckUtils]: 105: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t11_pc~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,848 INFO L290 TraceCheckUtils]: 106: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,849 INFO L290 TraceCheckUtils]: 107: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,849 INFO L290 TraceCheckUtils]: 108: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,849 INFO L290 TraceCheckUtils]: 109: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,849 INFO L290 TraceCheckUtils]: 110: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,850 INFO L290 TraceCheckUtils]: 111: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t12_pc~0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,850 INFO L290 TraceCheckUtils]: 112: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,850 INFO L290 TraceCheckUtils]: 113: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,850 INFO L290 TraceCheckUtils]: 114: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,851 INFO L290 TraceCheckUtils]: 115: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,851 INFO L290 TraceCheckUtils]: 116: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,851 INFO L290 TraceCheckUtils]: 117: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t13_pc~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,852 INFO L290 TraceCheckUtils]: 118: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,852 INFO L290 TraceCheckUtils]: 119: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,852 INFO L290 TraceCheckUtils]: 120: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,852 INFO L290 TraceCheckUtils]: 121: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,853 INFO L290 TraceCheckUtils]: 122: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,853 INFO L290 TraceCheckUtils]: 123: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~M_E~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,853 INFO L290 TraceCheckUtils]: 124: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,853 INFO L290 TraceCheckUtils]: 125: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,854 INFO L290 TraceCheckUtils]: 126: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,854 INFO L290 TraceCheckUtils]: 127: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,854 INFO L290 TraceCheckUtils]: 128: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,854 INFO L290 TraceCheckUtils]: 129: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,855 INFO L290 TraceCheckUtils]: 130: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,855 INFO L290 TraceCheckUtils]: 131: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T8_E~0); {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,855 INFO L290 TraceCheckUtils]: 132: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,855 INFO L290 TraceCheckUtils]: 133: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T10_E~0;~T10_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,856 INFO L290 TraceCheckUtils]: 134: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T11_E~0;~T11_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,856 INFO L290 TraceCheckUtils]: 135: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T12_E~0;~T12_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,856 INFO L290 TraceCheckUtils]: 136: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T13_E~0;~T13_E~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,856 INFO L290 TraceCheckUtils]: 137: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,857 INFO L290 TraceCheckUtils]: 138: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {142404#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:23:51,857 INFO L290 TraceCheckUtils]: 139: Hoare triple {142404#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {142403#false} is VALID [2022-02-21 04:23:51,857 INFO L290 TraceCheckUtils]: 140: Hoare triple {142403#false} assume 1 == ~E_3~0;~E_3~0 := 2; {142403#false} is VALID [2022-02-21 04:23:51,857 INFO L290 TraceCheckUtils]: 141: Hoare triple {142403#false} assume 1 == ~E_4~0;~E_4~0 := 2; {142403#false} is VALID [2022-02-21 04:23:51,857 INFO L290 TraceCheckUtils]: 142: Hoare triple {142403#false} assume 1 == ~E_5~0;~E_5~0 := 2; {142403#false} is VALID [2022-02-21 04:23:51,857 INFO L290 TraceCheckUtils]: 143: Hoare triple {142403#false} assume 1 == ~E_6~0;~E_6~0 := 2; {142403#false} is VALID [2022-02-21 04:23:51,858 INFO L290 TraceCheckUtils]: 144: Hoare triple {142403#false} assume 1 == ~E_7~0;~E_7~0 := 2; {142403#false} is VALID [2022-02-21 04:23:51,858 INFO L290 TraceCheckUtils]: 145: Hoare triple {142403#false} assume 1 == ~E_8~0;~E_8~0 := 2; {142403#false} is VALID [2022-02-21 04:23:51,858 INFO L290 TraceCheckUtils]: 146: Hoare triple {142403#false} assume 1 == ~E_9~0;~E_9~0 := 2; {142403#false} is VALID [2022-02-21 04:23:51,858 INFO L290 TraceCheckUtils]: 147: Hoare triple {142403#false} assume !(1 == ~E_10~0); {142403#false} is VALID [2022-02-21 04:23:51,858 INFO L290 TraceCheckUtils]: 148: Hoare triple {142403#false} assume 1 == ~E_11~0;~E_11~0 := 2; {142403#false} is VALID [2022-02-21 04:23:51,858 INFO L290 TraceCheckUtils]: 149: Hoare triple {142403#false} assume 1 == ~E_12~0;~E_12~0 := 2; {142403#false} is VALID [2022-02-21 04:23:51,858 INFO L290 TraceCheckUtils]: 150: Hoare triple {142403#false} assume 1 == ~E_13~0;~E_13~0 := 2; {142403#false} is VALID [2022-02-21 04:23:51,858 INFO L290 TraceCheckUtils]: 151: Hoare triple {142403#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {142403#false} is VALID [2022-02-21 04:23:51,858 INFO L290 TraceCheckUtils]: 152: Hoare triple {142403#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {142403#false} is VALID [2022-02-21 04:23:51,858 INFO L290 TraceCheckUtils]: 153: Hoare triple {142403#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {142403#false} is VALID [2022-02-21 04:23:51,859 INFO L290 TraceCheckUtils]: 154: Hoare triple {142403#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {142403#false} is VALID [2022-02-21 04:23:51,859 INFO L290 TraceCheckUtils]: 155: Hoare triple {142403#false} assume !(0 == start_simulation_~tmp~3#1); {142403#false} is VALID [2022-02-21 04:23:51,859 INFO L290 TraceCheckUtils]: 156: Hoare triple {142403#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {142403#false} is VALID [2022-02-21 04:23:51,859 INFO L290 TraceCheckUtils]: 157: Hoare triple {142403#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {142403#false} is VALID [2022-02-21 04:23:51,859 INFO L290 TraceCheckUtils]: 158: Hoare triple {142403#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {142403#false} is VALID [2022-02-21 04:23:51,859 INFO L290 TraceCheckUtils]: 159: Hoare triple {142403#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {142403#false} is VALID [2022-02-21 04:23:51,859 INFO L290 TraceCheckUtils]: 160: Hoare triple {142403#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {142403#false} is VALID [2022-02-21 04:23:51,859 INFO L290 TraceCheckUtils]: 161: Hoare triple {142403#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {142403#false} is VALID [2022-02-21 04:23:51,859 INFO L290 TraceCheckUtils]: 162: Hoare triple {142403#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {142403#false} is VALID [2022-02-21 04:23:51,859 INFO L290 TraceCheckUtils]: 163: Hoare triple {142403#false} assume !(0 != start_simulation_~tmp___0~1#1); {142403#false} is VALID [2022-02-21 04:23:51,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:51,860 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:51,860 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [283783696] [2022-02-21 04:23:51,861 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [283783696] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:51,861 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:51,861 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:51,861 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890112804] [2022-02-21 04:23:51,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:51,861 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:51,862 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:51,862 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:51,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:51,863 INFO L87 Difference]: Start difference. First operand 3761 states and 5525 transitions. cyclomatic complexity: 1765 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:53,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:53,531 INFO L93 Difference]: Finished difference Result 3761 states and 5487 transitions. [2022-02-21 04:23:53,531 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:53,531 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:53,619 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:53,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3761 states and 5487 transitions. [2022-02-21 04:23:54,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-02-21 04:23:54,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3761 states to 3761 states and 5487 transitions. [2022-02-21 04:23:54,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3761 [2022-02-21 04:23:54,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3761 [2022-02-21 04:23:54,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3761 states and 5487 transitions. [2022-02-21 04:23:54,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:54,491 INFO L681 BuchiCegarLoop]: Abstraction has 3761 states and 5487 transitions. [2022-02-21 04:23:54,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3761 states and 5487 transitions. [2022-02-21 04:23:54,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3761 to 3761. [2022-02-21 04:23:54,519 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:54,522 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3761 states and 5487 transitions. Second operand has 3761 states, 3761 states have (on average 1.4589204998670566) internal successors, (5487), 3760 states have internal predecessors, (5487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,524 INFO L74 IsIncluded]: Start isIncluded. First operand 3761 states and 5487 transitions. Second operand has 3761 states, 3761 states have (on average 1.4589204998670566) internal successors, (5487), 3760 states have internal predecessors, (5487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,525 INFO L87 Difference]: Start difference. First operand 3761 states and 5487 transitions. Second operand has 3761 states, 3761 states have (on average 1.4589204998670566) internal successors, (5487), 3760 states have internal predecessors, (5487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:54,836 INFO L93 Difference]: Finished difference Result 3761 states and 5487 transitions. [2022-02-21 04:23:54,836 INFO L276 IsEmpty]: Start isEmpty. Operand 3761 states and 5487 transitions. [2022-02-21 04:23:54,839 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:54,839 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:54,843 INFO L74 IsIncluded]: Start isIncluded. First operand has 3761 states, 3761 states have (on average 1.4589204998670566) internal successors, (5487), 3760 states have internal predecessors, (5487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3761 states and 5487 transitions. [2022-02-21 04:23:54,845 INFO L87 Difference]: Start difference. First operand has 3761 states, 3761 states have (on average 1.4589204998670566) internal successors, (5487), 3760 states have internal predecessors, (5487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3761 states and 5487 transitions. [2022-02-21 04:23:55,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:55,186 INFO L93 Difference]: Finished difference Result 3761 states and 5487 transitions. [2022-02-21 04:23:55,186 INFO L276 IsEmpty]: Start isEmpty. Operand 3761 states and 5487 transitions. [2022-02-21 04:23:55,189 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:55,189 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:55,189 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:55,189 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:55,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4589204998670566) internal successors, (5487), 3760 states have internal predecessors, (5487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:55,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5487 transitions. [2022-02-21 04:23:55,560 INFO L704 BuchiCegarLoop]: Abstraction has 3761 states and 5487 transitions. [2022-02-21 04:23:55,560 INFO L587 BuchiCegarLoop]: Abstraction has 3761 states and 5487 transitions. [2022-02-21 04:23:55,560 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2022-02-21 04:23:55,560 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5487 transitions. [2022-02-21 04:23:55,566 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-02-21 04:23:55,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:55,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:55,567 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:55,568 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:55,568 INFO L791 eck$LassoCheckResult]: Stem: 147077#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 147078#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 148160#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 147574#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 147575#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 147059#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 147060#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 147126#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 147127#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 147570#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 147571#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 147092#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 146911#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 146912#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 147357#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 147358#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 147232#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 147233#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 146883#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 146884#L1279 assume !(0 == ~M_E~0); 148150#L1279-2 assume !(0 == ~T1_E~0); 146508#L1284-1 assume !(0 == ~T2_E~0); 146509#L1289-1 assume !(0 == ~T3_E~0); 147229#L1294-1 assume !(0 == ~T4_E~0); 147230#L1299-1 assume !(0 == ~T5_E~0); 147241#L1304-1 assume !(0 == ~T6_E~0); 148249#L1309-1 assume !(0 == ~T7_E~0); 148250#L1314-1 assume !(0 == ~T8_E~0); 146438#L1319-1 assume !(0 == ~T9_E~0); 146439#L1324-1 assume !(0 == ~T10_E~0); 146611#L1329-1 assume !(0 == ~T11_E~0); 146612#L1334-1 assume !(0 == ~T12_E~0); 148039#L1339-1 assume !(0 == ~T13_E~0); 148133#L1344-1 assume !(0 == ~E_M~0); 148134#L1349-1 assume !(0 == ~E_1~0); 147418#L1354-1 assume !(0 == ~E_2~0); 147419#L1359-1 assume !(0 == ~E_3~0); 147856#L1364-1 assume !(0 == ~E_4~0); 146739#L1369-1 assume !(0 == ~E_5~0); 146740#L1374-1 assume !(0 == ~E_6~0); 147423#L1379-1 assume !(0 == ~E_7~0); 147424#L1384-1 assume !(0 == ~E_8~0); 147502#L1389-1 assume !(0 == ~E_9~0); 148061#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 148062#L1399-1 assume !(0 == ~E_11~0); 148189#L1404-1 assume !(0 == ~E_12~0); 146831#L1409-1 assume !(0 == ~E_13~0); 146832#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 148179#L628 assume !(1 == ~m_pc~0); 146736#L628-2 is_master_triggered_~__retres1~0#1 := 0; 146735#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 147500#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 147501#L1591 assume !(0 != activate_threads_~tmp~1#1); 148197#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 147286#L647 assume 1 == ~t1_pc~0; 146656#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 146657#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 146926#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 146927#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 148118#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 148119#L666 assume !(1 == ~t2_pc~0); 146507#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 146671#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 146672#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 148139#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 147623#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 147624#L685 assume !(1 == ~t3_pc~0); 147729#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 147728#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 147346#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 147347#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 147470#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 146953#L704 assume 1 == ~t4_pc~0; 146954#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 147481#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 147482#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 148165#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 147339#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 147340#L723 assume !(1 == ~t5_pc~0); 147464#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 147703#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 147851#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 147601#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 147602#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 146721#L742 assume 1 == ~t6_pc~0; 146722#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 146869#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 146870#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 146407#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 146408#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 146798#L761 assume !(1 == ~t7_pc~0); 146799#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 146667#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 146668#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 147471#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 147472#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 146432#L780 assume 1 == ~t8_pc~0; 146433#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 146708#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 146709#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 147431#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 147432#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 147554#L799 assume 1 == ~t9_pc~0; 147667#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 146435#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 146436#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 147566#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 147776#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 147584#L818 assume !(1 == ~t10_pc~0); 146217#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 146218#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 147660#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 147588#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 147589#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 147630#L837 assume 1 == ~t11_pc~0; 147631#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 147461#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 147872#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 147547#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 147548#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 147295#L856 assume !(1 == ~t12_pc~0); 147296#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 147963#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 147964#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 147943#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 147944#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 148154#L875 assume 1 == ~t13_pc~0; 147239#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 146872#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 146873#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 146813#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 146814#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 147657#L1427 assume !(1 == ~M_E~0); 147641#L1427-2 assume !(1 == ~T1_E~0); 146785#L1432-1 assume !(1 == ~T2_E~0); 146786#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 147862#L1442-1 assume !(1 == ~T4_E~0); 147863#L1447-1 assume !(1 == ~T5_E~0); 147714#L1452-1 assume !(1 == ~T6_E~0); 146351#L1457-1 assume !(1 == ~T7_E~0); 146352#L1462-1 assume !(1 == ~T8_E~0); 147892#L1467-1 assume !(1 == ~T9_E~0); 147911#L1472-1 assume !(1 == ~T10_E~0); 147912#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 147655#L1482-1 assume !(1 == ~T12_E~0); 147656#L1487-1 assume !(1 == ~T13_E~0); 146682#L1492-1 assume !(1 == ~E_M~0); 146683#L1497-1 assume !(1 == ~E_1~0); 147041#L1502-1 assume !(1 == ~E_2~0); 147042#L1507-1 assume !(1 == ~E_3~0); 146560#L1512-1 assume !(1 == ~E_4~0); 146561#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 147987#L1522-1 assume !(1 == ~E_6~0); 147283#L1527-1 assume !(1 == ~E_7~0); 147284#L1532-1 assume !(1 == ~E_8~0); 148228#L1537-1 assume !(1 == ~E_9~0); 147488#L1542-1 assume !(1 == ~E_10~0); 147317#L1547-1 assume !(1 == ~E_11~0); 147318#L1552-1 assume !(1 == ~E_12~0); 146256#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 146257#L1562-1 assume { :end_inline_reset_delta_events } true; 146860#L1928-2 [2022-02-21 04:23:55,568 INFO L793 eck$LassoCheckResult]: Loop: 146860#L1928-2 assume !false; 148383#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 148379#L1254 assume !false; 148378#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 148371#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 148363#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 148167#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 148168#L1067 assume !(0 != eval_~tmp~0#1); 148362#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 148361#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 148177#L1279-3 assume !(0 == ~M_E~0); 147063#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 147045#L1284-3 assume !(0 == ~T2_E~0); 147046#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 148358#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 148357#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 148356#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 147880#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 147881#L1314-3 assume !(0 == ~T8_E~0); 148355#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 147933#L1324-3 assume !(0 == ~T10_E~0); 146557#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 146558#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 147323#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 147324#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 147627#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 146904#L1354-3 assume !(0 == ~E_2~0); 146905#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 147638#L1364-3 assume !(0 == ~E_4~0); 148248#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 148081#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 146686#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 146687#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 148345#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 148344#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 148343#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 148092#L1404-3 assume !(0 == ~E_12~0); 148093#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 148149#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 147514#L628-45 assume !(1 == ~m_pc~0); 147515#L628-47 is_master_triggered_~__retres1~0#1 := 0; 148224#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 146551#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 146552#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 146937#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148339#L647-45 assume !(1 == ~t1_pc~0); 148338#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 148336#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148335#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 148334#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 148147#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 148148#L666-45 assume !(1 == ~t2_pc~0); 148332#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 148209#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 148210#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 148331#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 148330#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148329#L685-45 assume 1 == ~t3_pc~0; 148327#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 148137#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148138#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 147984#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 147985#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 148188#L704-45 assume 1 == ~t4_pc~0; 148009#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 146234#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 147089#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 147434#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148265#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 147549#L723-45 assume !(1 == ~t5_pc~0); 147550#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 148063#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 148317#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 148316#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 148315#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 147952#L742-45 assume 1 == ~t6_pc~0; 147953#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 147161#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 147636#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 147672#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 147673#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 148309#L761-45 assume 1 == ~t7_pc~0; 148307#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 148306#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 148305#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 148304#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 148303#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 148055#L780-45 assume 1 == ~t8_pc~0; 148056#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 148302#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 148301#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 148300#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 148299#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 148298#L799-45 assume !(1 == ~t9_pc~0); 148296#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 148295#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 148117#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 147715#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 147716#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 146485#L818-45 assume 1 == ~t10_pc~0; 146486#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 146603#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 147689#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 147087#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 147088#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 147811#L837-45 assume !(1 == ~t11_pc~0); 148284#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 148283#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 148282#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 148281#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 148280#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 148279#L856-45 assume 1 == ~t12_pc~0; 148146#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 146624#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 148278#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 148277#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 148276#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 147988#L875-45 assume 1 == ~t13_pc~0; 147399#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 147400#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 147462#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 148247#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 148271#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148038#L1427-3 assume !(1 == ~M_E~0); 147223#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 147224#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 147770#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 147416#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 147417#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 146275#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 146276#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 147969#L1462-3 assume !(1 == ~T8_E~0); 147970#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 147827#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 147828#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 146525#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 146526#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 146666#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 146838#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 146839#L1502-3 assume !(1 == ~E_2~0); 147794#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 147931#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 146876#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 146570#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 146571#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 146535#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 146536#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 147639#L1542-3 assume !(1 == ~E_10~0); 147779#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 147402#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 147403#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 146745#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 146746#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 146167#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 146928#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 146929#L1947 assume !(0 == start_simulation_~tmp~3#1); 147539#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 147746#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 146802#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 148184#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 148416#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 147899#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 147651#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 147652#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 146860#L1928-2 [2022-02-21 04:23:55,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:55,569 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2022-02-21 04:23:55,569 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:55,569 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44100561] [2022-02-21 04:23:55,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:55,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:55,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:55,594 INFO L290 TraceCheckUtils]: 0: Hoare triple {157452#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,594 INFO L290 TraceCheckUtils]: 1: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,594 INFO L290 TraceCheckUtils]: 2: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,595 INFO L290 TraceCheckUtils]: 3: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,595 INFO L290 TraceCheckUtils]: 4: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,595 INFO L290 TraceCheckUtils]: 5: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,595 INFO L290 TraceCheckUtils]: 6: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,596 INFO L290 TraceCheckUtils]: 7: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,596 INFO L290 TraceCheckUtils]: 8: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,596 INFO L290 TraceCheckUtils]: 9: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,596 INFO L290 TraceCheckUtils]: 10: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,597 INFO L290 TraceCheckUtils]: 11: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,597 INFO L290 TraceCheckUtils]: 12: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,597 INFO L290 TraceCheckUtils]: 13: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,597 INFO L290 TraceCheckUtils]: 14: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,598 INFO L290 TraceCheckUtils]: 15: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,598 INFO L290 TraceCheckUtils]: 16: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,598 INFO L290 TraceCheckUtils]: 17: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,598 INFO L290 TraceCheckUtils]: 18: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {157454#(= ~E_10~0 ~M_E~0)} is VALID [2022-02-21 04:23:55,599 INFO L290 TraceCheckUtils]: 19: Hoare triple {157454#(= ~E_10~0 ~M_E~0)} assume !(0 == ~M_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,599 INFO L290 TraceCheckUtils]: 20: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T1_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,599 INFO L290 TraceCheckUtils]: 21: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T2_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,599 INFO L290 TraceCheckUtils]: 22: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T3_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,600 INFO L290 TraceCheckUtils]: 23: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T4_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,600 INFO L290 TraceCheckUtils]: 24: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T5_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,600 INFO L290 TraceCheckUtils]: 25: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T6_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,600 INFO L290 TraceCheckUtils]: 26: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T7_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,601 INFO L290 TraceCheckUtils]: 27: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T8_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,601 INFO L290 TraceCheckUtils]: 28: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T9_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,601 INFO L290 TraceCheckUtils]: 29: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T10_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,601 INFO L290 TraceCheckUtils]: 30: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T11_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,602 INFO L290 TraceCheckUtils]: 31: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T12_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,602 INFO L290 TraceCheckUtils]: 32: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~T13_E~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,602 INFO L290 TraceCheckUtils]: 33: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~E_M~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,603 INFO L290 TraceCheckUtils]: 34: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~E_1~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,603 INFO L290 TraceCheckUtils]: 35: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~E_2~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,603 INFO L290 TraceCheckUtils]: 36: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~E_3~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,603 INFO L290 TraceCheckUtils]: 37: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~E_4~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,604 INFO L290 TraceCheckUtils]: 38: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~E_5~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,604 INFO L290 TraceCheckUtils]: 39: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~E_6~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,604 INFO L290 TraceCheckUtils]: 40: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~E_7~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,604 INFO L290 TraceCheckUtils]: 41: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~E_8~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,604 INFO L290 TraceCheckUtils]: 42: Hoare triple {157455#(not (= ~E_10~0 0))} assume !(0 == ~E_9~0); {157455#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:23:55,605 INFO L290 TraceCheckUtils]: 43: Hoare triple {157455#(not (= ~E_10~0 0))} assume 0 == ~E_10~0;~E_10~0 := 1; {157453#false} is VALID [2022-02-21 04:23:55,605 INFO L290 TraceCheckUtils]: 44: Hoare triple {157453#false} assume !(0 == ~E_11~0); {157453#false} is VALID [2022-02-21 04:23:55,605 INFO L290 TraceCheckUtils]: 45: Hoare triple {157453#false} assume !(0 == ~E_12~0); {157453#false} is VALID [2022-02-21 04:23:55,605 INFO L290 TraceCheckUtils]: 46: Hoare triple {157453#false} assume !(0 == ~E_13~0); {157453#false} is VALID [2022-02-21 04:23:55,605 INFO L290 TraceCheckUtils]: 47: Hoare triple {157453#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {157453#false} is VALID [2022-02-21 04:23:55,605 INFO L290 TraceCheckUtils]: 48: Hoare triple {157453#false} assume !(1 == ~m_pc~0); {157453#false} is VALID [2022-02-21 04:23:55,605 INFO L290 TraceCheckUtils]: 49: Hoare triple {157453#false} is_master_triggered_~__retres1~0#1 := 0; {157453#false} is VALID [2022-02-21 04:23:55,605 INFO L290 TraceCheckUtils]: 50: Hoare triple {157453#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {157453#false} is VALID [2022-02-21 04:23:55,606 INFO L290 TraceCheckUtils]: 51: Hoare triple {157453#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {157453#false} is VALID [2022-02-21 04:23:55,606 INFO L290 TraceCheckUtils]: 52: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp~1#1); {157453#false} is VALID [2022-02-21 04:23:55,606 INFO L290 TraceCheckUtils]: 53: Hoare triple {157453#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {157453#false} is VALID [2022-02-21 04:23:55,606 INFO L290 TraceCheckUtils]: 54: Hoare triple {157453#false} assume 1 == ~t1_pc~0; {157453#false} is VALID [2022-02-21 04:23:55,606 INFO L290 TraceCheckUtils]: 55: Hoare triple {157453#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {157453#false} is VALID [2022-02-21 04:23:55,606 INFO L290 TraceCheckUtils]: 56: Hoare triple {157453#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {157453#false} is VALID [2022-02-21 04:23:55,606 INFO L290 TraceCheckUtils]: 57: Hoare triple {157453#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {157453#false} is VALID [2022-02-21 04:23:55,606 INFO L290 TraceCheckUtils]: 58: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___0~0#1); {157453#false} is VALID [2022-02-21 04:23:55,606 INFO L290 TraceCheckUtils]: 59: Hoare triple {157453#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {157453#false} is VALID [2022-02-21 04:23:55,607 INFO L290 TraceCheckUtils]: 60: Hoare triple {157453#false} assume !(1 == ~t2_pc~0); {157453#false} is VALID [2022-02-21 04:23:55,607 INFO L290 TraceCheckUtils]: 61: Hoare triple {157453#false} is_transmit2_triggered_~__retres1~2#1 := 0; {157453#false} is VALID [2022-02-21 04:23:55,607 INFO L290 TraceCheckUtils]: 62: Hoare triple {157453#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {157453#false} is VALID [2022-02-21 04:23:55,607 INFO L290 TraceCheckUtils]: 63: Hoare triple {157453#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {157453#false} is VALID [2022-02-21 04:23:55,607 INFO L290 TraceCheckUtils]: 64: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___1~0#1); {157453#false} is VALID [2022-02-21 04:23:55,607 INFO L290 TraceCheckUtils]: 65: Hoare triple {157453#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {157453#false} is VALID [2022-02-21 04:23:55,607 INFO L290 TraceCheckUtils]: 66: Hoare triple {157453#false} assume !(1 == ~t3_pc~0); {157453#false} is VALID [2022-02-21 04:23:55,607 INFO L290 TraceCheckUtils]: 67: Hoare triple {157453#false} is_transmit3_triggered_~__retres1~3#1 := 0; {157453#false} is VALID [2022-02-21 04:23:55,607 INFO L290 TraceCheckUtils]: 68: Hoare triple {157453#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {157453#false} is VALID [2022-02-21 04:23:55,607 INFO L290 TraceCheckUtils]: 69: Hoare triple {157453#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {157453#false} is VALID [2022-02-21 04:23:55,608 INFO L290 TraceCheckUtils]: 70: Hoare triple {157453#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {157453#false} is VALID [2022-02-21 04:23:55,608 INFO L290 TraceCheckUtils]: 71: Hoare triple {157453#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {157453#false} is VALID [2022-02-21 04:23:55,608 INFO L290 TraceCheckUtils]: 72: Hoare triple {157453#false} assume 1 == ~t4_pc~0; {157453#false} is VALID [2022-02-21 04:23:55,608 INFO L290 TraceCheckUtils]: 73: Hoare triple {157453#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {157453#false} is VALID [2022-02-21 04:23:55,608 INFO L290 TraceCheckUtils]: 74: Hoare triple {157453#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {157453#false} is VALID [2022-02-21 04:23:55,608 INFO L290 TraceCheckUtils]: 75: Hoare triple {157453#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {157453#false} is VALID [2022-02-21 04:23:55,608 INFO L290 TraceCheckUtils]: 76: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___3~0#1); {157453#false} is VALID [2022-02-21 04:23:55,608 INFO L290 TraceCheckUtils]: 77: Hoare triple {157453#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {157453#false} is VALID [2022-02-21 04:23:55,608 INFO L290 TraceCheckUtils]: 78: Hoare triple {157453#false} assume !(1 == ~t5_pc~0); {157453#false} is VALID [2022-02-21 04:23:55,608 INFO L290 TraceCheckUtils]: 79: Hoare triple {157453#false} is_transmit5_triggered_~__retres1~5#1 := 0; {157453#false} is VALID [2022-02-21 04:23:55,609 INFO L290 TraceCheckUtils]: 80: Hoare triple {157453#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {157453#false} is VALID [2022-02-21 04:23:55,609 INFO L290 TraceCheckUtils]: 81: Hoare triple {157453#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {157453#false} is VALID [2022-02-21 04:23:55,609 INFO L290 TraceCheckUtils]: 82: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___4~0#1); {157453#false} is VALID [2022-02-21 04:23:55,609 INFO L290 TraceCheckUtils]: 83: Hoare triple {157453#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {157453#false} is VALID [2022-02-21 04:23:55,609 INFO L290 TraceCheckUtils]: 84: Hoare triple {157453#false} assume 1 == ~t6_pc~0; {157453#false} is VALID [2022-02-21 04:23:55,609 INFO L290 TraceCheckUtils]: 85: Hoare triple {157453#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {157453#false} is VALID [2022-02-21 04:23:55,609 INFO L290 TraceCheckUtils]: 86: Hoare triple {157453#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {157453#false} is VALID [2022-02-21 04:23:55,609 INFO L290 TraceCheckUtils]: 87: Hoare triple {157453#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {157453#false} is VALID [2022-02-21 04:23:55,609 INFO L290 TraceCheckUtils]: 88: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___5~0#1); {157453#false} is VALID [2022-02-21 04:23:55,610 INFO L290 TraceCheckUtils]: 89: Hoare triple {157453#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {157453#false} is VALID [2022-02-21 04:23:55,610 INFO L290 TraceCheckUtils]: 90: Hoare triple {157453#false} assume !(1 == ~t7_pc~0); {157453#false} is VALID [2022-02-21 04:23:55,610 INFO L290 TraceCheckUtils]: 91: Hoare triple {157453#false} is_transmit7_triggered_~__retres1~7#1 := 0; {157453#false} is VALID [2022-02-21 04:23:55,610 INFO L290 TraceCheckUtils]: 92: Hoare triple {157453#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {157453#false} is VALID [2022-02-21 04:23:55,610 INFO L290 TraceCheckUtils]: 93: Hoare triple {157453#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {157453#false} is VALID [2022-02-21 04:23:55,610 INFO L290 TraceCheckUtils]: 94: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___6~0#1); {157453#false} is VALID [2022-02-21 04:23:55,610 INFO L290 TraceCheckUtils]: 95: Hoare triple {157453#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {157453#false} is VALID [2022-02-21 04:23:55,610 INFO L290 TraceCheckUtils]: 96: Hoare triple {157453#false} assume 1 == ~t8_pc~0; {157453#false} is VALID [2022-02-21 04:23:55,610 INFO L290 TraceCheckUtils]: 97: Hoare triple {157453#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {157453#false} is VALID [2022-02-21 04:23:55,610 INFO L290 TraceCheckUtils]: 98: Hoare triple {157453#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {157453#false} is VALID [2022-02-21 04:23:55,611 INFO L290 TraceCheckUtils]: 99: Hoare triple {157453#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {157453#false} is VALID [2022-02-21 04:23:55,611 INFO L290 TraceCheckUtils]: 100: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___7~0#1); {157453#false} is VALID [2022-02-21 04:23:55,611 INFO L290 TraceCheckUtils]: 101: Hoare triple {157453#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {157453#false} is VALID [2022-02-21 04:23:55,611 INFO L290 TraceCheckUtils]: 102: Hoare triple {157453#false} assume 1 == ~t9_pc~0; {157453#false} is VALID [2022-02-21 04:23:55,611 INFO L290 TraceCheckUtils]: 103: Hoare triple {157453#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {157453#false} is VALID [2022-02-21 04:23:55,611 INFO L290 TraceCheckUtils]: 104: Hoare triple {157453#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {157453#false} is VALID [2022-02-21 04:23:55,611 INFO L290 TraceCheckUtils]: 105: Hoare triple {157453#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {157453#false} is VALID [2022-02-21 04:23:55,611 INFO L290 TraceCheckUtils]: 106: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___8~0#1); {157453#false} is VALID [2022-02-21 04:23:55,611 INFO L290 TraceCheckUtils]: 107: Hoare triple {157453#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {157453#false} is VALID [2022-02-21 04:23:55,611 INFO L290 TraceCheckUtils]: 108: Hoare triple {157453#false} assume !(1 == ~t10_pc~0); {157453#false} is VALID [2022-02-21 04:23:55,612 INFO L290 TraceCheckUtils]: 109: Hoare triple {157453#false} is_transmit10_triggered_~__retres1~10#1 := 0; {157453#false} is VALID [2022-02-21 04:23:55,612 INFO L290 TraceCheckUtils]: 110: Hoare triple {157453#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {157453#false} is VALID [2022-02-21 04:23:55,612 INFO L290 TraceCheckUtils]: 111: Hoare triple {157453#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {157453#false} is VALID [2022-02-21 04:23:55,612 INFO L290 TraceCheckUtils]: 112: Hoare triple {157453#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {157453#false} is VALID [2022-02-21 04:23:55,612 INFO L290 TraceCheckUtils]: 113: Hoare triple {157453#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {157453#false} is VALID [2022-02-21 04:23:55,612 INFO L290 TraceCheckUtils]: 114: Hoare triple {157453#false} assume 1 == ~t11_pc~0; {157453#false} is VALID [2022-02-21 04:23:55,612 INFO L290 TraceCheckUtils]: 115: Hoare triple {157453#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {157453#false} is VALID [2022-02-21 04:23:55,612 INFO L290 TraceCheckUtils]: 116: Hoare triple {157453#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {157453#false} is VALID [2022-02-21 04:23:55,612 INFO L290 TraceCheckUtils]: 117: Hoare triple {157453#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {157453#false} is VALID [2022-02-21 04:23:55,612 INFO L290 TraceCheckUtils]: 118: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___10~0#1); {157453#false} is VALID [2022-02-21 04:23:55,613 INFO L290 TraceCheckUtils]: 119: Hoare triple {157453#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {157453#false} is VALID [2022-02-21 04:23:55,613 INFO L290 TraceCheckUtils]: 120: Hoare triple {157453#false} assume !(1 == ~t12_pc~0); {157453#false} is VALID [2022-02-21 04:23:55,613 INFO L290 TraceCheckUtils]: 121: Hoare triple {157453#false} is_transmit12_triggered_~__retres1~12#1 := 0; {157453#false} is VALID [2022-02-21 04:23:55,613 INFO L290 TraceCheckUtils]: 122: Hoare triple {157453#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {157453#false} is VALID [2022-02-21 04:23:55,613 INFO L290 TraceCheckUtils]: 123: Hoare triple {157453#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {157453#false} is VALID [2022-02-21 04:23:55,613 INFO L290 TraceCheckUtils]: 124: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___11~0#1); {157453#false} is VALID [2022-02-21 04:23:55,613 INFO L290 TraceCheckUtils]: 125: Hoare triple {157453#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {157453#false} is VALID [2022-02-21 04:23:55,613 INFO L290 TraceCheckUtils]: 126: Hoare triple {157453#false} assume 1 == ~t13_pc~0; {157453#false} is VALID [2022-02-21 04:23:55,613 INFO L290 TraceCheckUtils]: 127: Hoare triple {157453#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {157453#false} is VALID [2022-02-21 04:23:55,613 INFO L290 TraceCheckUtils]: 128: Hoare triple {157453#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {157453#false} is VALID [2022-02-21 04:23:55,614 INFO L290 TraceCheckUtils]: 129: Hoare triple {157453#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {157453#false} is VALID [2022-02-21 04:23:55,614 INFO L290 TraceCheckUtils]: 130: Hoare triple {157453#false} assume !(0 != activate_threads_~tmp___12~0#1); {157453#false} is VALID [2022-02-21 04:23:55,614 INFO L290 TraceCheckUtils]: 131: Hoare triple {157453#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {157453#false} is VALID [2022-02-21 04:23:55,614 INFO L290 TraceCheckUtils]: 132: Hoare triple {157453#false} assume !(1 == ~M_E~0); {157453#false} is VALID [2022-02-21 04:23:55,614 INFO L290 TraceCheckUtils]: 133: Hoare triple {157453#false} assume !(1 == ~T1_E~0); {157453#false} is VALID [2022-02-21 04:23:55,614 INFO L290 TraceCheckUtils]: 134: Hoare triple {157453#false} assume !(1 == ~T2_E~0); {157453#false} is VALID [2022-02-21 04:23:55,614 INFO L290 TraceCheckUtils]: 135: Hoare triple {157453#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {157453#false} is VALID [2022-02-21 04:23:55,614 INFO L290 TraceCheckUtils]: 136: Hoare triple {157453#false} assume !(1 == ~T4_E~0); {157453#false} is VALID [2022-02-21 04:23:55,614 INFO L290 TraceCheckUtils]: 137: Hoare triple {157453#false} assume !(1 == ~T5_E~0); {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 138: Hoare triple {157453#false} assume !(1 == ~T6_E~0); {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 139: Hoare triple {157453#false} assume !(1 == ~T7_E~0); {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 140: Hoare triple {157453#false} assume !(1 == ~T8_E~0); {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 141: Hoare triple {157453#false} assume !(1 == ~T9_E~0); {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 142: Hoare triple {157453#false} assume !(1 == ~T10_E~0); {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 143: Hoare triple {157453#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 144: Hoare triple {157453#false} assume !(1 == ~T12_E~0); {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 145: Hoare triple {157453#false} assume !(1 == ~T13_E~0); {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 146: Hoare triple {157453#false} assume !(1 == ~E_M~0); {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 147: Hoare triple {157453#false} assume !(1 == ~E_1~0); {157453#false} is VALID [2022-02-21 04:23:55,615 INFO L290 TraceCheckUtils]: 148: Hoare triple {157453#false} assume !(1 == ~E_2~0); {157453#false} is VALID [2022-02-21 04:23:55,616 INFO L290 TraceCheckUtils]: 149: Hoare triple {157453#false} assume !(1 == ~E_3~0); {157453#false} is VALID [2022-02-21 04:23:55,616 INFO L290 TraceCheckUtils]: 150: Hoare triple {157453#false} assume !(1 == ~E_4~0); {157453#false} is VALID [2022-02-21 04:23:55,616 INFO L290 TraceCheckUtils]: 151: Hoare triple {157453#false} assume 1 == ~E_5~0;~E_5~0 := 2; {157453#false} is VALID [2022-02-21 04:23:55,616 INFO L290 TraceCheckUtils]: 152: Hoare triple {157453#false} assume !(1 == ~E_6~0); {157453#false} is VALID [2022-02-21 04:23:55,616 INFO L290 TraceCheckUtils]: 153: Hoare triple {157453#false} assume !(1 == ~E_7~0); {157453#false} is VALID [2022-02-21 04:23:55,616 INFO L290 TraceCheckUtils]: 154: Hoare triple {157453#false} assume !(1 == ~E_8~0); {157453#false} is VALID [2022-02-21 04:23:55,616 INFO L290 TraceCheckUtils]: 155: Hoare triple {157453#false} assume !(1 == ~E_9~0); {157453#false} is VALID [2022-02-21 04:23:55,616 INFO L290 TraceCheckUtils]: 156: Hoare triple {157453#false} assume !(1 == ~E_10~0); {157453#false} is VALID [2022-02-21 04:23:55,616 INFO L290 TraceCheckUtils]: 157: Hoare triple {157453#false} assume !(1 == ~E_11~0); {157453#false} is VALID [2022-02-21 04:23:55,617 INFO L290 TraceCheckUtils]: 158: Hoare triple {157453#false} assume !(1 == ~E_12~0); {157453#false} is VALID [2022-02-21 04:23:55,617 INFO L290 TraceCheckUtils]: 159: Hoare triple {157453#false} assume 1 == ~E_13~0;~E_13~0 := 2; {157453#false} is VALID [2022-02-21 04:23:55,617 INFO L290 TraceCheckUtils]: 160: Hoare triple {157453#false} assume { :end_inline_reset_delta_events } true; {157453#false} is VALID [2022-02-21 04:23:55,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:55,617 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:55,617 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44100561] [2022-02-21 04:23:55,618 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [44100561] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:55,618 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:55,618 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:55,618 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264051461] [2022-02-21 04:23:55,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:55,618 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:55,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:55,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1282195944, now seen corresponding path program 1 times [2022-02-21 04:23:55,619 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:55,619 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981173883] [2022-02-21 04:23:55,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:55,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:55,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:55,648 INFO L290 TraceCheckUtils]: 0: Hoare triple {157456#true} assume !false; {157456#true} is VALID [2022-02-21 04:23:55,648 INFO L290 TraceCheckUtils]: 1: Hoare triple {157456#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {157456#true} is VALID [2022-02-21 04:23:55,648 INFO L290 TraceCheckUtils]: 2: Hoare triple {157456#true} assume !false; {157456#true} is VALID [2022-02-21 04:23:55,648 INFO L290 TraceCheckUtils]: 3: Hoare triple {157456#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {157456#true} is VALID [2022-02-21 04:23:55,648 INFO L290 TraceCheckUtils]: 4: Hoare triple {157456#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {157456#true} is VALID [2022-02-21 04:23:55,648 INFO L290 TraceCheckUtils]: 5: Hoare triple {157456#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {157456#true} is VALID [2022-02-21 04:23:55,649 INFO L290 TraceCheckUtils]: 6: Hoare triple {157456#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {157456#true} is VALID [2022-02-21 04:23:55,649 INFO L290 TraceCheckUtils]: 7: Hoare triple {157456#true} assume !(0 != eval_~tmp~0#1); {157456#true} is VALID [2022-02-21 04:23:55,649 INFO L290 TraceCheckUtils]: 8: Hoare triple {157456#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {157456#true} is VALID [2022-02-21 04:23:55,649 INFO L290 TraceCheckUtils]: 9: Hoare triple {157456#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {157456#true} is VALID [2022-02-21 04:23:55,649 INFO L290 TraceCheckUtils]: 10: Hoare triple {157456#true} assume !(0 == ~M_E~0); {157456#true} is VALID [2022-02-21 04:23:55,649 INFO L290 TraceCheckUtils]: 11: Hoare triple {157456#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,649 INFO L290 TraceCheckUtils]: 12: Hoare triple {157456#true} assume !(0 == ~T2_E~0); {157456#true} is VALID [2022-02-21 04:23:55,649 INFO L290 TraceCheckUtils]: 13: Hoare triple {157456#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,649 INFO L290 TraceCheckUtils]: 14: Hoare triple {157456#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,649 INFO L290 TraceCheckUtils]: 15: Hoare triple {157456#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,650 INFO L290 TraceCheckUtils]: 16: Hoare triple {157456#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,650 INFO L290 TraceCheckUtils]: 17: Hoare triple {157456#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,650 INFO L290 TraceCheckUtils]: 18: Hoare triple {157456#true} assume !(0 == ~T8_E~0); {157456#true} is VALID [2022-02-21 04:23:55,650 INFO L290 TraceCheckUtils]: 19: Hoare triple {157456#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,650 INFO L290 TraceCheckUtils]: 20: Hoare triple {157456#true} assume !(0 == ~T10_E~0); {157456#true} is VALID [2022-02-21 04:23:55,650 INFO L290 TraceCheckUtils]: 21: Hoare triple {157456#true} assume 0 == ~T11_E~0;~T11_E~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,650 INFO L290 TraceCheckUtils]: 22: Hoare triple {157456#true} assume 0 == ~T12_E~0;~T12_E~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,650 INFO L290 TraceCheckUtils]: 23: Hoare triple {157456#true} assume 0 == ~T13_E~0;~T13_E~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,650 INFO L290 TraceCheckUtils]: 24: Hoare triple {157456#true} assume 0 == ~E_M~0;~E_M~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,650 INFO L290 TraceCheckUtils]: 25: Hoare triple {157456#true} assume 0 == ~E_1~0;~E_1~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,651 INFO L290 TraceCheckUtils]: 26: Hoare triple {157456#true} assume !(0 == ~E_2~0); {157456#true} is VALID [2022-02-21 04:23:55,651 INFO L290 TraceCheckUtils]: 27: Hoare triple {157456#true} assume 0 == ~E_3~0;~E_3~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,651 INFO L290 TraceCheckUtils]: 28: Hoare triple {157456#true} assume !(0 == ~E_4~0); {157456#true} is VALID [2022-02-21 04:23:55,651 INFO L290 TraceCheckUtils]: 29: Hoare triple {157456#true} assume 0 == ~E_5~0;~E_5~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,651 INFO L290 TraceCheckUtils]: 30: Hoare triple {157456#true} assume 0 == ~E_6~0;~E_6~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,651 INFO L290 TraceCheckUtils]: 31: Hoare triple {157456#true} assume 0 == ~E_7~0;~E_7~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,651 INFO L290 TraceCheckUtils]: 32: Hoare triple {157456#true} assume 0 == ~E_8~0;~E_8~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,651 INFO L290 TraceCheckUtils]: 33: Hoare triple {157456#true} assume 0 == ~E_9~0;~E_9~0 := 1; {157456#true} is VALID [2022-02-21 04:23:55,652 INFO L290 TraceCheckUtils]: 34: Hoare triple {157456#true} assume 0 == ~E_10~0;~E_10~0 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,652 INFO L290 TraceCheckUtils]: 35: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,652 INFO L290 TraceCheckUtils]: 36: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(0 == ~E_12~0); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,652 INFO L290 TraceCheckUtils]: 37: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,653 INFO L290 TraceCheckUtils]: 38: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,653 INFO L290 TraceCheckUtils]: 39: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(1 == ~m_pc~0); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,653 INFO L290 TraceCheckUtils]: 40: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_master_triggered_~__retres1~0#1 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,654 INFO L290 TraceCheckUtils]: 41: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,654 INFO L290 TraceCheckUtils]: 42: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,654 INFO L290 TraceCheckUtils]: 43: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,654 INFO L290 TraceCheckUtils]: 44: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,655 INFO L290 TraceCheckUtils]: 45: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(1 == ~t1_pc~0); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,655 INFO L290 TraceCheckUtils]: 46: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,655 INFO L290 TraceCheckUtils]: 47: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,656 INFO L290 TraceCheckUtils]: 48: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,656 INFO L290 TraceCheckUtils]: 49: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,656 INFO L290 TraceCheckUtils]: 50: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,657 INFO L290 TraceCheckUtils]: 51: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(1 == ~t2_pc~0); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,657 INFO L290 TraceCheckUtils]: 52: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,657 INFO L290 TraceCheckUtils]: 53: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,657 INFO L290 TraceCheckUtils]: 54: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,658 INFO L290 TraceCheckUtils]: 55: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,658 INFO L290 TraceCheckUtils]: 56: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,658 INFO L290 TraceCheckUtils]: 57: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~t3_pc~0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,659 INFO L290 TraceCheckUtils]: 58: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,659 INFO L290 TraceCheckUtils]: 59: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,659 INFO L290 TraceCheckUtils]: 60: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,660 INFO L290 TraceCheckUtils]: 61: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,660 INFO L290 TraceCheckUtils]: 62: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,660 INFO L290 TraceCheckUtils]: 63: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~t4_pc~0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,660 INFO L290 TraceCheckUtils]: 64: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,661 INFO L290 TraceCheckUtils]: 65: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,661 INFO L290 TraceCheckUtils]: 66: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,661 INFO L290 TraceCheckUtils]: 67: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,662 INFO L290 TraceCheckUtils]: 68: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,662 INFO L290 TraceCheckUtils]: 69: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(1 == ~t5_pc~0); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,662 INFO L290 TraceCheckUtils]: 70: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,663 INFO L290 TraceCheckUtils]: 71: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,663 INFO L290 TraceCheckUtils]: 72: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,663 INFO L290 TraceCheckUtils]: 73: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,664 INFO L290 TraceCheckUtils]: 74: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,664 INFO L290 TraceCheckUtils]: 75: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~t6_pc~0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,664 INFO L290 TraceCheckUtils]: 76: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,665 INFO L290 TraceCheckUtils]: 77: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,665 INFO L290 TraceCheckUtils]: 78: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,665 INFO L290 TraceCheckUtils]: 79: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,665 INFO L290 TraceCheckUtils]: 80: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,666 INFO L290 TraceCheckUtils]: 81: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~t7_pc~0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,666 INFO L290 TraceCheckUtils]: 82: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,666 INFO L290 TraceCheckUtils]: 83: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,667 INFO L290 TraceCheckUtils]: 84: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,667 INFO L290 TraceCheckUtils]: 85: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,667 INFO L290 TraceCheckUtils]: 86: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,667 INFO L290 TraceCheckUtils]: 87: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~t8_pc~0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,668 INFO L290 TraceCheckUtils]: 88: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,668 INFO L290 TraceCheckUtils]: 89: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,668 INFO L290 TraceCheckUtils]: 90: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,669 INFO L290 TraceCheckUtils]: 91: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,669 INFO L290 TraceCheckUtils]: 92: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,669 INFO L290 TraceCheckUtils]: 93: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(1 == ~t9_pc~0); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,669 INFO L290 TraceCheckUtils]: 94: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,670 INFO L290 TraceCheckUtils]: 95: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,670 INFO L290 TraceCheckUtils]: 96: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,670 INFO L290 TraceCheckUtils]: 97: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,671 INFO L290 TraceCheckUtils]: 98: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,671 INFO L290 TraceCheckUtils]: 99: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~t10_pc~0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,671 INFO L290 TraceCheckUtils]: 100: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,671 INFO L290 TraceCheckUtils]: 101: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,672 INFO L290 TraceCheckUtils]: 102: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,672 INFO L290 TraceCheckUtils]: 103: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,672 INFO L290 TraceCheckUtils]: 104: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,673 INFO L290 TraceCheckUtils]: 105: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(1 == ~t11_pc~0); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,673 INFO L290 TraceCheckUtils]: 106: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,673 INFO L290 TraceCheckUtils]: 107: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,673 INFO L290 TraceCheckUtils]: 108: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,674 INFO L290 TraceCheckUtils]: 109: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,674 INFO L290 TraceCheckUtils]: 110: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,674 INFO L290 TraceCheckUtils]: 111: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~t12_pc~0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,675 INFO L290 TraceCheckUtils]: 112: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,675 INFO L290 TraceCheckUtils]: 113: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,675 INFO L290 TraceCheckUtils]: 114: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,676 INFO L290 TraceCheckUtils]: 115: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,676 INFO L290 TraceCheckUtils]: 116: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,676 INFO L290 TraceCheckUtils]: 117: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~t13_pc~0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,677 INFO L290 TraceCheckUtils]: 118: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,677 INFO L290 TraceCheckUtils]: 119: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,677 INFO L290 TraceCheckUtils]: 120: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,678 INFO L290 TraceCheckUtils]: 121: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,678 INFO L290 TraceCheckUtils]: 122: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,678 INFO L290 TraceCheckUtils]: 123: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(1 == ~M_E~0); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,679 INFO L290 TraceCheckUtils]: 124: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,679 INFO L290 TraceCheckUtils]: 125: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,679 INFO L290 TraceCheckUtils]: 126: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,679 INFO L290 TraceCheckUtils]: 127: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,680 INFO L290 TraceCheckUtils]: 128: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,680 INFO L290 TraceCheckUtils]: 129: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,680 INFO L290 TraceCheckUtils]: 130: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,681 INFO L290 TraceCheckUtils]: 131: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(1 == ~T8_E~0); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,681 INFO L290 TraceCheckUtils]: 132: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,681 INFO L290 TraceCheckUtils]: 133: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T10_E~0;~T10_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,682 INFO L290 TraceCheckUtils]: 134: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T11_E~0;~T11_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,682 INFO L290 TraceCheckUtils]: 135: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T12_E~0;~T12_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,682 INFO L290 TraceCheckUtils]: 136: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~T13_E~0;~T13_E~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,682 INFO L290 TraceCheckUtils]: 137: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,683 INFO L290 TraceCheckUtils]: 138: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,683 INFO L290 TraceCheckUtils]: 139: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(1 == ~E_2~0); {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,683 INFO L290 TraceCheckUtils]: 140: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,684 INFO L290 TraceCheckUtils]: 141: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,684 INFO L290 TraceCheckUtils]: 142: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,684 INFO L290 TraceCheckUtils]: 143: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_6~0;~E_6~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,684 INFO L290 TraceCheckUtils]: 144: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_7~0;~E_7~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,685 INFO L290 TraceCheckUtils]: 145: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_8~0;~E_8~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,685 INFO L290 TraceCheckUtils]: 146: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume 1 == ~E_9~0;~E_9~0 := 2; {157458#(= (+ ~E_10~0 (- 1)) 0)} is VALID [2022-02-21 04:23:55,685 INFO L290 TraceCheckUtils]: 147: Hoare triple {157458#(= (+ ~E_10~0 (- 1)) 0)} assume !(1 == ~E_10~0); {157457#false} is VALID [2022-02-21 04:23:55,685 INFO L290 TraceCheckUtils]: 148: Hoare triple {157457#false} assume 1 == ~E_11~0;~E_11~0 := 2; {157457#false} is VALID [2022-02-21 04:23:55,686 INFO L290 TraceCheckUtils]: 149: Hoare triple {157457#false} assume 1 == ~E_12~0;~E_12~0 := 2; {157457#false} is VALID [2022-02-21 04:23:55,686 INFO L290 TraceCheckUtils]: 150: Hoare triple {157457#false} assume 1 == ~E_13~0;~E_13~0 := 2; {157457#false} is VALID [2022-02-21 04:23:55,686 INFO L290 TraceCheckUtils]: 151: Hoare triple {157457#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {157457#false} is VALID [2022-02-21 04:23:55,686 INFO L290 TraceCheckUtils]: 152: Hoare triple {157457#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {157457#false} is VALID [2022-02-21 04:23:55,686 INFO L290 TraceCheckUtils]: 153: Hoare triple {157457#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {157457#false} is VALID [2022-02-21 04:23:55,686 INFO L290 TraceCheckUtils]: 154: Hoare triple {157457#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {157457#false} is VALID [2022-02-21 04:23:55,686 INFO L290 TraceCheckUtils]: 155: Hoare triple {157457#false} assume !(0 == start_simulation_~tmp~3#1); {157457#false} is VALID [2022-02-21 04:23:55,686 INFO L290 TraceCheckUtils]: 156: Hoare triple {157457#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {157457#false} is VALID [2022-02-21 04:23:55,686 INFO L290 TraceCheckUtils]: 157: Hoare triple {157457#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {157457#false} is VALID [2022-02-21 04:23:55,686 INFO L290 TraceCheckUtils]: 158: Hoare triple {157457#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {157457#false} is VALID [2022-02-21 04:23:55,687 INFO L290 TraceCheckUtils]: 159: Hoare triple {157457#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {157457#false} is VALID [2022-02-21 04:23:55,687 INFO L290 TraceCheckUtils]: 160: Hoare triple {157457#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {157457#false} is VALID [2022-02-21 04:23:55,687 INFO L290 TraceCheckUtils]: 161: Hoare triple {157457#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {157457#false} is VALID [2022-02-21 04:23:55,687 INFO L290 TraceCheckUtils]: 162: Hoare triple {157457#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {157457#false} is VALID [2022-02-21 04:23:55,687 INFO L290 TraceCheckUtils]: 163: Hoare triple {157457#false} assume !(0 != start_simulation_~tmp___0~1#1); {157457#false} is VALID [2022-02-21 04:23:55,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:55,687 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:55,688 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981173883] [2022-02-21 04:23:55,688 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981173883] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:55,688 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:55,688 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:55,688 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108051345] [2022-02-21 04:23:55,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:55,688 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:55,689 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:55,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:55,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:55,689 INFO L87 Difference]: Start difference. First operand 3761 states and 5487 transitions. cyclomatic complexity: 1727 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:58,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:58,929 INFO L93 Difference]: Finished difference Result 5381 states and 7833 transitions. [2022-02-21 04:23:58,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:58,930 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:58,984 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:58,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5381 states and 7833 transitions. [2022-02-21 04:23:59,956 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5201 [2022-02-21 04:24:00,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5381 states to 5381 states and 7833 transitions. [2022-02-21 04:24:00,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5381 [2022-02-21 04:24:00,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5381 [2022-02-21 04:24:00,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5381 states and 7833 transitions. [2022-02-21 04:24:00,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:00,903 INFO L681 BuchiCegarLoop]: Abstraction has 5381 states and 7833 transitions. [2022-02-21 04:24:00,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5381 states and 7833 transitions. [2022-02-21 04:24:00,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5381 to 3761. [2022-02-21 04:24:00,944 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:00,948 INFO L82 GeneralOperation]: Start isEquivalent. First operand 5381 states and 7833 transitions. Second operand has 3761 states, 3761 states have (on average 1.4581228396703005) internal successors, (5484), 3760 states have internal predecessors, (5484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:00,951 INFO L74 IsIncluded]: Start isIncluded. First operand 5381 states and 7833 transitions. Second operand has 3761 states, 3761 states have (on average 1.4581228396703005) internal successors, (5484), 3760 states have internal predecessors, (5484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:00,990 INFO L87 Difference]: Start difference. First operand 5381 states and 7833 transitions. Second operand has 3761 states, 3761 states have (on average 1.4581228396703005) internal successors, (5484), 3760 states have internal predecessors, (5484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:01,659 INFO L93 Difference]: Finished difference Result 5381 states and 7833 transitions. [2022-02-21 04:24:01,659 INFO L276 IsEmpty]: Start isEmpty. Operand 5381 states and 7833 transitions. [2022-02-21 04:24:01,663 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:01,663 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:01,666 INFO L74 IsIncluded]: Start isIncluded. First operand has 3761 states, 3761 states have (on average 1.4581228396703005) internal successors, (5484), 3760 states have internal predecessors, (5484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5381 states and 7833 transitions. [2022-02-21 04:24:01,668 INFO L87 Difference]: Start difference. First operand has 3761 states, 3761 states have (on average 1.4581228396703005) internal successors, (5484), 3760 states have internal predecessors, (5484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5381 states and 7833 transitions. [2022-02-21 04:24:02,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,308 INFO L93 Difference]: Finished difference Result 5381 states and 7833 transitions. [2022-02-21 04:24:02,309 INFO L276 IsEmpty]: Start isEmpty. Operand 5381 states and 7833 transitions. [2022-02-21 04:24:02,312 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:02,312 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:02,312 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:02,312 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:02,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4581228396703005) internal successors, (5484), 3760 states have internal predecessors, (5484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5484 transitions. [2022-02-21 04:24:02,619 INFO L704 BuchiCegarLoop]: Abstraction has 3761 states and 5484 transitions. [2022-02-21 04:24:02,619 INFO L587 BuchiCegarLoop]: Abstraction has 3761 states and 5484 transitions. [2022-02-21 04:24:02,619 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2022-02-21 04:24:02,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5484 transitions. [2022-02-21 04:24:02,625 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-02-21 04:24:02,625 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:02,625 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:02,626 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,626 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,627 INFO L791 eck$LassoCheckResult]: Stem: 163754#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 163755#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 164797#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 164247#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 164248#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 163736#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 163737#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 163803#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 163804#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 164243#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 164244#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 163769#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 163587#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 163588#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 164033#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 164034#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 163909#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 163910#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 163559#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 163560#L1279 assume !(0 == ~M_E~0); 164789#L1279-2 assume !(0 == ~T1_E~0); 163183#L1284-1 assume !(0 == ~T2_E~0); 163184#L1289-1 assume !(0 == ~T3_E~0); 163906#L1294-1 assume !(0 == ~T4_E~0); 163907#L1299-1 assume !(0 == ~T5_E~0); 163918#L1304-1 assume !(0 == ~T6_E~0); 164857#L1309-1 assume !(0 == ~T7_E~0); 164858#L1314-1 assume !(0 == ~T8_E~0); 163114#L1319-1 assume !(0 == ~T9_E~0); 163115#L1324-1 assume !(0 == ~T10_E~0); 163286#L1329-1 assume !(0 == ~T11_E~0); 163287#L1334-1 assume !(0 == ~T12_E~0); 164695#L1339-1 assume !(0 == ~T13_E~0); 164777#L1344-1 assume !(0 == ~E_M~0); 164778#L1349-1 assume !(0 == ~E_1~0); 164094#L1354-1 assume !(0 == ~E_2~0); 164095#L1359-1 assume !(0 == ~E_3~0); 164526#L1364-1 assume !(0 == ~E_4~0); 163415#L1369-1 assume !(0 == ~E_5~0); 163416#L1374-1 assume !(0 == ~E_6~0); 164099#L1379-1 assume !(0 == ~E_7~0); 164100#L1384-1 assume !(0 == ~E_8~0); 164177#L1389-1 assume !(0 == ~E_9~0); 164714#L1394-1 assume !(0 == ~E_10~0); 164715#L1399-1 assume !(0 == ~E_11~0); 164819#L1404-1 assume !(0 == ~E_12~0); 163507#L1409-1 assume !(0 == ~E_13~0); 163508#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164811#L628 assume !(1 == ~m_pc~0); 163412#L628-2 is_master_triggered_~__retres1~0#1 := 0; 163411#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 164175#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 164176#L1591 assume !(0 != activate_threads_~tmp~1#1); 164824#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163962#L647 assume 1 == ~t1_pc~0; 163332#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 163333#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163602#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 163603#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 164764#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 164765#L666 assume !(1 == ~t2_pc~0); 163182#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 163347#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163348#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 164781#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 164295#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164296#L685 assume !(1 == ~t3_pc~0); 164401#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 164400#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 164022#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 164023#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 164145#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163629#L704 assume 1 == ~t4_pc~0; 163630#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 164156#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164157#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 164802#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 164015#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 164016#L723 assume !(1 == ~t5_pc~0); 164139#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 164375#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164521#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 164274#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 164275#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163397#L742 assume 1 == ~t6_pc~0; 163398#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 163545#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163546#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 163083#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 163084#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163474#L761 assume !(1 == ~t7_pc~0); 163475#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 163343#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 163344#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 164146#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 164147#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 163108#L780 assume 1 == ~t8_pc~0; 163109#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 163384#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 163385#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 164107#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 164108#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 164227#L799 assume 1 == ~t9_pc~0; 164339#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 163111#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 163112#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 164239#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 164446#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 164257#L818 assume !(1 == ~t10_pc~0); 162893#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 162894#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 164332#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 164261#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 164262#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 164302#L837 assume 1 == ~t11_pc~0; 164303#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 164137#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 164542#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 164220#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 164221#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 163971#L856 assume !(1 == ~t12_pc~0); 163972#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 164629#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 164630#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 164610#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 164611#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 164792#L875 assume 1 == ~t13_pc~0; 163916#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 163548#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 163549#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 163489#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 163490#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164329#L1427 assume !(1 == ~M_E~0); 164313#L1427-2 assume !(1 == ~T1_E~0); 163461#L1432-1 assume !(1 == ~T2_E~0); 163462#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 164532#L1442-1 assume !(1 == ~T4_E~0); 164533#L1447-1 assume !(1 == ~T5_E~0); 164386#L1452-1 assume !(1 == ~T6_E~0); 163027#L1457-1 assume !(1 == ~T7_E~0); 163028#L1462-1 assume !(1 == ~T8_E~0); 164559#L1467-1 assume !(1 == ~T9_E~0); 164577#L1472-1 assume !(1 == ~T10_E~0); 164578#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 164327#L1482-1 assume !(1 == ~T12_E~0); 164328#L1487-1 assume !(1 == ~T13_E~0); 163358#L1492-1 assume !(1 == ~E_M~0); 163359#L1497-1 assume !(1 == ~E_1~0); 163718#L1502-1 assume !(1 == ~E_2~0); 163719#L1507-1 assume !(1 == ~E_3~0); 163235#L1512-1 assume !(1 == ~E_4~0); 163236#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 164649#L1522-1 assume !(1 == ~E_6~0); 163959#L1527-1 assume !(1 == ~E_7~0); 163960#L1532-1 assume !(1 == ~E_8~0); 164840#L1537-1 assume !(1 == ~E_9~0); 164163#L1542-1 assume !(1 == ~E_10~0); 163993#L1547-1 assume !(1 == ~E_11~0); 163994#L1552-1 assume !(1 == ~E_12~0); 162932#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 162933#L1562-1 assume { :end_inline_reset_delta_events } true; 163536#L1928-2 [2022-02-21 04:24:02,627 INFO L793 eck$LassoCheckResult]: Loop: 163536#L1928-2 assume !false; 164027#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 163191#L1254 assume !false; 163777#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 163265#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 163266#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 163463#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 164637#L1067 assume !(0 != eval_~tmp~0#1); 163703#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 163281#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163282#L1279-3 assume !(0 == ~M_E~0); 163740#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 163722#L1284-3 assume !(0 == ~T2_E~0); 163723#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 163701#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 163702#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 164090#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 164091#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 163598#L1314-3 assume !(0 == ~T8_E~0); 163599#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 164600#L1324-3 assume !(0 == ~T10_E~0); 163232#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 163233#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 163999#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 164000#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 164299#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 163580#L1354-3 assume !(0 == ~E_2~0); 163581#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 164310#L1364-3 assume !(0 == ~E_4~0); 164838#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 164733#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 163362#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 163363#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 163578#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 163579#L1394-3 assume !(0 == ~E_10~0); 163869#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 164743#L1404-3 assume !(0 == ~E_12~0); 164706#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 164707#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164189#L628-45 assume 1 == ~m_pc~0; 163866#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 163868#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163226#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163227#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 163613#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164338#L647-45 assume 1 == ~t1_pc~0; 163178#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 163179#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 164106#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 163291#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 163292#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163502#L666-45 assume !(1 == ~t2_pc~0); 163503#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 163984#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 164549#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 164462#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 164456#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163042#L685-45 assume 1 == ~t3_pc~0; 163043#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 164101#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 164780#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 164647#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 164648#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164790#L704-45 assume 1 == ~t4_pc~0; 164667#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 162910#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163766#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 164110#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 164866#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 164222#L723-45 assume 1 == ~t5_pc~0; 164224#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 164716#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163813#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 163589#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 163590#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 164619#L742-45 assume 1 == ~t6_pc~0; 164620#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 163838#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 164308#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 164344#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 164345#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 164433#L761-45 assume !(1 == ~t7_pc~0); 164434#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 163831#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 163832#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 163239#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 163240#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 164710#L780-45 assume !(1 == ~t8_pc~0); 163616#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 163251#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 163252#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 164839#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 163221#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 163222#L799-45 assume !(1 == ~t9_pc~0); 163442#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 163443#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 164763#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 164387#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 164388#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 163160#L818-45 assume !(1 == ~t10_pc~0); 163162#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 163278#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 164361#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 163764#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 163765#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 164481#L837-45 assume 1 == ~t11_pc~0; 164775#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 163696#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 163833#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 164500#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 163297#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 163298#L856-45 assume !(1 == ~t12_pc~0); 163299#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 163300#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 163241#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 163242#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 164104#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 164105#L875-45 assume 1 == ~t13_pc~0; 164075#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 164076#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 164138#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 164755#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 164756#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164694#L1427-3 assume !(1 == ~M_E~0); 163900#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 163901#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 164440#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 164092#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 164093#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 162951#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 162952#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 164635#L1462-3 assume !(1 == ~T8_E~0); 164636#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 164497#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 164498#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 163200#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 163201#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 163342#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 163514#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 163515#L1502-3 assume !(1 == ~E_2~0); 164464#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 164597#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 163552#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 163245#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 163246#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 163210#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 163211#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 164311#L1542-3 assume !(1 == ~E_10~0); 164449#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 164078#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 164079#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 163421#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 163422#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 162843#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 163604#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 163605#L1947 assume !(0 == start_simulation_~tmp~3#1); 164212#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 164417#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 163478#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 164815#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 164739#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 164566#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 164323#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 164324#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 163536#L1928-2 [2022-02-21 04:24:02,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,628 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2022-02-21 04:24:02,628 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,628 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383311753] [2022-02-21 04:24:02,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:02,652 INFO L290 TraceCheckUtils]: 0: Hoare triple {177368#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,653 INFO L290 TraceCheckUtils]: 1: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,653 INFO L290 TraceCheckUtils]: 2: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,653 INFO L290 TraceCheckUtils]: 3: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,654 INFO L290 TraceCheckUtils]: 4: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,654 INFO L290 TraceCheckUtils]: 5: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,654 INFO L290 TraceCheckUtils]: 6: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,654 INFO L290 TraceCheckUtils]: 7: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,655 INFO L290 TraceCheckUtils]: 8: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,655 INFO L290 TraceCheckUtils]: 9: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,655 INFO L290 TraceCheckUtils]: 10: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,656 INFO L290 TraceCheckUtils]: 11: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,656 INFO L290 TraceCheckUtils]: 12: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,656 INFO L290 TraceCheckUtils]: 13: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,656 INFO L290 TraceCheckUtils]: 14: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,657 INFO L290 TraceCheckUtils]: 15: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,657 INFO L290 TraceCheckUtils]: 16: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,657 INFO L290 TraceCheckUtils]: 17: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,657 INFO L290 TraceCheckUtils]: 18: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,658 INFO L290 TraceCheckUtils]: 19: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,658 INFO L290 TraceCheckUtils]: 20: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,658 INFO L290 TraceCheckUtils]: 21: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,659 INFO L290 TraceCheckUtils]: 22: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,659 INFO L290 TraceCheckUtils]: 23: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,659 INFO L290 TraceCheckUtils]: 24: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,659 INFO L290 TraceCheckUtils]: 25: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,660 INFO L290 TraceCheckUtils]: 26: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T7_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,660 INFO L290 TraceCheckUtils]: 27: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T8_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,660 INFO L290 TraceCheckUtils]: 28: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T9_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,660 INFO L290 TraceCheckUtils]: 29: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T10_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,661 INFO L290 TraceCheckUtils]: 30: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T11_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,661 INFO L290 TraceCheckUtils]: 31: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T12_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,661 INFO L290 TraceCheckUtils]: 32: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T13_E~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,661 INFO L290 TraceCheckUtils]: 33: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_M~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,662 INFO L290 TraceCheckUtils]: 34: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,662 INFO L290 TraceCheckUtils]: 35: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,662 INFO L290 TraceCheckUtils]: 36: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,663 INFO L290 TraceCheckUtils]: 37: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,663 INFO L290 TraceCheckUtils]: 38: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,663 INFO L290 TraceCheckUtils]: 39: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,663 INFO L290 TraceCheckUtils]: 40: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_7~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,664 INFO L290 TraceCheckUtils]: 41: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_8~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,664 INFO L290 TraceCheckUtils]: 42: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_9~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,664 INFO L290 TraceCheckUtils]: 43: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_10~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,664 INFO L290 TraceCheckUtils]: 44: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_11~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,665 INFO L290 TraceCheckUtils]: 45: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_12~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,665 INFO L290 TraceCheckUtils]: 46: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_13~0); {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,665 INFO L290 TraceCheckUtils]: 47: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {177370#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:02,665 INFO L290 TraceCheckUtils]: 48: Hoare triple {177370#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {177371#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:02,666 INFO L290 TraceCheckUtils]: 49: Hoare triple {177371#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {177371#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:02,666 INFO L290 TraceCheckUtils]: 50: Hoare triple {177371#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {177371#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:02,666 INFO L290 TraceCheckUtils]: 51: Hoare triple {177371#(not (= ~t1_pc~0 1))} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {177371#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:02,666 INFO L290 TraceCheckUtils]: 52: Hoare triple {177371#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {177371#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:02,667 INFO L290 TraceCheckUtils]: 53: Hoare triple {177371#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {177371#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:02,667 INFO L290 TraceCheckUtils]: 54: Hoare triple {177371#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {177369#false} is VALID [2022-02-21 04:24:02,667 INFO L290 TraceCheckUtils]: 55: Hoare triple {177369#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {177369#false} is VALID [2022-02-21 04:24:02,667 INFO L290 TraceCheckUtils]: 56: Hoare triple {177369#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {177369#false} is VALID [2022-02-21 04:24:02,667 INFO L290 TraceCheckUtils]: 57: Hoare triple {177369#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {177369#false} is VALID [2022-02-21 04:24:02,667 INFO L290 TraceCheckUtils]: 58: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___0~0#1); {177369#false} is VALID [2022-02-21 04:24:02,667 INFO L290 TraceCheckUtils]: 59: Hoare triple {177369#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 60: Hoare triple {177369#false} assume !(1 == ~t2_pc~0); {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 61: Hoare triple {177369#false} is_transmit2_triggered_~__retres1~2#1 := 0; {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 62: Hoare triple {177369#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 63: Hoare triple {177369#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 64: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___1~0#1); {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 65: Hoare triple {177369#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 66: Hoare triple {177369#false} assume !(1 == ~t3_pc~0); {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 67: Hoare triple {177369#false} is_transmit3_triggered_~__retres1~3#1 := 0; {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 68: Hoare triple {177369#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 69: Hoare triple {177369#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {177369#false} is VALID [2022-02-21 04:24:02,668 INFO L290 TraceCheckUtils]: 70: Hoare triple {177369#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {177369#false} is VALID [2022-02-21 04:24:02,669 INFO L290 TraceCheckUtils]: 71: Hoare triple {177369#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {177369#false} is VALID [2022-02-21 04:24:02,669 INFO L290 TraceCheckUtils]: 72: Hoare triple {177369#false} assume 1 == ~t4_pc~0; {177369#false} is VALID [2022-02-21 04:24:02,669 INFO L290 TraceCheckUtils]: 73: Hoare triple {177369#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {177369#false} is VALID [2022-02-21 04:24:02,669 INFO L290 TraceCheckUtils]: 74: Hoare triple {177369#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {177369#false} is VALID [2022-02-21 04:24:02,669 INFO L290 TraceCheckUtils]: 75: Hoare triple {177369#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {177369#false} is VALID [2022-02-21 04:24:02,669 INFO L290 TraceCheckUtils]: 76: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___3~0#1); {177369#false} is VALID [2022-02-21 04:24:02,669 INFO L290 TraceCheckUtils]: 77: Hoare triple {177369#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {177369#false} is VALID [2022-02-21 04:24:02,669 INFO L290 TraceCheckUtils]: 78: Hoare triple {177369#false} assume !(1 == ~t5_pc~0); {177369#false} is VALID [2022-02-21 04:24:02,669 INFO L290 TraceCheckUtils]: 79: Hoare triple {177369#false} is_transmit5_triggered_~__retres1~5#1 := 0; {177369#false} is VALID [2022-02-21 04:24:02,669 INFO L290 TraceCheckUtils]: 80: Hoare triple {177369#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 81: Hoare triple {177369#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 82: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___4~0#1); {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 83: Hoare triple {177369#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 84: Hoare triple {177369#false} assume 1 == ~t6_pc~0; {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 85: Hoare triple {177369#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 86: Hoare triple {177369#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 87: Hoare triple {177369#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 88: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___5~0#1); {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 89: Hoare triple {177369#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 90: Hoare triple {177369#false} assume !(1 == ~t7_pc~0); {177369#false} is VALID [2022-02-21 04:24:02,670 INFO L290 TraceCheckUtils]: 91: Hoare triple {177369#false} is_transmit7_triggered_~__retres1~7#1 := 0; {177369#false} is VALID [2022-02-21 04:24:02,671 INFO L290 TraceCheckUtils]: 92: Hoare triple {177369#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {177369#false} is VALID [2022-02-21 04:24:02,671 INFO L290 TraceCheckUtils]: 93: Hoare triple {177369#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {177369#false} is VALID [2022-02-21 04:24:02,671 INFO L290 TraceCheckUtils]: 94: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___6~0#1); {177369#false} is VALID [2022-02-21 04:24:02,671 INFO L290 TraceCheckUtils]: 95: Hoare triple {177369#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {177369#false} is VALID [2022-02-21 04:24:02,671 INFO L290 TraceCheckUtils]: 96: Hoare triple {177369#false} assume 1 == ~t8_pc~0; {177369#false} is VALID [2022-02-21 04:24:02,671 INFO L290 TraceCheckUtils]: 97: Hoare triple {177369#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {177369#false} is VALID [2022-02-21 04:24:02,671 INFO L290 TraceCheckUtils]: 98: Hoare triple {177369#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {177369#false} is VALID [2022-02-21 04:24:02,671 INFO L290 TraceCheckUtils]: 99: Hoare triple {177369#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {177369#false} is VALID [2022-02-21 04:24:02,671 INFO L290 TraceCheckUtils]: 100: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___7~0#1); {177369#false} is VALID [2022-02-21 04:24:02,671 INFO L290 TraceCheckUtils]: 101: Hoare triple {177369#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 102: Hoare triple {177369#false} assume 1 == ~t9_pc~0; {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 103: Hoare triple {177369#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 104: Hoare triple {177369#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 105: Hoare triple {177369#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 106: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___8~0#1); {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 107: Hoare triple {177369#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 108: Hoare triple {177369#false} assume !(1 == ~t10_pc~0); {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 109: Hoare triple {177369#false} is_transmit10_triggered_~__retres1~10#1 := 0; {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 110: Hoare triple {177369#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 111: Hoare triple {177369#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {177369#false} is VALID [2022-02-21 04:24:02,672 INFO L290 TraceCheckUtils]: 112: Hoare triple {177369#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 113: Hoare triple {177369#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 114: Hoare triple {177369#false} assume 1 == ~t11_pc~0; {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 115: Hoare triple {177369#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 116: Hoare triple {177369#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 117: Hoare triple {177369#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 118: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___10~0#1); {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 119: Hoare triple {177369#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 120: Hoare triple {177369#false} assume !(1 == ~t12_pc~0); {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 121: Hoare triple {177369#false} is_transmit12_triggered_~__retres1~12#1 := 0; {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 122: Hoare triple {177369#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {177369#false} is VALID [2022-02-21 04:24:02,673 INFO L290 TraceCheckUtils]: 123: Hoare triple {177369#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {177369#false} is VALID [2022-02-21 04:24:02,674 INFO L290 TraceCheckUtils]: 124: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___11~0#1); {177369#false} is VALID [2022-02-21 04:24:02,674 INFO L290 TraceCheckUtils]: 125: Hoare triple {177369#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {177369#false} is VALID [2022-02-21 04:24:02,674 INFO L290 TraceCheckUtils]: 126: Hoare triple {177369#false} assume 1 == ~t13_pc~0; {177369#false} is VALID [2022-02-21 04:24:02,674 INFO L290 TraceCheckUtils]: 127: Hoare triple {177369#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {177369#false} is VALID [2022-02-21 04:24:02,674 INFO L290 TraceCheckUtils]: 128: Hoare triple {177369#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {177369#false} is VALID [2022-02-21 04:24:02,674 INFO L290 TraceCheckUtils]: 129: Hoare triple {177369#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {177369#false} is VALID [2022-02-21 04:24:02,674 INFO L290 TraceCheckUtils]: 130: Hoare triple {177369#false} assume !(0 != activate_threads_~tmp___12~0#1); {177369#false} is VALID [2022-02-21 04:24:02,674 INFO L290 TraceCheckUtils]: 131: Hoare triple {177369#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {177369#false} is VALID [2022-02-21 04:24:02,674 INFO L290 TraceCheckUtils]: 132: Hoare triple {177369#false} assume !(1 == ~M_E~0); {177369#false} is VALID [2022-02-21 04:24:02,674 INFO L290 TraceCheckUtils]: 133: Hoare triple {177369#false} assume !(1 == ~T1_E~0); {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 134: Hoare triple {177369#false} assume !(1 == ~T2_E~0); {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 135: Hoare triple {177369#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 136: Hoare triple {177369#false} assume !(1 == ~T4_E~0); {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 137: Hoare triple {177369#false} assume !(1 == ~T5_E~0); {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 138: Hoare triple {177369#false} assume !(1 == ~T6_E~0); {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 139: Hoare triple {177369#false} assume !(1 == ~T7_E~0); {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 140: Hoare triple {177369#false} assume !(1 == ~T8_E~0); {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 141: Hoare triple {177369#false} assume !(1 == ~T9_E~0); {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 142: Hoare triple {177369#false} assume !(1 == ~T10_E~0); {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 143: Hoare triple {177369#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {177369#false} is VALID [2022-02-21 04:24:02,675 INFO L290 TraceCheckUtils]: 144: Hoare triple {177369#false} assume !(1 == ~T12_E~0); {177369#false} is VALID [2022-02-21 04:24:02,676 INFO L290 TraceCheckUtils]: 145: Hoare triple {177369#false} assume !(1 == ~T13_E~0); {177369#false} is VALID [2022-02-21 04:24:02,676 INFO L290 TraceCheckUtils]: 146: Hoare triple {177369#false} assume !(1 == ~E_M~0); {177369#false} is VALID [2022-02-21 04:24:02,676 INFO L290 TraceCheckUtils]: 147: Hoare triple {177369#false} assume !(1 == ~E_1~0); {177369#false} is VALID [2022-02-21 04:24:02,676 INFO L290 TraceCheckUtils]: 148: Hoare triple {177369#false} assume !(1 == ~E_2~0); {177369#false} is VALID [2022-02-21 04:24:02,676 INFO L290 TraceCheckUtils]: 149: Hoare triple {177369#false} assume !(1 == ~E_3~0); {177369#false} is VALID [2022-02-21 04:24:02,676 INFO L290 TraceCheckUtils]: 150: Hoare triple {177369#false} assume !(1 == ~E_4~0); {177369#false} is VALID [2022-02-21 04:24:02,676 INFO L290 TraceCheckUtils]: 151: Hoare triple {177369#false} assume 1 == ~E_5~0;~E_5~0 := 2; {177369#false} is VALID [2022-02-21 04:24:02,676 INFO L290 TraceCheckUtils]: 152: Hoare triple {177369#false} assume !(1 == ~E_6~0); {177369#false} is VALID [2022-02-21 04:24:02,676 INFO L290 TraceCheckUtils]: 153: Hoare triple {177369#false} assume !(1 == ~E_7~0); {177369#false} is VALID [2022-02-21 04:24:02,676 INFO L290 TraceCheckUtils]: 154: Hoare triple {177369#false} assume !(1 == ~E_8~0); {177369#false} is VALID [2022-02-21 04:24:02,677 INFO L290 TraceCheckUtils]: 155: Hoare triple {177369#false} assume !(1 == ~E_9~0); {177369#false} is VALID [2022-02-21 04:24:02,677 INFO L290 TraceCheckUtils]: 156: Hoare triple {177369#false} assume !(1 == ~E_10~0); {177369#false} is VALID [2022-02-21 04:24:02,677 INFO L290 TraceCheckUtils]: 157: Hoare triple {177369#false} assume !(1 == ~E_11~0); {177369#false} is VALID [2022-02-21 04:24:02,677 INFO L290 TraceCheckUtils]: 158: Hoare triple {177369#false} assume !(1 == ~E_12~0); {177369#false} is VALID [2022-02-21 04:24:02,677 INFO L290 TraceCheckUtils]: 159: Hoare triple {177369#false} assume 1 == ~E_13~0;~E_13~0 := 2; {177369#false} is VALID [2022-02-21 04:24:02,677 INFO L290 TraceCheckUtils]: 160: Hoare triple {177369#false} assume { :end_inline_reset_delta_events } true; {177369#false} is VALID [2022-02-21 04:24:02,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:02,677 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:02,678 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [383311753] [2022-02-21 04:24:02,678 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [383311753] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:02,678 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:02,678 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:02,678 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686888560] [2022-02-21 04:24:02,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:02,678 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:02,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,679 INFO L85 PathProgramCache]: Analyzing trace with hash -1113247450, now seen corresponding path program 1 times [2022-02-21 04:24:02,679 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,679 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209024849] [2022-02-21 04:24:02,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:02,718 INFO L290 TraceCheckUtils]: 0: Hoare triple {177372#true} assume !false; {177372#true} is VALID [2022-02-21 04:24:02,718 INFO L290 TraceCheckUtils]: 1: Hoare triple {177372#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {177372#true} is VALID [2022-02-21 04:24:02,718 INFO L290 TraceCheckUtils]: 2: Hoare triple {177372#true} assume !false; {177372#true} is VALID [2022-02-21 04:24:02,718 INFO L290 TraceCheckUtils]: 3: Hoare triple {177372#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {177372#true} is VALID [2022-02-21 04:24:02,719 INFO L290 TraceCheckUtils]: 4: Hoare triple {177372#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {177374#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~14#1|)} is VALID [2022-02-21 04:24:02,719 INFO L290 TraceCheckUtils]: 5: Hoare triple {177374#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~14#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {177375#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:02,720 INFO L290 TraceCheckUtils]: 6: Hoare triple {177375#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {177376#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:02,720 INFO L290 TraceCheckUtils]: 7: Hoare triple {177376#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {177373#false} is VALID [2022-02-21 04:24:02,720 INFO L290 TraceCheckUtils]: 8: Hoare triple {177373#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {177373#false} is VALID [2022-02-21 04:24:02,720 INFO L290 TraceCheckUtils]: 9: Hoare triple {177373#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {177373#false} is VALID [2022-02-21 04:24:02,720 INFO L290 TraceCheckUtils]: 10: Hoare triple {177373#false} assume !(0 == ~M_E~0); {177373#false} is VALID [2022-02-21 04:24:02,720 INFO L290 TraceCheckUtils]: 11: Hoare triple {177373#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,721 INFO L290 TraceCheckUtils]: 12: Hoare triple {177373#false} assume !(0 == ~T2_E~0); {177373#false} is VALID [2022-02-21 04:24:02,721 INFO L290 TraceCheckUtils]: 13: Hoare triple {177373#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,721 INFO L290 TraceCheckUtils]: 14: Hoare triple {177373#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,721 INFO L290 TraceCheckUtils]: 15: Hoare triple {177373#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,721 INFO L290 TraceCheckUtils]: 16: Hoare triple {177373#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,721 INFO L290 TraceCheckUtils]: 17: Hoare triple {177373#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,721 INFO L290 TraceCheckUtils]: 18: Hoare triple {177373#false} assume !(0 == ~T8_E~0); {177373#false} is VALID [2022-02-21 04:24:02,721 INFO L290 TraceCheckUtils]: 19: Hoare triple {177373#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,721 INFO L290 TraceCheckUtils]: 20: Hoare triple {177373#false} assume !(0 == ~T10_E~0); {177373#false} is VALID [2022-02-21 04:24:02,722 INFO L290 TraceCheckUtils]: 21: Hoare triple {177373#false} assume 0 == ~T11_E~0;~T11_E~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,722 INFO L290 TraceCheckUtils]: 22: Hoare triple {177373#false} assume 0 == ~T12_E~0;~T12_E~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,722 INFO L290 TraceCheckUtils]: 23: Hoare triple {177373#false} assume 0 == ~T13_E~0;~T13_E~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,722 INFO L290 TraceCheckUtils]: 24: Hoare triple {177373#false} assume 0 == ~E_M~0;~E_M~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,722 INFO L290 TraceCheckUtils]: 25: Hoare triple {177373#false} assume 0 == ~E_1~0;~E_1~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,722 INFO L290 TraceCheckUtils]: 26: Hoare triple {177373#false} assume !(0 == ~E_2~0); {177373#false} is VALID [2022-02-21 04:24:02,722 INFO L290 TraceCheckUtils]: 27: Hoare triple {177373#false} assume 0 == ~E_3~0;~E_3~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,722 INFO L290 TraceCheckUtils]: 28: Hoare triple {177373#false} assume !(0 == ~E_4~0); {177373#false} is VALID [2022-02-21 04:24:02,722 INFO L290 TraceCheckUtils]: 29: Hoare triple {177373#false} assume 0 == ~E_5~0;~E_5~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,722 INFO L290 TraceCheckUtils]: 30: Hoare triple {177373#false} assume 0 == ~E_6~0;~E_6~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,723 INFO L290 TraceCheckUtils]: 31: Hoare triple {177373#false} assume 0 == ~E_7~0;~E_7~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,723 INFO L290 TraceCheckUtils]: 32: Hoare triple {177373#false} assume 0 == ~E_8~0;~E_8~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,723 INFO L290 TraceCheckUtils]: 33: Hoare triple {177373#false} assume 0 == ~E_9~0;~E_9~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,723 INFO L290 TraceCheckUtils]: 34: Hoare triple {177373#false} assume !(0 == ~E_10~0); {177373#false} is VALID [2022-02-21 04:24:02,723 INFO L290 TraceCheckUtils]: 35: Hoare triple {177373#false} assume 0 == ~E_11~0;~E_11~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,723 INFO L290 TraceCheckUtils]: 36: Hoare triple {177373#false} assume !(0 == ~E_12~0); {177373#false} is VALID [2022-02-21 04:24:02,723 INFO L290 TraceCheckUtils]: 37: Hoare triple {177373#false} assume 0 == ~E_13~0;~E_13~0 := 1; {177373#false} is VALID [2022-02-21 04:24:02,723 INFO L290 TraceCheckUtils]: 38: Hoare triple {177373#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {177373#false} is VALID [2022-02-21 04:24:02,723 INFO L290 TraceCheckUtils]: 39: Hoare triple {177373#false} assume 1 == ~m_pc~0; {177373#false} is VALID [2022-02-21 04:24:02,724 INFO L290 TraceCheckUtils]: 40: Hoare triple {177373#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {177373#false} is VALID [2022-02-21 04:24:02,724 INFO L290 TraceCheckUtils]: 41: Hoare triple {177373#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {177373#false} is VALID [2022-02-21 04:24:02,724 INFO L290 TraceCheckUtils]: 42: Hoare triple {177373#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {177373#false} is VALID [2022-02-21 04:24:02,724 INFO L290 TraceCheckUtils]: 43: Hoare triple {177373#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,724 INFO L290 TraceCheckUtils]: 44: Hoare triple {177373#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {177373#false} is VALID [2022-02-21 04:24:02,724 INFO L290 TraceCheckUtils]: 45: Hoare triple {177373#false} assume 1 == ~t1_pc~0; {177373#false} is VALID [2022-02-21 04:24:02,724 INFO L290 TraceCheckUtils]: 46: Hoare triple {177373#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {177373#false} is VALID [2022-02-21 04:24:02,724 INFO L290 TraceCheckUtils]: 47: Hoare triple {177373#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {177373#false} is VALID [2022-02-21 04:24:02,724 INFO L290 TraceCheckUtils]: 48: Hoare triple {177373#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {177373#false} is VALID [2022-02-21 04:24:02,724 INFO L290 TraceCheckUtils]: 49: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 50: Hoare triple {177373#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 51: Hoare triple {177373#false} assume !(1 == ~t2_pc~0); {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 52: Hoare triple {177373#false} is_transmit2_triggered_~__retres1~2#1 := 0; {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 53: Hoare triple {177373#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 54: Hoare triple {177373#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 55: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 56: Hoare triple {177373#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 57: Hoare triple {177373#false} assume 1 == ~t3_pc~0; {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 58: Hoare triple {177373#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 59: Hoare triple {177373#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {177373#false} is VALID [2022-02-21 04:24:02,725 INFO L290 TraceCheckUtils]: 60: Hoare triple {177373#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {177373#false} is VALID [2022-02-21 04:24:02,726 INFO L290 TraceCheckUtils]: 61: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,726 INFO L290 TraceCheckUtils]: 62: Hoare triple {177373#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {177373#false} is VALID [2022-02-21 04:24:02,726 INFO L290 TraceCheckUtils]: 63: Hoare triple {177373#false} assume 1 == ~t4_pc~0; {177373#false} is VALID [2022-02-21 04:24:02,726 INFO L290 TraceCheckUtils]: 64: Hoare triple {177373#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {177373#false} is VALID [2022-02-21 04:24:02,726 INFO L290 TraceCheckUtils]: 65: Hoare triple {177373#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {177373#false} is VALID [2022-02-21 04:24:02,726 INFO L290 TraceCheckUtils]: 66: Hoare triple {177373#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {177373#false} is VALID [2022-02-21 04:24:02,726 INFO L290 TraceCheckUtils]: 67: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,726 INFO L290 TraceCheckUtils]: 68: Hoare triple {177373#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {177373#false} is VALID [2022-02-21 04:24:02,726 INFO L290 TraceCheckUtils]: 69: Hoare triple {177373#false} assume 1 == ~t5_pc~0; {177373#false} is VALID [2022-02-21 04:24:02,727 INFO L290 TraceCheckUtils]: 70: Hoare triple {177373#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {177373#false} is VALID [2022-02-21 04:24:02,727 INFO L290 TraceCheckUtils]: 71: Hoare triple {177373#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {177373#false} is VALID [2022-02-21 04:24:02,727 INFO L290 TraceCheckUtils]: 72: Hoare triple {177373#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {177373#false} is VALID [2022-02-21 04:24:02,727 INFO L290 TraceCheckUtils]: 73: Hoare triple {177373#false} assume !(0 != activate_threads_~tmp___4~0#1); {177373#false} is VALID [2022-02-21 04:24:02,727 INFO L290 TraceCheckUtils]: 74: Hoare triple {177373#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {177373#false} is VALID [2022-02-21 04:24:02,727 INFO L290 TraceCheckUtils]: 75: Hoare triple {177373#false} assume 1 == ~t6_pc~0; {177373#false} is VALID [2022-02-21 04:24:02,727 INFO L290 TraceCheckUtils]: 76: Hoare triple {177373#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {177373#false} is VALID [2022-02-21 04:24:02,727 INFO L290 TraceCheckUtils]: 77: Hoare triple {177373#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {177373#false} is VALID [2022-02-21 04:24:02,727 INFO L290 TraceCheckUtils]: 78: Hoare triple {177373#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {177373#false} is VALID [2022-02-21 04:24:02,727 INFO L290 TraceCheckUtils]: 79: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,728 INFO L290 TraceCheckUtils]: 80: Hoare triple {177373#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {177373#false} is VALID [2022-02-21 04:24:02,728 INFO L290 TraceCheckUtils]: 81: Hoare triple {177373#false} assume !(1 == ~t7_pc~0); {177373#false} is VALID [2022-02-21 04:24:02,728 INFO L290 TraceCheckUtils]: 82: Hoare triple {177373#false} is_transmit7_triggered_~__retres1~7#1 := 0; {177373#false} is VALID [2022-02-21 04:24:02,728 INFO L290 TraceCheckUtils]: 83: Hoare triple {177373#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {177373#false} is VALID [2022-02-21 04:24:02,728 INFO L290 TraceCheckUtils]: 84: Hoare triple {177373#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {177373#false} is VALID [2022-02-21 04:24:02,728 INFO L290 TraceCheckUtils]: 85: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,728 INFO L290 TraceCheckUtils]: 86: Hoare triple {177373#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {177373#false} is VALID [2022-02-21 04:24:02,728 INFO L290 TraceCheckUtils]: 87: Hoare triple {177373#false} assume !(1 == ~t8_pc~0); {177373#false} is VALID [2022-02-21 04:24:02,728 INFO L290 TraceCheckUtils]: 88: Hoare triple {177373#false} is_transmit8_triggered_~__retres1~8#1 := 0; {177373#false} is VALID [2022-02-21 04:24:02,728 INFO L290 TraceCheckUtils]: 89: Hoare triple {177373#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 90: Hoare triple {177373#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 91: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 92: Hoare triple {177373#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 93: Hoare triple {177373#false} assume !(1 == ~t9_pc~0); {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 94: Hoare triple {177373#false} is_transmit9_triggered_~__retres1~9#1 := 0; {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 95: Hoare triple {177373#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 96: Hoare triple {177373#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 97: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 98: Hoare triple {177373#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 99: Hoare triple {177373#false} assume !(1 == ~t10_pc~0); {177373#false} is VALID [2022-02-21 04:24:02,729 INFO L290 TraceCheckUtils]: 100: Hoare triple {177373#false} is_transmit10_triggered_~__retres1~10#1 := 0; {177373#false} is VALID [2022-02-21 04:24:02,730 INFO L290 TraceCheckUtils]: 101: Hoare triple {177373#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {177373#false} is VALID [2022-02-21 04:24:02,730 INFO L290 TraceCheckUtils]: 102: Hoare triple {177373#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {177373#false} is VALID [2022-02-21 04:24:02,730 INFO L290 TraceCheckUtils]: 103: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,730 INFO L290 TraceCheckUtils]: 104: Hoare triple {177373#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {177373#false} is VALID [2022-02-21 04:24:02,730 INFO L290 TraceCheckUtils]: 105: Hoare triple {177373#false} assume 1 == ~t11_pc~0; {177373#false} is VALID [2022-02-21 04:24:02,730 INFO L290 TraceCheckUtils]: 106: Hoare triple {177373#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {177373#false} is VALID [2022-02-21 04:24:02,730 INFO L290 TraceCheckUtils]: 107: Hoare triple {177373#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {177373#false} is VALID [2022-02-21 04:24:02,730 INFO L290 TraceCheckUtils]: 108: Hoare triple {177373#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {177373#false} is VALID [2022-02-21 04:24:02,730 INFO L290 TraceCheckUtils]: 109: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,730 INFO L290 TraceCheckUtils]: 110: Hoare triple {177373#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {177373#false} is VALID [2022-02-21 04:24:02,731 INFO L290 TraceCheckUtils]: 111: Hoare triple {177373#false} assume !(1 == ~t12_pc~0); {177373#false} is VALID [2022-02-21 04:24:02,731 INFO L290 TraceCheckUtils]: 112: Hoare triple {177373#false} is_transmit12_triggered_~__retres1~12#1 := 0; {177373#false} is VALID [2022-02-21 04:24:02,731 INFO L290 TraceCheckUtils]: 113: Hoare triple {177373#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {177373#false} is VALID [2022-02-21 04:24:02,731 INFO L290 TraceCheckUtils]: 114: Hoare triple {177373#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {177373#false} is VALID [2022-02-21 04:24:02,731 INFO L290 TraceCheckUtils]: 115: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,731 INFO L290 TraceCheckUtils]: 116: Hoare triple {177373#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {177373#false} is VALID [2022-02-21 04:24:02,731 INFO L290 TraceCheckUtils]: 117: Hoare triple {177373#false} assume 1 == ~t13_pc~0; {177373#false} is VALID [2022-02-21 04:24:02,731 INFO L290 TraceCheckUtils]: 118: Hoare triple {177373#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {177373#false} is VALID [2022-02-21 04:24:02,731 INFO L290 TraceCheckUtils]: 119: Hoare triple {177373#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {177373#false} is VALID [2022-02-21 04:24:02,731 INFO L290 TraceCheckUtils]: 120: Hoare triple {177373#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {177373#false} is VALID [2022-02-21 04:24:02,732 INFO L290 TraceCheckUtils]: 121: Hoare triple {177373#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {177373#false} is VALID [2022-02-21 04:24:02,732 INFO L290 TraceCheckUtils]: 122: Hoare triple {177373#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {177373#false} is VALID [2022-02-21 04:24:02,732 INFO L290 TraceCheckUtils]: 123: Hoare triple {177373#false} assume !(1 == ~M_E~0); {177373#false} is VALID [2022-02-21 04:24:02,732 INFO L290 TraceCheckUtils]: 124: Hoare triple {177373#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,732 INFO L290 TraceCheckUtils]: 125: Hoare triple {177373#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,732 INFO L290 TraceCheckUtils]: 126: Hoare triple {177373#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,732 INFO L290 TraceCheckUtils]: 127: Hoare triple {177373#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,732 INFO L290 TraceCheckUtils]: 128: Hoare triple {177373#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,732 INFO L290 TraceCheckUtils]: 129: Hoare triple {177373#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,732 INFO L290 TraceCheckUtils]: 130: Hoare triple {177373#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,733 INFO L290 TraceCheckUtils]: 131: Hoare triple {177373#false} assume !(1 == ~T8_E~0); {177373#false} is VALID [2022-02-21 04:24:02,733 INFO L290 TraceCheckUtils]: 132: Hoare triple {177373#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,733 INFO L290 TraceCheckUtils]: 133: Hoare triple {177373#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,733 INFO L290 TraceCheckUtils]: 134: Hoare triple {177373#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,733 INFO L290 TraceCheckUtils]: 135: Hoare triple {177373#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,733 INFO L290 TraceCheckUtils]: 136: Hoare triple {177373#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,733 INFO L290 TraceCheckUtils]: 137: Hoare triple {177373#false} assume 1 == ~E_M~0;~E_M~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,733 INFO L290 TraceCheckUtils]: 138: Hoare triple {177373#false} assume 1 == ~E_1~0;~E_1~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,733 INFO L290 TraceCheckUtils]: 139: Hoare triple {177373#false} assume !(1 == ~E_2~0); {177373#false} is VALID [2022-02-21 04:24:02,733 INFO L290 TraceCheckUtils]: 140: Hoare triple {177373#false} assume 1 == ~E_3~0;~E_3~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,734 INFO L290 TraceCheckUtils]: 141: Hoare triple {177373#false} assume 1 == ~E_4~0;~E_4~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,734 INFO L290 TraceCheckUtils]: 142: Hoare triple {177373#false} assume 1 == ~E_5~0;~E_5~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,734 INFO L290 TraceCheckUtils]: 143: Hoare triple {177373#false} assume 1 == ~E_6~0;~E_6~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,734 INFO L290 TraceCheckUtils]: 144: Hoare triple {177373#false} assume 1 == ~E_7~0;~E_7~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,734 INFO L290 TraceCheckUtils]: 145: Hoare triple {177373#false} assume 1 == ~E_8~0;~E_8~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,734 INFO L290 TraceCheckUtils]: 146: Hoare triple {177373#false} assume 1 == ~E_9~0;~E_9~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,734 INFO L290 TraceCheckUtils]: 147: Hoare triple {177373#false} assume !(1 == ~E_10~0); {177373#false} is VALID [2022-02-21 04:24:02,734 INFO L290 TraceCheckUtils]: 148: Hoare triple {177373#false} assume 1 == ~E_11~0;~E_11~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,734 INFO L290 TraceCheckUtils]: 149: Hoare triple {177373#false} assume 1 == ~E_12~0;~E_12~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,734 INFO L290 TraceCheckUtils]: 150: Hoare triple {177373#false} assume 1 == ~E_13~0;~E_13~0 := 2; {177373#false} is VALID [2022-02-21 04:24:02,735 INFO L290 TraceCheckUtils]: 151: Hoare triple {177373#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {177373#false} is VALID [2022-02-21 04:24:02,735 INFO L290 TraceCheckUtils]: 152: Hoare triple {177373#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {177373#false} is VALID [2022-02-21 04:24:02,735 INFO L290 TraceCheckUtils]: 153: Hoare triple {177373#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {177373#false} is VALID [2022-02-21 04:24:02,735 INFO L290 TraceCheckUtils]: 154: Hoare triple {177373#false} start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {177373#false} is VALID [2022-02-21 04:24:02,735 INFO L290 TraceCheckUtils]: 155: Hoare triple {177373#false} assume !(0 == start_simulation_~tmp~3#1); {177373#false} is VALID [2022-02-21 04:24:02,735 INFO L290 TraceCheckUtils]: 156: Hoare triple {177373#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {177373#false} is VALID [2022-02-21 04:24:02,735 INFO L290 TraceCheckUtils]: 157: Hoare triple {177373#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {177373#false} is VALID [2022-02-21 04:24:02,735 INFO L290 TraceCheckUtils]: 158: Hoare triple {177373#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {177373#false} is VALID [2022-02-21 04:24:02,735 INFO L290 TraceCheckUtils]: 159: Hoare triple {177373#false} stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; {177373#false} is VALID [2022-02-21 04:24:02,735 INFO L290 TraceCheckUtils]: 160: Hoare triple {177373#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {177373#false} is VALID [2022-02-21 04:24:02,736 INFO L290 TraceCheckUtils]: 161: Hoare triple {177373#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {177373#false} is VALID [2022-02-21 04:24:02,736 INFO L290 TraceCheckUtils]: 162: Hoare triple {177373#false} start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {177373#false} is VALID [2022-02-21 04:24:02,736 INFO L290 TraceCheckUtils]: 163: Hoare triple {177373#false} assume !(0 != start_simulation_~tmp___0~1#1); {177373#false} is VALID [2022-02-21 04:24:02,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:02,736 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:02,736 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209024849] [2022-02-21 04:24:02,736 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209024849] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:02,737 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:02,737 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:02,737 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [807792076] [2022-02-21 04:24:02,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:02,737 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:02,737 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:02,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:02,738 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:02,738 INFO L87 Difference]: Start difference. First operand 3761 states and 5484 transitions. cyclomatic complexity: 1724 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:10,498 INFO L93 Difference]: Finished difference Result 10616 states and 15321 transitions. [2022-02-21 04:24:10,498 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:10,498 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,601 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:10,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10616 states and 15321 transitions. [2022-02-21 04:24:13,647 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10233