./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.14.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.14.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:23:05,760 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:23:05,761 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:23:05,813 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:23:05,814 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:23:05,816 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:23:05,817 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:23:05,821 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:23:05,823 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:23:05,826 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:23:05,827 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:23:05,828 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:23:05,828 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:23:05,830 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:23:05,831 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:23:05,833 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:23:05,834 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:23:05,834 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:23:05,836 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:23:05,839 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:23:05,840 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:23:05,841 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:23:05,842 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:23:05,843 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:23:05,848 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:23:05,848 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:23:05,849 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:23:05,849 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:23:05,850 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:23:05,850 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:23:05,850 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:23:05,851 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:23:05,851 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:23:05,852 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:23:05,852 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:23:05,853 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:23:05,853 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:23:05,853 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:23:05,853 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:23:05,854 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:23:05,854 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:23:05,856 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:23:05,884 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:23:05,885 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:23:05,886 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:23:05,886 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:23:05,887 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:23:05,887 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:23:05,887 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:23:05,888 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:23:05,888 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:23:05,888 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:23:05,888 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:23:05,889 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:23:05,889 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:23:05,889 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:23:05,889 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:23:05,889 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:23:05,889 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:23:05,890 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:23:05,890 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:23:05,890 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:23:05,890 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:23:05,890 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:23:05,890 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:23:05,891 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:23:05,891 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:23:05,891 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:23:05,891 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:23:05,891 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:23:05,891 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:23:05,892 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:23:05,892 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:23:05,893 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:23:05,893 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f [2022-02-21 04:23:06,106 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:23:06,124 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:23:06,126 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:23:06,126 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:23:06,127 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:23:06,128 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.14.cil.c [2022-02-21 04:23:06,191 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/88feea6b9/310d8ac9188247448d5f6f0f5056e3c2/FLAGbbbace316 [2022-02-21 04:23:06,579 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:23:06,580 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c [2022-02-21 04:23:06,592 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/88feea6b9/310d8ac9188247448d5f6f0f5056e3c2/FLAGbbbace316 [2022-02-21 04:23:06,603 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/88feea6b9/310d8ac9188247448d5f6f0f5056e3c2 [2022-02-21 04:23:06,606 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:23:06,607 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:23:06,610 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:06,610 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:23:06,612 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:23:06,613 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,614 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5d44e277 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:06, skipping insertion in model container [2022-02-21 04:23:06,614 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:06" (1/1) ... [2022-02-21 04:23:06,618 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:23:06,661 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:23:06,818 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c[669,682] [2022-02-21 04:23:06,950 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:06,958 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:23:06,975 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c[669,682] [2022-02-21 04:23:07,041 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:07,058 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:23:07,061 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07 WrapperNode [2022-02-21 04:23:07,061 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:07,063 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:07,063 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:23:07,063 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:23:07,068 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (1/1) ... [2022-02-21 04:23:07,092 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (1/1) ... [2022-02-21 04:23:07,210 INFO L137 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4144 [2022-02-21 04:23:07,210 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:07,210 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:23:07,211 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:23:07,211 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:23:07,219 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (1/1) ... [2022-02-21 04:23:07,219 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (1/1) ... [2022-02-21 04:23:07,228 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (1/1) ... [2022-02-21 04:23:07,229 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (1/1) ... [2022-02-21 04:23:07,269 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (1/1) ... [2022-02-21 04:23:07,292 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (1/1) ... [2022-02-21 04:23:07,298 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (1/1) ... [2022-02-21 04:23:07,307 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:23:07,309 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:23:07,309 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:23:07,309 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:23:07,311 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (1/1) ... [2022-02-21 04:23:07,315 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:23:07,323 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:23:07,333 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:23:07,352 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:23:07,375 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:23:07,376 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:23:07,376 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:23:07,376 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:23:07,463 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:23:07,464 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:23:09,104 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:23:09,129 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:23:09,130 INFO L299 CfgBuilder]: Removed 15 assume(true) statements. [2022-02-21 04:23:09,133 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:09 BoogieIcfgContainer [2022-02-21 04:23:09,133 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:23:09,134 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:23:09,134 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:23:09,136 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:23:09,137 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:09,137 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:23:06" (1/3) ... [2022-02-21 04:23:09,138 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@11ba4239 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:09, skipping insertion in model container [2022-02-21 04:23:09,138 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:09,138 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:07" (2/3) ... [2022-02-21 04:23:09,138 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@11ba4239 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:09, skipping insertion in model container [2022-02-21 04:23:09,138 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:09,138 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:09" (3/3) ... [2022-02-21 04:23:09,139 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.14.cil.c [2022-02-21 04:23:09,180 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:23:09,180 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:23:09,180 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:23:09,180 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:23:09,180 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:23:09,180 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:23:09,181 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:23:09,181 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:23:09,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1629 [2022-02-21 04:23:09,473 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:09,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:09,482 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,482 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,482 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:23:09,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1629 [2022-02-21 04:23:09,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:09,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:09,659 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,659 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,665 INFO L791 eck$LassoCheckResult]: Stem: 425#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1703#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 148#L1773true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174#L841true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1363#L848true assume !(1 == ~m_i~0);~m_st~0 := 2; 1469#L848-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 431#L853-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 308#L858-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3#L863-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 749#L868-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 843#L873-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1599#L878-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1565#L883-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1650#L888-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 384#L893-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 773#L898-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1774#L903-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 696#L908-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 408#L1201true assume !(0 == ~M_E~0); 1177#L1201-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1596#L1206-1true assume !(0 == ~T2_E~0); 1156#L1211-1true assume !(0 == ~T3_E~0); 1303#L1216-1true assume !(0 == ~T4_E~0); 298#L1221-1true assume !(0 == ~T5_E~0); 1244#L1226-1true assume !(0 == ~T6_E~0); 105#L1231-1true assume !(0 == ~T7_E~0); 1388#L1236-1true assume !(0 == ~T8_E~0); 1225#L1241-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 321#L1246-1true assume !(0 == ~T10_E~0); 406#L1251-1true assume !(0 == ~T11_E~0); 876#L1256-1true assume !(0 == ~T12_E~0); 9#L1261-1true assume !(0 == ~E_M~0); 1568#L1266-1true assume !(0 == ~E_1~0); 1508#L1271-1true assume !(0 == ~E_2~0); 831#L1276-1true assume !(0 == ~E_3~0); 1503#L1281-1true assume 0 == ~E_4~0;~E_4~0 := 1; 786#L1286-1true assume !(0 == ~E_5~0); 238#L1291-1true assume !(0 == ~E_6~0); 1594#L1296-1true assume !(0 == ~E_7~0); 610#L1301-1true assume !(0 == ~E_8~0); 1099#L1306-1true assume !(0 == ~E_9~0); 1072#L1311-1true assume !(0 == ~E_10~0); 213#L1316-1true assume !(0 == ~E_11~0); 1457#L1321-1true assume 0 == ~E_12~0;~E_12~0 := 1; 623#L1326-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 739#L593true assume 1 == ~m_pc~0; 863#L594true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1468#L604true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1724#L605true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 794#L1492true assume !(0 != activate_threads_~tmp~1#1); 1227#L1492-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1125#L612true assume !(1 == ~t1_pc~0); 1658#L612-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1534#L623true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364#L624true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154#L1500true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 437#L1500-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 390#L631true assume 1 == ~t2_pc~0; 351#L632true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47#L642true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 917#L643true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 525#L1508true assume !(0 != activate_threads_~tmp___1~0#1); 1307#L1508-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192#L650true assume !(1 == ~t3_pc~0); 960#L650-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1217#L661true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152#L662true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26#L1516true assume !(0 != activate_threads_~tmp___2~0#1); 970#L1516-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 767#L669true assume 1 == ~t4_pc~0; 1269#L670true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1782#L680true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 383#L681true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122#L1524true assume !(0 != activate_threads_~tmp___3~0#1); 244#L1524-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 984#L688true assume !(1 == ~t5_pc~0); 130#L688-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1467#L699true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 719#L700true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 664#L1532true assume !(0 != activate_threads_~tmp___4~0#1); 779#L1532-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1293#L707true assume 1 == ~t6_pc~0; 1339#L708true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 504#L718true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1289#L719true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1369#L1540true assume !(0 != activate_threads_~tmp___5~0#1); 726#L1540-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 407#L726true assume 1 == ~t7_pc~0; 343#L727true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 911#L737true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1578#L738true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1304#L1548true assume !(0 != activate_threads_~tmp___6~0#1); 63#L1548-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 295#L745true assume !(1 == ~t8_pc~0); 1109#L745-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1191#L756true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 948#L757true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 553#L1556true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1025#L1556-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1787#L764true assume 1 == ~t9_pc~0; 404#L765true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 797#L775true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1557#L776true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1434#L1564true assume !(0 != activate_threads_~tmp___8~0#1); 72#L1564-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1390#L783true assume !(1 == ~t10_pc~0); 99#L783-2true is_transmit10_triggered_~__retres1~10#1 := 0; 194#L794true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 119#L795true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 377#L1572true assume !(0 != activate_threads_~tmp___9~0#1); 1168#L1572-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1273#L802true assume 1 == ~t11_pc~0; 1142#L803true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45#L813true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 751#L814true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 299#L1580true assume !(0 != activate_threads_~tmp___10~0#1); 363#L1580-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 534#L821true assume !(1 == ~t12_pc~0); 602#L821-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1329#L832true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48#L833true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1243#L1588true assume !(0 != activate_threads_~tmp___11~0#1); 1250#L1588-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 804#L1339true assume !(1 == ~M_E~0); 1455#L1339-2true assume !(1 == ~T1_E~0); 1311#L1344-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1722#L1349-1true assume !(1 == ~T3_E~0); 619#L1354-1true assume !(1 == ~T4_E~0); 992#L1359-1true assume !(1 == ~T5_E~0); 1541#L1364-1true assume !(1 == ~T6_E~0); 268#L1369-1true assume !(1 == ~T7_E~0); 963#L1374-1true assume !(1 == ~T8_E~0); 621#L1379-1true assume !(1 == ~T9_E~0); 691#L1384-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1760#L1389-1true assume !(1 == ~T11_E~0); 1232#L1394-1true assume !(1 == ~T12_E~0); 1628#L1399-1true assume !(1 == ~E_M~0); 1437#L1404-1true assume !(1 == ~E_1~0); 323#L1409-1true assume !(1 == ~E_2~0); 1406#L1414-1true assume !(1 == ~E_3~0); 864#L1419-1true assume !(1 == ~E_4~0); 126#L1424-1true assume 1 == ~E_5~0;~E_5~0 := 2; 627#L1429-1true assume !(1 == ~E_6~0); 1264#L1434-1true assume !(1 == ~E_7~0); 1602#L1439-1true assume !(1 == ~E_8~0); 146#L1444-1true assume !(1 == ~E_9~0); 816#L1449-1true assume !(1 == ~E_10~0); 354#L1454-1true assume !(1 == ~E_11~0); 1302#L1459-1true assume !(1 == ~E_12~0); 724#L1464-1true assume { :end_inline_reset_delta_events } true; 490#L1810-2true [2022-02-21 04:23:09,667 INFO L793 eck$LassoCheckResult]: Loop: 490#L1810-2true assume !false; 1335#L1811true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1770#L1176true assume false; 158#L1191true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1414#L841-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1054#L1201-3true assume 0 == ~M_E~0;~M_E~0 := 1; 821#L1201-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1598#L1206-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 722#L1211-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 190#L1216-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 467#L1221-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1023#L1226-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 230#L1231-3true assume !(0 == ~T7_E~0); 370#L1236-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1772#L1241-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1334#L1246-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1145#L1251-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 807#L1256-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 199#L1261-3true assume 0 == ~E_M~0;~E_M~0 := 1; 518#L1266-3true assume 0 == ~E_1~0;~E_1~0 := 1; 226#L1271-3true assume !(0 == ~E_2~0); 488#L1276-3true assume 0 == ~E_3~0;~E_3~0 := 1; 451#L1281-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1201#L1286-3true assume 0 == ~E_5~0;~E_5~0 := 1; 861#L1291-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1610#L1296-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1535#L1301-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1425#L1306-3true assume 0 == ~E_9~0;~E_9~0 := 1; 530#L1311-3true assume !(0 == ~E_10~0); 159#L1316-3true assume 0 == ~E_11~0;~E_11~0 := 1; 200#L1321-3true assume 0 == ~E_12~0;~E_12~0 := 1; 601#L1326-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1210#L593-42true assume 1 == ~m_pc~0; 949#L594-14true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1757#L604-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1501#L605-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1720#L1492-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 108#L1492-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 681#L612-42true assume 1 == ~t1_pc~0; 1728#L613-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1582#L623-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1291#L624-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 153#L1500-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1754#L1500-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 577#L631-42true assume 1 == ~t2_pc~0; 41#L632-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 568#L642-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1748#L643-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486#L1508-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1635#L1508-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 240#L650-42true assume !(1 == ~t3_pc~0); 135#L650-44true is_transmit3_triggered_~__retres1~3#1 := 0; 1716#L661-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1348#L662-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350#L1516-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1375#L1516-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1268#L669-42true assume 1 == ~t4_pc~0; 537#L670-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 998#L680-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1496#L681-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 871#L1524-42true assume !(0 != activate_threads_~tmp___3~0#1); 778#L1524-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 860#L688-42true assume !(1 == ~t5_pc~0); 1101#L688-44true is_transmit5_triggered_~__retres1~5#1 := 0; 1351#L699-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86#L700-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121#L1532-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1431#L1532-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36#L707-42true assume !(1 == ~t6_pc~0); 1679#L707-44true is_transmit6_triggered_~__retres1~6#1 := 0; 1695#L718-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1004#L719-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1292#L1540-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 753#L1540-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1033#L726-42true assume 1 == ~t7_pc~0; 1330#L727-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1070#L737-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1600#L738-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 532#L1548-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 605#L1548-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1186#L745-42true assume 1 == ~t8_pc~0; 632#L746-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1429#L756-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 206#L757-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30#L1556-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 422#L1556-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 515#L764-42true assume 1 == ~t9_pc~0; 1659#L765-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 792#L775-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 996#L776-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 166#L1564-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 195#L1564-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 243#L783-42true assume 1 == ~t10_pc~0; 11#L784-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 315#L794-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 392#L795-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1537#L1572-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1517#L1572-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 959#L802-42true assume !(1 == ~t11_pc~0); 1075#L802-44true is_transmit11_triggered_~__retres1~11#1 := 0; 75#L813-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1188#L814-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52#L1580-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1550#L1580-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 802#L821-42true assume !(1 == ~t12_pc~0); 337#L821-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1007#L832-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10#L833-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1159#L1588-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 560#L1588-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 552#L1339-3true assume !(1 == ~M_E~0); 666#L1339-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 808#L1344-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 766#L1349-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 342#L1354-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 775#L1359-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1607#L1364-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1499#L1369-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1263#L1374-3true assume !(1 == ~T8_E~0); 241#L1379-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1149#L1384-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 341#L1389-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 479#L1394-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1707#L1399-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1279#L1404-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1224#L1409-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1333#L1414-3true assume !(1 == ~E_3~0); 1356#L1419-3true assume 1 == ~E_4~0;~E_4~0 := 2; 962#L1424-3true assume 1 == ~E_5~0;~E_5~0 := 2; 176#L1429-3true assume 1 == ~E_6~0;~E_6~0 := 2; 774#L1434-3true assume 1 == ~E_7~0;~E_7~0 := 2; 925#L1439-3true assume 1 == ~E_8~0;~E_8~0 := 2; 140#L1444-3true assume 1 == ~E_9~0;~E_9~0 := 2; 204#L1449-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1424#L1454-3true assume !(1 == ~E_11~0); 770#L1459-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1769#L1464-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 505#L921-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1727#L988-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 232#L989-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1456#L1829true assume !(0 == start_simulation_~tmp~3#1); 88#L1829-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1040#L921-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 556#L988-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 931#L989-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 787#L1784true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1543#L1791true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 493#L1792true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 219#L1842true assume !(0 != start_simulation_~tmp___0~1#1); 490#L1810-2true [2022-02-21 04:23:09,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,672 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2022-02-21 04:23:09,678 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,679 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141485424] [2022-02-21 04:23:09,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,840 INFO L290 TraceCheckUtils]: 0: Hoare triple {1800#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {1800#true} is VALID [2022-02-21 04:23:09,841 INFO L290 TraceCheckUtils]: 1: Hoare triple {1800#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {1802#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:09,842 INFO L290 TraceCheckUtils]: 2: Hoare triple {1802#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1802#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:09,842 INFO L290 TraceCheckUtils]: 3: Hoare triple {1802#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1802#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:09,842 INFO L290 TraceCheckUtils]: 4: Hoare triple {1802#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 5: Hoare triple {1801#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1801#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 6: Hoare triple {1801#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 7: Hoare triple {1801#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 8: Hoare triple {1801#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,843 INFO L290 TraceCheckUtils]: 9: Hoare triple {1801#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 10: Hoare triple {1801#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 11: Hoare triple {1801#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 12: Hoare triple {1801#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 13: Hoare triple {1801#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1801#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 14: Hoare triple {1801#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,844 INFO L290 TraceCheckUtils]: 15: Hoare triple {1801#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 16: Hoare triple {1801#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 17: Hoare triple {1801#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1801#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 18: Hoare triple {1801#false} assume !(0 == ~M_E~0); {1801#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 19: Hoare triple {1801#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1801#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 20: Hoare triple {1801#false} assume !(0 == ~T2_E~0); {1801#false} is VALID [2022-02-21 04:23:09,845 INFO L290 TraceCheckUtils]: 21: Hoare triple {1801#false} assume !(0 == ~T3_E~0); {1801#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 22: Hoare triple {1801#false} assume !(0 == ~T4_E~0); {1801#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 23: Hoare triple {1801#false} assume !(0 == ~T5_E~0); {1801#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 24: Hoare triple {1801#false} assume !(0 == ~T6_E~0); {1801#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 25: Hoare triple {1801#false} assume !(0 == ~T7_E~0); {1801#false} is VALID [2022-02-21 04:23:09,846 INFO L290 TraceCheckUtils]: 26: Hoare triple {1801#false} assume !(0 == ~T8_E~0); {1801#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 27: Hoare triple {1801#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1801#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 28: Hoare triple {1801#false} assume !(0 == ~T10_E~0); {1801#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 29: Hoare triple {1801#false} assume !(0 == ~T11_E~0); {1801#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 30: Hoare triple {1801#false} assume !(0 == ~T12_E~0); {1801#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 31: Hoare triple {1801#false} assume !(0 == ~E_M~0); {1801#false} is VALID [2022-02-21 04:23:09,847 INFO L290 TraceCheckUtils]: 32: Hoare triple {1801#false} assume !(0 == ~E_1~0); {1801#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 33: Hoare triple {1801#false} assume !(0 == ~E_2~0); {1801#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 34: Hoare triple {1801#false} assume !(0 == ~E_3~0); {1801#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 35: Hoare triple {1801#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1801#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 36: Hoare triple {1801#false} assume !(0 == ~E_5~0); {1801#false} is VALID [2022-02-21 04:23:09,848 INFO L290 TraceCheckUtils]: 37: Hoare triple {1801#false} assume !(0 == ~E_6~0); {1801#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 38: Hoare triple {1801#false} assume !(0 == ~E_7~0); {1801#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 39: Hoare triple {1801#false} assume !(0 == ~E_8~0); {1801#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 40: Hoare triple {1801#false} assume !(0 == ~E_9~0); {1801#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 41: Hoare triple {1801#false} assume !(0 == ~E_10~0); {1801#false} is VALID [2022-02-21 04:23:09,849 INFO L290 TraceCheckUtils]: 42: Hoare triple {1801#false} assume !(0 == ~E_11~0); {1801#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 43: Hoare triple {1801#false} assume 0 == ~E_12~0;~E_12~0 := 1; {1801#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 44: Hoare triple {1801#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1801#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 45: Hoare triple {1801#false} assume 1 == ~m_pc~0; {1801#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 46: Hoare triple {1801#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1801#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 47: Hoare triple {1801#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1801#false} is VALID [2022-02-21 04:23:09,850 INFO L290 TraceCheckUtils]: 48: Hoare triple {1801#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1801#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 49: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp~1#1); {1801#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 50: Hoare triple {1801#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1801#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 51: Hoare triple {1801#false} assume !(1 == ~t1_pc~0); {1801#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 52: Hoare triple {1801#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1801#false} is VALID [2022-02-21 04:23:09,851 INFO L290 TraceCheckUtils]: 53: Hoare triple {1801#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1801#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 54: Hoare triple {1801#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1801#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 55: Hoare triple {1801#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1801#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 56: Hoare triple {1801#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1801#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 57: Hoare triple {1801#false} assume 1 == ~t2_pc~0; {1801#false} is VALID [2022-02-21 04:23:09,852 INFO L290 TraceCheckUtils]: 58: Hoare triple {1801#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1801#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 59: Hoare triple {1801#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1801#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 60: Hoare triple {1801#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1801#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 61: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp___1~0#1); {1801#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 62: Hoare triple {1801#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1801#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 63: Hoare triple {1801#false} assume !(1 == ~t3_pc~0); {1801#false} is VALID [2022-02-21 04:23:09,853 INFO L290 TraceCheckUtils]: 64: Hoare triple {1801#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1801#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 65: Hoare triple {1801#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1801#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 66: Hoare triple {1801#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1801#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 67: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp___2~0#1); {1801#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 68: Hoare triple {1801#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1801#false} is VALID [2022-02-21 04:23:09,854 INFO L290 TraceCheckUtils]: 69: Hoare triple {1801#false} assume 1 == ~t4_pc~0; {1801#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 70: Hoare triple {1801#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1801#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 71: Hoare triple {1801#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1801#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 72: Hoare triple {1801#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1801#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 73: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp___3~0#1); {1801#false} is VALID [2022-02-21 04:23:09,855 INFO L290 TraceCheckUtils]: 74: Hoare triple {1801#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1801#false} is VALID [2022-02-21 04:23:09,856 INFO L290 TraceCheckUtils]: 75: Hoare triple {1801#false} assume !(1 == ~t5_pc~0); {1801#false} is VALID [2022-02-21 04:23:09,856 INFO L290 TraceCheckUtils]: 76: Hoare triple {1801#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1801#false} is VALID [2022-02-21 04:23:09,856 INFO L290 TraceCheckUtils]: 77: Hoare triple {1801#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1801#false} is VALID [2022-02-21 04:23:09,856 INFO L290 TraceCheckUtils]: 78: Hoare triple {1801#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1801#false} is VALID [2022-02-21 04:23:09,856 INFO L290 TraceCheckUtils]: 79: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp___4~0#1); {1801#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 80: Hoare triple {1801#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1801#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 81: Hoare triple {1801#false} assume 1 == ~t6_pc~0; {1801#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 82: Hoare triple {1801#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1801#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 83: Hoare triple {1801#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1801#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 84: Hoare triple {1801#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1801#false} is VALID [2022-02-21 04:23:09,857 INFO L290 TraceCheckUtils]: 85: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp___5~0#1); {1801#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 86: Hoare triple {1801#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1801#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 87: Hoare triple {1801#false} assume 1 == ~t7_pc~0; {1801#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 88: Hoare triple {1801#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1801#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 89: Hoare triple {1801#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1801#false} is VALID [2022-02-21 04:23:09,858 INFO L290 TraceCheckUtils]: 90: Hoare triple {1801#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1801#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 91: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp___6~0#1); {1801#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 92: Hoare triple {1801#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1801#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 93: Hoare triple {1801#false} assume !(1 == ~t8_pc~0); {1801#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 94: Hoare triple {1801#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1801#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 95: Hoare triple {1801#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1801#false} is VALID [2022-02-21 04:23:09,859 INFO L290 TraceCheckUtils]: 96: Hoare triple {1801#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1801#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 97: Hoare triple {1801#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1801#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 98: Hoare triple {1801#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1801#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 99: Hoare triple {1801#false} assume 1 == ~t9_pc~0; {1801#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 100: Hoare triple {1801#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1801#false} is VALID [2022-02-21 04:23:09,860 INFO L290 TraceCheckUtils]: 101: Hoare triple {1801#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1801#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 102: Hoare triple {1801#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1801#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 103: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp___8~0#1); {1801#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 104: Hoare triple {1801#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1801#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 105: Hoare triple {1801#false} assume !(1 == ~t10_pc~0); {1801#false} is VALID [2022-02-21 04:23:09,861 INFO L290 TraceCheckUtils]: 106: Hoare triple {1801#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1801#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 107: Hoare triple {1801#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1801#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 108: Hoare triple {1801#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {1801#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 109: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp___9~0#1); {1801#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 110: Hoare triple {1801#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1801#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 111: Hoare triple {1801#false} assume 1 == ~t11_pc~0; {1801#false} is VALID [2022-02-21 04:23:09,862 INFO L290 TraceCheckUtils]: 112: Hoare triple {1801#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {1801#false} is VALID [2022-02-21 04:23:09,863 INFO L290 TraceCheckUtils]: 113: Hoare triple {1801#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1801#false} is VALID [2022-02-21 04:23:09,863 INFO L290 TraceCheckUtils]: 114: Hoare triple {1801#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {1801#false} is VALID [2022-02-21 04:23:09,863 INFO L290 TraceCheckUtils]: 115: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp___10~0#1); {1801#false} is VALID [2022-02-21 04:23:09,863 INFO L290 TraceCheckUtils]: 116: Hoare triple {1801#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {1801#false} is VALID [2022-02-21 04:23:09,864 INFO L290 TraceCheckUtils]: 117: Hoare triple {1801#false} assume !(1 == ~t12_pc~0); {1801#false} is VALID [2022-02-21 04:23:09,864 INFO L290 TraceCheckUtils]: 118: Hoare triple {1801#false} is_transmit12_triggered_~__retres1~12#1 := 0; {1801#false} is VALID [2022-02-21 04:23:09,864 INFO L290 TraceCheckUtils]: 119: Hoare triple {1801#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {1801#false} is VALID [2022-02-21 04:23:09,864 INFO L290 TraceCheckUtils]: 120: Hoare triple {1801#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {1801#false} is VALID [2022-02-21 04:23:09,864 INFO L290 TraceCheckUtils]: 121: Hoare triple {1801#false} assume !(0 != activate_threads_~tmp___11~0#1); {1801#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 122: Hoare triple {1801#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1801#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 123: Hoare triple {1801#false} assume !(1 == ~M_E~0); {1801#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 124: Hoare triple {1801#false} assume !(1 == ~T1_E~0); {1801#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 125: Hoare triple {1801#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,865 INFO L290 TraceCheckUtils]: 126: Hoare triple {1801#false} assume !(1 == ~T3_E~0); {1801#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 127: Hoare triple {1801#false} assume !(1 == ~T4_E~0); {1801#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 128: Hoare triple {1801#false} assume !(1 == ~T5_E~0); {1801#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 129: Hoare triple {1801#false} assume !(1 == ~T6_E~0); {1801#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 130: Hoare triple {1801#false} assume !(1 == ~T7_E~0); {1801#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 131: Hoare triple {1801#false} assume !(1 == ~T8_E~0); {1801#false} is VALID [2022-02-21 04:23:09,866 INFO L290 TraceCheckUtils]: 132: Hoare triple {1801#false} assume !(1 == ~T9_E~0); {1801#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 133: Hoare triple {1801#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 134: Hoare triple {1801#false} assume !(1 == ~T11_E~0); {1801#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 135: Hoare triple {1801#false} assume !(1 == ~T12_E~0); {1801#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 136: Hoare triple {1801#false} assume !(1 == ~E_M~0); {1801#false} is VALID [2022-02-21 04:23:09,867 INFO L290 TraceCheckUtils]: 137: Hoare triple {1801#false} assume !(1 == ~E_1~0); {1801#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 138: Hoare triple {1801#false} assume !(1 == ~E_2~0); {1801#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 139: Hoare triple {1801#false} assume !(1 == ~E_3~0); {1801#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 140: Hoare triple {1801#false} assume !(1 == ~E_4~0); {1801#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 141: Hoare triple {1801#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1801#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 142: Hoare triple {1801#false} assume !(1 == ~E_6~0); {1801#false} is VALID [2022-02-21 04:23:09,868 INFO L290 TraceCheckUtils]: 143: Hoare triple {1801#false} assume !(1 == ~E_7~0); {1801#false} is VALID [2022-02-21 04:23:09,869 INFO L290 TraceCheckUtils]: 144: Hoare triple {1801#false} assume !(1 == ~E_8~0); {1801#false} is VALID [2022-02-21 04:23:09,869 INFO L290 TraceCheckUtils]: 145: Hoare triple {1801#false} assume !(1 == ~E_9~0); {1801#false} is VALID [2022-02-21 04:23:09,869 INFO L290 TraceCheckUtils]: 146: Hoare triple {1801#false} assume !(1 == ~E_10~0); {1801#false} is VALID [2022-02-21 04:23:09,869 INFO L290 TraceCheckUtils]: 147: Hoare triple {1801#false} assume !(1 == ~E_11~0); {1801#false} is VALID [2022-02-21 04:23:09,869 INFO L290 TraceCheckUtils]: 148: Hoare triple {1801#false} assume !(1 == ~E_12~0); {1801#false} is VALID [2022-02-21 04:23:09,869 INFO L290 TraceCheckUtils]: 149: Hoare triple {1801#false} assume { :end_inline_reset_delta_events } true; {1801#false} is VALID [2022-02-21 04:23:09,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,871 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,871 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141485424] [2022-02-21 04:23:09,872 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1141485424] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,872 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,872 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:09,873 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301407930] [2022-02-21 04:23:09,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,876 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:09,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,877 INFO L85 PathProgramCache]: Analyzing trace with hash -1810120649, now seen corresponding path program 1 times [2022-02-21 04:23:09,877 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,877 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647512065] [2022-02-21 04:23:09,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,919 INFO L290 TraceCheckUtils]: 0: Hoare triple {1803#true} assume !false; {1803#true} is VALID [2022-02-21 04:23:09,919 INFO L290 TraceCheckUtils]: 1: Hoare triple {1803#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1803#true} is VALID [2022-02-21 04:23:09,920 INFO L290 TraceCheckUtils]: 2: Hoare triple {1803#true} assume false; {1804#false} is VALID [2022-02-21 04:23:09,920 INFO L290 TraceCheckUtils]: 3: Hoare triple {1804#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1804#false} is VALID [2022-02-21 04:23:09,920 INFO L290 TraceCheckUtils]: 4: Hoare triple {1804#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1804#false} is VALID [2022-02-21 04:23:09,920 INFO L290 TraceCheckUtils]: 5: Hoare triple {1804#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,923 INFO L290 TraceCheckUtils]: 6: Hoare triple {1804#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,923 INFO L290 TraceCheckUtils]: 7: Hoare triple {1804#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,923 INFO L290 TraceCheckUtils]: 8: Hoare triple {1804#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,923 INFO L290 TraceCheckUtils]: 9: Hoare triple {1804#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,924 INFO L290 TraceCheckUtils]: 10: Hoare triple {1804#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,924 INFO L290 TraceCheckUtils]: 11: Hoare triple {1804#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,924 INFO L290 TraceCheckUtils]: 12: Hoare triple {1804#false} assume !(0 == ~T7_E~0); {1804#false} is VALID [2022-02-21 04:23:09,924 INFO L290 TraceCheckUtils]: 13: Hoare triple {1804#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,924 INFO L290 TraceCheckUtils]: 14: Hoare triple {1804#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,925 INFO L290 TraceCheckUtils]: 15: Hoare triple {1804#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,925 INFO L290 TraceCheckUtils]: 16: Hoare triple {1804#false} assume 0 == ~T11_E~0;~T11_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,925 INFO L290 TraceCheckUtils]: 17: Hoare triple {1804#false} assume 0 == ~T12_E~0;~T12_E~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,931 INFO L290 TraceCheckUtils]: 18: Hoare triple {1804#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,931 INFO L290 TraceCheckUtils]: 19: Hoare triple {1804#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,931 INFO L290 TraceCheckUtils]: 20: Hoare triple {1804#false} assume !(0 == ~E_2~0); {1804#false} is VALID [2022-02-21 04:23:09,932 INFO L290 TraceCheckUtils]: 21: Hoare triple {1804#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,932 INFO L290 TraceCheckUtils]: 22: Hoare triple {1804#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,932 INFO L290 TraceCheckUtils]: 23: Hoare triple {1804#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,932 INFO L290 TraceCheckUtils]: 24: Hoare triple {1804#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,932 INFO L290 TraceCheckUtils]: 25: Hoare triple {1804#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,932 INFO L290 TraceCheckUtils]: 26: Hoare triple {1804#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,933 INFO L290 TraceCheckUtils]: 27: Hoare triple {1804#false} assume 0 == ~E_9~0;~E_9~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,933 INFO L290 TraceCheckUtils]: 28: Hoare triple {1804#false} assume !(0 == ~E_10~0); {1804#false} is VALID [2022-02-21 04:23:09,933 INFO L290 TraceCheckUtils]: 29: Hoare triple {1804#false} assume 0 == ~E_11~0;~E_11~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,933 INFO L290 TraceCheckUtils]: 30: Hoare triple {1804#false} assume 0 == ~E_12~0;~E_12~0 := 1; {1804#false} is VALID [2022-02-21 04:23:09,933 INFO L290 TraceCheckUtils]: 31: Hoare triple {1804#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1804#false} is VALID [2022-02-21 04:23:09,934 INFO L290 TraceCheckUtils]: 32: Hoare triple {1804#false} assume 1 == ~m_pc~0; {1804#false} is VALID [2022-02-21 04:23:09,934 INFO L290 TraceCheckUtils]: 33: Hoare triple {1804#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1804#false} is VALID [2022-02-21 04:23:09,934 INFO L290 TraceCheckUtils]: 34: Hoare triple {1804#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1804#false} is VALID [2022-02-21 04:23:09,934 INFO L290 TraceCheckUtils]: 35: Hoare triple {1804#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1804#false} is VALID [2022-02-21 04:23:09,934 INFO L290 TraceCheckUtils]: 36: Hoare triple {1804#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,934 INFO L290 TraceCheckUtils]: 37: Hoare triple {1804#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1804#false} is VALID [2022-02-21 04:23:09,935 INFO L290 TraceCheckUtils]: 38: Hoare triple {1804#false} assume 1 == ~t1_pc~0; {1804#false} is VALID [2022-02-21 04:23:09,935 INFO L290 TraceCheckUtils]: 39: Hoare triple {1804#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1804#false} is VALID [2022-02-21 04:23:09,935 INFO L290 TraceCheckUtils]: 40: Hoare triple {1804#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1804#false} is VALID [2022-02-21 04:23:09,935 INFO L290 TraceCheckUtils]: 41: Hoare triple {1804#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1804#false} is VALID [2022-02-21 04:23:09,935 INFO L290 TraceCheckUtils]: 42: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,935 INFO L290 TraceCheckUtils]: 43: Hoare triple {1804#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1804#false} is VALID [2022-02-21 04:23:09,936 INFO L290 TraceCheckUtils]: 44: Hoare triple {1804#false} assume 1 == ~t2_pc~0; {1804#false} is VALID [2022-02-21 04:23:09,936 INFO L290 TraceCheckUtils]: 45: Hoare triple {1804#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1804#false} is VALID [2022-02-21 04:23:09,936 INFO L290 TraceCheckUtils]: 46: Hoare triple {1804#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1804#false} is VALID [2022-02-21 04:23:09,936 INFO L290 TraceCheckUtils]: 47: Hoare triple {1804#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1804#false} is VALID [2022-02-21 04:23:09,936 INFO L290 TraceCheckUtils]: 48: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,938 INFO L290 TraceCheckUtils]: 49: Hoare triple {1804#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1804#false} is VALID [2022-02-21 04:23:09,939 INFO L290 TraceCheckUtils]: 50: Hoare triple {1804#false} assume !(1 == ~t3_pc~0); {1804#false} is VALID [2022-02-21 04:23:09,939 INFO L290 TraceCheckUtils]: 51: Hoare triple {1804#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1804#false} is VALID [2022-02-21 04:23:09,939 INFO L290 TraceCheckUtils]: 52: Hoare triple {1804#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1804#false} is VALID [2022-02-21 04:23:09,939 INFO L290 TraceCheckUtils]: 53: Hoare triple {1804#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1804#false} is VALID [2022-02-21 04:23:09,939 INFO L290 TraceCheckUtils]: 54: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,939 INFO L290 TraceCheckUtils]: 55: Hoare triple {1804#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1804#false} is VALID [2022-02-21 04:23:09,940 INFO L290 TraceCheckUtils]: 56: Hoare triple {1804#false} assume 1 == ~t4_pc~0; {1804#false} is VALID [2022-02-21 04:23:09,940 INFO L290 TraceCheckUtils]: 57: Hoare triple {1804#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1804#false} is VALID [2022-02-21 04:23:09,940 INFO L290 TraceCheckUtils]: 58: Hoare triple {1804#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1804#false} is VALID [2022-02-21 04:23:09,940 INFO L290 TraceCheckUtils]: 59: Hoare triple {1804#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1804#false} is VALID [2022-02-21 04:23:09,940 INFO L290 TraceCheckUtils]: 60: Hoare triple {1804#false} assume !(0 != activate_threads_~tmp___3~0#1); {1804#false} is VALID [2022-02-21 04:23:09,940 INFO L290 TraceCheckUtils]: 61: Hoare triple {1804#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1804#false} is VALID [2022-02-21 04:23:09,943 INFO L290 TraceCheckUtils]: 62: Hoare triple {1804#false} assume !(1 == ~t5_pc~0); {1804#false} is VALID [2022-02-21 04:23:09,943 INFO L290 TraceCheckUtils]: 63: Hoare triple {1804#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1804#false} is VALID [2022-02-21 04:23:09,944 INFO L290 TraceCheckUtils]: 64: Hoare triple {1804#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1804#false} is VALID [2022-02-21 04:23:09,944 INFO L290 TraceCheckUtils]: 65: Hoare triple {1804#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1804#false} is VALID [2022-02-21 04:23:09,944 INFO L290 TraceCheckUtils]: 66: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,944 INFO L290 TraceCheckUtils]: 67: Hoare triple {1804#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1804#false} is VALID [2022-02-21 04:23:09,944 INFO L290 TraceCheckUtils]: 68: Hoare triple {1804#false} assume !(1 == ~t6_pc~0); {1804#false} is VALID [2022-02-21 04:23:09,944 INFO L290 TraceCheckUtils]: 69: Hoare triple {1804#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1804#false} is VALID [2022-02-21 04:23:09,945 INFO L290 TraceCheckUtils]: 70: Hoare triple {1804#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1804#false} is VALID [2022-02-21 04:23:09,945 INFO L290 TraceCheckUtils]: 71: Hoare triple {1804#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1804#false} is VALID [2022-02-21 04:23:09,945 INFO L290 TraceCheckUtils]: 72: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,945 INFO L290 TraceCheckUtils]: 73: Hoare triple {1804#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1804#false} is VALID [2022-02-21 04:23:09,945 INFO L290 TraceCheckUtils]: 74: Hoare triple {1804#false} assume 1 == ~t7_pc~0; {1804#false} is VALID [2022-02-21 04:23:09,945 INFO L290 TraceCheckUtils]: 75: Hoare triple {1804#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1804#false} is VALID [2022-02-21 04:23:09,946 INFO L290 TraceCheckUtils]: 76: Hoare triple {1804#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1804#false} is VALID [2022-02-21 04:23:09,946 INFO L290 TraceCheckUtils]: 77: Hoare triple {1804#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1804#false} is VALID [2022-02-21 04:23:09,946 INFO L290 TraceCheckUtils]: 78: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,946 INFO L290 TraceCheckUtils]: 79: Hoare triple {1804#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1804#false} is VALID [2022-02-21 04:23:09,946 INFO L290 TraceCheckUtils]: 80: Hoare triple {1804#false} assume 1 == ~t8_pc~0; {1804#false} is VALID [2022-02-21 04:23:09,946 INFO L290 TraceCheckUtils]: 81: Hoare triple {1804#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1804#false} is VALID [2022-02-21 04:23:09,947 INFO L290 TraceCheckUtils]: 82: Hoare triple {1804#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1804#false} is VALID [2022-02-21 04:23:09,947 INFO L290 TraceCheckUtils]: 83: Hoare triple {1804#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1804#false} is VALID [2022-02-21 04:23:09,947 INFO L290 TraceCheckUtils]: 84: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,948 INFO L290 TraceCheckUtils]: 85: Hoare triple {1804#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1804#false} is VALID [2022-02-21 04:23:09,948 INFO L290 TraceCheckUtils]: 86: Hoare triple {1804#false} assume 1 == ~t9_pc~0; {1804#false} is VALID [2022-02-21 04:23:09,948 INFO L290 TraceCheckUtils]: 87: Hoare triple {1804#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1804#false} is VALID [2022-02-21 04:23:09,948 INFO L290 TraceCheckUtils]: 88: Hoare triple {1804#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1804#false} is VALID [2022-02-21 04:23:09,949 INFO L290 TraceCheckUtils]: 89: Hoare triple {1804#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1804#false} is VALID [2022-02-21 04:23:09,955 INFO L290 TraceCheckUtils]: 90: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,955 INFO L290 TraceCheckUtils]: 91: Hoare triple {1804#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1804#false} is VALID [2022-02-21 04:23:09,955 INFO L290 TraceCheckUtils]: 92: Hoare triple {1804#false} assume 1 == ~t10_pc~0; {1804#false} is VALID [2022-02-21 04:23:09,955 INFO L290 TraceCheckUtils]: 93: Hoare triple {1804#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {1804#false} is VALID [2022-02-21 04:23:09,955 INFO L290 TraceCheckUtils]: 94: Hoare triple {1804#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1804#false} is VALID [2022-02-21 04:23:09,956 INFO L290 TraceCheckUtils]: 95: Hoare triple {1804#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {1804#false} is VALID [2022-02-21 04:23:09,956 INFO L290 TraceCheckUtils]: 96: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,956 INFO L290 TraceCheckUtils]: 97: Hoare triple {1804#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1804#false} is VALID [2022-02-21 04:23:09,956 INFO L290 TraceCheckUtils]: 98: Hoare triple {1804#false} assume !(1 == ~t11_pc~0); {1804#false} is VALID [2022-02-21 04:23:09,956 INFO L290 TraceCheckUtils]: 99: Hoare triple {1804#false} is_transmit11_triggered_~__retres1~11#1 := 0; {1804#false} is VALID [2022-02-21 04:23:09,956 INFO L290 TraceCheckUtils]: 100: Hoare triple {1804#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1804#false} is VALID [2022-02-21 04:23:09,956 INFO L290 TraceCheckUtils]: 101: Hoare triple {1804#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {1804#false} is VALID [2022-02-21 04:23:09,956 INFO L290 TraceCheckUtils]: 102: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,956 INFO L290 TraceCheckUtils]: 103: Hoare triple {1804#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {1804#false} is VALID [2022-02-21 04:23:09,956 INFO L290 TraceCheckUtils]: 104: Hoare triple {1804#false} assume !(1 == ~t12_pc~0); {1804#false} is VALID [2022-02-21 04:23:09,957 INFO L290 TraceCheckUtils]: 105: Hoare triple {1804#false} is_transmit12_triggered_~__retres1~12#1 := 0; {1804#false} is VALID [2022-02-21 04:23:09,957 INFO L290 TraceCheckUtils]: 106: Hoare triple {1804#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {1804#false} is VALID [2022-02-21 04:23:09,957 INFO L290 TraceCheckUtils]: 107: Hoare triple {1804#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {1804#false} is VALID [2022-02-21 04:23:09,957 INFO L290 TraceCheckUtils]: 108: Hoare triple {1804#false} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {1804#false} is VALID [2022-02-21 04:23:09,957 INFO L290 TraceCheckUtils]: 109: Hoare triple {1804#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1804#false} is VALID [2022-02-21 04:23:09,957 INFO L290 TraceCheckUtils]: 110: Hoare triple {1804#false} assume !(1 == ~M_E~0); {1804#false} is VALID [2022-02-21 04:23:09,957 INFO L290 TraceCheckUtils]: 111: Hoare triple {1804#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,957 INFO L290 TraceCheckUtils]: 112: Hoare triple {1804#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,957 INFO L290 TraceCheckUtils]: 113: Hoare triple {1804#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,957 INFO L290 TraceCheckUtils]: 114: Hoare triple {1804#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 115: Hoare triple {1804#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 116: Hoare triple {1804#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 117: Hoare triple {1804#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 118: Hoare triple {1804#false} assume !(1 == ~T8_E~0); {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 119: Hoare triple {1804#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 120: Hoare triple {1804#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 121: Hoare triple {1804#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 122: Hoare triple {1804#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 123: Hoare triple {1804#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 124: Hoare triple {1804#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,958 INFO L290 TraceCheckUtils]: 125: Hoare triple {1804#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 126: Hoare triple {1804#false} assume !(1 == ~E_3~0); {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 127: Hoare triple {1804#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 128: Hoare triple {1804#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 129: Hoare triple {1804#false} assume 1 == ~E_6~0;~E_6~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 130: Hoare triple {1804#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 131: Hoare triple {1804#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 132: Hoare triple {1804#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 133: Hoare triple {1804#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 134: Hoare triple {1804#false} assume !(1 == ~E_11~0); {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 135: Hoare triple {1804#false} assume 1 == ~E_12~0;~E_12~0 := 2; {1804#false} is VALID [2022-02-21 04:23:09,959 INFO L290 TraceCheckUtils]: 136: Hoare triple {1804#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {1804#false} is VALID [2022-02-21 04:23:09,960 INFO L290 TraceCheckUtils]: 137: Hoare triple {1804#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {1804#false} is VALID [2022-02-21 04:23:09,960 INFO L290 TraceCheckUtils]: 138: Hoare triple {1804#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {1804#false} is VALID [2022-02-21 04:23:09,960 INFO L290 TraceCheckUtils]: 139: Hoare triple {1804#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {1804#false} is VALID [2022-02-21 04:23:09,960 INFO L290 TraceCheckUtils]: 140: Hoare triple {1804#false} assume !(0 == start_simulation_~tmp~3#1); {1804#false} is VALID [2022-02-21 04:23:09,960 INFO L290 TraceCheckUtils]: 141: Hoare triple {1804#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {1804#false} is VALID [2022-02-21 04:23:09,960 INFO L290 TraceCheckUtils]: 142: Hoare triple {1804#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {1804#false} is VALID [2022-02-21 04:23:09,960 INFO L290 TraceCheckUtils]: 143: Hoare triple {1804#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {1804#false} is VALID [2022-02-21 04:23:09,960 INFO L290 TraceCheckUtils]: 144: Hoare triple {1804#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {1804#false} is VALID [2022-02-21 04:23:09,960 INFO L290 TraceCheckUtils]: 145: Hoare triple {1804#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1804#false} is VALID [2022-02-21 04:23:09,960 INFO L290 TraceCheckUtils]: 146: Hoare triple {1804#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1804#false} is VALID [2022-02-21 04:23:09,961 INFO L290 TraceCheckUtils]: 147: Hoare triple {1804#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {1804#false} is VALID [2022-02-21 04:23:09,961 INFO L290 TraceCheckUtils]: 148: Hoare triple {1804#false} assume !(0 != start_simulation_~tmp___0~1#1); {1804#false} is VALID [2022-02-21 04:23:09,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,961 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,961 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647512065] [2022-02-21 04:23:09,962 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [647512065] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,962 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,962 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:09,962 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529421183] [2022-02-21 04:23:09,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,964 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:09,965 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:09,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-21 04:23:09,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-21 04:23:09,992 INFO L87 Difference]: Start difference. First operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,895 INFO L93 Difference]: Finished difference Result 1794 states and 2657 transitions. [2022-02-21 04:23:10,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-21 04:23:10,896 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,001 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 149 edges. 149 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:11,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1794 states and 2657 transitions. [2022-02-21 04:23:11,118 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:11,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1794 states to 1788 states and 2651 transitions. [2022-02-21 04:23:11,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:11,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:11,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2651 transitions. [2022-02-21 04:23:11,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:11,215 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2022-02-21 04:23:11,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2651 transitions. [2022-02-21 04:23:11,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:11,290 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:11,296 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2651 transitions. Second operand has 1788 states, 1788 states have (on average 1.482662192393736) internal successors, (2651), 1787 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,302 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2651 transitions. Second operand has 1788 states, 1788 states have (on average 1.482662192393736) internal successors, (2651), 1787 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,305 INFO L87 Difference]: Start difference. First operand 1788 states and 2651 transitions. Second operand has 1788 states, 1788 states have (on average 1.482662192393736) internal successors, (2651), 1787 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,395 INFO L93 Difference]: Finished difference Result 1788 states and 2651 transitions. [2022-02-21 04:23:11,395 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2651 transitions. [2022-02-21 04:23:11,414 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:11,414 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:11,417 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.482662192393736) internal successors, (2651), 1787 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2651 transitions. [2022-02-21 04:23:11,419 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.482662192393736) internal successors, (2651), 1787 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2651 transitions. [2022-02-21 04:23:11,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,503 INFO L93 Difference]: Finished difference Result 1788 states and 2651 transitions. [2022-02-21 04:23:11,504 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2651 transitions. [2022-02-21 04:23:11,506 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:11,506 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:11,506 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:11,506 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:11,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.482662192393736) internal successors, (2651), 1787 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2651 transitions. [2022-02-21 04:23:11,593 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2022-02-21 04:23:11,593 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2022-02-21 04:23:11,594 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:23:11,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2651 transitions. [2022-02-21 04:23:11,600 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:11,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:11,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:11,602 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,602 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,602 INFO L791 eck$LassoCheckResult]: Stem: 4388#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3909#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3910#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3964#L848 assume !(1 == ~m_i~0);~m_st~0 := 2; 5303#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4397#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4200#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3599#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3600#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4822#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4933#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5369#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5370#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4328#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4329#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4851#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4770#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4363#L1201 assume !(0 == ~M_E~0); 4364#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5210#L1206-1 assume !(0 == ~T2_E~0); 5196#L1211-1 assume !(0 == ~T3_E~0); 5197#L1216-1 assume !(0 == ~T4_E~0); 4184#L1221-1 assume !(0 == ~T5_E~0); 4185#L1226-1 assume !(0 == ~T6_E~0); 3824#L1231-1 assume !(0 == ~T7_E~0); 3825#L1236-1 assume !(0 == ~T8_E~0); 5233#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4221#L1246-1 assume !(0 == ~T10_E~0); 4222#L1251-1 assume !(0 == ~T11_E~0); 4361#L1256-1 assume !(0 == ~T12_E~0); 3610#L1261-1 assume !(0 == ~E_M~0); 3611#L1266-1 assume !(0 == ~E_1~0); 5355#L1271-1 assume !(0 == ~E_2~0); 4917#L1276-1 assume !(0 == ~E_3~0); 4918#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4865#L1286-1 assume !(0 == ~E_5~0); 4075#L1291-1 assume !(0 == ~E_6~0); 4076#L1296-1 assume !(0 == ~E_7~0); 4651#L1301-1 assume !(0 == ~E_8~0); 4652#L1306-1 assume !(0 == ~E_9~0); 5132#L1311-1 assume !(0 == ~E_10~0); 4026#L1316-1 assume !(0 == ~E_11~0); 4027#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 4669#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4670#L593 assume 1 == ~m_pc~0; 4814#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3916#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5342#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4876#L1492 assume !(0 != activate_threads_~tmp~1#1); 4877#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5168#L612 assume !(1 == ~t1_pc~0); 5169#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5298#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4298#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3920#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3921#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4340#L631 assume 1 == ~t2_pc~0; 4275#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3697#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3698#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4534#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 4535#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3993#L650 assume !(1 == ~t3_pc~0); 3994#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4694#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3917#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3650#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 3651#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4843#L669 assume 1 == ~t4_pc~0; 4844#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5202#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4327#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3859#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 3860#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4084#L688 assume !(1 == ~t5_pc~0); 3875#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3876#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4794#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4728#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 4729#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4858#L707 assume 1 == ~t6_pc~0; 5267#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4504#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4505#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5265#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 4800#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4362#L726 assume 1 == ~t7_pc~0; 4261#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3960#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5001#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5275#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 3729#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3730#L745 assume !(1 == ~t8_pc~0); 4177#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4196#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5034#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4582#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4583#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5093#L764 assume 1 == ~t9_pc~0; 4360#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4202#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4879#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5326#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 3749#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3750#L783 assume !(1 == ~t10_pc~0); 3811#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3812#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3853#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3854#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 4316#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5204#L802 assume 1 == ~t11_pc~0; 5186#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3694#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3695#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4186#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 4187#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4297#L821 assume !(1 == ~t12_pc~0); 4548#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4644#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3699#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3700#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 5242#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4888#L1339 assume !(1 == ~M_E~0); 4889#L1339-2 assume !(1 == ~T1_E~0); 5277#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5278#L1349-1 assume !(1 == ~T3_E~0); 4662#L1354-1 assume !(1 == ~T4_E~0); 4663#L1359-1 assume !(1 == ~T5_E~0); 5064#L1364-1 assume !(1 == ~T6_E~0); 4127#L1369-1 assume !(1 == ~T7_E~0); 4128#L1374-1 assume !(1 == ~T8_E~0); 4665#L1379-1 assume !(1 == ~T9_E~0); 4666#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4765#L1389-1 assume !(1 == ~T11_E~0); 5236#L1394-1 assume !(1 == ~T12_E~0); 5237#L1399-1 assume !(1 == ~E_M~0); 5327#L1404-1 assume !(1 == ~E_1~0); 4226#L1409-1 assume !(1 == ~E_2~0); 4227#L1414-1 assume !(1 == ~E_3~0); 4953#L1419-1 assume !(1 == ~E_4~0); 3867#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3868#L1429-1 assume !(1 == ~E_6~0); 4678#L1434-1 assume !(1 == ~E_7~0); 5257#L1439-1 assume !(1 == ~E_8~0); 3905#L1444-1 assume !(1 == ~E_9~0); 3906#L1449-1 assume !(1 == ~E_10~0); 4280#L1454-1 assume !(1 == ~E_11~0); 4281#L1459-1 assume !(1 == ~E_12~0); 4799#L1464-1 assume { :end_inline_reset_delta_events } true; 4039#L1810-2 [2022-02-21 04:23:11,603 INFO L793 eck$LassoCheckResult]: Loop: 4039#L1810-2 assume !false; 4483#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4399#L1176 assume !false; 4961#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4531#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3737#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4287#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4288#L1003 assume !(0 != eval_~tmp~0#1); 3929#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3930#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5120#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4903#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4904#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4797#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3988#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3989#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4455#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4059#L1231-3 assume !(0 == ~T7_E~0); 4060#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4306#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5288#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5189#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4894#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4005#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4006#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4051#L1271-3 assume !(0 == ~E_2~0); 4052#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4428#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4429#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4950#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4951#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5366#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5323#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4540#L1311-3 assume !(0 == ~E_10~0); 3931#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3932#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4007#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4643#L593-42 assume !(1 == ~m_pc~0); 4801#L593-44 is_master_triggered_~__retres1~0#1 := 0; 4802#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5351#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5352#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3830#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3831#L612-42 assume !(1 == ~t1_pc~0); 4752#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 5145#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5266#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3918#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3919#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4614#L631-42 assume 1 == ~t2_pc~0; 3683#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3684#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4603#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4479#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4480#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4080#L650-42 assume 1 == ~t3_pc~0; 3642#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3643#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5294#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4273#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4274#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5258#L669-42 assume !(1 == ~t4_pc~0); 3640#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3641#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5069#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4959#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 4856#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4857#L688-42 assume 1 == ~t5_pc~0; 4948#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5149#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3781#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3782#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3858#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3672#L707-42 assume !(1 == ~t6_pc~0); 3673#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 5330#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5074#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5075#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4824#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4825#L726-42 assume 1 == ~t7_pc~0; 5102#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5128#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5129#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4543#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4544#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4647#L745-42 assume 1 == ~t8_pc~0; 4684#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4686#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4013#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3658#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3659#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4384#L764-42 assume 1 == ~t9_pc~0; 4520#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4873#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4874#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3944#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3945#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3998#L783-42 assume !(1 == ~t10_pc~0); 3616#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 3615#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4210#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4343#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5360#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5044#L802-42 assume 1 == ~t11_pc~0; 4145#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3756#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3757#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3707#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3708#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4884#L821-42 assume 1 == ~t12_pc~0; 4885#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4250#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3612#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3613#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4590#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4580#L1339-3 assume !(1 == ~M_E~0); 4581#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4732#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4842#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4259#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4260#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4853#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5349#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5256#L1374-3 assume !(1 == ~T8_E~0); 4081#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4082#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4257#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4258#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4467#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5263#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5231#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5232#L1414-3 assume !(1 == ~E_3~0); 5287#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5046#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3965#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3966#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4852#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3893#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3894#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4010#L1454-3 assume !(1 == ~E_11~0); 4847#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4848#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4506#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3803#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4063#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4064#L1829 assume !(0 == start_simulation_~tmp~3#1); 3785#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3786#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4586#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4587#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4866#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4867#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4487#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4038#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 4039#L1810-2 [2022-02-21 04:23:11,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,604 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2022-02-21 04:23:11,604 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,604 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722101688] [2022-02-21 04:23:11,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,648 INFO L290 TraceCheckUtils]: 0: Hoare triple {8966#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {8966#true} is VALID [2022-02-21 04:23:11,649 INFO L290 TraceCheckUtils]: 1: Hoare triple {8966#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {8968#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:11,649 INFO L290 TraceCheckUtils]: 2: Hoare triple {8968#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8968#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:11,650 INFO L290 TraceCheckUtils]: 3: Hoare triple {8968#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8968#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:11,650 INFO L290 TraceCheckUtils]: 4: Hoare triple {8968#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,650 INFO L290 TraceCheckUtils]: 5: Hoare triple {8967#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8967#false} is VALID [2022-02-21 04:23:11,650 INFO L290 TraceCheckUtils]: 6: Hoare triple {8967#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,650 INFO L290 TraceCheckUtils]: 7: Hoare triple {8967#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 8: Hoare triple {8967#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 9: Hoare triple {8967#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 10: Hoare triple {8967#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 11: Hoare triple {8967#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 12: Hoare triple {8967#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 13: Hoare triple {8967#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {8967#false} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 14: Hoare triple {8967#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 15: Hoare triple {8967#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 16: Hoare triple {8967#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 17: Hoare triple {8967#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8967#false} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 18: Hoare triple {8967#false} assume !(0 == ~M_E~0); {8967#false} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 19: Hoare triple {8967#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8967#false} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 20: Hoare triple {8967#false} assume !(0 == ~T2_E~0); {8967#false} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 21: Hoare triple {8967#false} assume !(0 == ~T3_E~0); {8967#false} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 22: Hoare triple {8967#false} assume !(0 == ~T4_E~0); {8967#false} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 23: Hoare triple {8967#false} assume !(0 == ~T5_E~0); {8967#false} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 24: Hoare triple {8967#false} assume !(0 == ~T6_E~0); {8967#false} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 25: Hoare triple {8967#false} assume !(0 == ~T7_E~0); {8967#false} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 26: Hoare triple {8967#false} assume !(0 == ~T8_E~0); {8967#false} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 27: Hoare triple {8967#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {8967#false} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 28: Hoare triple {8967#false} assume !(0 == ~T10_E~0); {8967#false} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 29: Hoare triple {8967#false} assume !(0 == ~T11_E~0); {8967#false} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 30: Hoare triple {8967#false} assume !(0 == ~T12_E~0); {8967#false} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 31: Hoare triple {8967#false} assume !(0 == ~E_M~0); {8967#false} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 32: Hoare triple {8967#false} assume !(0 == ~E_1~0); {8967#false} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 33: Hoare triple {8967#false} assume !(0 == ~E_2~0); {8967#false} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 34: Hoare triple {8967#false} assume !(0 == ~E_3~0); {8967#false} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 35: Hoare triple {8967#false} assume 0 == ~E_4~0;~E_4~0 := 1; {8967#false} is VALID [2022-02-21 04:23:11,655 INFO L290 TraceCheckUtils]: 36: Hoare triple {8967#false} assume !(0 == ~E_5~0); {8967#false} is VALID [2022-02-21 04:23:11,655 INFO L290 TraceCheckUtils]: 37: Hoare triple {8967#false} assume !(0 == ~E_6~0); {8967#false} is VALID [2022-02-21 04:23:11,655 INFO L290 TraceCheckUtils]: 38: Hoare triple {8967#false} assume !(0 == ~E_7~0); {8967#false} is VALID [2022-02-21 04:23:11,655 INFO L290 TraceCheckUtils]: 39: Hoare triple {8967#false} assume !(0 == ~E_8~0); {8967#false} is VALID [2022-02-21 04:23:11,655 INFO L290 TraceCheckUtils]: 40: Hoare triple {8967#false} assume !(0 == ~E_9~0); {8967#false} is VALID [2022-02-21 04:23:11,655 INFO L290 TraceCheckUtils]: 41: Hoare triple {8967#false} assume !(0 == ~E_10~0); {8967#false} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 42: Hoare triple {8967#false} assume !(0 == ~E_11~0); {8967#false} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 43: Hoare triple {8967#false} assume 0 == ~E_12~0;~E_12~0 := 1; {8967#false} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 44: Hoare triple {8967#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8967#false} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 45: Hoare triple {8967#false} assume 1 == ~m_pc~0; {8967#false} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 46: Hoare triple {8967#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {8967#false} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 47: Hoare triple {8967#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8967#false} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 48: Hoare triple {8967#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8967#false} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 49: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp~1#1); {8967#false} is VALID [2022-02-21 04:23:11,657 INFO L290 TraceCheckUtils]: 50: Hoare triple {8967#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8967#false} is VALID [2022-02-21 04:23:11,657 INFO L290 TraceCheckUtils]: 51: Hoare triple {8967#false} assume !(1 == ~t1_pc~0); {8967#false} is VALID [2022-02-21 04:23:11,657 INFO L290 TraceCheckUtils]: 52: Hoare triple {8967#false} is_transmit1_triggered_~__retres1~1#1 := 0; {8967#false} is VALID [2022-02-21 04:23:11,657 INFO L290 TraceCheckUtils]: 53: Hoare triple {8967#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8967#false} is VALID [2022-02-21 04:23:11,657 INFO L290 TraceCheckUtils]: 54: Hoare triple {8967#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {8967#false} is VALID [2022-02-21 04:23:11,657 INFO L290 TraceCheckUtils]: 55: Hoare triple {8967#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8967#false} is VALID [2022-02-21 04:23:11,658 INFO L290 TraceCheckUtils]: 56: Hoare triple {8967#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8967#false} is VALID [2022-02-21 04:23:11,658 INFO L290 TraceCheckUtils]: 57: Hoare triple {8967#false} assume 1 == ~t2_pc~0; {8967#false} is VALID [2022-02-21 04:23:11,658 INFO L290 TraceCheckUtils]: 58: Hoare triple {8967#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8967#false} is VALID [2022-02-21 04:23:11,658 INFO L290 TraceCheckUtils]: 59: Hoare triple {8967#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8967#false} is VALID [2022-02-21 04:23:11,660 INFO L290 TraceCheckUtils]: 60: Hoare triple {8967#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {8967#false} is VALID [2022-02-21 04:23:11,660 INFO L290 TraceCheckUtils]: 61: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp___1~0#1); {8967#false} is VALID [2022-02-21 04:23:11,660 INFO L290 TraceCheckUtils]: 62: Hoare triple {8967#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8967#false} is VALID [2022-02-21 04:23:11,660 INFO L290 TraceCheckUtils]: 63: Hoare triple {8967#false} assume !(1 == ~t3_pc~0); {8967#false} is VALID [2022-02-21 04:23:11,660 INFO L290 TraceCheckUtils]: 64: Hoare triple {8967#false} is_transmit3_triggered_~__retres1~3#1 := 0; {8967#false} is VALID [2022-02-21 04:23:11,660 INFO L290 TraceCheckUtils]: 65: Hoare triple {8967#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8967#false} is VALID [2022-02-21 04:23:11,661 INFO L290 TraceCheckUtils]: 66: Hoare triple {8967#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {8967#false} is VALID [2022-02-21 04:23:11,661 INFO L290 TraceCheckUtils]: 67: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp___2~0#1); {8967#false} is VALID [2022-02-21 04:23:11,662 INFO L290 TraceCheckUtils]: 68: Hoare triple {8967#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8967#false} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 69: Hoare triple {8967#false} assume 1 == ~t4_pc~0; {8967#false} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 70: Hoare triple {8967#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8967#false} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 71: Hoare triple {8967#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8967#false} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 72: Hoare triple {8967#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {8967#false} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 73: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp___3~0#1); {8967#false} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 74: Hoare triple {8967#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8967#false} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 75: Hoare triple {8967#false} assume !(1 == ~t5_pc~0); {8967#false} is VALID [2022-02-21 04:23:11,664 INFO L290 TraceCheckUtils]: 76: Hoare triple {8967#false} is_transmit5_triggered_~__retres1~5#1 := 0; {8967#false} is VALID [2022-02-21 04:23:11,664 INFO L290 TraceCheckUtils]: 77: Hoare triple {8967#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8967#false} is VALID [2022-02-21 04:23:11,664 INFO L290 TraceCheckUtils]: 78: Hoare triple {8967#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {8967#false} is VALID [2022-02-21 04:23:11,664 INFO L290 TraceCheckUtils]: 79: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp___4~0#1); {8967#false} is VALID [2022-02-21 04:23:11,664 INFO L290 TraceCheckUtils]: 80: Hoare triple {8967#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8967#false} is VALID [2022-02-21 04:23:11,664 INFO L290 TraceCheckUtils]: 81: Hoare triple {8967#false} assume 1 == ~t6_pc~0; {8967#false} is VALID [2022-02-21 04:23:11,664 INFO L290 TraceCheckUtils]: 82: Hoare triple {8967#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {8967#false} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 83: Hoare triple {8967#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8967#false} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 84: Hoare triple {8967#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {8967#false} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 85: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp___5~0#1); {8967#false} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 86: Hoare triple {8967#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {8967#false} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 87: Hoare triple {8967#false} assume 1 == ~t7_pc~0; {8967#false} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 88: Hoare triple {8967#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {8967#false} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 89: Hoare triple {8967#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {8967#false} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 90: Hoare triple {8967#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {8967#false} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 91: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp___6~0#1); {8967#false} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 92: Hoare triple {8967#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {8967#false} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 93: Hoare triple {8967#false} assume !(1 == ~t8_pc~0); {8967#false} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 94: Hoare triple {8967#false} is_transmit8_triggered_~__retres1~8#1 := 0; {8967#false} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 95: Hoare triple {8967#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {8967#false} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 96: Hoare triple {8967#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {8967#false} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 97: Hoare triple {8967#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {8967#false} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 98: Hoare triple {8967#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {8967#false} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 99: Hoare triple {8967#false} assume 1 == ~t9_pc~0; {8967#false} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 100: Hoare triple {8967#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {8967#false} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 101: Hoare triple {8967#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {8967#false} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 102: Hoare triple {8967#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {8967#false} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 103: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp___8~0#1); {8967#false} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 104: Hoare triple {8967#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {8967#false} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 105: Hoare triple {8967#false} assume !(1 == ~t10_pc~0); {8967#false} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 106: Hoare triple {8967#false} is_transmit10_triggered_~__retres1~10#1 := 0; {8967#false} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 107: Hoare triple {8967#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {8967#false} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 108: Hoare triple {8967#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {8967#false} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 109: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp___9~0#1); {8967#false} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 110: Hoare triple {8967#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {8967#false} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 111: Hoare triple {8967#false} assume 1 == ~t11_pc~0; {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 112: Hoare triple {8967#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 113: Hoare triple {8967#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 114: Hoare triple {8967#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 115: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp___10~0#1); {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 116: Hoare triple {8967#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 117: Hoare triple {8967#false} assume !(1 == ~t12_pc~0); {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 118: Hoare triple {8967#false} is_transmit12_triggered_~__retres1~12#1 := 0; {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 119: Hoare triple {8967#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 120: Hoare triple {8967#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 121: Hoare triple {8967#false} assume !(0 != activate_threads_~tmp___11~0#1); {8967#false} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 122: Hoare triple {8967#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8967#false} is VALID [2022-02-21 04:23:11,670 INFO L290 TraceCheckUtils]: 123: Hoare triple {8967#false} assume !(1 == ~M_E~0); {8967#false} is VALID [2022-02-21 04:23:11,670 INFO L290 TraceCheckUtils]: 124: Hoare triple {8967#false} assume !(1 == ~T1_E~0); {8967#false} is VALID [2022-02-21 04:23:11,670 INFO L290 TraceCheckUtils]: 125: Hoare triple {8967#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,670 INFO L290 TraceCheckUtils]: 126: Hoare triple {8967#false} assume !(1 == ~T3_E~0); {8967#false} is VALID [2022-02-21 04:23:11,670 INFO L290 TraceCheckUtils]: 127: Hoare triple {8967#false} assume !(1 == ~T4_E~0); {8967#false} is VALID [2022-02-21 04:23:11,670 INFO L290 TraceCheckUtils]: 128: Hoare triple {8967#false} assume !(1 == ~T5_E~0); {8967#false} is VALID [2022-02-21 04:23:11,670 INFO L290 TraceCheckUtils]: 129: Hoare triple {8967#false} assume !(1 == ~T6_E~0); {8967#false} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 130: Hoare triple {8967#false} assume !(1 == ~T7_E~0); {8967#false} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 131: Hoare triple {8967#false} assume !(1 == ~T8_E~0); {8967#false} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 132: Hoare triple {8967#false} assume !(1 == ~T9_E~0); {8967#false} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 133: Hoare triple {8967#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 134: Hoare triple {8967#false} assume !(1 == ~T11_E~0); {8967#false} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 135: Hoare triple {8967#false} assume !(1 == ~T12_E~0); {8967#false} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 136: Hoare triple {8967#false} assume !(1 == ~E_M~0); {8967#false} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 137: Hoare triple {8967#false} assume !(1 == ~E_1~0); {8967#false} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 138: Hoare triple {8967#false} assume !(1 == ~E_2~0); {8967#false} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 139: Hoare triple {8967#false} assume !(1 == ~E_3~0); {8967#false} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 140: Hoare triple {8967#false} assume !(1 == ~E_4~0); {8967#false} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 141: Hoare triple {8967#false} assume 1 == ~E_5~0;~E_5~0 := 2; {8967#false} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 142: Hoare triple {8967#false} assume !(1 == ~E_6~0); {8967#false} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 143: Hoare triple {8967#false} assume !(1 == ~E_7~0); {8967#false} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 144: Hoare triple {8967#false} assume !(1 == ~E_8~0); {8967#false} is VALID [2022-02-21 04:23:11,673 INFO L290 TraceCheckUtils]: 145: Hoare triple {8967#false} assume !(1 == ~E_9~0); {8967#false} is VALID [2022-02-21 04:23:11,673 INFO L290 TraceCheckUtils]: 146: Hoare triple {8967#false} assume !(1 == ~E_10~0); {8967#false} is VALID [2022-02-21 04:23:11,673 INFO L290 TraceCheckUtils]: 147: Hoare triple {8967#false} assume !(1 == ~E_11~0); {8967#false} is VALID [2022-02-21 04:23:11,673 INFO L290 TraceCheckUtils]: 148: Hoare triple {8967#false} assume !(1 == ~E_12~0); {8967#false} is VALID [2022-02-21 04:23:11,673 INFO L290 TraceCheckUtils]: 149: Hoare triple {8967#false} assume { :end_inline_reset_delta_events } true; {8967#false} is VALID [2022-02-21 04:23:11,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,674 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,674 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722101688] [2022-02-21 04:23:11,674 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [722101688] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,674 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,674 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,675 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920883028] [2022-02-21 04:23:11,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,675 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:11,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,676 INFO L85 PathProgramCache]: Analyzing trace with hash -830311852, now seen corresponding path program 1 times [2022-02-21 04:23:11,676 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,676 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359019873] [2022-02-21 04:23:11,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,762 INFO L290 TraceCheckUtils]: 0: Hoare triple {8969#true} assume !false; {8969#true} is VALID [2022-02-21 04:23:11,762 INFO L290 TraceCheckUtils]: 1: Hoare triple {8969#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {8969#true} is VALID [2022-02-21 04:23:11,762 INFO L290 TraceCheckUtils]: 2: Hoare triple {8969#true} assume !false; {8969#true} is VALID [2022-02-21 04:23:11,762 INFO L290 TraceCheckUtils]: 3: Hoare triple {8969#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {8969#true} is VALID [2022-02-21 04:23:11,762 INFO L290 TraceCheckUtils]: 4: Hoare triple {8969#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {8969#true} is VALID [2022-02-21 04:23:11,763 INFO L290 TraceCheckUtils]: 5: Hoare triple {8969#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {8969#true} is VALID [2022-02-21 04:23:11,763 INFO L290 TraceCheckUtils]: 6: Hoare triple {8969#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {8969#true} is VALID [2022-02-21 04:23:11,763 INFO L290 TraceCheckUtils]: 7: Hoare triple {8969#true} assume !(0 != eval_~tmp~0#1); {8969#true} is VALID [2022-02-21 04:23:11,763 INFO L290 TraceCheckUtils]: 8: Hoare triple {8969#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8969#true} is VALID [2022-02-21 04:23:11,763 INFO L290 TraceCheckUtils]: 9: Hoare triple {8969#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8969#true} is VALID [2022-02-21 04:23:11,763 INFO L290 TraceCheckUtils]: 10: Hoare triple {8969#true} assume 0 == ~M_E~0;~M_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,763 INFO L290 TraceCheckUtils]: 11: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 12: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 13: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,764 INFO L290 TraceCheckUtils]: 14: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,765 INFO L290 TraceCheckUtils]: 15: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,765 INFO L290 TraceCheckUtils]: 16: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,765 INFO L290 TraceCheckUtils]: 17: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,765 INFO L290 TraceCheckUtils]: 18: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,766 INFO L290 TraceCheckUtils]: 19: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,766 INFO L290 TraceCheckUtils]: 20: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,766 INFO L290 TraceCheckUtils]: 21: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,767 INFO L290 TraceCheckUtils]: 22: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,767 INFO L290 TraceCheckUtils]: 23: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,767 INFO L290 TraceCheckUtils]: 24: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,767 INFO L290 TraceCheckUtils]: 25: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,768 INFO L290 TraceCheckUtils]: 26: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,768 INFO L290 TraceCheckUtils]: 27: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,768 INFO L290 TraceCheckUtils]: 28: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,769 INFO L290 TraceCheckUtils]: 29: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,769 INFO L290 TraceCheckUtils]: 30: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,769 INFO L290 TraceCheckUtils]: 31: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,769 INFO L290 TraceCheckUtils]: 32: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,770 INFO L290 TraceCheckUtils]: 33: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,770 INFO L290 TraceCheckUtils]: 34: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,770 INFO L290 TraceCheckUtils]: 35: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,771 INFO L290 TraceCheckUtils]: 36: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,771 INFO L290 TraceCheckUtils]: 37: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,771 INFO L290 TraceCheckUtils]: 38: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,772 INFO L290 TraceCheckUtils]: 39: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,772 INFO L290 TraceCheckUtils]: 40: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,772 INFO L290 TraceCheckUtils]: 41: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,772 INFO L290 TraceCheckUtils]: 42: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,773 INFO L290 TraceCheckUtils]: 43: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,773 INFO L290 TraceCheckUtils]: 44: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,773 INFO L290 TraceCheckUtils]: 45: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,774 INFO L290 TraceCheckUtils]: 46: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,774 INFO L290 TraceCheckUtils]: 47: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,774 INFO L290 TraceCheckUtils]: 48: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,774 INFO L290 TraceCheckUtils]: 49: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,775 INFO L290 TraceCheckUtils]: 50: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,776 INFO L290 TraceCheckUtils]: 51: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,777 INFO L290 TraceCheckUtils]: 52: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,777 INFO L290 TraceCheckUtils]: 53: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,777 INFO L290 TraceCheckUtils]: 54: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,777 INFO L290 TraceCheckUtils]: 55: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,778 INFO L290 TraceCheckUtils]: 56: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,778 INFO L290 TraceCheckUtils]: 57: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,778 INFO L290 TraceCheckUtils]: 58: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,779 INFO L290 TraceCheckUtils]: 59: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,779 INFO L290 TraceCheckUtils]: 60: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,787 INFO L290 TraceCheckUtils]: 61: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,789 INFO L290 TraceCheckUtils]: 62: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,790 INFO L290 TraceCheckUtils]: 63: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,791 INFO L290 TraceCheckUtils]: 64: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,791 INFO L290 TraceCheckUtils]: 65: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,791 INFO L290 TraceCheckUtils]: 66: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,791 INFO L290 TraceCheckUtils]: 67: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,792 INFO L290 TraceCheckUtils]: 68: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,792 INFO L290 TraceCheckUtils]: 69: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,792 INFO L290 TraceCheckUtils]: 70: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,793 INFO L290 TraceCheckUtils]: 71: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,793 INFO L290 TraceCheckUtils]: 72: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,793 INFO L290 TraceCheckUtils]: 73: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,794 INFO L290 TraceCheckUtils]: 74: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,795 INFO L290 TraceCheckUtils]: 75: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,796 INFO L290 TraceCheckUtils]: 76: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,796 INFO L290 TraceCheckUtils]: 77: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,796 INFO L290 TraceCheckUtils]: 78: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,796 INFO L290 TraceCheckUtils]: 79: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,797 INFO L290 TraceCheckUtils]: 80: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,797 INFO L290 TraceCheckUtils]: 81: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,797 INFO L290 TraceCheckUtils]: 82: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,798 INFO L290 TraceCheckUtils]: 83: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,798 INFO L290 TraceCheckUtils]: 84: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,798 INFO L290 TraceCheckUtils]: 85: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,798 INFO L290 TraceCheckUtils]: 86: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,799 INFO L290 TraceCheckUtils]: 87: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,799 INFO L290 TraceCheckUtils]: 88: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,799 INFO L290 TraceCheckUtils]: 89: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,800 INFO L290 TraceCheckUtils]: 90: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,800 INFO L290 TraceCheckUtils]: 91: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,800 INFO L290 TraceCheckUtils]: 92: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,800 INFO L290 TraceCheckUtils]: 93: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,801 INFO L290 TraceCheckUtils]: 94: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,801 INFO L290 TraceCheckUtils]: 95: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,801 INFO L290 TraceCheckUtils]: 96: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,802 INFO L290 TraceCheckUtils]: 97: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,802 INFO L290 TraceCheckUtils]: 98: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,802 INFO L290 TraceCheckUtils]: 99: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,802 INFO L290 TraceCheckUtils]: 100: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,803 INFO L290 TraceCheckUtils]: 101: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,803 INFO L290 TraceCheckUtils]: 102: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,803 INFO L290 TraceCheckUtils]: 103: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,804 INFO L290 TraceCheckUtils]: 104: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,804 INFO L290 TraceCheckUtils]: 105: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,804 INFO L290 TraceCheckUtils]: 106: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,804 INFO L290 TraceCheckUtils]: 107: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,805 INFO L290 TraceCheckUtils]: 108: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,805 INFO L290 TraceCheckUtils]: 109: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,805 INFO L290 TraceCheckUtils]: 110: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,805 INFO L290 TraceCheckUtils]: 111: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,806 INFO L290 TraceCheckUtils]: 112: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,806 INFO L290 TraceCheckUtils]: 113: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,806 INFO L290 TraceCheckUtils]: 114: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8971#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:11,807 INFO L290 TraceCheckUtils]: 115: Hoare triple {8971#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {8970#false} is VALID [2022-02-21 04:23:11,807 INFO L290 TraceCheckUtils]: 116: Hoare triple {8970#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,807 INFO L290 TraceCheckUtils]: 117: Hoare triple {8970#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,807 INFO L290 TraceCheckUtils]: 118: Hoare triple {8970#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,807 INFO L290 TraceCheckUtils]: 119: Hoare triple {8970#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,807 INFO L290 TraceCheckUtils]: 120: Hoare triple {8970#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,807 INFO L290 TraceCheckUtils]: 121: Hoare triple {8970#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,808 INFO L290 TraceCheckUtils]: 122: Hoare triple {8970#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,808 INFO L290 TraceCheckUtils]: 123: Hoare triple {8970#false} assume !(1 == ~T8_E~0); {8970#false} is VALID [2022-02-21 04:23:11,808 INFO L290 TraceCheckUtils]: 124: Hoare triple {8970#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,808 INFO L290 TraceCheckUtils]: 125: Hoare triple {8970#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,808 INFO L290 TraceCheckUtils]: 126: Hoare triple {8970#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,808 INFO L290 TraceCheckUtils]: 127: Hoare triple {8970#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,808 INFO L290 TraceCheckUtils]: 128: Hoare triple {8970#false} assume 1 == ~E_M~0;~E_M~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,808 INFO L290 TraceCheckUtils]: 129: Hoare triple {8970#false} assume 1 == ~E_1~0;~E_1~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,808 INFO L290 TraceCheckUtils]: 130: Hoare triple {8970#false} assume 1 == ~E_2~0;~E_2~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,809 INFO L290 TraceCheckUtils]: 131: Hoare triple {8970#false} assume !(1 == ~E_3~0); {8970#false} is VALID [2022-02-21 04:23:11,809 INFO L290 TraceCheckUtils]: 132: Hoare triple {8970#false} assume 1 == ~E_4~0;~E_4~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,809 INFO L290 TraceCheckUtils]: 133: Hoare triple {8970#false} assume 1 == ~E_5~0;~E_5~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,809 INFO L290 TraceCheckUtils]: 134: Hoare triple {8970#false} assume 1 == ~E_6~0;~E_6~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,809 INFO L290 TraceCheckUtils]: 135: Hoare triple {8970#false} assume 1 == ~E_7~0;~E_7~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,809 INFO L290 TraceCheckUtils]: 136: Hoare triple {8970#false} assume 1 == ~E_8~0;~E_8~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,809 INFO L290 TraceCheckUtils]: 137: Hoare triple {8970#false} assume 1 == ~E_9~0;~E_9~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,809 INFO L290 TraceCheckUtils]: 138: Hoare triple {8970#false} assume 1 == ~E_10~0;~E_10~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,810 INFO L290 TraceCheckUtils]: 139: Hoare triple {8970#false} assume !(1 == ~E_11~0); {8970#false} is VALID [2022-02-21 04:23:11,810 INFO L290 TraceCheckUtils]: 140: Hoare triple {8970#false} assume 1 == ~E_12~0;~E_12~0 := 2; {8970#false} is VALID [2022-02-21 04:23:11,810 INFO L290 TraceCheckUtils]: 141: Hoare triple {8970#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {8970#false} is VALID [2022-02-21 04:23:11,810 INFO L290 TraceCheckUtils]: 142: Hoare triple {8970#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {8970#false} is VALID [2022-02-21 04:23:11,810 INFO L290 TraceCheckUtils]: 143: Hoare triple {8970#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {8970#false} is VALID [2022-02-21 04:23:11,810 INFO L290 TraceCheckUtils]: 144: Hoare triple {8970#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {8970#false} is VALID [2022-02-21 04:23:11,810 INFO L290 TraceCheckUtils]: 145: Hoare triple {8970#false} assume !(0 == start_simulation_~tmp~3#1); {8970#false} is VALID [2022-02-21 04:23:11,810 INFO L290 TraceCheckUtils]: 146: Hoare triple {8970#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {8970#false} is VALID [2022-02-21 04:23:11,811 INFO L290 TraceCheckUtils]: 147: Hoare triple {8970#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {8970#false} is VALID [2022-02-21 04:23:11,811 INFO L290 TraceCheckUtils]: 148: Hoare triple {8970#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {8970#false} is VALID [2022-02-21 04:23:11,811 INFO L290 TraceCheckUtils]: 149: Hoare triple {8970#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {8970#false} is VALID [2022-02-21 04:23:11,811 INFO L290 TraceCheckUtils]: 150: Hoare triple {8970#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {8970#false} is VALID [2022-02-21 04:23:11,811 INFO L290 TraceCheckUtils]: 151: Hoare triple {8970#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8970#false} is VALID [2022-02-21 04:23:11,811 INFO L290 TraceCheckUtils]: 152: Hoare triple {8970#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {8970#false} is VALID [2022-02-21 04:23:11,811 INFO L290 TraceCheckUtils]: 153: Hoare triple {8970#false} assume !(0 != start_simulation_~tmp___0~1#1); {8970#false} is VALID [2022-02-21 04:23:11,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,814 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,814 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359019873] [2022-02-21 04:23:11,814 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359019873] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,815 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,815 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,815 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [836684843] [2022-02-21 04:23:11,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,816 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:11,816 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:11,816 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:11,817 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:11,817 INFO L87 Difference]: Start difference. First operand 1788 states and 2651 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,081 INFO L93 Difference]: Finished difference Result 1788 states and 2650 transitions. [2022-02-21 04:23:13,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:13,081 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,199 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:13,199 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2650 transitions. [2022-02-21 04:23:13,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:13,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2650 transitions. [2022-02-21 04:23:13,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:13,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:13,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2650 transitions. [2022-02-21 04:23:13,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:13,399 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2022-02-21 04:23:13,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2650 transitions. [2022-02-21 04:23:13,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:13,430 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:13,434 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2650 transitions. Second operand has 1788 states, 1788 states have (on average 1.4821029082774049) internal successors, (2650), 1787 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,438 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2650 transitions. Second operand has 1788 states, 1788 states have (on average 1.4821029082774049) internal successors, (2650), 1787 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,441 INFO L87 Difference]: Start difference. First operand 1788 states and 2650 transitions. Second operand has 1788 states, 1788 states have (on average 1.4821029082774049) internal successors, (2650), 1787 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,530 INFO L93 Difference]: Finished difference Result 1788 states and 2650 transitions. [2022-02-21 04:23:13,530 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2650 transitions. [2022-02-21 04:23:13,533 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:13,533 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:13,537 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4821029082774049) internal successors, (2650), 1787 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2650 transitions. [2022-02-21 04:23:13,553 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4821029082774049) internal successors, (2650), 1787 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2650 transitions. [2022-02-21 04:23:13,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,639 INFO L93 Difference]: Finished difference Result 1788 states and 2650 transitions. [2022-02-21 04:23:13,639 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2650 transitions. [2022-02-21 04:23:13,642 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:13,642 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:13,642 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:13,642 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:13,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4821029082774049) internal successors, (2650), 1787 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2650 transitions. [2022-02-21 04:23:13,734 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2022-02-21 04:23:13,734 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2022-02-21 04:23:13,734 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:23:13,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2650 transitions. [2022-02-21 04:23:13,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:13,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:13,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:13,742 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:13,743 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:13,743 INFO L791 eck$LassoCheckResult]: Stem: 11549#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11070#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11071#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11125#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 12464#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11558#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 11361#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10760#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10761#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11983#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12094#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12530#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12531#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11489#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11490#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12012#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11931#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11524#L1201 assume !(0 == ~M_E~0); 11525#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12371#L1206-1 assume !(0 == ~T2_E~0); 12357#L1211-1 assume !(0 == ~T3_E~0); 12358#L1216-1 assume !(0 == ~T4_E~0); 11345#L1221-1 assume !(0 == ~T5_E~0); 11346#L1226-1 assume !(0 == ~T6_E~0); 10985#L1231-1 assume !(0 == ~T7_E~0); 10986#L1236-1 assume !(0 == ~T8_E~0); 12394#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11382#L1246-1 assume !(0 == ~T10_E~0); 11383#L1251-1 assume !(0 == ~T11_E~0); 11522#L1256-1 assume !(0 == ~T12_E~0); 10771#L1261-1 assume !(0 == ~E_M~0); 10772#L1266-1 assume !(0 == ~E_1~0); 12516#L1271-1 assume !(0 == ~E_2~0); 12078#L1276-1 assume !(0 == ~E_3~0); 12079#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12026#L1286-1 assume !(0 == ~E_5~0); 11236#L1291-1 assume !(0 == ~E_6~0); 11237#L1296-1 assume !(0 == ~E_7~0); 11812#L1301-1 assume !(0 == ~E_8~0); 11813#L1306-1 assume !(0 == ~E_9~0); 12293#L1311-1 assume !(0 == ~E_10~0); 11187#L1316-1 assume !(0 == ~E_11~0); 11188#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11830#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11831#L593 assume 1 == ~m_pc~0; 11975#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11077#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12503#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12037#L1492 assume !(0 != activate_threads_~tmp~1#1); 12038#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12329#L612 assume !(1 == ~t1_pc~0); 12330#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12459#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11459#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11081#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11082#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11501#L631 assume 1 == ~t2_pc~0; 11436#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10858#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10859#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11695#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 11696#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11154#L650 assume !(1 == ~t3_pc~0); 11155#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11855#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11078#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10811#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 10812#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12004#L669 assume 1 == ~t4_pc~0; 12005#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12363#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11488#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11020#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 11021#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11245#L688 assume !(1 == ~t5_pc~0); 11036#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11037#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11955#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11889#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 11890#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12019#L707 assume 1 == ~t6_pc~0; 12428#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11665#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11666#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12426#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 11961#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11523#L726 assume 1 == ~t7_pc~0; 11422#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11121#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12162#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12436#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 10890#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10891#L745 assume !(1 == ~t8_pc~0); 11338#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11357#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12195#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11743#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11744#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12254#L764 assume 1 == ~t9_pc~0; 11521#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11363#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12040#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12487#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 10910#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10911#L783 assume !(1 == ~t10_pc~0); 10972#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10973#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11014#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11015#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 11477#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12365#L802 assume 1 == ~t11_pc~0; 12347#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10855#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10856#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11347#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 11348#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11458#L821 assume !(1 == ~t12_pc~0); 11709#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11805#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10860#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10861#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 12403#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12049#L1339 assume !(1 == ~M_E~0); 12050#L1339-2 assume !(1 == ~T1_E~0); 12438#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12439#L1349-1 assume !(1 == ~T3_E~0); 11823#L1354-1 assume !(1 == ~T4_E~0); 11824#L1359-1 assume !(1 == ~T5_E~0); 12225#L1364-1 assume !(1 == ~T6_E~0); 11288#L1369-1 assume !(1 == ~T7_E~0); 11289#L1374-1 assume !(1 == ~T8_E~0); 11826#L1379-1 assume !(1 == ~T9_E~0); 11827#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11926#L1389-1 assume !(1 == ~T11_E~0); 12397#L1394-1 assume !(1 == ~T12_E~0); 12398#L1399-1 assume !(1 == ~E_M~0); 12488#L1404-1 assume !(1 == ~E_1~0); 11387#L1409-1 assume !(1 == ~E_2~0); 11388#L1414-1 assume !(1 == ~E_3~0); 12114#L1419-1 assume !(1 == ~E_4~0); 11028#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11029#L1429-1 assume !(1 == ~E_6~0); 11839#L1434-1 assume !(1 == ~E_7~0); 12418#L1439-1 assume !(1 == ~E_8~0); 11066#L1444-1 assume !(1 == ~E_9~0); 11067#L1449-1 assume !(1 == ~E_10~0); 11441#L1454-1 assume !(1 == ~E_11~0); 11442#L1459-1 assume !(1 == ~E_12~0); 11960#L1464-1 assume { :end_inline_reset_delta_events } true; 11200#L1810-2 [2022-02-21 04:23:13,744 INFO L793 eck$LassoCheckResult]: Loop: 11200#L1810-2 assume !false; 11644#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11560#L1176 assume !false; 12122#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11692#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10898#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11448#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11449#L1003 assume !(0 != eval_~tmp~0#1); 11090#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11091#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12281#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12064#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12065#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11958#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11149#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11150#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11616#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11220#L1231-3 assume !(0 == ~T7_E~0); 11221#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11467#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12449#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12350#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12055#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11166#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11167#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11212#L1271-3 assume !(0 == ~E_2~0); 11213#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11589#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11590#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12111#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12112#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12527#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12484#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11701#L1311-3 assume !(0 == ~E_10~0); 11092#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11093#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11168#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11804#L593-42 assume 1 == ~m_pc~0; 12197#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11963#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12512#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12513#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10991#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10992#L612-42 assume !(1 == ~t1_pc~0); 11913#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12306#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12427#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11079#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11080#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11775#L631-42 assume 1 == ~t2_pc~0; 10844#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10845#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11764#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11640#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11641#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11241#L650-42 assume 1 == ~t3_pc~0; 10803#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10804#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12455#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11434#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11435#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12419#L669-42 assume !(1 == ~t4_pc~0); 10801#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 10802#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12230#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12120#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 12017#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12018#L688-42 assume 1 == ~t5_pc~0; 12109#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12310#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10942#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10943#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11019#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10833#L707-42 assume !(1 == ~t6_pc~0); 10834#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 12491#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12235#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12236#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11985#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11986#L726-42 assume 1 == ~t7_pc~0; 12263#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12289#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12290#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11704#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11705#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11808#L745-42 assume 1 == ~t8_pc~0; 11845#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11847#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11174#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10819#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10820#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11545#L764-42 assume 1 == ~t9_pc~0; 11681#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12034#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12035#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11105#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11106#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11159#L783-42 assume 1 == ~t10_pc~0; 10775#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10776#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11371#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11504#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12521#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12205#L802-42 assume 1 == ~t11_pc~0; 11306#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10917#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10918#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10868#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10869#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12045#L821-42 assume !(1 == ~t12_pc~0); 11410#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 11411#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10773#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10774#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11751#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11741#L1339-3 assume !(1 == ~M_E~0); 11742#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11893#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12003#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11420#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11421#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12014#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12510#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12417#L1374-3 assume !(1 == ~T8_E~0); 11242#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11243#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11418#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11419#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11628#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12424#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12392#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12393#L1414-3 assume !(1 == ~E_3~0); 12448#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12207#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11126#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11127#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12013#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11054#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11055#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11171#L1454-3 assume !(1 == ~E_11~0); 12008#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12009#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11667#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10964#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11224#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11225#L1829 assume !(0 == start_simulation_~tmp~3#1); 10946#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10947#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11747#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11748#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 12027#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12028#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11648#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11199#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 11200#L1810-2 [2022-02-21 04:23:13,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:13,745 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2022-02-21 04:23:13,745 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:13,745 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886941405] [2022-02-21 04:23:13,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:13,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:13,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:13,793 INFO L290 TraceCheckUtils]: 0: Hoare triple {16127#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {16127#true} is VALID [2022-02-21 04:23:13,795 INFO L290 TraceCheckUtils]: 1: Hoare triple {16127#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {16129#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:13,795 INFO L290 TraceCheckUtils]: 2: Hoare triple {16129#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {16129#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:13,795 INFO L290 TraceCheckUtils]: 3: Hoare triple {16129#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {16129#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:13,796 INFO L290 TraceCheckUtils]: 4: Hoare triple {16129#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {16129#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:13,796 INFO L290 TraceCheckUtils]: 5: Hoare triple {16129#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {16129#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:13,796 INFO L290 TraceCheckUtils]: 6: Hoare triple {16129#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,796 INFO L290 TraceCheckUtils]: 7: Hoare triple {16128#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,796 INFO L290 TraceCheckUtils]: 8: Hoare triple {16128#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,797 INFO L290 TraceCheckUtils]: 9: Hoare triple {16128#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,797 INFO L290 TraceCheckUtils]: 10: Hoare triple {16128#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,797 INFO L290 TraceCheckUtils]: 11: Hoare triple {16128#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,797 INFO L290 TraceCheckUtils]: 12: Hoare triple {16128#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,797 INFO L290 TraceCheckUtils]: 13: Hoare triple {16128#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {16128#false} is VALID [2022-02-21 04:23:13,797 INFO L290 TraceCheckUtils]: 14: Hoare triple {16128#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,797 INFO L290 TraceCheckUtils]: 15: Hoare triple {16128#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,798 INFO L290 TraceCheckUtils]: 16: Hoare triple {16128#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,798 INFO L290 TraceCheckUtils]: 17: Hoare triple {16128#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {16128#false} is VALID [2022-02-21 04:23:13,798 INFO L290 TraceCheckUtils]: 18: Hoare triple {16128#false} assume !(0 == ~M_E~0); {16128#false} is VALID [2022-02-21 04:23:13,798 INFO L290 TraceCheckUtils]: 19: Hoare triple {16128#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {16128#false} is VALID [2022-02-21 04:23:13,798 INFO L290 TraceCheckUtils]: 20: Hoare triple {16128#false} assume !(0 == ~T2_E~0); {16128#false} is VALID [2022-02-21 04:23:13,798 INFO L290 TraceCheckUtils]: 21: Hoare triple {16128#false} assume !(0 == ~T3_E~0); {16128#false} is VALID [2022-02-21 04:23:13,799 INFO L290 TraceCheckUtils]: 22: Hoare triple {16128#false} assume !(0 == ~T4_E~0); {16128#false} is VALID [2022-02-21 04:23:13,799 INFO L290 TraceCheckUtils]: 23: Hoare triple {16128#false} assume !(0 == ~T5_E~0); {16128#false} is VALID [2022-02-21 04:23:13,799 INFO L290 TraceCheckUtils]: 24: Hoare triple {16128#false} assume !(0 == ~T6_E~0); {16128#false} is VALID [2022-02-21 04:23:13,799 INFO L290 TraceCheckUtils]: 25: Hoare triple {16128#false} assume !(0 == ~T7_E~0); {16128#false} is VALID [2022-02-21 04:23:13,799 INFO L290 TraceCheckUtils]: 26: Hoare triple {16128#false} assume !(0 == ~T8_E~0); {16128#false} is VALID [2022-02-21 04:23:13,799 INFO L290 TraceCheckUtils]: 27: Hoare triple {16128#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {16128#false} is VALID [2022-02-21 04:23:13,799 INFO L290 TraceCheckUtils]: 28: Hoare triple {16128#false} assume !(0 == ~T10_E~0); {16128#false} is VALID [2022-02-21 04:23:13,800 INFO L290 TraceCheckUtils]: 29: Hoare triple {16128#false} assume !(0 == ~T11_E~0); {16128#false} is VALID [2022-02-21 04:23:13,800 INFO L290 TraceCheckUtils]: 30: Hoare triple {16128#false} assume !(0 == ~T12_E~0); {16128#false} is VALID [2022-02-21 04:23:13,800 INFO L290 TraceCheckUtils]: 31: Hoare triple {16128#false} assume !(0 == ~E_M~0); {16128#false} is VALID [2022-02-21 04:23:13,800 INFO L290 TraceCheckUtils]: 32: Hoare triple {16128#false} assume !(0 == ~E_1~0); {16128#false} is VALID [2022-02-21 04:23:13,800 INFO L290 TraceCheckUtils]: 33: Hoare triple {16128#false} assume !(0 == ~E_2~0); {16128#false} is VALID [2022-02-21 04:23:13,800 INFO L290 TraceCheckUtils]: 34: Hoare triple {16128#false} assume !(0 == ~E_3~0); {16128#false} is VALID [2022-02-21 04:23:13,800 INFO L290 TraceCheckUtils]: 35: Hoare triple {16128#false} assume 0 == ~E_4~0;~E_4~0 := 1; {16128#false} is VALID [2022-02-21 04:23:13,800 INFO L290 TraceCheckUtils]: 36: Hoare triple {16128#false} assume !(0 == ~E_5~0); {16128#false} is VALID [2022-02-21 04:23:13,801 INFO L290 TraceCheckUtils]: 37: Hoare triple {16128#false} assume !(0 == ~E_6~0); {16128#false} is VALID [2022-02-21 04:23:13,801 INFO L290 TraceCheckUtils]: 38: Hoare triple {16128#false} assume !(0 == ~E_7~0); {16128#false} is VALID [2022-02-21 04:23:13,801 INFO L290 TraceCheckUtils]: 39: Hoare triple {16128#false} assume !(0 == ~E_8~0); {16128#false} is VALID [2022-02-21 04:23:13,801 INFO L290 TraceCheckUtils]: 40: Hoare triple {16128#false} assume !(0 == ~E_9~0); {16128#false} is VALID [2022-02-21 04:23:13,801 INFO L290 TraceCheckUtils]: 41: Hoare triple {16128#false} assume !(0 == ~E_10~0); {16128#false} is VALID [2022-02-21 04:23:13,801 INFO L290 TraceCheckUtils]: 42: Hoare triple {16128#false} assume !(0 == ~E_11~0); {16128#false} is VALID [2022-02-21 04:23:13,801 INFO L290 TraceCheckUtils]: 43: Hoare triple {16128#false} assume 0 == ~E_12~0;~E_12~0 := 1; {16128#false} is VALID [2022-02-21 04:23:13,802 INFO L290 TraceCheckUtils]: 44: Hoare triple {16128#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16128#false} is VALID [2022-02-21 04:23:13,802 INFO L290 TraceCheckUtils]: 45: Hoare triple {16128#false} assume 1 == ~m_pc~0; {16128#false} is VALID [2022-02-21 04:23:13,802 INFO L290 TraceCheckUtils]: 46: Hoare triple {16128#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {16128#false} is VALID [2022-02-21 04:23:13,802 INFO L290 TraceCheckUtils]: 47: Hoare triple {16128#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16128#false} is VALID [2022-02-21 04:23:13,802 INFO L290 TraceCheckUtils]: 48: Hoare triple {16128#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {16128#false} is VALID [2022-02-21 04:23:13,802 INFO L290 TraceCheckUtils]: 49: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp~1#1); {16128#false} is VALID [2022-02-21 04:23:13,802 INFO L290 TraceCheckUtils]: 50: Hoare triple {16128#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16128#false} is VALID [2022-02-21 04:23:13,803 INFO L290 TraceCheckUtils]: 51: Hoare triple {16128#false} assume !(1 == ~t1_pc~0); {16128#false} is VALID [2022-02-21 04:23:13,803 INFO L290 TraceCheckUtils]: 52: Hoare triple {16128#false} is_transmit1_triggered_~__retres1~1#1 := 0; {16128#false} is VALID [2022-02-21 04:23:13,803 INFO L290 TraceCheckUtils]: 53: Hoare triple {16128#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16128#false} is VALID [2022-02-21 04:23:13,803 INFO L290 TraceCheckUtils]: 54: Hoare triple {16128#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {16128#false} is VALID [2022-02-21 04:23:13,803 INFO L290 TraceCheckUtils]: 55: Hoare triple {16128#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {16128#false} is VALID [2022-02-21 04:23:13,803 INFO L290 TraceCheckUtils]: 56: Hoare triple {16128#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16128#false} is VALID [2022-02-21 04:23:13,804 INFO L290 TraceCheckUtils]: 57: Hoare triple {16128#false} assume 1 == ~t2_pc~0; {16128#false} is VALID [2022-02-21 04:23:13,804 INFO L290 TraceCheckUtils]: 58: Hoare triple {16128#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {16128#false} is VALID [2022-02-21 04:23:13,804 INFO L290 TraceCheckUtils]: 59: Hoare triple {16128#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16128#false} is VALID [2022-02-21 04:23:13,804 INFO L290 TraceCheckUtils]: 60: Hoare triple {16128#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {16128#false} is VALID [2022-02-21 04:23:13,804 INFO L290 TraceCheckUtils]: 61: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp___1~0#1); {16128#false} is VALID [2022-02-21 04:23:13,804 INFO L290 TraceCheckUtils]: 62: Hoare triple {16128#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16128#false} is VALID [2022-02-21 04:23:13,804 INFO L290 TraceCheckUtils]: 63: Hoare triple {16128#false} assume !(1 == ~t3_pc~0); {16128#false} is VALID [2022-02-21 04:23:13,804 INFO L290 TraceCheckUtils]: 64: Hoare triple {16128#false} is_transmit3_triggered_~__retres1~3#1 := 0; {16128#false} is VALID [2022-02-21 04:23:13,805 INFO L290 TraceCheckUtils]: 65: Hoare triple {16128#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16128#false} is VALID [2022-02-21 04:23:13,805 INFO L290 TraceCheckUtils]: 66: Hoare triple {16128#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {16128#false} is VALID [2022-02-21 04:23:13,805 INFO L290 TraceCheckUtils]: 67: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp___2~0#1); {16128#false} is VALID [2022-02-21 04:23:13,805 INFO L290 TraceCheckUtils]: 68: Hoare triple {16128#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16128#false} is VALID [2022-02-21 04:23:13,805 INFO L290 TraceCheckUtils]: 69: Hoare triple {16128#false} assume 1 == ~t4_pc~0; {16128#false} is VALID [2022-02-21 04:23:13,805 INFO L290 TraceCheckUtils]: 70: Hoare triple {16128#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {16128#false} is VALID [2022-02-21 04:23:13,805 INFO L290 TraceCheckUtils]: 71: Hoare triple {16128#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16128#false} is VALID [2022-02-21 04:23:13,806 INFO L290 TraceCheckUtils]: 72: Hoare triple {16128#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {16128#false} is VALID [2022-02-21 04:23:13,806 INFO L290 TraceCheckUtils]: 73: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp___3~0#1); {16128#false} is VALID [2022-02-21 04:23:13,806 INFO L290 TraceCheckUtils]: 74: Hoare triple {16128#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {16128#false} is VALID [2022-02-21 04:23:13,806 INFO L290 TraceCheckUtils]: 75: Hoare triple {16128#false} assume !(1 == ~t5_pc~0); {16128#false} is VALID [2022-02-21 04:23:13,806 INFO L290 TraceCheckUtils]: 76: Hoare triple {16128#false} is_transmit5_triggered_~__retres1~5#1 := 0; {16128#false} is VALID [2022-02-21 04:23:13,806 INFO L290 TraceCheckUtils]: 77: Hoare triple {16128#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {16128#false} is VALID [2022-02-21 04:23:13,806 INFO L290 TraceCheckUtils]: 78: Hoare triple {16128#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {16128#false} is VALID [2022-02-21 04:23:13,807 INFO L290 TraceCheckUtils]: 79: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp___4~0#1); {16128#false} is VALID [2022-02-21 04:23:13,807 INFO L290 TraceCheckUtils]: 80: Hoare triple {16128#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {16128#false} is VALID [2022-02-21 04:23:13,807 INFO L290 TraceCheckUtils]: 81: Hoare triple {16128#false} assume 1 == ~t6_pc~0; {16128#false} is VALID [2022-02-21 04:23:13,807 INFO L290 TraceCheckUtils]: 82: Hoare triple {16128#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {16128#false} is VALID [2022-02-21 04:23:13,807 INFO L290 TraceCheckUtils]: 83: Hoare triple {16128#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {16128#false} is VALID [2022-02-21 04:23:13,807 INFO L290 TraceCheckUtils]: 84: Hoare triple {16128#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {16128#false} is VALID [2022-02-21 04:23:13,807 INFO L290 TraceCheckUtils]: 85: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp___5~0#1); {16128#false} is VALID [2022-02-21 04:23:13,808 INFO L290 TraceCheckUtils]: 86: Hoare triple {16128#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {16128#false} is VALID [2022-02-21 04:23:13,808 INFO L290 TraceCheckUtils]: 87: Hoare triple {16128#false} assume 1 == ~t7_pc~0; {16128#false} is VALID [2022-02-21 04:23:13,808 INFO L290 TraceCheckUtils]: 88: Hoare triple {16128#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {16128#false} is VALID [2022-02-21 04:23:13,808 INFO L290 TraceCheckUtils]: 89: Hoare triple {16128#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {16128#false} is VALID [2022-02-21 04:23:13,808 INFO L290 TraceCheckUtils]: 90: Hoare triple {16128#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {16128#false} is VALID [2022-02-21 04:23:13,808 INFO L290 TraceCheckUtils]: 91: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp___6~0#1); {16128#false} is VALID [2022-02-21 04:23:13,808 INFO L290 TraceCheckUtils]: 92: Hoare triple {16128#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {16128#false} is VALID [2022-02-21 04:23:13,809 INFO L290 TraceCheckUtils]: 93: Hoare triple {16128#false} assume !(1 == ~t8_pc~0); {16128#false} is VALID [2022-02-21 04:23:13,809 INFO L290 TraceCheckUtils]: 94: Hoare triple {16128#false} is_transmit8_triggered_~__retres1~8#1 := 0; {16128#false} is VALID [2022-02-21 04:23:13,809 INFO L290 TraceCheckUtils]: 95: Hoare triple {16128#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {16128#false} is VALID [2022-02-21 04:23:13,809 INFO L290 TraceCheckUtils]: 96: Hoare triple {16128#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {16128#false} is VALID [2022-02-21 04:23:13,809 INFO L290 TraceCheckUtils]: 97: Hoare triple {16128#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {16128#false} is VALID [2022-02-21 04:23:13,809 INFO L290 TraceCheckUtils]: 98: Hoare triple {16128#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {16128#false} is VALID [2022-02-21 04:23:13,809 INFO L290 TraceCheckUtils]: 99: Hoare triple {16128#false} assume 1 == ~t9_pc~0; {16128#false} is VALID [2022-02-21 04:23:13,809 INFO L290 TraceCheckUtils]: 100: Hoare triple {16128#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {16128#false} is VALID [2022-02-21 04:23:13,810 INFO L290 TraceCheckUtils]: 101: Hoare triple {16128#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {16128#false} is VALID [2022-02-21 04:23:13,810 INFO L290 TraceCheckUtils]: 102: Hoare triple {16128#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {16128#false} is VALID [2022-02-21 04:23:13,810 INFO L290 TraceCheckUtils]: 103: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp___8~0#1); {16128#false} is VALID [2022-02-21 04:23:13,810 INFO L290 TraceCheckUtils]: 104: Hoare triple {16128#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {16128#false} is VALID [2022-02-21 04:23:13,810 INFO L290 TraceCheckUtils]: 105: Hoare triple {16128#false} assume !(1 == ~t10_pc~0); {16128#false} is VALID [2022-02-21 04:23:13,810 INFO L290 TraceCheckUtils]: 106: Hoare triple {16128#false} is_transmit10_triggered_~__retres1~10#1 := 0; {16128#false} is VALID [2022-02-21 04:23:13,810 INFO L290 TraceCheckUtils]: 107: Hoare triple {16128#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {16128#false} is VALID [2022-02-21 04:23:13,811 INFO L290 TraceCheckUtils]: 108: Hoare triple {16128#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {16128#false} is VALID [2022-02-21 04:23:13,811 INFO L290 TraceCheckUtils]: 109: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp___9~0#1); {16128#false} is VALID [2022-02-21 04:23:13,811 INFO L290 TraceCheckUtils]: 110: Hoare triple {16128#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {16128#false} is VALID [2022-02-21 04:23:13,811 INFO L290 TraceCheckUtils]: 111: Hoare triple {16128#false} assume 1 == ~t11_pc~0; {16128#false} is VALID [2022-02-21 04:23:13,811 INFO L290 TraceCheckUtils]: 112: Hoare triple {16128#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {16128#false} is VALID [2022-02-21 04:23:13,811 INFO L290 TraceCheckUtils]: 113: Hoare triple {16128#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {16128#false} is VALID [2022-02-21 04:23:13,811 INFO L290 TraceCheckUtils]: 114: Hoare triple {16128#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {16128#false} is VALID [2022-02-21 04:23:13,812 INFO L290 TraceCheckUtils]: 115: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp___10~0#1); {16128#false} is VALID [2022-02-21 04:23:13,812 INFO L290 TraceCheckUtils]: 116: Hoare triple {16128#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {16128#false} is VALID [2022-02-21 04:23:13,812 INFO L290 TraceCheckUtils]: 117: Hoare triple {16128#false} assume !(1 == ~t12_pc~0); {16128#false} is VALID [2022-02-21 04:23:13,812 INFO L290 TraceCheckUtils]: 118: Hoare triple {16128#false} is_transmit12_triggered_~__retres1~12#1 := 0; {16128#false} is VALID [2022-02-21 04:23:13,812 INFO L290 TraceCheckUtils]: 119: Hoare triple {16128#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {16128#false} is VALID [2022-02-21 04:23:13,812 INFO L290 TraceCheckUtils]: 120: Hoare triple {16128#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {16128#false} is VALID [2022-02-21 04:23:13,812 INFO L290 TraceCheckUtils]: 121: Hoare triple {16128#false} assume !(0 != activate_threads_~tmp___11~0#1); {16128#false} is VALID [2022-02-21 04:23:13,813 INFO L290 TraceCheckUtils]: 122: Hoare triple {16128#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16128#false} is VALID [2022-02-21 04:23:13,813 INFO L290 TraceCheckUtils]: 123: Hoare triple {16128#false} assume !(1 == ~M_E~0); {16128#false} is VALID [2022-02-21 04:23:13,813 INFO L290 TraceCheckUtils]: 124: Hoare triple {16128#false} assume !(1 == ~T1_E~0); {16128#false} is VALID [2022-02-21 04:23:13,813 INFO L290 TraceCheckUtils]: 125: Hoare triple {16128#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,813 INFO L290 TraceCheckUtils]: 126: Hoare triple {16128#false} assume !(1 == ~T3_E~0); {16128#false} is VALID [2022-02-21 04:23:13,813 INFO L290 TraceCheckUtils]: 127: Hoare triple {16128#false} assume !(1 == ~T4_E~0); {16128#false} is VALID [2022-02-21 04:23:13,814 INFO L290 TraceCheckUtils]: 128: Hoare triple {16128#false} assume !(1 == ~T5_E~0); {16128#false} is VALID [2022-02-21 04:23:13,826 INFO L290 TraceCheckUtils]: 129: Hoare triple {16128#false} assume !(1 == ~T6_E~0); {16128#false} is VALID [2022-02-21 04:23:13,836 INFO L290 TraceCheckUtils]: 130: Hoare triple {16128#false} assume !(1 == ~T7_E~0); {16128#false} is VALID [2022-02-21 04:23:13,837 INFO L290 TraceCheckUtils]: 131: Hoare triple {16128#false} assume !(1 == ~T8_E~0); {16128#false} is VALID [2022-02-21 04:23:13,837 INFO L290 TraceCheckUtils]: 132: Hoare triple {16128#false} assume !(1 == ~T9_E~0); {16128#false} is VALID [2022-02-21 04:23:13,837 INFO L290 TraceCheckUtils]: 133: Hoare triple {16128#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,837 INFO L290 TraceCheckUtils]: 134: Hoare triple {16128#false} assume !(1 == ~T11_E~0); {16128#false} is VALID [2022-02-21 04:23:13,837 INFO L290 TraceCheckUtils]: 135: Hoare triple {16128#false} assume !(1 == ~T12_E~0); {16128#false} is VALID [2022-02-21 04:23:13,837 INFO L290 TraceCheckUtils]: 136: Hoare triple {16128#false} assume !(1 == ~E_M~0); {16128#false} is VALID [2022-02-21 04:23:13,838 INFO L290 TraceCheckUtils]: 137: Hoare triple {16128#false} assume !(1 == ~E_1~0); {16128#false} is VALID [2022-02-21 04:23:13,838 INFO L290 TraceCheckUtils]: 138: Hoare triple {16128#false} assume !(1 == ~E_2~0); {16128#false} is VALID [2022-02-21 04:23:13,838 INFO L290 TraceCheckUtils]: 139: Hoare triple {16128#false} assume !(1 == ~E_3~0); {16128#false} is VALID [2022-02-21 04:23:13,838 INFO L290 TraceCheckUtils]: 140: Hoare triple {16128#false} assume !(1 == ~E_4~0); {16128#false} is VALID [2022-02-21 04:23:13,838 INFO L290 TraceCheckUtils]: 141: Hoare triple {16128#false} assume 1 == ~E_5~0;~E_5~0 := 2; {16128#false} is VALID [2022-02-21 04:23:13,838 INFO L290 TraceCheckUtils]: 142: Hoare triple {16128#false} assume !(1 == ~E_6~0); {16128#false} is VALID [2022-02-21 04:23:13,838 INFO L290 TraceCheckUtils]: 143: Hoare triple {16128#false} assume !(1 == ~E_7~0); {16128#false} is VALID [2022-02-21 04:23:13,839 INFO L290 TraceCheckUtils]: 144: Hoare triple {16128#false} assume !(1 == ~E_8~0); {16128#false} is VALID [2022-02-21 04:23:13,839 INFO L290 TraceCheckUtils]: 145: Hoare triple {16128#false} assume !(1 == ~E_9~0); {16128#false} is VALID [2022-02-21 04:23:13,839 INFO L290 TraceCheckUtils]: 146: Hoare triple {16128#false} assume !(1 == ~E_10~0); {16128#false} is VALID [2022-02-21 04:23:13,839 INFO L290 TraceCheckUtils]: 147: Hoare triple {16128#false} assume !(1 == ~E_11~0); {16128#false} is VALID [2022-02-21 04:23:13,839 INFO L290 TraceCheckUtils]: 148: Hoare triple {16128#false} assume !(1 == ~E_12~0); {16128#false} is VALID [2022-02-21 04:23:13,839 INFO L290 TraceCheckUtils]: 149: Hoare triple {16128#false} assume { :end_inline_reset_delta_events } true; {16128#false} is VALID [2022-02-21 04:23:13,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:13,840 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:13,840 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886941405] [2022-02-21 04:23:13,840 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886941405] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:13,840 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:13,841 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:13,841 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [159610041] [2022-02-21 04:23:13,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:13,841 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:13,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:13,842 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 1 times [2022-02-21 04:23:13,842 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:13,842 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092163715] [2022-02-21 04:23:13,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:13,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:13,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:13,913 INFO L290 TraceCheckUtils]: 0: Hoare triple {16130#true} assume !false; {16130#true} is VALID [2022-02-21 04:23:13,913 INFO L290 TraceCheckUtils]: 1: Hoare triple {16130#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {16130#true} is VALID [2022-02-21 04:23:13,914 INFO L290 TraceCheckUtils]: 2: Hoare triple {16130#true} assume !false; {16130#true} is VALID [2022-02-21 04:23:13,914 INFO L290 TraceCheckUtils]: 3: Hoare triple {16130#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {16130#true} is VALID [2022-02-21 04:23:13,914 INFO L290 TraceCheckUtils]: 4: Hoare triple {16130#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {16130#true} is VALID [2022-02-21 04:23:13,914 INFO L290 TraceCheckUtils]: 5: Hoare triple {16130#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {16130#true} is VALID [2022-02-21 04:23:13,914 INFO L290 TraceCheckUtils]: 6: Hoare triple {16130#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {16130#true} is VALID [2022-02-21 04:23:13,914 INFO L290 TraceCheckUtils]: 7: Hoare triple {16130#true} assume !(0 != eval_~tmp~0#1); {16130#true} is VALID [2022-02-21 04:23:13,914 INFO L290 TraceCheckUtils]: 8: Hoare triple {16130#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {16130#true} is VALID [2022-02-21 04:23:13,914 INFO L290 TraceCheckUtils]: 9: Hoare triple {16130#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {16130#true} is VALID [2022-02-21 04:23:13,915 INFO L290 TraceCheckUtils]: 10: Hoare triple {16130#true} assume 0 == ~M_E~0;~M_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,915 INFO L290 TraceCheckUtils]: 11: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,915 INFO L290 TraceCheckUtils]: 12: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,916 INFO L290 TraceCheckUtils]: 13: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,916 INFO L290 TraceCheckUtils]: 14: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,916 INFO L290 TraceCheckUtils]: 15: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,916 INFO L290 TraceCheckUtils]: 16: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,917 INFO L290 TraceCheckUtils]: 17: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,917 INFO L290 TraceCheckUtils]: 18: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,917 INFO L290 TraceCheckUtils]: 19: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,918 INFO L290 TraceCheckUtils]: 20: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,918 INFO L290 TraceCheckUtils]: 21: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,918 INFO L290 TraceCheckUtils]: 22: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,918 INFO L290 TraceCheckUtils]: 23: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,919 INFO L290 TraceCheckUtils]: 24: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,919 INFO L290 TraceCheckUtils]: 25: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,919 INFO L290 TraceCheckUtils]: 26: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,920 INFO L290 TraceCheckUtils]: 27: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,920 INFO L290 TraceCheckUtils]: 28: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,920 INFO L290 TraceCheckUtils]: 29: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,920 INFO L290 TraceCheckUtils]: 30: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,921 INFO L290 TraceCheckUtils]: 31: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,921 INFO L290 TraceCheckUtils]: 32: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,921 INFO L290 TraceCheckUtils]: 33: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,921 INFO L290 TraceCheckUtils]: 34: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,922 INFO L290 TraceCheckUtils]: 35: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,922 INFO L290 TraceCheckUtils]: 36: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,922 INFO L290 TraceCheckUtils]: 37: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,923 INFO L290 TraceCheckUtils]: 38: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,923 INFO L290 TraceCheckUtils]: 39: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,923 INFO L290 TraceCheckUtils]: 40: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,923 INFO L290 TraceCheckUtils]: 41: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,924 INFO L290 TraceCheckUtils]: 42: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,924 INFO L290 TraceCheckUtils]: 43: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,924 INFO L290 TraceCheckUtils]: 44: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,925 INFO L290 TraceCheckUtils]: 45: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,925 INFO L290 TraceCheckUtils]: 46: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,925 INFO L290 TraceCheckUtils]: 47: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,925 INFO L290 TraceCheckUtils]: 48: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,926 INFO L290 TraceCheckUtils]: 49: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,927 INFO L290 TraceCheckUtils]: 50: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,927 INFO L290 TraceCheckUtils]: 51: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,927 INFO L290 TraceCheckUtils]: 52: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,928 INFO L290 TraceCheckUtils]: 53: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,928 INFO L290 TraceCheckUtils]: 54: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,928 INFO L290 TraceCheckUtils]: 55: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,929 INFO L290 TraceCheckUtils]: 56: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,929 INFO L290 TraceCheckUtils]: 57: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,929 INFO L290 TraceCheckUtils]: 58: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,929 INFO L290 TraceCheckUtils]: 59: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,930 INFO L290 TraceCheckUtils]: 60: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,930 INFO L290 TraceCheckUtils]: 61: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,930 INFO L290 TraceCheckUtils]: 62: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,931 INFO L290 TraceCheckUtils]: 63: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,931 INFO L290 TraceCheckUtils]: 64: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,931 INFO L290 TraceCheckUtils]: 65: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,931 INFO L290 TraceCheckUtils]: 66: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,932 INFO L290 TraceCheckUtils]: 67: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,932 INFO L290 TraceCheckUtils]: 68: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,932 INFO L290 TraceCheckUtils]: 69: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,933 INFO L290 TraceCheckUtils]: 70: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,933 INFO L290 TraceCheckUtils]: 71: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,933 INFO L290 TraceCheckUtils]: 72: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,933 INFO L290 TraceCheckUtils]: 73: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,934 INFO L290 TraceCheckUtils]: 74: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,934 INFO L290 TraceCheckUtils]: 75: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,934 INFO L290 TraceCheckUtils]: 76: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,935 INFO L290 TraceCheckUtils]: 77: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,935 INFO L290 TraceCheckUtils]: 78: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,935 INFO L290 TraceCheckUtils]: 79: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,935 INFO L290 TraceCheckUtils]: 80: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,936 INFO L290 TraceCheckUtils]: 81: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,936 INFO L290 TraceCheckUtils]: 82: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,936 INFO L290 TraceCheckUtils]: 83: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,936 INFO L290 TraceCheckUtils]: 84: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,937 INFO L290 TraceCheckUtils]: 85: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,937 INFO L290 TraceCheckUtils]: 86: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,937 INFO L290 TraceCheckUtils]: 87: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,938 INFO L290 TraceCheckUtils]: 88: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,938 INFO L290 TraceCheckUtils]: 89: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,938 INFO L290 TraceCheckUtils]: 90: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,938 INFO L290 TraceCheckUtils]: 91: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,939 INFO L290 TraceCheckUtils]: 92: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,939 INFO L290 TraceCheckUtils]: 93: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,939 INFO L290 TraceCheckUtils]: 94: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,940 INFO L290 TraceCheckUtils]: 95: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,940 INFO L290 TraceCheckUtils]: 96: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,940 INFO L290 TraceCheckUtils]: 97: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,940 INFO L290 TraceCheckUtils]: 98: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,941 INFO L290 TraceCheckUtils]: 99: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,941 INFO L290 TraceCheckUtils]: 100: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,941 INFO L290 TraceCheckUtils]: 101: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,941 INFO L290 TraceCheckUtils]: 102: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,942 INFO L290 TraceCheckUtils]: 103: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,942 INFO L290 TraceCheckUtils]: 104: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,942 INFO L290 TraceCheckUtils]: 105: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,943 INFO L290 TraceCheckUtils]: 106: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,943 INFO L290 TraceCheckUtils]: 107: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,943 INFO L290 TraceCheckUtils]: 108: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,943 INFO L290 TraceCheckUtils]: 109: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,944 INFO L290 TraceCheckUtils]: 110: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,944 INFO L290 TraceCheckUtils]: 111: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,944 INFO L290 TraceCheckUtils]: 112: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,944 INFO L290 TraceCheckUtils]: 113: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,945 INFO L290 TraceCheckUtils]: 114: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16132#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:13,945 INFO L290 TraceCheckUtils]: 115: Hoare triple {16132#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {16131#false} is VALID [2022-02-21 04:23:13,945 INFO L290 TraceCheckUtils]: 116: Hoare triple {16131#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,945 INFO L290 TraceCheckUtils]: 117: Hoare triple {16131#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,945 INFO L290 TraceCheckUtils]: 118: Hoare triple {16131#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,946 INFO L290 TraceCheckUtils]: 119: Hoare triple {16131#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,946 INFO L290 TraceCheckUtils]: 120: Hoare triple {16131#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,946 INFO L290 TraceCheckUtils]: 121: Hoare triple {16131#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,946 INFO L290 TraceCheckUtils]: 122: Hoare triple {16131#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,946 INFO L290 TraceCheckUtils]: 123: Hoare triple {16131#false} assume !(1 == ~T8_E~0); {16131#false} is VALID [2022-02-21 04:23:13,946 INFO L290 TraceCheckUtils]: 124: Hoare triple {16131#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,946 INFO L290 TraceCheckUtils]: 125: Hoare triple {16131#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,946 INFO L290 TraceCheckUtils]: 126: Hoare triple {16131#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,947 INFO L290 TraceCheckUtils]: 127: Hoare triple {16131#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,947 INFO L290 TraceCheckUtils]: 128: Hoare triple {16131#false} assume 1 == ~E_M~0;~E_M~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,947 INFO L290 TraceCheckUtils]: 129: Hoare triple {16131#false} assume 1 == ~E_1~0;~E_1~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,947 INFO L290 TraceCheckUtils]: 130: Hoare triple {16131#false} assume 1 == ~E_2~0;~E_2~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,947 INFO L290 TraceCheckUtils]: 131: Hoare triple {16131#false} assume !(1 == ~E_3~0); {16131#false} is VALID [2022-02-21 04:23:13,947 INFO L290 TraceCheckUtils]: 132: Hoare triple {16131#false} assume 1 == ~E_4~0;~E_4~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,947 INFO L290 TraceCheckUtils]: 133: Hoare triple {16131#false} assume 1 == ~E_5~0;~E_5~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,947 INFO L290 TraceCheckUtils]: 134: Hoare triple {16131#false} assume 1 == ~E_6~0;~E_6~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,948 INFO L290 TraceCheckUtils]: 135: Hoare triple {16131#false} assume 1 == ~E_7~0;~E_7~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,948 INFO L290 TraceCheckUtils]: 136: Hoare triple {16131#false} assume 1 == ~E_8~0;~E_8~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,948 INFO L290 TraceCheckUtils]: 137: Hoare triple {16131#false} assume 1 == ~E_9~0;~E_9~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,948 INFO L290 TraceCheckUtils]: 138: Hoare triple {16131#false} assume 1 == ~E_10~0;~E_10~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,948 INFO L290 TraceCheckUtils]: 139: Hoare triple {16131#false} assume !(1 == ~E_11~0); {16131#false} is VALID [2022-02-21 04:23:13,948 INFO L290 TraceCheckUtils]: 140: Hoare triple {16131#false} assume 1 == ~E_12~0;~E_12~0 := 2; {16131#false} is VALID [2022-02-21 04:23:13,948 INFO L290 TraceCheckUtils]: 141: Hoare triple {16131#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {16131#false} is VALID [2022-02-21 04:23:13,948 INFO L290 TraceCheckUtils]: 142: Hoare triple {16131#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {16131#false} is VALID [2022-02-21 04:23:13,949 INFO L290 TraceCheckUtils]: 143: Hoare triple {16131#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {16131#false} is VALID [2022-02-21 04:23:13,949 INFO L290 TraceCheckUtils]: 144: Hoare triple {16131#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {16131#false} is VALID [2022-02-21 04:23:13,949 INFO L290 TraceCheckUtils]: 145: Hoare triple {16131#false} assume !(0 == start_simulation_~tmp~3#1); {16131#false} is VALID [2022-02-21 04:23:13,949 INFO L290 TraceCheckUtils]: 146: Hoare triple {16131#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {16131#false} is VALID [2022-02-21 04:23:13,949 INFO L290 TraceCheckUtils]: 147: Hoare triple {16131#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {16131#false} is VALID [2022-02-21 04:23:13,949 INFO L290 TraceCheckUtils]: 148: Hoare triple {16131#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {16131#false} is VALID [2022-02-21 04:23:13,949 INFO L290 TraceCheckUtils]: 149: Hoare triple {16131#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {16131#false} is VALID [2022-02-21 04:23:13,949 INFO L290 TraceCheckUtils]: 150: Hoare triple {16131#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {16131#false} is VALID [2022-02-21 04:23:13,950 INFO L290 TraceCheckUtils]: 151: Hoare triple {16131#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {16131#false} is VALID [2022-02-21 04:23:13,950 INFO L290 TraceCheckUtils]: 152: Hoare triple {16131#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {16131#false} is VALID [2022-02-21 04:23:13,950 INFO L290 TraceCheckUtils]: 153: Hoare triple {16131#false} assume !(0 != start_simulation_~tmp___0~1#1); {16131#false} is VALID [2022-02-21 04:23:13,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:13,951 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:13,951 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1092163715] [2022-02-21 04:23:13,952 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1092163715] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:13,952 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:13,952 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:13,952 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984749785] [2022-02-21 04:23:13,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:13,952 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:13,953 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:13,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:13,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:13,954 INFO L87 Difference]: Start difference. First operand 1788 states and 2650 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:15,278 INFO L93 Difference]: Finished difference Result 1788 states and 2649 transitions. [2022-02-21 04:23:15,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:15,279 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,365 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:15,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2649 transitions. [2022-02-21 04:23:15,436 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:15,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2649 transitions. [2022-02-21 04:23:15,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:15,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:15,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2649 transitions. [2022-02-21 04:23:15,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:15,510 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2022-02-21 04:23:15,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2649 transitions. [2022-02-21 04:23:15,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:15,528 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:15,530 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2649 transitions. Second operand has 1788 states, 1788 states have (on average 1.4815436241610738) internal successors, (2649), 1787 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,532 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2649 transitions. Second operand has 1788 states, 1788 states have (on average 1.4815436241610738) internal successors, (2649), 1787 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,534 INFO L87 Difference]: Start difference. First operand 1788 states and 2649 transitions. Second operand has 1788 states, 1788 states have (on average 1.4815436241610738) internal successors, (2649), 1787 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:15,604 INFO L93 Difference]: Finished difference Result 1788 states and 2649 transitions. [2022-02-21 04:23:15,604 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2649 transitions. [2022-02-21 04:23:15,607 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:15,607 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:15,609 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4815436241610738) internal successors, (2649), 1787 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2649 transitions. [2022-02-21 04:23:15,611 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4815436241610738) internal successors, (2649), 1787 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2649 transitions. [2022-02-21 04:23:15,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:15,681 INFO L93 Difference]: Finished difference Result 1788 states and 2649 transitions. [2022-02-21 04:23:15,681 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2649 transitions. [2022-02-21 04:23:15,684 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:15,684 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:15,684 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:15,684 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:15,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4815436241610738) internal successors, (2649), 1787 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2649 transitions. [2022-02-21 04:23:15,756 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2022-02-21 04:23:15,756 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2022-02-21 04:23:15,756 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:23:15,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2649 transitions. [2022-02-21 04:23:15,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:15,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:15,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:15,762 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:15,762 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:15,762 INFO L791 eck$LassoCheckResult]: Stem: 18710#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18711#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18231#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18232#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18286#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 19625#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18719#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18522#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 17921#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17922#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19144#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19257#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19691#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19692#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18650#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18651#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19173#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19092#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18685#L1201 assume !(0 == ~M_E~0); 18686#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19532#L1206-1 assume !(0 == ~T2_E~0); 19518#L1211-1 assume !(0 == ~T3_E~0); 19519#L1216-1 assume !(0 == ~T4_E~0); 18507#L1221-1 assume !(0 == ~T5_E~0); 18508#L1226-1 assume !(0 == ~T6_E~0); 18146#L1231-1 assume !(0 == ~T7_E~0); 18147#L1236-1 assume !(0 == ~T8_E~0); 19555#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18546#L1246-1 assume !(0 == ~T10_E~0); 18547#L1251-1 assume !(0 == ~T11_E~0); 18683#L1256-1 assume !(0 == ~T12_E~0); 17934#L1261-1 assume !(0 == ~E_M~0); 17935#L1266-1 assume !(0 == ~E_1~0); 19677#L1271-1 assume !(0 == ~E_2~0); 19239#L1276-1 assume !(0 == ~E_3~0); 19240#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19187#L1286-1 assume !(0 == ~E_5~0); 18397#L1291-1 assume !(0 == ~E_6~0); 18398#L1296-1 assume !(0 == ~E_7~0); 18973#L1301-1 assume !(0 == ~E_8~0); 18974#L1306-1 assume !(0 == ~E_9~0); 19454#L1311-1 assume !(0 == ~E_10~0); 18348#L1316-1 assume !(0 == ~E_11~0); 18349#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18991#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18992#L593 assume 1 == ~m_pc~0; 19136#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18238#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19664#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19198#L1492 assume !(0 != activate_threads_~tmp~1#1); 19199#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19490#L612 assume !(1 == ~t1_pc~0); 19491#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19620#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18620#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18242#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18243#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18662#L631 assume 1 == ~t2_pc~0; 18597#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18019#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18020#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18856#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 18857#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18315#L650 assume !(1 == ~t3_pc~0); 18316#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19016#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18239#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17972#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 17973#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19165#L669 assume 1 == ~t4_pc~0; 19166#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19524#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18649#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18181#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 18182#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18406#L688 assume !(1 == ~t5_pc~0); 18197#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18198#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19116#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19052#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 19053#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19183#L707 assume 1 == ~t6_pc~0; 19589#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18826#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18827#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19587#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 19124#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18684#L726 assume 1 == ~t7_pc~0; 18585#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18282#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19323#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19598#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 18051#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18052#L745 assume !(1 == ~t8_pc~0); 18499#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18518#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19356#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18904#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18905#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19415#L764 assume 1 == ~t9_pc~0; 18682#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18524#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19201#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19648#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 18071#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18072#L783 assume !(1 == ~t10_pc~0); 18133#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 18134#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18175#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18176#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 18643#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19526#L802 assume 1 == ~t11_pc~0; 19508#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18016#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18017#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18509#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 18510#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18619#L821 assume !(1 == ~t12_pc~0); 18870#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18966#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18023#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18024#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 19564#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19210#L1339 assume !(1 == ~M_E~0); 19211#L1339-2 assume !(1 == ~T1_E~0); 19599#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19600#L1349-1 assume !(1 == ~T3_E~0); 18985#L1354-1 assume !(1 == ~T4_E~0); 18986#L1359-1 assume !(1 == ~T5_E~0); 19388#L1364-1 assume !(1 == ~T6_E~0); 18449#L1369-1 assume !(1 == ~T7_E~0); 18450#L1374-1 assume !(1 == ~T8_E~0); 18989#L1379-1 assume !(1 == ~T9_E~0); 18990#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19087#L1389-1 assume !(1 == ~T11_E~0); 19558#L1394-1 assume !(1 == ~T12_E~0); 19559#L1399-1 assume !(1 == ~E_M~0); 19649#L1404-1 assume !(1 == ~E_1~0); 18550#L1409-1 assume !(1 == ~E_2~0); 18551#L1414-1 assume !(1 == ~E_3~0); 19275#L1419-1 assume !(1 == ~E_4~0); 18189#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18190#L1429-1 assume !(1 == ~E_6~0); 19000#L1434-1 assume !(1 == ~E_7~0); 19579#L1439-1 assume !(1 == ~E_8~0); 18227#L1444-1 assume !(1 == ~E_9~0); 18228#L1449-1 assume !(1 == ~E_10~0); 18602#L1454-1 assume !(1 == ~E_11~0); 18603#L1459-1 assume !(1 == ~E_12~0); 19121#L1464-1 assume { :end_inline_reset_delta_events } true; 18361#L1810-2 [2022-02-21 04:23:15,763 INFO L793 eck$LassoCheckResult]: Loop: 18361#L1810-2 assume !false; 18805#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18721#L1176 assume !false; 19283#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18855#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18059#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18609#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18610#L1003 assume !(0 != eval_~tmp~0#1); 18253#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18254#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19442#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19225#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19226#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19120#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18310#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18311#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18777#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18381#L1231-3 assume !(0 == ~T7_E~0); 18382#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18628#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19610#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19511#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19216#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18327#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18328#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18373#L1271-3 assume !(0 == ~E_2~0); 18374#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18750#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18751#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19272#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19273#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19688#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19645#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18862#L1311-3 assume !(0 == ~E_10~0); 18251#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18252#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18329#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18965#L593-42 assume !(1 == ~m_pc~0); 19122#L593-44 is_master_triggered_~__retres1~0#1 := 0; 19123#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19672#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19673#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18152#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18153#L612-42 assume !(1 == ~t1_pc~0); 19074#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 19467#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19588#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18240#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18241#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18936#L631-42 assume 1 == ~t2_pc~0; 18005#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18006#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18925#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18801#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18802#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18402#L650-42 assume 1 == ~t3_pc~0; 17964#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17965#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19616#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18595#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18596#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19580#L669-42 assume !(1 == ~t4_pc~0); 17962#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 17963#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19391#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19281#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 19178#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19179#L688-42 assume 1 == ~t5_pc~0; 19270#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19471#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18103#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18104#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18177#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17994#L707-42 assume !(1 == ~t6_pc~0); 17995#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 19652#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19396#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19397#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19146#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19147#L726-42 assume 1 == ~t7_pc~0; 19424#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19450#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19451#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18865#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18866#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18969#L745-42 assume 1 == ~t8_pc~0; 19006#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19008#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18335#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17980#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17981#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18706#L764-42 assume 1 == ~t9_pc~0; 18842#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19195#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19196#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18266#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18267#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18320#L783-42 assume 1 == ~t10_pc~0; 17936#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17937#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18532#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18665#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19682#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19366#L802-42 assume 1 == ~t11_pc~0; 18467#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18078#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18079#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18029#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18030#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19206#L821-42 assume 1 == ~t12_pc~0; 19207#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18572#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17932#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17933#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18912#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18902#L1339-3 assume !(1 == ~M_E~0); 18903#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19054#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19164#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18581#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18582#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19175#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19671#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19578#L1374-3 assume !(1 == ~T8_E~0); 18403#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18404#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18579#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18580#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18789#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19585#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19553#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19554#L1414-3 assume !(1 == ~E_3~0); 19609#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19368#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18287#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18288#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19174#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18215#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18216#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18332#L1454-3 assume !(1 == ~E_11~0); 19169#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19170#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18828#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18125#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18385#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18386#L1829 assume !(0 == start_simulation_~tmp~3#1); 18107#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18108#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18908#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18909#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19188#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19189#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18809#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18360#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 18361#L1810-2 [2022-02-21 04:23:15,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:15,763 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2022-02-21 04:23:15,764 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:15,764 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368278815] [2022-02-21 04:23:15,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:15,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:15,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:15,787 INFO L290 TraceCheckUtils]: 0: Hoare triple {23288#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {23288#true} is VALID [2022-02-21 04:23:15,795 INFO L290 TraceCheckUtils]: 1: Hoare triple {23288#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {23290#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:15,796 INFO L290 TraceCheckUtils]: 2: Hoare triple {23290#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {23290#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:15,796 INFO L290 TraceCheckUtils]: 3: Hoare triple {23290#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {23290#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:15,796 INFO L290 TraceCheckUtils]: 4: Hoare triple {23290#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {23290#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:15,796 INFO L290 TraceCheckUtils]: 5: Hoare triple {23290#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {23290#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:15,797 INFO L290 TraceCheckUtils]: 6: Hoare triple {23290#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {23290#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:15,797 INFO L290 TraceCheckUtils]: 7: Hoare triple {23290#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,797 INFO L290 TraceCheckUtils]: 8: Hoare triple {23289#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,797 INFO L290 TraceCheckUtils]: 9: Hoare triple {23289#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,797 INFO L290 TraceCheckUtils]: 10: Hoare triple {23289#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,797 INFO L290 TraceCheckUtils]: 11: Hoare triple {23289#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,798 INFO L290 TraceCheckUtils]: 12: Hoare triple {23289#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,798 INFO L290 TraceCheckUtils]: 13: Hoare triple {23289#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {23289#false} is VALID [2022-02-21 04:23:15,798 INFO L290 TraceCheckUtils]: 14: Hoare triple {23289#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,798 INFO L290 TraceCheckUtils]: 15: Hoare triple {23289#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,798 INFO L290 TraceCheckUtils]: 16: Hoare triple {23289#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,798 INFO L290 TraceCheckUtils]: 17: Hoare triple {23289#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {23289#false} is VALID [2022-02-21 04:23:15,798 INFO L290 TraceCheckUtils]: 18: Hoare triple {23289#false} assume !(0 == ~M_E~0); {23289#false} is VALID [2022-02-21 04:23:15,798 INFO L290 TraceCheckUtils]: 19: Hoare triple {23289#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {23289#false} is VALID [2022-02-21 04:23:15,798 INFO L290 TraceCheckUtils]: 20: Hoare triple {23289#false} assume !(0 == ~T2_E~0); {23289#false} is VALID [2022-02-21 04:23:15,799 INFO L290 TraceCheckUtils]: 21: Hoare triple {23289#false} assume !(0 == ~T3_E~0); {23289#false} is VALID [2022-02-21 04:23:15,799 INFO L290 TraceCheckUtils]: 22: Hoare triple {23289#false} assume !(0 == ~T4_E~0); {23289#false} is VALID [2022-02-21 04:23:15,799 INFO L290 TraceCheckUtils]: 23: Hoare triple {23289#false} assume !(0 == ~T5_E~0); {23289#false} is VALID [2022-02-21 04:23:15,799 INFO L290 TraceCheckUtils]: 24: Hoare triple {23289#false} assume !(0 == ~T6_E~0); {23289#false} is VALID [2022-02-21 04:23:15,799 INFO L290 TraceCheckUtils]: 25: Hoare triple {23289#false} assume !(0 == ~T7_E~0); {23289#false} is VALID [2022-02-21 04:23:15,799 INFO L290 TraceCheckUtils]: 26: Hoare triple {23289#false} assume !(0 == ~T8_E~0); {23289#false} is VALID [2022-02-21 04:23:15,799 INFO L290 TraceCheckUtils]: 27: Hoare triple {23289#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {23289#false} is VALID [2022-02-21 04:23:15,799 INFO L290 TraceCheckUtils]: 28: Hoare triple {23289#false} assume !(0 == ~T10_E~0); {23289#false} is VALID [2022-02-21 04:23:15,800 INFO L290 TraceCheckUtils]: 29: Hoare triple {23289#false} assume !(0 == ~T11_E~0); {23289#false} is VALID [2022-02-21 04:23:15,800 INFO L290 TraceCheckUtils]: 30: Hoare triple {23289#false} assume !(0 == ~T12_E~0); {23289#false} is VALID [2022-02-21 04:23:15,800 INFO L290 TraceCheckUtils]: 31: Hoare triple {23289#false} assume !(0 == ~E_M~0); {23289#false} is VALID [2022-02-21 04:23:15,800 INFO L290 TraceCheckUtils]: 32: Hoare triple {23289#false} assume !(0 == ~E_1~0); {23289#false} is VALID [2022-02-21 04:23:15,800 INFO L290 TraceCheckUtils]: 33: Hoare triple {23289#false} assume !(0 == ~E_2~0); {23289#false} is VALID [2022-02-21 04:23:15,800 INFO L290 TraceCheckUtils]: 34: Hoare triple {23289#false} assume !(0 == ~E_3~0); {23289#false} is VALID [2022-02-21 04:23:15,800 INFO L290 TraceCheckUtils]: 35: Hoare triple {23289#false} assume 0 == ~E_4~0;~E_4~0 := 1; {23289#false} is VALID [2022-02-21 04:23:15,800 INFO L290 TraceCheckUtils]: 36: Hoare triple {23289#false} assume !(0 == ~E_5~0); {23289#false} is VALID [2022-02-21 04:23:15,800 INFO L290 TraceCheckUtils]: 37: Hoare triple {23289#false} assume !(0 == ~E_6~0); {23289#false} is VALID [2022-02-21 04:23:15,801 INFO L290 TraceCheckUtils]: 38: Hoare triple {23289#false} assume !(0 == ~E_7~0); {23289#false} is VALID [2022-02-21 04:23:15,801 INFO L290 TraceCheckUtils]: 39: Hoare triple {23289#false} assume !(0 == ~E_8~0); {23289#false} is VALID [2022-02-21 04:23:15,801 INFO L290 TraceCheckUtils]: 40: Hoare triple {23289#false} assume !(0 == ~E_9~0); {23289#false} is VALID [2022-02-21 04:23:15,801 INFO L290 TraceCheckUtils]: 41: Hoare triple {23289#false} assume !(0 == ~E_10~0); {23289#false} is VALID [2022-02-21 04:23:15,801 INFO L290 TraceCheckUtils]: 42: Hoare triple {23289#false} assume !(0 == ~E_11~0); {23289#false} is VALID [2022-02-21 04:23:15,801 INFO L290 TraceCheckUtils]: 43: Hoare triple {23289#false} assume 0 == ~E_12~0;~E_12~0 := 1; {23289#false} is VALID [2022-02-21 04:23:15,801 INFO L290 TraceCheckUtils]: 44: Hoare triple {23289#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23289#false} is VALID [2022-02-21 04:23:15,801 INFO L290 TraceCheckUtils]: 45: Hoare triple {23289#false} assume 1 == ~m_pc~0; {23289#false} is VALID [2022-02-21 04:23:15,802 INFO L290 TraceCheckUtils]: 46: Hoare triple {23289#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {23289#false} is VALID [2022-02-21 04:23:15,802 INFO L290 TraceCheckUtils]: 47: Hoare triple {23289#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23289#false} is VALID [2022-02-21 04:23:15,802 INFO L290 TraceCheckUtils]: 48: Hoare triple {23289#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23289#false} is VALID [2022-02-21 04:23:15,802 INFO L290 TraceCheckUtils]: 49: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp~1#1); {23289#false} is VALID [2022-02-21 04:23:15,802 INFO L290 TraceCheckUtils]: 50: Hoare triple {23289#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23289#false} is VALID [2022-02-21 04:23:15,802 INFO L290 TraceCheckUtils]: 51: Hoare triple {23289#false} assume !(1 == ~t1_pc~0); {23289#false} is VALID [2022-02-21 04:23:15,802 INFO L290 TraceCheckUtils]: 52: Hoare triple {23289#false} is_transmit1_triggered_~__retres1~1#1 := 0; {23289#false} is VALID [2022-02-21 04:23:15,802 INFO L290 TraceCheckUtils]: 53: Hoare triple {23289#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23289#false} is VALID [2022-02-21 04:23:15,802 INFO L290 TraceCheckUtils]: 54: Hoare triple {23289#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23289#false} is VALID [2022-02-21 04:23:15,803 INFO L290 TraceCheckUtils]: 55: Hoare triple {23289#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {23289#false} is VALID [2022-02-21 04:23:15,803 INFO L290 TraceCheckUtils]: 56: Hoare triple {23289#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23289#false} is VALID [2022-02-21 04:23:15,803 INFO L290 TraceCheckUtils]: 57: Hoare triple {23289#false} assume 1 == ~t2_pc~0; {23289#false} is VALID [2022-02-21 04:23:15,803 INFO L290 TraceCheckUtils]: 58: Hoare triple {23289#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {23289#false} is VALID [2022-02-21 04:23:15,803 INFO L290 TraceCheckUtils]: 59: Hoare triple {23289#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23289#false} is VALID [2022-02-21 04:23:15,803 INFO L290 TraceCheckUtils]: 60: Hoare triple {23289#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23289#false} is VALID [2022-02-21 04:23:15,803 INFO L290 TraceCheckUtils]: 61: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp___1~0#1); {23289#false} is VALID [2022-02-21 04:23:15,803 INFO L290 TraceCheckUtils]: 62: Hoare triple {23289#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23289#false} is VALID [2022-02-21 04:23:15,804 INFO L290 TraceCheckUtils]: 63: Hoare triple {23289#false} assume !(1 == ~t3_pc~0); {23289#false} is VALID [2022-02-21 04:23:15,804 INFO L290 TraceCheckUtils]: 64: Hoare triple {23289#false} is_transmit3_triggered_~__retres1~3#1 := 0; {23289#false} is VALID [2022-02-21 04:23:15,804 INFO L290 TraceCheckUtils]: 65: Hoare triple {23289#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23289#false} is VALID [2022-02-21 04:23:15,804 INFO L290 TraceCheckUtils]: 66: Hoare triple {23289#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {23289#false} is VALID [2022-02-21 04:23:15,804 INFO L290 TraceCheckUtils]: 67: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp___2~0#1); {23289#false} is VALID [2022-02-21 04:23:15,804 INFO L290 TraceCheckUtils]: 68: Hoare triple {23289#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23289#false} is VALID [2022-02-21 04:23:15,804 INFO L290 TraceCheckUtils]: 69: Hoare triple {23289#false} assume 1 == ~t4_pc~0; {23289#false} is VALID [2022-02-21 04:23:15,804 INFO L290 TraceCheckUtils]: 70: Hoare triple {23289#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {23289#false} is VALID [2022-02-21 04:23:15,804 INFO L290 TraceCheckUtils]: 71: Hoare triple {23289#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23289#false} is VALID [2022-02-21 04:23:15,805 INFO L290 TraceCheckUtils]: 72: Hoare triple {23289#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {23289#false} is VALID [2022-02-21 04:23:15,805 INFO L290 TraceCheckUtils]: 73: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp___3~0#1); {23289#false} is VALID [2022-02-21 04:23:15,805 INFO L290 TraceCheckUtils]: 74: Hoare triple {23289#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23289#false} is VALID [2022-02-21 04:23:15,805 INFO L290 TraceCheckUtils]: 75: Hoare triple {23289#false} assume !(1 == ~t5_pc~0); {23289#false} is VALID [2022-02-21 04:23:15,805 INFO L290 TraceCheckUtils]: 76: Hoare triple {23289#false} is_transmit5_triggered_~__retres1~5#1 := 0; {23289#false} is VALID [2022-02-21 04:23:15,805 INFO L290 TraceCheckUtils]: 77: Hoare triple {23289#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23289#false} is VALID [2022-02-21 04:23:15,805 INFO L290 TraceCheckUtils]: 78: Hoare triple {23289#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {23289#false} is VALID [2022-02-21 04:23:15,805 INFO L290 TraceCheckUtils]: 79: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp___4~0#1); {23289#false} is VALID [2022-02-21 04:23:15,806 INFO L290 TraceCheckUtils]: 80: Hoare triple {23289#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23289#false} is VALID [2022-02-21 04:23:15,806 INFO L290 TraceCheckUtils]: 81: Hoare triple {23289#false} assume 1 == ~t6_pc~0; {23289#false} is VALID [2022-02-21 04:23:15,806 INFO L290 TraceCheckUtils]: 82: Hoare triple {23289#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {23289#false} is VALID [2022-02-21 04:23:15,806 INFO L290 TraceCheckUtils]: 83: Hoare triple {23289#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23289#false} is VALID [2022-02-21 04:23:15,806 INFO L290 TraceCheckUtils]: 84: Hoare triple {23289#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {23289#false} is VALID [2022-02-21 04:23:15,806 INFO L290 TraceCheckUtils]: 85: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp___5~0#1); {23289#false} is VALID [2022-02-21 04:23:15,806 INFO L290 TraceCheckUtils]: 86: Hoare triple {23289#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23289#false} is VALID [2022-02-21 04:23:15,806 INFO L290 TraceCheckUtils]: 87: Hoare triple {23289#false} assume 1 == ~t7_pc~0; {23289#false} is VALID [2022-02-21 04:23:15,806 INFO L290 TraceCheckUtils]: 88: Hoare triple {23289#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {23289#false} is VALID [2022-02-21 04:23:15,807 INFO L290 TraceCheckUtils]: 89: Hoare triple {23289#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23289#false} is VALID [2022-02-21 04:23:15,807 INFO L290 TraceCheckUtils]: 90: Hoare triple {23289#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {23289#false} is VALID [2022-02-21 04:23:15,807 INFO L290 TraceCheckUtils]: 91: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp___6~0#1); {23289#false} is VALID [2022-02-21 04:23:15,807 INFO L290 TraceCheckUtils]: 92: Hoare triple {23289#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23289#false} is VALID [2022-02-21 04:23:15,807 INFO L290 TraceCheckUtils]: 93: Hoare triple {23289#false} assume !(1 == ~t8_pc~0); {23289#false} is VALID [2022-02-21 04:23:15,807 INFO L290 TraceCheckUtils]: 94: Hoare triple {23289#false} is_transmit8_triggered_~__retres1~8#1 := 0; {23289#false} is VALID [2022-02-21 04:23:15,807 INFO L290 TraceCheckUtils]: 95: Hoare triple {23289#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23289#false} is VALID [2022-02-21 04:23:15,807 INFO L290 TraceCheckUtils]: 96: Hoare triple {23289#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {23289#false} is VALID [2022-02-21 04:23:15,808 INFO L290 TraceCheckUtils]: 97: Hoare triple {23289#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {23289#false} is VALID [2022-02-21 04:23:15,808 INFO L290 TraceCheckUtils]: 98: Hoare triple {23289#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {23289#false} is VALID [2022-02-21 04:23:15,808 INFO L290 TraceCheckUtils]: 99: Hoare triple {23289#false} assume 1 == ~t9_pc~0; {23289#false} is VALID [2022-02-21 04:23:15,808 INFO L290 TraceCheckUtils]: 100: Hoare triple {23289#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {23289#false} is VALID [2022-02-21 04:23:15,808 INFO L290 TraceCheckUtils]: 101: Hoare triple {23289#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {23289#false} is VALID [2022-02-21 04:23:15,808 INFO L290 TraceCheckUtils]: 102: Hoare triple {23289#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {23289#false} is VALID [2022-02-21 04:23:15,808 INFO L290 TraceCheckUtils]: 103: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp___8~0#1); {23289#false} is VALID [2022-02-21 04:23:15,808 INFO L290 TraceCheckUtils]: 104: Hoare triple {23289#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {23289#false} is VALID [2022-02-21 04:23:15,808 INFO L290 TraceCheckUtils]: 105: Hoare triple {23289#false} assume !(1 == ~t10_pc~0); {23289#false} is VALID [2022-02-21 04:23:15,809 INFO L290 TraceCheckUtils]: 106: Hoare triple {23289#false} is_transmit10_triggered_~__retres1~10#1 := 0; {23289#false} is VALID [2022-02-21 04:23:15,809 INFO L290 TraceCheckUtils]: 107: Hoare triple {23289#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {23289#false} is VALID [2022-02-21 04:23:15,809 INFO L290 TraceCheckUtils]: 108: Hoare triple {23289#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {23289#false} is VALID [2022-02-21 04:23:15,809 INFO L290 TraceCheckUtils]: 109: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp___9~0#1); {23289#false} is VALID [2022-02-21 04:23:15,809 INFO L290 TraceCheckUtils]: 110: Hoare triple {23289#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {23289#false} is VALID [2022-02-21 04:23:15,809 INFO L290 TraceCheckUtils]: 111: Hoare triple {23289#false} assume 1 == ~t11_pc~0; {23289#false} is VALID [2022-02-21 04:23:15,809 INFO L290 TraceCheckUtils]: 112: Hoare triple {23289#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {23289#false} is VALID [2022-02-21 04:23:15,809 INFO L290 TraceCheckUtils]: 113: Hoare triple {23289#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {23289#false} is VALID [2022-02-21 04:23:15,810 INFO L290 TraceCheckUtils]: 114: Hoare triple {23289#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {23289#false} is VALID [2022-02-21 04:23:15,810 INFO L290 TraceCheckUtils]: 115: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp___10~0#1); {23289#false} is VALID [2022-02-21 04:23:15,810 INFO L290 TraceCheckUtils]: 116: Hoare triple {23289#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {23289#false} is VALID [2022-02-21 04:23:15,810 INFO L290 TraceCheckUtils]: 117: Hoare triple {23289#false} assume !(1 == ~t12_pc~0); {23289#false} is VALID [2022-02-21 04:23:15,810 INFO L290 TraceCheckUtils]: 118: Hoare triple {23289#false} is_transmit12_triggered_~__retres1~12#1 := 0; {23289#false} is VALID [2022-02-21 04:23:15,810 INFO L290 TraceCheckUtils]: 119: Hoare triple {23289#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {23289#false} is VALID [2022-02-21 04:23:15,810 INFO L290 TraceCheckUtils]: 120: Hoare triple {23289#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {23289#false} is VALID [2022-02-21 04:23:15,810 INFO L290 TraceCheckUtils]: 121: Hoare triple {23289#false} assume !(0 != activate_threads_~tmp___11~0#1); {23289#false} is VALID [2022-02-21 04:23:15,810 INFO L290 TraceCheckUtils]: 122: Hoare triple {23289#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23289#false} is VALID [2022-02-21 04:23:15,811 INFO L290 TraceCheckUtils]: 123: Hoare triple {23289#false} assume !(1 == ~M_E~0); {23289#false} is VALID [2022-02-21 04:23:15,811 INFO L290 TraceCheckUtils]: 124: Hoare triple {23289#false} assume !(1 == ~T1_E~0); {23289#false} is VALID [2022-02-21 04:23:15,811 INFO L290 TraceCheckUtils]: 125: Hoare triple {23289#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,811 INFO L290 TraceCheckUtils]: 126: Hoare triple {23289#false} assume !(1 == ~T3_E~0); {23289#false} is VALID [2022-02-21 04:23:15,811 INFO L290 TraceCheckUtils]: 127: Hoare triple {23289#false} assume !(1 == ~T4_E~0); {23289#false} is VALID [2022-02-21 04:23:15,811 INFO L290 TraceCheckUtils]: 128: Hoare triple {23289#false} assume !(1 == ~T5_E~0); {23289#false} is VALID [2022-02-21 04:23:15,811 INFO L290 TraceCheckUtils]: 129: Hoare triple {23289#false} assume !(1 == ~T6_E~0); {23289#false} is VALID [2022-02-21 04:23:15,811 INFO L290 TraceCheckUtils]: 130: Hoare triple {23289#false} assume !(1 == ~T7_E~0); {23289#false} is VALID [2022-02-21 04:23:15,811 INFO L290 TraceCheckUtils]: 131: Hoare triple {23289#false} assume !(1 == ~T8_E~0); {23289#false} is VALID [2022-02-21 04:23:15,812 INFO L290 TraceCheckUtils]: 132: Hoare triple {23289#false} assume !(1 == ~T9_E~0); {23289#false} is VALID [2022-02-21 04:23:15,812 INFO L290 TraceCheckUtils]: 133: Hoare triple {23289#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,812 INFO L290 TraceCheckUtils]: 134: Hoare triple {23289#false} assume !(1 == ~T11_E~0); {23289#false} is VALID [2022-02-21 04:23:15,812 INFO L290 TraceCheckUtils]: 135: Hoare triple {23289#false} assume !(1 == ~T12_E~0); {23289#false} is VALID [2022-02-21 04:23:15,812 INFO L290 TraceCheckUtils]: 136: Hoare triple {23289#false} assume !(1 == ~E_M~0); {23289#false} is VALID [2022-02-21 04:23:15,812 INFO L290 TraceCheckUtils]: 137: Hoare triple {23289#false} assume !(1 == ~E_1~0); {23289#false} is VALID [2022-02-21 04:23:15,812 INFO L290 TraceCheckUtils]: 138: Hoare triple {23289#false} assume !(1 == ~E_2~0); {23289#false} is VALID [2022-02-21 04:23:15,812 INFO L290 TraceCheckUtils]: 139: Hoare triple {23289#false} assume !(1 == ~E_3~0); {23289#false} is VALID [2022-02-21 04:23:15,813 INFO L290 TraceCheckUtils]: 140: Hoare triple {23289#false} assume !(1 == ~E_4~0); {23289#false} is VALID [2022-02-21 04:23:15,813 INFO L290 TraceCheckUtils]: 141: Hoare triple {23289#false} assume 1 == ~E_5~0;~E_5~0 := 2; {23289#false} is VALID [2022-02-21 04:23:15,813 INFO L290 TraceCheckUtils]: 142: Hoare triple {23289#false} assume !(1 == ~E_6~0); {23289#false} is VALID [2022-02-21 04:23:15,813 INFO L290 TraceCheckUtils]: 143: Hoare triple {23289#false} assume !(1 == ~E_7~0); {23289#false} is VALID [2022-02-21 04:23:15,813 INFO L290 TraceCheckUtils]: 144: Hoare triple {23289#false} assume !(1 == ~E_8~0); {23289#false} is VALID [2022-02-21 04:23:15,813 INFO L290 TraceCheckUtils]: 145: Hoare triple {23289#false} assume !(1 == ~E_9~0); {23289#false} is VALID [2022-02-21 04:23:15,813 INFO L290 TraceCheckUtils]: 146: Hoare triple {23289#false} assume !(1 == ~E_10~0); {23289#false} is VALID [2022-02-21 04:23:15,813 INFO L290 TraceCheckUtils]: 147: Hoare triple {23289#false} assume !(1 == ~E_11~0); {23289#false} is VALID [2022-02-21 04:23:15,813 INFO L290 TraceCheckUtils]: 148: Hoare triple {23289#false} assume !(1 == ~E_12~0); {23289#false} is VALID [2022-02-21 04:23:15,814 INFO L290 TraceCheckUtils]: 149: Hoare triple {23289#false} assume { :end_inline_reset_delta_events } true; {23289#false} is VALID [2022-02-21 04:23:15,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:15,814 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:15,814 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368278815] [2022-02-21 04:23:15,814 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368278815] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:15,814 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:15,815 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:15,815 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1774164889] [2022-02-21 04:23:15,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:15,815 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:15,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:15,816 INFO L85 PathProgramCache]: Analyzing trace with hash -1070579181, now seen corresponding path program 1 times [2022-02-21 04:23:15,816 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:15,816 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916742655] [2022-02-21 04:23:15,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:15,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:15,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:15,848 INFO L290 TraceCheckUtils]: 0: Hoare triple {23291#true} assume !false; {23291#true} is VALID [2022-02-21 04:23:15,848 INFO L290 TraceCheckUtils]: 1: Hoare triple {23291#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {23291#true} is VALID [2022-02-21 04:23:15,848 INFO L290 TraceCheckUtils]: 2: Hoare triple {23291#true} assume !false; {23291#true} is VALID [2022-02-21 04:23:15,849 INFO L290 TraceCheckUtils]: 3: Hoare triple {23291#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {23291#true} is VALID [2022-02-21 04:23:15,849 INFO L290 TraceCheckUtils]: 4: Hoare triple {23291#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {23291#true} is VALID [2022-02-21 04:23:15,849 INFO L290 TraceCheckUtils]: 5: Hoare triple {23291#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {23291#true} is VALID [2022-02-21 04:23:15,849 INFO L290 TraceCheckUtils]: 6: Hoare triple {23291#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {23291#true} is VALID [2022-02-21 04:23:15,849 INFO L290 TraceCheckUtils]: 7: Hoare triple {23291#true} assume !(0 != eval_~tmp~0#1); {23291#true} is VALID [2022-02-21 04:23:15,849 INFO L290 TraceCheckUtils]: 8: Hoare triple {23291#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {23291#true} is VALID [2022-02-21 04:23:15,849 INFO L290 TraceCheckUtils]: 9: Hoare triple {23291#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {23291#true} is VALID [2022-02-21 04:23:15,850 INFO L290 TraceCheckUtils]: 10: Hoare triple {23291#true} assume 0 == ~M_E~0;~M_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,850 INFO L290 TraceCheckUtils]: 11: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,850 INFO L290 TraceCheckUtils]: 12: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,850 INFO L290 TraceCheckUtils]: 13: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,851 INFO L290 TraceCheckUtils]: 14: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,851 INFO L290 TraceCheckUtils]: 15: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,851 INFO L290 TraceCheckUtils]: 16: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,851 INFO L290 TraceCheckUtils]: 17: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,852 INFO L290 TraceCheckUtils]: 18: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,852 INFO L290 TraceCheckUtils]: 19: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,852 INFO L290 TraceCheckUtils]: 20: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,852 INFO L290 TraceCheckUtils]: 21: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,853 INFO L290 TraceCheckUtils]: 22: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,853 INFO L290 TraceCheckUtils]: 23: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,853 INFO L290 TraceCheckUtils]: 24: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,854 INFO L290 TraceCheckUtils]: 25: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,854 INFO L290 TraceCheckUtils]: 26: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,854 INFO L290 TraceCheckUtils]: 27: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,854 INFO L290 TraceCheckUtils]: 28: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,855 INFO L290 TraceCheckUtils]: 29: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,855 INFO L290 TraceCheckUtils]: 30: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,855 INFO L290 TraceCheckUtils]: 31: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,856 INFO L290 TraceCheckUtils]: 32: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,856 INFO L290 TraceCheckUtils]: 33: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,856 INFO L290 TraceCheckUtils]: 34: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,856 INFO L290 TraceCheckUtils]: 35: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,857 INFO L290 TraceCheckUtils]: 36: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,857 INFO L290 TraceCheckUtils]: 37: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,857 INFO L290 TraceCheckUtils]: 38: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,857 INFO L290 TraceCheckUtils]: 39: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,858 INFO L290 TraceCheckUtils]: 40: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,858 INFO L290 TraceCheckUtils]: 41: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,858 INFO L290 TraceCheckUtils]: 42: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,859 INFO L290 TraceCheckUtils]: 43: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,859 INFO L290 TraceCheckUtils]: 44: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,859 INFO L290 TraceCheckUtils]: 45: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,859 INFO L290 TraceCheckUtils]: 46: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,860 INFO L290 TraceCheckUtils]: 47: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,860 INFO L290 TraceCheckUtils]: 48: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,860 INFO L290 TraceCheckUtils]: 49: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,860 INFO L290 TraceCheckUtils]: 50: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,861 INFO L290 TraceCheckUtils]: 51: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,861 INFO L290 TraceCheckUtils]: 52: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,861 INFO L290 TraceCheckUtils]: 53: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,861 INFO L290 TraceCheckUtils]: 54: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,862 INFO L290 TraceCheckUtils]: 55: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,862 INFO L290 TraceCheckUtils]: 56: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,862 INFO L290 TraceCheckUtils]: 57: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,863 INFO L290 TraceCheckUtils]: 58: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,863 INFO L290 TraceCheckUtils]: 59: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,863 INFO L290 TraceCheckUtils]: 60: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,863 INFO L290 TraceCheckUtils]: 61: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,864 INFO L290 TraceCheckUtils]: 62: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,864 INFO L290 TraceCheckUtils]: 63: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,864 INFO L290 TraceCheckUtils]: 64: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,864 INFO L290 TraceCheckUtils]: 65: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,865 INFO L290 TraceCheckUtils]: 66: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,865 INFO L290 TraceCheckUtils]: 67: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,865 INFO L290 TraceCheckUtils]: 68: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,865 INFO L290 TraceCheckUtils]: 69: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,866 INFO L290 TraceCheckUtils]: 70: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,866 INFO L290 TraceCheckUtils]: 71: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,866 INFO L290 TraceCheckUtils]: 72: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,867 INFO L290 TraceCheckUtils]: 73: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,867 INFO L290 TraceCheckUtils]: 74: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,867 INFO L290 TraceCheckUtils]: 75: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,867 INFO L290 TraceCheckUtils]: 76: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,868 INFO L290 TraceCheckUtils]: 77: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,868 INFO L290 TraceCheckUtils]: 78: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,868 INFO L290 TraceCheckUtils]: 79: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,868 INFO L290 TraceCheckUtils]: 80: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,869 INFO L290 TraceCheckUtils]: 81: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,869 INFO L290 TraceCheckUtils]: 82: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,869 INFO L290 TraceCheckUtils]: 83: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,869 INFO L290 TraceCheckUtils]: 84: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,870 INFO L290 TraceCheckUtils]: 85: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,870 INFO L290 TraceCheckUtils]: 86: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,870 INFO L290 TraceCheckUtils]: 87: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,871 INFO L290 TraceCheckUtils]: 88: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,871 INFO L290 TraceCheckUtils]: 89: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,871 INFO L290 TraceCheckUtils]: 90: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,871 INFO L290 TraceCheckUtils]: 91: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,872 INFO L290 TraceCheckUtils]: 92: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,872 INFO L290 TraceCheckUtils]: 93: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,872 INFO L290 TraceCheckUtils]: 94: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,872 INFO L290 TraceCheckUtils]: 95: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,873 INFO L290 TraceCheckUtils]: 96: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,873 INFO L290 TraceCheckUtils]: 97: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,873 INFO L290 TraceCheckUtils]: 98: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,873 INFO L290 TraceCheckUtils]: 99: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,874 INFO L290 TraceCheckUtils]: 100: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,874 INFO L290 TraceCheckUtils]: 101: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,874 INFO L290 TraceCheckUtils]: 102: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,875 INFO L290 TraceCheckUtils]: 103: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,875 INFO L290 TraceCheckUtils]: 104: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,875 INFO L290 TraceCheckUtils]: 105: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,875 INFO L290 TraceCheckUtils]: 106: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,876 INFO L290 TraceCheckUtils]: 107: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,876 INFO L290 TraceCheckUtils]: 108: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,876 INFO L290 TraceCheckUtils]: 109: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,876 INFO L290 TraceCheckUtils]: 110: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,877 INFO L290 TraceCheckUtils]: 111: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,877 INFO L290 TraceCheckUtils]: 112: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,877 INFO L290 TraceCheckUtils]: 113: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,877 INFO L290 TraceCheckUtils]: 114: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23293#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:15,878 INFO L290 TraceCheckUtils]: 115: Hoare triple {23293#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {23292#false} is VALID [2022-02-21 04:23:15,878 INFO L290 TraceCheckUtils]: 116: Hoare triple {23292#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,878 INFO L290 TraceCheckUtils]: 117: Hoare triple {23292#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,878 INFO L290 TraceCheckUtils]: 118: Hoare triple {23292#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,878 INFO L290 TraceCheckUtils]: 119: Hoare triple {23292#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,878 INFO L290 TraceCheckUtils]: 120: Hoare triple {23292#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,878 INFO L290 TraceCheckUtils]: 121: Hoare triple {23292#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,879 INFO L290 TraceCheckUtils]: 122: Hoare triple {23292#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,879 INFO L290 TraceCheckUtils]: 123: Hoare triple {23292#false} assume !(1 == ~T8_E~0); {23292#false} is VALID [2022-02-21 04:23:15,879 INFO L290 TraceCheckUtils]: 124: Hoare triple {23292#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,879 INFO L290 TraceCheckUtils]: 125: Hoare triple {23292#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,879 INFO L290 TraceCheckUtils]: 126: Hoare triple {23292#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,879 INFO L290 TraceCheckUtils]: 127: Hoare triple {23292#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,879 INFO L290 TraceCheckUtils]: 128: Hoare triple {23292#false} assume 1 == ~E_M~0;~E_M~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,879 INFO L290 TraceCheckUtils]: 129: Hoare triple {23292#false} assume 1 == ~E_1~0;~E_1~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,879 INFO L290 TraceCheckUtils]: 130: Hoare triple {23292#false} assume 1 == ~E_2~0;~E_2~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,880 INFO L290 TraceCheckUtils]: 131: Hoare triple {23292#false} assume !(1 == ~E_3~0); {23292#false} is VALID [2022-02-21 04:23:15,880 INFO L290 TraceCheckUtils]: 132: Hoare triple {23292#false} assume 1 == ~E_4~0;~E_4~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,880 INFO L290 TraceCheckUtils]: 133: Hoare triple {23292#false} assume 1 == ~E_5~0;~E_5~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,880 INFO L290 TraceCheckUtils]: 134: Hoare triple {23292#false} assume 1 == ~E_6~0;~E_6~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,880 INFO L290 TraceCheckUtils]: 135: Hoare triple {23292#false} assume 1 == ~E_7~0;~E_7~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,880 INFO L290 TraceCheckUtils]: 136: Hoare triple {23292#false} assume 1 == ~E_8~0;~E_8~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,880 INFO L290 TraceCheckUtils]: 137: Hoare triple {23292#false} assume 1 == ~E_9~0;~E_9~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,880 INFO L290 TraceCheckUtils]: 138: Hoare triple {23292#false} assume 1 == ~E_10~0;~E_10~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,880 INFO L290 TraceCheckUtils]: 139: Hoare triple {23292#false} assume !(1 == ~E_11~0); {23292#false} is VALID [2022-02-21 04:23:15,881 INFO L290 TraceCheckUtils]: 140: Hoare triple {23292#false} assume 1 == ~E_12~0;~E_12~0 := 2; {23292#false} is VALID [2022-02-21 04:23:15,881 INFO L290 TraceCheckUtils]: 141: Hoare triple {23292#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {23292#false} is VALID [2022-02-21 04:23:15,881 INFO L290 TraceCheckUtils]: 142: Hoare triple {23292#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {23292#false} is VALID [2022-02-21 04:23:15,881 INFO L290 TraceCheckUtils]: 143: Hoare triple {23292#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {23292#false} is VALID [2022-02-21 04:23:15,881 INFO L290 TraceCheckUtils]: 144: Hoare triple {23292#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {23292#false} is VALID [2022-02-21 04:23:15,881 INFO L290 TraceCheckUtils]: 145: Hoare triple {23292#false} assume !(0 == start_simulation_~tmp~3#1); {23292#false} is VALID [2022-02-21 04:23:15,881 INFO L290 TraceCheckUtils]: 146: Hoare triple {23292#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {23292#false} is VALID [2022-02-21 04:23:15,881 INFO L290 TraceCheckUtils]: 147: Hoare triple {23292#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {23292#false} is VALID [2022-02-21 04:23:15,882 INFO L290 TraceCheckUtils]: 148: Hoare triple {23292#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {23292#false} is VALID [2022-02-21 04:23:15,882 INFO L290 TraceCheckUtils]: 149: Hoare triple {23292#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {23292#false} is VALID [2022-02-21 04:23:15,882 INFO L290 TraceCheckUtils]: 150: Hoare triple {23292#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {23292#false} is VALID [2022-02-21 04:23:15,882 INFO L290 TraceCheckUtils]: 151: Hoare triple {23292#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {23292#false} is VALID [2022-02-21 04:23:15,882 INFO L290 TraceCheckUtils]: 152: Hoare triple {23292#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {23292#false} is VALID [2022-02-21 04:23:15,882 INFO L290 TraceCheckUtils]: 153: Hoare triple {23292#false} assume !(0 != start_simulation_~tmp___0~1#1); {23292#false} is VALID [2022-02-21 04:23:15,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:15,883 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:15,883 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916742655] [2022-02-21 04:23:15,883 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916742655] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:15,883 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:15,883 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:15,883 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766551404] [2022-02-21 04:23:15,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:15,884 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:15,884 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:15,884 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:15,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:15,885 INFO L87 Difference]: Start difference. First operand 1788 states and 2649 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,180 INFO L93 Difference]: Finished difference Result 1788 states and 2648 transitions. [2022-02-21 04:23:17,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:17,180 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,264 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:17,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2648 transitions. [2022-02-21 04:23:17,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:17,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2648 transitions. [2022-02-21 04:23:17,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:17,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:17,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2648 transitions. [2022-02-21 04:23:17,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:17,423 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2022-02-21 04:23:17,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2648 transitions. [2022-02-21 04:23:17,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:17,439 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:17,441 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2648 transitions. Second operand has 1788 states, 1788 states have (on average 1.4809843400447427) internal successors, (2648), 1787 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,443 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2648 transitions. Second operand has 1788 states, 1788 states have (on average 1.4809843400447427) internal successors, (2648), 1787 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,444 INFO L87 Difference]: Start difference. First operand 1788 states and 2648 transitions. Second operand has 1788 states, 1788 states have (on average 1.4809843400447427) internal successors, (2648), 1787 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,511 INFO L93 Difference]: Finished difference Result 1788 states and 2648 transitions. [2022-02-21 04:23:17,511 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2648 transitions. [2022-02-21 04:23:17,513 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:17,513 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:17,516 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4809843400447427) internal successors, (2648), 1787 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2648 transitions. [2022-02-21 04:23:17,517 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4809843400447427) internal successors, (2648), 1787 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2648 transitions. [2022-02-21 04:23:17,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,584 INFO L93 Difference]: Finished difference Result 1788 states and 2648 transitions. [2022-02-21 04:23:17,584 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2648 transitions. [2022-02-21 04:23:17,586 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:17,587 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:17,587 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:17,587 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:17,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4809843400447427) internal successors, (2648), 1787 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2648 transitions. [2022-02-21 04:23:17,657 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2022-02-21 04:23:17,657 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2022-02-21 04:23:17,657 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:23:17,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2648 transitions. [2022-02-21 04:23:17,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:17,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:17,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:17,663 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:17,663 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:17,664 INFO L791 eck$LassoCheckResult]: Stem: 25871#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25872#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25392#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25393#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25447#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 26786#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25880#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25683#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25082#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 25083#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 26305#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26416#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26852#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26853#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25811#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25812#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26334#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26253#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25846#L1201 assume !(0 == ~M_E~0); 25847#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26693#L1206-1 assume !(0 == ~T2_E~0); 26679#L1211-1 assume !(0 == ~T3_E~0); 26680#L1216-1 assume !(0 == ~T4_E~0); 25668#L1221-1 assume !(0 == ~T5_E~0); 25669#L1226-1 assume !(0 == ~T6_E~0); 25307#L1231-1 assume !(0 == ~T7_E~0); 25308#L1236-1 assume !(0 == ~T8_E~0); 26716#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25704#L1246-1 assume !(0 == ~T10_E~0); 25705#L1251-1 assume !(0 == ~T11_E~0); 25844#L1256-1 assume !(0 == ~T12_E~0); 25095#L1261-1 assume !(0 == ~E_M~0); 25096#L1266-1 assume !(0 == ~E_1~0); 26838#L1271-1 assume !(0 == ~E_2~0); 26400#L1276-1 assume !(0 == ~E_3~0); 26401#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26348#L1286-1 assume !(0 == ~E_5~0); 25558#L1291-1 assume !(0 == ~E_6~0); 25559#L1296-1 assume !(0 == ~E_7~0); 26134#L1301-1 assume !(0 == ~E_8~0); 26135#L1306-1 assume !(0 == ~E_9~0); 26615#L1311-1 assume !(0 == ~E_10~0); 25509#L1316-1 assume !(0 == ~E_11~0); 25510#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 26152#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26153#L593 assume 1 == ~m_pc~0; 26297#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25399#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26825#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26359#L1492 assume !(0 != activate_threads_~tmp~1#1); 26360#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26651#L612 assume !(1 == ~t1_pc~0); 26652#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26781#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25781#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25403#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25404#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25823#L631 assume 1 == ~t2_pc~0; 25758#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25180#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25181#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26017#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 26018#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25476#L650 assume !(1 == ~t3_pc~0); 25477#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26177#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25400#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25133#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 25134#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26326#L669 assume 1 == ~t4_pc~0; 26327#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26685#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25810#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25342#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 25343#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25567#L688 assume !(1 == ~t5_pc~0); 25358#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25359#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26277#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26211#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 26212#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26344#L707 assume 1 == ~t6_pc~0; 26750#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25987#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25988#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26748#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 26283#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25845#L726 assume 1 == ~t7_pc~0; 25746#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25443#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26484#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26758#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 25212#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25213#L745 assume !(1 == ~t8_pc~0); 25660#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25679#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26517#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26065#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26066#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26576#L764 assume 1 == ~t9_pc~0; 25843#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25685#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26362#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26809#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 25232#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25233#L783 assume !(1 == ~t10_pc~0); 25294#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25295#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25336#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25337#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 25801#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26687#L802 assume 1 == ~t11_pc~0; 26669#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25177#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25178#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25670#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 25671#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25780#L821 assume !(1 == ~t12_pc~0); 26031#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26127#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25184#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25185#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 26725#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26371#L1339 assume !(1 == ~M_E~0); 26372#L1339-2 assume !(1 == ~T1_E~0); 26760#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26761#L1349-1 assume !(1 == ~T3_E~0); 26146#L1354-1 assume !(1 == ~T4_E~0); 26147#L1359-1 assume !(1 == ~T5_E~0); 26547#L1364-1 assume !(1 == ~T6_E~0); 25610#L1369-1 assume !(1 == ~T7_E~0); 25611#L1374-1 assume !(1 == ~T8_E~0); 26148#L1379-1 assume !(1 == ~T9_E~0); 26149#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26248#L1389-1 assume !(1 == ~T11_E~0); 26719#L1394-1 assume !(1 == ~T12_E~0); 26720#L1399-1 assume !(1 == ~E_M~0); 26810#L1404-1 assume !(1 == ~E_1~0); 25709#L1409-1 assume !(1 == ~E_2~0); 25710#L1414-1 assume !(1 == ~E_3~0); 26436#L1419-1 assume !(1 == ~E_4~0); 25350#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 25351#L1429-1 assume !(1 == ~E_6~0); 26161#L1434-1 assume !(1 == ~E_7~0); 26740#L1439-1 assume !(1 == ~E_8~0); 25388#L1444-1 assume !(1 == ~E_9~0); 25389#L1449-1 assume !(1 == ~E_10~0); 25763#L1454-1 assume !(1 == ~E_11~0); 25764#L1459-1 assume !(1 == ~E_12~0); 26282#L1464-1 assume { :end_inline_reset_delta_events } true; 25522#L1810-2 [2022-02-21 04:23:17,664 INFO L793 eck$LassoCheckResult]: Loop: 25522#L1810-2 assume !false; 25966#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25882#L1176 assume !false; 26444#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26014#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25220#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25770#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25771#L1003 assume !(0 != eval_~tmp~0#1); 25412#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25413#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26603#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26386#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26387#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26280#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25471#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25472#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25938#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25542#L1231-3 assume !(0 == ~T7_E~0); 25543#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25791#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26771#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26672#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26377#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25488#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25489#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25534#L1271-3 assume !(0 == ~E_2~0); 25535#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25911#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25912#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26434#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26435#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26849#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26806#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26023#L1311-3 assume !(0 == ~E_10~0); 25414#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25415#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25490#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26126#L593-42 assume 1 == ~m_pc~0; 26520#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26285#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26834#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26835#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25313#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25314#L612-42 assume !(1 == ~t1_pc~0); 26235#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 26628#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26749#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25401#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25402#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26097#L631-42 assume 1 == ~t2_pc~0; 25169#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25170#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26086#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25962#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25963#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25563#L650-42 assume 1 == ~t3_pc~0; 25128#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25129#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26777#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25756#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25757#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26741#L669-42 assume !(1 == ~t4_pc~0); 25123#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 25124#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26552#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26442#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 26339#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26340#L688-42 assume !(1 == ~t5_pc~0); 26432#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 26632#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25266#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25267#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25341#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25155#L707-42 assume !(1 == ~t6_pc~0); 25156#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26815#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26557#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26558#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26307#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26308#L726-42 assume 1 == ~t7_pc~0; 26583#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26611#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26612#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26026#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26027#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26130#L745-42 assume 1 == ~t8_pc~0; 26166#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26168#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25494#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25141#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25142#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25867#L764-42 assume 1 == ~t9_pc~0; 26001#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26356#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26357#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25427#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25428#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25481#L783-42 assume 1 == ~t10_pc~0; 25097#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25098#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25693#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25826#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26843#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26527#L802-42 assume 1 == ~t11_pc~0; 25626#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25239#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25240#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25190#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25191#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26367#L821-42 assume 1 == ~t12_pc~0; 26368#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25733#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25093#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25094#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26073#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26060#L1339-3 assume !(1 == ~M_E~0); 26061#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26215#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26325#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25742#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25743#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26336#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26832#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26739#L1374-3 assume !(1 == ~T8_E~0); 25564#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25565#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25740#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25741#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25950#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26746#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26714#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26715#L1414-3 assume !(1 == ~E_3~0); 26770#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26529#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25448#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25449#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26335#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25376#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25377#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25493#L1454-3 assume !(1 == ~E_11~0); 26330#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26331#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25989#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25286#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25546#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25547#L1829 assume !(0 == start_simulation_~tmp~3#1); 25268#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25269#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26069#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26070#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26349#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26350#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25970#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25521#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 25522#L1810-2 [2022-02-21 04:23:17,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:17,665 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2022-02-21 04:23:17,665 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:17,665 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1546542319] [2022-02-21 04:23:17,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:17,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:17,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:17,685 INFO L290 TraceCheckUtils]: 0: Hoare triple {30449#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {30449#true} is VALID [2022-02-21 04:23:17,686 INFO L290 TraceCheckUtils]: 1: Hoare triple {30449#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {30451#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:17,686 INFO L290 TraceCheckUtils]: 2: Hoare triple {30451#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {30451#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:17,686 INFO L290 TraceCheckUtils]: 3: Hoare triple {30451#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {30451#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:17,686 INFO L290 TraceCheckUtils]: 4: Hoare triple {30451#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {30451#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:17,687 INFO L290 TraceCheckUtils]: 5: Hoare triple {30451#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {30451#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:17,687 INFO L290 TraceCheckUtils]: 6: Hoare triple {30451#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {30451#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:17,687 INFO L290 TraceCheckUtils]: 7: Hoare triple {30451#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {30451#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:17,687 INFO L290 TraceCheckUtils]: 8: Hoare triple {30451#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 9: Hoare triple {30450#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 10: Hoare triple {30450#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 11: Hoare triple {30450#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 12: Hoare triple {30450#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 13: Hoare triple {30450#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {30450#false} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 14: Hoare triple {30450#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 15: Hoare triple {30450#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 16: Hoare triple {30450#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,688 INFO L290 TraceCheckUtils]: 17: Hoare triple {30450#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {30450#false} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 18: Hoare triple {30450#false} assume !(0 == ~M_E~0); {30450#false} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 19: Hoare triple {30450#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {30450#false} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 20: Hoare triple {30450#false} assume !(0 == ~T2_E~0); {30450#false} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 21: Hoare triple {30450#false} assume !(0 == ~T3_E~0); {30450#false} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 22: Hoare triple {30450#false} assume !(0 == ~T4_E~0); {30450#false} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 23: Hoare triple {30450#false} assume !(0 == ~T5_E~0); {30450#false} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 24: Hoare triple {30450#false} assume !(0 == ~T6_E~0); {30450#false} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 25: Hoare triple {30450#false} assume !(0 == ~T7_E~0); {30450#false} is VALID [2022-02-21 04:23:17,689 INFO L290 TraceCheckUtils]: 26: Hoare triple {30450#false} assume !(0 == ~T8_E~0); {30450#false} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 27: Hoare triple {30450#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {30450#false} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 28: Hoare triple {30450#false} assume !(0 == ~T10_E~0); {30450#false} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 29: Hoare triple {30450#false} assume !(0 == ~T11_E~0); {30450#false} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 30: Hoare triple {30450#false} assume !(0 == ~T12_E~0); {30450#false} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 31: Hoare triple {30450#false} assume !(0 == ~E_M~0); {30450#false} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 32: Hoare triple {30450#false} assume !(0 == ~E_1~0); {30450#false} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 33: Hoare triple {30450#false} assume !(0 == ~E_2~0); {30450#false} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 34: Hoare triple {30450#false} assume !(0 == ~E_3~0); {30450#false} is VALID [2022-02-21 04:23:17,690 INFO L290 TraceCheckUtils]: 35: Hoare triple {30450#false} assume 0 == ~E_4~0;~E_4~0 := 1; {30450#false} is VALID [2022-02-21 04:23:17,691 INFO L290 TraceCheckUtils]: 36: Hoare triple {30450#false} assume !(0 == ~E_5~0); {30450#false} is VALID [2022-02-21 04:23:17,691 INFO L290 TraceCheckUtils]: 37: Hoare triple {30450#false} assume !(0 == ~E_6~0); {30450#false} is VALID [2022-02-21 04:23:17,691 INFO L290 TraceCheckUtils]: 38: Hoare triple {30450#false} assume !(0 == ~E_7~0); {30450#false} is VALID [2022-02-21 04:23:17,691 INFO L290 TraceCheckUtils]: 39: Hoare triple {30450#false} assume !(0 == ~E_8~0); {30450#false} is VALID [2022-02-21 04:23:17,691 INFO L290 TraceCheckUtils]: 40: Hoare triple {30450#false} assume !(0 == ~E_9~0); {30450#false} is VALID [2022-02-21 04:23:17,691 INFO L290 TraceCheckUtils]: 41: Hoare triple {30450#false} assume !(0 == ~E_10~0); {30450#false} is VALID [2022-02-21 04:23:17,691 INFO L290 TraceCheckUtils]: 42: Hoare triple {30450#false} assume !(0 == ~E_11~0); {30450#false} is VALID [2022-02-21 04:23:17,691 INFO L290 TraceCheckUtils]: 43: Hoare triple {30450#false} assume 0 == ~E_12~0;~E_12~0 := 1; {30450#false} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 44: Hoare triple {30450#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {30450#false} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 45: Hoare triple {30450#false} assume 1 == ~m_pc~0; {30450#false} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 46: Hoare triple {30450#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {30450#false} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 47: Hoare triple {30450#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {30450#false} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 48: Hoare triple {30450#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {30450#false} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 49: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp~1#1); {30450#false} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 50: Hoare triple {30450#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {30450#false} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 51: Hoare triple {30450#false} assume !(1 == ~t1_pc~0); {30450#false} is VALID [2022-02-21 04:23:17,692 INFO L290 TraceCheckUtils]: 52: Hoare triple {30450#false} is_transmit1_triggered_~__retres1~1#1 := 0; {30450#false} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 53: Hoare triple {30450#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {30450#false} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 54: Hoare triple {30450#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {30450#false} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 55: Hoare triple {30450#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {30450#false} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 56: Hoare triple {30450#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {30450#false} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 57: Hoare triple {30450#false} assume 1 == ~t2_pc~0; {30450#false} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 58: Hoare triple {30450#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {30450#false} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 59: Hoare triple {30450#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {30450#false} is VALID [2022-02-21 04:23:17,693 INFO L290 TraceCheckUtils]: 60: Hoare triple {30450#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {30450#false} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 61: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp___1~0#1); {30450#false} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 62: Hoare triple {30450#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {30450#false} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 63: Hoare triple {30450#false} assume !(1 == ~t3_pc~0); {30450#false} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 64: Hoare triple {30450#false} is_transmit3_triggered_~__retres1~3#1 := 0; {30450#false} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 65: Hoare triple {30450#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {30450#false} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 66: Hoare triple {30450#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {30450#false} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 67: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp___2~0#1); {30450#false} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 68: Hoare triple {30450#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {30450#false} is VALID [2022-02-21 04:23:17,694 INFO L290 TraceCheckUtils]: 69: Hoare triple {30450#false} assume 1 == ~t4_pc~0; {30450#false} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 70: Hoare triple {30450#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {30450#false} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 71: Hoare triple {30450#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {30450#false} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 72: Hoare triple {30450#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {30450#false} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 73: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp___3~0#1); {30450#false} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 74: Hoare triple {30450#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {30450#false} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 75: Hoare triple {30450#false} assume !(1 == ~t5_pc~0); {30450#false} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 76: Hoare triple {30450#false} is_transmit5_triggered_~__retres1~5#1 := 0; {30450#false} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 77: Hoare triple {30450#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {30450#false} is VALID [2022-02-21 04:23:17,695 INFO L290 TraceCheckUtils]: 78: Hoare triple {30450#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {30450#false} is VALID [2022-02-21 04:23:17,701 INFO L290 TraceCheckUtils]: 79: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp___4~0#1); {30450#false} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 80: Hoare triple {30450#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {30450#false} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 81: Hoare triple {30450#false} assume 1 == ~t6_pc~0; {30450#false} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 82: Hoare triple {30450#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {30450#false} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 83: Hoare triple {30450#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {30450#false} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 84: Hoare triple {30450#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {30450#false} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 85: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp___5~0#1); {30450#false} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 86: Hoare triple {30450#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {30450#false} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 87: Hoare triple {30450#false} assume 1 == ~t7_pc~0; {30450#false} is VALID [2022-02-21 04:23:17,702 INFO L290 TraceCheckUtils]: 88: Hoare triple {30450#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {30450#false} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 89: Hoare triple {30450#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {30450#false} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 90: Hoare triple {30450#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {30450#false} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 91: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp___6~0#1); {30450#false} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 92: Hoare triple {30450#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {30450#false} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 93: Hoare triple {30450#false} assume !(1 == ~t8_pc~0); {30450#false} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 94: Hoare triple {30450#false} is_transmit8_triggered_~__retres1~8#1 := 0; {30450#false} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 95: Hoare triple {30450#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {30450#false} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 96: Hoare triple {30450#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {30450#false} is VALID [2022-02-21 04:23:17,703 INFO L290 TraceCheckUtils]: 97: Hoare triple {30450#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {30450#false} is VALID [2022-02-21 04:23:17,704 INFO L290 TraceCheckUtils]: 98: Hoare triple {30450#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {30450#false} is VALID [2022-02-21 04:23:17,704 INFO L290 TraceCheckUtils]: 99: Hoare triple {30450#false} assume 1 == ~t9_pc~0; {30450#false} is VALID [2022-02-21 04:23:17,704 INFO L290 TraceCheckUtils]: 100: Hoare triple {30450#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {30450#false} is VALID [2022-02-21 04:23:17,704 INFO L290 TraceCheckUtils]: 101: Hoare triple {30450#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {30450#false} is VALID [2022-02-21 04:23:17,704 INFO L290 TraceCheckUtils]: 102: Hoare triple {30450#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {30450#false} is VALID [2022-02-21 04:23:17,704 INFO L290 TraceCheckUtils]: 103: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp___8~0#1); {30450#false} is VALID [2022-02-21 04:23:17,704 INFO L290 TraceCheckUtils]: 104: Hoare triple {30450#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {30450#false} is VALID [2022-02-21 04:23:17,704 INFO L290 TraceCheckUtils]: 105: Hoare triple {30450#false} assume !(1 == ~t10_pc~0); {30450#false} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 106: Hoare triple {30450#false} is_transmit10_triggered_~__retres1~10#1 := 0; {30450#false} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 107: Hoare triple {30450#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {30450#false} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 108: Hoare triple {30450#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {30450#false} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 109: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp___9~0#1); {30450#false} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 110: Hoare triple {30450#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {30450#false} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 111: Hoare triple {30450#false} assume 1 == ~t11_pc~0; {30450#false} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 112: Hoare triple {30450#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {30450#false} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 113: Hoare triple {30450#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {30450#false} is VALID [2022-02-21 04:23:17,705 INFO L290 TraceCheckUtils]: 114: Hoare triple {30450#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {30450#false} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 115: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp___10~0#1); {30450#false} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 116: Hoare triple {30450#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {30450#false} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 117: Hoare triple {30450#false} assume !(1 == ~t12_pc~0); {30450#false} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 118: Hoare triple {30450#false} is_transmit12_triggered_~__retres1~12#1 := 0; {30450#false} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 119: Hoare triple {30450#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {30450#false} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 120: Hoare triple {30450#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {30450#false} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 121: Hoare triple {30450#false} assume !(0 != activate_threads_~tmp___11~0#1); {30450#false} is VALID [2022-02-21 04:23:17,706 INFO L290 TraceCheckUtils]: 122: Hoare triple {30450#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {30450#false} is VALID [2022-02-21 04:23:17,707 INFO L290 TraceCheckUtils]: 123: Hoare triple {30450#false} assume !(1 == ~M_E~0); {30450#false} is VALID [2022-02-21 04:23:17,707 INFO L290 TraceCheckUtils]: 124: Hoare triple {30450#false} assume !(1 == ~T1_E~0); {30450#false} is VALID [2022-02-21 04:23:17,707 INFO L290 TraceCheckUtils]: 125: Hoare triple {30450#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,707 INFO L290 TraceCheckUtils]: 126: Hoare triple {30450#false} assume !(1 == ~T3_E~0); {30450#false} is VALID [2022-02-21 04:23:17,707 INFO L290 TraceCheckUtils]: 127: Hoare triple {30450#false} assume !(1 == ~T4_E~0); {30450#false} is VALID [2022-02-21 04:23:17,707 INFO L290 TraceCheckUtils]: 128: Hoare triple {30450#false} assume !(1 == ~T5_E~0); {30450#false} is VALID [2022-02-21 04:23:17,707 INFO L290 TraceCheckUtils]: 129: Hoare triple {30450#false} assume !(1 == ~T6_E~0); {30450#false} is VALID [2022-02-21 04:23:17,707 INFO L290 TraceCheckUtils]: 130: Hoare triple {30450#false} assume !(1 == ~T7_E~0); {30450#false} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 131: Hoare triple {30450#false} assume !(1 == ~T8_E~0); {30450#false} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 132: Hoare triple {30450#false} assume !(1 == ~T9_E~0); {30450#false} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 133: Hoare triple {30450#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 134: Hoare triple {30450#false} assume !(1 == ~T11_E~0); {30450#false} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 135: Hoare triple {30450#false} assume !(1 == ~T12_E~0); {30450#false} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 136: Hoare triple {30450#false} assume !(1 == ~E_M~0); {30450#false} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 137: Hoare triple {30450#false} assume !(1 == ~E_1~0); {30450#false} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 138: Hoare triple {30450#false} assume !(1 == ~E_2~0); {30450#false} is VALID [2022-02-21 04:23:17,708 INFO L290 TraceCheckUtils]: 139: Hoare triple {30450#false} assume !(1 == ~E_3~0); {30450#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 140: Hoare triple {30450#false} assume !(1 == ~E_4~0); {30450#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 141: Hoare triple {30450#false} assume 1 == ~E_5~0;~E_5~0 := 2; {30450#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 142: Hoare triple {30450#false} assume !(1 == ~E_6~0); {30450#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 143: Hoare triple {30450#false} assume !(1 == ~E_7~0); {30450#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 144: Hoare triple {30450#false} assume !(1 == ~E_8~0); {30450#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 145: Hoare triple {30450#false} assume !(1 == ~E_9~0); {30450#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 146: Hoare triple {30450#false} assume !(1 == ~E_10~0); {30450#false} is VALID [2022-02-21 04:23:17,709 INFO L290 TraceCheckUtils]: 147: Hoare triple {30450#false} assume !(1 == ~E_11~0); {30450#false} is VALID [2022-02-21 04:23:17,710 INFO L290 TraceCheckUtils]: 148: Hoare triple {30450#false} assume !(1 == ~E_12~0); {30450#false} is VALID [2022-02-21 04:23:17,710 INFO L290 TraceCheckUtils]: 149: Hoare triple {30450#false} assume { :end_inline_reset_delta_events } true; {30450#false} is VALID [2022-02-21 04:23:17,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:17,710 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:17,710 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1546542319] [2022-02-21 04:23:17,710 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1546542319] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:17,711 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:17,711 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:17,711 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1968239887] [2022-02-21 04:23:17,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:17,711 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:17,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:17,712 INFO L85 PathProgramCache]: Analyzing trace with hash -1973331501, now seen corresponding path program 1 times [2022-02-21 04:23:17,712 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:17,712 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848914029] [2022-02-21 04:23:17,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:17,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:17,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:17,740 INFO L290 TraceCheckUtils]: 0: Hoare triple {30452#true} assume !false; {30452#true} is VALID [2022-02-21 04:23:17,740 INFO L290 TraceCheckUtils]: 1: Hoare triple {30452#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {30452#true} is VALID [2022-02-21 04:23:17,741 INFO L290 TraceCheckUtils]: 2: Hoare triple {30452#true} assume !false; {30452#true} is VALID [2022-02-21 04:23:17,741 INFO L290 TraceCheckUtils]: 3: Hoare triple {30452#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {30452#true} is VALID [2022-02-21 04:23:17,741 INFO L290 TraceCheckUtils]: 4: Hoare triple {30452#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {30452#true} is VALID [2022-02-21 04:23:17,741 INFO L290 TraceCheckUtils]: 5: Hoare triple {30452#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {30452#true} is VALID [2022-02-21 04:23:17,741 INFO L290 TraceCheckUtils]: 6: Hoare triple {30452#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {30452#true} is VALID [2022-02-21 04:23:17,741 INFO L290 TraceCheckUtils]: 7: Hoare triple {30452#true} assume !(0 != eval_~tmp~0#1); {30452#true} is VALID [2022-02-21 04:23:17,741 INFO L290 TraceCheckUtils]: 8: Hoare triple {30452#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {30452#true} is VALID [2022-02-21 04:23:17,741 INFO L290 TraceCheckUtils]: 9: Hoare triple {30452#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {30452#true} is VALID [2022-02-21 04:23:17,742 INFO L290 TraceCheckUtils]: 10: Hoare triple {30452#true} assume 0 == ~M_E~0;~M_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,742 INFO L290 TraceCheckUtils]: 11: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,742 INFO L290 TraceCheckUtils]: 12: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,743 INFO L290 TraceCheckUtils]: 13: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,743 INFO L290 TraceCheckUtils]: 14: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,743 INFO L290 TraceCheckUtils]: 15: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,743 INFO L290 TraceCheckUtils]: 16: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,744 INFO L290 TraceCheckUtils]: 17: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,744 INFO L290 TraceCheckUtils]: 18: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,744 INFO L290 TraceCheckUtils]: 19: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,744 INFO L290 TraceCheckUtils]: 20: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,745 INFO L290 TraceCheckUtils]: 21: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,745 INFO L290 TraceCheckUtils]: 22: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,745 INFO L290 TraceCheckUtils]: 23: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,745 INFO L290 TraceCheckUtils]: 24: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,746 INFO L290 TraceCheckUtils]: 25: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,746 INFO L290 TraceCheckUtils]: 26: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,746 INFO L290 TraceCheckUtils]: 27: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,746 INFO L290 TraceCheckUtils]: 28: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,747 INFO L290 TraceCheckUtils]: 29: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,747 INFO L290 TraceCheckUtils]: 30: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,747 INFO L290 TraceCheckUtils]: 31: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,747 INFO L290 TraceCheckUtils]: 32: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,748 INFO L290 TraceCheckUtils]: 33: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,748 INFO L290 TraceCheckUtils]: 34: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,748 INFO L290 TraceCheckUtils]: 35: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,749 INFO L290 TraceCheckUtils]: 36: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,749 INFO L290 TraceCheckUtils]: 37: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,749 INFO L290 TraceCheckUtils]: 38: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,749 INFO L290 TraceCheckUtils]: 39: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,750 INFO L290 TraceCheckUtils]: 40: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,750 INFO L290 TraceCheckUtils]: 41: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,750 INFO L290 TraceCheckUtils]: 42: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,750 INFO L290 TraceCheckUtils]: 43: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,751 INFO L290 TraceCheckUtils]: 44: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,751 INFO L290 TraceCheckUtils]: 45: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,751 INFO L290 TraceCheckUtils]: 46: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,751 INFO L290 TraceCheckUtils]: 47: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,752 INFO L290 TraceCheckUtils]: 48: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,752 INFO L290 TraceCheckUtils]: 49: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,752 INFO L290 TraceCheckUtils]: 50: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,752 INFO L290 TraceCheckUtils]: 51: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,753 INFO L290 TraceCheckUtils]: 52: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,753 INFO L290 TraceCheckUtils]: 53: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,753 INFO L290 TraceCheckUtils]: 54: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,753 INFO L290 TraceCheckUtils]: 55: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,754 INFO L290 TraceCheckUtils]: 56: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,754 INFO L290 TraceCheckUtils]: 57: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,754 INFO L290 TraceCheckUtils]: 58: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,754 INFO L290 TraceCheckUtils]: 59: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,755 INFO L290 TraceCheckUtils]: 60: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,755 INFO L290 TraceCheckUtils]: 61: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,755 INFO L290 TraceCheckUtils]: 62: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,755 INFO L290 TraceCheckUtils]: 63: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,756 INFO L290 TraceCheckUtils]: 64: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,756 INFO L290 TraceCheckUtils]: 65: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,756 INFO L290 TraceCheckUtils]: 66: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,757 INFO L290 TraceCheckUtils]: 67: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,757 INFO L290 TraceCheckUtils]: 68: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,757 INFO L290 TraceCheckUtils]: 69: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,757 INFO L290 TraceCheckUtils]: 70: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,758 INFO L290 TraceCheckUtils]: 71: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,758 INFO L290 TraceCheckUtils]: 72: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,758 INFO L290 TraceCheckUtils]: 73: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,758 INFO L290 TraceCheckUtils]: 74: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,759 INFO L290 TraceCheckUtils]: 75: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,759 INFO L290 TraceCheckUtils]: 76: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,759 INFO L290 TraceCheckUtils]: 77: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,759 INFO L290 TraceCheckUtils]: 78: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,760 INFO L290 TraceCheckUtils]: 79: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,760 INFO L290 TraceCheckUtils]: 80: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,760 INFO L290 TraceCheckUtils]: 81: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,760 INFO L290 TraceCheckUtils]: 82: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,761 INFO L290 TraceCheckUtils]: 83: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,761 INFO L290 TraceCheckUtils]: 84: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,761 INFO L290 TraceCheckUtils]: 85: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,761 INFO L290 TraceCheckUtils]: 86: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,762 INFO L290 TraceCheckUtils]: 87: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,762 INFO L290 TraceCheckUtils]: 88: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,762 INFO L290 TraceCheckUtils]: 89: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,762 INFO L290 TraceCheckUtils]: 90: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,763 INFO L290 TraceCheckUtils]: 91: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,763 INFO L290 TraceCheckUtils]: 92: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,763 INFO L290 TraceCheckUtils]: 93: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,763 INFO L290 TraceCheckUtils]: 94: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,764 INFO L290 TraceCheckUtils]: 95: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,764 INFO L290 TraceCheckUtils]: 96: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,764 INFO L290 TraceCheckUtils]: 97: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,764 INFO L290 TraceCheckUtils]: 98: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,765 INFO L290 TraceCheckUtils]: 99: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,765 INFO L290 TraceCheckUtils]: 100: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,765 INFO L290 TraceCheckUtils]: 101: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,765 INFO L290 TraceCheckUtils]: 102: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,766 INFO L290 TraceCheckUtils]: 103: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,766 INFO L290 TraceCheckUtils]: 104: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,766 INFO L290 TraceCheckUtils]: 105: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,766 INFO L290 TraceCheckUtils]: 106: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,767 INFO L290 TraceCheckUtils]: 107: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,767 INFO L290 TraceCheckUtils]: 108: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,767 INFO L290 TraceCheckUtils]: 109: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,768 INFO L290 TraceCheckUtils]: 110: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,768 INFO L290 TraceCheckUtils]: 111: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,768 INFO L290 TraceCheckUtils]: 112: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,768 INFO L290 TraceCheckUtils]: 113: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,769 INFO L290 TraceCheckUtils]: 114: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {30454#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:17,769 INFO L290 TraceCheckUtils]: 115: Hoare triple {30454#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {30453#false} is VALID [2022-02-21 04:23:17,769 INFO L290 TraceCheckUtils]: 116: Hoare triple {30453#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,769 INFO L290 TraceCheckUtils]: 117: Hoare triple {30453#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,769 INFO L290 TraceCheckUtils]: 118: Hoare triple {30453#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,769 INFO L290 TraceCheckUtils]: 119: Hoare triple {30453#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,769 INFO L290 TraceCheckUtils]: 120: Hoare triple {30453#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,770 INFO L290 TraceCheckUtils]: 121: Hoare triple {30453#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,770 INFO L290 TraceCheckUtils]: 122: Hoare triple {30453#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,770 INFO L290 TraceCheckUtils]: 123: Hoare triple {30453#false} assume !(1 == ~T8_E~0); {30453#false} is VALID [2022-02-21 04:23:17,770 INFO L290 TraceCheckUtils]: 124: Hoare triple {30453#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,770 INFO L290 TraceCheckUtils]: 125: Hoare triple {30453#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,770 INFO L290 TraceCheckUtils]: 126: Hoare triple {30453#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,770 INFO L290 TraceCheckUtils]: 127: Hoare triple {30453#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,770 INFO L290 TraceCheckUtils]: 128: Hoare triple {30453#false} assume 1 == ~E_M~0;~E_M~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,771 INFO L290 TraceCheckUtils]: 129: Hoare triple {30453#false} assume 1 == ~E_1~0;~E_1~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,771 INFO L290 TraceCheckUtils]: 130: Hoare triple {30453#false} assume 1 == ~E_2~0;~E_2~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,771 INFO L290 TraceCheckUtils]: 131: Hoare triple {30453#false} assume !(1 == ~E_3~0); {30453#false} is VALID [2022-02-21 04:23:17,771 INFO L290 TraceCheckUtils]: 132: Hoare triple {30453#false} assume 1 == ~E_4~0;~E_4~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,771 INFO L290 TraceCheckUtils]: 133: Hoare triple {30453#false} assume 1 == ~E_5~0;~E_5~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,771 INFO L290 TraceCheckUtils]: 134: Hoare triple {30453#false} assume 1 == ~E_6~0;~E_6~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,771 INFO L290 TraceCheckUtils]: 135: Hoare triple {30453#false} assume 1 == ~E_7~0;~E_7~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,771 INFO L290 TraceCheckUtils]: 136: Hoare triple {30453#false} assume 1 == ~E_8~0;~E_8~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,771 INFO L290 TraceCheckUtils]: 137: Hoare triple {30453#false} assume 1 == ~E_9~0;~E_9~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,772 INFO L290 TraceCheckUtils]: 138: Hoare triple {30453#false} assume 1 == ~E_10~0;~E_10~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,772 INFO L290 TraceCheckUtils]: 139: Hoare triple {30453#false} assume !(1 == ~E_11~0); {30453#false} is VALID [2022-02-21 04:23:17,772 INFO L290 TraceCheckUtils]: 140: Hoare triple {30453#false} assume 1 == ~E_12~0;~E_12~0 := 2; {30453#false} is VALID [2022-02-21 04:23:17,772 INFO L290 TraceCheckUtils]: 141: Hoare triple {30453#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {30453#false} is VALID [2022-02-21 04:23:17,772 INFO L290 TraceCheckUtils]: 142: Hoare triple {30453#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {30453#false} is VALID [2022-02-21 04:23:17,772 INFO L290 TraceCheckUtils]: 143: Hoare triple {30453#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {30453#false} is VALID [2022-02-21 04:23:17,772 INFO L290 TraceCheckUtils]: 144: Hoare triple {30453#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {30453#false} is VALID [2022-02-21 04:23:17,772 INFO L290 TraceCheckUtils]: 145: Hoare triple {30453#false} assume !(0 == start_simulation_~tmp~3#1); {30453#false} is VALID [2022-02-21 04:23:17,772 INFO L290 TraceCheckUtils]: 146: Hoare triple {30453#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {30453#false} is VALID [2022-02-21 04:23:17,773 INFO L290 TraceCheckUtils]: 147: Hoare triple {30453#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {30453#false} is VALID [2022-02-21 04:23:17,773 INFO L290 TraceCheckUtils]: 148: Hoare triple {30453#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {30453#false} is VALID [2022-02-21 04:23:17,773 INFO L290 TraceCheckUtils]: 149: Hoare triple {30453#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {30453#false} is VALID [2022-02-21 04:23:17,773 INFO L290 TraceCheckUtils]: 150: Hoare triple {30453#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {30453#false} is VALID [2022-02-21 04:23:17,773 INFO L290 TraceCheckUtils]: 151: Hoare triple {30453#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {30453#false} is VALID [2022-02-21 04:23:17,773 INFO L290 TraceCheckUtils]: 152: Hoare triple {30453#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {30453#false} is VALID [2022-02-21 04:23:17,773 INFO L290 TraceCheckUtils]: 153: Hoare triple {30453#false} assume !(0 != start_simulation_~tmp___0~1#1); {30453#false} is VALID [2022-02-21 04:23:17,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:17,774 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:17,774 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848914029] [2022-02-21 04:23:17,774 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848914029] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:17,774 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:17,774 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:17,775 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268664890] [2022-02-21 04:23:17,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:17,775 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:17,775 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:17,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:17,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:17,776 INFO L87 Difference]: Start difference. First operand 1788 states and 2648 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,023 INFO L93 Difference]: Finished difference Result 1788 states and 2647 transitions. [2022-02-21 04:23:19,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:19,023 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,114 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:19,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2647 transitions. [2022-02-21 04:23:19,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:19,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2647 transitions. [2022-02-21 04:23:19,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:19,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:19,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2647 transitions. [2022-02-21 04:23:19,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:19,270 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2022-02-21 04:23:19,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2647 transitions. [2022-02-21 04:23:19,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:19,338 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:19,340 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2647 transitions. Second operand has 1788 states, 1788 states have (on average 1.4804250559284116) internal successors, (2647), 1787 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,342 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2647 transitions. Second operand has 1788 states, 1788 states have (on average 1.4804250559284116) internal successors, (2647), 1787 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,344 INFO L87 Difference]: Start difference. First operand 1788 states and 2647 transitions. Second operand has 1788 states, 1788 states have (on average 1.4804250559284116) internal successors, (2647), 1787 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,423 INFO L93 Difference]: Finished difference Result 1788 states and 2647 transitions. [2022-02-21 04:23:19,423 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2647 transitions. [2022-02-21 04:23:19,426 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:19,426 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:19,429 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4804250559284116) internal successors, (2647), 1787 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2647 transitions. [2022-02-21 04:23:19,431 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4804250559284116) internal successors, (2647), 1787 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2647 transitions. [2022-02-21 04:23:19,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,500 INFO L93 Difference]: Finished difference Result 1788 states and 2647 transitions. [2022-02-21 04:23:19,500 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2647 transitions. [2022-02-21 04:23:19,502 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:19,502 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:19,502 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:19,502 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:19,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4804250559284116) internal successors, (2647), 1787 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2647 transitions. [2022-02-21 04:23:19,569 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2022-02-21 04:23:19,570 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2022-02-21 04:23:19,570 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:23:19,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2647 transitions. [2022-02-21 04:23:19,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:19,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:19,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:19,574 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:19,574 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:19,575 INFO L791 eck$LassoCheckResult]: Stem: 33032#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 33033#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32553#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32554#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32608#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 33947#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33041#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32844#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32243#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32244#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 33466#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 33577#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 34013#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 34014#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32972#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32973#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33495#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33414#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33007#L1201 assume !(0 == ~M_E~0); 33008#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33854#L1206-1 assume !(0 == ~T2_E~0); 33840#L1211-1 assume !(0 == ~T3_E~0); 33841#L1216-1 assume !(0 == ~T4_E~0); 32828#L1221-1 assume !(0 == ~T5_E~0); 32829#L1226-1 assume !(0 == ~T6_E~0); 32468#L1231-1 assume !(0 == ~T7_E~0); 32469#L1236-1 assume !(0 == ~T8_E~0); 33877#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32865#L1246-1 assume !(0 == ~T10_E~0); 32866#L1251-1 assume !(0 == ~T11_E~0); 33005#L1256-1 assume !(0 == ~T12_E~0); 32254#L1261-1 assume !(0 == ~E_M~0); 32255#L1266-1 assume !(0 == ~E_1~0); 33999#L1271-1 assume !(0 == ~E_2~0); 33561#L1276-1 assume !(0 == ~E_3~0); 33562#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33509#L1286-1 assume !(0 == ~E_5~0); 32719#L1291-1 assume !(0 == ~E_6~0); 32720#L1296-1 assume !(0 == ~E_7~0); 33295#L1301-1 assume !(0 == ~E_8~0); 33296#L1306-1 assume !(0 == ~E_9~0); 33776#L1311-1 assume !(0 == ~E_10~0); 32670#L1316-1 assume !(0 == ~E_11~0); 32671#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 33313#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33314#L593 assume 1 == ~m_pc~0; 33458#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32560#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33986#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33520#L1492 assume !(0 != activate_threads_~tmp~1#1); 33521#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33812#L612 assume !(1 == ~t1_pc~0); 33813#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33942#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32942#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32564#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32565#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32984#L631 assume 1 == ~t2_pc~0; 32919#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32341#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32342#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33178#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 33179#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32637#L650 assume !(1 == ~t3_pc~0); 32638#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33338#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32561#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32294#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 32295#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33487#L669 assume 1 == ~t4_pc~0; 33488#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33846#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32971#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32503#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 32504#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32728#L688 assume !(1 == ~t5_pc~0); 32519#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32520#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33438#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33372#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 33373#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33502#L707 assume 1 == ~t6_pc~0; 33911#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33148#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33149#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33909#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 33444#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33006#L726 assume 1 == ~t7_pc~0; 32905#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32604#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33645#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33919#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 32373#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32374#L745 assume !(1 == ~t8_pc~0); 32821#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32840#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33678#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33226#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33227#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33737#L764 assume 1 == ~t9_pc~0; 33004#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32846#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33523#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33970#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 32393#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32394#L783 assume !(1 == ~t10_pc~0); 32455#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32456#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32497#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32498#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 32960#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33848#L802 assume 1 == ~t11_pc~0; 33830#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32338#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32339#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32830#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 32831#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32941#L821 assume !(1 == ~t12_pc~0); 33192#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33288#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32343#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32344#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 33886#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33532#L1339 assume !(1 == ~M_E~0); 33533#L1339-2 assume !(1 == ~T1_E~0); 33921#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33922#L1349-1 assume !(1 == ~T3_E~0); 33306#L1354-1 assume !(1 == ~T4_E~0); 33307#L1359-1 assume !(1 == ~T5_E~0); 33708#L1364-1 assume !(1 == ~T6_E~0); 32771#L1369-1 assume !(1 == ~T7_E~0); 32772#L1374-1 assume !(1 == ~T8_E~0); 33309#L1379-1 assume !(1 == ~T9_E~0); 33310#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33409#L1389-1 assume !(1 == ~T11_E~0); 33880#L1394-1 assume !(1 == ~T12_E~0); 33881#L1399-1 assume !(1 == ~E_M~0); 33971#L1404-1 assume !(1 == ~E_1~0); 32870#L1409-1 assume !(1 == ~E_2~0); 32871#L1414-1 assume !(1 == ~E_3~0); 33597#L1419-1 assume !(1 == ~E_4~0); 32511#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 32512#L1429-1 assume !(1 == ~E_6~0); 33322#L1434-1 assume !(1 == ~E_7~0); 33901#L1439-1 assume !(1 == ~E_8~0); 32549#L1444-1 assume !(1 == ~E_9~0); 32550#L1449-1 assume !(1 == ~E_10~0); 32924#L1454-1 assume !(1 == ~E_11~0); 32925#L1459-1 assume !(1 == ~E_12~0); 33443#L1464-1 assume { :end_inline_reset_delta_events } true; 32683#L1810-2 [2022-02-21 04:23:19,575 INFO L793 eck$LassoCheckResult]: Loop: 32683#L1810-2 assume !false; 33127#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33043#L1176 assume !false; 33605#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33175#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32381#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32931#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32932#L1003 assume !(0 != eval_~tmp~0#1); 32573#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32574#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33764#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33547#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33548#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33441#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32632#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32633#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33099#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32703#L1231-3 assume !(0 == ~T7_E~0); 32704#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32950#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33932#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33833#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33538#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32649#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32650#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32695#L1271-3 assume !(0 == ~E_2~0); 32696#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33072#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33073#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33594#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33595#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34010#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33967#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33184#L1311-3 assume !(0 == ~E_10~0); 32575#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32576#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32651#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33287#L593-42 assume 1 == ~m_pc~0; 33680#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33446#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33995#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33996#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32474#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32475#L612-42 assume !(1 == ~t1_pc~0); 33396#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 33789#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33910#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32562#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32563#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33258#L631-42 assume 1 == ~t2_pc~0; 32327#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32328#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33247#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33123#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33124#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32724#L650-42 assume !(1 == ~t3_pc~0); 32288#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 32287#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33938#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32917#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32918#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33902#L669-42 assume !(1 == ~t4_pc~0); 32284#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32285#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33713#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33603#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 33500#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33501#L688-42 assume 1 == ~t5_pc~0; 33592#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33793#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32425#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32426#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32502#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32316#L707-42 assume !(1 == ~t6_pc~0); 32317#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 33974#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33718#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33719#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33468#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33469#L726-42 assume 1 == ~t7_pc~0; 33746#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33772#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33773#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33187#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33188#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33291#L745-42 assume 1 == ~t8_pc~0; 33328#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33330#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32657#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32302#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32303#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33028#L764-42 assume 1 == ~t9_pc~0; 33164#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33517#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33518#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32588#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32589#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32642#L783-42 assume 1 == ~t10_pc~0; 32258#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32259#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32854#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32987#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34004#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33688#L802-42 assume 1 == ~t11_pc~0; 32789#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32400#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32401#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32351#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32352#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33528#L821-42 assume 1 == ~t12_pc~0; 33529#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32894#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32256#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32257#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33234#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33224#L1339-3 assume !(1 == ~M_E~0); 33225#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33376#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33486#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32903#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32904#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33497#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33993#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33900#L1374-3 assume !(1 == ~T8_E~0); 32725#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32726#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32901#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32902#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33111#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33907#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33875#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33876#L1414-3 assume !(1 == ~E_3~0); 33931#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33690#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32609#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32610#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33496#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32537#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32538#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32654#L1454-3 assume !(1 == ~E_11~0); 33491#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33492#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33150#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32447#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32707#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32708#L1829 assume !(0 == start_simulation_~tmp~3#1); 32429#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32430#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33230#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33231#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 33510#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33511#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33131#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32682#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 32683#L1810-2 [2022-02-21 04:23:19,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:19,576 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2022-02-21 04:23:19,576 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:19,576 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1258408787] [2022-02-21 04:23:19,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:19,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:19,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:19,597 INFO L290 TraceCheckUtils]: 0: Hoare triple {37610#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {37610#true} is VALID [2022-02-21 04:23:19,597 INFO L290 TraceCheckUtils]: 1: Hoare triple {37610#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {37612#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:19,597 INFO L290 TraceCheckUtils]: 2: Hoare triple {37612#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {37612#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:19,598 INFO L290 TraceCheckUtils]: 3: Hoare triple {37612#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {37612#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:19,598 INFO L290 TraceCheckUtils]: 4: Hoare triple {37612#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {37612#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:19,598 INFO L290 TraceCheckUtils]: 5: Hoare triple {37612#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {37612#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:19,598 INFO L290 TraceCheckUtils]: 6: Hoare triple {37612#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {37612#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:19,599 INFO L290 TraceCheckUtils]: 7: Hoare triple {37612#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {37612#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:19,599 INFO L290 TraceCheckUtils]: 8: Hoare triple {37612#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {37612#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:19,599 INFO L290 TraceCheckUtils]: 9: Hoare triple {37612#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {37611#false} is VALID [2022-02-21 04:23:19,599 INFO L290 TraceCheckUtils]: 10: Hoare triple {37611#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {37611#false} is VALID [2022-02-21 04:23:19,599 INFO L290 TraceCheckUtils]: 11: Hoare triple {37611#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {37611#false} is VALID [2022-02-21 04:23:19,599 INFO L290 TraceCheckUtils]: 12: Hoare triple {37611#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {37611#false} is VALID [2022-02-21 04:23:19,600 INFO L290 TraceCheckUtils]: 13: Hoare triple {37611#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {37611#false} is VALID [2022-02-21 04:23:19,600 INFO L290 TraceCheckUtils]: 14: Hoare triple {37611#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {37611#false} is VALID [2022-02-21 04:23:19,600 INFO L290 TraceCheckUtils]: 15: Hoare triple {37611#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {37611#false} is VALID [2022-02-21 04:23:19,600 INFO L290 TraceCheckUtils]: 16: Hoare triple {37611#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {37611#false} is VALID [2022-02-21 04:23:19,600 INFO L290 TraceCheckUtils]: 17: Hoare triple {37611#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {37611#false} is VALID [2022-02-21 04:23:19,600 INFO L290 TraceCheckUtils]: 18: Hoare triple {37611#false} assume !(0 == ~M_E~0); {37611#false} is VALID [2022-02-21 04:23:19,600 INFO L290 TraceCheckUtils]: 19: Hoare triple {37611#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {37611#false} is VALID [2022-02-21 04:23:19,600 INFO L290 TraceCheckUtils]: 20: Hoare triple {37611#false} assume !(0 == ~T2_E~0); {37611#false} is VALID [2022-02-21 04:23:19,601 INFO L290 TraceCheckUtils]: 21: Hoare triple {37611#false} assume !(0 == ~T3_E~0); {37611#false} is VALID [2022-02-21 04:23:19,601 INFO L290 TraceCheckUtils]: 22: Hoare triple {37611#false} assume !(0 == ~T4_E~0); {37611#false} is VALID [2022-02-21 04:23:19,601 INFO L290 TraceCheckUtils]: 23: Hoare triple {37611#false} assume !(0 == ~T5_E~0); {37611#false} is VALID [2022-02-21 04:23:19,601 INFO L290 TraceCheckUtils]: 24: Hoare triple {37611#false} assume !(0 == ~T6_E~0); {37611#false} is VALID [2022-02-21 04:23:19,601 INFO L290 TraceCheckUtils]: 25: Hoare triple {37611#false} assume !(0 == ~T7_E~0); {37611#false} is VALID [2022-02-21 04:23:19,601 INFO L290 TraceCheckUtils]: 26: Hoare triple {37611#false} assume !(0 == ~T8_E~0); {37611#false} is VALID [2022-02-21 04:23:19,601 INFO L290 TraceCheckUtils]: 27: Hoare triple {37611#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {37611#false} is VALID [2022-02-21 04:23:19,601 INFO L290 TraceCheckUtils]: 28: Hoare triple {37611#false} assume !(0 == ~T10_E~0); {37611#false} is VALID [2022-02-21 04:23:19,601 INFO L290 TraceCheckUtils]: 29: Hoare triple {37611#false} assume !(0 == ~T11_E~0); {37611#false} is VALID [2022-02-21 04:23:19,602 INFO L290 TraceCheckUtils]: 30: Hoare triple {37611#false} assume !(0 == ~T12_E~0); {37611#false} is VALID [2022-02-21 04:23:19,602 INFO L290 TraceCheckUtils]: 31: Hoare triple {37611#false} assume !(0 == ~E_M~0); {37611#false} is VALID [2022-02-21 04:23:19,602 INFO L290 TraceCheckUtils]: 32: Hoare triple {37611#false} assume !(0 == ~E_1~0); {37611#false} is VALID [2022-02-21 04:23:19,602 INFO L290 TraceCheckUtils]: 33: Hoare triple {37611#false} assume !(0 == ~E_2~0); {37611#false} is VALID [2022-02-21 04:23:19,602 INFO L290 TraceCheckUtils]: 34: Hoare triple {37611#false} assume !(0 == ~E_3~0); {37611#false} is VALID [2022-02-21 04:23:19,602 INFO L290 TraceCheckUtils]: 35: Hoare triple {37611#false} assume 0 == ~E_4~0;~E_4~0 := 1; {37611#false} is VALID [2022-02-21 04:23:19,602 INFO L290 TraceCheckUtils]: 36: Hoare triple {37611#false} assume !(0 == ~E_5~0); {37611#false} is VALID [2022-02-21 04:23:19,602 INFO L290 TraceCheckUtils]: 37: Hoare triple {37611#false} assume !(0 == ~E_6~0); {37611#false} is VALID [2022-02-21 04:23:19,602 INFO L290 TraceCheckUtils]: 38: Hoare triple {37611#false} assume !(0 == ~E_7~0); {37611#false} is VALID [2022-02-21 04:23:19,603 INFO L290 TraceCheckUtils]: 39: Hoare triple {37611#false} assume !(0 == ~E_8~0); {37611#false} is VALID [2022-02-21 04:23:19,603 INFO L290 TraceCheckUtils]: 40: Hoare triple {37611#false} assume !(0 == ~E_9~0); {37611#false} is VALID [2022-02-21 04:23:19,603 INFO L290 TraceCheckUtils]: 41: Hoare triple {37611#false} assume !(0 == ~E_10~0); {37611#false} is VALID [2022-02-21 04:23:19,603 INFO L290 TraceCheckUtils]: 42: Hoare triple {37611#false} assume !(0 == ~E_11~0); {37611#false} is VALID [2022-02-21 04:23:19,603 INFO L290 TraceCheckUtils]: 43: Hoare triple {37611#false} assume 0 == ~E_12~0;~E_12~0 := 1; {37611#false} is VALID [2022-02-21 04:23:19,603 INFO L290 TraceCheckUtils]: 44: Hoare triple {37611#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37611#false} is VALID [2022-02-21 04:23:19,603 INFO L290 TraceCheckUtils]: 45: Hoare triple {37611#false} assume 1 == ~m_pc~0; {37611#false} is VALID [2022-02-21 04:23:19,603 INFO L290 TraceCheckUtils]: 46: Hoare triple {37611#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {37611#false} is VALID [2022-02-21 04:23:19,603 INFO L290 TraceCheckUtils]: 47: Hoare triple {37611#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37611#false} is VALID [2022-02-21 04:23:19,604 INFO L290 TraceCheckUtils]: 48: Hoare triple {37611#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {37611#false} is VALID [2022-02-21 04:23:19,604 INFO L290 TraceCheckUtils]: 49: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp~1#1); {37611#false} is VALID [2022-02-21 04:23:19,604 INFO L290 TraceCheckUtils]: 50: Hoare triple {37611#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37611#false} is VALID [2022-02-21 04:23:19,604 INFO L290 TraceCheckUtils]: 51: Hoare triple {37611#false} assume !(1 == ~t1_pc~0); {37611#false} is VALID [2022-02-21 04:23:19,604 INFO L290 TraceCheckUtils]: 52: Hoare triple {37611#false} is_transmit1_triggered_~__retres1~1#1 := 0; {37611#false} is VALID [2022-02-21 04:23:19,604 INFO L290 TraceCheckUtils]: 53: Hoare triple {37611#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37611#false} is VALID [2022-02-21 04:23:19,604 INFO L290 TraceCheckUtils]: 54: Hoare triple {37611#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {37611#false} is VALID [2022-02-21 04:23:19,604 INFO L290 TraceCheckUtils]: 55: Hoare triple {37611#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {37611#false} is VALID [2022-02-21 04:23:19,604 INFO L290 TraceCheckUtils]: 56: Hoare triple {37611#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37611#false} is VALID [2022-02-21 04:23:19,605 INFO L290 TraceCheckUtils]: 57: Hoare triple {37611#false} assume 1 == ~t2_pc~0; {37611#false} is VALID [2022-02-21 04:23:19,605 INFO L290 TraceCheckUtils]: 58: Hoare triple {37611#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {37611#false} is VALID [2022-02-21 04:23:19,605 INFO L290 TraceCheckUtils]: 59: Hoare triple {37611#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37611#false} is VALID [2022-02-21 04:23:19,605 INFO L290 TraceCheckUtils]: 60: Hoare triple {37611#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {37611#false} is VALID [2022-02-21 04:23:19,605 INFO L290 TraceCheckUtils]: 61: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp___1~0#1); {37611#false} is VALID [2022-02-21 04:23:19,605 INFO L290 TraceCheckUtils]: 62: Hoare triple {37611#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37611#false} is VALID [2022-02-21 04:23:19,605 INFO L290 TraceCheckUtils]: 63: Hoare triple {37611#false} assume !(1 == ~t3_pc~0); {37611#false} is VALID [2022-02-21 04:23:19,605 INFO L290 TraceCheckUtils]: 64: Hoare triple {37611#false} is_transmit3_triggered_~__retres1~3#1 := 0; {37611#false} is VALID [2022-02-21 04:23:19,605 INFO L290 TraceCheckUtils]: 65: Hoare triple {37611#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37611#false} is VALID [2022-02-21 04:23:19,606 INFO L290 TraceCheckUtils]: 66: Hoare triple {37611#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {37611#false} is VALID [2022-02-21 04:23:19,606 INFO L290 TraceCheckUtils]: 67: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp___2~0#1); {37611#false} is VALID [2022-02-21 04:23:19,606 INFO L290 TraceCheckUtils]: 68: Hoare triple {37611#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {37611#false} is VALID [2022-02-21 04:23:19,606 INFO L290 TraceCheckUtils]: 69: Hoare triple {37611#false} assume 1 == ~t4_pc~0; {37611#false} is VALID [2022-02-21 04:23:19,606 INFO L290 TraceCheckUtils]: 70: Hoare triple {37611#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {37611#false} is VALID [2022-02-21 04:23:19,606 INFO L290 TraceCheckUtils]: 71: Hoare triple {37611#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {37611#false} is VALID [2022-02-21 04:23:19,606 INFO L290 TraceCheckUtils]: 72: Hoare triple {37611#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {37611#false} is VALID [2022-02-21 04:23:19,606 INFO L290 TraceCheckUtils]: 73: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp___3~0#1); {37611#false} is VALID [2022-02-21 04:23:19,606 INFO L290 TraceCheckUtils]: 74: Hoare triple {37611#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {37611#false} is VALID [2022-02-21 04:23:19,607 INFO L290 TraceCheckUtils]: 75: Hoare triple {37611#false} assume !(1 == ~t5_pc~0); {37611#false} is VALID [2022-02-21 04:23:19,607 INFO L290 TraceCheckUtils]: 76: Hoare triple {37611#false} is_transmit5_triggered_~__retres1~5#1 := 0; {37611#false} is VALID [2022-02-21 04:23:19,607 INFO L290 TraceCheckUtils]: 77: Hoare triple {37611#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {37611#false} is VALID [2022-02-21 04:23:19,607 INFO L290 TraceCheckUtils]: 78: Hoare triple {37611#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {37611#false} is VALID [2022-02-21 04:23:19,607 INFO L290 TraceCheckUtils]: 79: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp___4~0#1); {37611#false} is VALID [2022-02-21 04:23:19,607 INFO L290 TraceCheckUtils]: 80: Hoare triple {37611#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {37611#false} is VALID [2022-02-21 04:23:19,607 INFO L290 TraceCheckUtils]: 81: Hoare triple {37611#false} assume 1 == ~t6_pc~0; {37611#false} is VALID [2022-02-21 04:23:19,607 INFO L290 TraceCheckUtils]: 82: Hoare triple {37611#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {37611#false} is VALID [2022-02-21 04:23:19,607 INFO L290 TraceCheckUtils]: 83: Hoare triple {37611#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {37611#false} is VALID [2022-02-21 04:23:19,608 INFO L290 TraceCheckUtils]: 84: Hoare triple {37611#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {37611#false} is VALID [2022-02-21 04:23:19,608 INFO L290 TraceCheckUtils]: 85: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp___5~0#1); {37611#false} is VALID [2022-02-21 04:23:19,608 INFO L290 TraceCheckUtils]: 86: Hoare triple {37611#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {37611#false} is VALID [2022-02-21 04:23:19,608 INFO L290 TraceCheckUtils]: 87: Hoare triple {37611#false} assume 1 == ~t7_pc~0; {37611#false} is VALID [2022-02-21 04:23:19,608 INFO L290 TraceCheckUtils]: 88: Hoare triple {37611#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {37611#false} is VALID [2022-02-21 04:23:19,608 INFO L290 TraceCheckUtils]: 89: Hoare triple {37611#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {37611#false} is VALID [2022-02-21 04:23:19,608 INFO L290 TraceCheckUtils]: 90: Hoare triple {37611#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {37611#false} is VALID [2022-02-21 04:23:19,608 INFO L290 TraceCheckUtils]: 91: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp___6~0#1); {37611#false} is VALID [2022-02-21 04:23:19,609 INFO L290 TraceCheckUtils]: 92: Hoare triple {37611#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {37611#false} is VALID [2022-02-21 04:23:19,609 INFO L290 TraceCheckUtils]: 93: Hoare triple {37611#false} assume !(1 == ~t8_pc~0); {37611#false} is VALID [2022-02-21 04:23:19,609 INFO L290 TraceCheckUtils]: 94: Hoare triple {37611#false} is_transmit8_triggered_~__retres1~8#1 := 0; {37611#false} is VALID [2022-02-21 04:23:19,609 INFO L290 TraceCheckUtils]: 95: Hoare triple {37611#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {37611#false} is VALID [2022-02-21 04:23:19,609 INFO L290 TraceCheckUtils]: 96: Hoare triple {37611#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {37611#false} is VALID [2022-02-21 04:23:19,609 INFO L290 TraceCheckUtils]: 97: Hoare triple {37611#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {37611#false} is VALID [2022-02-21 04:23:19,609 INFO L290 TraceCheckUtils]: 98: Hoare triple {37611#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {37611#false} is VALID [2022-02-21 04:23:19,609 INFO L290 TraceCheckUtils]: 99: Hoare triple {37611#false} assume 1 == ~t9_pc~0; {37611#false} is VALID [2022-02-21 04:23:19,609 INFO L290 TraceCheckUtils]: 100: Hoare triple {37611#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {37611#false} is VALID [2022-02-21 04:23:19,610 INFO L290 TraceCheckUtils]: 101: Hoare triple {37611#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {37611#false} is VALID [2022-02-21 04:23:19,610 INFO L290 TraceCheckUtils]: 102: Hoare triple {37611#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {37611#false} is VALID [2022-02-21 04:23:19,610 INFO L290 TraceCheckUtils]: 103: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp___8~0#1); {37611#false} is VALID [2022-02-21 04:23:19,610 INFO L290 TraceCheckUtils]: 104: Hoare triple {37611#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {37611#false} is VALID [2022-02-21 04:23:19,610 INFO L290 TraceCheckUtils]: 105: Hoare triple {37611#false} assume !(1 == ~t10_pc~0); {37611#false} is VALID [2022-02-21 04:23:19,610 INFO L290 TraceCheckUtils]: 106: Hoare triple {37611#false} is_transmit10_triggered_~__retres1~10#1 := 0; {37611#false} is VALID [2022-02-21 04:23:19,610 INFO L290 TraceCheckUtils]: 107: Hoare triple {37611#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {37611#false} is VALID [2022-02-21 04:23:19,610 INFO L290 TraceCheckUtils]: 108: Hoare triple {37611#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {37611#false} is VALID [2022-02-21 04:23:19,610 INFO L290 TraceCheckUtils]: 109: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp___9~0#1); {37611#false} is VALID [2022-02-21 04:23:19,611 INFO L290 TraceCheckUtils]: 110: Hoare triple {37611#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {37611#false} is VALID [2022-02-21 04:23:19,611 INFO L290 TraceCheckUtils]: 111: Hoare triple {37611#false} assume 1 == ~t11_pc~0; {37611#false} is VALID [2022-02-21 04:23:19,611 INFO L290 TraceCheckUtils]: 112: Hoare triple {37611#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {37611#false} is VALID [2022-02-21 04:23:19,611 INFO L290 TraceCheckUtils]: 113: Hoare triple {37611#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {37611#false} is VALID [2022-02-21 04:23:19,611 INFO L290 TraceCheckUtils]: 114: Hoare triple {37611#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {37611#false} is VALID [2022-02-21 04:23:19,611 INFO L290 TraceCheckUtils]: 115: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp___10~0#1); {37611#false} is VALID [2022-02-21 04:23:19,611 INFO L290 TraceCheckUtils]: 116: Hoare triple {37611#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {37611#false} is VALID [2022-02-21 04:23:19,611 INFO L290 TraceCheckUtils]: 117: Hoare triple {37611#false} assume !(1 == ~t12_pc~0); {37611#false} is VALID [2022-02-21 04:23:19,611 INFO L290 TraceCheckUtils]: 118: Hoare triple {37611#false} is_transmit12_triggered_~__retres1~12#1 := 0; {37611#false} is VALID [2022-02-21 04:23:19,612 INFO L290 TraceCheckUtils]: 119: Hoare triple {37611#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {37611#false} is VALID [2022-02-21 04:23:19,612 INFO L290 TraceCheckUtils]: 120: Hoare triple {37611#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {37611#false} is VALID [2022-02-21 04:23:19,612 INFO L290 TraceCheckUtils]: 121: Hoare triple {37611#false} assume !(0 != activate_threads_~tmp___11~0#1); {37611#false} is VALID [2022-02-21 04:23:19,612 INFO L290 TraceCheckUtils]: 122: Hoare triple {37611#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37611#false} is VALID [2022-02-21 04:23:19,612 INFO L290 TraceCheckUtils]: 123: Hoare triple {37611#false} assume !(1 == ~M_E~0); {37611#false} is VALID [2022-02-21 04:23:19,612 INFO L290 TraceCheckUtils]: 124: Hoare triple {37611#false} assume !(1 == ~T1_E~0); {37611#false} is VALID [2022-02-21 04:23:19,612 INFO L290 TraceCheckUtils]: 125: Hoare triple {37611#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {37611#false} is VALID [2022-02-21 04:23:19,612 INFO L290 TraceCheckUtils]: 126: Hoare triple {37611#false} assume !(1 == ~T3_E~0); {37611#false} is VALID [2022-02-21 04:23:19,612 INFO L290 TraceCheckUtils]: 127: Hoare triple {37611#false} assume !(1 == ~T4_E~0); {37611#false} is VALID [2022-02-21 04:23:19,613 INFO L290 TraceCheckUtils]: 128: Hoare triple {37611#false} assume !(1 == ~T5_E~0); {37611#false} is VALID [2022-02-21 04:23:19,613 INFO L290 TraceCheckUtils]: 129: Hoare triple {37611#false} assume !(1 == ~T6_E~0); {37611#false} is VALID [2022-02-21 04:23:19,613 INFO L290 TraceCheckUtils]: 130: Hoare triple {37611#false} assume !(1 == ~T7_E~0); {37611#false} is VALID [2022-02-21 04:23:19,613 INFO L290 TraceCheckUtils]: 131: Hoare triple {37611#false} assume !(1 == ~T8_E~0); {37611#false} is VALID [2022-02-21 04:23:19,613 INFO L290 TraceCheckUtils]: 132: Hoare triple {37611#false} assume !(1 == ~T9_E~0); {37611#false} is VALID [2022-02-21 04:23:19,613 INFO L290 TraceCheckUtils]: 133: Hoare triple {37611#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {37611#false} is VALID [2022-02-21 04:23:19,613 INFO L290 TraceCheckUtils]: 134: Hoare triple {37611#false} assume !(1 == ~T11_E~0); {37611#false} is VALID [2022-02-21 04:23:19,613 INFO L290 TraceCheckUtils]: 135: Hoare triple {37611#false} assume !(1 == ~T12_E~0); {37611#false} is VALID [2022-02-21 04:23:19,613 INFO L290 TraceCheckUtils]: 136: Hoare triple {37611#false} assume !(1 == ~E_M~0); {37611#false} is VALID [2022-02-21 04:23:19,614 INFO L290 TraceCheckUtils]: 137: Hoare triple {37611#false} assume !(1 == ~E_1~0); {37611#false} is VALID [2022-02-21 04:23:19,614 INFO L290 TraceCheckUtils]: 138: Hoare triple {37611#false} assume !(1 == ~E_2~0); {37611#false} is VALID [2022-02-21 04:23:19,614 INFO L290 TraceCheckUtils]: 139: Hoare triple {37611#false} assume !(1 == ~E_3~0); {37611#false} is VALID [2022-02-21 04:23:19,614 INFO L290 TraceCheckUtils]: 140: Hoare triple {37611#false} assume !(1 == ~E_4~0); {37611#false} is VALID [2022-02-21 04:23:19,614 INFO L290 TraceCheckUtils]: 141: Hoare triple {37611#false} assume 1 == ~E_5~0;~E_5~0 := 2; {37611#false} is VALID [2022-02-21 04:23:19,614 INFO L290 TraceCheckUtils]: 142: Hoare triple {37611#false} assume !(1 == ~E_6~0); {37611#false} is VALID [2022-02-21 04:23:19,614 INFO L290 TraceCheckUtils]: 143: Hoare triple {37611#false} assume !(1 == ~E_7~0); {37611#false} is VALID [2022-02-21 04:23:19,614 INFO L290 TraceCheckUtils]: 144: Hoare triple {37611#false} assume !(1 == ~E_8~0); {37611#false} is VALID [2022-02-21 04:23:19,614 INFO L290 TraceCheckUtils]: 145: Hoare triple {37611#false} assume !(1 == ~E_9~0); {37611#false} is VALID [2022-02-21 04:23:19,615 INFO L290 TraceCheckUtils]: 146: Hoare triple {37611#false} assume !(1 == ~E_10~0); {37611#false} is VALID [2022-02-21 04:23:19,615 INFO L290 TraceCheckUtils]: 147: Hoare triple {37611#false} assume !(1 == ~E_11~0); {37611#false} is VALID [2022-02-21 04:23:19,615 INFO L290 TraceCheckUtils]: 148: Hoare triple {37611#false} assume !(1 == ~E_12~0); {37611#false} is VALID [2022-02-21 04:23:19,615 INFO L290 TraceCheckUtils]: 149: Hoare triple {37611#false} assume { :end_inline_reset_delta_events } true; {37611#false} is VALID [2022-02-21 04:23:19,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:19,615 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:19,616 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1258408787] [2022-02-21 04:23:19,616 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1258408787] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:19,616 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:19,616 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:19,616 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753143834] [2022-02-21 04:23:19,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:19,616 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:19,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:19,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1696309331, now seen corresponding path program 1 times [2022-02-21 04:23:19,617 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:19,617 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228074763] [2022-02-21 04:23:19,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:19,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:19,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:19,645 INFO L290 TraceCheckUtils]: 0: Hoare triple {37613#true} assume !false; {37613#true} is VALID [2022-02-21 04:23:19,646 INFO L290 TraceCheckUtils]: 1: Hoare triple {37613#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {37613#true} is VALID [2022-02-21 04:23:19,646 INFO L290 TraceCheckUtils]: 2: Hoare triple {37613#true} assume !false; {37613#true} is VALID [2022-02-21 04:23:19,646 INFO L290 TraceCheckUtils]: 3: Hoare triple {37613#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {37613#true} is VALID [2022-02-21 04:23:19,646 INFO L290 TraceCheckUtils]: 4: Hoare triple {37613#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {37613#true} is VALID [2022-02-21 04:23:19,646 INFO L290 TraceCheckUtils]: 5: Hoare triple {37613#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {37613#true} is VALID [2022-02-21 04:23:19,646 INFO L290 TraceCheckUtils]: 6: Hoare triple {37613#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {37613#true} is VALID [2022-02-21 04:23:19,646 INFO L290 TraceCheckUtils]: 7: Hoare triple {37613#true} assume !(0 != eval_~tmp~0#1); {37613#true} is VALID [2022-02-21 04:23:19,646 INFO L290 TraceCheckUtils]: 8: Hoare triple {37613#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {37613#true} is VALID [2022-02-21 04:23:19,647 INFO L290 TraceCheckUtils]: 9: Hoare triple {37613#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {37613#true} is VALID [2022-02-21 04:23:19,647 INFO L290 TraceCheckUtils]: 10: Hoare triple {37613#true} assume 0 == ~M_E~0;~M_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,647 INFO L290 TraceCheckUtils]: 11: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,647 INFO L290 TraceCheckUtils]: 12: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,648 INFO L290 TraceCheckUtils]: 13: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,648 INFO L290 TraceCheckUtils]: 14: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,648 INFO L290 TraceCheckUtils]: 15: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,648 INFO L290 TraceCheckUtils]: 16: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,649 INFO L290 TraceCheckUtils]: 17: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,649 INFO L290 TraceCheckUtils]: 18: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,649 INFO L290 TraceCheckUtils]: 19: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,649 INFO L290 TraceCheckUtils]: 20: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,650 INFO L290 TraceCheckUtils]: 21: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,650 INFO L290 TraceCheckUtils]: 22: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,650 INFO L290 TraceCheckUtils]: 23: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,650 INFO L290 TraceCheckUtils]: 24: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,651 INFO L290 TraceCheckUtils]: 25: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,651 INFO L290 TraceCheckUtils]: 26: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,651 INFO L290 TraceCheckUtils]: 27: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,651 INFO L290 TraceCheckUtils]: 28: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,652 INFO L290 TraceCheckUtils]: 29: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,652 INFO L290 TraceCheckUtils]: 30: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,652 INFO L290 TraceCheckUtils]: 31: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,652 INFO L290 TraceCheckUtils]: 32: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,653 INFO L290 TraceCheckUtils]: 33: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,653 INFO L290 TraceCheckUtils]: 34: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,653 INFO L290 TraceCheckUtils]: 35: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,653 INFO L290 TraceCheckUtils]: 36: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,654 INFO L290 TraceCheckUtils]: 37: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,654 INFO L290 TraceCheckUtils]: 38: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,654 INFO L290 TraceCheckUtils]: 39: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,654 INFO L290 TraceCheckUtils]: 40: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,655 INFO L290 TraceCheckUtils]: 41: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,655 INFO L290 TraceCheckUtils]: 42: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,655 INFO L290 TraceCheckUtils]: 43: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,655 INFO L290 TraceCheckUtils]: 44: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,656 INFO L290 TraceCheckUtils]: 45: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,656 INFO L290 TraceCheckUtils]: 46: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,656 INFO L290 TraceCheckUtils]: 47: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,656 INFO L290 TraceCheckUtils]: 48: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,657 INFO L290 TraceCheckUtils]: 49: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,657 INFO L290 TraceCheckUtils]: 50: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,657 INFO L290 TraceCheckUtils]: 51: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,657 INFO L290 TraceCheckUtils]: 52: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,657 INFO L290 TraceCheckUtils]: 53: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,658 INFO L290 TraceCheckUtils]: 54: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,658 INFO L290 TraceCheckUtils]: 55: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,658 INFO L290 TraceCheckUtils]: 56: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,658 INFO L290 TraceCheckUtils]: 57: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,659 INFO L290 TraceCheckUtils]: 58: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,659 INFO L290 TraceCheckUtils]: 59: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,659 INFO L290 TraceCheckUtils]: 60: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,659 INFO L290 TraceCheckUtils]: 61: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,660 INFO L290 TraceCheckUtils]: 62: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,660 INFO L290 TraceCheckUtils]: 63: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,660 INFO L290 TraceCheckUtils]: 64: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,660 INFO L290 TraceCheckUtils]: 65: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,661 INFO L290 TraceCheckUtils]: 66: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,661 INFO L290 TraceCheckUtils]: 67: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,661 INFO L290 TraceCheckUtils]: 68: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,661 INFO L290 TraceCheckUtils]: 69: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,662 INFO L290 TraceCheckUtils]: 70: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,662 INFO L290 TraceCheckUtils]: 71: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,662 INFO L290 TraceCheckUtils]: 72: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,662 INFO L290 TraceCheckUtils]: 73: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,663 INFO L290 TraceCheckUtils]: 74: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,663 INFO L290 TraceCheckUtils]: 75: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,663 INFO L290 TraceCheckUtils]: 76: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,663 INFO L290 TraceCheckUtils]: 77: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,664 INFO L290 TraceCheckUtils]: 78: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,664 INFO L290 TraceCheckUtils]: 79: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,664 INFO L290 TraceCheckUtils]: 80: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,664 INFO L290 TraceCheckUtils]: 81: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,665 INFO L290 TraceCheckUtils]: 82: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,665 INFO L290 TraceCheckUtils]: 83: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,665 INFO L290 TraceCheckUtils]: 84: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,665 INFO L290 TraceCheckUtils]: 85: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,666 INFO L290 TraceCheckUtils]: 86: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,666 INFO L290 TraceCheckUtils]: 87: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,666 INFO L290 TraceCheckUtils]: 88: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,666 INFO L290 TraceCheckUtils]: 89: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,667 INFO L290 TraceCheckUtils]: 90: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,667 INFO L290 TraceCheckUtils]: 91: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,667 INFO L290 TraceCheckUtils]: 92: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,667 INFO L290 TraceCheckUtils]: 93: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,668 INFO L290 TraceCheckUtils]: 94: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,668 INFO L290 TraceCheckUtils]: 95: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,668 INFO L290 TraceCheckUtils]: 96: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,668 INFO L290 TraceCheckUtils]: 97: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,669 INFO L290 TraceCheckUtils]: 98: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,669 INFO L290 TraceCheckUtils]: 99: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,669 INFO L290 TraceCheckUtils]: 100: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,669 INFO L290 TraceCheckUtils]: 101: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,670 INFO L290 TraceCheckUtils]: 102: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,670 INFO L290 TraceCheckUtils]: 103: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,670 INFO L290 TraceCheckUtils]: 104: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,670 INFO L290 TraceCheckUtils]: 105: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,671 INFO L290 TraceCheckUtils]: 106: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,671 INFO L290 TraceCheckUtils]: 107: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,671 INFO L290 TraceCheckUtils]: 108: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,671 INFO L290 TraceCheckUtils]: 109: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,672 INFO L290 TraceCheckUtils]: 110: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,672 INFO L290 TraceCheckUtils]: 111: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,672 INFO L290 TraceCheckUtils]: 112: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,672 INFO L290 TraceCheckUtils]: 113: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,673 INFO L290 TraceCheckUtils]: 114: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37615#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:19,673 INFO L290 TraceCheckUtils]: 115: Hoare triple {37615#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {37614#false} is VALID [2022-02-21 04:23:19,673 INFO L290 TraceCheckUtils]: 116: Hoare triple {37614#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,673 INFO L290 TraceCheckUtils]: 117: Hoare triple {37614#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,673 INFO L290 TraceCheckUtils]: 118: Hoare triple {37614#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,673 INFO L290 TraceCheckUtils]: 119: Hoare triple {37614#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,673 INFO L290 TraceCheckUtils]: 120: Hoare triple {37614#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,674 INFO L290 TraceCheckUtils]: 121: Hoare triple {37614#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,674 INFO L290 TraceCheckUtils]: 122: Hoare triple {37614#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,674 INFO L290 TraceCheckUtils]: 123: Hoare triple {37614#false} assume !(1 == ~T8_E~0); {37614#false} is VALID [2022-02-21 04:23:19,674 INFO L290 TraceCheckUtils]: 124: Hoare triple {37614#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,674 INFO L290 TraceCheckUtils]: 125: Hoare triple {37614#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,674 INFO L290 TraceCheckUtils]: 126: Hoare triple {37614#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,674 INFO L290 TraceCheckUtils]: 127: Hoare triple {37614#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,674 INFO L290 TraceCheckUtils]: 128: Hoare triple {37614#false} assume 1 == ~E_M~0;~E_M~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,674 INFO L290 TraceCheckUtils]: 129: Hoare triple {37614#false} assume 1 == ~E_1~0;~E_1~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,675 INFO L290 TraceCheckUtils]: 130: Hoare triple {37614#false} assume 1 == ~E_2~0;~E_2~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,675 INFO L290 TraceCheckUtils]: 131: Hoare triple {37614#false} assume !(1 == ~E_3~0); {37614#false} is VALID [2022-02-21 04:23:19,675 INFO L290 TraceCheckUtils]: 132: Hoare triple {37614#false} assume 1 == ~E_4~0;~E_4~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,675 INFO L290 TraceCheckUtils]: 133: Hoare triple {37614#false} assume 1 == ~E_5~0;~E_5~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,675 INFO L290 TraceCheckUtils]: 134: Hoare triple {37614#false} assume 1 == ~E_6~0;~E_6~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,675 INFO L290 TraceCheckUtils]: 135: Hoare triple {37614#false} assume 1 == ~E_7~0;~E_7~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,675 INFO L290 TraceCheckUtils]: 136: Hoare triple {37614#false} assume 1 == ~E_8~0;~E_8~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,675 INFO L290 TraceCheckUtils]: 137: Hoare triple {37614#false} assume 1 == ~E_9~0;~E_9~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,675 INFO L290 TraceCheckUtils]: 138: Hoare triple {37614#false} assume 1 == ~E_10~0;~E_10~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,676 INFO L290 TraceCheckUtils]: 139: Hoare triple {37614#false} assume !(1 == ~E_11~0); {37614#false} is VALID [2022-02-21 04:23:19,676 INFO L290 TraceCheckUtils]: 140: Hoare triple {37614#false} assume 1 == ~E_12~0;~E_12~0 := 2; {37614#false} is VALID [2022-02-21 04:23:19,676 INFO L290 TraceCheckUtils]: 141: Hoare triple {37614#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {37614#false} is VALID [2022-02-21 04:23:19,676 INFO L290 TraceCheckUtils]: 142: Hoare triple {37614#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {37614#false} is VALID [2022-02-21 04:23:19,676 INFO L290 TraceCheckUtils]: 143: Hoare triple {37614#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {37614#false} is VALID [2022-02-21 04:23:19,676 INFO L290 TraceCheckUtils]: 144: Hoare triple {37614#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {37614#false} is VALID [2022-02-21 04:23:19,676 INFO L290 TraceCheckUtils]: 145: Hoare triple {37614#false} assume !(0 == start_simulation_~tmp~3#1); {37614#false} is VALID [2022-02-21 04:23:19,676 INFO L290 TraceCheckUtils]: 146: Hoare triple {37614#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {37614#false} is VALID [2022-02-21 04:23:19,676 INFO L290 TraceCheckUtils]: 147: Hoare triple {37614#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {37614#false} is VALID [2022-02-21 04:23:19,677 INFO L290 TraceCheckUtils]: 148: Hoare triple {37614#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {37614#false} is VALID [2022-02-21 04:23:19,677 INFO L290 TraceCheckUtils]: 149: Hoare triple {37614#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {37614#false} is VALID [2022-02-21 04:23:19,677 INFO L290 TraceCheckUtils]: 150: Hoare triple {37614#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {37614#false} is VALID [2022-02-21 04:23:19,677 INFO L290 TraceCheckUtils]: 151: Hoare triple {37614#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {37614#false} is VALID [2022-02-21 04:23:19,677 INFO L290 TraceCheckUtils]: 152: Hoare triple {37614#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {37614#false} is VALID [2022-02-21 04:23:19,677 INFO L290 TraceCheckUtils]: 153: Hoare triple {37614#false} assume !(0 != start_simulation_~tmp___0~1#1); {37614#false} is VALID [2022-02-21 04:23:19,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:19,678 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:19,678 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228074763] [2022-02-21 04:23:19,678 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228074763] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:19,678 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:19,678 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:19,678 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1182550826] [2022-02-21 04:23:19,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:19,679 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:19,679 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:19,680 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:19,680 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:19,680 INFO L87 Difference]: Start difference. First operand 1788 states and 2647 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:20,839 INFO L93 Difference]: Finished difference Result 1788 states and 2646 transitions. [2022-02-21 04:23:20,839 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:20,839 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,936 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:20,937 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2646 transitions. [2022-02-21 04:23:21,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:21,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2646 transitions. [2022-02-21 04:23:21,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:21,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:21,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2646 transitions. [2022-02-21 04:23:21,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:21,089 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2022-02-21 04:23:21,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2646 transitions. [2022-02-21 04:23:21,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:21,108 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:21,111 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2646 transitions. Second operand has 1788 states, 1788 states have (on average 1.4798657718120805) internal successors, (2646), 1787 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,113 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2646 transitions. Second operand has 1788 states, 1788 states have (on average 1.4798657718120805) internal successors, (2646), 1787 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,115 INFO L87 Difference]: Start difference. First operand 1788 states and 2646 transitions. Second operand has 1788 states, 1788 states have (on average 1.4798657718120805) internal successors, (2646), 1787 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:21,181 INFO L93 Difference]: Finished difference Result 1788 states and 2646 transitions. [2022-02-21 04:23:21,181 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2646 transitions. [2022-02-21 04:23:21,183 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:21,183 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:21,185 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4798657718120805) internal successors, (2646), 1787 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2646 transitions. [2022-02-21 04:23:21,187 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4798657718120805) internal successors, (2646), 1787 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2646 transitions. [2022-02-21 04:23:21,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:21,252 INFO L93 Difference]: Finished difference Result 1788 states and 2646 transitions. [2022-02-21 04:23:21,253 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2646 transitions. [2022-02-21 04:23:21,254 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:21,254 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:21,254 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:21,254 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:21,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4798657718120805) internal successors, (2646), 1787 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2646 transitions. [2022-02-21 04:23:21,323 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2022-02-21 04:23:21,323 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2022-02-21 04:23:21,323 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:23:21,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2646 transitions. [2022-02-21 04:23:21,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:21,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:21,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:21,330 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:21,330 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:21,330 INFO L791 eck$LassoCheckResult]: Stem: 40193#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40194#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 39714#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39715#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39769#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 41108#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40202#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40005#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39404#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39405#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40627#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 40738#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 41174#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 41175#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40133#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 40134#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 40656#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40575#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40168#L1201 assume !(0 == ~M_E~0); 40169#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41015#L1206-1 assume !(0 == ~T2_E~0); 41001#L1211-1 assume !(0 == ~T3_E~0); 41002#L1216-1 assume !(0 == ~T4_E~0); 39989#L1221-1 assume !(0 == ~T5_E~0); 39990#L1226-1 assume !(0 == ~T6_E~0); 39629#L1231-1 assume !(0 == ~T7_E~0); 39630#L1236-1 assume !(0 == ~T8_E~0); 41038#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40026#L1246-1 assume !(0 == ~T10_E~0); 40027#L1251-1 assume !(0 == ~T11_E~0); 40166#L1256-1 assume !(0 == ~T12_E~0); 39415#L1261-1 assume !(0 == ~E_M~0); 39416#L1266-1 assume !(0 == ~E_1~0); 41160#L1271-1 assume !(0 == ~E_2~0); 40722#L1276-1 assume !(0 == ~E_3~0); 40723#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 40670#L1286-1 assume !(0 == ~E_5~0); 39880#L1291-1 assume !(0 == ~E_6~0); 39881#L1296-1 assume !(0 == ~E_7~0); 40456#L1301-1 assume !(0 == ~E_8~0); 40457#L1306-1 assume !(0 == ~E_9~0); 40937#L1311-1 assume !(0 == ~E_10~0); 39831#L1316-1 assume !(0 == ~E_11~0); 39832#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 40474#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40475#L593 assume 1 == ~m_pc~0; 40619#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39721#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41147#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40681#L1492 assume !(0 != activate_threads_~tmp~1#1); 40682#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40973#L612 assume !(1 == ~t1_pc~0); 40974#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41103#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40103#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39725#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39726#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40145#L631 assume 1 == ~t2_pc~0; 40080#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39502#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39503#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40339#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 40340#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39798#L650 assume !(1 == ~t3_pc~0); 39799#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40499#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39722#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39455#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 39456#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40648#L669 assume 1 == ~t4_pc~0; 40649#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41007#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40132#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39664#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 39665#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39889#L688 assume !(1 == ~t5_pc~0); 39680#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39681#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40599#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40533#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 40534#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40663#L707 assume 1 == ~t6_pc~0; 41072#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40309#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40310#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41070#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 40605#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40167#L726 assume 1 == ~t7_pc~0; 40066#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39765#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40806#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41080#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 39534#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39535#L745 assume !(1 == ~t8_pc~0); 39982#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40001#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40839#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40387#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40388#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40898#L764 assume 1 == ~t9_pc~0; 40165#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40007#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40684#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41131#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 39554#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39555#L783 assume !(1 == ~t10_pc~0); 39616#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39617#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39658#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39659#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 40121#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41009#L802 assume 1 == ~t11_pc~0; 40991#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39499#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39500#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39991#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 39992#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40102#L821 assume !(1 == ~t12_pc~0); 40353#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40449#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39504#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39505#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 41047#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40693#L1339 assume !(1 == ~M_E~0); 40694#L1339-2 assume !(1 == ~T1_E~0); 41082#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41083#L1349-1 assume !(1 == ~T3_E~0); 40467#L1354-1 assume !(1 == ~T4_E~0); 40468#L1359-1 assume !(1 == ~T5_E~0); 40869#L1364-1 assume !(1 == ~T6_E~0); 39932#L1369-1 assume !(1 == ~T7_E~0); 39933#L1374-1 assume !(1 == ~T8_E~0); 40470#L1379-1 assume !(1 == ~T9_E~0); 40471#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40570#L1389-1 assume !(1 == ~T11_E~0); 41041#L1394-1 assume !(1 == ~T12_E~0); 41042#L1399-1 assume !(1 == ~E_M~0); 41132#L1404-1 assume !(1 == ~E_1~0); 40031#L1409-1 assume !(1 == ~E_2~0); 40032#L1414-1 assume !(1 == ~E_3~0); 40758#L1419-1 assume !(1 == ~E_4~0); 39672#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 39673#L1429-1 assume !(1 == ~E_6~0); 40483#L1434-1 assume !(1 == ~E_7~0); 41062#L1439-1 assume !(1 == ~E_8~0); 39710#L1444-1 assume !(1 == ~E_9~0); 39711#L1449-1 assume !(1 == ~E_10~0); 40085#L1454-1 assume !(1 == ~E_11~0); 40086#L1459-1 assume !(1 == ~E_12~0); 40604#L1464-1 assume { :end_inline_reset_delta_events } true; 39844#L1810-2 [2022-02-21 04:23:21,331 INFO L793 eck$LassoCheckResult]: Loop: 39844#L1810-2 assume !false; 40288#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40204#L1176 assume !false; 40766#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40336#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39542#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40092#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40093#L1003 assume !(0 != eval_~tmp~0#1); 39734#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39735#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40925#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40708#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40709#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40602#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39793#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39794#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40260#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39864#L1231-3 assume !(0 == ~T7_E~0); 39865#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40111#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41093#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40994#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40699#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39810#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39811#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39856#L1271-3 assume !(0 == ~E_2~0); 39857#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40233#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40234#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40755#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40756#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41171#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41128#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40345#L1311-3 assume !(0 == ~E_10~0); 39736#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39737#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 39812#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40448#L593-42 assume 1 == ~m_pc~0; 40841#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40607#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41156#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41157#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39635#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39636#L612-42 assume !(1 == ~t1_pc~0); 40557#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 40950#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41071#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39723#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39724#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40419#L631-42 assume 1 == ~t2_pc~0; 39488#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39489#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40408#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40284#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40285#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39885#L650-42 assume 1 == ~t3_pc~0; 39447#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39448#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41099#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40078#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40079#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41063#L669-42 assume !(1 == ~t4_pc~0); 39445#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39446#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40874#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40764#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 40661#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40662#L688-42 assume 1 == ~t5_pc~0; 40753#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40954#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39586#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39587#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39663#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39477#L707-42 assume !(1 == ~t6_pc~0); 39478#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 41135#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40879#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40880#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40629#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40630#L726-42 assume 1 == ~t7_pc~0; 40907#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40933#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40934#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40348#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40349#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40452#L745-42 assume 1 == ~t8_pc~0; 40489#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40491#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39818#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39463#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39464#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40189#L764-42 assume 1 == ~t9_pc~0; 40325#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40678#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40679#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39749#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39750#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39803#L783-42 assume 1 == ~t10_pc~0; 39419#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39420#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40015#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40148#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41165#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40849#L802-42 assume 1 == ~t11_pc~0; 39950#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39561#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39562#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39512#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39513#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40689#L821-42 assume 1 == ~t12_pc~0; 40690#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40055#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39417#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39418#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40395#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40385#L1339-3 assume !(1 == ~M_E~0); 40386#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40537#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40647#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40064#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40065#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40658#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41154#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41061#L1374-3 assume !(1 == ~T8_E~0); 39886#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39887#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40062#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40063#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40272#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41068#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41036#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41037#L1414-3 assume !(1 == ~E_3~0); 41092#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40851#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39770#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39771#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40657#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39698#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39699#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39815#L1454-3 assume !(1 == ~E_11~0); 40652#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40653#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40311#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39608#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39868#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39869#L1829 assume !(0 == start_simulation_~tmp~3#1); 39590#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39591#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40391#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40392#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 40671#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40672#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40292#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 39843#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 39844#L1810-2 [2022-02-21 04:23:21,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:21,331 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2022-02-21 04:23:21,331 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:21,331 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901640217] [2022-02-21 04:23:21,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:21,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:21,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:21,360 INFO L290 TraceCheckUtils]: 0: Hoare triple {44771#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {44771#true} is VALID [2022-02-21 04:23:21,360 INFO L290 TraceCheckUtils]: 1: Hoare triple {44771#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {44773#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:21,361 INFO L290 TraceCheckUtils]: 2: Hoare triple {44773#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {44773#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:21,361 INFO L290 TraceCheckUtils]: 3: Hoare triple {44773#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {44773#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:21,361 INFO L290 TraceCheckUtils]: 4: Hoare triple {44773#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {44773#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:21,362 INFO L290 TraceCheckUtils]: 5: Hoare triple {44773#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {44773#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:21,362 INFO L290 TraceCheckUtils]: 6: Hoare triple {44773#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {44773#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:21,362 INFO L290 TraceCheckUtils]: 7: Hoare triple {44773#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {44773#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:21,362 INFO L290 TraceCheckUtils]: 8: Hoare triple {44773#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {44773#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:21,363 INFO L290 TraceCheckUtils]: 9: Hoare triple {44773#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {44773#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:21,363 INFO L290 TraceCheckUtils]: 10: Hoare triple {44773#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {44772#false} is VALID [2022-02-21 04:23:21,363 INFO L290 TraceCheckUtils]: 11: Hoare triple {44772#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {44772#false} is VALID [2022-02-21 04:23:21,363 INFO L290 TraceCheckUtils]: 12: Hoare triple {44772#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {44772#false} is VALID [2022-02-21 04:23:21,363 INFO L290 TraceCheckUtils]: 13: Hoare triple {44772#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {44772#false} is VALID [2022-02-21 04:23:21,363 INFO L290 TraceCheckUtils]: 14: Hoare triple {44772#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {44772#false} is VALID [2022-02-21 04:23:21,363 INFO L290 TraceCheckUtils]: 15: Hoare triple {44772#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {44772#false} is VALID [2022-02-21 04:23:21,363 INFO L290 TraceCheckUtils]: 16: Hoare triple {44772#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {44772#false} is VALID [2022-02-21 04:23:21,363 INFO L290 TraceCheckUtils]: 17: Hoare triple {44772#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {44772#false} is VALID [2022-02-21 04:23:21,363 INFO L290 TraceCheckUtils]: 18: Hoare triple {44772#false} assume !(0 == ~M_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 19: Hoare triple {44772#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 20: Hoare triple {44772#false} assume !(0 == ~T2_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 21: Hoare triple {44772#false} assume !(0 == ~T3_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 22: Hoare triple {44772#false} assume !(0 == ~T4_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 23: Hoare triple {44772#false} assume !(0 == ~T5_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 24: Hoare triple {44772#false} assume !(0 == ~T6_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 25: Hoare triple {44772#false} assume !(0 == ~T7_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 26: Hoare triple {44772#false} assume !(0 == ~T8_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 27: Hoare triple {44772#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 28: Hoare triple {44772#false} assume !(0 == ~T10_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 29: Hoare triple {44772#false} assume !(0 == ~T11_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 30: Hoare triple {44772#false} assume !(0 == ~T12_E~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 31: Hoare triple {44772#false} assume !(0 == ~E_M~0); {44772#false} is VALID [2022-02-21 04:23:21,364 INFO L290 TraceCheckUtils]: 32: Hoare triple {44772#false} assume !(0 == ~E_1~0); {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 33: Hoare triple {44772#false} assume !(0 == ~E_2~0); {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 34: Hoare triple {44772#false} assume !(0 == ~E_3~0); {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 35: Hoare triple {44772#false} assume 0 == ~E_4~0;~E_4~0 := 1; {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 36: Hoare triple {44772#false} assume !(0 == ~E_5~0); {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 37: Hoare triple {44772#false} assume !(0 == ~E_6~0); {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 38: Hoare triple {44772#false} assume !(0 == ~E_7~0); {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 39: Hoare triple {44772#false} assume !(0 == ~E_8~0); {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 40: Hoare triple {44772#false} assume !(0 == ~E_9~0); {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 41: Hoare triple {44772#false} assume !(0 == ~E_10~0); {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 42: Hoare triple {44772#false} assume !(0 == ~E_11~0); {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 43: Hoare triple {44772#false} assume 0 == ~E_12~0;~E_12~0 := 1; {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 44: Hoare triple {44772#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 45: Hoare triple {44772#false} assume 1 == ~m_pc~0; {44772#false} is VALID [2022-02-21 04:23:21,365 INFO L290 TraceCheckUtils]: 46: Hoare triple {44772#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 47: Hoare triple {44772#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 48: Hoare triple {44772#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 49: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp~1#1); {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 50: Hoare triple {44772#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 51: Hoare triple {44772#false} assume !(1 == ~t1_pc~0); {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 52: Hoare triple {44772#false} is_transmit1_triggered_~__retres1~1#1 := 0; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 53: Hoare triple {44772#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 54: Hoare triple {44772#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 55: Hoare triple {44772#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 56: Hoare triple {44772#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 57: Hoare triple {44772#false} assume 1 == ~t2_pc~0; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 58: Hoare triple {44772#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 59: Hoare triple {44772#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {44772#false} is VALID [2022-02-21 04:23:21,366 INFO L290 TraceCheckUtils]: 60: Hoare triple {44772#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 61: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp___1~0#1); {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 62: Hoare triple {44772#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 63: Hoare triple {44772#false} assume !(1 == ~t3_pc~0); {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 64: Hoare triple {44772#false} is_transmit3_triggered_~__retres1~3#1 := 0; {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 65: Hoare triple {44772#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 66: Hoare triple {44772#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 67: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp___2~0#1); {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 68: Hoare triple {44772#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 69: Hoare triple {44772#false} assume 1 == ~t4_pc~0; {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 70: Hoare triple {44772#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 71: Hoare triple {44772#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 72: Hoare triple {44772#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 73: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp___3~0#1); {44772#false} is VALID [2022-02-21 04:23:21,367 INFO L290 TraceCheckUtils]: 74: Hoare triple {44772#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 75: Hoare triple {44772#false} assume !(1 == ~t5_pc~0); {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 76: Hoare triple {44772#false} is_transmit5_triggered_~__retres1~5#1 := 0; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 77: Hoare triple {44772#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 78: Hoare triple {44772#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 79: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp___4~0#1); {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 80: Hoare triple {44772#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 81: Hoare triple {44772#false} assume 1 == ~t6_pc~0; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 82: Hoare triple {44772#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 83: Hoare triple {44772#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 84: Hoare triple {44772#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 85: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp___5~0#1); {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 86: Hoare triple {44772#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 87: Hoare triple {44772#false} assume 1 == ~t7_pc~0; {44772#false} is VALID [2022-02-21 04:23:21,368 INFO L290 TraceCheckUtils]: 88: Hoare triple {44772#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 89: Hoare triple {44772#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 90: Hoare triple {44772#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 91: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp___6~0#1); {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 92: Hoare triple {44772#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 93: Hoare triple {44772#false} assume !(1 == ~t8_pc~0); {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 94: Hoare triple {44772#false} is_transmit8_triggered_~__retres1~8#1 := 0; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 95: Hoare triple {44772#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 96: Hoare triple {44772#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 97: Hoare triple {44772#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 98: Hoare triple {44772#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 99: Hoare triple {44772#false} assume 1 == ~t9_pc~0; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 100: Hoare triple {44772#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 101: Hoare triple {44772#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {44772#false} is VALID [2022-02-21 04:23:21,369 INFO L290 TraceCheckUtils]: 102: Hoare triple {44772#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 103: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp___8~0#1); {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 104: Hoare triple {44772#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 105: Hoare triple {44772#false} assume !(1 == ~t10_pc~0); {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 106: Hoare triple {44772#false} is_transmit10_triggered_~__retres1~10#1 := 0; {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 107: Hoare triple {44772#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 108: Hoare triple {44772#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 109: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp___9~0#1); {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 110: Hoare triple {44772#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 111: Hoare triple {44772#false} assume 1 == ~t11_pc~0; {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 112: Hoare triple {44772#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 113: Hoare triple {44772#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 114: Hoare triple {44772#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 115: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp___10~0#1); {44772#false} is VALID [2022-02-21 04:23:21,370 INFO L290 TraceCheckUtils]: 116: Hoare triple {44772#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 117: Hoare triple {44772#false} assume !(1 == ~t12_pc~0); {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 118: Hoare triple {44772#false} is_transmit12_triggered_~__retres1~12#1 := 0; {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 119: Hoare triple {44772#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 120: Hoare triple {44772#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 121: Hoare triple {44772#false} assume !(0 != activate_threads_~tmp___11~0#1); {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 122: Hoare triple {44772#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 123: Hoare triple {44772#false} assume !(1 == ~M_E~0); {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 124: Hoare triple {44772#false} assume !(1 == ~T1_E~0); {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 125: Hoare triple {44772#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 126: Hoare triple {44772#false} assume !(1 == ~T3_E~0); {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 127: Hoare triple {44772#false} assume !(1 == ~T4_E~0); {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 128: Hoare triple {44772#false} assume !(1 == ~T5_E~0); {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 129: Hoare triple {44772#false} assume !(1 == ~T6_E~0); {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 130: Hoare triple {44772#false} assume !(1 == ~T7_E~0); {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 131: Hoare triple {44772#false} assume !(1 == ~T8_E~0); {44772#false} is VALID [2022-02-21 04:23:21,371 INFO L290 TraceCheckUtils]: 132: Hoare triple {44772#false} assume !(1 == ~T9_E~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 133: Hoare triple {44772#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 134: Hoare triple {44772#false} assume !(1 == ~T11_E~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 135: Hoare triple {44772#false} assume !(1 == ~T12_E~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 136: Hoare triple {44772#false} assume !(1 == ~E_M~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 137: Hoare triple {44772#false} assume !(1 == ~E_1~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 138: Hoare triple {44772#false} assume !(1 == ~E_2~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 139: Hoare triple {44772#false} assume !(1 == ~E_3~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 140: Hoare triple {44772#false} assume !(1 == ~E_4~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 141: Hoare triple {44772#false} assume 1 == ~E_5~0;~E_5~0 := 2; {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 142: Hoare triple {44772#false} assume !(1 == ~E_6~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 143: Hoare triple {44772#false} assume !(1 == ~E_7~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 144: Hoare triple {44772#false} assume !(1 == ~E_8~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 145: Hoare triple {44772#false} assume !(1 == ~E_9~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 146: Hoare triple {44772#false} assume !(1 == ~E_10~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 147: Hoare triple {44772#false} assume !(1 == ~E_11~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 148: Hoare triple {44772#false} assume !(1 == ~E_12~0); {44772#false} is VALID [2022-02-21 04:23:21,372 INFO L290 TraceCheckUtils]: 149: Hoare triple {44772#false} assume { :end_inline_reset_delta_events } true; {44772#false} is VALID [2022-02-21 04:23:21,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,373 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,373 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901640217] [2022-02-21 04:23:21,373 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [901640217] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,373 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,373 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,373 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1813754495] [2022-02-21 04:23:21,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,374 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:21,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:21,374 INFO L85 PathProgramCache]: Analyzing trace with hash -488091310, now seen corresponding path program 1 times [2022-02-21 04:23:21,374 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:21,374 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092708062] [2022-02-21 04:23:21,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:21,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:21,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:21,404 INFO L290 TraceCheckUtils]: 0: Hoare triple {44774#true} assume !false; {44774#true} is VALID [2022-02-21 04:23:21,404 INFO L290 TraceCheckUtils]: 1: Hoare triple {44774#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {44774#true} is VALID [2022-02-21 04:23:21,404 INFO L290 TraceCheckUtils]: 2: Hoare triple {44774#true} assume !false; {44774#true} is VALID [2022-02-21 04:23:21,404 INFO L290 TraceCheckUtils]: 3: Hoare triple {44774#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {44774#true} is VALID [2022-02-21 04:23:21,404 INFO L290 TraceCheckUtils]: 4: Hoare triple {44774#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {44774#true} is VALID [2022-02-21 04:23:21,404 INFO L290 TraceCheckUtils]: 5: Hoare triple {44774#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {44774#true} is VALID [2022-02-21 04:23:21,405 INFO L290 TraceCheckUtils]: 6: Hoare triple {44774#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {44774#true} is VALID [2022-02-21 04:23:21,405 INFO L290 TraceCheckUtils]: 7: Hoare triple {44774#true} assume !(0 != eval_~tmp~0#1); {44774#true} is VALID [2022-02-21 04:23:21,405 INFO L290 TraceCheckUtils]: 8: Hoare triple {44774#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {44774#true} is VALID [2022-02-21 04:23:21,405 INFO L290 TraceCheckUtils]: 9: Hoare triple {44774#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {44774#true} is VALID [2022-02-21 04:23:21,405 INFO L290 TraceCheckUtils]: 10: Hoare triple {44774#true} assume 0 == ~M_E~0;~M_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,405 INFO L290 TraceCheckUtils]: 11: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,406 INFO L290 TraceCheckUtils]: 12: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,406 INFO L290 TraceCheckUtils]: 13: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,406 INFO L290 TraceCheckUtils]: 14: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,407 INFO L290 TraceCheckUtils]: 15: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,407 INFO L290 TraceCheckUtils]: 16: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,407 INFO L290 TraceCheckUtils]: 17: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,407 INFO L290 TraceCheckUtils]: 18: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,408 INFO L290 TraceCheckUtils]: 19: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,408 INFO L290 TraceCheckUtils]: 20: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,408 INFO L290 TraceCheckUtils]: 21: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,408 INFO L290 TraceCheckUtils]: 22: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,409 INFO L290 TraceCheckUtils]: 23: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,409 INFO L290 TraceCheckUtils]: 24: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,409 INFO L290 TraceCheckUtils]: 25: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,409 INFO L290 TraceCheckUtils]: 26: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,410 INFO L290 TraceCheckUtils]: 27: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,410 INFO L290 TraceCheckUtils]: 28: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,410 INFO L290 TraceCheckUtils]: 29: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,410 INFO L290 TraceCheckUtils]: 30: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,411 INFO L290 TraceCheckUtils]: 31: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,411 INFO L290 TraceCheckUtils]: 32: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,411 INFO L290 TraceCheckUtils]: 33: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,412 INFO L290 TraceCheckUtils]: 34: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,412 INFO L290 TraceCheckUtils]: 35: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,412 INFO L290 TraceCheckUtils]: 36: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,412 INFO L290 TraceCheckUtils]: 37: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,413 INFO L290 TraceCheckUtils]: 38: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,413 INFO L290 TraceCheckUtils]: 39: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,413 INFO L290 TraceCheckUtils]: 40: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,413 INFO L290 TraceCheckUtils]: 41: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,414 INFO L290 TraceCheckUtils]: 42: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,414 INFO L290 TraceCheckUtils]: 43: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,414 INFO L290 TraceCheckUtils]: 44: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,414 INFO L290 TraceCheckUtils]: 45: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,415 INFO L290 TraceCheckUtils]: 46: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,415 INFO L290 TraceCheckUtils]: 47: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,415 INFO L290 TraceCheckUtils]: 48: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,415 INFO L290 TraceCheckUtils]: 49: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,416 INFO L290 TraceCheckUtils]: 50: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,416 INFO L290 TraceCheckUtils]: 51: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,416 INFO L290 TraceCheckUtils]: 52: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,416 INFO L290 TraceCheckUtils]: 53: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,417 INFO L290 TraceCheckUtils]: 54: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,417 INFO L290 TraceCheckUtils]: 55: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,417 INFO L290 TraceCheckUtils]: 56: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,417 INFO L290 TraceCheckUtils]: 57: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,418 INFO L290 TraceCheckUtils]: 58: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,418 INFO L290 TraceCheckUtils]: 59: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,418 INFO L290 TraceCheckUtils]: 60: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,419 INFO L290 TraceCheckUtils]: 61: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,419 INFO L290 TraceCheckUtils]: 62: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,419 INFO L290 TraceCheckUtils]: 63: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,419 INFO L290 TraceCheckUtils]: 64: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,420 INFO L290 TraceCheckUtils]: 65: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,420 INFO L290 TraceCheckUtils]: 66: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,420 INFO L290 TraceCheckUtils]: 67: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,420 INFO L290 TraceCheckUtils]: 68: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,421 INFO L290 TraceCheckUtils]: 69: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,421 INFO L290 TraceCheckUtils]: 70: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,421 INFO L290 TraceCheckUtils]: 71: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,421 INFO L290 TraceCheckUtils]: 72: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,422 INFO L290 TraceCheckUtils]: 73: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,422 INFO L290 TraceCheckUtils]: 74: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,422 INFO L290 TraceCheckUtils]: 75: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,422 INFO L290 TraceCheckUtils]: 76: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,423 INFO L290 TraceCheckUtils]: 77: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,423 INFO L290 TraceCheckUtils]: 78: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,423 INFO L290 TraceCheckUtils]: 79: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,423 INFO L290 TraceCheckUtils]: 80: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,424 INFO L290 TraceCheckUtils]: 81: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,424 INFO L290 TraceCheckUtils]: 82: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,424 INFO L290 TraceCheckUtils]: 83: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,425 INFO L290 TraceCheckUtils]: 84: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,425 INFO L290 TraceCheckUtils]: 85: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,425 INFO L290 TraceCheckUtils]: 86: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,425 INFO L290 TraceCheckUtils]: 87: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,426 INFO L290 TraceCheckUtils]: 88: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,426 INFO L290 TraceCheckUtils]: 89: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,426 INFO L290 TraceCheckUtils]: 90: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,426 INFO L290 TraceCheckUtils]: 91: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,427 INFO L290 TraceCheckUtils]: 92: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,427 INFO L290 TraceCheckUtils]: 93: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,427 INFO L290 TraceCheckUtils]: 94: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,427 INFO L290 TraceCheckUtils]: 95: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,428 INFO L290 TraceCheckUtils]: 96: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,428 INFO L290 TraceCheckUtils]: 97: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,428 INFO L290 TraceCheckUtils]: 98: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,428 INFO L290 TraceCheckUtils]: 99: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,429 INFO L290 TraceCheckUtils]: 100: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,429 INFO L290 TraceCheckUtils]: 101: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,429 INFO L290 TraceCheckUtils]: 102: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,429 INFO L290 TraceCheckUtils]: 103: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,430 INFO L290 TraceCheckUtils]: 104: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,430 INFO L290 TraceCheckUtils]: 105: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,430 INFO L290 TraceCheckUtils]: 106: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,430 INFO L290 TraceCheckUtils]: 107: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,431 INFO L290 TraceCheckUtils]: 108: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,431 INFO L290 TraceCheckUtils]: 109: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,431 INFO L290 TraceCheckUtils]: 110: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,431 INFO L290 TraceCheckUtils]: 111: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,432 INFO L290 TraceCheckUtils]: 112: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,432 INFO L290 TraceCheckUtils]: 113: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,432 INFO L290 TraceCheckUtils]: 114: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {44776#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:21,433 INFO L290 TraceCheckUtils]: 115: Hoare triple {44776#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {44775#false} is VALID [2022-02-21 04:23:21,433 INFO L290 TraceCheckUtils]: 116: Hoare triple {44775#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,433 INFO L290 TraceCheckUtils]: 117: Hoare triple {44775#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,433 INFO L290 TraceCheckUtils]: 118: Hoare triple {44775#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,433 INFO L290 TraceCheckUtils]: 119: Hoare triple {44775#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,433 INFO L290 TraceCheckUtils]: 120: Hoare triple {44775#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,433 INFO L290 TraceCheckUtils]: 121: Hoare triple {44775#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,433 INFO L290 TraceCheckUtils]: 122: Hoare triple {44775#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,433 INFO L290 TraceCheckUtils]: 123: Hoare triple {44775#false} assume !(1 == ~T8_E~0); {44775#false} is VALID [2022-02-21 04:23:21,434 INFO L290 TraceCheckUtils]: 124: Hoare triple {44775#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,434 INFO L290 TraceCheckUtils]: 125: Hoare triple {44775#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,434 INFO L290 TraceCheckUtils]: 126: Hoare triple {44775#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,434 INFO L290 TraceCheckUtils]: 127: Hoare triple {44775#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,434 INFO L290 TraceCheckUtils]: 128: Hoare triple {44775#false} assume 1 == ~E_M~0;~E_M~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,434 INFO L290 TraceCheckUtils]: 129: Hoare triple {44775#false} assume 1 == ~E_1~0;~E_1~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,434 INFO L290 TraceCheckUtils]: 130: Hoare triple {44775#false} assume 1 == ~E_2~0;~E_2~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,434 INFO L290 TraceCheckUtils]: 131: Hoare triple {44775#false} assume !(1 == ~E_3~0); {44775#false} is VALID [2022-02-21 04:23:21,434 INFO L290 TraceCheckUtils]: 132: Hoare triple {44775#false} assume 1 == ~E_4~0;~E_4~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,435 INFO L290 TraceCheckUtils]: 133: Hoare triple {44775#false} assume 1 == ~E_5~0;~E_5~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,435 INFO L290 TraceCheckUtils]: 134: Hoare triple {44775#false} assume 1 == ~E_6~0;~E_6~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,435 INFO L290 TraceCheckUtils]: 135: Hoare triple {44775#false} assume 1 == ~E_7~0;~E_7~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,435 INFO L290 TraceCheckUtils]: 136: Hoare triple {44775#false} assume 1 == ~E_8~0;~E_8~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,435 INFO L290 TraceCheckUtils]: 137: Hoare triple {44775#false} assume 1 == ~E_9~0;~E_9~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,435 INFO L290 TraceCheckUtils]: 138: Hoare triple {44775#false} assume 1 == ~E_10~0;~E_10~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,435 INFO L290 TraceCheckUtils]: 139: Hoare triple {44775#false} assume !(1 == ~E_11~0); {44775#false} is VALID [2022-02-21 04:23:21,435 INFO L290 TraceCheckUtils]: 140: Hoare triple {44775#false} assume 1 == ~E_12~0;~E_12~0 := 2; {44775#false} is VALID [2022-02-21 04:23:21,435 INFO L290 TraceCheckUtils]: 141: Hoare triple {44775#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {44775#false} is VALID [2022-02-21 04:23:21,436 INFO L290 TraceCheckUtils]: 142: Hoare triple {44775#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {44775#false} is VALID [2022-02-21 04:23:21,436 INFO L290 TraceCheckUtils]: 143: Hoare triple {44775#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {44775#false} is VALID [2022-02-21 04:23:21,436 INFO L290 TraceCheckUtils]: 144: Hoare triple {44775#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {44775#false} is VALID [2022-02-21 04:23:21,436 INFO L290 TraceCheckUtils]: 145: Hoare triple {44775#false} assume !(0 == start_simulation_~tmp~3#1); {44775#false} is VALID [2022-02-21 04:23:21,436 INFO L290 TraceCheckUtils]: 146: Hoare triple {44775#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {44775#false} is VALID [2022-02-21 04:23:21,436 INFO L290 TraceCheckUtils]: 147: Hoare triple {44775#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {44775#false} is VALID [2022-02-21 04:23:21,436 INFO L290 TraceCheckUtils]: 148: Hoare triple {44775#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {44775#false} is VALID [2022-02-21 04:23:21,436 INFO L290 TraceCheckUtils]: 149: Hoare triple {44775#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {44775#false} is VALID [2022-02-21 04:23:21,436 INFO L290 TraceCheckUtils]: 150: Hoare triple {44775#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {44775#false} is VALID [2022-02-21 04:23:21,437 INFO L290 TraceCheckUtils]: 151: Hoare triple {44775#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {44775#false} is VALID [2022-02-21 04:23:21,437 INFO L290 TraceCheckUtils]: 152: Hoare triple {44775#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {44775#false} is VALID [2022-02-21 04:23:21,437 INFO L290 TraceCheckUtils]: 153: Hoare triple {44775#false} assume !(0 != start_simulation_~tmp___0~1#1); {44775#false} is VALID [2022-02-21 04:23:21,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,437 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,438 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1092708062] [2022-02-21 04:23:21,438 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1092708062] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,438 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,438 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,438 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062981749] [2022-02-21 04:23:21,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,439 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:21,439 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:21,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:21,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:21,439 INFO L87 Difference]: Start difference. First operand 1788 states and 2646 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:22,565 INFO L93 Difference]: Finished difference Result 1788 states and 2645 transitions. [2022-02-21 04:23:22,575 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:22,575 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,660 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:22,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2645 transitions. [2022-02-21 04:23:22,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:22,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2645 transitions. [2022-02-21 04:23:22,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:22,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:22,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2645 transitions. [2022-02-21 04:23:22,797 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:22,797 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2022-02-21 04:23:22,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2645 transitions. [2022-02-21 04:23:22,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:22,811 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:22,812 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2645 transitions. Second operand has 1788 states, 1788 states have (on average 1.4793064876957494) internal successors, (2645), 1787 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,814 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2645 transitions. Second operand has 1788 states, 1788 states have (on average 1.4793064876957494) internal successors, (2645), 1787 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,815 INFO L87 Difference]: Start difference. First operand 1788 states and 2645 transitions. Second operand has 1788 states, 1788 states have (on average 1.4793064876957494) internal successors, (2645), 1787 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:22,878 INFO L93 Difference]: Finished difference Result 1788 states and 2645 transitions. [2022-02-21 04:23:22,878 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2645 transitions. [2022-02-21 04:23:22,880 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:22,880 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:22,881 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4793064876957494) internal successors, (2645), 1787 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2645 transitions. [2022-02-21 04:23:22,882 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4793064876957494) internal successors, (2645), 1787 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2645 transitions. [2022-02-21 04:23:22,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:22,949 INFO L93 Difference]: Finished difference Result 1788 states and 2645 transitions. [2022-02-21 04:23:22,949 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2645 transitions. [2022-02-21 04:23:22,951 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:22,951 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:22,951 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:22,951 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:22,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4793064876957494) internal successors, (2645), 1787 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2645 transitions. [2022-02-21 04:23:23,030 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2022-02-21 04:23:23,030 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2022-02-21 04:23:23,030 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:23:23,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2645 transitions. [2022-02-21 04:23:23,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:23,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:23,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:23,034 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:23,034 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:23,034 INFO L791 eck$LassoCheckResult]: Stem: 47354#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47355#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 46875#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46876#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46930#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 48269#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47363#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47166#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46565#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46566#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47788#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47901#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 48335#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 48336#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47294#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 47295#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 47817#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 47736#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47329#L1201 assume !(0 == ~M_E~0); 47330#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48176#L1206-1 assume !(0 == ~T2_E~0); 48162#L1211-1 assume !(0 == ~T3_E~0); 48163#L1216-1 assume !(0 == ~T4_E~0); 47151#L1221-1 assume !(0 == ~T5_E~0); 47152#L1226-1 assume !(0 == ~T6_E~0); 46790#L1231-1 assume !(0 == ~T7_E~0); 46791#L1236-1 assume !(0 == ~T8_E~0); 48199#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47190#L1246-1 assume !(0 == ~T10_E~0); 47191#L1251-1 assume !(0 == ~T11_E~0); 47327#L1256-1 assume !(0 == ~T12_E~0); 46578#L1261-1 assume !(0 == ~E_M~0); 46579#L1266-1 assume !(0 == ~E_1~0); 48321#L1271-1 assume !(0 == ~E_2~0); 47883#L1276-1 assume !(0 == ~E_3~0); 47884#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 47831#L1286-1 assume !(0 == ~E_5~0); 47041#L1291-1 assume !(0 == ~E_6~0); 47042#L1296-1 assume !(0 == ~E_7~0); 47617#L1301-1 assume !(0 == ~E_8~0); 47618#L1306-1 assume !(0 == ~E_9~0); 48098#L1311-1 assume !(0 == ~E_10~0); 46992#L1316-1 assume !(0 == ~E_11~0); 46993#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 47635#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47636#L593 assume 1 == ~m_pc~0; 47780#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46882#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48308#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47842#L1492 assume !(0 != activate_threads_~tmp~1#1); 47843#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48134#L612 assume !(1 == ~t1_pc~0); 48135#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48264#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47264#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46886#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46887#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47306#L631 assume 1 == ~t2_pc~0; 47241#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46663#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46664#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47500#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 47501#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46959#L650 assume !(1 == ~t3_pc~0); 46960#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47660#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46883#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46616#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 46617#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47809#L669 assume 1 == ~t4_pc~0; 47810#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48168#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47293#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46825#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 46826#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47050#L688 assume !(1 == ~t5_pc~0); 46841#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46842#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47760#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47696#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 47697#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47827#L707 assume 1 == ~t6_pc~0; 48233#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47470#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47471#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48231#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 47768#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47328#L726 assume 1 == ~t7_pc~0; 47229#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46926#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47967#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48242#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 46695#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46696#L745 assume !(1 == ~t8_pc~0); 47143#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47162#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48000#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47548#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47549#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48059#L764 assume 1 == ~t9_pc~0; 47326#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47168#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47845#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48292#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 46715#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46716#L783 assume !(1 == ~t10_pc~0); 46777#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46778#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46819#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46820#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 47287#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48170#L802 assume 1 == ~t11_pc~0; 48152#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46660#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46661#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47153#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 47154#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47263#L821 assume !(1 == ~t12_pc~0); 47514#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47610#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46667#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46668#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 48208#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47854#L1339 assume !(1 == ~M_E~0); 47855#L1339-2 assume !(1 == ~T1_E~0); 48243#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48244#L1349-1 assume !(1 == ~T3_E~0); 47629#L1354-1 assume !(1 == ~T4_E~0); 47630#L1359-1 assume !(1 == ~T5_E~0); 48032#L1364-1 assume !(1 == ~T6_E~0); 47093#L1369-1 assume !(1 == ~T7_E~0); 47094#L1374-1 assume !(1 == ~T8_E~0); 47633#L1379-1 assume !(1 == ~T9_E~0); 47634#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47731#L1389-1 assume !(1 == ~T11_E~0); 48202#L1394-1 assume !(1 == ~T12_E~0); 48203#L1399-1 assume !(1 == ~E_M~0); 48293#L1404-1 assume !(1 == ~E_1~0); 47194#L1409-1 assume !(1 == ~E_2~0); 47195#L1414-1 assume !(1 == ~E_3~0); 47919#L1419-1 assume !(1 == ~E_4~0); 46833#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46834#L1429-1 assume !(1 == ~E_6~0); 47644#L1434-1 assume !(1 == ~E_7~0); 48223#L1439-1 assume !(1 == ~E_8~0); 46871#L1444-1 assume !(1 == ~E_9~0); 46872#L1449-1 assume !(1 == ~E_10~0); 47246#L1454-1 assume !(1 == ~E_11~0); 47247#L1459-1 assume !(1 == ~E_12~0); 47765#L1464-1 assume { :end_inline_reset_delta_events } true; 47005#L1810-2 [2022-02-21 04:23:23,035 INFO L793 eck$LassoCheckResult]: Loop: 47005#L1810-2 assume !false; 47449#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47365#L1176 assume !false; 47927#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47499#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46703#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47253#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 47254#L1003 assume !(0 != eval_~tmp~0#1); 46897#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46898#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48086#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47869#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47870#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47764#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46954#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46955#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47421#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47027#L1231-3 assume !(0 == ~T7_E~0); 47028#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47272#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48254#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48155#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47860#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 46971#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46972#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47015#L1271-3 assume !(0 == ~E_2~0); 47016#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47394#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47395#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47916#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47917#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48332#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48289#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47506#L1311-3 assume !(0 == ~E_10~0); 46895#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46896#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 46973#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47609#L593-42 assume 1 == ~m_pc~0; 48002#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47767#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48316#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48317#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46796#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46797#L612-42 assume !(1 == ~t1_pc~0); 47718#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 48111#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48232#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46884#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46885#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47580#L631-42 assume 1 == ~t2_pc~0; 46649#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46650#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47569#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47445#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47446#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47046#L650-42 assume 1 == ~t3_pc~0; 46608#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46609#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48260#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47239#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47240#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48224#L669-42 assume 1 == ~t4_pc~0; 47520#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46607#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48035#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47925#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 47822#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47823#L688-42 assume 1 == ~t5_pc~0; 47914#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48115#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46747#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46748#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46821#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46638#L707-42 assume 1 == ~t6_pc~0; 46640#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48296#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48040#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48041#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47790#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47791#L726-42 assume 1 == ~t7_pc~0; 48068#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48094#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48095#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47509#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47510#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47613#L745-42 assume 1 == ~t8_pc~0; 47650#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47652#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46979#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46624#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46625#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47350#L764-42 assume 1 == ~t9_pc~0; 47486#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47839#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47840#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46910#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46911#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46964#L783-42 assume 1 == ~t10_pc~0; 46580#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46581#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47176#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47309#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48326#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48010#L802-42 assume 1 == ~t11_pc~0; 47111#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46722#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46723#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46673#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46674#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47850#L821-42 assume 1 == ~t12_pc~0; 47851#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47216#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46576#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46577#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47556#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47546#L1339-3 assume !(1 == ~M_E~0); 47547#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47698#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47808#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47225#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47226#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47819#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48315#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48222#L1374-3 assume !(1 == ~T8_E~0); 47047#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47048#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47223#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47224#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47433#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48229#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48197#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48198#L1414-3 assume !(1 == ~E_3~0); 48253#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48012#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46931#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46932#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47818#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46859#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46860#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 46976#L1454-3 assume !(1 == ~E_11~0); 47813#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47814#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47472#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46769#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47029#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47030#L1829 assume !(0 == start_simulation_~tmp~3#1); 46751#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 46752#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47552#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47553#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47832#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47833#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47453#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 47004#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 47005#L1810-2 [2022-02-21 04:23:23,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:23,036 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2022-02-21 04:23:23,036 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:23,036 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104413898] [2022-02-21 04:23:23,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:23,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:23,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:23,055 INFO L290 TraceCheckUtils]: 0: Hoare triple {51932#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {51932#true} is VALID [2022-02-21 04:23:23,056 INFO L290 TraceCheckUtils]: 1: Hoare triple {51932#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {51934#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:23,056 INFO L290 TraceCheckUtils]: 2: Hoare triple {51934#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {51934#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:23,056 INFO L290 TraceCheckUtils]: 3: Hoare triple {51934#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {51934#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:23,056 INFO L290 TraceCheckUtils]: 4: Hoare triple {51934#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {51934#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:23,057 INFO L290 TraceCheckUtils]: 5: Hoare triple {51934#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {51934#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:23,057 INFO L290 TraceCheckUtils]: 6: Hoare triple {51934#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {51934#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:23,057 INFO L290 TraceCheckUtils]: 7: Hoare triple {51934#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {51934#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:23,058 INFO L290 TraceCheckUtils]: 8: Hoare triple {51934#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {51934#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:23,058 INFO L290 TraceCheckUtils]: 9: Hoare triple {51934#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {51934#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:23,058 INFO L290 TraceCheckUtils]: 10: Hoare triple {51934#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {51934#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:23,058 INFO L290 TraceCheckUtils]: 11: Hoare triple {51934#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {51933#false} is VALID [2022-02-21 04:23:23,058 INFO L290 TraceCheckUtils]: 12: Hoare triple {51933#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {51933#false} is VALID [2022-02-21 04:23:23,059 INFO L290 TraceCheckUtils]: 13: Hoare triple {51933#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {51933#false} is VALID [2022-02-21 04:23:23,059 INFO L290 TraceCheckUtils]: 14: Hoare triple {51933#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {51933#false} is VALID [2022-02-21 04:23:23,059 INFO L290 TraceCheckUtils]: 15: Hoare triple {51933#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {51933#false} is VALID [2022-02-21 04:23:23,059 INFO L290 TraceCheckUtils]: 16: Hoare triple {51933#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {51933#false} is VALID [2022-02-21 04:23:23,059 INFO L290 TraceCheckUtils]: 17: Hoare triple {51933#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {51933#false} is VALID [2022-02-21 04:23:23,059 INFO L290 TraceCheckUtils]: 18: Hoare triple {51933#false} assume !(0 == ~M_E~0); {51933#false} is VALID [2022-02-21 04:23:23,059 INFO L290 TraceCheckUtils]: 19: Hoare triple {51933#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {51933#false} is VALID [2022-02-21 04:23:23,059 INFO L290 TraceCheckUtils]: 20: Hoare triple {51933#false} assume !(0 == ~T2_E~0); {51933#false} is VALID [2022-02-21 04:23:23,059 INFO L290 TraceCheckUtils]: 21: Hoare triple {51933#false} assume !(0 == ~T3_E~0); {51933#false} is VALID [2022-02-21 04:23:23,060 INFO L290 TraceCheckUtils]: 22: Hoare triple {51933#false} assume !(0 == ~T4_E~0); {51933#false} is VALID [2022-02-21 04:23:23,060 INFO L290 TraceCheckUtils]: 23: Hoare triple {51933#false} assume !(0 == ~T5_E~0); {51933#false} is VALID [2022-02-21 04:23:23,060 INFO L290 TraceCheckUtils]: 24: Hoare triple {51933#false} assume !(0 == ~T6_E~0); {51933#false} is VALID [2022-02-21 04:23:23,060 INFO L290 TraceCheckUtils]: 25: Hoare triple {51933#false} assume !(0 == ~T7_E~0); {51933#false} is VALID [2022-02-21 04:23:23,060 INFO L290 TraceCheckUtils]: 26: Hoare triple {51933#false} assume !(0 == ~T8_E~0); {51933#false} is VALID [2022-02-21 04:23:23,060 INFO L290 TraceCheckUtils]: 27: Hoare triple {51933#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {51933#false} is VALID [2022-02-21 04:23:23,060 INFO L290 TraceCheckUtils]: 28: Hoare triple {51933#false} assume !(0 == ~T10_E~0); {51933#false} is VALID [2022-02-21 04:23:23,060 INFO L290 TraceCheckUtils]: 29: Hoare triple {51933#false} assume !(0 == ~T11_E~0); {51933#false} is VALID [2022-02-21 04:23:23,061 INFO L290 TraceCheckUtils]: 30: Hoare triple {51933#false} assume !(0 == ~T12_E~0); {51933#false} is VALID [2022-02-21 04:23:23,061 INFO L290 TraceCheckUtils]: 31: Hoare triple {51933#false} assume !(0 == ~E_M~0); {51933#false} is VALID [2022-02-21 04:23:23,061 INFO L290 TraceCheckUtils]: 32: Hoare triple {51933#false} assume !(0 == ~E_1~0); {51933#false} is VALID [2022-02-21 04:23:23,061 INFO L290 TraceCheckUtils]: 33: Hoare triple {51933#false} assume !(0 == ~E_2~0); {51933#false} is VALID [2022-02-21 04:23:23,061 INFO L290 TraceCheckUtils]: 34: Hoare triple {51933#false} assume !(0 == ~E_3~0); {51933#false} is VALID [2022-02-21 04:23:23,061 INFO L290 TraceCheckUtils]: 35: Hoare triple {51933#false} assume 0 == ~E_4~0;~E_4~0 := 1; {51933#false} is VALID [2022-02-21 04:23:23,061 INFO L290 TraceCheckUtils]: 36: Hoare triple {51933#false} assume !(0 == ~E_5~0); {51933#false} is VALID [2022-02-21 04:23:23,061 INFO L290 TraceCheckUtils]: 37: Hoare triple {51933#false} assume !(0 == ~E_6~0); {51933#false} is VALID [2022-02-21 04:23:23,061 INFO L290 TraceCheckUtils]: 38: Hoare triple {51933#false} assume !(0 == ~E_7~0); {51933#false} is VALID [2022-02-21 04:23:23,062 INFO L290 TraceCheckUtils]: 39: Hoare triple {51933#false} assume !(0 == ~E_8~0); {51933#false} is VALID [2022-02-21 04:23:23,062 INFO L290 TraceCheckUtils]: 40: Hoare triple {51933#false} assume !(0 == ~E_9~0); {51933#false} is VALID [2022-02-21 04:23:23,062 INFO L290 TraceCheckUtils]: 41: Hoare triple {51933#false} assume !(0 == ~E_10~0); {51933#false} is VALID [2022-02-21 04:23:23,062 INFO L290 TraceCheckUtils]: 42: Hoare triple {51933#false} assume !(0 == ~E_11~0); {51933#false} is VALID [2022-02-21 04:23:23,062 INFO L290 TraceCheckUtils]: 43: Hoare triple {51933#false} assume 0 == ~E_12~0;~E_12~0 := 1; {51933#false} is VALID [2022-02-21 04:23:23,062 INFO L290 TraceCheckUtils]: 44: Hoare triple {51933#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {51933#false} is VALID [2022-02-21 04:23:23,062 INFO L290 TraceCheckUtils]: 45: Hoare triple {51933#false} assume 1 == ~m_pc~0; {51933#false} is VALID [2022-02-21 04:23:23,062 INFO L290 TraceCheckUtils]: 46: Hoare triple {51933#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {51933#false} is VALID [2022-02-21 04:23:23,062 INFO L290 TraceCheckUtils]: 47: Hoare triple {51933#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {51933#false} is VALID [2022-02-21 04:23:23,063 INFO L290 TraceCheckUtils]: 48: Hoare triple {51933#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {51933#false} is VALID [2022-02-21 04:23:23,063 INFO L290 TraceCheckUtils]: 49: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp~1#1); {51933#false} is VALID [2022-02-21 04:23:23,063 INFO L290 TraceCheckUtils]: 50: Hoare triple {51933#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {51933#false} is VALID [2022-02-21 04:23:23,075 INFO L290 TraceCheckUtils]: 51: Hoare triple {51933#false} assume !(1 == ~t1_pc~0); {51933#false} is VALID [2022-02-21 04:23:23,075 INFO L290 TraceCheckUtils]: 52: Hoare triple {51933#false} is_transmit1_triggered_~__retres1~1#1 := 0; {51933#false} is VALID [2022-02-21 04:23:23,075 INFO L290 TraceCheckUtils]: 53: Hoare triple {51933#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {51933#false} is VALID [2022-02-21 04:23:23,075 INFO L290 TraceCheckUtils]: 54: Hoare triple {51933#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {51933#false} is VALID [2022-02-21 04:23:23,075 INFO L290 TraceCheckUtils]: 55: Hoare triple {51933#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {51933#false} is VALID [2022-02-21 04:23:23,075 INFO L290 TraceCheckUtils]: 56: Hoare triple {51933#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {51933#false} is VALID [2022-02-21 04:23:23,076 INFO L290 TraceCheckUtils]: 57: Hoare triple {51933#false} assume 1 == ~t2_pc~0; {51933#false} is VALID [2022-02-21 04:23:23,076 INFO L290 TraceCheckUtils]: 58: Hoare triple {51933#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {51933#false} is VALID [2022-02-21 04:23:23,076 INFO L290 TraceCheckUtils]: 59: Hoare triple {51933#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {51933#false} is VALID [2022-02-21 04:23:23,076 INFO L290 TraceCheckUtils]: 60: Hoare triple {51933#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {51933#false} is VALID [2022-02-21 04:23:23,076 INFO L290 TraceCheckUtils]: 61: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp___1~0#1); {51933#false} is VALID [2022-02-21 04:23:23,076 INFO L290 TraceCheckUtils]: 62: Hoare triple {51933#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {51933#false} is VALID [2022-02-21 04:23:23,076 INFO L290 TraceCheckUtils]: 63: Hoare triple {51933#false} assume !(1 == ~t3_pc~0); {51933#false} is VALID [2022-02-21 04:23:23,076 INFO L290 TraceCheckUtils]: 64: Hoare triple {51933#false} is_transmit3_triggered_~__retres1~3#1 := 0; {51933#false} is VALID [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 65: Hoare triple {51933#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {51933#false} is VALID [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 66: Hoare triple {51933#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {51933#false} is VALID [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 67: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp___2~0#1); {51933#false} is VALID [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 68: Hoare triple {51933#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {51933#false} is VALID [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 69: Hoare triple {51933#false} assume 1 == ~t4_pc~0; {51933#false} is VALID [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 70: Hoare triple {51933#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {51933#false} is VALID [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 71: Hoare triple {51933#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {51933#false} is VALID [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 72: Hoare triple {51933#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {51933#false} is VALID [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 73: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp___3~0#1); {51933#false} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 74: Hoare triple {51933#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {51933#false} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 75: Hoare triple {51933#false} assume !(1 == ~t5_pc~0); {51933#false} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 76: Hoare triple {51933#false} is_transmit5_triggered_~__retres1~5#1 := 0; {51933#false} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 77: Hoare triple {51933#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {51933#false} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 78: Hoare triple {51933#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {51933#false} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 79: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp___4~0#1); {51933#false} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 80: Hoare triple {51933#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {51933#false} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 81: Hoare triple {51933#false} assume 1 == ~t6_pc~0; {51933#false} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 82: Hoare triple {51933#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {51933#false} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 83: Hoare triple {51933#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {51933#false} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 84: Hoare triple {51933#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {51933#false} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 85: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp___5~0#1); {51933#false} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 86: Hoare triple {51933#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {51933#false} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 87: Hoare triple {51933#false} assume 1 == ~t7_pc~0; {51933#false} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 88: Hoare triple {51933#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {51933#false} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 89: Hoare triple {51933#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {51933#false} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 90: Hoare triple {51933#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {51933#false} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 91: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp___6~0#1); {51933#false} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 92: Hoare triple {51933#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {51933#false} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 93: Hoare triple {51933#false} assume !(1 == ~t8_pc~0); {51933#false} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 94: Hoare triple {51933#false} is_transmit8_triggered_~__retres1~8#1 := 0; {51933#false} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 95: Hoare triple {51933#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {51933#false} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 96: Hoare triple {51933#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {51933#false} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 97: Hoare triple {51933#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {51933#false} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 98: Hoare triple {51933#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {51933#false} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 99: Hoare triple {51933#false} assume 1 == ~t9_pc~0; {51933#false} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 100: Hoare triple {51933#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {51933#false} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 101: Hoare triple {51933#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {51933#false} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 102: Hoare triple {51933#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {51933#false} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 103: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp___8~0#1); {51933#false} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 104: Hoare triple {51933#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {51933#false} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 105: Hoare triple {51933#false} assume !(1 == ~t10_pc~0); {51933#false} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 106: Hoare triple {51933#false} is_transmit10_triggered_~__retres1~10#1 := 0; {51933#false} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 107: Hoare triple {51933#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {51933#false} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 108: Hoare triple {51933#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {51933#false} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 109: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp___9~0#1); {51933#false} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 110: Hoare triple {51933#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {51933#false} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 111: Hoare triple {51933#false} assume 1 == ~t11_pc~0; {51933#false} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 112: Hoare triple {51933#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {51933#false} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 113: Hoare triple {51933#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {51933#false} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 114: Hoare triple {51933#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {51933#false} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 115: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp___10~0#1); {51933#false} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 116: Hoare triple {51933#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {51933#false} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 117: Hoare triple {51933#false} assume !(1 == ~t12_pc~0); {51933#false} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 118: Hoare triple {51933#false} is_transmit12_triggered_~__retres1~12#1 := 0; {51933#false} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 119: Hoare triple {51933#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {51933#false} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 120: Hoare triple {51933#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {51933#false} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 121: Hoare triple {51933#false} assume !(0 != activate_threads_~tmp___11~0#1); {51933#false} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 122: Hoare triple {51933#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {51933#false} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 123: Hoare triple {51933#false} assume !(1 == ~M_E~0); {51933#false} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 124: Hoare triple {51933#false} assume !(1 == ~T1_E~0); {51933#false} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 125: Hoare triple {51933#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {51933#false} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 126: Hoare triple {51933#false} assume !(1 == ~T3_E~0); {51933#false} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 127: Hoare triple {51933#false} assume !(1 == ~T4_E~0); {51933#false} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 128: Hoare triple {51933#false} assume !(1 == ~T5_E~0); {51933#false} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 129: Hoare triple {51933#false} assume !(1 == ~T6_E~0); {51933#false} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 130: Hoare triple {51933#false} assume !(1 == ~T7_E~0); {51933#false} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 131: Hoare triple {51933#false} assume !(1 == ~T8_E~0); {51933#false} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 132: Hoare triple {51933#false} assume !(1 == ~T9_E~0); {51933#false} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 133: Hoare triple {51933#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {51933#false} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 134: Hoare triple {51933#false} assume !(1 == ~T11_E~0); {51933#false} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 135: Hoare triple {51933#false} assume !(1 == ~T12_E~0); {51933#false} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 136: Hoare triple {51933#false} assume !(1 == ~E_M~0); {51933#false} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 137: Hoare triple {51933#false} assume !(1 == ~E_1~0); {51933#false} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 138: Hoare triple {51933#false} assume !(1 == ~E_2~0); {51933#false} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 139: Hoare triple {51933#false} assume !(1 == ~E_3~0); {51933#false} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 140: Hoare triple {51933#false} assume !(1 == ~E_4~0); {51933#false} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 141: Hoare triple {51933#false} assume 1 == ~E_5~0;~E_5~0 := 2; {51933#false} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 142: Hoare triple {51933#false} assume !(1 == ~E_6~0); {51933#false} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 143: Hoare triple {51933#false} assume !(1 == ~E_7~0); {51933#false} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 144: Hoare triple {51933#false} assume !(1 == ~E_8~0); {51933#false} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 145: Hoare triple {51933#false} assume !(1 == ~E_9~0); {51933#false} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 146: Hoare triple {51933#false} assume !(1 == ~E_10~0); {51933#false} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 147: Hoare triple {51933#false} assume !(1 == ~E_11~0); {51933#false} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 148: Hoare triple {51933#false} assume !(1 == ~E_12~0); {51933#false} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 149: Hoare triple {51933#false} assume { :end_inline_reset_delta_events } true; {51933#false} is VALID [2022-02-21 04:23:23,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:23,087 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:23,087 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [104413898] [2022-02-21 04:23:23,087 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [104413898] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:23,088 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:23,088 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:23,089 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563160959] [2022-02-21 04:23:23,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:23,089 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:23,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:23,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1229697104, now seen corresponding path program 1 times [2022-02-21 04:23:23,090 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:23,092 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921219195] [2022-02-21 04:23:23,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:23,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:23,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:23,127 INFO L290 TraceCheckUtils]: 0: Hoare triple {51935#true} assume !false; {51935#true} is VALID [2022-02-21 04:23:23,128 INFO L290 TraceCheckUtils]: 1: Hoare triple {51935#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {51935#true} is VALID [2022-02-21 04:23:23,128 INFO L290 TraceCheckUtils]: 2: Hoare triple {51935#true} assume !false; {51935#true} is VALID [2022-02-21 04:23:23,128 INFO L290 TraceCheckUtils]: 3: Hoare triple {51935#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {51935#true} is VALID [2022-02-21 04:23:23,128 INFO L290 TraceCheckUtils]: 4: Hoare triple {51935#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {51935#true} is VALID [2022-02-21 04:23:23,128 INFO L290 TraceCheckUtils]: 5: Hoare triple {51935#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {51935#true} is VALID [2022-02-21 04:23:23,128 INFO L290 TraceCheckUtils]: 6: Hoare triple {51935#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {51935#true} is VALID [2022-02-21 04:23:23,128 INFO L290 TraceCheckUtils]: 7: Hoare triple {51935#true} assume !(0 != eval_~tmp~0#1); {51935#true} is VALID [2022-02-21 04:23:23,128 INFO L290 TraceCheckUtils]: 8: Hoare triple {51935#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {51935#true} is VALID [2022-02-21 04:23:23,128 INFO L290 TraceCheckUtils]: 9: Hoare triple {51935#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {51935#true} is VALID [2022-02-21 04:23:23,129 INFO L290 TraceCheckUtils]: 10: Hoare triple {51935#true} assume 0 == ~M_E~0;~M_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,129 INFO L290 TraceCheckUtils]: 11: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,129 INFO L290 TraceCheckUtils]: 12: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,130 INFO L290 TraceCheckUtils]: 13: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,130 INFO L290 TraceCheckUtils]: 14: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,130 INFO L290 TraceCheckUtils]: 15: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,130 INFO L290 TraceCheckUtils]: 16: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,131 INFO L290 TraceCheckUtils]: 17: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,131 INFO L290 TraceCheckUtils]: 18: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,131 INFO L290 TraceCheckUtils]: 19: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,131 INFO L290 TraceCheckUtils]: 20: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,132 INFO L290 TraceCheckUtils]: 21: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,132 INFO L290 TraceCheckUtils]: 22: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,132 INFO L290 TraceCheckUtils]: 23: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,132 INFO L290 TraceCheckUtils]: 24: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,133 INFO L290 TraceCheckUtils]: 25: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,133 INFO L290 TraceCheckUtils]: 26: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,133 INFO L290 TraceCheckUtils]: 27: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,134 INFO L290 TraceCheckUtils]: 28: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,134 INFO L290 TraceCheckUtils]: 29: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,134 INFO L290 TraceCheckUtils]: 30: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,134 INFO L290 TraceCheckUtils]: 31: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,135 INFO L290 TraceCheckUtils]: 32: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,135 INFO L290 TraceCheckUtils]: 33: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,135 INFO L290 TraceCheckUtils]: 34: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,135 INFO L290 TraceCheckUtils]: 35: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,136 INFO L290 TraceCheckUtils]: 36: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,136 INFO L290 TraceCheckUtils]: 37: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,136 INFO L290 TraceCheckUtils]: 38: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,136 INFO L290 TraceCheckUtils]: 39: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,137 INFO L290 TraceCheckUtils]: 40: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,137 INFO L290 TraceCheckUtils]: 41: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,137 INFO L290 TraceCheckUtils]: 42: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,138 INFO L290 TraceCheckUtils]: 43: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,138 INFO L290 TraceCheckUtils]: 44: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,138 INFO L290 TraceCheckUtils]: 45: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,138 INFO L290 TraceCheckUtils]: 46: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,139 INFO L290 TraceCheckUtils]: 47: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,139 INFO L290 TraceCheckUtils]: 48: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,139 INFO L290 TraceCheckUtils]: 49: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,139 INFO L290 TraceCheckUtils]: 50: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,140 INFO L290 TraceCheckUtils]: 51: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,140 INFO L290 TraceCheckUtils]: 52: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,140 INFO L290 TraceCheckUtils]: 53: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,141 INFO L290 TraceCheckUtils]: 54: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,141 INFO L290 TraceCheckUtils]: 55: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,141 INFO L290 TraceCheckUtils]: 56: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,141 INFO L290 TraceCheckUtils]: 57: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,142 INFO L290 TraceCheckUtils]: 58: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,142 INFO L290 TraceCheckUtils]: 59: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,142 INFO L290 TraceCheckUtils]: 60: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,142 INFO L290 TraceCheckUtils]: 61: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,143 INFO L290 TraceCheckUtils]: 62: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,143 INFO L290 TraceCheckUtils]: 63: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,143 INFO L290 TraceCheckUtils]: 64: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,143 INFO L290 TraceCheckUtils]: 65: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,144 INFO L290 TraceCheckUtils]: 66: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,144 INFO L290 TraceCheckUtils]: 67: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,144 INFO L290 TraceCheckUtils]: 68: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,145 INFO L290 TraceCheckUtils]: 69: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,145 INFO L290 TraceCheckUtils]: 70: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,145 INFO L290 TraceCheckUtils]: 71: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,145 INFO L290 TraceCheckUtils]: 72: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,146 INFO L290 TraceCheckUtils]: 73: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,146 INFO L290 TraceCheckUtils]: 74: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,146 INFO L290 TraceCheckUtils]: 75: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,146 INFO L290 TraceCheckUtils]: 76: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,147 INFO L290 TraceCheckUtils]: 77: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,147 INFO L290 TraceCheckUtils]: 78: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,147 INFO L290 TraceCheckUtils]: 79: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,147 INFO L290 TraceCheckUtils]: 80: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,148 INFO L290 TraceCheckUtils]: 81: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,148 INFO L290 TraceCheckUtils]: 82: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,148 INFO L290 TraceCheckUtils]: 83: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,149 INFO L290 TraceCheckUtils]: 84: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,149 INFO L290 TraceCheckUtils]: 85: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,149 INFO L290 TraceCheckUtils]: 86: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,149 INFO L290 TraceCheckUtils]: 87: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,150 INFO L290 TraceCheckUtils]: 88: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,150 INFO L290 TraceCheckUtils]: 89: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,150 INFO L290 TraceCheckUtils]: 90: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,150 INFO L290 TraceCheckUtils]: 91: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,151 INFO L290 TraceCheckUtils]: 92: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,151 INFO L290 TraceCheckUtils]: 93: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,151 INFO L290 TraceCheckUtils]: 94: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,151 INFO L290 TraceCheckUtils]: 95: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,152 INFO L290 TraceCheckUtils]: 96: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,152 INFO L290 TraceCheckUtils]: 97: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,152 INFO L290 TraceCheckUtils]: 98: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,153 INFO L290 TraceCheckUtils]: 99: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,153 INFO L290 TraceCheckUtils]: 100: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,153 INFO L290 TraceCheckUtils]: 101: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,153 INFO L290 TraceCheckUtils]: 102: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,154 INFO L290 TraceCheckUtils]: 103: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,154 INFO L290 TraceCheckUtils]: 104: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,154 INFO L290 TraceCheckUtils]: 105: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,154 INFO L290 TraceCheckUtils]: 106: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,155 INFO L290 TraceCheckUtils]: 107: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,155 INFO L290 TraceCheckUtils]: 108: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,155 INFO L290 TraceCheckUtils]: 109: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,155 INFO L290 TraceCheckUtils]: 110: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,156 INFO L290 TraceCheckUtils]: 111: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,156 INFO L290 TraceCheckUtils]: 112: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,156 INFO L290 TraceCheckUtils]: 113: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,156 INFO L290 TraceCheckUtils]: 114: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {51937#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:23,157 INFO L290 TraceCheckUtils]: 115: Hoare triple {51937#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {51936#false} is VALID [2022-02-21 04:23:23,157 INFO L290 TraceCheckUtils]: 116: Hoare triple {51936#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,157 INFO L290 TraceCheckUtils]: 117: Hoare triple {51936#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,157 INFO L290 TraceCheckUtils]: 118: Hoare triple {51936#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,157 INFO L290 TraceCheckUtils]: 119: Hoare triple {51936#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,157 INFO L290 TraceCheckUtils]: 120: Hoare triple {51936#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,158 INFO L290 TraceCheckUtils]: 121: Hoare triple {51936#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,158 INFO L290 TraceCheckUtils]: 122: Hoare triple {51936#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,158 INFO L290 TraceCheckUtils]: 123: Hoare triple {51936#false} assume !(1 == ~T8_E~0); {51936#false} is VALID [2022-02-21 04:23:23,158 INFO L290 TraceCheckUtils]: 124: Hoare triple {51936#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,158 INFO L290 TraceCheckUtils]: 125: Hoare triple {51936#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,158 INFO L290 TraceCheckUtils]: 126: Hoare triple {51936#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,158 INFO L290 TraceCheckUtils]: 127: Hoare triple {51936#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,158 INFO L290 TraceCheckUtils]: 128: Hoare triple {51936#false} assume 1 == ~E_M~0;~E_M~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,158 INFO L290 TraceCheckUtils]: 129: Hoare triple {51936#false} assume 1 == ~E_1~0;~E_1~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,159 INFO L290 TraceCheckUtils]: 130: Hoare triple {51936#false} assume 1 == ~E_2~0;~E_2~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,159 INFO L290 TraceCheckUtils]: 131: Hoare triple {51936#false} assume !(1 == ~E_3~0); {51936#false} is VALID [2022-02-21 04:23:23,159 INFO L290 TraceCheckUtils]: 132: Hoare triple {51936#false} assume 1 == ~E_4~0;~E_4~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,159 INFO L290 TraceCheckUtils]: 133: Hoare triple {51936#false} assume 1 == ~E_5~0;~E_5~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,159 INFO L290 TraceCheckUtils]: 134: Hoare triple {51936#false} assume 1 == ~E_6~0;~E_6~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,159 INFO L290 TraceCheckUtils]: 135: Hoare triple {51936#false} assume 1 == ~E_7~0;~E_7~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,159 INFO L290 TraceCheckUtils]: 136: Hoare triple {51936#false} assume 1 == ~E_8~0;~E_8~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,159 INFO L290 TraceCheckUtils]: 137: Hoare triple {51936#false} assume 1 == ~E_9~0;~E_9~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,159 INFO L290 TraceCheckUtils]: 138: Hoare triple {51936#false} assume 1 == ~E_10~0;~E_10~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,160 INFO L290 TraceCheckUtils]: 139: Hoare triple {51936#false} assume !(1 == ~E_11~0); {51936#false} is VALID [2022-02-21 04:23:23,160 INFO L290 TraceCheckUtils]: 140: Hoare triple {51936#false} assume 1 == ~E_12~0;~E_12~0 := 2; {51936#false} is VALID [2022-02-21 04:23:23,160 INFO L290 TraceCheckUtils]: 141: Hoare triple {51936#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {51936#false} is VALID [2022-02-21 04:23:23,160 INFO L290 TraceCheckUtils]: 142: Hoare triple {51936#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {51936#false} is VALID [2022-02-21 04:23:23,160 INFO L290 TraceCheckUtils]: 143: Hoare triple {51936#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {51936#false} is VALID [2022-02-21 04:23:23,160 INFO L290 TraceCheckUtils]: 144: Hoare triple {51936#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {51936#false} is VALID [2022-02-21 04:23:23,160 INFO L290 TraceCheckUtils]: 145: Hoare triple {51936#false} assume !(0 == start_simulation_~tmp~3#1); {51936#false} is VALID [2022-02-21 04:23:23,160 INFO L290 TraceCheckUtils]: 146: Hoare triple {51936#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {51936#false} is VALID [2022-02-21 04:23:23,160 INFO L290 TraceCheckUtils]: 147: Hoare triple {51936#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {51936#false} is VALID [2022-02-21 04:23:23,161 INFO L290 TraceCheckUtils]: 148: Hoare triple {51936#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {51936#false} is VALID [2022-02-21 04:23:23,161 INFO L290 TraceCheckUtils]: 149: Hoare triple {51936#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {51936#false} is VALID [2022-02-21 04:23:23,161 INFO L290 TraceCheckUtils]: 150: Hoare triple {51936#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {51936#false} is VALID [2022-02-21 04:23:23,161 INFO L290 TraceCheckUtils]: 151: Hoare triple {51936#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {51936#false} is VALID [2022-02-21 04:23:23,161 INFO L290 TraceCheckUtils]: 152: Hoare triple {51936#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {51936#false} is VALID [2022-02-21 04:23:23,161 INFO L290 TraceCheckUtils]: 153: Hoare triple {51936#false} assume !(0 != start_simulation_~tmp___0~1#1); {51936#false} is VALID [2022-02-21 04:23:23,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:23,162 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:23,163 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921219195] [2022-02-21 04:23:23,164 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921219195] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:23,164 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:23,165 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:23,165 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854317788] [2022-02-21 04:23:23,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:23,165 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:23,165 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:23,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:23,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:23,166 INFO L87 Difference]: Start difference. First operand 1788 states and 2645 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,267 INFO L93 Difference]: Finished difference Result 1788 states and 2644 transitions. [2022-02-21 04:23:24,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:24,267 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,357 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:24,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2644 transitions. [2022-02-21 04:23:24,428 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:24,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2644 transitions. [2022-02-21 04:23:24,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:24,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:24,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2644 transitions. [2022-02-21 04:23:24,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:24,497 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2022-02-21 04:23:24,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2644 transitions. [2022-02-21 04:23:24,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:24,512 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:24,514 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2644 transitions. Second operand has 1788 states, 1788 states have (on average 1.4787472035794182) internal successors, (2644), 1787 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,515 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2644 transitions. Second operand has 1788 states, 1788 states have (on average 1.4787472035794182) internal successors, (2644), 1787 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,516 INFO L87 Difference]: Start difference. First operand 1788 states and 2644 transitions. Second operand has 1788 states, 1788 states have (on average 1.4787472035794182) internal successors, (2644), 1787 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,581 INFO L93 Difference]: Finished difference Result 1788 states and 2644 transitions. [2022-02-21 04:23:24,581 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2644 transitions. [2022-02-21 04:23:24,582 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:24,582 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:24,584 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4787472035794182) internal successors, (2644), 1787 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2644 transitions. [2022-02-21 04:23:24,585 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4787472035794182) internal successors, (2644), 1787 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2644 transitions. [2022-02-21 04:23:24,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,651 INFO L93 Difference]: Finished difference Result 1788 states and 2644 transitions. [2022-02-21 04:23:24,651 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2644 transitions. [2022-02-21 04:23:24,653 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:24,653 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:24,653 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:24,653 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:24,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4787472035794182) internal successors, (2644), 1787 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2644 transitions. [2022-02-21 04:23:24,721 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2022-02-21 04:23:24,721 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2022-02-21 04:23:24,721 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:23:24,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2644 transitions. [2022-02-21 04:23:24,724 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:24,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:24,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:24,725 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:24,725 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:24,726 INFO L791 eck$LassoCheckResult]: Stem: 54515#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 54516#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 54036#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54037#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54091#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 55430#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54524#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54327#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53726#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53727#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54949#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55060#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55496#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 55497#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54455#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 54456#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 54978#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 54897#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54490#L1201 assume !(0 == ~M_E~0); 54491#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55337#L1206-1 assume !(0 == ~T2_E~0); 55323#L1211-1 assume !(0 == ~T3_E~0); 55324#L1216-1 assume !(0 == ~T4_E~0); 54312#L1221-1 assume !(0 == ~T5_E~0); 54313#L1226-1 assume !(0 == ~T6_E~0); 53951#L1231-1 assume !(0 == ~T7_E~0); 53952#L1236-1 assume !(0 == ~T8_E~0); 55360#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54348#L1246-1 assume !(0 == ~T10_E~0); 54349#L1251-1 assume !(0 == ~T11_E~0); 54488#L1256-1 assume !(0 == ~T12_E~0); 53739#L1261-1 assume !(0 == ~E_M~0); 53740#L1266-1 assume !(0 == ~E_1~0); 55482#L1271-1 assume !(0 == ~E_2~0); 55044#L1276-1 assume !(0 == ~E_3~0); 55045#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 54992#L1286-1 assume !(0 == ~E_5~0); 54202#L1291-1 assume !(0 == ~E_6~0); 54203#L1296-1 assume !(0 == ~E_7~0); 54778#L1301-1 assume !(0 == ~E_8~0); 54779#L1306-1 assume !(0 == ~E_9~0); 55259#L1311-1 assume !(0 == ~E_10~0); 54153#L1316-1 assume !(0 == ~E_11~0); 54154#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 54796#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54797#L593 assume 1 == ~m_pc~0; 54941#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 54043#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55469#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55003#L1492 assume !(0 != activate_threads_~tmp~1#1); 55004#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55295#L612 assume !(1 == ~t1_pc~0); 55296#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55425#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54425#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54047#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54048#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54467#L631 assume 1 == ~t2_pc~0; 54402#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53824#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53825#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54661#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 54662#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54120#L650 assume !(1 == ~t3_pc~0); 54121#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54821#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54044#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53777#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 53778#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54970#L669 assume 1 == ~t4_pc~0; 54971#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 55329#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54454#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53986#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 53987#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54211#L688 assume !(1 == ~t5_pc~0); 54002#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54003#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54921#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54855#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 54856#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54988#L707 assume 1 == ~t6_pc~0; 55394#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54631#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54632#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55392#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 54927#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54489#L726 assume 1 == ~t7_pc~0; 54390#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54087#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55128#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55402#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 53856#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53857#L745 assume !(1 == ~t8_pc~0); 54304#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 54323#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55161#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54709#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54710#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55220#L764 assume 1 == ~t9_pc~0; 54487#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54329#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55006#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55453#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 53876#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53877#L783 assume !(1 == ~t10_pc~0); 53938#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53939#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53980#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53981#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 54443#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55331#L802 assume 1 == ~t11_pc~0; 55313#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53821#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53822#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54314#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 54315#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54424#L821 assume !(1 == ~t12_pc~0); 54675#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54771#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53828#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53829#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 55369#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55015#L1339 assume !(1 == ~M_E~0); 55016#L1339-2 assume !(1 == ~T1_E~0); 55404#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55405#L1349-1 assume !(1 == ~T3_E~0); 54790#L1354-1 assume !(1 == ~T4_E~0); 54791#L1359-1 assume !(1 == ~T5_E~0); 55191#L1364-1 assume !(1 == ~T6_E~0); 54254#L1369-1 assume !(1 == ~T7_E~0); 54255#L1374-1 assume !(1 == ~T8_E~0); 54792#L1379-1 assume !(1 == ~T9_E~0); 54793#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54892#L1389-1 assume !(1 == ~T11_E~0); 55363#L1394-1 assume !(1 == ~T12_E~0); 55364#L1399-1 assume !(1 == ~E_M~0); 55454#L1404-1 assume !(1 == ~E_1~0); 54353#L1409-1 assume !(1 == ~E_2~0); 54354#L1414-1 assume !(1 == ~E_3~0); 55080#L1419-1 assume !(1 == ~E_4~0); 53994#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 53995#L1429-1 assume !(1 == ~E_6~0); 54805#L1434-1 assume !(1 == ~E_7~0); 55384#L1439-1 assume !(1 == ~E_8~0); 54032#L1444-1 assume !(1 == ~E_9~0); 54033#L1449-1 assume !(1 == ~E_10~0); 54407#L1454-1 assume !(1 == ~E_11~0); 54408#L1459-1 assume !(1 == ~E_12~0); 54926#L1464-1 assume { :end_inline_reset_delta_events } true; 54166#L1810-2 [2022-02-21 04:23:24,726 INFO L793 eck$LassoCheckResult]: Loop: 54166#L1810-2 assume !false; 54610#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54526#L1176 assume !false; 55088#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54658#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53864#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54414#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 54415#L1003 assume !(0 != eval_~tmp~0#1); 54056#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54057#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55247#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 55030#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55031#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54924#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54115#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54116#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54582#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54186#L1231-3 assume !(0 == ~T7_E~0); 54187#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 54435#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 55415#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 55316#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55021#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 54132#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54133#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54178#L1271-3 assume !(0 == ~E_2~0); 54179#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54555#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54556#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55078#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55079#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 55493#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 55450#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54667#L1311-3 assume !(0 == ~E_10~0); 54058#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54059#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54134#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54770#L593-42 assume !(1 == ~m_pc~0); 54928#L593-44 is_master_triggered_~__retres1~0#1 := 0; 54929#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55478#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55479#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53957#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53958#L612-42 assume 1 == ~t1_pc~0; 54880#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55272#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55393#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54045#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54046#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54741#L631-42 assume 1 == ~t2_pc~0; 53813#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53814#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54730#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54606#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54607#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54207#L650-42 assume 1 == ~t3_pc~0; 53772#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53773#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55421#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54400#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54401#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55385#L669-42 assume !(1 == ~t4_pc~0); 53767#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 53768#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55196#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55086#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 54983#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54984#L688-42 assume 1 == ~t5_pc~0; 55075#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55276#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53910#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53911#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53985#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53799#L707-42 assume !(1 == ~t6_pc~0); 53800#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 55459#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55201#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55202#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54951#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54952#L726-42 assume 1 == ~t7_pc~0; 55229#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55255#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55256#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54670#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54671#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54774#L745-42 assume 1 == ~t8_pc~0; 54810#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54812#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54138#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53785#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53786#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54511#L764-42 assume 1 == ~t9_pc~0; 54645#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55000#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55001#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54071#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54072#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54125#L783-42 assume 1 == ~t10_pc~0; 53741#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53742#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54337#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54470#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55487#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55171#L802-42 assume 1 == ~t11_pc~0; 54270#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53883#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53884#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53834#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 53835#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 55011#L821-42 assume 1 == ~t12_pc~0; 55012#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54377#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53737#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53738#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54717#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54704#L1339-3 assume !(1 == ~M_E~0); 54705#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54859#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54969#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54386#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54387#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54980#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55476#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55383#L1374-3 assume !(1 == ~T8_E~0); 54208#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54209#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54384#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54385#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54594#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55390#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55358#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55359#L1414-3 assume !(1 == ~E_3~0); 55414#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55173#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54092#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54093#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54979#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54020#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54021#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54137#L1454-3 assume !(1 == ~E_11~0); 54974#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54975#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54633#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53930#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54190#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 54191#L1829 assume !(0 == start_simulation_~tmp~3#1); 53912#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53913#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54713#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54714#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 54993#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54994#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54614#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 54165#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 54166#L1810-2 [2022-02-21 04:23:24,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:24,727 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2022-02-21 04:23:24,727 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:24,727 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365400728] [2022-02-21 04:23:24,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:24,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:24,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:24,745 INFO L290 TraceCheckUtils]: 0: Hoare triple {59093#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {59093#true} is VALID [2022-02-21 04:23:24,745 INFO L290 TraceCheckUtils]: 1: Hoare triple {59093#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,746 INFO L290 TraceCheckUtils]: 2: Hoare triple {59095#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,746 INFO L290 TraceCheckUtils]: 3: Hoare triple {59095#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,746 INFO L290 TraceCheckUtils]: 4: Hoare triple {59095#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,746 INFO L290 TraceCheckUtils]: 5: Hoare triple {59095#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,747 INFO L290 TraceCheckUtils]: 6: Hoare triple {59095#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,747 INFO L290 TraceCheckUtils]: 7: Hoare triple {59095#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,747 INFO L290 TraceCheckUtils]: 8: Hoare triple {59095#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,747 INFO L290 TraceCheckUtils]: 9: Hoare triple {59095#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,748 INFO L290 TraceCheckUtils]: 10: Hoare triple {59095#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,748 INFO L290 TraceCheckUtils]: 11: Hoare triple {59095#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {59095#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:24,748 INFO L290 TraceCheckUtils]: 12: Hoare triple {59095#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {59094#false} is VALID [2022-02-21 04:23:24,748 INFO L290 TraceCheckUtils]: 13: Hoare triple {59094#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {59094#false} is VALID [2022-02-21 04:23:24,748 INFO L290 TraceCheckUtils]: 14: Hoare triple {59094#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {59094#false} is VALID [2022-02-21 04:23:24,748 INFO L290 TraceCheckUtils]: 15: Hoare triple {59094#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {59094#false} is VALID [2022-02-21 04:23:24,748 INFO L290 TraceCheckUtils]: 16: Hoare triple {59094#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {59094#false} is VALID [2022-02-21 04:23:24,749 INFO L290 TraceCheckUtils]: 17: Hoare triple {59094#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {59094#false} is VALID [2022-02-21 04:23:24,749 INFO L290 TraceCheckUtils]: 18: Hoare triple {59094#false} assume !(0 == ~M_E~0); {59094#false} is VALID [2022-02-21 04:23:24,749 INFO L290 TraceCheckUtils]: 19: Hoare triple {59094#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {59094#false} is VALID [2022-02-21 04:23:24,749 INFO L290 TraceCheckUtils]: 20: Hoare triple {59094#false} assume !(0 == ~T2_E~0); {59094#false} is VALID [2022-02-21 04:23:24,749 INFO L290 TraceCheckUtils]: 21: Hoare triple {59094#false} assume !(0 == ~T3_E~0); {59094#false} is VALID [2022-02-21 04:23:24,749 INFO L290 TraceCheckUtils]: 22: Hoare triple {59094#false} assume !(0 == ~T4_E~0); {59094#false} is VALID [2022-02-21 04:23:24,749 INFO L290 TraceCheckUtils]: 23: Hoare triple {59094#false} assume !(0 == ~T5_E~0); {59094#false} is VALID [2022-02-21 04:23:24,749 INFO L290 TraceCheckUtils]: 24: Hoare triple {59094#false} assume !(0 == ~T6_E~0); {59094#false} is VALID [2022-02-21 04:23:24,749 INFO L290 TraceCheckUtils]: 25: Hoare triple {59094#false} assume !(0 == ~T7_E~0); {59094#false} is VALID [2022-02-21 04:23:24,750 INFO L290 TraceCheckUtils]: 26: Hoare triple {59094#false} assume !(0 == ~T8_E~0); {59094#false} is VALID [2022-02-21 04:23:24,750 INFO L290 TraceCheckUtils]: 27: Hoare triple {59094#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {59094#false} is VALID [2022-02-21 04:23:24,750 INFO L290 TraceCheckUtils]: 28: Hoare triple {59094#false} assume !(0 == ~T10_E~0); {59094#false} is VALID [2022-02-21 04:23:24,750 INFO L290 TraceCheckUtils]: 29: Hoare triple {59094#false} assume !(0 == ~T11_E~0); {59094#false} is VALID [2022-02-21 04:23:24,750 INFO L290 TraceCheckUtils]: 30: Hoare triple {59094#false} assume !(0 == ~T12_E~0); {59094#false} is VALID [2022-02-21 04:23:24,750 INFO L290 TraceCheckUtils]: 31: Hoare triple {59094#false} assume !(0 == ~E_M~0); {59094#false} is VALID [2022-02-21 04:23:24,750 INFO L290 TraceCheckUtils]: 32: Hoare triple {59094#false} assume !(0 == ~E_1~0); {59094#false} is VALID [2022-02-21 04:23:24,750 INFO L290 TraceCheckUtils]: 33: Hoare triple {59094#false} assume !(0 == ~E_2~0); {59094#false} is VALID [2022-02-21 04:23:24,750 INFO L290 TraceCheckUtils]: 34: Hoare triple {59094#false} assume !(0 == ~E_3~0); {59094#false} is VALID [2022-02-21 04:23:24,751 INFO L290 TraceCheckUtils]: 35: Hoare triple {59094#false} assume 0 == ~E_4~0;~E_4~0 := 1; {59094#false} is VALID [2022-02-21 04:23:24,751 INFO L290 TraceCheckUtils]: 36: Hoare triple {59094#false} assume !(0 == ~E_5~0); {59094#false} is VALID [2022-02-21 04:23:24,751 INFO L290 TraceCheckUtils]: 37: Hoare triple {59094#false} assume !(0 == ~E_6~0); {59094#false} is VALID [2022-02-21 04:23:24,751 INFO L290 TraceCheckUtils]: 38: Hoare triple {59094#false} assume !(0 == ~E_7~0); {59094#false} is VALID [2022-02-21 04:23:24,751 INFO L290 TraceCheckUtils]: 39: Hoare triple {59094#false} assume !(0 == ~E_8~0); {59094#false} is VALID [2022-02-21 04:23:24,751 INFO L290 TraceCheckUtils]: 40: Hoare triple {59094#false} assume !(0 == ~E_9~0); {59094#false} is VALID [2022-02-21 04:23:24,751 INFO L290 TraceCheckUtils]: 41: Hoare triple {59094#false} assume !(0 == ~E_10~0); {59094#false} is VALID [2022-02-21 04:23:24,751 INFO L290 TraceCheckUtils]: 42: Hoare triple {59094#false} assume !(0 == ~E_11~0); {59094#false} is VALID [2022-02-21 04:23:24,751 INFO L290 TraceCheckUtils]: 43: Hoare triple {59094#false} assume 0 == ~E_12~0;~E_12~0 := 1; {59094#false} is VALID [2022-02-21 04:23:24,752 INFO L290 TraceCheckUtils]: 44: Hoare triple {59094#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {59094#false} is VALID [2022-02-21 04:23:24,752 INFO L290 TraceCheckUtils]: 45: Hoare triple {59094#false} assume 1 == ~m_pc~0; {59094#false} is VALID [2022-02-21 04:23:24,752 INFO L290 TraceCheckUtils]: 46: Hoare triple {59094#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {59094#false} is VALID [2022-02-21 04:23:24,752 INFO L290 TraceCheckUtils]: 47: Hoare triple {59094#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {59094#false} is VALID [2022-02-21 04:23:24,752 INFO L290 TraceCheckUtils]: 48: Hoare triple {59094#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {59094#false} is VALID [2022-02-21 04:23:24,752 INFO L290 TraceCheckUtils]: 49: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp~1#1); {59094#false} is VALID [2022-02-21 04:23:24,752 INFO L290 TraceCheckUtils]: 50: Hoare triple {59094#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {59094#false} is VALID [2022-02-21 04:23:24,752 INFO L290 TraceCheckUtils]: 51: Hoare triple {59094#false} assume !(1 == ~t1_pc~0); {59094#false} is VALID [2022-02-21 04:23:24,753 INFO L290 TraceCheckUtils]: 52: Hoare triple {59094#false} is_transmit1_triggered_~__retres1~1#1 := 0; {59094#false} is VALID [2022-02-21 04:23:24,753 INFO L290 TraceCheckUtils]: 53: Hoare triple {59094#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {59094#false} is VALID [2022-02-21 04:23:24,753 INFO L290 TraceCheckUtils]: 54: Hoare triple {59094#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {59094#false} is VALID [2022-02-21 04:23:24,753 INFO L290 TraceCheckUtils]: 55: Hoare triple {59094#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {59094#false} is VALID [2022-02-21 04:23:24,753 INFO L290 TraceCheckUtils]: 56: Hoare triple {59094#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {59094#false} is VALID [2022-02-21 04:23:24,753 INFO L290 TraceCheckUtils]: 57: Hoare triple {59094#false} assume 1 == ~t2_pc~0; {59094#false} is VALID [2022-02-21 04:23:24,753 INFO L290 TraceCheckUtils]: 58: Hoare triple {59094#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {59094#false} is VALID [2022-02-21 04:23:24,753 INFO L290 TraceCheckUtils]: 59: Hoare triple {59094#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {59094#false} is VALID [2022-02-21 04:23:24,753 INFO L290 TraceCheckUtils]: 60: Hoare triple {59094#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {59094#false} is VALID [2022-02-21 04:23:24,754 INFO L290 TraceCheckUtils]: 61: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp___1~0#1); {59094#false} is VALID [2022-02-21 04:23:24,754 INFO L290 TraceCheckUtils]: 62: Hoare triple {59094#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {59094#false} is VALID [2022-02-21 04:23:24,754 INFO L290 TraceCheckUtils]: 63: Hoare triple {59094#false} assume !(1 == ~t3_pc~0); {59094#false} is VALID [2022-02-21 04:23:24,754 INFO L290 TraceCheckUtils]: 64: Hoare triple {59094#false} is_transmit3_triggered_~__retres1~3#1 := 0; {59094#false} is VALID [2022-02-21 04:23:24,754 INFO L290 TraceCheckUtils]: 65: Hoare triple {59094#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {59094#false} is VALID [2022-02-21 04:23:24,754 INFO L290 TraceCheckUtils]: 66: Hoare triple {59094#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {59094#false} is VALID [2022-02-21 04:23:24,754 INFO L290 TraceCheckUtils]: 67: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp___2~0#1); {59094#false} is VALID [2022-02-21 04:23:24,754 INFO L290 TraceCheckUtils]: 68: Hoare triple {59094#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {59094#false} is VALID [2022-02-21 04:23:24,754 INFO L290 TraceCheckUtils]: 69: Hoare triple {59094#false} assume 1 == ~t4_pc~0; {59094#false} is VALID [2022-02-21 04:23:24,755 INFO L290 TraceCheckUtils]: 70: Hoare triple {59094#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {59094#false} is VALID [2022-02-21 04:23:24,755 INFO L290 TraceCheckUtils]: 71: Hoare triple {59094#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {59094#false} is VALID [2022-02-21 04:23:24,755 INFO L290 TraceCheckUtils]: 72: Hoare triple {59094#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {59094#false} is VALID [2022-02-21 04:23:24,755 INFO L290 TraceCheckUtils]: 73: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp___3~0#1); {59094#false} is VALID [2022-02-21 04:23:24,755 INFO L290 TraceCheckUtils]: 74: Hoare triple {59094#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {59094#false} is VALID [2022-02-21 04:23:24,755 INFO L290 TraceCheckUtils]: 75: Hoare triple {59094#false} assume !(1 == ~t5_pc~0); {59094#false} is VALID [2022-02-21 04:23:24,755 INFO L290 TraceCheckUtils]: 76: Hoare triple {59094#false} is_transmit5_triggered_~__retres1~5#1 := 0; {59094#false} is VALID [2022-02-21 04:23:24,755 INFO L290 TraceCheckUtils]: 77: Hoare triple {59094#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {59094#false} is VALID [2022-02-21 04:23:24,755 INFO L290 TraceCheckUtils]: 78: Hoare triple {59094#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {59094#false} is VALID [2022-02-21 04:23:24,756 INFO L290 TraceCheckUtils]: 79: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp___4~0#1); {59094#false} is VALID [2022-02-21 04:23:24,756 INFO L290 TraceCheckUtils]: 80: Hoare triple {59094#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {59094#false} is VALID [2022-02-21 04:23:24,756 INFO L290 TraceCheckUtils]: 81: Hoare triple {59094#false} assume 1 == ~t6_pc~0; {59094#false} is VALID [2022-02-21 04:23:24,756 INFO L290 TraceCheckUtils]: 82: Hoare triple {59094#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {59094#false} is VALID [2022-02-21 04:23:24,756 INFO L290 TraceCheckUtils]: 83: Hoare triple {59094#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {59094#false} is VALID [2022-02-21 04:23:24,756 INFO L290 TraceCheckUtils]: 84: Hoare triple {59094#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {59094#false} is VALID [2022-02-21 04:23:24,756 INFO L290 TraceCheckUtils]: 85: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp___5~0#1); {59094#false} is VALID [2022-02-21 04:23:24,756 INFO L290 TraceCheckUtils]: 86: Hoare triple {59094#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {59094#false} is VALID [2022-02-21 04:23:24,756 INFO L290 TraceCheckUtils]: 87: Hoare triple {59094#false} assume 1 == ~t7_pc~0; {59094#false} is VALID [2022-02-21 04:23:24,757 INFO L290 TraceCheckUtils]: 88: Hoare triple {59094#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {59094#false} is VALID [2022-02-21 04:23:24,757 INFO L290 TraceCheckUtils]: 89: Hoare triple {59094#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {59094#false} is VALID [2022-02-21 04:23:24,757 INFO L290 TraceCheckUtils]: 90: Hoare triple {59094#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {59094#false} is VALID [2022-02-21 04:23:24,757 INFO L290 TraceCheckUtils]: 91: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp___6~0#1); {59094#false} is VALID [2022-02-21 04:23:24,757 INFO L290 TraceCheckUtils]: 92: Hoare triple {59094#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {59094#false} is VALID [2022-02-21 04:23:24,757 INFO L290 TraceCheckUtils]: 93: Hoare triple {59094#false} assume !(1 == ~t8_pc~0); {59094#false} is VALID [2022-02-21 04:23:24,757 INFO L290 TraceCheckUtils]: 94: Hoare triple {59094#false} is_transmit8_triggered_~__retres1~8#1 := 0; {59094#false} is VALID [2022-02-21 04:23:24,757 INFO L290 TraceCheckUtils]: 95: Hoare triple {59094#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {59094#false} is VALID [2022-02-21 04:23:24,757 INFO L290 TraceCheckUtils]: 96: Hoare triple {59094#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {59094#false} is VALID [2022-02-21 04:23:24,758 INFO L290 TraceCheckUtils]: 97: Hoare triple {59094#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {59094#false} is VALID [2022-02-21 04:23:24,758 INFO L290 TraceCheckUtils]: 98: Hoare triple {59094#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {59094#false} is VALID [2022-02-21 04:23:24,758 INFO L290 TraceCheckUtils]: 99: Hoare triple {59094#false} assume 1 == ~t9_pc~0; {59094#false} is VALID [2022-02-21 04:23:24,758 INFO L290 TraceCheckUtils]: 100: Hoare triple {59094#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {59094#false} is VALID [2022-02-21 04:23:24,758 INFO L290 TraceCheckUtils]: 101: Hoare triple {59094#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {59094#false} is VALID [2022-02-21 04:23:24,758 INFO L290 TraceCheckUtils]: 102: Hoare triple {59094#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {59094#false} is VALID [2022-02-21 04:23:24,758 INFO L290 TraceCheckUtils]: 103: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp___8~0#1); {59094#false} is VALID [2022-02-21 04:23:24,758 INFO L290 TraceCheckUtils]: 104: Hoare triple {59094#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {59094#false} is VALID [2022-02-21 04:23:24,758 INFO L290 TraceCheckUtils]: 105: Hoare triple {59094#false} assume !(1 == ~t10_pc~0); {59094#false} is VALID [2022-02-21 04:23:24,759 INFO L290 TraceCheckUtils]: 106: Hoare triple {59094#false} is_transmit10_triggered_~__retres1~10#1 := 0; {59094#false} is VALID [2022-02-21 04:23:24,759 INFO L290 TraceCheckUtils]: 107: Hoare triple {59094#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {59094#false} is VALID [2022-02-21 04:23:24,759 INFO L290 TraceCheckUtils]: 108: Hoare triple {59094#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {59094#false} is VALID [2022-02-21 04:23:24,759 INFO L290 TraceCheckUtils]: 109: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp___9~0#1); {59094#false} is VALID [2022-02-21 04:23:24,759 INFO L290 TraceCheckUtils]: 110: Hoare triple {59094#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {59094#false} is VALID [2022-02-21 04:23:24,759 INFO L290 TraceCheckUtils]: 111: Hoare triple {59094#false} assume 1 == ~t11_pc~0; {59094#false} is VALID [2022-02-21 04:23:24,759 INFO L290 TraceCheckUtils]: 112: Hoare triple {59094#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {59094#false} is VALID [2022-02-21 04:23:24,759 INFO L290 TraceCheckUtils]: 113: Hoare triple {59094#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {59094#false} is VALID [2022-02-21 04:23:24,760 INFO L290 TraceCheckUtils]: 114: Hoare triple {59094#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {59094#false} is VALID [2022-02-21 04:23:24,760 INFO L290 TraceCheckUtils]: 115: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp___10~0#1); {59094#false} is VALID [2022-02-21 04:23:24,760 INFO L290 TraceCheckUtils]: 116: Hoare triple {59094#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {59094#false} is VALID [2022-02-21 04:23:24,760 INFO L290 TraceCheckUtils]: 117: Hoare triple {59094#false} assume !(1 == ~t12_pc~0); {59094#false} is VALID [2022-02-21 04:23:24,760 INFO L290 TraceCheckUtils]: 118: Hoare triple {59094#false} is_transmit12_triggered_~__retres1~12#1 := 0; {59094#false} is VALID [2022-02-21 04:23:24,760 INFO L290 TraceCheckUtils]: 119: Hoare triple {59094#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {59094#false} is VALID [2022-02-21 04:23:24,760 INFO L290 TraceCheckUtils]: 120: Hoare triple {59094#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {59094#false} is VALID [2022-02-21 04:23:24,760 INFO L290 TraceCheckUtils]: 121: Hoare triple {59094#false} assume !(0 != activate_threads_~tmp___11~0#1); {59094#false} is VALID [2022-02-21 04:23:24,760 INFO L290 TraceCheckUtils]: 122: Hoare triple {59094#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {59094#false} is VALID [2022-02-21 04:23:24,761 INFO L290 TraceCheckUtils]: 123: Hoare triple {59094#false} assume !(1 == ~M_E~0); {59094#false} is VALID [2022-02-21 04:23:24,761 INFO L290 TraceCheckUtils]: 124: Hoare triple {59094#false} assume !(1 == ~T1_E~0); {59094#false} is VALID [2022-02-21 04:23:24,761 INFO L290 TraceCheckUtils]: 125: Hoare triple {59094#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {59094#false} is VALID [2022-02-21 04:23:24,761 INFO L290 TraceCheckUtils]: 126: Hoare triple {59094#false} assume !(1 == ~T3_E~0); {59094#false} is VALID [2022-02-21 04:23:24,761 INFO L290 TraceCheckUtils]: 127: Hoare triple {59094#false} assume !(1 == ~T4_E~0); {59094#false} is VALID [2022-02-21 04:23:24,761 INFO L290 TraceCheckUtils]: 128: Hoare triple {59094#false} assume !(1 == ~T5_E~0); {59094#false} is VALID [2022-02-21 04:23:24,761 INFO L290 TraceCheckUtils]: 129: Hoare triple {59094#false} assume !(1 == ~T6_E~0); {59094#false} is VALID [2022-02-21 04:23:24,761 INFO L290 TraceCheckUtils]: 130: Hoare triple {59094#false} assume !(1 == ~T7_E~0); {59094#false} is VALID [2022-02-21 04:23:24,761 INFO L290 TraceCheckUtils]: 131: Hoare triple {59094#false} assume !(1 == ~T8_E~0); {59094#false} is VALID [2022-02-21 04:23:24,762 INFO L290 TraceCheckUtils]: 132: Hoare triple {59094#false} assume !(1 == ~T9_E~0); {59094#false} is VALID [2022-02-21 04:23:24,762 INFO L290 TraceCheckUtils]: 133: Hoare triple {59094#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {59094#false} is VALID [2022-02-21 04:23:24,762 INFO L290 TraceCheckUtils]: 134: Hoare triple {59094#false} assume !(1 == ~T11_E~0); {59094#false} is VALID [2022-02-21 04:23:24,762 INFO L290 TraceCheckUtils]: 135: Hoare triple {59094#false} assume !(1 == ~T12_E~0); {59094#false} is VALID [2022-02-21 04:23:24,762 INFO L290 TraceCheckUtils]: 136: Hoare triple {59094#false} assume !(1 == ~E_M~0); {59094#false} is VALID [2022-02-21 04:23:24,762 INFO L290 TraceCheckUtils]: 137: Hoare triple {59094#false} assume !(1 == ~E_1~0); {59094#false} is VALID [2022-02-21 04:23:24,762 INFO L290 TraceCheckUtils]: 138: Hoare triple {59094#false} assume !(1 == ~E_2~0); {59094#false} is VALID [2022-02-21 04:23:24,762 INFO L290 TraceCheckUtils]: 139: Hoare triple {59094#false} assume !(1 == ~E_3~0); {59094#false} is VALID [2022-02-21 04:23:24,762 INFO L290 TraceCheckUtils]: 140: Hoare triple {59094#false} assume !(1 == ~E_4~0); {59094#false} is VALID [2022-02-21 04:23:24,763 INFO L290 TraceCheckUtils]: 141: Hoare triple {59094#false} assume 1 == ~E_5~0;~E_5~0 := 2; {59094#false} is VALID [2022-02-21 04:23:24,763 INFO L290 TraceCheckUtils]: 142: Hoare triple {59094#false} assume !(1 == ~E_6~0); {59094#false} is VALID [2022-02-21 04:23:24,763 INFO L290 TraceCheckUtils]: 143: Hoare triple {59094#false} assume !(1 == ~E_7~0); {59094#false} is VALID [2022-02-21 04:23:24,763 INFO L290 TraceCheckUtils]: 144: Hoare triple {59094#false} assume !(1 == ~E_8~0); {59094#false} is VALID [2022-02-21 04:23:24,763 INFO L290 TraceCheckUtils]: 145: Hoare triple {59094#false} assume !(1 == ~E_9~0); {59094#false} is VALID [2022-02-21 04:23:24,763 INFO L290 TraceCheckUtils]: 146: Hoare triple {59094#false} assume !(1 == ~E_10~0); {59094#false} is VALID [2022-02-21 04:23:24,763 INFO L290 TraceCheckUtils]: 147: Hoare triple {59094#false} assume !(1 == ~E_11~0); {59094#false} is VALID [2022-02-21 04:23:24,763 INFO L290 TraceCheckUtils]: 148: Hoare triple {59094#false} assume !(1 == ~E_12~0); {59094#false} is VALID [2022-02-21 04:23:24,763 INFO L290 TraceCheckUtils]: 149: Hoare triple {59094#false} assume { :end_inline_reset_delta_events } true; {59094#false} is VALID [2022-02-21 04:23:24,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:24,764 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:24,764 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365400728] [2022-02-21 04:23:24,764 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [365400728] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:24,764 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:24,764 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:24,765 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [51760884] [2022-02-21 04:23:24,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:24,765 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:24,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:24,765 INFO L85 PathProgramCache]: Analyzing trace with hash -1795658606, now seen corresponding path program 1 times [2022-02-21 04:23:24,765 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:24,766 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975652582] [2022-02-21 04:23:24,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:24,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:24,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:24,788 INFO L290 TraceCheckUtils]: 0: Hoare triple {59096#true} assume !false; {59096#true} is VALID [2022-02-21 04:23:24,789 INFO L290 TraceCheckUtils]: 1: Hoare triple {59096#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {59096#true} is VALID [2022-02-21 04:23:24,789 INFO L290 TraceCheckUtils]: 2: Hoare triple {59096#true} assume !false; {59096#true} is VALID [2022-02-21 04:23:24,789 INFO L290 TraceCheckUtils]: 3: Hoare triple {59096#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {59096#true} is VALID [2022-02-21 04:23:24,789 INFO L290 TraceCheckUtils]: 4: Hoare triple {59096#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {59096#true} is VALID [2022-02-21 04:23:24,789 INFO L290 TraceCheckUtils]: 5: Hoare triple {59096#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {59096#true} is VALID [2022-02-21 04:23:24,789 INFO L290 TraceCheckUtils]: 6: Hoare triple {59096#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {59096#true} is VALID [2022-02-21 04:23:24,789 INFO L290 TraceCheckUtils]: 7: Hoare triple {59096#true} assume !(0 != eval_~tmp~0#1); {59096#true} is VALID [2022-02-21 04:23:24,789 INFO L290 TraceCheckUtils]: 8: Hoare triple {59096#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {59096#true} is VALID [2022-02-21 04:23:24,790 INFO L290 TraceCheckUtils]: 9: Hoare triple {59096#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {59096#true} is VALID [2022-02-21 04:23:24,790 INFO L290 TraceCheckUtils]: 10: Hoare triple {59096#true} assume 0 == ~M_E~0;~M_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,790 INFO L290 TraceCheckUtils]: 11: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,790 INFO L290 TraceCheckUtils]: 12: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,791 INFO L290 TraceCheckUtils]: 13: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,791 INFO L290 TraceCheckUtils]: 14: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,791 INFO L290 TraceCheckUtils]: 15: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,791 INFO L290 TraceCheckUtils]: 16: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,792 INFO L290 TraceCheckUtils]: 17: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,792 INFO L290 TraceCheckUtils]: 18: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,792 INFO L290 TraceCheckUtils]: 19: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,792 INFO L290 TraceCheckUtils]: 20: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,793 INFO L290 TraceCheckUtils]: 21: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,793 INFO L290 TraceCheckUtils]: 22: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,793 INFO L290 TraceCheckUtils]: 23: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,793 INFO L290 TraceCheckUtils]: 24: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,793 INFO L290 TraceCheckUtils]: 25: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,794 INFO L290 TraceCheckUtils]: 26: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,794 INFO L290 TraceCheckUtils]: 27: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,794 INFO L290 TraceCheckUtils]: 28: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,794 INFO L290 TraceCheckUtils]: 29: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,795 INFO L290 TraceCheckUtils]: 30: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,795 INFO L290 TraceCheckUtils]: 31: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,795 INFO L290 TraceCheckUtils]: 32: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,795 INFO L290 TraceCheckUtils]: 33: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,796 INFO L290 TraceCheckUtils]: 34: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,796 INFO L290 TraceCheckUtils]: 35: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,796 INFO L290 TraceCheckUtils]: 36: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,796 INFO L290 TraceCheckUtils]: 37: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,797 INFO L290 TraceCheckUtils]: 38: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,797 INFO L290 TraceCheckUtils]: 39: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,797 INFO L290 TraceCheckUtils]: 40: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,797 INFO L290 TraceCheckUtils]: 41: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,798 INFO L290 TraceCheckUtils]: 42: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,798 INFO L290 TraceCheckUtils]: 43: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,798 INFO L290 TraceCheckUtils]: 44: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,798 INFO L290 TraceCheckUtils]: 45: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,798 INFO L290 TraceCheckUtils]: 46: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,799 INFO L290 TraceCheckUtils]: 47: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,799 INFO L290 TraceCheckUtils]: 48: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,799 INFO L290 TraceCheckUtils]: 49: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,799 INFO L290 TraceCheckUtils]: 50: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,800 INFO L290 TraceCheckUtils]: 51: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,800 INFO L290 TraceCheckUtils]: 52: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,800 INFO L290 TraceCheckUtils]: 53: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,800 INFO L290 TraceCheckUtils]: 54: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,801 INFO L290 TraceCheckUtils]: 55: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,801 INFO L290 TraceCheckUtils]: 56: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,801 INFO L290 TraceCheckUtils]: 57: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,801 INFO L290 TraceCheckUtils]: 58: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,802 INFO L290 TraceCheckUtils]: 59: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,802 INFO L290 TraceCheckUtils]: 60: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,802 INFO L290 TraceCheckUtils]: 61: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,802 INFO L290 TraceCheckUtils]: 62: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,803 INFO L290 TraceCheckUtils]: 63: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,803 INFO L290 TraceCheckUtils]: 64: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,803 INFO L290 TraceCheckUtils]: 65: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,803 INFO L290 TraceCheckUtils]: 66: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,804 INFO L290 TraceCheckUtils]: 67: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,804 INFO L290 TraceCheckUtils]: 68: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,804 INFO L290 TraceCheckUtils]: 69: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,804 INFO L290 TraceCheckUtils]: 70: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,805 INFO L290 TraceCheckUtils]: 71: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,805 INFO L290 TraceCheckUtils]: 72: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,805 INFO L290 TraceCheckUtils]: 73: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,805 INFO L290 TraceCheckUtils]: 74: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,806 INFO L290 TraceCheckUtils]: 75: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,806 INFO L290 TraceCheckUtils]: 76: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,806 INFO L290 TraceCheckUtils]: 77: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,806 INFO L290 TraceCheckUtils]: 78: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,807 INFO L290 TraceCheckUtils]: 79: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,807 INFO L290 TraceCheckUtils]: 80: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,807 INFO L290 TraceCheckUtils]: 81: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,807 INFO L290 TraceCheckUtils]: 82: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,807 INFO L290 TraceCheckUtils]: 83: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,808 INFO L290 TraceCheckUtils]: 84: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,808 INFO L290 TraceCheckUtils]: 85: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,808 INFO L290 TraceCheckUtils]: 86: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,808 INFO L290 TraceCheckUtils]: 87: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,809 INFO L290 TraceCheckUtils]: 88: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,809 INFO L290 TraceCheckUtils]: 89: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,809 INFO L290 TraceCheckUtils]: 90: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,809 INFO L290 TraceCheckUtils]: 91: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,810 INFO L290 TraceCheckUtils]: 92: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,810 INFO L290 TraceCheckUtils]: 93: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,810 INFO L290 TraceCheckUtils]: 94: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,810 INFO L290 TraceCheckUtils]: 95: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,811 INFO L290 TraceCheckUtils]: 96: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,811 INFO L290 TraceCheckUtils]: 97: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,811 INFO L290 TraceCheckUtils]: 98: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,811 INFO L290 TraceCheckUtils]: 99: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,812 INFO L290 TraceCheckUtils]: 100: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,812 INFO L290 TraceCheckUtils]: 101: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,812 INFO L290 TraceCheckUtils]: 102: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,812 INFO L290 TraceCheckUtils]: 103: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,813 INFO L290 TraceCheckUtils]: 104: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,813 INFO L290 TraceCheckUtils]: 105: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,813 INFO L290 TraceCheckUtils]: 106: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,813 INFO L290 TraceCheckUtils]: 107: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,814 INFO L290 TraceCheckUtils]: 108: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,814 INFO L290 TraceCheckUtils]: 109: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,814 INFO L290 TraceCheckUtils]: 110: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,814 INFO L290 TraceCheckUtils]: 111: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,815 INFO L290 TraceCheckUtils]: 112: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,815 INFO L290 TraceCheckUtils]: 113: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,815 INFO L290 TraceCheckUtils]: 114: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {59098#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:24,815 INFO L290 TraceCheckUtils]: 115: Hoare triple {59098#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {59097#false} is VALID [2022-02-21 04:23:24,815 INFO L290 TraceCheckUtils]: 116: Hoare triple {59097#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,816 INFO L290 TraceCheckUtils]: 117: Hoare triple {59097#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,816 INFO L290 TraceCheckUtils]: 118: Hoare triple {59097#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,816 INFO L290 TraceCheckUtils]: 119: Hoare triple {59097#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,816 INFO L290 TraceCheckUtils]: 120: Hoare triple {59097#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,816 INFO L290 TraceCheckUtils]: 121: Hoare triple {59097#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,816 INFO L290 TraceCheckUtils]: 122: Hoare triple {59097#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,816 INFO L290 TraceCheckUtils]: 123: Hoare triple {59097#false} assume !(1 == ~T8_E~0); {59097#false} is VALID [2022-02-21 04:23:24,816 INFO L290 TraceCheckUtils]: 124: Hoare triple {59097#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,817 INFO L290 TraceCheckUtils]: 125: Hoare triple {59097#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,817 INFO L290 TraceCheckUtils]: 126: Hoare triple {59097#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,817 INFO L290 TraceCheckUtils]: 127: Hoare triple {59097#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,817 INFO L290 TraceCheckUtils]: 128: Hoare triple {59097#false} assume 1 == ~E_M~0;~E_M~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,817 INFO L290 TraceCheckUtils]: 129: Hoare triple {59097#false} assume 1 == ~E_1~0;~E_1~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,817 INFO L290 TraceCheckUtils]: 130: Hoare triple {59097#false} assume 1 == ~E_2~0;~E_2~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,817 INFO L290 TraceCheckUtils]: 131: Hoare triple {59097#false} assume !(1 == ~E_3~0); {59097#false} is VALID [2022-02-21 04:23:24,817 INFO L290 TraceCheckUtils]: 132: Hoare triple {59097#false} assume 1 == ~E_4~0;~E_4~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,817 INFO L290 TraceCheckUtils]: 133: Hoare triple {59097#false} assume 1 == ~E_5~0;~E_5~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,818 INFO L290 TraceCheckUtils]: 134: Hoare triple {59097#false} assume 1 == ~E_6~0;~E_6~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,818 INFO L290 TraceCheckUtils]: 135: Hoare triple {59097#false} assume 1 == ~E_7~0;~E_7~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,818 INFO L290 TraceCheckUtils]: 136: Hoare triple {59097#false} assume 1 == ~E_8~0;~E_8~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,818 INFO L290 TraceCheckUtils]: 137: Hoare triple {59097#false} assume 1 == ~E_9~0;~E_9~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,818 INFO L290 TraceCheckUtils]: 138: Hoare triple {59097#false} assume 1 == ~E_10~0;~E_10~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,818 INFO L290 TraceCheckUtils]: 139: Hoare triple {59097#false} assume !(1 == ~E_11~0); {59097#false} is VALID [2022-02-21 04:23:24,818 INFO L290 TraceCheckUtils]: 140: Hoare triple {59097#false} assume 1 == ~E_12~0;~E_12~0 := 2; {59097#false} is VALID [2022-02-21 04:23:24,818 INFO L290 TraceCheckUtils]: 141: Hoare triple {59097#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {59097#false} is VALID [2022-02-21 04:23:24,818 INFO L290 TraceCheckUtils]: 142: Hoare triple {59097#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {59097#false} is VALID [2022-02-21 04:23:24,819 INFO L290 TraceCheckUtils]: 143: Hoare triple {59097#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {59097#false} is VALID [2022-02-21 04:23:24,819 INFO L290 TraceCheckUtils]: 144: Hoare triple {59097#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {59097#false} is VALID [2022-02-21 04:23:24,819 INFO L290 TraceCheckUtils]: 145: Hoare triple {59097#false} assume !(0 == start_simulation_~tmp~3#1); {59097#false} is VALID [2022-02-21 04:23:24,819 INFO L290 TraceCheckUtils]: 146: Hoare triple {59097#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {59097#false} is VALID [2022-02-21 04:23:24,819 INFO L290 TraceCheckUtils]: 147: Hoare triple {59097#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {59097#false} is VALID [2022-02-21 04:23:24,819 INFO L290 TraceCheckUtils]: 148: Hoare triple {59097#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {59097#false} is VALID [2022-02-21 04:23:24,819 INFO L290 TraceCheckUtils]: 149: Hoare triple {59097#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {59097#false} is VALID [2022-02-21 04:23:24,819 INFO L290 TraceCheckUtils]: 150: Hoare triple {59097#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {59097#false} is VALID [2022-02-21 04:23:24,819 INFO L290 TraceCheckUtils]: 151: Hoare triple {59097#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {59097#false} is VALID [2022-02-21 04:23:24,820 INFO L290 TraceCheckUtils]: 152: Hoare triple {59097#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {59097#false} is VALID [2022-02-21 04:23:24,820 INFO L290 TraceCheckUtils]: 153: Hoare triple {59097#false} assume !(0 != start_simulation_~tmp___0~1#1); {59097#false} is VALID [2022-02-21 04:23:24,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:24,820 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:24,820 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1975652582] [2022-02-21 04:23:24,820 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1975652582] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:24,821 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:24,821 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:24,821 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591150046] [2022-02-21 04:23:24,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:24,821 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:24,821 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:24,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:24,822 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:24,822 INFO L87 Difference]: Start difference. First operand 1788 states and 2644 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:25,946 INFO L93 Difference]: Finished difference Result 1788 states and 2643 transitions. [2022-02-21 04:23:25,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:25,946 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,040 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:26,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2643 transitions. [2022-02-21 04:23:26,107 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:26,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2643 transitions. [2022-02-21 04:23:26,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:26,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:26,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2643 transitions. [2022-02-21 04:23:26,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:26,177 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2022-02-21 04:23:26,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2643 transitions. [2022-02-21 04:23:26,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:26,190 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:26,193 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2643 transitions. Second operand has 1788 states, 1788 states have (on average 1.4781879194630871) internal successors, (2643), 1787 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,194 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2643 transitions. Second operand has 1788 states, 1788 states have (on average 1.4781879194630871) internal successors, (2643), 1787 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,195 INFO L87 Difference]: Start difference. First operand 1788 states and 2643 transitions. Second operand has 1788 states, 1788 states have (on average 1.4781879194630871) internal successors, (2643), 1787 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,263 INFO L93 Difference]: Finished difference Result 1788 states and 2643 transitions. [2022-02-21 04:23:26,263 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2643 transitions. [2022-02-21 04:23:26,265 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:26,265 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:26,267 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4781879194630871) internal successors, (2643), 1787 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2643 transitions. [2022-02-21 04:23:26,268 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4781879194630871) internal successors, (2643), 1787 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2643 transitions. [2022-02-21 04:23:26,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,335 INFO L93 Difference]: Finished difference Result 1788 states and 2643 transitions. [2022-02-21 04:23:26,335 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2643 transitions. [2022-02-21 04:23:26,336 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:26,336 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:26,336 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:26,336 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:26,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4781879194630871) internal successors, (2643), 1787 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2643 transitions. [2022-02-21 04:23:26,404 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2022-02-21 04:23:26,404 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2022-02-21 04:23:26,404 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:23:26,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2643 transitions. [2022-02-21 04:23:26,407 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:26,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:26,407 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:26,409 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:26,409 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:26,409 INFO L791 eck$LassoCheckResult]: Stem: 61676#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 61677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 61197#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61198#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61252#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 62591#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61685#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61488#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60887#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60888#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62110#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62221#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 62657#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62658#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 61616#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 61617#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 62139#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 62058#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61651#L1201 assume !(0 == ~M_E~0); 61652#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62498#L1206-1 assume !(0 == ~T2_E~0); 62484#L1211-1 assume !(0 == ~T3_E~0); 62485#L1216-1 assume !(0 == ~T4_E~0); 61472#L1221-1 assume !(0 == ~T5_E~0); 61473#L1226-1 assume !(0 == ~T6_E~0); 61112#L1231-1 assume !(0 == ~T7_E~0); 61113#L1236-1 assume !(0 == ~T8_E~0); 62521#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 61509#L1246-1 assume !(0 == ~T10_E~0); 61510#L1251-1 assume !(0 == ~T11_E~0); 61649#L1256-1 assume !(0 == ~T12_E~0); 60898#L1261-1 assume !(0 == ~E_M~0); 60899#L1266-1 assume !(0 == ~E_1~0); 62643#L1271-1 assume !(0 == ~E_2~0); 62205#L1276-1 assume !(0 == ~E_3~0); 62206#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 62153#L1286-1 assume !(0 == ~E_5~0); 61363#L1291-1 assume !(0 == ~E_6~0); 61364#L1296-1 assume !(0 == ~E_7~0); 61939#L1301-1 assume !(0 == ~E_8~0); 61940#L1306-1 assume !(0 == ~E_9~0); 62420#L1311-1 assume !(0 == ~E_10~0); 61314#L1316-1 assume !(0 == ~E_11~0); 61315#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 61957#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61958#L593 assume 1 == ~m_pc~0; 62102#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61204#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62630#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62164#L1492 assume !(0 != activate_threads_~tmp~1#1); 62165#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62456#L612 assume !(1 == ~t1_pc~0); 62457#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62586#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61586#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61208#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61209#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61628#L631 assume 1 == ~t2_pc~0; 61563#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60985#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60986#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61822#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 61823#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61281#L650 assume !(1 == ~t3_pc~0); 61282#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 61982#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61205#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60938#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 60939#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62131#L669 assume 1 == ~t4_pc~0; 62132#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62490#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61615#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61147#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 61148#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61372#L688 assume !(1 == ~t5_pc~0); 61163#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 61164#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62082#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62016#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 62017#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62146#L707 assume 1 == ~t6_pc~0; 62555#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61792#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61793#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62553#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 62088#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61650#L726 assume 1 == ~t7_pc~0; 61549#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61248#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62289#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62563#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 61017#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61018#L745 assume !(1 == ~t8_pc~0); 61465#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 61484#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62322#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61870#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61871#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62381#L764 assume 1 == ~t9_pc~0; 61648#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61490#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62167#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62614#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 61037#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61038#L783 assume !(1 == ~t10_pc~0); 61099#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 61100#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61141#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61142#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 61604#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62492#L802 assume 1 == ~t11_pc~0; 62474#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60982#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60983#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61474#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 61475#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61585#L821 assume !(1 == ~t12_pc~0); 61836#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 61932#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60987#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60988#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 62530#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62176#L1339 assume !(1 == ~M_E~0); 62177#L1339-2 assume !(1 == ~T1_E~0); 62565#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62566#L1349-1 assume !(1 == ~T3_E~0); 61950#L1354-1 assume !(1 == ~T4_E~0); 61951#L1359-1 assume !(1 == ~T5_E~0); 62352#L1364-1 assume !(1 == ~T6_E~0); 61415#L1369-1 assume !(1 == ~T7_E~0); 61416#L1374-1 assume !(1 == ~T8_E~0); 61953#L1379-1 assume !(1 == ~T9_E~0); 61954#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62053#L1389-1 assume !(1 == ~T11_E~0); 62524#L1394-1 assume !(1 == ~T12_E~0); 62525#L1399-1 assume !(1 == ~E_M~0); 62615#L1404-1 assume !(1 == ~E_1~0); 61514#L1409-1 assume !(1 == ~E_2~0); 61515#L1414-1 assume !(1 == ~E_3~0); 62241#L1419-1 assume !(1 == ~E_4~0); 61155#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 61156#L1429-1 assume !(1 == ~E_6~0); 61966#L1434-1 assume !(1 == ~E_7~0); 62545#L1439-1 assume !(1 == ~E_8~0); 61193#L1444-1 assume !(1 == ~E_9~0); 61194#L1449-1 assume !(1 == ~E_10~0); 61568#L1454-1 assume !(1 == ~E_11~0); 61569#L1459-1 assume !(1 == ~E_12~0); 62087#L1464-1 assume { :end_inline_reset_delta_events } true; 61327#L1810-2 [2022-02-21 04:23:26,410 INFO L793 eck$LassoCheckResult]: Loop: 61327#L1810-2 assume !false; 61771#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61687#L1176 assume !false; 62249#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 61819#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 61025#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 61575#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 61576#L1003 assume !(0 != eval_~tmp~0#1); 61217#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61218#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62408#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 62191#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62192#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62085#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61276#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61277#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61743#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61347#L1231-3 assume !(0 == ~T7_E~0); 61348#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 61594#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62576#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62477#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62182#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 61293#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 61294#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61339#L1271-3 assume !(0 == ~E_2~0); 61340#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61716#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 61717#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62238#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62239#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62654#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62611#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 61828#L1311-3 assume !(0 == ~E_10~0); 61219#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 61220#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 61295#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61931#L593-42 assume 1 == ~m_pc~0; 62324#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62090#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62639#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62640#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61118#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61119#L612-42 assume !(1 == ~t1_pc~0); 62040#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 62433#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62554#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61206#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61207#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61902#L631-42 assume 1 == ~t2_pc~0; 60971#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60972#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61891#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61767#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61768#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61368#L650-42 assume 1 == ~t3_pc~0; 60930#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60931#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62582#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61561#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61562#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62546#L669-42 assume !(1 == ~t4_pc~0); 60928#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 60929#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62357#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62247#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 62144#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62145#L688-42 assume 1 == ~t5_pc~0; 62236#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62437#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61069#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61070#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 61146#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60960#L707-42 assume !(1 == ~t6_pc~0); 60961#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 62618#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62362#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62363#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62112#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62113#L726-42 assume 1 == ~t7_pc~0; 62390#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62416#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62417#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61831#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 61832#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61935#L745-42 assume 1 == ~t8_pc~0; 61972#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61974#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61301#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60946#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60947#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61672#L764-42 assume 1 == ~t9_pc~0; 61808#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62161#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62162#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 61232#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61233#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61286#L783-42 assume 1 == ~t10_pc~0; 60902#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 60903#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61498#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61631#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 62648#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62332#L802-42 assume 1 == ~t11_pc~0; 61433#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61044#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61045#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60995#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 60996#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62172#L821-42 assume !(1 == ~t12_pc~0); 61537#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 61538#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60900#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60901#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61878#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61868#L1339-3 assume !(1 == ~M_E~0); 61869#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62020#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62130#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61547#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61548#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62141#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62637#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62544#L1374-3 assume !(1 == ~T8_E~0); 61369#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61370#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61545#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61546#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 61755#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62551#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62519#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62520#L1414-3 assume !(1 == ~E_3~0); 62575#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62334#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61253#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61254#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 62140#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61181#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 61182#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 61298#L1454-3 assume !(1 == ~E_11~0); 62135#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 62136#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 61794#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 61091#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 61351#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 61352#L1829 assume !(0 == start_simulation_~tmp~3#1); 61073#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 61074#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 61874#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 61875#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 62154#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 62155#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 61775#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 61326#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 61327#L1810-2 [2022-02-21 04:23:26,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:26,410 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2022-02-21 04:23:26,410 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:26,410 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069187525] [2022-02-21 04:23:26,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:26,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:26,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:26,428 INFO L290 TraceCheckUtils]: 0: Hoare triple {66254#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {66254#true} is VALID [2022-02-21 04:23:26,429 INFO L290 TraceCheckUtils]: 1: Hoare triple {66254#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,429 INFO L290 TraceCheckUtils]: 2: Hoare triple {66256#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,429 INFO L290 TraceCheckUtils]: 3: Hoare triple {66256#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,429 INFO L290 TraceCheckUtils]: 4: Hoare triple {66256#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,430 INFO L290 TraceCheckUtils]: 5: Hoare triple {66256#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,430 INFO L290 TraceCheckUtils]: 6: Hoare triple {66256#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,430 INFO L290 TraceCheckUtils]: 7: Hoare triple {66256#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,430 INFO L290 TraceCheckUtils]: 8: Hoare triple {66256#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,431 INFO L290 TraceCheckUtils]: 9: Hoare triple {66256#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,431 INFO L290 TraceCheckUtils]: 10: Hoare triple {66256#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,431 INFO L290 TraceCheckUtils]: 11: Hoare triple {66256#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,431 INFO L290 TraceCheckUtils]: 12: Hoare triple {66256#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,432 INFO L290 TraceCheckUtils]: 13: Hoare triple {66256#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {66256#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:26,432 INFO L290 TraceCheckUtils]: 14: Hoare triple {66256#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {66255#false} is VALID [2022-02-21 04:23:26,432 INFO L290 TraceCheckUtils]: 15: Hoare triple {66255#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {66255#false} is VALID [2022-02-21 04:23:26,432 INFO L290 TraceCheckUtils]: 16: Hoare triple {66255#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {66255#false} is VALID [2022-02-21 04:23:26,432 INFO L290 TraceCheckUtils]: 17: Hoare triple {66255#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {66255#false} is VALID [2022-02-21 04:23:26,432 INFO L290 TraceCheckUtils]: 18: Hoare triple {66255#false} assume !(0 == ~M_E~0); {66255#false} is VALID [2022-02-21 04:23:26,433 INFO L290 TraceCheckUtils]: 19: Hoare triple {66255#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {66255#false} is VALID [2022-02-21 04:23:26,433 INFO L290 TraceCheckUtils]: 20: Hoare triple {66255#false} assume !(0 == ~T2_E~0); {66255#false} is VALID [2022-02-21 04:23:26,433 INFO L290 TraceCheckUtils]: 21: Hoare triple {66255#false} assume !(0 == ~T3_E~0); {66255#false} is VALID [2022-02-21 04:23:26,433 INFO L290 TraceCheckUtils]: 22: Hoare triple {66255#false} assume !(0 == ~T4_E~0); {66255#false} is VALID [2022-02-21 04:23:26,433 INFO L290 TraceCheckUtils]: 23: Hoare triple {66255#false} assume !(0 == ~T5_E~0); {66255#false} is VALID [2022-02-21 04:23:26,433 INFO L290 TraceCheckUtils]: 24: Hoare triple {66255#false} assume !(0 == ~T6_E~0); {66255#false} is VALID [2022-02-21 04:23:26,433 INFO L290 TraceCheckUtils]: 25: Hoare triple {66255#false} assume !(0 == ~T7_E~0); {66255#false} is VALID [2022-02-21 04:23:26,433 INFO L290 TraceCheckUtils]: 26: Hoare triple {66255#false} assume !(0 == ~T8_E~0); {66255#false} is VALID [2022-02-21 04:23:26,433 INFO L290 TraceCheckUtils]: 27: Hoare triple {66255#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {66255#false} is VALID [2022-02-21 04:23:26,434 INFO L290 TraceCheckUtils]: 28: Hoare triple {66255#false} assume !(0 == ~T10_E~0); {66255#false} is VALID [2022-02-21 04:23:26,434 INFO L290 TraceCheckUtils]: 29: Hoare triple {66255#false} assume !(0 == ~T11_E~0); {66255#false} is VALID [2022-02-21 04:23:26,434 INFO L290 TraceCheckUtils]: 30: Hoare triple {66255#false} assume !(0 == ~T12_E~0); {66255#false} is VALID [2022-02-21 04:23:26,434 INFO L290 TraceCheckUtils]: 31: Hoare triple {66255#false} assume !(0 == ~E_M~0); {66255#false} is VALID [2022-02-21 04:23:26,434 INFO L290 TraceCheckUtils]: 32: Hoare triple {66255#false} assume !(0 == ~E_1~0); {66255#false} is VALID [2022-02-21 04:23:26,434 INFO L290 TraceCheckUtils]: 33: Hoare triple {66255#false} assume !(0 == ~E_2~0); {66255#false} is VALID [2022-02-21 04:23:26,434 INFO L290 TraceCheckUtils]: 34: Hoare triple {66255#false} assume !(0 == ~E_3~0); {66255#false} is VALID [2022-02-21 04:23:26,434 INFO L290 TraceCheckUtils]: 35: Hoare triple {66255#false} assume 0 == ~E_4~0;~E_4~0 := 1; {66255#false} is VALID [2022-02-21 04:23:26,434 INFO L290 TraceCheckUtils]: 36: Hoare triple {66255#false} assume !(0 == ~E_5~0); {66255#false} is VALID [2022-02-21 04:23:26,435 INFO L290 TraceCheckUtils]: 37: Hoare triple {66255#false} assume !(0 == ~E_6~0); {66255#false} is VALID [2022-02-21 04:23:26,435 INFO L290 TraceCheckUtils]: 38: Hoare triple {66255#false} assume !(0 == ~E_7~0); {66255#false} is VALID [2022-02-21 04:23:26,435 INFO L290 TraceCheckUtils]: 39: Hoare triple {66255#false} assume !(0 == ~E_8~0); {66255#false} is VALID [2022-02-21 04:23:26,435 INFO L290 TraceCheckUtils]: 40: Hoare triple {66255#false} assume !(0 == ~E_9~0); {66255#false} is VALID [2022-02-21 04:23:26,435 INFO L290 TraceCheckUtils]: 41: Hoare triple {66255#false} assume !(0 == ~E_10~0); {66255#false} is VALID [2022-02-21 04:23:26,435 INFO L290 TraceCheckUtils]: 42: Hoare triple {66255#false} assume !(0 == ~E_11~0); {66255#false} is VALID [2022-02-21 04:23:26,435 INFO L290 TraceCheckUtils]: 43: Hoare triple {66255#false} assume 0 == ~E_12~0;~E_12~0 := 1; {66255#false} is VALID [2022-02-21 04:23:26,435 INFO L290 TraceCheckUtils]: 44: Hoare triple {66255#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66255#false} is VALID [2022-02-21 04:23:26,436 INFO L290 TraceCheckUtils]: 45: Hoare triple {66255#false} assume 1 == ~m_pc~0; {66255#false} is VALID [2022-02-21 04:23:26,436 INFO L290 TraceCheckUtils]: 46: Hoare triple {66255#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {66255#false} is VALID [2022-02-21 04:23:26,436 INFO L290 TraceCheckUtils]: 47: Hoare triple {66255#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66255#false} is VALID [2022-02-21 04:23:26,436 INFO L290 TraceCheckUtils]: 48: Hoare triple {66255#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {66255#false} is VALID [2022-02-21 04:23:26,436 INFO L290 TraceCheckUtils]: 49: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp~1#1); {66255#false} is VALID [2022-02-21 04:23:26,436 INFO L290 TraceCheckUtils]: 50: Hoare triple {66255#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66255#false} is VALID [2022-02-21 04:23:26,436 INFO L290 TraceCheckUtils]: 51: Hoare triple {66255#false} assume !(1 == ~t1_pc~0); {66255#false} is VALID [2022-02-21 04:23:26,436 INFO L290 TraceCheckUtils]: 52: Hoare triple {66255#false} is_transmit1_triggered_~__retres1~1#1 := 0; {66255#false} is VALID [2022-02-21 04:23:26,436 INFO L290 TraceCheckUtils]: 53: Hoare triple {66255#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66255#false} is VALID [2022-02-21 04:23:26,437 INFO L290 TraceCheckUtils]: 54: Hoare triple {66255#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {66255#false} is VALID [2022-02-21 04:23:26,437 INFO L290 TraceCheckUtils]: 55: Hoare triple {66255#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {66255#false} is VALID [2022-02-21 04:23:26,437 INFO L290 TraceCheckUtils]: 56: Hoare triple {66255#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66255#false} is VALID [2022-02-21 04:23:26,437 INFO L290 TraceCheckUtils]: 57: Hoare triple {66255#false} assume 1 == ~t2_pc~0; {66255#false} is VALID [2022-02-21 04:23:26,437 INFO L290 TraceCheckUtils]: 58: Hoare triple {66255#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {66255#false} is VALID [2022-02-21 04:23:26,437 INFO L290 TraceCheckUtils]: 59: Hoare triple {66255#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66255#false} is VALID [2022-02-21 04:23:26,437 INFO L290 TraceCheckUtils]: 60: Hoare triple {66255#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {66255#false} is VALID [2022-02-21 04:23:26,437 INFO L290 TraceCheckUtils]: 61: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp___1~0#1); {66255#false} is VALID [2022-02-21 04:23:26,437 INFO L290 TraceCheckUtils]: 62: Hoare triple {66255#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66255#false} is VALID [2022-02-21 04:23:26,438 INFO L290 TraceCheckUtils]: 63: Hoare triple {66255#false} assume !(1 == ~t3_pc~0); {66255#false} is VALID [2022-02-21 04:23:26,438 INFO L290 TraceCheckUtils]: 64: Hoare triple {66255#false} is_transmit3_triggered_~__retres1~3#1 := 0; {66255#false} is VALID [2022-02-21 04:23:26,438 INFO L290 TraceCheckUtils]: 65: Hoare triple {66255#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66255#false} is VALID [2022-02-21 04:23:26,438 INFO L290 TraceCheckUtils]: 66: Hoare triple {66255#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {66255#false} is VALID [2022-02-21 04:23:26,438 INFO L290 TraceCheckUtils]: 67: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp___2~0#1); {66255#false} is VALID [2022-02-21 04:23:26,438 INFO L290 TraceCheckUtils]: 68: Hoare triple {66255#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66255#false} is VALID [2022-02-21 04:23:26,438 INFO L290 TraceCheckUtils]: 69: Hoare triple {66255#false} assume 1 == ~t4_pc~0; {66255#false} is VALID [2022-02-21 04:23:26,438 INFO L290 TraceCheckUtils]: 70: Hoare triple {66255#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {66255#false} is VALID [2022-02-21 04:23:26,438 INFO L290 TraceCheckUtils]: 71: Hoare triple {66255#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66255#false} is VALID [2022-02-21 04:23:26,439 INFO L290 TraceCheckUtils]: 72: Hoare triple {66255#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {66255#false} is VALID [2022-02-21 04:23:26,439 INFO L290 TraceCheckUtils]: 73: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp___3~0#1); {66255#false} is VALID [2022-02-21 04:23:26,439 INFO L290 TraceCheckUtils]: 74: Hoare triple {66255#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66255#false} is VALID [2022-02-21 04:23:26,439 INFO L290 TraceCheckUtils]: 75: Hoare triple {66255#false} assume !(1 == ~t5_pc~0); {66255#false} is VALID [2022-02-21 04:23:26,439 INFO L290 TraceCheckUtils]: 76: Hoare triple {66255#false} is_transmit5_triggered_~__retres1~5#1 := 0; {66255#false} is VALID [2022-02-21 04:23:26,439 INFO L290 TraceCheckUtils]: 77: Hoare triple {66255#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66255#false} is VALID [2022-02-21 04:23:26,439 INFO L290 TraceCheckUtils]: 78: Hoare triple {66255#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {66255#false} is VALID [2022-02-21 04:23:26,439 INFO L290 TraceCheckUtils]: 79: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp___4~0#1); {66255#false} is VALID [2022-02-21 04:23:26,439 INFO L290 TraceCheckUtils]: 80: Hoare triple {66255#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66255#false} is VALID [2022-02-21 04:23:26,440 INFO L290 TraceCheckUtils]: 81: Hoare triple {66255#false} assume 1 == ~t6_pc~0; {66255#false} is VALID [2022-02-21 04:23:26,440 INFO L290 TraceCheckUtils]: 82: Hoare triple {66255#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {66255#false} is VALID [2022-02-21 04:23:26,440 INFO L290 TraceCheckUtils]: 83: Hoare triple {66255#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66255#false} is VALID [2022-02-21 04:23:26,440 INFO L290 TraceCheckUtils]: 84: Hoare triple {66255#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {66255#false} is VALID [2022-02-21 04:23:26,440 INFO L290 TraceCheckUtils]: 85: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp___5~0#1); {66255#false} is VALID [2022-02-21 04:23:26,440 INFO L290 TraceCheckUtils]: 86: Hoare triple {66255#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {66255#false} is VALID [2022-02-21 04:23:26,440 INFO L290 TraceCheckUtils]: 87: Hoare triple {66255#false} assume 1 == ~t7_pc~0; {66255#false} is VALID [2022-02-21 04:23:26,440 INFO L290 TraceCheckUtils]: 88: Hoare triple {66255#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {66255#false} is VALID [2022-02-21 04:23:26,441 INFO L290 TraceCheckUtils]: 89: Hoare triple {66255#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {66255#false} is VALID [2022-02-21 04:23:26,441 INFO L290 TraceCheckUtils]: 90: Hoare triple {66255#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {66255#false} is VALID [2022-02-21 04:23:26,441 INFO L290 TraceCheckUtils]: 91: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp___6~0#1); {66255#false} is VALID [2022-02-21 04:23:26,441 INFO L290 TraceCheckUtils]: 92: Hoare triple {66255#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {66255#false} is VALID [2022-02-21 04:23:26,441 INFO L290 TraceCheckUtils]: 93: Hoare triple {66255#false} assume !(1 == ~t8_pc~0); {66255#false} is VALID [2022-02-21 04:23:26,441 INFO L290 TraceCheckUtils]: 94: Hoare triple {66255#false} is_transmit8_triggered_~__retres1~8#1 := 0; {66255#false} is VALID [2022-02-21 04:23:26,441 INFO L290 TraceCheckUtils]: 95: Hoare triple {66255#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {66255#false} is VALID [2022-02-21 04:23:26,441 INFO L290 TraceCheckUtils]: 96: Hoare triple {66255#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {66255#false} is VALID [2022-02-21 04:23:26,441 INFO L290 TraceCheckUtils]: 97: Hoare triple {66255#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {66255#false} is VALID [2022-02-21 04:23:26,442 INFO L290 TraceCheckUtils]: 98: Hoare triple {66255#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {66255#false} is VALID [2022-02-21 04:23:26,442 INFO L290 TraceCheckUtils]: 99: Hoare triple {66255#false} assume 1 == ~t9_pc~0; {66255#false} is VALID [2022-02-21 04:23:26,442 INFO L290 TraceCheckUtils]: 100: Hoare triple {66255#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {66255#false} is VALID [2022-02-21 04:23:26,442 INFO L290 TraceCheckUtils]: 101: Hoare triple {66255#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {66255#false} is VALID [2022-02-21 04:23:26,442 INFO L290 TraceCheckUtils]: 102: Hoare triple {66255#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {66255#false} is VALID [2022-02-21 04:23:26,442 INFO L290 TraceCheckUtils]: 103: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp___8~0#1); {66255#false} is VALID [2022-02-21 04:23:26,442 INFO L290 TraceCheckUtils]: 104: Hoare triple {66255#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {66255#false} is VALID [2022-02-21 04:23:26,442 INFO L290 TraceCheckUtils]: 105: Hoare triple {66255#false} assume !(1 == ~t10_pc~0); {66255#false} is VALID [2022-02-21 04:23:26,442 INFO L290 TraceCheckUtils]: 106: Hoare triple {66255#false} is_transmit10_triggered_~__retres1~10#1 := 0; {66255#false} is VALID [2022-02-21 04:23:26,443 INFO L290 TraceCheckUtils]: 107: Hoare triple {66255#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {66255#false} is VALID [2022-02-21 04:23:26,443 INFO L290 TraceCheckUtils]: 108: Hoare triple {66255#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {66255#false} is VALID [2022-02-21 04:23:26,443 INFO L290 TraceCheckUtils]: 109: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp___9~0#1); {66255#false} is VALID [2022-02-21 04:23:26,443 INFO L290 TraceCheckUtils]: 110: Hoare triple {66255#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {66255#false} is VALID [2022-02-21 04:23:26,443 INFO L290 TraceCheckUtils]: 111: Hoare triple {66255#false} assume 1 == ~t11_pc~0; {66255#false} is VALID [2022-02-21 04:23:26,443 INFO L290 TraceCheckUtils]: 112: Hoare triple {66255#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {66255#false} is VALID [2022-02-21 04:23:26,443 INFO L290 TraceCheckUtils]: 113: Hoare triple {66255#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {66255#false} is VALID [2022-02-21 04:23:26,443 INFO L290 TraceCheckUtils]: 114: Hoare triple {66255#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {66255#false} is VALID [2022-02-21 04:23:26,443 INFO L290 TraceCheckUtils]: 115: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp___10~0#1); {66255#false} is VALID [2022-02-21 04:23:26,444 INFO L290 TraceCheckUtils]: 116: Hoare triple {66255#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {66255#false} is VALID [2022-02-21 04:23:26,444 INFO L290 TraceCheckUtils]: 117: Hoare triple {66255#false} assume !(1 == ~t12_pc~0); {66255#false} is VALID [2022-02-21 04:23:26,444 INFO L290 TraceCheckUtils]: 118: Hoare triple {66255#false} is_transmit12_triggered_~__retres1~12#1 := 0; {66255#false} is VALID [2022-02-21 04:23:26,444 INFO L290 TraceCheckUtils]: 119: Hoare triple {66255#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {66255#false} is VALID [2022-02-21 04:23:26,444 INFO L290 TraceCheckUtils]: 120: Hoare triple {66255#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {66255#false} is VALID [2022-02-21 04:23:26,444 INFO L290 TraceCheckUtils]: 121: Hoare triple {66255#false} assume !(0 != activate_threads_~tmp___11~0#1); {66255#false} is VALID [2022-02-21 04:23:26,444 INFO L290 TraceCheckUtils]: 122: Hoare triple {66255#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66255#false} is VALID [2022-02-21 04:23:26,444 INFO L290 TraceCheckUtils]: 123: Hoare triple {66255#false} assume !(1 == ~M_E~0); {66255#false} is VALID [2022-02-21 04:23:26,444 INFO L290 TraceCheckUtils]: 124: Hoare triple {66255#false} assume !(1 == ~T1_E~0); {66255#false} is VALID [2022-02-21 04:23:26,445 INFO L290 TraceCheckUtils]: 125: Hoare triple {66255#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {66255#false} is VALID [2022-02-21 04:23:26,445 INFO L290 TraceCheckUtils]: 126: Hoare triple {66255#false} assume !(1 == ~T3_E~0); {66255#false} is VALID [2022-02-21 04:23:26,445 INFO L290 TraceCheckUtils]: 127: Hoare triple {66255#false} assume !(1 == ~T4_E~0); {66255#false} is VALID [2022-02-21 04:23:26,445 INFO L290 TraceCheckUtils]: 128: Hoare triple {66255#false} assume !(1 == ~T5_E~0); {66255#false} is VALID [2022-02-21 04:23:26,445 INFO L290 TraceCheckUtils]: 129: Hoare triple {66255#false} assume !(1 == ~T6_E~0); {66255#false} is VALID [2022-02-21 04:23:26,445 INFO L290 TraceCheckUtils]: 130: Hoare triple {66255#false} assume !(1 == ~T7_E~0); {66255#false} is VALID [2022-02-21 04:23:26,445 INFO L290 TraceCheckUtils]: 131: Hoare triple {66255#false} assume !(1 == ~T8_E~0); {66255#false} is VALID [2022-02-21 04:23:26,445 INFO L290 TraceCheckUtils]: 132: Hoare triple {66255#false} assume !(1 == ~T9_E~0); {66255#false} is VALID [2022-02-21 04:23:26,445 INFO L290 TraceCheckUtils]: 133: Hoare triple {66255#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {66255#false} is VALID [2022-02-21 04:23:26,446 INFO L290 TraceCheckUtils]: 134: Hoare triple {66255#false} assume !(1 == ~T11_E~0); {66255#false} is VALID [2022-02-21 04:23:26,446 INFO L290 TraceCheckUtils]: 135: Hoare triple {66255#false} assume !(1 == ~T12_E~0); {66255#false} is VALID [2022-02-21 04:23:26,446 INFO L290 TraceCheckUtils]: 136: Hoare triple {66255#false} assume !(1 == ~E_M~0); {66255#false} is VALID [2022-02-21 04:23:26,446 INFO L290 TraceCheckUtils]: 137: Hoare triple {66255#false} assume !(1 == ~E_1~0); {66255#false} is VALID [2022-02-21 04:23:26,446 INFO L290 TraceCheckUtils]: 138: Hoare triple {66255#false} assume !(1 == ~E_2~0); {66255#false} is VALID [2022-02-21 04:23:26,446 INFO L290 TraceCheckUtils]: 139: Hoare triple {66255#false} assume !(1 == ~E_3~0); {66255#false} is VALID [2022-02-21 04:23:26,446 INFO L290 TraceCheckUtils]: 140: Hoare triple {66255#false} assume !(1 == ~E_4~0); {66255#false} is VALID [2022-02-21 04:23:26,446 INFO L290 TraceCheckUtils]: 141: Hoare triple {66255#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66255#false} is VALID [2022-02-21 04:23:26,446 INFO L290 TraceCheckUtils]: 142: Hoare triple {66255#false} assume !(1 == ~E_6~0); {66255#false} is VALID [2022-02-21 04:23:26,447 INFO L290 TraceCheckUtils]: 143: Hoare triple {66255#false} assume !(1 == ~E_7~0); {66255#false} is VALID [2022-02-21 04:23:26,447 INFO L290 TraceCheckUtils]: 144: Hoare triple {66255#false} assume !(1 == ~E_8~0); {66255#false} is VALID [2022-02-21 04:23:26,447 INFO L290 TraceCheckUtils]: 145: Hoare triple {66255#false} assume !(1 == ~E_9~0); {66255#false} is VALID [2022-02-21 04:23:26,447 INFO L290 TraceCheckUtils]: 146: Hoare triple {66255#false} assume !(1 == ~E_10~0); {66255#false} is VALID [2022-02-21 04:23:26,447 INFO L290 TraceCheckUtils]: 147: Hoare triple {66255#false} assume !(1 == ~E_11~0); {66255#false} is VALID [2022-02-21 04:23:26,447 INFO L290 TraceCheckUtils]: 148: Hoare triple {66255#false} assume !(1 == ~E_12~0); {66255#false} is VALID [2022-02-21 04:23:26,447 INFO L290 TraceCheckUtils]: 149: Hoare triple {66255#false} assume { :end_inline_reset_delta_events } true; {66255#false} is VALID [2022-02-21 04:23:26,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:26,448 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:26,448 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069187525] [2022-02-21 04:23:26,448 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2069187525] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:26,448 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:26,448 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:26,448 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316807942] [2022-02-21 04:23:26,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:26,449 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:26,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:26,449 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 2 times [2022-02-21 04:23:26,449 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:26,449 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874446745] [2022-02-21 04:23:26,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:26,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:26,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:26,473 INFO L290 TraceCheckUtils]: 0: Hoare triple {66257#true} assume !false; {66257#true} is VALID [2022-02-21 04:23:26,474 INFO L290 TraceCheckUtils]: 1: Hoare triple {66257#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {66257#true} is VALID [2022-02-21 04:23:26,474 INFO L290 TraceCheckUtils]: 2: Hoare triple {66257#true} assume !false; {66257#true} is VALID [2022-02-21 04:23:26,474 INFO L290 TraceCheckUtils]: 3: Hoare triple {66257#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {66257#true} is VALID [2022-02-21 04:23:26,474 INFO L290 TraceCheckUtils]: 4: Hoare triple {66257#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {66257#true} is VALID [2022-02-21 04:23:26,474 INFO L290 TraceCheckUtils]: 5: Hoare triple {66257#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {66257#true} is VALID [2022-02-21 04:23:26,474 INFO L290 TraceCheckUtils]: 6: Hoare triple {66257#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {66257#true} is VALID [2022-02-21 04:23:26,474 INFO L290 TraceCheckUtils]: 7: Hoare triple {66257#true} assume !(0 != eval_~tmp~0#1); {66257#true} is VALID [2022-02-21 04:23:26,474 INFO L290 TraceCheckUtils]: 8: Hoare triple {66257#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {66257#true} is VALID [2022-02-21 04:23:26,475 INFO L290 TraceCheckUtils]: 9: Hoare triple {66257#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {66257#true} is VALID [2022-02-21 04:23:26,475 INFO L290 TraceCheckUtils]: 10: Hoare triple {66257#true} assume 0 == ~M_E~0;~M_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,475 INFO L290 TraceCheckUtils]: 11: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,475 INFO L290 TraceCheckUtils]: 12: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,476 INFO L290 TraceCheckUtils]: 13: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,476 INFO L290 TraceCheckUtils]: 14: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,476 INFO L290 TraceCheckUtils]: 15: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,476 INFO L290 TraceCheckUtils]: 16: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,477 INFO L290 TraceCheckUtils]: 17: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,477 INFO L290 TraceCheckUtils]: 18: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,477 INFO L290 TraceCheckUtils]: 19: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,477 INFO L290 TraceCheckUtils]: 20: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,478 INFO L290 TraceCheckUtils]: 21: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,478 INFO L290 TraceCheckUtils]: 22: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,478 INFO L290 TraceCheckUtils]: 23: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,478 INFO L290 TraceCheckUtils]: 24: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,479 INFO L290 TraceCheckUtils]: 25: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,479 INFO L290 TraceCheckUtils]: 26: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,479 INFO L290 TraceCheckUtils]: 27: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,479 INFO L290 TraceCheckUtils]: 28: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,480 INFO L290 TraceCheckUtils]: 29: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,480 INFO L290 TraceCheckUtils]: 30: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,480 INFO L290 TraceCheckUtils]: 31: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,480 INFO L290 TraceCheckUtils]: 32: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,481 INFO L290 TraceCheckUtils]: 33: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,481 INFO L290 TraceCheckUtils]: 34: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,481 INFO L290 TraceCheckUtils]: 35: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,481 INFO L290 TraceCheckUtils]: 36: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,482 INFO L290 TraceCheckUtils]: 37: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,482 INFO L290 TraceCheckUtils]: 38: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,482 INFO L290 TraceCheckUtils]: 39: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,482 INFO L290 TraceCheckUtils]: 40: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,483 INFO L290 TraceCheckUtils]: 41: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,483 INFO L290 TraceCheckUtils]: 42: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,483 INFO L290 TraceCheckUtils]: 43: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,483 INFO L290 TraceCheckUtils]: 44: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,484 INFO L290 TraceCheckUtils]: 45: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,484 INFO L290 TraceCheckUtils]: 46: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,484 INFO L290 TraceCheckUtils]: 47: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,484 INFO L290 TraceCheckUtils]: 48: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,485 INFO L290 TraceCheckUtils]: 49: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,485 INFO L290 TraceCheckUtils]: 50: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,485 INFO L290 TraceCheckUtils]: 51: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,485 INFO L290 TraceCheckUtils]: 52: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,486 INFO L290 TraceCheckUtils]: 53: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,486 INFO L290 TraceCheckUtils]: 54: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,486 INFO L290 TraceCheckUtils]: 55: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,486 INFO L290 TraceCheckUtils]: 56: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,487 INFO L290 TraceCheckUtils]: 57: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,487 INFO L290 TraceCheckUtils]: 58: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,487 INFO L290 TraceCheckUtils]: 59: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,487 INFO L290 TraceCheckUtils]: 60: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,488 INFO L290 TraceCheckUtils]: 61: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,488 INFO L290 TraceCheckUtils]: 62: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,488 INFO L290 TraceCheckUtils]: 63: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,488 INFO L290 TraceCheckUtils]: 64: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,489 INFO L290 TraceCheckUtils]: 65: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,489 INFO L290 TraceCheckUtils]: 66: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,489 INFO L290 TraceCheckUtils]: 67: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,489 INFO L290 TraceCheckUtils]: 68: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,490 INFO L290 TraceCheckUtils]: 69: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,490 INFO L290 TraceCheckUtils]: 70: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,490 INFO L290 TraceCheckUtils]: 71: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,490 INFO L290 TraceCheckUtils]: 72: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,491 INFO L290 TraceCheckUtils]: 73: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,491 INFO L290 TraceCheckUtils]: 74: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,491 INFO L290 TraceCheckUtils]: 75: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,491 INFO L290 TraceCheckUtils]: 76: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,492 INFO L290 TraceCheckUtils]: 77: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,492 INFO L290 TraceCheckUtils]: 78: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,492 INFO L290 TraceCheckUtils]: 79: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,492 INFO L290 TraceCheckUtils]: 80: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,493 INFO L290 TraceCheckUtils]: 81: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,493 INFO L290 TraceCheckUtils]: 82: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,493 INFO L290 TraceCheckUtils]: 83: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,493 INFO L290 TraceCheckUtils]: 84: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,494 INFO L290 TraceCheckUtils]: 85: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,494 INFO L290 TraceCheckUtils]: 86: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,494 INFO L290 TraceCheckUtils]: 87: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,494 INFO L290 TraceCheckUtils]: 88: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,495 INFO L290 TraceCheckUtils]: 89: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,495 INFO L290 TraceCheckUtils]: 90: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,495 INFO L290 TraceCheckUtils]: 91: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,495 INFO L290 TraceCheckUtils]: 92: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,496 INFO L290 TraceCheckUtils]: 93: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,496 INFO L290 TraceCheckUtils]: 94: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,496 INFO L290 TraceCheckUtils]: 95: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,496 INFO L290 TraceCheckUtils]: 96: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,497 INFO L290 TraceCheckUtils]: 97: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,497 INFO L290 TraceCheckUtils]: 98: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,497 INFO L290 TraceCheckUtils]: 99: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,497 INFO L290 TraceCheckUtils]: 100: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,498 INFO L290 TraceCheckUtils]: 101: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,498 INFO L290 TraceCheckUtils]: 102: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,498 INFO L290 TraceCheckUtils]: 103: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,498 INFO L290 TraceCheckUtils]: 104: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,499 INFO L290 TraceCheckUtils]: 105: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,499 INFO L290 TraceCheckUtils]: 106: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,499 INFO L290 TraceCheckUtils]: 107: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,499 INFO L290 TraceCheckUtils]: 108: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,500 INFO L290 TraceCheckUtils]: 109: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,500 INFO L290 TraceCheckUtils]: 110: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,500 INFO L290 TraceCheckUtils]: 111: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,500 INFO L290 TraceCheckUtils]: 112: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,501 INFO L290 TraceCheckUtils]: 113: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,501 INFO L290 TraceCheckUtils]: 114: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66259#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:26,501 INFO L290 TraceCheckUtils]: 115: Hoare triple {66259#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {66258#false} is VALID [2022-02-21 04:23:26,501 INFO L290 TraceCheckUtils]: 116: Hoare triple {66258#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,501 INFO L290 TraceCheckUtils]: 117: Hoare triple {66258#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,501 INFO L290 TraceCheckUtils]: 118: Hoare triple {66258#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,502 INFO L290 TraceCheckUtils]: 119: Hoare triple {66258#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,502 INFO L290 TraceCheckUtils]: 120: Hoare triple {66258#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,502 INFO L290 TraceCheckUtils]: 121: Hoare triple {66258#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,502 INFO L290 TraceCheckUtils]: 122: Hoare triple {66258#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,502 INFO L290 TraceCheckUtils]: 123: Hoare triple {66258#false} assume !(1 == ~T8_E~0); {66258#false} is VALID [2022-02-21 04:23:26,502 INFO L290 TraceCheckUtils]: 124: Hoare triple {66258#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,502 INFO L290 TraceCheckUtils]: 125: Hoare triple {66258#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,502 INFO L290 TraceCheckUtils]: 126: Hoare triple {66258#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,502 INFO L290 TraceCheckUtils]: 127: Hoare triple {66258#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,503 INFO L290 TraceCheckUtils]: 128: Hoare triple {66258#false} assume 1 == ~E_M~0;~E_M~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,503 INFO L290 TraceCheckUtils]: 129: Hoare triple {66258#false} assume 1 == ~E_1~0;~E_1~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,503 INFO L290 TraceCheckUtils]: 130: Hoare triple {66258#false} assume 1 == ~E_2~0;~E_2~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,503 INFO L290 TraceCheckUtils]: 131: Hoare triple {66258#false} assume !(1 == ~E_3~0); {66258#false} is VALID [2022-02-21 04:23:26,503 INFO L290 TraceCheckUtils]: 132: Hoare triple {66258#false} assume 1 == ~E_4~0;~E_4~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,503 INFO L290 TraceCheckUtils]: 133: Hoare triple {66258#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,503 INFO L290 TraceCheckUtils]: 134: Hoare triple {66258#false} assume 1 == ~E_6~0;~E_6~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,503 INFO L290 TraceCheckUtils]: 135: Hoare triple {66258#false} assume 1 == ~E_7~0;~E_7~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,503 INFO L290 TraceCheckUtils]: 136: Hoare triple {66258#false} assume 1 == ~E_8~0;~E_8~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,504 INFO L290 TraceCheckUtils]: 137: Hoare triple {66258#false} assume 1 == ~E_9~0;~E_9~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,504 INFO L290 TraceCheckUtils]: 138: Hoare triple {66258#false} assume 1 == ~E_10~0;~E_10~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,504 INFO L290 TraceCheckUtils]: 139: Hoare triple {66258#false} assume !(1 == ~E_11~0); {66258#false} is VALID [2022-02-21 04:23:26,504 INFO L290 TraceCheckUtils]: 140: Hoare triple {66258#false} assume 1 == ~E_12~0;~E_12~0 := 2; {66258#false} is VALID [2022-02-21 04:23:26,504 INFO L290 TraceCheckUtils]: 141: Hoare triple {66258#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {66258#false} is VALID [2022-02-21 04:23:26,504 INFO L290 TraceCheckUtils]: 142: Hoare triple {66258#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {66258#false} is VALID [2022-02-21 04:23:26,504 INFO L290 TraceCheckUtils]: 143: Hoare triple {66258#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {66258#false} is VALID [2022-02-21 04:23:26,504 INFO L290 TraceCheckUtils]: 144: Hoare triple {66258#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {66258#false} is VALID [2022-02-21 04:23:26,504 INFO L290 TraceCheckUtils]: 145: Hoare triple {66258#false} assume !(0 == start_simulation_~tmp~3#1); {66258#false} is VALID [2022-02-21 04:23:26,505 INFO L290 TraceCheckUtils]: 146: Hoare triple {66258#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {66258#false} is VALID [2022-02-21 04:23:26,505 INFO L290 TraceCheckUtils]: 147: Hoare triple {66258#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {66258#false} is VALID [2022-02-21 04:23:26,505 INFO L290 TraceCheckUtils]: 148: Hoare triple {66258#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {66258#false} is VALID [2022-02-21 04:23:26,505 INFO L290 TraceCheckUtils]: 149: Hoare triple {66258#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {66258#false} is VALID [2022-02-21 04:23:26,505 INFO L290 TraceCheckUtils]: 150: Hoare triple {66258#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {66258#false} is VALID [2022-02-21 04:23:26,505 INFO L290 TraceCheckUtils]: 151: Hoare triple {66258#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {66258#false} is VALID [2022-02-21 04:23:26,505 INFO L290 TraceCheckUtils]: 152: Hoare triple {66258#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {66258#false} is VALID [2022-02-21 04:23:26,505 INFO L290 TraceCheckUtils]: 153: Hoare triple {66258#false} assume !(0 != start_simulation_~tmp___0~1#1); {66258#false} is VALID [2022-02-21 04:23:26,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:26,506 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:26,506 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [874446745] [2022-02-21 04:23:26,506 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [874446745] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:26,506 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:26,506 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:26,507 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880432091] [2022-02-21 04:23:26,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:26,507 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:26,507 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:26,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:26,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:26,508 INFO L87 Difference]: Start difference. First operand 1788 states and 2643 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:27,638 INFO L93 Difference]: Finished difference Result 1788 states and 2642 transitions. [2022-02-21 04:23:27,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:27,639 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,724 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:27,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2642 transitions. [2022-02-21 04:23:27,794 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:27,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2642 transitions. [2022-02-21 04:23:27,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:27,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:27,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2642 transitions. [2022-02-21 04:23:27,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:27,867 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2022-02-21 04:23:27,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2642 transitions. [2022-02-21 04:23:27,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:27,880 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:27,881 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2642 transitions. Second operand has 1788 states, 1788 states have (on average 1.4776286353467563) internal successors, (2642), 1787 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,882 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2642 transitions. Second operand has 1788 states, 1788 states have (on average 1.4776286353467563) internal successors, (2642), 1787 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,883 INFO L87 Difference]: Start difference. First operand 1788 states and 2642 transitions. Second operand has 1788 states, 1788 states have (on average 1.4776286353467563) internal successors, (2642), 1787 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:27,951 INFO L93 Difference]: Finished difference Result 1788 states and 2642 transitions. [2022-02-21 04:23:27,951 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2642 transitions. [2022-02-21 04:23:27,953 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:27,953 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:27,955 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4776286353467563) internal successors, (2642), 1787 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2642 transitions. [2022-02-21 04:23:27,956 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4776286353467563) internal successors, (2642), 1787 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2642 transitions. [2022-02-21 04:23:28,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:28,022 INFO L93 Difference]: Finished difference Result 1788 states and 2642 transitions. [2022-02-21 04:23:28,022 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2642 transitions. [2022-02-21 04:23:28,024 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:28,024 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:28,024 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:28,024 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:28,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4776286353467563) internal successors, (2642), 1787 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2642 transitions. [2022-02-21 04:23:28,107 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2022-02-21 04:23:28,107 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2022-02-21 04:23:28,107 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:23:28,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2642 transitions. [2022-02-21 04:23:28,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:28,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:28,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:28,111 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:28,111 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:28,111 INFO L791 eck$LassoCheckResult]: Stem: 68837#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 68838#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 68358#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68359#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68413#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 69752#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68846#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68649#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68048#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68049#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69271#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69382#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69818#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 69819#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 68777#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 68778#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 69300#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 69219#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68812#L1201 assume !(0 == ~M_E~0); 68813#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69659#L1206-1 assume !(0 == ~T2_E~0); 69645#L1211-1 assume !(0 == ~T3_E~0); 69646#L1216-1 assume !(0 == ~T4_E~0); 68633#L1221-1 assume !(0 == ~T5_E~0); 68634#L1226-1 assume !(0 == ~T6_E~0); 68273#L1231-1 assume !(0 == ~T7_E~0); 68274#L1236-1 assume !(0 == ~T8_E~0); 69682#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 68670#L1246-1 assume !(0 == ~T10_E~0); 68671#L1251-1 assume !(0 == ~T11_E~0); 68810#L1256-1 assume !(0 == ~T12_E~0); 68059#L1261-1 assume !(0 == ~E_M~0); 68060#L1266-1 assume !(0 == ~E_1~0); 69804#L1271-1 assume !(0 == ~E_2~0); 69366#L1276-1 assume !(0 == ~E_3~0); 69367#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 69314#L1286-1 assume !(0 == ~E_5~0); 68524#L1291-1 assume !(0 == ~E_6~0); 68525#L1296-1 assume !(0 == ~E_7~0); 69100#L1301-1 assume !(0 == ~E_8~0); 69101#L1306-1 assume !(0 == ~E_9~0); 69581#L1311-1 assume !(0 == ~E_10~0); 68475#L1316-1 assume !(0 == ~E_11~0); 68476#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 69118#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69119#L593 assume 1 == ~m_pc~0; 69263#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 68365#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69791#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69325#L1492 assume !(0 != activate_threads_~tmp~1#1); 69326#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69617#L612 assume !(1 == ~t1_pc~0); 69618#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69747#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68747#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68369#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68370#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68789#L631 assume 1 == ~t2_pc~0; 68724#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68146#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68147#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68983#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 68984#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68442#L650 assume !(1 == ~t3_pc~0); 68443#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69143#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68366#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68099#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 68100#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69292#L669 assume 1 == ~t4_pc~0; 69293#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 69651#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68776#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68308#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 68309#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68533#L688 assume !(1 == ~t5_pc~0); 68324#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68325#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69243#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69177#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 69178#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69307#L707 assume 1 == ~t6_pc~0; 69716#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68953#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68954#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69714#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 69249#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68811#L726 assume 1 == ~t7_pc~0; 68710#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68409#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69450#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69724#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 68178#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68179#L745 assume !(1 == ~t8_pc~0); 68626#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 68645#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69483#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69031#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 69032#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69542#L764 assume 1 == ~t9_pc~0; 68809#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68651#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69328#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69775#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 68198#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68199#L783 assume !(1 == ~t10_pc~0); 68260#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 68261#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68302#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68303#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 68765#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69653#L802 assume 1 == ~t11_pc~0; 69635#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68143#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68144#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68635#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 68636#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68746#L821 assume !(1 == ~t12_pc~0); 68997#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69093#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68148#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68149#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 69691#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69337#L1339 assume !(1 == ~M_E~0); 69338#L1339-2 assume !(1 == ~T1_E~0); 69726#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69727#L1349-1 assume !(1 == ~T3_E~0); 69111#L1354-1 assume !(1 == ~T4_E~0); 69112#L1359-1 assume !(1 == ~T5_E~0); 69513#L1364-1 assume !(1 == ~T6_E~0); 68576#L1369-1 assume !(1 == ~T7_E~0); 68577#L1374-1 assume !(1 == ~T8_E~0); 69114#L1379-1 assume !(1 == ~T9_E~0); 69115#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69214#L1389-1 assume !(1 == ~T11_E~0); 69685#L1394-1 assume !(1 == ~T12_E~0); 69686#L1399-1 assume !(1 == ~E_M~0); 69776#L1404-1 assume !(1 == ~E_1~0); 68675#L1409-1 assume !(1 == ~E_2~0); 68676#L1414-1 assume !(1 == ~E_3~0); 69402#L1419-1 assume !(1 == ~E_4~0); 68316#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 68317#L1429-1 assume !(1 == ~E_6~0); 69127#L1434-1 assume !(1 == ~E_7~0); 69706#L1439-1 assume !(1 == ~E_8~0); 68354#L1444-1 assume !(1 == ~E_9~0); 68355#L1449-1 assume !(1 == ~E_10~0); 68729#L1454-1 assume !(1 == ~E_11~0); 68730#L1459-1 assume !(1 == ~E_12~0); 69248#L1464-1 assume { :end_inline_reset_delta_events } true; 68488#L1810-2 [2022-02-21 04:23:28,111 INFO L793 eck$LassoCheckResult]: Loop: 68488#L1810-2 assume !false; 68932#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68848#L1176 assume !false; 69410#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 68980#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 68186#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 68736#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 68737#L1003 assume !(0 != eval_~tmp~0#1); 68378#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68379#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69569#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 69352#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69353#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 69246#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68437#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68438#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68904#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68508#L1231-3 assume !(0 == ~T7_E~0); 68509#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 68755#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69737#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 69638#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 69343#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 68454#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68455#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68500#L1271-3 assume !(0 == ~E_2~0); 68501#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68877#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 68878#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69399#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69400#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 69815#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69772#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68989#L1311-3 assume !(0 == ~E_10~0); 68380#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 68381#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 68456#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69092#L593-42 assume !(1 == ~m_pc~0); 69250#L593-44 is_master_triggered_~__retres1~0#1 := 0; 69251#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69800#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69801#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68279#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68280#L612-42 assume !(1 == ~t1_pc~0); 69201#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 69594#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69715#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68367#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68368#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69063#L631-42 assume 1 == ~t2_pc~0; 68132#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68133#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69052#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68928#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68929#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68529#L650-42 assume 1 == ~t3_pc~0; 68091#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68092#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69743#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68722#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68723#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69707#L669-42 assume !(1 == ~t4_pc~0); 68089#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 68090#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69518#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69408#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 69305#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69306#L688-42 assume 1 == ~t5_pc~0; 69397#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69598#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68230#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68231#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 68307#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68121#L707-42 assume 1 == ~t6_pc~0; 68123#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69779#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69523#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69524#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69273#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69274#L726-42 assume !(1 == ~t7_pc~0); 69552#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 69577#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69578#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68992#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68993#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69096#L745-42 assume 1 == ~t8_pc~0; 69133#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69135#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68462#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68107#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68108#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68833#L764-42 assume 1 == ~t9_pc~0; 68969#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69322#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69323#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68393#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 68394#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68447#L783-42 assume !(1 == ~t10_pc~0); 68065#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 68064#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68659#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68792#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69809#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69493#L802-42 assume !(1 == ~t11_pc~0); 68595#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 68205#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68206#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68156#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68157#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69333#L821-42 assume 1 == ~t12_pc~0; 69334#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 68699#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68061#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68062#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69039#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69029#L1339-3 assume !(1 == ~M_E~0); 69030#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69181#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69291#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68708#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68709#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69302#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69798#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69705#L1374-3 assume !(1 == ~T8_E~0); 68530#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 68531#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 68706#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68707#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 68916#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69712#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69680#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69681#L1414-3 assume !(1 == ~E_3~0); 69736#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69495#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68414#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 68415#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 69301#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68342#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 68343#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 68459#L1454-3 assume !(1 == ~E_11~0); 69296#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69297#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 68955#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 68252#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 68512#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 68513#L1829 assume !(0 == start_simulation_~tmp~3#1); 68234#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 68235#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 69035#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 69036#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 69315#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69316#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68936#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68487#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 68488#L1810-2 [2022-02-21 04:23:28,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:28,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2022-02-21 04:23:28,112 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:28,112 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746729316] [2022-02-21 04:23:28,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:28,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:28,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:28,134 INFO L290 TraceCheckUtils]: 0: Hoare triple {73415#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {73415#true} is VALID [2022-02-21 04:23:28,134 INFO L290 TraceCheckUtils]: 1: Hoare triple {73415#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,134 INFO L290 TraceCheckUtils]: 2: Hoare triple {73417#(= ~t11_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,135 INFO L290 TraceCheckUtils]: 3: Hoare triple {73417#(= ~t11_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,135 INFO L290 TraceCheckUtils]: 4: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,135 INFO L290 TraceCheckUtils]: 5: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,135 INFO L290 TraceCheckUtils]: 6: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,136 INFO L290 TraceCheckUtils]: 7: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,136 INFO L290 TraceCheckUtils]: 8: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,136 INFO L290 TraceCheckUtils]: 9: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,136 INFO L290 TraceCheckUtils]: 10: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,137 INFO L290 TraceCheckUtils]: 11: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,137 INFO L290 TraceCheckUtils]: 12: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,137 INFO L290 TraceCheckUtils]: 13: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,137 INFO L290 TraceCheckUtils]: 14: Hoare triple {73417#(= ~t11_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {73417#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:28,138 INFO L290 TraceCheckUtils]: 15: Hoare triple {73417#(= ~t11_i~0 1)} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {73416#false} is VALID [2022-02-21 04:23:28,138 INFO L290 TraceCheckUtils]: 16: Hoare triple {73416#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {73416#false} is VALID [2022-02-21 04:23:28,138 INFO L290 TraceCheckUtils]: 17: Hoare triple {73416#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {73416#false} is VALID [2022-02-21 04:23:28,138 INFO L290 TraceCheckUtils]: 18: Hoare triple {73416#false} assume !(0 == ~M_E~0); {73416#false} is VALID [2022-02-21 04:23:28,138 INFO L290 TraceCheckUtils]: 19: Hoare triple {73416#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {73416#false} is VALID [2022-02-21 04:23:28,138 INFO L290 TraceCheckUtils]: 20: Hoare triple {73416#false} assume !(0 == ~T2_E~0); {73416#false} is VALID [2022-02-21 04:23:28,138 INFO L290 TraceCheckUtils]: 21: Hoare triple {73416#false} assume !(0 == ~T3_E~0); {73416#false} is VALID [2022-02-21 04:23:28,139 INFO L290 TraceCheckUtils]: 22: Hoare triple {73416#false} assume !(0 == ~T4_E~0); {73416#false} is VALID [2022-02-21 04:23:28,139 INFO L290 TraceCheckUtils]: 23: Hoare triple {73416#false} assume !(0 == ~T5_E~0); {73416#false} is VALID [2022-02-21 04:23:28,139 INFO L290 TraceCheckUtils]: 24: Hoare triple {73416#false} assume !(0 == ~T6_E~0); {73416#false} is VALID [2022-02-21 04:23:28,139 INFO L290 TraceCheckUtils]: 25: Hoare triple {73416#false} assume !(0 == ~T7_E~0); {73416#false} is VALID [2022-02-21 04:23:28,139 INFO L290 TraceCheckUtils]: 26: Hoare triple {73416#false} assume !(0 == ~T8_E~0); {73416#false} is VALID [2022-02-21 04:23:28,139 INFO L290 TraceCheckUtils]: 27: Hoare triple {73416#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {73416#false} is VALID [2022-02-21 04:23:28,139 INFO L290 TraceCheckUtils]: 28: Hoare triple {73416#false} assume !(0 == ~T10_E~0); {73416#false} is VALID [2022-02-21 04:23:28,139 INFO L290 TraceCheckUtils]: 29: Hoare triple {73416#false} assume !(0 == ~T11_E~0); {73416#false} is VALID [2022-02-21 04:23:28,139 INFO L290 TraceCheckUtils]: 30: Hoare triple {73416#false} assume !(0 == ~T12_E~0); {73416#false} is VALID [2022-02-21 04:23:28,140 INFO L290 TraceCheckUtils]: 31: Hoare triple {73416#false} assume !(0 == ~E_M~0); {73416#false} is VALID [2022-02-21 04:23:28,140 INFO L290 TraceCheckUtils]: 32: Hoare triple {73416#false} assume !(0 == ~E_1~0); {73416#false} is VALID [2022-02-21 04:23:28,140 INFO L290 TraceCheckUtils]: 33: Hoare triple {73416#false} assume !(0 == ~E_2~0); {73416#false} is VALID [2022-02-21 04:23:28,140 INFO L290 TraceCheckUtils]: 34: Hoare triple {73416#false} assume !(0 == ~E_3~0); {73416#false} is VALID [2022-02-21 04:23:28,140 INFO L290 TraceCheckUtils]: 35: Hoare triple {73416#false} assume 0 == ~E_4~0;~E_4~0 := 1; {73416#false} is VALID [2022-02-21 04:23:28,140 INFO L290 TraceCheckUtils]: 36: Hoare triple {73416#false} assume !(0 == ~E_5~0); {73416#false} is VALID [2022-02-21 04:23:28,140 INFO L290 TraceCheckUtils]: 37: Hoare triple {73416#false} assume !(0 == ~E_6~0); {73416#false} is VALID [2022-02-21 04:23:28,140 INFO L290 TraceCheckUtils]: 38: Hoare triple {73416#false} assume !(0 == ~E_7~0); {73416#false} is VALID [2022-02-21 04:23:28,140 INFO L290 TraceCheckUtils]: 39: Hoare triple {73416#false} assume !(0 == ~E_8~0); {73416#false} is VALID [2022-02-21 04:23:28,141 INFO L290 TraceCheckUtils]: 40: Hoare triple {73416#false} assume !(0 == ~E_9~0); {73416#false} is VALID [2022-02-21 04:23:28,141 INFO L290 TraceCheckUtils]: 41: Hoare triple {73416#false} assume !(0 == ~E_10~0); {73416#false} is VALID [2022-02-21 04:23:28,141 INFO L290 TraceCheckUtils]: 42: Hoare triple {73416#false} assume !(0 == ~E_11~0); {73416#false} is VALID [2022-02-21 04:23:28,141 INFO L290 TraceCheckUtils]: 43: Hoare triple {73416#false} assume 0 == ~E_12~0;~E_12~0 := 1; {73416#false} is VALID [2022-02-21 04:23:28,141 INFO L290 TraceCheckUtils]: 44: Hoare triple {73416#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {73416#false} is VALID [2022-02-21 04:23:28,141 INFO L290 TraceCheckUtils]: 45: Hoare triple {73416#false} assume 1 == ~m_pc~0; {73416#false} is VALID [2022-02-21 04:23:28,141 INFO L290 TraceCheckUtils]: 46: Hoare triple {73416#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {73416#false} is VALID [2022-02-21 04:23:28,141 INFO L290 TraceCheckUtils]: 47: Hoare triple {73416#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {73416#false} is VALID [2022-02-21 04:23:28,141 INFO L290 TraceCheckUtils]: 48: Hoare triple {73416#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {73416#false} is VALID [2022-02-21 04:23:28,142 INFO L290 TraceCheckUtils]: 49: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp~1#1); {73416#false} is VALID [2022-02-21 04:23:28,142 INFO L290 TraceCheckUtils]: 50: Hoare triple {73416#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {73416#false} is VALID [2022-02-21 04:23:28,142 INFO L290 TraceCheckUtils]: 51: Hoare triple {73416#false} assume !(1 == ~t1_pc~0); {73416#false} is VALID [2022-02-21 04:23:28,142 INFO L290 TraceCheckUtils]: 52: Hoare triple {73416#false} is_transmit1_triggered_~__retres1~1#1 := 0; {73416#false} is VALID [2022-02-21 04:23:28,142 INFO L290 TraceCheckUtils]: 53: Hoare triple {73416#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {73416#false} is VALID [2022-02-21 04:23:28,142 INFO L290 TraceCheckUtils]: 54: Hoare triple {73416#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {73416#false} is VALID [2022-02-21 04:23:28,142 INFO L290 TraceCheckUtils]: 55: Hoare triple {73416#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {73416#false} is VALID [2022-02-21 04:23:28,142 INFO L290 TraceCheckUtils]: 56: Hoare triple {73416#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {73416#false} is VALID [2022-02-21 04:23:28,142 INFO L290 TraceCheckUtils]: 57: Hoare triple {73416#false} assume 1 == ~t2_pc~0; {73416#false} is VALID [2022-02-21 04:23:28,143 INFO L290 TraceCheckUtils]: 58: Hoare triple {73416#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {73416#false} is VALID [2022-02-21 04:23:28,143 INFO L290 TraceCheckUtils]: 59: Hoare triple {73416#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {73416#false} is VALID [2022-02-21 04:23:28,143 INFO L290 TraceCheckUtils]: 60: Hoare triple {73416#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {73416#false} is VALID [2022-02-21 04:23:28,143 INFO L290 TraceCheckUtils]: 61: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp___1~0#1); {73416#false} is VALID [2022-02-21 04:23:28,143 INFO L290 TraceCheckUtils]: 62: Hoare triple {73416#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {73416#false} is VALID [2022-02-21 04:23:28,143 INFO L290 TraceCheckUtils]: 63: Hoare triple {73416#false} assume !(1 == ~t3_pc~0); {73416#false} is VALID [2022-02-21 04:23:28,143 INFO L290 TraceCheckUtils]: 64: Hoare triple {73416#false} is_transmit3_triggered_~__retres1~3#1 := 0; {73416#false} is VALID [2022-02-21 04:23:28,143 INFO L290 TraceCheckUtils]: 65: Hoare triple {73416#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {73416#false} is VALID [2022-02-21 04:23:28,143 INFO L290 TraceCheckUtils]: 66: Hoare triple {73416#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {73416#false} is VALID [2022-02-21 04:23:28,144 INFO L290 TraceCheckUtils]: 67: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp___2~0#1); {73416#false} is VALID [2022-02-21 04:23:28,144 INFO L290 TraceCheckUtils]: 68: Hoare triple {73416#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {73416#false} is VALID [2022-02-21 04:23:28,144 INFO L290 TraceCheckUtils]: 69: Hoare triple {73416#false} assume 1 == ~t4_pc~0; {73416#false} is VALID [2022-02-21 04:23:28,144 INFO L290 TraceCheckUtils]: 70: Hoare triple {73416#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {73416#false} is VALID [2022-02-21 04:23:28,144 INFO L290 TraceCheckUtils]: 71: Hoare triple {73416#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {73416#false} is VALID [2022-02-21 04:23:28,144 INFO L290 TraceCheckUtils]: 72: Hoare triple {73416#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {73416#false} is VALID [2022-02-21 04:23:28,144 INFO L290 TraceCheckUtils]: 73: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp___3~0#1); {73416#false} is VALID [2022-02-21 04:23:28,144 INFO L290 TraceCheckUtils]: 74: Hoare triple {73416#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {73416#false} is VALID [2022-02-21 04:23:28,144 INFO L290 TraceCheckUtils]: 75: Hoare triple {73416#false} assume !(1 == ~t5_pc~0); {73416#false} is VALID [2022-02-21 04:23:28,145 INFO L290 TraceCheckUtils]: 76: Hoare triple {73416#false} is_transmit5_triggered_~__retres1~5#1 := 0; {73416#false} is VALID [2022-02-21 04:23:28,145 INFO L290 TraceCheckUtils]: 77: Hoare triple {73416#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {73416#false} is VALID [2022-02-21 04:23:28,145 INFO L290 TraceCheckUtils]: 78: Hoare triple {73416#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {73416#false} is VALID [2022-02-21 04:23:28,145 INFO L290 TraceCheckUtils]: 79: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp___4~0#1); {73416#false} is VALID [2022-02-21 04:23:28,145 INFO L290 TraceCheckUtils]: 80: Hoare triple {73416#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {73416#false} is VALID [2022-02-21 04:23:28,145 INFO L290 TraceCheckUtils]: 81: Hoare triple {73416#false} assume 1 == ~t6_pc~0; {73416#false} is VALID [2022-02-21 04:23:28,145 INFO L290 TraceCheckUtils]: 82: Hoare triple {73416#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {73416#false} is VALID [2022-02-21 04:23:28,145 INFO L290 TraceCheckUtils]: 83: Hoare triple {73416#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {73416#false} is VALID [2022-02-21 04:23:28,145 INFO L290 TraceCheckUtils]: 84: Hoare triple {73416#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {73416#false} is VALID [2022-02-21 04:23:28,146 INFO L290 TraceCheckUtils]: 85: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp___5~0#1); {73416#false} is VALID [2022-02-21 04:23:28,146 INFO L290 TraceCheckUtils]: 86: Hoare triple {73416#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {73416#false} is VALID [2022-02-21 04:23:28,146 INFO L290 TraceCheckUtils]: 87: Hoare triple {73416#false} assume 1 == ~t7_pc~0; {73416#false} is VALID [2022-02-21 04:23:28,146 INFO L290 TraceCheckUtils]: 88: Hoare triple {73416#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {73416#false} is VALID [2022-02-21 04:23:28,146 INFO L290 TraceCheckUtils]: 89: Hoare triple {73416#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {73416#false} is VALID [2022-02-21 04:23:28,146 INFO L290 TraceCheckUtils]: 90: Hoare triple {73416#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {73416#false} is VALID [2022-02-21 04:23:28,146 INFO L290 TraceCheckUtils]: 91: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp___6~0#1); {73416#false} is VALID [2022-02-21 04:23:28,146 INFO L290 TraceCheckUtils]: 92: Hoare triple {73416#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {73416#false} is VALID [2022-02-21 04:23:28,146 INFO L290 TraceCheckUtils]: 93: Hoare triple {73416#false} assume !(1 == ~t8_pc~0); {73416#false} is VALID [2022-02-21 04:23:28,147 INFO L290 TraceCheckUtils]: 94: Hoare triple {73416#false} is_transmit8_triggered_~__retres1~8#1 := 0; {73416#false} is VALID [2022-02-21 04:23:28,147 INFO L290 TraceCheckUtils]: 95: Hoare triple {73416#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {73416#false} is VALID [2022-02-21 04:23:28,147 INFO L290 TraceCheckUtils]: 96: Hoare triple {73416#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {73416#false} is VALID [2022-02-21 04:23:28,147 INFO L290 TraceCheckUtils]: 97: Hoare triple {73416#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {73416#false} is VALID [2022-02-21 04:23:28,147 INFO L290 TraceCheckUtils]: 98: Hoare triple {73416#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {73416#false} is VALID [2022-02-21 04:23:28,147 INFO L290 TraceCheckUtils]: 99: Hoare triple {73416#false} assume 1 == ~t9_pc~0; {73416#false} is VALID [2022-02-21 04:23:28,147 INFO L290 TraceCheckUtils]: 100: Hoare triple {73416#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {73416#false} is VALID [2022-02-21 04:23:28,147 INFO L290 TraceCheckUtils]: 101: Hoare triple {73416#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {73416#false} is VALID [2022-02-21 04:23:28,147 INFO L290 TraceCheckUtils]: 102: Hoare triple {73416#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {73416#false} is VALID [2022-02-21 04:23:28,148 INFO L290 TraceCheckUtils]: 103: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp___8~0#1); {73416#false} is VALID [2022-02-21 04:23:28,148 INFO L290 TraceCheckUtils]: 104: Hoare triple {73416#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {73416#false} is VALID [2022-02-21 04:23:28,148 INFO L290 TraceCheckUtils]: 105: Hoare triple {73416#false} assume !(1 == ~t10_pc~0); {73416#false} is VALID [2022-02-21 04:23:28,148 INFO L290 TraceCheckUtils]: 106: Hoare triple {73416#false} is_transmit10_triggered_~__retres1~10#1 := 0; {73416#false} is VALID [2022-02-21 04:23:28,148 INFO L290 TraceCheckUtils]: 107: Hoare triple {73416#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {73416#false} is VALID [2022-02-21 04:23:28,148 INFO L290 TraceCheckUtils]: 108: Hoare triple {73416#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {73416#false} is VALID [2022-02-21 04:23:28,148 INFO L290 TraceCheckUtils]: 109: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp___9~0#1); {73416#false} is VALID [2022-02-21 04:23:28,148 INFO L290 TraceCheckUtils]: 110: Hoare triple {73416#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {73416#false} is VALID [2022-02-21 04:23:28,149 INFO L290 TraceCheckUtils]: 111: Hoare triple {73416#false} assume 1 == ~t11_pc~0; {73416#false} is VALID [2022-02-21 04:23:28,149 INFO L290 TraceCheckUtils]: 112: Hoare triple {73416#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {73416#false} is VALID [2022-02-21 04:23:28,149 INFO L290 TraceCheckUtils]: 113: Hoare triple {73416#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {73416#false} is VALID [2022-02-21 04:23:28,149 INFO L290 TraceCheckUtils]: 114: Hoare triple {73416#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {73416#false} is VALID [2022-02-21 04:23:28,149 INFO L290 TraceCheckUtils]: 115: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp___10~0#1); {73416#false} is VALID [2022-02-21 04:23:28,149 INFO L290 TraceCheckUtils]: 116: Hoare triple {73416#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {73416#false} is VALID [2022-02-21 04:23:28,149 INFO L290 TraceCheckUtils]: 117: Hoare triple {73416#false} assume !(1 == ~t12_pc~0); {73416#false} is VALID [2022-02-21 04:23:28,149 INFO L290 TraceCheckUtils]: 118: Hoare triple {73416#false} is_transmit12_triggered_~__retres1~12#1 := 0; {73416#false} is VALID [2022-02-21 04:23:28,149 INFO L290 TraceCheckUtils]: 119: Hoare triple {73416#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {73416#false} is VALID [2022-02-21 04:23:28,150 INFO L290 TraceCheckUtils]: 120: Hoare triple {73416#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {73416#false} is VALID [2022-02-21 04:23:28,150 INFO L290 TraceCheckUtils]: 121: Hoare triple {73416#false} assume !(0 != activate_threads_~tmp___11~0#1); {73416#false} is VALID [2022-02-21 04:23:28,150 INFO L290 TraceCheckUtils]: 122: Hoare triple {73416#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {73416#false} is VALID [2022-02-21 04:23:28,150 INFO L290 TraceCheckUtils]: 123: Hoare triple {73416#false} assume !(1 == ~M_E~0); {73416#false} is VALID [2022-02-21 04:23:28,150 INFO L290 TraceCheckUtils]: 124: Hoare triple {73416#false} assume !(1 == ~T1_E~0); {73416#false} is VALID [2022-02-21 04:23:28,150 INFO L290 TraceCheckUtils]: 125: Hoare triple {73416#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {73416#false} is VALID [2022-02-21 04:23:28,150 INFO L290 TraceCheckUtils]: 126: Hoare triple {73416#false} assume !(1 == ~T3_E~0); {73416#false} is VALID [2022-02-21 04:23:28,150 INFO L290 TraceCheckUtils]: 127: Hoare triple {73416#false} assume !(1 == ~T4_E~0); {73416#false} is VALID [2022-02-21 04:23:28,150 INFO L290 TraceCheckUtils]: 128: Hoare triple {73416#false} assume !(1 == ~T5_E~0); {73416#false} is VALID [2022-02-21 04:23:28,151 INFO L290 TraceCheckUtils]: 129: Hoare triple {73416#false} assume !(1 == ~T6_E~0); {73416#false} is VALID [2022-02-21 04:23:28,151 INFO L290 TraceCheckUtils]: 130: Hoare triple {73416#false} assume !(1 == ~T7_E~0); {73416#false} is VALID [2022-02-21 04:23:28,151 INFO L290 TraceCheckUtils]: 131: Hoare triple {73416#false} assume !(1 == ~T8_E~0); {73416#false} is VALID [2022-02-21 04:23:28,151 INFO L290 TraceCheckUtils]: 132: Hoare triple {73416#false} assume !(1 == ~T9_E~0); {73416#false} is VALID [2022-02-21 04:23:28,151 INFO L290 TraceCheckUtils]: 133: Hoare triple {73416#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {73416#false} is VALID [2022-02-21 04:23:28,151 INFO L290 TraceCheckUtils]: 134: Hoare triple {73416#false} assume !(1 == ~T11_E~0); {73416#false} is VALID [2022-02-21 04:23:28,151 INFO L290 TraceCheckUtils]: 135: Hoare triple {73416#false} assume !(1 == ~T12_E~0); {73416#false} is VALID [2022-02-21 04:23:28,151 INFO L290 TraceCheckUtils]: 136: Hoare triple {73416#false} assume !(1 == ~E_M~0); {73416#false} is VALID [2022-02-21 04:23:28,151 INFO L290 TraceCheckUtils]: 137: Hoare triple {73416#false} assume !(1 == ~E_1~0); {73416#false} is VALID [2022-02-21 04:23:28,152 INFO L290 TraceCheckUtils]: 138: Hoare triple {73416#false} assume !(1 == ~E_2~0); {73416#false} is VALID [2022-02-21 04:23:28,152 INFO L290 TraceCheckUtils]: 139: Hoare triple {73416#false} assume !(1 == ~E_3~0); {73416#false} is VALID [2022-02-21 04:23:28,152 INFO L290 TraceCheckUtils]: 140: Hoare triple {73416#false} assume !(1 == ~E_4~0); {73416#false} is VALID [2022-02-21 04:23:28,152 INFO L290 TraceCheckUtils]: 141: Hoare triple {73416#false} assume 1 == ~E_5~0;~E_5~0 := 2; {73416#false} is VALID [2022-02-21 04:23:28,152 INFO L290 TraceCheckUtils]: 142: Hoare triple {73416#false} assume !(1 == ~E_6~0); {73416#false} is VALID [2022-02-21 04:23:28,152 INFO L290 TraceCheckUtils]: 143: Hoare triple {73416#false} assume !(1 == ~E_7~0); {73416#false} is VALID [2022-02-21 04:23:28,152 INFO L290 TraceCheckUtils]: 144: Hoare triple {73416#false} assume !(1 == ~E_8~0); {73416#false} is VALID [2022-02-21 04:23:28,152 INFO L290 TraceCheckUtils]: 145: Hoare triple {73416#false} assume !(1 == ~E_9~0); {73416#false} is VALID [2022-02-21 04:23:28,152 INFO L290 TraceCheckUtils]: 146: Hoare triple {73416#false} assume !(1 == ~E_10~0); {73416#false} is VALID [2022-02-21 04:23:28,153 INFO L290 TraceCheckUtils]: 147: Hoare triple {73416#false} assume !(1 == ~E_11~0); {73416#false} is VALID [2022-02-21 04:23:28,153 INFO L290 TraceCheckUtils]: 148: Hoare triple {73416#false} assume !(1 == ~E_12~0); {73416#false} is VALID [2022-02-21 04:23:28,153 INFO L290 TraceCheckUtils]: 149: Hoare triple {73416#false} assume { :end_inline_reset_delta_events } true; {73416#false} is VALID [2022-02-21 04:23:28,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:28,153 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:28,153 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [746729316] [2022-02-21 04:23:28,153 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [746729316] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:28,154 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:28,154 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:28,154 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58369355] [2022-02-21 04:23:28,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:28,154 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:28,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:28,155 INFO L85 PathProgramCache]: Analyzing trace with hash 44919829, now seen corresponding path program 1 times [2022-02-21 04:23:28,155 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:28,155 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319617761] [2022-02-21 04:23:28,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:28,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:28,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:28,181 INFO L290 TraceCheckUtils]: 0: Hoare triple {73418#true} assume !false; {73418#true} is VALID [2022-02-21 04:23:28,181 INFO L290 TraceCheckUtils]: 1: Hoare triple {73418#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {73418#true} is VALID [2022-02-21 04:23:28,181 INFO L290 TraceCheckUtils]: 2: Hoare triple {73418#true} assume !false; {73418#true} is VALID [2022-02-21 04:23:28,181 INFO L290 TraceCheckUtils]: 3: Hoare triple {73418#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {73418#true} is VALID [2022-02-21 04:23:28,181 INFO L290 TraceCheckUtils]: 4: Hoare triple {73418#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {73418#true} is VALID [2022-02-21 04:23:28,181 INFO L290 TraceCheckUtils]: 5: Hoare triple {73418#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {73418#true} is VALID [2022-02-21 04:23:28,181 INFO L290 TraceCheckUtils]: 6: Hoare triple {73418#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {73418#true} is VALID [2022-02-21 04:23:28,182 INFO L290 TraceCheckUtils]: 7: Hoare triple {73418#true} assume !(0 != eval_~tmp~0#1); {73418#true} is VALID [2022-02-21 04:23:28,182 INFO L290 TraceCheckUtils]: 8: Hoare triple {73418#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {73418#true} is VALID [2022-02-21 04:23:28,182 INFO L290 TraceCheckUtils]: 9: Hoare triple {73418#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {73418#true} is VALID [2022-02-21 04:23:28,182 INFO L290 TraceCheckUtils]: 10: Hoare triple {73418#true} assume 0 == ~M_E~0;~M_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,182 INFO L290 TraceCheckUtils]: 11: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,183 INFO L290 TraceCheckUtils]: 12: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,183 INFO L290 TraceCheckUtils]: 13: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,183 INFO L290 TraceCheckUtils]: 14: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,183 INFO L290 TraceCheckUtils]: 15: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,183 INFO L290 TraceCheckUtils]: 16: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,184 INFO L290 TraceCheckUtils]: 17: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,184 INFO L290 TraceCheckUtils]: 18: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,184 INFO L290 TraceCheckUtils]: 19: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,184 INFO L290 TraceCheckUtils]: 20: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,185 INFO L290 TraceCheckUtils]: 21: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,185 INFO L290 TraceCheckUtils]: 22: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,185 INFO L290 TraceCheckUtils]: 23: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,185 INFO L290 TraceCheckUtils]: 24: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,186 INFO L290 TraceCheckUtils]: 25: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,186 INFO L290 TraceCheckUtils]: 26: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,186 INFO L290 TraceCheckUtils]: 27: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,186 INFO L290 TraceCheckUtils]: 28: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,187 INFO L290 TraceCheckUtils]: 29: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,187 INFO L290 TraceCheckUtils]: 30: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,187 INFO L290 TraceCheckUtils]: 31: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,187 INFO L290 TraceCheckUtils]: 32: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,188 INFO L290 TraceCheckUtils]: 33: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,188 INFO L290 TraceCheckUtils]: 34: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,188 INFO L290 TraceCheckUtils]: 35: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,188 INFO L290 TraceCheckUtils]: 36: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,189 INFO L290 TraceCheckUtils]: 37: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,189 INFO L290 TraceCheckUtils]: 38: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,189 INFO L290 TraceCheckUtils]: 39: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,189 INFO L290 TraceCheckUtils]: 40: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,190 INFO L290 TraceCheckUtils]: 41: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,190 INFO L290 TraceCheckUtils]: 42: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,190 INFO L290 TraceCheckUtils]: 43: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,190 INFO L290 TraceCheckUtils]: 44: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,191 INFO L290 TraceCheckUtils]: 45: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,191 INFO L290 TraceCheckUtils]: 46: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,191 INFO L290 TraceCheckUtils]: 47: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,191 INFO L290 TraceCheckUtils]: 48: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,192 INFO L290 TraceCheckUtils]: 49: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,192 INFO L290 TraceCheckUtils]: 50: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,192 INFO L290 TraceCheckUtils]: 51: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,192 INFO L290 TraceCheckUtils]: 52: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,193 INFO L290 TraceCheckUtils]: 53: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,193 INFO L290 TraceCheckUtils]: 54: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,193 INFO L290 TraceCheckUtils]: 55: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,193 INFO L290 TraceCheckUtils]: 56: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,193 INFO L290 TraceCheckUtils]: 57: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,194 INFO L290 TraceCheckUtils]: 58: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,194 INFO L290 TraceCheckUtils]: 59: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,194 INFO L290 TraceCheckUtils]: 60: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,194 INFO L290 TraceCheckUtils]: 61: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,195 INFO L290 TraceCheckUtils]: 62: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,195 INFO L290 TraceCheckUtils]: 63: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,195 INFO L290 TraceCheckUtils]: 64: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,195 INFO L290 TraceCheckUtils]: 65: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,196 INFO L290 TraceCheckUtils]: 66: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,196 INFO L290 TraceCheckUtils]: 67: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,196 INFO L290 TraceCheckUtils]: 68: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,196 INFO L290 TraceCheckUtils]: 69: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,197 INFO L290 TraceCheckUtils]: 70: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,197 INFO L290 TraceCheckUtils]: 71: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,197 INFO L290 TraceCheckUtils]: 72: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,197 INFO L290 TraceCheckUtils]: 73: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,198 INFO L290 TraceCheckUtils]: 74: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,198 INFO L290 TraceCheckUtils]: 75: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,198 INFO L290 TraceCheckUtils]: 76: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,198 INFO L290 TraceCheckUtils]: 77: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,199 INFO L290 TraceCheckUtils]: 78: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,199 INFO L290 TraceCheckUtils]: 79: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,199 INFO L290 TraceCheckUtils]: 80: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,199 INFO L290 TraceCheckUtils]: 81: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,200 INFO L290 TraceCheckUtils]: 82: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,200 INFO L290 TraceCheckUtils]: 83: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,200 INFO L290 TraceCheckUtils]: 84: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,200 INFO L290 TraceCheckUtils]: 85: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,200 INFO L290 TraceCheckUtils]: 86: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,201 INFO L290 TraceCheckUtils]: 87: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,201 INFO L290 TraceCheckUtils]: 88: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,201 INFO L290 TraceCheckUtils]: 89: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,207 INFO L290 TraceCheckUtils]: 90: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,208 INFO L290 TraceCheckUtils]: 91: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,208 INFO L290 TraceCheckUtils]: 92: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,208 INFO L290 TraceCheckUtils]: 93: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,209 INFO L290 TraceCheckUtils]: 94: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,209 INFO L290 TraceCheckUtils]: 95: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,209 INFO L290 TraceCheckUtils]: 96: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,209 INFO L290 TraceCheckUtils]: 97: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,210 INFO L290 TraceCheckUtils]: 98: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,210 INFO L290 TraceCheckUtils]: 99: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,210 INFO L290 TraceCheckUtils]: 100: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,210 INFO L290 TraceCheckUtils]: 101: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,211 INFO L290 TraceCheckUtils]: 102: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,211 INFO L290 TraceCheckUtils]: 103: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,211 INFO L290 TraceCheckUtils]: 104: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,211 INFO L290 TraceCheckUtils]: 105: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,212 INFO L290 TraceCheckUtils]: 106: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,212 INFO L290 TraceCheckUtils]: 107: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,212 INFO L290 TraceCheckUtils]: 108: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,212 INFO L290 TraceCheckUtils]: 109: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,213 INFO L290 TraceCheckUtils]: 110: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,213 INFO L290 TraceCheckUtils]: 111: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,213 INFO L290 TraceCheckUtils]: 112: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,213 INFO L290 TraceCheckUtils]: 113: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,214 INFO L290 TraceCheckUtils]: 114: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {73420#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:28,214 INFO L290 TraceCheckUtils]: 115: Hoare triple {73420#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {73419#false} is VALID [2022-02-21 04:23:28,214 INFO L290 TraceCheckUtils]: 116: Hoare triple {73419#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,214 INFO L290 TraceCheckUtils]: 117: Hoare triple {73419#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,214 INFO L290 TraceCheckUtils]: 118: Hoare triple {73419#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,214 INFO L290 TraceCheckUtils]: 119: Hoare triple {73419#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,214 INFO L290 TraceCheckUtils]: 120: Hoare triple {73419#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,214 INFO L290 TraceCheckUtils]: 121: Hoare triple {73419#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,215 INFO L290 TraceCheckUtils]: 122: Hoare triple {73419#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,215 INFO L290 TraceCheckUtils]: 123: Hoare triple {73419#false} assume !(1 == ~T8_E~0); {73419#false} is VALID [2022-02-21 04:23:28,215 INFO L290 TraceCheckUtils]: 124: Hoare triple {73419#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,215 INFO L290 TraceCheckUtils]: 125: Hoare triple {73419#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,215 INFO L290 TraceCheckUtils]: 126: Hoare triple {73419#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,215 INFO L290 TraceCheckUtils]: 127: Hoare triple {73419#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,215 INFO L290 TraceCheckUtils]: 128: Hoare triple {73419#false} assume 1 == ~E_M~0;~E_M~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,215 INFO L290 TraceCheckUtils]: 129: Hoare triple {73419#false} assume 1 == ~E_1~0;~E_1~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,215 INFO L290 TraceCheckUtils]: 130: Hoare triple {73419#false} assume 1 == ~E_2~0;~E_2~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,216 INFO L290 TraceCheckUtils]: 131: Hoare triple {73419#false} assume !(1 == ~E_3~0); {73419#false} is VALID [2022-02-21 04:23:28,216 INFO L290 TraceCheckUtils]: 132: Hoare triple {73419#false} assume 1 == ~E_4~0;~E_4~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,216 INFO L290 TraceCheckUtils]: 133: Hoare triple {73419#false} assume 1 == ~E_5~0;~E_5~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,216 INFO L290 TraceCheckUtils]: 134: Hoare triple {73419#false} assume 1 == ~E_6~0;~E_6~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,216 INFO L290 TraceCheckUtils]: 135: Hoare triple {73419#false} assume 1 == ~E_7~0;~E_7~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,216 INFO L290 TraceCheckUtils]: 136: Hoare triple {73419#false} assume 1 == ~E_8~0;~E_8~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,216 INFO L290 TraceCheckUtils]: 137: Hoare triple {73419#false} assume 1 == ~E_9~0;~E_9~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,216 INFO L290 TraceCheckUtils]: 138: Hoare triple {73419#false} assume 1 == ~E_10~0;~E_10~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,216 INFO L290 TraceCheckUtils]: 139: Hoare triple {73419#false} assume !(1 == ~E_11~0); {73419#false} is VALID [2022-02-21 04:23:28,217 INFO L290 TraceCheckUtils]: 140: Hoare triple {73419#false} assume 1 == ~E_12~0;~E_12~0 := 2; {73419#false} is VALID [2022-02-21 04:23:28,217 INFO L290 TraceCheckUtils]: 141: Hoare triple {73419#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {73419#false} is VALID [2022-02-21 04:23:28,217 INFO L290 TraceCheckUtils]: 142: Hoare triple {73419#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {73419#false} is VALID [2022-02-21 04:23:28,217 INFO L290 TraceCheckUtils]: 143: Hoare triple {73419#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {73419#false} is VALID [2022-02-21 04:23:28,217 INFO L290 TraceCheckUtils]: 144: Hoare triple {73419#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {73419#false} is VALID [2022-02-21 04:23:28,217 INFO L290 TraceCheckUtils]: 145: Hoare triple {73419#false} assume !(0 == start_simulation_~tmp~3#1); {73419#false} is VALID [2022-02-21 04:23:28,217 INFO L290 TraceCheckUtils]: 146: Hoare triple {73419#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {73419#false} is VALID [2022-02-21 04:23:28,217 INFO L290 TraceCheckUtils]: 147: Hoare triple {73419#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {73419#false} is VALID [2022-02-21 04:23:28,217 INFO L290 TraceCheckUtils]: 148: Hoare triple {73419#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {73419#false} is VALID [2022-02-21 04:23:28,218 INFO L290 TraceCheckUtils]: 149: Hoare triple {73419#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {73419#false} is VALID [2022-02-21 04:23:28,218 INFO L290 TraceCheckUtils]: 150: Hoare triple {73419#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {73419#false} is VALID [2022-02-21 04:23:28,218 INFO L290 TraceCheckUtils]: 151: Hoare triple {73419#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {73419#false} is VALID [2022-02-21 04:23:28,218 INFO L290 TraceCheckUtils]: 152: Hoare triple {73419#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {73419#false} is VALID [2022-02-21 04:23:28,218 INFO L290 TraceCheckUtils]: 153: Hoare triple {73419#false} assume !(0 != start_simulation_~tmp___0~1#1); {73419#false} is VALID [2022-02-21 04:23:28,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:28,219 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:28,219 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319617761] [2022-02-21 04:23:28,219 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319617761] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:28,219 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:28,219 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:28,219 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741901910] [2022-02-21 04:23:28,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:28,220 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:28,220 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:28,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:28,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:28,220 INFO L87 Difference]: Start difference. First operand 1788 states and 2642 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,337 INFO L93 Difference]: Finished difference Result 1788 states and 2641 transitions. [2022-02-21 04:23:29,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:29,341 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,425 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:29,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2641 transitions. [2022-02-21 04:23:29,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:29,570 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2641 transitions. [2022-02-21 04:23:29,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:29,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:29,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2641 transitions. [2022-02-21 04:23:29,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:29,573 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2022-02-21 04:23:29,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2641 transitions. [2022-02-21 04:23:29,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:29,587 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:29,588 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2641 transitions. Second operand has 1788 states, 1788 states have (on average 1.4770693512304252) internal successors, (2641), 1787 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,589 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2641 transitions. Second operand has 1788 states, 1788 states have (on average 1.4770693512304252) internal successors, (2641), 1787 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,590 INFO L87 Difference]: Start difference. First operand 1788 states and 2641 transitions. Second operand has 1788 states, 1788 states have (on average 1.4770693512304252) internal successors, (2641), 1787 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,657 INFO L93 Difference]: Finished difference Result 1788 states and 2641 transitions. [2022-02-21 04:23:29,657 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2641 transitions. [2022-02-21 04:23:29,659 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:29,659 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:29,661 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4770693512304252) internal successors, (2641), 1787 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2641 transitions. [2022-02-21 04:23:29,662 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4770693512304252) internal successors, (2641), 1787 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2641 transitions. [2022-02-21 04:23:29,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,730 INFO L93 Difference]: Finished difference Result 1788 states and 2641 transitions. [2022-02-21 04:23:29,730 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2641 transitions. [2022-02-21 04:23:29,732 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:29,732 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:29,732 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:29,732 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:29,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4770693512304252) internal successors, (2641), 1787 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2641 transitions. [2022-02-21 04:23:29,807 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2022-02-21 04:23:29,807 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2022-02-21 04:23:29,807 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:23:29,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2641 transitions. [2022-02-21 04:23:29,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:29,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:29,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:29,811 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:29,811 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:29,811 INFO L791 eck$LassoCheckResult]: Stem: 75998#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 75999#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 75519#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75520#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75574#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 76913#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76007#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75810#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75209#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75210#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76432#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76545#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76979#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76980#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75938#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75939#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76461#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 76380#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75973#L1201 assume !(0 == ~M_E~0); 75974#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76820#L1206-1 assume !(0 == ~T2_E~0); 76806#L1211-1 assume !(0 == ~T3_E~0); 76807#L1216-1 assume !(0 == ~T4_E~0); 75795#L1221-1 assume !(0 == ~T5_E~0); 75796#L1226-1 assume !(0 == ~T6_E~0); 75434#L1231-1 assume !(0 == ~T7_E~0); 75435#L1236-1 assume !(0 == ~T8_E~0); 76843#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 75834#L1246-1 assume !(0 == ~T10_E~0); 75835#L1251-1 assume !(0 == ~T11_E~0); 75971#L1256-1 assume !(0 == ~T12_E~0); 75222#L1261-1 assume !(0 == ~E_M~0); 75223#L1266-1 assume !(0 == ~E_1~0); 76965#L1271-1 assume !(0 == ~E_2~0); 76527#L1276-1 assume !(0 == ~E_3~0); 76528#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 76475#L1286-1 assume !(0 == ~E_5~0); 75685#L1291-1 assume !(0 == ~E_6~0); 75686#L1296-1 assume !(0 == ~E_7~0); 76261#L1301-1 assume !(0 == ~E_8~0); 76262#L1306-1 assume !(0 == ~E_9~0); 76742#L1311-1 assume !(0 == ~E_10~0); 75636#L1316-1 assume !(0 == ~E_11~0); 75637#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 76279#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76280#L593 assume 1 == ~m_pc~0; 76424#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 75526#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76952#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76486#L1492 assume !(0 != activate_threads_~tmp~1#1); 76487#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76778#L612 assume !(1 == ~t1_pc~0); 76779#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76908#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75908#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75530#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75531#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75950#L631 assume 1 == ~t2_pc~0; 75885#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75307#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75308#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76144#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 76145#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75603#L650 assume !(1 == ~t3_pc~0); 75604#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76304#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75527#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75260#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 75261#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76453#L669 assume 1 == ~t4_pc~0; 76454#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76812#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75937#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75469#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 75470#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75694#L688 assume !(1 == ~t5_pc~0); 75485#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75486#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76404#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76340#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 76341#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76471#L707 assume 1 == ~t6_pc~0; 76877#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76114#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76115#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76875#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 76412#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75972#L726 assume 1 == ~t7_pc~0; 75873#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75570#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76611#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76885#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 75339#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75340#L745 assume !(1 == ~t8_pc~0); 75787#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75806#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76644#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76192#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 76193#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76703#L764 assume 1 == ~t9_pc~0; 75970#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75812#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76489#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76936#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 75359#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75360#L783 assume !(1 == ~t10_pc~0); 75421#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75422#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75463#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75464#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 75931#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76814#L802 assume 1 == ~t11_pc~0; 76796#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75304#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75305#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75797#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 75798#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75907#L821 assume !(1 == ~t12_pc~0); 76158#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76254#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75311#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75312#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 76852#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76498#L1339 assume !(1 == ~M_E~0); 76499#L1339-2 assume !(1 == ~T1_E~0); 76887#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76888#L1349-1 assume !(1 == ~T3_E~0); 76273#L1354-1 assume !(1 == ~T4_E~0); 76274#L1359-1 assume !(1 == ~T5_E~0); 76676#L1364-1 assume !(1 == ~T6_E~0); 75737#L1369-1 assume !(1 == ~T7_E~0); 75738#L1374-1 assume !(1 == ~T8_E~0); 76277#L1379-1 assume !(1 == ~T9_E~0); 76278#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 76375#L1389-1 assume !(1 == ~T11_E~0); 76846#L1394-1 assume !(1 == ~T12_E~0); 76847#L1399-1 assume !(1 == ~E_M~0); 76937#L1404-1 assume !(1 == ~E_1~0); 75838#L1409-1 assume !(1 == ~E_2~0); 75839#L1414-1 assume !(1 == ~E_3~0); 76563#L1419-1 assume !(1 == ~E_4~0); 75477#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 75478#L1429-1 assume !(1 == ~E_6~0); 76288#L1434-1 assume !(1 == ~E_7~0); 76867#L1439-1 assume !(1 == ~E_8~0); 75515#L1444-1 assume !(1 == ~E_9~0); 75516#L1449-1 assume !(1 == ~E_10~0); 75890#L1454-1 assume !(1 == ~E_11~0); 75891#L1459-1 assume !(1 == ~E_12~0); 76409#L1464-1 assume { :end_inline_reset_delta_events } true; 75649#L1810-2 [2022-02-21 04:23:29,811 INFO L793 eck$LassoCheckResult]: Loop: 75649#L1810-2 assume !false; 76093#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76009#L1176 assume !false; 76571#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 76143#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 75347#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 75897#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 75898#L1003 assume !(0 != eval_~tmp~0#1); 75541#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75542#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76730#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 76513#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76514#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 76408#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 75598#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75599#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76065#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 75671#L1231-3 assume !(0 == ~T7_E~0); 75672#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 75918#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 76898#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 76799#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 76504#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 75615#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 75616#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 75659#L1271-3 assume !(0 == ~E_2~0); 75660#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76038#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76039#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76560#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76561#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 76976#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 76933#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 76150#L1311-3 assume !(0 == ~E_10~0); 75539#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 75540#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 75617#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76253#L593-42 assume 1 == ~m_pc~0; 76646#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 76411#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76960#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76961#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75437#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75438#L612-42 assume 1 == ~t1_pc~0; 76363#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76755#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76876#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75528#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75529#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76224#L631-42 assume 1 == ~t2_pc~0; 75293#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75294#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76213#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76089#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76090#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75690#L650-42 assume 1 == ~t3_pc~0; 75252#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75253#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76904#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75883#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 75884#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76868#L669-42 assume !(1 == ~t4_pc~0); 75250#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 75251#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76679#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76569#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 76466#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76467#L688-42 assume !(1 == ~t5_pc~0); 76559#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 76759#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75391#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75392#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 75465#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75282#L707-42 assume !(1 == ~t6_pc~0); 75283#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 76940#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76684#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76685#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76434#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76435#L726-42 assume !(1 == ~t7_pc~0); 76713#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 76738#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76739#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76153#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 76154#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76257#L745-42 assume !(1 == ~t8_pc~0); 76295#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 76296#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75623#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75268#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75269#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75994#L764-42 assume !(1 == ~t9_pc~0); 76131#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 76483#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76484#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75554#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 75555#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75608#L783-42 assume 1 == ~t10_pc~0; 75224#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 75225#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75820#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75953#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76970#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76654#L802-42 assume 1 == ~t11_pc~0; 75755#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75366#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75367#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75317#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 75318#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76494#L821-42 assume !(1 == ~t12_pc~0); 75859#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 75860#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75220#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75221#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 76200#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76190#L1339-3 assume !(1 == ~M_E~0); 76191#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76342#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76452#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75869#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 75870#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76463#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76959#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 76866#L1374-3 assume !(1 == ~T8_E~0); 75691#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 75692#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 75867#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 75868#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 76077#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 76873#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 76841#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 76842#L1414-3 assume !(1 == ~E_3~0); 76897#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 76656#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 75575#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 75576#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 76462#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 75503#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 75504#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 75620#L1454-3 assume !(1 == ~E_11~0); 76457#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 76458#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 76116#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 75413#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 75673#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 75674#L1829 assume !(0 == start_simulation_~tmp~3#1); 75395#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 75396#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 76196#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 76197#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 76476#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76477#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76097#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 75648#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 75649#L1810-2 [2022-02-21 04:23:29,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:29,812 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2022-02-21 04:23:29,812 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:29,812 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190748722] [2022-02-21 04:23:29,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:29,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:29,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:29,830 INFO L290 TraceCheckUtils]: 0: Hoare triple {80576#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {80576#true} is VALID [2022-02-21 04:23:29,831 INFO L290 TraceCheckUtils]: 1: Hoare triple {80576#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,831 INFO L290 TraceCheckUtils]: 2: Hoare triple {80578#(= ~t12_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,831 INFO L290 TraceCheckUtils]: 3: Hoare triple {80578#(= ~t12_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,831 INFO L290 TraceCheckUtils]: 4: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,832 INFO L290 TraceCheckUtils]: 5: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,832 INFO L290 TraceCheckUtils]: 6: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,832 INFO L290 TraceCheckUtils]: 7: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,832 INFO L290 TraceCheckUtils]: 8: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,833 INFO L290 TraceCheckUtils]: 9: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,833 INFO L290 TraceCheckUtils]: 10: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,833 INFO L290 TraceCheckUtils]: 11: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,833 INFO L290 TraceCheckUtils]: 12: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,834 INFO L290 TraceCheckUtils]: 13: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,834 INFO L290 TraceCheckUtils]: 14: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,834 INFO L290 TraceCheckUtils]: 15: Hoare triple {80578#(= ~t12_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {80578#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:29,834 INFO L290 TraceCheckUtils]: 16: Hoare triple {80578#(= ~t12_i~0 1)} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {80577#false} is VALID [2022-02-21 04:23:29,834 INFO L290 TraceCheckUtils]: 17: Hoare triple {80577#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {80577#false} is VALID [2022-02-21 04:23:29,835 INFO L290 TraceCheckUtils]: 18: Hoare triple {80577#false} assume !(0 == ~M_E~0); {80577#false} is VALID [2022-02-21 04:23:29,835 INFO L290 TraceCheckUtils]: 19: Hoare triple {80577#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {80577#false} is VALID [2022-02-21 04:23:29,835 INFO L290 TraceCheckUtils]: 20: Hoare triple {80577#false} assume !(0 == ~T2_E~0); {80577#false} is VALID [2022-02-21 04:23:29,835 INFO L290 TraceCheckUtils]: 21: Hoare triple {80577#false} assume !(0 == ~T3_E~0); {80577#false} is VALID [2022-02-21 04:23:29,835 INFO L290 TraceCheckUtils]: 22: Hoare triple {80577#false} assume !(0 == ~T4_E~0); {80577#false} is VALID [2022-02-21 04:23:29,835 INFO L290 TraceCheckUtils]: 23: Hoare triple {80577#false} assume !(0 == ~T5_E~0); {80577#false} is VALID [2022-02-21 04:23:29,835 INFO L290 TraceCheckUtils]: 24: Hoare triple {80577#false} assume !(0 == ~T6_E~0); {80577#false} is VALID [2022-02-21 04:23:29,835 INFO L290 TraceCheckUtils]: 25: Hoare triple {80577#false} assume !(0 == ~T7_E~0); {80577#false} is VALID [2022-02-21 04:23:29,835 INFO L290 TraceCheckUtils]: 26: Hoare triple {80577#false} assume !(0 == ~T8_E~0); {80577#false} is VALID [2022-02-21 04:23:29,836 INFO L290 TraceCheckUtils]: 27: Hoare triple {80577#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {80577#false} is VALID [2022-02-21 04:23:29,836 INFO L290 TraceCheckUtils]: 28: Hoare triple {80577#false} assume !(0 == ~T10_E~0); {80577#false} is VALID [2022-02-21 04:23:29,836 INFO L290 TraceCheckUtils]: 29: Hoare triple {80577#false} assume !(0 == ~T11_E~0); {80577#false} is VALID [2022-02-21 04:23:29,836 INFO L290 TraceCheckUtils]: 30: Hoare triple {80577#false} assume !(0 == ~T12_E~0); {80577#false} is VALID [2022-02-21 04:23:29,836 INFO L290 TraceCheckUtils]: 31: Hoare triple {80577#false} assume !(0 == ~E_M~0); {80577#false} is VALID [2022-02-21 04:23:29,836 INFO L290 TraceCheckUtils]: 32: Hoare triple {80577#false} assume !(0 == ~E_1~0); {80577#false} is VALID [2022-02-21 04:23:29,836 INFO L290 TraceCheckUtils]: 33: Hoare triple {80577#false} assume !(0 == ~E_2~0); {80577#false} is VALID [2022-02-21 04:23:29,836 INFO L290 TraceCheckUtils]: 34: Hoare triple {80577#false} assume !(0 == ~E_3~0); {80577#false} is VALID [2022-02-21 04:23:29,836 INFO L290 TraceCheckUtils]: 35: Hoare triple {80577#false} assume 0 == ~E_4~0;~E_4~0 := 1; {80577#false} is VALID [2022-02-21 04:23:29,837 INFO L290 TraceCheckUtils]: 36: Hoare triple {80577#false} assume !(0 == ~E_5~0); {80577#false} is VALID [2022-02-21 04:23:29,837 INFO L290 TraceCheckUtils]: 37: Hoare triple {80577#false} assume !(0 == ~E_6~0); {80577#false} is VALID [2022-02-21 04:23:29,837 INFO L290 TraceCheckUtils]: 38: Hoare triple {80577#false} assume !(0 == ~E_7~0); {80577#false} is VALID [2022-02-21 04:23:29,837 INFO L290 TraceCheckUtils]: 39: Hoare triple {80577#false} assume !(0 == ~E_8~0); {80577#false} is VALID [2022-02-21 04:23:29,837 INFO L290 TraceCheckUtils]: 40: Hoare triple {80577#false} assume !(0 == ~E_9~0); {80577#false} is VALID [2022-02-21 04:23:29,837 INFO L290 TraceCheckUtils]: 41: Hoare triple {80577#false} assume !(0 == ~E_10~0); {80577#false} is VALID [2022-02-21 04:23:29,837 INFO L290 TraceCheckUtils]: 42: Hoare triple {80577#false} assume !(0 == ~E_11~0); {80577#false} is VALID [2022-02-21 04:23:29,837 INFO L290 TraceCheckUtils]: 43: Hoare triple {80577#false} assume 0 == ~E_12~0;~E_12~0 := 1; {80577#false} is VALID [2022-02-21 04:23:29,838 INFO L290 TraceCheckUtils]: 44: Hoare triple {80577#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {80577#false} is VALID [2022-02-21 04:23:29,838 INFO L290 TraceCheckUtils]: 45: Hoare triple {80577#false} assume 1 == ~m_pc~0; {80577#false} is VALID [2022-02-21 04:23:29,838 INFO L290 TraceCheckUtils]: 46: Hoare triple {80577#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {80577#false} is VALID [2022-02-21 04:23:29,838 INFO L290 TraceCheckUtils]: 47: Hoare triple {80577#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {80577#false} is VALID [2022-02-21 04:23:29,838 INFO L290 TraceCheckUtils]: 48: Hoare triple {80577#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {80577#false} is VALID [2022-02-21 04:23:29,838 INFO L290 TraceCheckUtils]: 49: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp~1#1); {80577#false} is VALID [2022-02-21 04:23:29,838 INFO L290 TraceCheckUtils]: 50: Hoare triple {80577#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {80577#false} is VALID [2022-02-21 04:23:29,838 INFO L290 TraceCheckUtils]: 51: Hoare triple {80577#false} assume !(1 == ~t1_pc~0); {80577#false} is VALID [2022-02-21 04:23:29,838 INFO L290 TraceCheckUtils]: 52: Hoare triple {80577#false} is_transmit1_triggered_~__retres1~1#1 := 0; {80577#false} is VALID [2022-02-21 04:23:29,839 INFO L290 TraceCheckUtils]: 53: Hoare triple {80577#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {80577#false} is VALID [2022-02-21 04:23:29,839 INFO L290 TraceCheckUtils]: 54: Hoare triple {80577#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {80577#false} is VALID [2022-02-21 04:23:29,839 INFO L290 TraceCheckUtils]: 55: Hoare triple {80577#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {80577#false} is VALID [2022-02-21 04:23:29,839 INFO L290 TraceCheckUtils]: 56: Hoare triple {80577#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {80577#false} is VALID [2022-02-21 04:23:29,839 INFO L290 TraceCheckUtils]: 57: Hoare triple {80577#false} assume 1 == ~t2_pc~0; {80577#false} is VALID [2022-02-21 04:23:29,839 INFO L290 TraceCheckUtils]: 58: Hoare triple {80577#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {80577#false} is VALID [2022-02-21 04:23:29,839 INFO L290 TraceCheckUtils]: 59: Hoare triple {80577#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {80577#false} is VALID [2022-02-21 04:23:29,839 INFO L290 TraceCheckUtils]: 60: Hoare triple {80577#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {80577#false} is VALID [2022-02-21 04:23:29,839 INFO L290 TraceCheckUtils]: 61: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp___1~0#1); {80577#false} is VALID [2022-02-21 04:23:29,840 INFO L290 TraceCheckUtils]: 62: Hoare triple {80577#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {80577#false} is VALID [2022-02-21 04:23:29,840 INFO L290 TraceCheckUtils]: 63: Hoare triple {80577#false} assume !(1 == ~t3_pc~0); {80577#false} is VALID [2022-02-21 04:23:29,840 INFO L290 TraceCheckUtils]: 64: Hoare triple {80577#false} is_transmit3_triggered_~__retres1~3#1 := 0; {80577#false} is VALID [2022-02-21 04:23:29,840 INFO L290 TraceCheckUtils]: 65: Hoare triple {80577#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {80577#false} is VALID [2022-02-21 04:23:29,840 INFO L290 TraceCheckUtils]: 66: Hoare triple {80577#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {80577#false} is VALID [2022-02-21 04:23:29,840 INFO L290 TraceCheckUtils]: 67: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp___2~0#1); {80577#false} is VALID [2022-02-21 04:23:29,840 INFO L290 TraceCheckUtils]: 68: Hoare triple {80577#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {80577#false} is VALID [2022-02-21 04:23:29,840 INFO L290 TraceCheckUtils]: 69: Hoare triple {80577#false} assume 1 == ~t4_pc~0; {80577#false} is VALID [2022-02-21 04:23:29,840 INFO L290 TraceCheckUtils]: 70: Hoare triple {80577#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {80577#false} is VALID [2022-02-21 04:23:29,841 INFO L290 TraceCheckUtils]: 71: Hoare triple {80577#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {80577#false} is VALID [2022-02-21 04:23:29,841 INFO L290 TraceCheckUtils]: 72: Hoare triple {80577#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {80577#false} is VALID [2022-02-21 04:23:29,841 INFO L290 TraceCheckUtils]: 73: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp___3~0#1); {80577#false} is VALID [2022-02-21 04:23:29,841 INFO L290 TraceCheckUtils]: 74: Hoare triple {80577#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {80577#false} is VALID [2022-02-21 04:23:29,841 INFO L290 TraceCheckUtils]: 75: Hoare triple {80577#false} assume !(1 == ~t5_pc~0); {80577#false} is VALID [2022-02-21 04:23:29,841 INFO L290 TraceCheckUtils]: 76: Hoare triple {80577#false} is_transmit5_triggered_~__retres1~5#1 := 0; {80577#false} is VALID [2022-02-21 04:23:29,841 INFO L290 TraceCheckUtils]: 77: Hoare triple {80577#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {80577#false} is VALID [2022-02-21 04:23:29,841 INFO L290 TraceCheckUtils]: 78: Hoare triple {80577#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {80577#false} is VALID [2022-02-21 04:23:29,841 INFO L290 TraceCheckUtils]: 79: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp___4~0#1); {80577#false} is VALID [2022-02-21 04:23:29,842 INFO L290 TraceCheckUtils]: 80: Hoare triple {80577#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {80577#false} is VALID [2022-02-21 04:23:29,842 INFO L290 TraceCheckUtils]: 81: Hoare triple {80577#false} assume 1 == ~t6_pc~0; {80577#false} is VALID [2022-02-21 04:23:29,842 INFO L290 TraceCheckUtils]: 82: Hoare triple {80577#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {80577#false} is VALID [2022-02-21 04:23:29,842 INFO L290 TraceCheckUtils]: 83: Hoare triple {80577#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {80577#false} is VALID [2022-02-21 04:23:29,842 INFO L290 TraceCheckUtils]: 84: Hoare triple {80577#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {80577#false} is VALID [2022-02-21 04:23:29,842 INFO L290 TraceCheckUtils]: 85: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp___5~0#1); {80577#false} is VALID [2022-02-21 04:23:29,842 INFO L290 TraceCheckUtils]: 86: Hoare triple {80577#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {80577#false} is VALID [2022-02-21 04:23:29,842 INFO L290 TraceCheckUtils]: 87: Hoare triple {80577#false} assume 1 == ~t7_pc~0; {80577#false} is VALID [2022-02-21 04:23:29,842 INFO L290 TraceCheckUtils]: 88: Hoare triple {80577#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {80577#false} is VALID [2022-02-21 04:23:29,843 INFO L290 TraceCheckUtils]: 89: Hoare triple {80577#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {80577#false} is VALID [2022-02-21 04:23:29,843 INFO L290 TraceCheckUtils]: 90: Hoare triple {80577#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {80577#false} is VALID [2022-02-21 04:23:29,843 INFO L290 TraceCheckUtils]: 91: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp___6~0#1); {80577#false} is VALID [2022-02-21 04:23:29,843 INFO L290 TraceCheckUtils]: 92: Hoare triple {80577#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {80577#false} is VALID [2022-02-21 04:23:29,843 INFO L290 TraceCheckUtils]: 93: Hoare triple {80577#false} assume !(1 == ~t8_pc~0); {80577#false} is VALID [2022-02-21 04:23:29,843 INFO L290 TraceCheckUtils]: 94: Hoare triple {80577#false} is_transmit8_triggered_~__retres1~8#1 := 0; {80577#false} is VALID [2022-02-21 04:23:29,843 INFO L290 TraceCheckUtils]: 95: Hoare triple {80577#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {80577#false} is VALID [2022-02-21 04:23:29,843 INFO L290 TraceCheckUtils]: 96: Hoare triple {80577#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {80577#false} is VALID [2022-02-21 04:23:29,843 INFO L290 TraceCheckUtils]: 97: Hoare triple {80577#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {80577#false} is VALID [2022-02-21 04:23:29,844 INFO L290 TraceCheckUtils]: 98: Hoare triple {80577#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {80577#false} is VALID [2022-02-21 04:23:29,844 INFO L290 TraceCheckUtils]: 99: Hoare triple {80577#false} assume 1 == ~t9_pc~0; {80577#false} is VALID [2022-02-21 04:23:29,844 INFO L290 TraceCheckUtils]: 100: Hoare triple {80577#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {80577#false} is VALID [2022-02-21 04:23:29,844 INFO L290 TraceCheckUtils]: 101: Hoare triple {80577#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {80577#false} is VALID [2022-02-21 04:23:29,844 INFO L290 TraceCheckUtils]: 102: Hoare triple {80577#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {80577#false} is VALID [2022-02-21 04:23:29,844 INFO L290 TraceCheckUtils]: 103: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp___8~0#1); {80577#false} is VALID [2022-02-21 04:23:29,844 INFO L290 TraceCheckUtils]: 104: Hoare triple {80577#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {80577#false} is VALID [2022-02-21 04:23:29,844 INFO L290 TraceCheckUtils]: 105: Hoare triple {80577#false} assume !(1 == ~t10_pc~0); {80577#false} is VALID [2022-02-21 04:23:29,844 INFO L290 TraceCheckUtils]: 106: Hoare triple {80577#false} is_transmit10_triggered_~__retres1~10#1 := 0; {80577#false} is VALID [2022-02-21 04:23:29,845 INFO L290 TraceCheckUtils]: 107: Hoare triple {80577#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {80577#false} is VALID [2022-02-21 04:23:29,845 INFO L290 TraceCheckUtils]: 108: Hoare triple {80577#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {80577#false} is VALID [2022-02-21 04:23:29,845 INFO L290 TraceCheckUtils]: 109: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp___9~0#1); {80577#false} is VALID [2022-02-21 04:23:29,845 INFO L290 TraceCheckUtils]: 110: Hoare triple {80577#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {80577#false} is VALID [2022-02-21 04:23:29,845 INFO L290 TraceCheckUtils]: 111: Hoare triple {80577#false} assume 1 == ~t11_pc~0; {80577#false} is VALID [2022-02-21 04:23:29,845 INFO L290 TraceCheckUtils]: 112: Hoare triple {80577#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {80577#false} is VALID [2022-02-21 04:23:29,845 INFO L290 TraceCheckUtils]: 113: Hoare triple {80577#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {80577#false} is VALID [2022-02-21 04:23:29,845 INFO L290 TraceCheckUtils]: 114: Hoare triple {80577#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {80577#false} is VALID [2022-02-21 04:23:29,845 INFO L290 TraceCheckUtils]: 115: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp___10~0#1); {80577#false} is VALID [2022-02-21 04:23:29,846 INFO L290 TraceCheckUtils]: 116: Hoare triple {80577#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {80577#false} is VALID [2022-02-21 04:23:29,846 INFO L290 TraceCheckUtils]: 117: Hoare triple {80577#false} assume !(1 == ~t12_pc~0); {80577#false} is VALID [2022-02-21 04:23:29,846 INFO L290 TraceCheckUtils]: 118: Hoare triple {80577#false} is_transmit12_triggered_~__retres1~12#1 := 0; {80577#false} is VALID [2022-02-21 04:23:29,846 INFO L290 TraceCheckUtils]: 119: Hoare triple {80577#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {80577#false} is VALID [2022-02-21 04:23:29,846 INFO L290 TraceCheckUtils]: 120: Hoare triple {80577#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {80577#false} is VALID [2022-02-21 04:23:29,846 INFO L290 TraceCheckUtils]: 121: Hoare triple {80577#false} assume !(0 != activate_threads_~tmp___11~0#1); {80577#false} is VALID [2022-02-21 04:23:29,846 INFO L290 TraceCheckUtils]: 122: Hoare triple {80577#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {80577#false} is VALID [2022-02-21 04:23:29,846 INFO L290 TraceCheckUtils]: 123: Hoare triple {80577#false} assume !(1 == ~M_E~0); {80577#false} is VALID [2022-02-21 04:23:29,846 INFO L290 TraceCheckUtils]: 124: Hoare triple {80577#false} assume !(1 == ~T1_E~0); {80577#false} is VALID [2022-02-21 04:23:29,847 INFO L290 TraceCheckUtils]: 125: Hoare triple {80577#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {80577#false} is VALID [2022-02-21 04:23:29,847 INFO L290 TraceCheckUtils]: 126: Hoare triple {80577#false} assume !(1 == ~T3_E~0); {80577#false} is VALID [2022-02-21 04:23:29,847 INFO L290 TraceCheckUtils]: 127: Hoare triple {80577#false} assume !(1 == ~T4_E~0); {80577#false} is VALID [2022-02-21 04:23:29,847 INFO L290 TraceCheckUtils]: 128: Hoare triple {80577#false} assume !(1 == ~T5_E~0); {80577#false} is VALID [2022-02-21 04:23:29,847 INFO L290 TraceCheckUtils]: 129: Hoare triple {80577#false} assume !(1 == ~T6_E~0); {80577#false} is VALID [2022-02-21 04:23:29,847 INFO L290 TraceCheckUtils]: 130: Hoare triple {80577#false} assume !(1 == ~T7_E~0); {80577#false} is VALID [2022-02-21 04:23:29,847 INFO L290 TraceCheckUtils]: 131: Hoare triple {80577#false} assume !(1 == ~T8_E~0); {80577#false} is VALID [2022-02-21 04:23:29,847 INFO L290 TraceCheckUtils]: 132: Hoare triple {80577#false} assume !(1 == ~T9_E~0); {80577#false} is VALID [2022-02-21 04:23:29,847 INFO L290 TraceCheckUtils]: 133: Hoare triple {80577#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {80577#false} is VALID [2022-02-21 04:23:29,848 INFO L290 TraceCheckUtils]: 134: Hoare triple {80577#false} assume !(1 == ~T11_E~0); {80577#false} is VALID [2022-02-21 04:23:29,848 INFO L290 TraceCheckUtils]: 135: Hoare triple {80577#false} assume !(1 == ~T12_E~0); {80577#false} is VALID [2022-02-21 04:23:29,848 INFO L290 TraceCheckUtils]: 136: Hoare triple {80577#false} assume !(1 == ~E_M~0); {80577#false} is VALID [2022-02-21 04:23:29,848 INFO L290 TraceCheckUtils]: 137: Hoare triple {80577#false} assume !(1 == ~E_1~0); {80577#false} is VALID [2022-02-21 04:23:29,848 INFO L290 TraceCheckUtils]: 138: Hoare triple {80577#false} assume !(1 == ~E_2~0); {80577#false} is VALID [2022-02-21 04:23:29,848 INFO L290 TraceCheckUtils]: 139: Hoare triple {80577#false} assume !(1 == ~E_3~0); {80577#false} is VALID [2022-02-21 04:23:29,848 INFO L290 TraceCheckUtils]: 140: Hoare triple {80577#false} assume !(1 == ~E_4~0); {80577#false} is VALID [2022-02-21 04:23:29,848 INFO L290 TraceCheckUtils]: 141: Hoare triple {80577#false} assume 1 == ~E_5~0;~E_5~0 := 2; {80577#false} is VALID [2022-02-21 04:23:29,849 INFO L290 TraceCheckUtils]: 142: Hoare triple {80577#false} assume !(1 == ~E_6~0); {80577#false} is VALID [2022-02-21 04:23:29,849 INFO L290 TraceCheckUtils]: 143: Hoare triple {80577#false} assume !(1 == ~E_7~0); {80577#false} is VALID [2022-02-21 04:23:29,849 INFO L290 TraceCheckUtils]: 144: Hoare triple {80577#false} assume !(1 == ~E_8~0); {80577#false} is VALID [2022-02-21 04:23:29,849 INFO L290 TraceCheckUtils]: 145: Hoare triple {80577#false} assume !(1 == ~E_9~0); {80577#false} is VALID [2022-02-21 04:23:29,849 INFO L290 TraceCheckUtils]: 146: Hoare triple {80577#false} assume !(1 == ~E_10~0); {80577#false} is VALID [2022-02-21 04:23:29,849 INFO L290 TraceCheckUtils]: 147: Hoare triple {80577#false} assume !(1 == ~E_11~0); {80577#false} is VALID [2022-02-21 04:23:29,849 INFO L290 TraceCheckUtils]: 148: Hoare triple {80577#false} assume !(1 == ~E_12~0); {80577#false} is VALID [2022-02-21 04:23:29,849 INFO L290 TraceCheckUtils]: 149: Hoare triple {80577#false} assume { :end_inline_reset_delta_events } true; {80577#false} is VALID [2022-02-21 04:23:29,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:29,850 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:29,850 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190748722] [2022-02-21 04:23:29,850 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190748722] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:29,850 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:29,850 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:29,850 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592536634] [2022-02-21 04:23:29,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:29,851 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:29,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:29,851 INFO L85 PathProgramCache]: Analyzing trace with hash -1716231594, now seen corresponding path program 1 times [2022-02-21 04:23:29,851 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:29,851 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608283078] [2022-02-21 04:23:29,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:29,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:29,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:29,874 INFO L290 TraceCheckUtils]: 0: Hoare triple {80579#true} assume !false; {80579#true} is VALID [2022-02-21 04:23:29,874 INFO L290 TraceCheckUtils]: 1: Hoare triple {80579#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {80579#true} is VALID [2022-02-21 04:23:29,874 INFO L290 TraceCheckUtils]: 2: Hoare triple {80579#true} assume !false; {80579#true} is VALID [2022-02-21 04:23:29,874 INFO L290 TraceCheckUtils]: 3: Hoare triple {80579#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {80579#true} is VALID [2022-02-21 04:23:29,874 INFO L290 TraceCheckUtils]: 4: Hoare triple {80579#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {80579#true} is VALID [2022-02-21 04:23:29,874 INFO L290 TraceCheckUtils]: 5: Hoare triple {80579#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {80579#true} is VALID [2022-02-21 04:23:29,875 INFO L290 TraceCheckUtils]: 6: Hoare triple {80579#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {80579#true} is VALID [2022-02-21 04:23:29,875 INFO L290 TraceCheckUtils]: 7: Hoare triple {80579#true} assume !(0 != eval_~tmp~0#1); {80579#true} is VALID [2022-02-21 04:23:29,875 INFO L290 TraceCheckUtils]: 8: Hoare triple {80579#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {80579#true} is VALID [2022-02-21 04:23:29,875 INFO L290 TraceCheckUtils]: 9: Hoare triple {80579#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {80579#true} is VALID [2022-02-21 04:23:29,875 INFO L290 TraceCheckUtils]: 10: Hoare triple {80579#true} assume 0 == ~M_E~0;~M_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,876 INFO L290 TraceCheckUtils]: 11: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,876 INFO L290 TraceCheckUtils]: 12: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,876 INFO L290 TraceCheckUtils]: 13: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,876 INFO L290 TraceCheckUtils]: 14: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,877 INFO L290 TraceCheckUtils]: 15: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,877 INFO L290 TraceCheckUtils]: 16: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,877 INFO L290 TraceCheckUtils]: 17: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,877 INFO L290 TraceCheckUtils]: 18: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,878 INFO L290 TraceCheckUtils]: 19: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,878 INFO L290 TraceCheckUtils]: 20: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,878 INFO L290 TraceCheckUtils]: 21: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,878 INFO L290 TraceCheckUtils]: 22: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,879 INFO L290 TraceCheckUtils]: 23: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,879 INFO L290 TraceCheckUtils]: 24: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,879 INFO L290 TraceCheckUtils]: 25: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,879 INFO L290 TraceCheckUtils]: 26: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,880 INFO L290 TraceCheckUtils]: 27: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,880 INFO L290 TraceCheckUtils]: 28: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,880 INFO L290 TraceCheckUtils]: 29: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,880 INFO L290 TraceCheckUtils]: 30: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,881 INFO L290 TraceCheckUtils]: 31: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,881 INFO L290 TraceCheckUtils]: 32: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,881 INFO L290 TraceCheckUtils]: 33: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,881 INFO L290 TraceCheckUtils]: 34: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,882 INFO L290 TraceCheckUtils]: 35: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,882 INFO L290 TraceCheckUtils]: 36: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,882 INFO L290 TraceCheckUtils]: 37: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,882 INFO L290 TraceCheckUtils]: 38: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,883 INFO L290 TraceCheckUtils]: 39: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,883 INFO L290 TraceCheckUtils]: 40: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,883 INFO L290 TraceCheckUtils]: 41: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,883 INFO L290 TraceCheckUtils]: 42: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,884 INFO L290 TraceCheckUtils]: 43: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,884 INFO L290 TraceCheckUtils]: 44: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,884 INFO L290 TraceCheckUtils]: 45: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,884 INFO L290 TraceCheckUtils]: 46: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,885 INFO L290 TraceCheckUtils]: 47: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,885 INFO L290 TraceCheckUtils]: 48: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,885 INFO L290 TraceCheckUtils]: 49: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,885 INFO L290 TraceCheckUtils]: 50: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,886 INFO L290 TraceCheckUtils]: 51: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,886 INFO L290 TraceCheckUtils]: 52: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,886 INFO L290 TraceCheckUtils]: 53: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,886 INFO L290 TraceCheckUtils]: 54: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,887 INFO L290 TraceCheckUtils]: 55: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,887 INFO L290 TraceCheckUtils]: 56: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,887 INFO L290 TraceCheckUtils]: 57: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,887 INFO L290 TraceCheckUtils]: 58: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,888 INFO L290 TraceCheckUtils]: 59: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,888 INFO L290 TraceCheckUtils]: 60: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,888 INFO L290 TraceCheckUtils]: 61: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,888 INFO L290 TraceCheckUtils]: 62: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,889 INFO L290 TraceCheckUtils]: 63: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,889 INFO L290 TraceCheckUtils]: 64: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,889 INFO L290 TraceCheckUtils]: 65: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,889 INFO L290 TraceCheckUtils]: 66: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,890 INFO L290 TraceCheckUtils]: 67: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,890 INFO L290 TraceCheckUtils]: 68: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,890 INFO L290 TraceCheckUtils]: 69: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,890 INFO L290 TraceCheckUtils]: 70: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,891 INFO L290 TraceCheckUtils]: 71: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,891 INFO L290 TraceCheckUtils]: 72: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,891 INFO L290 TraceCheckUtils]: 73: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,891 INFO L290 TraceCheckUtils]: 74: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,892 INFO L290 TraceCheckUtils]: 75: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,892 INFO L290 TraceCheckUtils]: 76: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,892 INFO L290 TraceCheckUtils]: 77: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,892 INFO L290 TraceCheckUtils]: 78: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,893 INFO L290 TraceCheckUtils]: 79: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,893 INFO L290 TraceCheckUtils]: 80: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,893 INFO L290 TraceCheckUtils]: 81: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,893 INFO L290 TraceCheckUtils]: 82: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,894 INFO L290 TraceCheckUtils]: 83: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,894 INFO L290 TraceCheckUtils]: 84: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,894 INFO L290 TraceCheckUtils]: 85: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,894 INFO L290 TraceCheckUtils]: 86: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,895 INFO L290 TraceCheckUtils]: 87: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,895 INFO L290 TraceCheckUtils]: 88: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,895 INFO L290 TraceCheckUtils]: 89: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,895 INFO L290 TraceCheckUtils]: 90: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,896 INFO L290 TraceCheckUtils]: 91: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,896 INFO L290 TraceCheckUtils]: 92: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,896 INFO L290 TraceCheckUtils]: 93: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,896 INFO L290 TraceCheckUtils]: 94: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,897 INFO L290 TraceCheckUtils]: 95: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,897 INFO L290 TraceCheckUtils]: 96: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,897 INFO L290 TraceCheckUtils]: 97: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,897 INFO L290 TraceCheckUtils]: 98: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,898 INFO L290 TraceCheckUtils]: 99: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,898 INFO L290 TraceCheckUtils]: 100: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,898 INFO L290 TraceCheckUtils]: 101: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,898 INFO L290 TraceCheckUtils]: 102: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,899 INFO L290 TraceCheckUtils]: 103: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,899 INFO L290 TraceCheckUtils]: 104: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,899 INFO L290 TraceCheckUtils]: 105: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,899 INFO L290 TraceCheckUtils]: 106: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,900 INFO L290 TraceCheckUtils]: 107: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,900 INFO L290 TraceCheckUtils]: 108: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,900 INFO L290 TraceCheckUtils]: 109: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,900 INFO L290 TraceCheckUtils]: 110: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,901 INFO L290 TraceCheckUtils]: 111: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,901 INFO L290 TraceCheckUtils]: 112: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,901 INFO L290 TraceCheckUtils]: 113: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,901 INFO L290 TraceCheckUtils]: 114: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {80581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:29,902 INFO L290 TraceCheckUtils]: 115: Hoare triple {80581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {80580#false} is VALID [2022-02-21 04:23:29,902 INFO L290 TraceCheckUtils]: 116: Hoare triple {80580#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,902 INFO L290 TraceCheckUtils]: 117: Hoare triple {80580#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,902 INFO L290 TraceCheckUtils]: 118: Hoare triple {80580#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,902 INFO L290 TraceCheckUtils]: 119: Hoare triple {80580#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,902 INFO L290 TraceCheckUtils]: 120: Hoare triple {80580#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,902 INFO L290 TraceCheckUtils]: 121: Hoare triple {80580#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,903 INFO L290 TraceCheckUtils]: 122: Hoare triple {80580#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,903 INFO L290 TraceCheckUtils]: 123: Hoare triple {80580#false} assume !(1 == ~T8_E~0); {80580#false} is VALID [2022-02-21 04:23:29,903 INFO L290 TraceCheckUtils]: 124: Hoare triple {80580#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,903 INFO L290 TraceCheckUtils]: 125: Hoare triple {80580#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,903 INFO L290 TraceCheckUtils]: 126: Hoare triple {80580#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,903 INFO L290 TraceCheckUtils]: 127: Hoare triple {80580#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,903 INFO L290 TraceCheckUtils]: 128: Hoare triple {80580#false} assume 1 == ~E_M~0;~E_M~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,903 INFO L290 TraceCheckUtils]: 129: Hoare triple {80580#false} assume 1 == ~E_1~0;~E_1~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,903 INFO L290 TraceCheckUtils]: 130: Hoare triple {80580#false} assume 1 == ~E_2~0;~E_2~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,904 INFO L290 TraceCheckUtils]: 131: Hoare triple {80580#false} assume !(1 == ~E_3~0); {80580#false} is VALID [2022-02-21 04:23:29,904 INFO L290 TraceCheckUtils]: 132: Hoare triple {80580#false} assume 1 == ~E_4~0;~E_4~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,904 INFO L290 TraceCheckUtils]: 133: Hoare triple {80580#false} assume 1 == ~E_5~0;~E_5~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,904 INFO L290 TraceCheckUtils]: 134: Hoare triple {80580#false} assume 1 == ~E_6~0;~E_6~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,904 INFO L290 TraceCheckUtils]: 135: Hoare triple {80580#false} assume 1 == ~E_7~0;~E_7~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,904 INFO L290 TraceCheckUtils]: 136: Hoare triple {80580#false} assume 1 == ~E_8~0;~E_8~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,904 INFO L290 TraceCheckUtils]: 137: Hoare triple {80580#false} assume 1 == ~E_9~0;~E_9~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,904 INFO L290 TraceCheckUtils]: 138: Hoare triple {80580#false} assume 1 == ~E_10~0;~E_10~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,904 INFO L290 TraceCheckUtils]: 139: Hoare triple {80580#false} assume !(1 == ~E_11~0); {80580#false} is VALID [2022-02-21 04:23:29,905 INFO L290 TraceCheckUtils]: 140: Hoare triple {80580#false} assume 1 == ~E_12~0;~E_12~0 := 2; {80580#false} is VALID [2022-02-21 04:23:29,905 INFO L290 TraceCheckUtils]: 141: Hoare triple {80580#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {80580#false} is VALID [2022-02-21 04:23:29,905 INFO L290 TraceCheckUtils]: 142: Hoare triple {80580#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {80580#false} is VALID [2022-02-21 04:23:29,905 INFO L290 TraceCheckUtils]: 143: Hoare triple {80580#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {80580#false} is VALID [2022-02-21 04:23:29,905 INFO L290 TraceCheckUtils]: 144: Hoare triple {80580#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {80580#false} is VALID [2022-02-21 04:23:29,905 INFO L290 TraceCheckUtils]: 145: Hoare triple {80580#false} assume !(0 == start_simulation_~tmp~3#1); {80580#false} is VALID [2022-02-21 04:23:29,905 INFO L290 TraceCheckUtils]: 146: Hoare triple {80580#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {80580#false} is VALID [2022-02-21 04:23:29,905 INFO L290 TraceCheckUtils]: 147: Hoare triple {80580#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {80580#false} is VALID [2022-02-21 04:23:29,905 INFO L290 TraceCheckUtils]: 148: Hoare triple {80580#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {80580#false} is VALID [2022-02-21 04:23:29,906 INFO L290 TraceCheckUtils]: 149: Hoare triple {80580#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {80580#false} is VALID [2022-02-21 04:23:29,906 INFO L290 TraceCheckUtils]: 150: Hoare triple {80580#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {80580#false} is VALID [2022-02-21 04:23:29,906 INFO L290 TraceCheckUtils]: 151: Hoare triple {80580#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {80580#false} is VALID [2022-02-21 04:23:29,906 INFO L290 TraceCheckUtils]: 152: Hoare triple {80580#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {80580#false} is VALID [2022-02-21 04:23:29,906 INFO L290 TraceCheckUtils]: 153: Hoare triple {80580#false} assume !(0 != start_simulation_~tmp___0~1#1); {80580#false} is VALID [2022-02-21 04:23:29,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:29,907 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:29,907 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1608283078] [2022-02-21 04:23:29,907 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1608283078] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:29,907 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:29,907 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:29,907 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768004173] [2022-02-21 04:23:29,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:29,908 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:29,908 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:29,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:29,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:29,908 INFO L87 Difference]: Start difference. First operand 1788 states and 2641 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:31,034 INFO L93 Difference]: Finished difference Result 1788 states and 2640 transitions. [2022-02-21 04:23:31,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:31,034 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,111 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:31,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2640 transitions. [2022-02-21 04:23:31,186 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:31,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2640 transitions. [2022-02-21 04:23:31,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:31,266 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:31,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2640 transitions. [2022-02-21 04:23:31,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:31,267 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2022-02-21 04:23:31,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2640 transitions. [2022-02-21 04:23:31,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:31,279 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:31,280 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2640 transitions. Second operand has 1788 states, 1788 states have (on average 1.476510067114094) internal successors, (2640), 1787 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,281 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2640 transitions. Second operand has 1788 states, 1788 states have (on average 1.476510067114094) internal successors, (2640), 1787 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,282 INFO L87 Difference]: Start difference. First operand 1788 states and 2640 transitions. Second operand has 1788 states, 1788 states have (on average 1.476510067114094) internal successors, (2640), 1787 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:31,348 INFO L93 Difference]: Finished difference Result 1788 states and 2640 transitions. [2022-02-21 04:23:31,349 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2640 transitions. [2022-02-21 04:23:31,350 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:31,350 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:31,352 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.476510067114094) internal successors, (2640), 1787 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2640 transitions. [2022-02-21 04:23:31,353 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.476510067114094) internal successors, (2640), 1787 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2640 transitions. [2022-02-21 04:23:31,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:31,418 INFO L93 Difference]: Finished difference Result 1788 states and 2640 transitions. [2022-02-21 04:23:31,418 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2640 transitions. [2022-02-21 04:23:31,420 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:31,420 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:31,420 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:31,420 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:31,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.476510067114094) internal successors, (2640), 1787 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2640 transitions. [2022-02-21 04:23:31,485 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2022-02-21 04:23:31,485 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2022-02-21 04:23:31,485 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:23:31,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2640 transitions. [2022-02-21 04:23:31,488 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:31,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:31,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:31,489 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:31,489 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:31,489 INFO L791 eck$LassoCheckResult]: Stem: 83159#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 83160#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 82680#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82681#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82735#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 84074#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83168#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82971#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82370#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82371#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83593#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83704#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 84140#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84141#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 83099#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 83100#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 83622#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 83541#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 83134#L1201 assume !(0 == ~M_E~0); 83135#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83981#L1206-1 assume !(0 == ~T2_E~0); 83967#L1211-1 assume !(0 == ~T3_E~0); 83968#L1216-1 assume !(0 == ~T4_E~0); 82956#L1221-1 assume !(0 == ~T5_E~0); 82957#L1226-1 assume !(0 == ~T6_E~0); 82595#L1231-1 assume !(0 == ~T7_E~0); 82596#L1236-1 assume !(0 == ~T8_E~0); 84004#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 82992#L1246-1 assume !(0 == ~T10_E~0); 82993#L1251-1 assume !(0 == ~T11_E~0); 83132#L1256-1 assume !(0 == ~T12_E~0); 82383#L1261-1 assume !(0 == ~E_M~0); 82384#L1266-1 assume !(0 == ~E_1~0); 84126#L1271-1 assume !(0 == ~E_2~0); 83688#L1276-1 assume !(0 == ~E_3~0); 83689#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 83636#L1286-1 assume !(0 == ~E_5~0); 82846#L1291-1 assume !(0 == ~E_6~0); 82847#L1296-1 assume !(0 == ~E_7~0); 83422#L1301-1 assume !(0 == ~E_8~0); 83423#L1306-1 assume !(0 == ~E_9~0); 83903#L1311-1 assume !(0 == ~E_10~0); 82797#L1316-1 assume !(0 == ~E_11~0); 82798#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 83440#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83441#L593 assume 1 == ~m_pc~0; 83585#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 82687#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84113#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83647#L1492 assume !(0 != activate_threads_~tmp~1#1); 83648#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83939#L612 assume !(1 == ~t1_pc~0); 83940#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84069#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83069#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82691#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82692#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83111#L631 assume 1 == ~t2_pc~0; 83046#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 82468#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82469#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83305#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 83306#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82764#L650 assume !(1 == ~t3_pc~0); 82765#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83465#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82688#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82421#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 82422#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83614#L669 assume 1 == ~t4_pc~0; 83615#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 83973#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83098#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82630#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 82631#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82855#L688 assume !(1 == ~t5_pc~0); 82646#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 82647#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83565#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 83499#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 83500#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83632#L707 assume 1 == ~t6_pc~0; 84038#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 83275#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83276#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84036#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 83571#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83133#L726 assume 1 == ~t7_pc~0; 83034#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 82731#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 83772#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84046#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 82500#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82501#L745 assume !(1 == ~t8_pc~0); 82948#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 82967#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83805#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 83353#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 83354#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83864#L764 assume 1 == ~t9_pc~0; 83131#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82973#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83650#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 84097#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 82520#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 82521#L783 assume !(1 == ~t10_pc~0); 82582#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 82583#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82624#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82625#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 83087#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 83975#L802 assume 1 == ~t11_pc~0; 83957#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 82465#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 82466#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 82958#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 82959#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 83068#L821 assume !(1 == ~t12_pc~0); 83319#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 83415#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 82472#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 82473#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 84013#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83659#L1339 assume !(1 == ~M_E~0); 83660#L1339-2 assume !(1 == ~T1_E~0); 84048#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84049#L1349-1 assume !(1 == ~T3_E~0); 83434#L1354-1 assume !(1 == ~T4_E~0); 83435#L1359-1 assume !(1 == ~T5_E~0); 83835#L1364-1 assume !(1 == ~T6_E~0); 82898#L1369-1 assume !(1 == ~T7_E~0); 82899#L1374-1 assume !(1 == ~T8_E~0); 83436#L1379-1 assume !(1 == ~T9_E~0); 83437#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83536#L1389-1 assume !(1 == ~T11_E~0); 84007#L1394-1 assume !(1 == ~T12_E~0); 84008#L1399-1 assume !(1 == ~E_M~0); 84098#L1404-1 assume !(1 == ~E_1~0); 82997#L1409-1 assume !(1 == ~E_2~0); 82998#L1414-1 assume !(1 == ~E_3~0); 83724#L1419-1 assume !(1 == ~E_4~0); 82638#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 82639#L1429-1 assume !(1 == ~E_6~0); 83449#L1434-1 assume !(1 == ~E_7~0); 84028#L1439-1 assume !(1 == ~E_8~0); 82676#L1444-1 assume !(1 == ~E_9~0); 82677#L1449-1 assume !(1 == ~E_10~0); 83051#L1454-1 assume !(1 == ~E_11~0); 83052#L1459-1 assume !(1 == ~E_12~0); 83570#L1464-1 assume { :end_inline_reset_delta_events } true; 82810#L1810-2 [2022-02-21 04:23:31,489 INFO L793 eck$LassoCheckResult]: Loop: 82810#L1810-2 assume !false; 83254#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83170#L1176 assume !false; 83732#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83302#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82508#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83058#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 83059#L1003 assume !(0 != eval_~tmp~0#1); 82700#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82701#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83891#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 83674#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83675#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 83568#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82759#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82760#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 83226#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 82830#L1231-3 assume !(0 == ~T7_E~0); 82831#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 83079#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 84059#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 83960#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 83665#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 82776#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 82777#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 82822#L1271-3 assume !(0 == ~E_2~0); 82823#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 83199#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 83200#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 83722#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 83723#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 84137#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 84094#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 83311#L1311-3 assume !(0 == ~E_10~0); 82702#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 82703#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 82778#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83414#L593-42 assume 1 == ~m_pc~0; 83808#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 83573#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84122#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84123#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 82601#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82602#L612-42 assume !(1 == ~t1_pc~0); 83523#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 83916#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84037#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82689#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82690#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83385#L631-42 assume 1 == ~t2_pc~0; 82457#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 82458#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83374#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83250#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 83251#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82851#L650-42 assume 1 == ~t3_pc~0; 82416#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 82417#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84065#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83044#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 83045#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84029#L669-42 assume 1 == ~t4_pc~0; 83328#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82412#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83840#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83730#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 83627#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83628#L688-42 assume 1 == ~t5_pc~0; 83719#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83920#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82554#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82555#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82629#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82443#L707-42 assume 1 == ~t6_pc~0; 82445#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 84103#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83845#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 83846#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 83595#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83596#L726-42 assume 1 == ~t7_pc~0; 83873#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83899#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 83900#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 83314#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 83315#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83418#L745-42 assume !(1 == ~t8_pc~0); 83455#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 83456#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82782#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82429#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82430#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83155#L764-42 assume 1 == ~t9_pc~0; 83289#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 83644#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83645#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 82715#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 82716#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 82769#L783-42 assume 1 == ~t10_pc~0; 82385#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 82386#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82981#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 83114#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84131#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 83815#L802-42 assume !(1 == ~t11_pc~0); 82915#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 82527#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 82528#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 82478#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 82479#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 83655#L821-42 assume 1 == ~t12_pc~0; 83656#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 83021#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 82381#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 82382#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 83361#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83348#L1339-3 assume !(1 == ~M_E~0); 83349#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 83503#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83613#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83030#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83031#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 83624#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84120#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 84027#L1374-3 assume !(1 == ~T8_E~0); 82852#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 82853#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83028#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 83029#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 83238#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 84034#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 84002#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 84003#L1414-3 assume !(1 == ~E_3~0); 84058#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 83817#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82736#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 82737#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 83623#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 82664#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 82665#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 82781#L1454-3 assume !(1 == ~E_11~0); 83618#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 83619#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83277#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82574#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82834#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 82835#L1829 assume !(0 == start_simulation_~tmp~3#1); 82556#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 82557#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83357#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83358#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 83637#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 83638#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83258#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 82809#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 82810#L1810-2 [2022-02-21 04:23:31,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:31,490 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2022-02-21 04:23:31,490 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:31,490 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430097406] [2022-02-21 04:23:31,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:31,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:31,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:31,518 INFO L290 TraceCheckUtils]: 0: Hoare triple {87737#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,519 INFO L290 TraceCheckUtils]: 1: Hoare triple {87739#(<= 2 ~T1_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,519 INFO L290 TraceCheckUtils]: 2: Hoare triple {87739#(<= 2 ~T1_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,519 INFO L290 TraceCheckUtils]: 3: Hoare triple {87739#(<= 2 ~T1_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,520 INFO L290 TraceCheckUtils]: 4: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,520 INFO L290 TraceCheckUtils]: 5: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,520 INFO L290 TraceCheckUtils]: 6: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,521 INFO L290 TraceCheckUtils]: 7: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,521 INFO L290 TraceCheckUtils]: 8: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,521 INFO L290 TraceCheckUtils]: 9: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,522 INFO L290 TraceCheckUtils]: 10: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,522 INFO L290 TraceCheckUtils]: 11: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,522 INFO L290 TraceCheckUtils]: 12: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,522 INFO L290 TraceCheckUtils]: 13: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,523 INFO L290 TraceCheckUtils]: 14: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,523 INFO L290 TraceCheckUtils]: 15: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,523 INFO L290 TraceCheckUtils]: 16: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,524 INFO L290 TraceCheckUtils]: 17: Hoare triple {87739#(<= 2 ~T1_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,524 INFO L290 TraceCheckUtils]: 18: Hoare triple {87739#(<= 2 ~T1_E~0)} assume !(0 == ~M_E~0); {87739#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:31,524 INFO L290 TraceCheckUtils]: 19: Hoare triple {87739#(<= 2 ~T1_E~0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {87738#false} is VALID [2022-02-21 04:23:31,524 INFO L290 TraceCheckUtils]: 20: Hoare triple {87738#false} assume !(0 == ~T2_E~0); {87738#false} is VALID [2022-02-21 04:23:31,525 INFO L290 TraceCheckUtils]: 21: Hoare triple {87738#false} assume !(0 == ~T3_E~0); {87738#false} is VALID [2022-02-21 04:23:31,525 INFO L290 TraceCheckUtils]: 22: Hoare triple {87738#false} assume !(0 == ~T4_E~0); {87738#false} is VALID [2022-02-21 04:23:31,525 INFO L290 TraceCheckUtils]: 23: Hoare triple {87738#false} assume !(0 == ~T5_E~0); {87738#false} is VALID [2022-02-21 04:23:31,525 INFO L290 TraceCheckUtils]: 24: Hoare triple {87738#false} assume !(0 == ~T6_E~0); {87738#false} is VALID [2022-02-21 04:23:31,525 INFO L290 TraceCheckUtils]: 25: Hoare triple {87738#false} assume !(0 == ~T7_E~0); {87738#false} is VALID [2022-02-21 04:23:31,525 INFO L290 TraceCheckUtils]: 26: Hoare triple {87738#false} assume !(0 == ~T8_E~0); {87738#false} is VALID [2022-02-21 04:23:31,525 INFO L290 TraceCheckUtils]: 27: Hoare triple {87738#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {87738#false} is VALID [2022-02-21 04:23:31,525 INFO L290 TraceCheckUtils]: 28: Hoare triple {87738#false} assume !(0 == ~T10_E~0); {87738#false} is VALID [2022-02-21 04:23:31,526 INFO L290 TraceCheckUtils]: 29: Hoare triple {87738#false} assume !(0 == ~T11_E~0); {87738#false} is VALID [2022-02-21 04:23:31,526 INFO L290 TraceCheckUtils]: 30: Hoare triple {87738#false} assume !(0 == ~T12_E~0); {87738#false} is VALID [2022-02-21 04:23:31,526 INFO L290 TraceCheckUtils]: 31: Hoare triple {87738#false} assume !(0 == ~E_M~0); {87738#false} is VALID [2022-02-21 04:23:31,526 INFO L290 TraceCheckUtils]: 32: Hoare triple {87738#false} assume !(0 == ~E_1~0); {87738#false} is VALID [2022-02-21 04:23:31,526 INFO L290 TraceCheckUtils]: 33: Hoare triple {87738#false} assume !(0 == ~E_2~0); {87738#false} is VALID [2022-02-21 04:23:31,526 INFO L290 TraceCheckUtils]: 34: Hoare triple {87738#false} assume !(0 == ~E_3~0); {87738#false} is VALID [2022-02-21 04:23:31,526 INFO L290 TraceCheckUtils]: 35: Hoare triple {87738#false} assume 0 == ~E_4~0;~E_4~0 := 1; {87738#false} is VALID [2022-02-21 04:23:31,527 INFO L290 TraceCheckUtils]: 36: Hoare triple {87738#false} assume !(0 == ~E_5~0); {87738#false} is VALID [2022-02-21 04:23:31,527 INFO L290 TraceCheckUtils]: 37: Hoare triple {87738#false} assume !(0 == ~E_6~0); {87738#false} is VALID [2022-02-21 04:23:31,527 INFO L290 TraceCheckUtils]: 38: Hoare triple {87738#false} assume !(0 == ~E_7~0); {87738#false} is VALID [2022-02-21 04:23:31,527 INFO L290 TraceCheckUtils]: 39: Hoare triple {87738#false} assume !(0 == ~E_8~0); {87738#false} is VALID [2022-02-21 04:23:31,527 INFO L290 TraceCheckUtils]: 40: Hoare triple {87738#false} assume !(0 == ~E_9~0); {87738#false} is VALID [2022-02-21 04:23:31,527 INFO L290 TraceCheckUtils]: 41: Hoare triple {87738#false} assume !(0 == ~E_10~0); {87738#false} is VALID [2022-02-21 04:23:31,527 INFO L290 TraceCheckUtils]: 42: Hoare triple {87738#false} assume !(0 == ~E_11~0); {87738#false} is VALID [2022-02-21 04:23:31,527 INFO L290 TraceCheckUtils]: 43: Hoare triple {87738#false} assume 0 == ~E_12~0;~E_12~0 := 1; {87738#false} is VALID [2022-02-21 04:23:31,528 INFO L290 TraceCheckUtils]: 44: Hoare triple {87738#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {87738#false} is VALID [2022-02-21 04:23:31,528 INFO L290 TraceCheckUtils]: 45: Hoare triple {87738#false} assume 1 == ~m_pc~0; {87738#false} is VALID [2022-02-21 04:23:31,528 INFO L290 TraceCheckUtils]: 46: Hoare triple {87738#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {87738#false} is VALID [2022-02-21 04:23:31,528 INFO L290 TraceCheckUtils]: 47: Hoare triple {87738#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {87738#false} is VALID [2022-02-21 04:23:31,528 INFO L290 TraceCheckUtils]: 48: Hoare triple {87738#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {87738#false} is VALID [2022-02-21 04:23:31,528 INFO L290 TraceCheckUtils]: 49: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp~1#1); {87738#false} is VALID [2022-02-21 04:23:31,528 INFO L290 TraceCheckUtils]: 50: Hoare triple {87738#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {87738#false} is VALID [2022-02-21 04:23:31,529 INFO L290 TraceCheckUtils]: 51: Hoare triple {87738#false} assume !(1 == ~t1_pc~0); {87738#false} is VALID [2022-02-21 04:23:31,529 INFO L290 TraceCheckUtils]: 52: Hoare triple {87738#false} is_transmit1_triggered_~__retres1~1#1 := 0; {87738#false} is VALID [2022-02-21 04:23:31,529 INFO L290 TraceCheckUtils]: 53: Hoare triple {87738#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {87738#false} is VALID [2022-02-21 04:23:31,529 INFO L290 TraceCheckUtils]: 54: Hoare triple {87738#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {87738#false} is VALID [2022-02-21 04:23:31,529 INFO L290 TraceCheckUtils]: 55: Hoare triple {87738#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {87738#false} is VALID [2022-02-21 04:23:31,529 INFO L290 TraceCheckUtils]: 56: Hoare triple {87738#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {87738#false} is VALID [2022-02-21 04:23:31,529 INFO L290 TraceCheckUtils]: 57: Hoare triple {87738#false} assume 1 == ~t2_pc~0; {87738#false} is VALID [2022-02-21 04:23:31,529 INFO L290 TraceCheckUtils]: 58: Hoare triple {87738#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {87738#false} is VALID [2022-02-21 04:23:31,530 INFO L290 TraceCheckUtils]: 59: Hoare triple {87738#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {87738#false} is VALID [2022-02-21 04:23:31,530 INFO L290 TraceCheckUtils]: 60: Hoare triple {87738#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {87738#false} is VALID [2022-02-21 04:23:31,530 INFO L290 TraceCheckUtils]: 61: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp___1~0#1); {87738#false} is VALID [2022-02-21 04:23:31,530 INFO L290 TraceCheckUtils]: 62: Hoare triple {87738#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {87738#false} is VALID [2022-02-21 04:23:31,530 INFO L290 TraceCheckUtils]: 63: Hoare triple {87738#false} assume !(1 == ~t3_pc~0); {87738#false} is VALID [2022-02-21 04:23:31,530 INFO L290 TraceCheckUtils]: 64: Hoare triple {87738#false} is_transmit3_triggered_~__retres1~3#1 := 0; {87738#false} is VALID [2022-02-21 04:23:31,530 INFO L290 TraceCheckUtils]: 65: Hoare triple {87738#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {87738#false} is VALID [2022-02-21 04:23:31,531 INFO L290 TraceCheckUtils]: 66: Hoare triple {87738#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {87738#false} is VALID [2022-02-21 04:23:31,531 INFO L290 TraceCheckUtils]: 67: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp___2~0#1); {87738#false} is VALID [2022-02-21 04:23:31,531 INFO L290 TraceCheckUtils]: 68: Hoare triple {87738#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {87738#false} is VALID [2022-02-21 04:23:31,531 INFO L290 TraceCheckUtils]: 69: Hoare triple {87738#false} assume 1 == ~t4_pc~0; {87738#false} is VALID [2022-02-21 04:23:31,531 INFO L290 TraceCheckUtils]: 70: Hoare triple {87738#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {87738#false} is VALID [2022-02-21 04:23:31,531 INFO L290 TraceCheckUtils]: 71: Hoare triple {87738#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {87738#false} is VALID [2022-02-21 04:23:31,531 INFO L290 TraceCheckUtils]: 72: Hoare triple {87738#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {87738#false} is VALID [2022-02-21 04:23:31,532 INFO L290 TraceCheckUtils]: 73: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp___3~0#1); {87738#false} is VALID [2022-02-21 04:23:31,532 INFO L290 TraceCheckUtils]: 74: Hoare triple {87738#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {87738#false} is VALID [2022-02-21 04:23:31,532 INFO L290 TraceCheckUtils]: 75: Hoare triple {87738#false} assume !(1 == ~t5_pc~0); {87738#false} is VALID [2022-02-21 04:23:31,532 INFO L290 TraceCheckUtils]: 76: Hoare triple {87738#false} is_transmit5_triggered_~__retres1~5#1 := 0; {87738#false} is VALID [2022-02-21 04:23:31,532 INFO L290 TraceCheckUtils]: 77: Hoare triple {87738#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {87738#false} is VALID [2022-02-21 04:23:31,532 INFO L290 TraceCheckUtils]: 78: Hoare triple {87738#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {87738#false} is VALID [2022-02-21 04:23:31,532 INFO L290 TraceCheckUtils]: 79: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp___4~0#1); {87738#false} is VALID [2022-02-21 04:23:31,532 INFO L290 TraceCheckUtils]: 80: Hoare triple {87738#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {87738#false} is VALID [2022-02-21 04:23:31,533 INFO L290 TraceCheckUtils]: 81: Hoare triple {87738#false} assume 1 == ~t6_pc~0; {87738#false} is VALID [2022-02-21 04:23:31,533 INFO L290 TraceCheckUtils]: 82: Hoare triple {87738#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {87738#false} is VALID [2022-02-21 04:23:31,533 INFO L290 TraceCheckUtils]: 83: Hoare triple {87738#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {87738#false} is VALID [2022-02-21 04:23:31,533 INFO L290 TraceCheckUtils]: 84: Hoare triple {87738#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {87738#false} is VALID [2022-02-21 04:23:31,533 INFO L290 TraceCheckUtils]: 85: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp___5~0#1); {87738#false} is VALID [2022-02-21 04:23:31,533 INFO L290 TraceCheckUtils]: 86: Hoare triple {87738#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {87738#false} is VALID [2022-02-21 04:23:31,533 INFO L290 TraceCheckUtils]: 87: Hoare triple {87738#false} assume 1 == ~t7_pc~0; {87738#false} is VALID [2022-02-21 04:23:31,533 INFO L290 TraceCheckUtils]: 88: Hoare triple {87738#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {87738#false} is VALID [2022-02-21 04:23:31,534 INFO L290 TraceCheckUtils]: 89: Hoare triple {87738#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {87738#false} is VALID [2022-02-21 04:23:31,534 INFO L290 TraceCheckUtils]: 90: Hoare triple {87738#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {87738#false} is VALID [2022-02-21 04:23:31,534 INFO L290 TraceCheckUtils]: 91: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp___6~0#1); {87738#false} is VALID [2022-02-21 04:23:31,534 INFO L290 TraceCheckUtils]: 92: Hoare triple {87738#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {87738#false} is VALID [2022-02-21 04:23:31,534 INFO L290 TraceCheckUtils]: 93: Hoare triple {87738#false} assume !(1 == ~t8_pc~0); {87738#false} is VALID [2022-02-21 04:23:31,534 INFO L290 TraceCheckUtils]: 94: Hoare triple {87738#false} is_transmit8_triggered_~__retres1~8#1 := 0; {87738#false} is VALID [2022-02-21 04:23:31,534 INFO L290 TraceCheckUtils]: 95: Hoare triple {87738#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {87738#false} is VALID [2022-02-21 04:23:31,534 INFO L290 TraceCheckUtils]: 96: Hoare triple {87738#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {87738#false} is VALID [2022-02-21 04:23:31,534 INFO L290 TraceCheckUtils]: 97: Hoare triple {87738#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {87738#false} is VALID [2022-02-21 04:23:31,534 INFO L290 TraceCheckUtils]: 98: Hoare triple {87738#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {87738#false} is VALID [2022-02-21 04:23:31,535 INFO L290 TraceCheckUtils]: 99: Hoare triple {87738#false} assume 1 == ~t9_pc~0; {87738#false} is VALID [2022-02-21 04:23:31,535 INFO L290 TraceCheckUtils]: 100: Hoare triple {87738#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {87738#false} is VALID [2022-02-21 04:23:31,535 INFO L290 TraceCheckUtils]: 101: Hoare triple {87738#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {87738#false} is VALID [2022-02-21 04:23:31,535 INFO L290 TraceCheckUtils]: 102: Hoare triple {87738#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {87738#false} is VALID [2022-02-21 04:23:31,535 INFO L290 TraceCheckUtils]: 103: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp___8~0#1); {87738#false} is VALID [2022-02-21 04:23:31,535 INFO L290 TraceCheckUtils]: 104: Hoare triple {87738#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {87738#false} is VALID [2022-02-21 04:23:31,535 INFO L290 TraceCheckUtils]: 105: Hoare triple {87738#false} assume !(1 == ~t10_pc~0); {87738#false} is VALID [2022-02-21 04:23:31,535 INFO L290 TraceCheckUtils]: 106: Hoare triple {87738#false} is_transmit10_triggered_~__retres1~10#1 := 0; {87738#false} is VALID [2022-02-21 04:23:31,535 INFO L290 TraceCheckUtils]: 107: Hoare triple {87738#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {87738#false} is VALID [2022-02-21 04:23:31,536 INFO L290 TraceCheckUtils]: 108: Hoare triple {87738#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {87738#false} is VALID [2022-02-21 04:23:31,536 INFO L290 TraceCheckUtils]: 109: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp___9~0#1); {87738#false} is VALID [2022-02-21 04:23:31,536 INFO L290 TraceCheckUtils]: 110: Hoare triple {87738#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {87738#false} is VALID [2022-02-21 04:23:31,536 INFO L290 TraceCheckUtils]: 111: Hoare triple {87738#false} assume 1 == ~t11_pc~0; {87738#false} is VALID [2022-02-21 04:23:31,536 INFO L290 TraceCheckUtils]: 112: Hoare triple {87738#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {87738#false} is VALID [2022-02-21 04:23:31,536 INFO L290 TraceCheckUtils]: 113: Hoare triple {87738#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {87738#false} is VALID [2022-02-21 04:23:31,536 INFO L290 TraceCheckUtils]: 114: Hoare triple {87738#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {87738#false} is VALID [2022-02-21 04:23:31,536 INFO L290 TraceCheckUtils]: 115: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp___10~0#1); {87738#false} is VALID [2022-02-21 04:23:31,536 INFO L290 TraceCheckUtils]: 116: Hoare triple {87738#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {87738#false} is VALID [2022-02-21 04:23:31,536 INFO L290 TraceCheckUtils]: 117: Hoare triple {87738#false} assume !(1 == ~t12_pc~0); {87738#false} is VALID [2022-02-21 04:23:31,537 INFO L290 TraceCheckUtils]: 118: Hoare triple {87738#false} is_transmit12_triggered_~__retres1~12#1 := 0; {87738#false} is VALID [2022-02-21 04:23:31,537 INFO L290 TraceCheckUtils]: 119: Hoare triple {87738#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {87738#false} is VALID [2022-02-21 04:23:31,537 INFO L290 TraceCheckUtils]: 120: Hoare triple {87738#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {87738#false} is VALID [2022-02-21 04:23:31,537 INFO L290 TraceCheckUtils]: 121: Hoare triple {87738#false} assume !(0 != activate_threads_~tmp___11~0#1); {87738#false} is VALID [2022-02-21 04:23:31,537 INFO L290 TraceCheckUtils]: 122: Hoare triple {87738#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {87738#false} is VALID [2022-02-21 04:23:31,537 INFO L290 TraceCheckUtils]: 123: Hoare triple {87738#false} assume !(1 == ~M_E~0); {87738#false} is VALID [2022-02-21 04:23:31,537 INFO L290 TraceCheckUtils]: 124: Hoare triple {87738#false} assume !(1 == ~T1_E~0); {87738#false} is VALID [2022-02-21 04:23:31,537 INFO L290 TraceCheckUtils]: 125: Hoare triple {87738#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {87738#false} is VALID [2022-02-21 04:23:31,537 INFO L290 TraceCheckUtils]: 126: Hoare triple {87738#false} assume !(1 == ~T3_E~0); {87738#false} is VALID [2022-02-21 04:23:31,538 INFO L290 TraceCheckUtils]: 127: Hoare triple {87738#false} assume !(1 == ~T4_E~0); {87738#false} is VALID [2022-02-21 04:23:31,538 INFO L290 TraceCheckUtils]: 128: Hoare triple {87738#false} assume !(1 == ~T5_E~0); {87738#false} is VALID [2022-02-21 04:23:31,538 INFO L290 TraceCheckUtils]: 129: Hoare triple {87738#false} assume !(1 == ~T6_E~0); {87738#false} is VALID [2022-02-21 04:23:31,538 INFO L290 TraceCheckUtils]: 130: Hoare triple {87738#false} assume !(1 == ~T7_E~0); {87738#false} is VALID [2022-02-21 04:23:31,538 INFO L290 TraceCheckUtils]: 131: Hoare triple {87738#false} assume !(1 == ~T8_E~0); {87738#false} is VALID [2022-02-21 04:23:31,538 INFO L290 TraceCheckUtils]: 132: Hoare triple {87738#false} assume !(1 == ~T9_E~0); {87738#false} is VALID [2022-02-21 04:23:31,538 INFO L290 TraceCheckUtils]: 133: Hoare triple {87738#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {87738#false} is VALID [2022-02-21 04:23:31,538 INFO L290 TraceCheckUtils]: 134: Hoare triple {87738#false} assume !(1 == ~T11_E~0); {87738#false} is VALID [2022-02-21 04:23:31,538 INFO L290 TraceCheckUtils]: 135: Hoare triple {87738#false} assume !(1 == ~T12_E~0); {87738#false} is VALID [2022-02-21 04:23:31,539 INFO L290 TraceCheckUtils]: 136: Hoare triple {87738#false} assume !(1 == ~E_M~0); {87738#false} is VALID [2022-02-21 04:23:31,539 INFO L290 TraceCheckUtils]: 137: Hoare triple {87738#false} assume !(1 == ~E_1~0); {87738#false} is VALID [2022-02-21 04:23:31,539 INFO L290 TraceCheckUtils]: 138: Hoare triple {87738#false} assume !(1 == ~E_2~0); {87738#false} is VALID [2022-02-21 04:23:31,539 INFO L290 TraceCheckUtils]: 139: Hoare triple {87738#false} assume !(1 == ~E_3~0); {87738#false} is VALID [2022-02-21 04:23:31,539 INFO L290 TraceCheckUtils]: 140: Hoare triple {87738#false} assume !(1 == ~E_4~0); {87738#false} is VALID [2022-02-21 04:23:31,539 INFO L290 TraceCheckUtils]: 141: Hoare triple {87738#false} assume 1 == ~E_5~0;~E_5~0 := 2; {87738#false} is VALID [2022-02-21 04:23:31,539 INFO L290 TraceCheckUtils]: 142: Hoare triple {87738#false} assume !(1 == ~E_6~0); {87738#false} is VALID [2022-02-21 04:23:31,539 INFO L290 TraceCheckUtils]: 143: Hoare triple {87738#false} assume !(1 == ~E_7~0); {87738#false} is VALID [2022-02-21 04:23:31,539 INFO L290 TraceCheckUtils]: 144: Hoare triple {87738#false} assume !(1 == ~E_8~0); {87738#false} is VALID [2022-02-21 04:23:31,539 INFO L290 TraceCheckUtils]: 145: Hoare triple {87738#false} assume !(1 == ~E_9~0); {87738#false} is VALID [2022-02-21 04:23:31,540 INFO L290 TraceCheckUtils]: 146: Hoare triple {87738#false} assume !(1 == ~E_10~0); {87738#false} is VALID [2022-02-21 04:23:31,540 INFO L290 TraceCheckUtils]: 147: Hoare triple {87738#false} assume !(1 == ~E_11~0); {87738#false} is VALID [2022-02-21 04:23:31,540 INFO L290 TraceCheckUtils]: 148: Hoare triple {87738#false} assume !(1 == ~E_12~0); {87738#false} is VALID [2022-02-21 04:23:31,540 INFO L290 TraceCheckUtils]: 149: Hoare triple {87738#false} assume { :end_inline_reset_delta_events } true; {87738#false} is VALID [2022-02-21 04:23:31,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:31,540 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:31,541 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430097406] [2022-02-21 04:23:31,541 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430097406] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:31,541 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:31,541 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:31,541 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1691085175] [2022-02-21 04:23:31,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:31,542 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:31,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:31,543 INFO L85 PathProgramCache]: Analyzing trace with hash 266484754, now seen corresponding path program 1 times [2022-02-21 04:23:31,543 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:31,543 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991034092] [2022-02-21 04:23:31,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:31,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:31,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:31,565 INFO L290 TraceCheckUtils]: 0: Hoare triple {87740#true} assume !false; {87740#true} is VALID [2022-02-21 04:23:31,565 INFO L290 TraceCheckUtils]: 1: Hoare triple {87740#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {87740#true} is VALID [2022-02-21 04:23:31,565 INFO L290 TraceCheckUtils]: 2: Hoare triple {87740#true} assume !false; {87740#true} is VALID [2022-02-21 04:23:31,565 INFO L290 TraceCheckUtils]: 3: Hoare triple {87740#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {87740#true} is VALID [2022-02-21 04:23:31,566 INFO L290 TraceCheckUtils]: 4: Hoare triple {87740#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {87740#true} is VALID [2022-02-21 04:23:31,566 INFO L290 TraceCheckUtils]: 5: Hoare triple {87740#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {87740#true} is VALID [2022-02-21 04:23:31,566 INFO L290 TraceCheckUtils]: 6: Hoare triple {87740#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {87740#true} is VALID [2022-02-21 04:23:31,566 INFO L290 TraceCheckUtils]: 7: Hoare triple {87740#true} assume !(0 != eval_~tmp~0#1); {87740#true} is VALID [2022-02-21 04:23:31,566 INFO L290 TraceCheckUtils]: 8: Hoare triple {87740#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {87740#true} is VALID [2022-02-21 04:23:31,566 INFO L290 TraceCheckUtils]: 9: Hoare triple {87740#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {87740#true} is VALID [2022-02-21 04:23:31,566 INFO L290 TraceCheckUtils]: 10: Hoare triple {87740#true} assume 0 == ~M_E~0;~M_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,567 INFO L290 TraceCheckUtils]: 11: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,567 INFO L290 TraceCheckUtils]: 12: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,567 INFO L290 TraceCheckUtils]: 13: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,567 INFO L290 TraceCheckUtils]: 14: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,568 INFO L290 TraceCheckUtils]: 15: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,568 INFO L290 TraceCheckUtils]: 16: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,568 INFO L290 TraceCheckUtils]: 17: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,568 INFO L290 TraceCheckUtils]: 18: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,569 INFO L290 TraceCheckUtils]: 19: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,569 INFO L290 TraceCheckUtils]: 20: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,569 INFO L290 TraceCheckUtils]: 21: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,569 INFO L290 TraceCheckUtils]: 22: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,570 INFO L290 TraceCheckUtils]: 23: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,570 INFO L290 TraceCheckUtils]: 24: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,570 INFO L290 TraceCheckUtils]: 25: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,570 INFO L290 TraceCheckUtils]: 26: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,582 INFO L290 TraceCheckUtils]: 27: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,582 INFO L290 TraceCheckUtils]: 28: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,582 INFO L290 TraceCheckUtils]: 29: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,582 INFO L290 TraceCheckUtils]: 30: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,583 INFO L290 TraceCheckUtils]: 31: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,583 INFO L290 TraceCheckUtils]: 32: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,583 INFO L290 TraceCheckUtils]: 33: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,584 INFO L290 TraceCheckUtils]: 34: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,584 INFO L290 TraceCheckUtils]: 35: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,584 INFO L290 TraceCheckUtils]: 36: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,584 INFO L290 TraceCheckUtils]: 37: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,585 INFO L290 TraceCheckUtils]: 38: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,585 INFO L290 TraceCheckUtils]: 39: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,585 INFO L290 TraceCheckUtils]: 40: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,585 INFO L290 TraceCheckUtils]: 41: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,586 INFO L290 TraceCheckUtils]: 42: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,586 INFO L290 TraceCheckUtils]: 43: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,586 INFO L290 TraceCheckUtils]: 44: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,586 INFO L290 TraceCheckUtils]: 45: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,587 INFO L290 TraceCheckUtils]: 46: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,587 INFO L290 TraceCheckUtils]: 47: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,587 INFO L290 TraceCheckUtils]: 48: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,588 INFO L290 TraceCheckUtils]: 49: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,588 INFO L290 TraceCheckUtils]: 50: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,588 INFO L290 TraceCheckUtils]: 51: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,588 INFO L290 TraceCheckUtils]: 52: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,589 INFO L290 TraceCheckUtils]: 53: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,589 INFO L290 TraceCheckUtils]: 54: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,589 INFO L290 TraceCheckUtils]: 55: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,590 INFO L290 TraceCheckUtils]: 56: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,590 INFO L290 TraceCheckUtils]: 57: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,590 INFO L290 TraceCheckUtils]: 58: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,590 INFO L290 TraceCheckUtils]: 59: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,591 INFO L290 TraceCheckUtils]: 60: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,591 INFO L290 TraceCheckUtils]: 61: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,591 INFO L290 TraceCheckUtils]: 62: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,591 INFO L290 TraceCheckUtils]: 63: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,592 INFO L290 TraceCheckUtils]: 64: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,592 INFO L290 TraceCheckUtils]: 65: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,592 INFO L290 TraceCheckUtils]: 66: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,592 INFO L290 TraceCheckUtils]: 67: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,593 INFO L290 TraceCheckUtils]: 68: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,593 INFO L290 TraceCheckUtils]: 69: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,593 INFO L290 TraceCheckUtils]: 70: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,593 INFO L290 TraceCheckUtils]: 71: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,594 INFO L290 TraceCheckUtils]: 72: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,594 INFO L290 TraceCheckUtils]: 73: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,594 INFO L290 TraceCheckUtils]: 74: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,594 INFO L290 TraceCheckUtils]: 75: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,595 INFO L290 TraceCheckUtils]: 76: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,595 INFO L290 TraceCheckUtils]: 77: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,595 INFO L290 TraceCheckUtils]: 78: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,595 INFO L290 TraceCheckUtils]: 79: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,596 INFO L290 TraceCheckUtils]: 80: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,596 INFO L290 TraceCheckUtils]: 81: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,596 INFO L290 TraceCheckUtils]: 82: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,596 INFO L290 TraceCheckUtils]: 83: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,597 INFO L290 TraceCheckUtils]: 84: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,597 INFO L290 TraceCheckUtils]: 85: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,597 INFO L290 TraceCheckUtils]: 86: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,597 INFO L290 TraceCheckUtils]: 87: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,598 INFO L290 TraceCheckUtils]: 88: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,598 INFO L290 TraceCheckUtils]: 89: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,598 INFO L290 TraceCheckUtils]: 90: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,598 INFO L290 TraceCheckUtils]: 91: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,599 INFO L290 TraceCheckUtils]: 92: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,599 INFO L290 TraceCheckUtils]: 93: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,599 INFO L290 TraceCheckUtils]: 94: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,599 INFO L290 TraceCheckUtils]: 95: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,600 INFO L290 TraceCheckUtils]: 96: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,600 INFO L290 TraceCheckUtils]: 97: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,600 INFO L290 TraceCheckUtils]: 98: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,600 INFO L290 TraceCheckUtils]: 99: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,601 INFO L290 TraceCheckUtils]: 100: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,601 INFO L290 TraceCheckUtils]: 101: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,601 INFO L290 TraceCheckUtils]: 102: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,601 INFO L290 TraceCheckUtils]: 103: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,602 INFO L290 TraceCheckUtils]: 104: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,602 INFO L290 TraceCheckUtils]: 105: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,602 INFO L290 TraceCheckUtils]: 106: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,602 INFO L290 TraceCheckUtils]: 107: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 108: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 109: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 110: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,603 INFO L290 TraceCheckUtils]: 111: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,604 INFO L290 TraceCheckUtils]: 112: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,604 INFO L290 TraceCheckUtils]: 113: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,604 INFO L290 TraceCheckUtils]: 114: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {87742#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 115: Hoare triple {87742#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {87741#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 116: Hoare triple {87741#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 117: Hoare triple {87741#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 118: Hoare triple {87741#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 119: Hoare triple {87741#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 120: Hoare triple {87741#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 121: Hoare triple {87741#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 122: Hoare triple {87741#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,605 INFO L290 TraceCheckUtils]: 123: Hoare triple {87741#false} assume !(1 == ~T8_E~0); {87741#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 124: Hoare triple {87741#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 125: Hoare triple {87741#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 126: Hoare triple {87741#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 127: Hoare triple {87741#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 128: Hoare triple {87741#false} assume 1 == ~E_M~0;~E_M~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 129: Hoare triple {87741#false} assume 1 == ~E_1~0;~E_1~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 130: Hoare triple {87741#false} assume 1 == ~E_2~0;~E_2~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 131: Hoare triple {87741#false} assume !(1 == ~E_3~0); {87741#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 132: Hoare triple {87741#false} assume 1 == ~E_4~0;~E_4~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,606 INFO L290 TraceCheckUtils]: 133: Hoare triple {87741#false} assume 1 == ~E_5~0;~E_5~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 134: Hoare triple {87741#false} assume 1 == ~E_6~0;~E_6~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 135: Hoare triple {87741#false} assume 1 == ~E_7~0;~E_7~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 136: Hoare triple {87741#false} assume 1 == ~E_8~0;~E_8~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 137: Hoare triple {87741#false} assume 1 == ~E_9~0;~E_9~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 138: Hoare triple {87741#false} assume 1 == ~E_10~0;~E_10~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 139: Hoare triple {87741#false} assume !(1 == ~E_11~0); {87741#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 140: Hoare triple {87741#false} assume 1 == ~E_12~0;~E_12~0 := 2; {87741#false} is VALID [2022-02-21 04:23:31,607 INFO L290 TraceCheckUtils]: 141: Hoare triple {87741#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {87741#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 142: Hoare triple {87741#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {87741#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 143: Hoare triple {87741#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {87741#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 144: Hoare triple {87741#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {87741#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 145: Hoare triple {87741#false} assume !(0 == start_simulation_~tmp~3#1); {87741#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 146: Hoare triple {87741#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {87741#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 147: Hoare triple {87741#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {87741#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 148: Hoare triple {87741#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {87741#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 149: Hoare triple {87741#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {87741#false} is VALID [2022-02-21 04:23:31,608 INFO L290 TraceCheckUtils]: 150: Hoare triple {87741#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {87741#false} is VALID [2022-02-21 04:23:31,609 INFO L290 TraceCheckUtils]: 151: Hoare triple {87741#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {87741#false} is VALID [2022-02-21 04:23:31,609 INFO L290 TraceCheckUtils]: 152: Hoare triple {87741#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {87741#false} is VALID [2022-02-21 04:23:31,609 INFO L290 TraceCheckUtils]: 153: Hoare triple {87741#false} assume !(0 != start_simulation_~tmp___0~1#1); {87741#false} is VALID [2022-02-21 04:23:31,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:31,609 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:31,609 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991034092] [2022-02-21 04:23:31,610 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1991034092] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:31,610 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:31,610 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:31,610 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869079751] [2022-02-21 04:23:31,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:31,611 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:31,611 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:31,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:31,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:31,611 INFO L87 Difference]: Start difference. First operand 1788 states and 2640 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:32,777 INFO L93 Difference]: Finished difference Result 1788 states and 2635 transitions. [2022-02-21 04:23:32,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:32,777 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,879 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:32,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2635 transitions. [2022-02-21 04:23:32,972 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:33,053 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2635 transitions. [2022-02-21 04:23:33,054 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-02-21 04:23:33,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-02-21 04:23:33,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2635 transitions. [2022-02-21 04:23:33,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:33,069 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2022-02-21 04:23:33,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2635 transitions. [2022-02-21 04:23:33,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-02-21 04:23:33,080 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:33,081 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1788 states and 2635 transitions. Second operand has 1788 states, 1788 states have (on average 1.4737136465324385) internal successors, (2635), 1787 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,082 INFO L74 IsIncluded]: Start isIncluded. First operand 1788 states and 2635 transitions. Second operand has 1788 states, 1788 states have (on average 1.4737136465324385) internal successors, (2635), 1787 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,083 INFO L87 Difference]: Start difference. First operand 1788 states and 2635 transitions. Second operand has 1788 states, 1788 states have (on average 1.4737136465324385) internal successors, (2635), 1787 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:33,151 INFO L93 Difference]: Finished difference Result 1788 states and 2635 transitions. [2022-02-21 04:23:33,151 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2635 transitions. [2022-02-21 04:23:33,153 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:33,153 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:33,155 INFO L74 IsIncluded]: Start isIncluded. First operand has 1788 states, 1788 states have (on average 1.4737136465324385) internal successors, (2635), 1787 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2635 transitions. [2022-02-21 04:23:33,155 INFO L87 Difference]: Start difference. First operand has 1788 states, 1788 states have (on average 1.4737136465324385) internal successors, (2635), 1787 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1788 states and 2635 transitions. [2022-02-21 04:23:33,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:33,221 INFO L93 Difference]: Finished difference Result 1788 states and 2635 transitions. [2022-02-21 04:23:33,221 INFO L276 IsEmpty]: Start isEmpty. Operand 1788 states and 2635 transitions. [2022-02-21 04:23:33,223 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:33,223 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:33,223 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:33,223 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:33,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4737136465324385) internal successors, (2635), 1787 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2635 transitions. [2022-02-21 04:23:33,290 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2022-02-21 04:23:33,291 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2022-02-21 04:23:33,291 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:23:33,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2635 transitions. [2022-02-21 04:23:33,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-02-21 04:23:33,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:33,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:33,295 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:33,295 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:33,295 INFO L791 eck$LassoCheckResult]: Stem: 90320#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 90321#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 89841#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89842#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89896#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 91235#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 90329#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 90132#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89531#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89532#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 90754#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 90865#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 91301#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 91302#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 90260#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 90261#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 90783#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 90702#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 90295#L1201 assume !(0 == ~M_E~0); 90296#L1201-2 assume !(0 == ~T1_E~0); 91142#L1206-1 assume !(0 == ~T2_E~0); 91128#L1211-1 assume !(0 == ~T3_E~0); 91129#L1216-1 assume !(0 == ~T4_E~0); 90116#L1221-1 assume !(0 == ~T5_E~0); 90117#L1226-1 assume !(0 == ~T6_E~0); 89756#L1231-1 assume !(0 == ~T7_E~0); 89757#L1236-1 assume !(0 == ~T8_E~0); 91165#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 90153#L1246-1 assume !(0 == ~T10_E~0); 90154#L1251-1 assume !(0 == ~T11_E~0); 90293#L1256-1 assume !(0 == ~T12_E~0); 89542#L1261-1 assume !(0 == ~E_M~0); 89543#L1266-1 assume !(0 == ~E_1~0); 91287#L1271-1 assume !(0 == ~E_2~0); 90849#L1276-1 assume !(0 == ~E_3~0); 90850#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 90797#L1286-1 assume !(0 == ~E_5~0); 90007#L1291-1 assume !(0 == ~E_6~0); 90008#L1296-1 assume !(0 == ~E_7~0); 90583#L1301-1 assume !(0 == ~E_8~0); 90584#L1306-1 assume !(0 == ~E_9~0); 91064#L1311-1 assume !(0 == ~E_10~0); 89958#L1316-1 assume !(0 == ~E_11~0); 89959#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 90601#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90602#L593 assume 1 == ~m_pc~0; 90746#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 89848#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91274#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 90808#L1492 assume !(0 != activate_threads_~tmp~1#1); 90809#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91100#L612 assume !(1 == ~t1_pc~0); 91101#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 91230#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90230#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89852#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89853#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90272#L631 assume 1 == ~t2_pc~0; 90207#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 89629#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89630#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90466#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 90467#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89925#L650 assume !(1 == ~t3_pc~0); 89926#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 90626#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89849#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89582#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 89583#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 90775#L669 assume 1 == ~t4_pc~0; 90776#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 91134#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 90259#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89791#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 89792#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90016#L688 assume !(1 == ~t5_pc~0); 89807#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 89808#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 90726#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 90660#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 90661#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90790#L707 assume 1 == ~t6_pc~0; 91199#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 90436#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 90437#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 91197#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 90732#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90294#L726 assume 1 == ~t7_pc~0; 90193#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 89892#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 90933#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 91207#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 89661#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89662#L745 assume !(1 == ~t8_pc~0); 90109#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 90128#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 90966#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 90514#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 90515#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 91025#L764 assume 1 == ~t9_pc~0; 90292#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 90134#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 90811#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 91258#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 89681#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 89682#L783 assume !(1 == ~t10_pc~0); 89743#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 89744#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 89785#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 89786#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 90248#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 91136#L802 assume 1 == ~t11_pc~0; 91118#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 89626#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 89627#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 90118#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 90119#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 90229#L821 assume !(1 == ~t12_pc~0); 90480#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 90576#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 89631#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 89632#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 91174#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90820#L1339 assume !(1 == ~M_E~0); 90821#L1339-2 assume !(1 == ~T1_E~0); 91209#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 91210#L1349-1 assume !(1 == ~T3_E~0); 90594#L1354-1 assume !(1 == ~T4_E~0); 90595#L1359-1 assume !(1 == ~T5_E~0); 90996#L1364-1 assume !(1 == ~T6_E~0); 90059#L1369-1 assume !(1 == ~T7_E~0); 90060#L1374-1 assume !(1 == ~T8_E~0); 90597#L1379-1 assume !(1 == ~T9_E~0); 90598#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 90697#L1389-1 assume !(1 == ~T11_E~0); 91168#L1394-1 assume !(1 == ~T12_E~0); 91169#L1399-1 assume !(1 == ~E_M~0); 91259#L1404-1 assume !(1 == ~E_1~0); 90158#L1409-1 assume !(1 == ~E_2~0); 90159#L1414-1 assume !(1 == ~E_3~0); 90885#L1419-1 assume !(1 == ~E_4~0); 89799#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 89800#L1429-1 assume !(1 == ~E_6~0); 90610#L1434-1 assume !(1 == ~E_7~0); 91189#L1439-1 assume !(1 == ~E_8~0); 89837#L1444-1 assume !(1 == ~E_9~0); 89838#L1449-1 assume !(1 == ~E_10~0); 90212#L1454-1 assume !(1 == ~E_11~0); 90213#L1459-1 assume !(1 == ~E_12~0); 90731#L1464-1 assume { :end_inline_reset_delta_events } true; 89971#L1810-2 [2022-02-21 04:23:33,295 INFO L793 eck$LassoCheckResult]: Loop: 89971#L1810-2 assume !false; 90415#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 90331#L1176 assume !false; 90893#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 90463#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 89669#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 90219#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 90220#L1003 assume !(0 != eval_~tmp~0#1); 89861#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89862#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 91052#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 90835#L1201-5 assume !(0 == ~T1_E~0); 90836#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 90729#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89920#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 89921#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 90387#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 89991#L1231-3 assume !(0 == ~T7_E~0); 89992#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 90238#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 91220#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 91121#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 90826#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 89937#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 89938#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 89983#L1271-3 assume !(0 == ~E_2~0); 89984#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 90360#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 90361#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 90882#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 90883#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 91298#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 91255#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 90472#L1311-3 assume !(0 == ~E_10~0); 89863#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 89864#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 89939#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90575#L593-42 assume 1 == ~m_pc~0; 90968#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 90734#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91283#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 91284#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 89762#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89763#L612-42 assume 1 == ~t1_pc~0; 90685#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 91077#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91198#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89850#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89851#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90546#L631-42 assume !(1 == ~t2_pc~0); 89617#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 89616#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90535#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90411#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 90412#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 90012#L650-42 assume 1 == ~t3_pc~0; 89574#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 89575#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91226#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 90205#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 90206#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91190#L669-42 assume !(1 == ~t4_pc~0); 89572#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 89573#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91001#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 90891#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 90788#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90789#L688-42 assume !(1 == ~t5_pc~0); 90881#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 91081#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89713#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 89714#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 89790#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89604#L707-42 assume !(1 == ~t6_pc~0); 89605#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 91262#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 91006#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 91007#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 90756#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90757#L726-42 assume !(1 == ~t7_pc~0); 91035#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 91060#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 91061#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 90475#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 90476#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 90579#L745-42 assume !(1 == ~t8_pc~0); 90617#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 90618#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89945#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 89590#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 89591#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 90316#L764-42 assume !(1 == ~t9_pc~0); 90453#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 90805#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 90806#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 89876#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 89877#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 89930#L783-42 assume 1 == ~t10_pc~0; 89546#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 89547#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 90142#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 90275#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 91292#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 90976#L802-42 assume 1 == ~t11_pc~0; 90077#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 89688#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 89689#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 89639#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 89640#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 90816#L821-42 assume 1 == ~t12_pc~0; 90817#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 90182#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 89544#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 89545#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 90522#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90512#L1339-3 assume !(1 == ~M_E~0); 90513#L1339-5 assume !(1 == ~T1_E~0); 90664#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90774#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90191#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90192#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 90785#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 91281#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 91188#L1374-3 assume !(1 == ~T8_E~0); 90013#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 90014#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 90189#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 90190#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 90399#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 91195#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 91163#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 91164#L1414-3 assume !(1 == ~E_3~0); 91219#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 90978#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89897#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 89898#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 90784#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 89825#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 89826#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 89942#L1454-3 assume !(1 == ~E_11~0); 90779#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 90780#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 90438#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 89735#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 89995#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 89996#L1829 assume !(0 == start_simulation_~tmp~3#1); 89717#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 89718#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 90518#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 90519#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 90798#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 90799#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 90419#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 89970#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 89971#L1810-2 [2022-02-21 04:23:33,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:33,296 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2022-02-21 04:23:33,296 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:33,296 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104476742] [2022-02-21 04:23:33,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:33,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:33,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:33,329 INFO L290 TraceCheckUtils]: 0: Hoare triple {94898#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,330 INFO L290 TraceCheckUtils]: 1: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,330 INFO L290 TraceCheckUtils]: 2: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,330 INFO L290 TraceCheckUtils]: 3: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,331 INFO L290 TraceCheckUtils]: 4: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,331 INFO L290 TraceCheckUtils]: 5: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,331 INFO L290 TraceCheckUtils]: 6: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,332 INFO L290 TraceCheckUtils]: 7: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,332 INFO L290 TraceCheckUtils]: 8: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,332 INFO L290 TraceCheckUtils]: 9: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,332 INFO L290 TraceCheckUtils]: 10: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,333 INFO L290 TraceCheckUtils]: 11: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,333 INFO L290 TraceCheckUtils]: 12: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,333 INFO L290 TraceCheckUtils]: 13: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,334 INFO L290 TraceCheckUtils]: 14: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,334 INFO L290 TraceCheckUtils]: 15: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,334 INFO L290 TraceCheckUtils]: 16: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,334 INFO L290 TraceCheckUtils]: 17: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,335 INFO L290 TraceCheckUtils]: 18: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume !(0 == ~M_E~0); {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,335 INFO L290 TraceCheckUtils]: 19: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume !(0 == ~T1_E~0); {94900#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:23:33,335 INFO L290 TraceCheckUtils]: 20: Hoare triple {94900#(= ~T2_E~0 ~T9_E~0)} assume !(0 == ~T2_E~0); {94901#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:33,336 INFO L290 TraceCheckUtils]: 21: Hoare triple {94901#(not (= ~T9_E~0 0))} assume !(0 == ~T3_E~0); {94901#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:33,336 INFO L290 TraceCheckUtils]: 22: Hoare triple {94901#(not (= ~T9_E~0 0))} assume !(0 == ~T4_E~0); {94901#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:33,336 INFO L290 TraceCheckUtils]: 23: Hoare triple {94901#(not (= ~T9_E~0 0))} assume !(0 == ~T5_E~0); {94901#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:33,336 INFO L290 TraceCheckUtils]: 24: Hoare triple {94901#(not (= ~T9_E~0 0))} assume !(0 == ~T6_E~0); {94901#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:33,337 INFO L290 TraceCheckUtils]: 25: Hoare triple {94901#(not (= ~T9_E~0 0))} assume !(0 == ~T7_E~0); {94901#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:33,337 INFO L290 TraceCheckUtils]: 26: Hoare triple {94901#(not (= ~T9_E~0 0))} assume !(0 == ~T8_E~0); {94901#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:33,337 INFO L290 TraceCheckUtils]: 27: Hoare triple {94901#(not (= ~T9_E~0 0))} assume 0 == ~T9_E~0;~T9_E~0 := 1; {94899#false} is VALID [2022-02-21 04:23:33,337 INFO L290 TraceCheckUtils]: 28: Hoare triple {94899#false} assume !(0 == ~T10_E~0); {94899#false} is VALID [2022-02-21 04:23:33,338 INFO L290 TraceCheckUtils]: 29: Hoare triple {94899#false} assume !(0 == ~T11_E~0); {94899#false} is VALID [2022-02-21 04:23:33,338 INFO L290 TraceCheckUtils]: 30: Hoare triple {94899#false} assume !(0 == ~T12_E~0); {94899#false} is VALID [2022-02-21 04:23:33,338 INFO L290 TraceCheckUtils]: 31: Hoare triple {94899#false} assume !(0 == ~E_M~0); {94899#false} is VALID [2022-02-21 04:23:33,338 INFO L290 TraceCheckUtils]: 32: Hoare triple {94899#false} assume !(0 == ~E_1~0); {94899#false} is VALID [2022-02-21 04:23:33,338 INFO L290 TraceCheckUtils]: 33: Hoare triple {94899#false} assume !(0 == ~E_2~0); {94899#false} is VALID [2022-02-21 04:23:33,338 INFO L290 TraceCheckUtils]: 34: Hoare triple {94899#false} assume !(0 == ~E_3~0); {94899#false} is VALID [2022-02-21 04:23:33,338 INFO L290 TraceCheckUtils]: 35: Hoare triple {94899#false} assume 0 == ~E_4~0;~E_4~0 := 1; {94899#false} is VALID [2022-02-21 04:23:33,338 INFO L290 TraceCheckUtils]: 36: Hoare triple {94899#false} assume !(0 == ~E_5~0); {94899#false} is VALID [2022-02-21 04:23:33,338 INFO L290 TraceCheckUtils]: 37: Hoare triple {94899#false} assume !(0 == ~E_6~0); {94899#false} is VALID [2022-02-21 04:23:33,339 INFO L290 TraceCheckUtils]: 38: Hoare triple {94899#false} assume !(0 == ~E_7~0); {94899#false} is VALID [2022-02-21 04:23:33,339 INFO L290 TraceCheckUtils]: 39: Hoare triple {94899#false} assume !(0 == ~E_8~0); {94899#false} is VALID [2022-02-21 04:23:33,339 INFO L290 TraceCheckUtils]: 40: Hoare triple {94899#false} assume !(0 == ~E_9~0); {94899#false} is VALID [2022-02-21 04:23:33,339 INFO L290 TraceCheckUtils]: 41: Hoare triple {94899#false} assume !(0 == ~E_10~0); {94899#false} is VALID [2022-02-21 04:23:33,339 INFO L290 TraceCheckUtils]: 42: Hoare triple {94899#false} assume !(0 == ~E_11~0); {94899#false} is VALID [2022-02-21 04:23:33,339 INFO L290 TraceCheckUtils]: 43: Hoare triple {94899#false} assume 0 == ~E_12~0;~E_12~0 := 1; {94899#false} is VALID [2022-02-21 04:23:33,339 INFO L290 TraceCheckUtils]: 44: Hoare triple {94899#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {94899#false} is VALID [2022-02-21 04:23:33,339 INFO L290 TraceCheckUtils]: 45: Hoare triple {94899#false} assume 1 == ~m_pc~0; {94899#false} is VALID [2022-02-21 04:23:33,339 INFO L290 TraceCheckUtils]: 46: Hoare triple {94899#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {94899#false} is VALID [2022-02-21 04:23:33,340 INFO L290 TraceCheckUtils]: 47: Hoare triple {94899#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {94899#false} is VALID [2022-02-21 04:23:33,340 INFO L290 TraceCheckUtils]: 48: Hoare triple {94899#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {94899#false} is VALID [2022-02-21 04:23:33,340 INFO L290 TraceCheckUtils]: 49: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp~1#1); {94899#false} is VALID [2022-02-21 04:23:33,340 INFO L290 TraceCheckUtils]: 50: Hoare triple {94899#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {94899#false} is VALID [2022-02-21 04:23:33,340 INFO L290 TraceCheckUtils]: 51: Hoare triple {94899#false} assume !(1 == ~t1_pc~0); {94899#false} is VALID [2022-02-21 04:23:33,340 INFO L290 TraceCheckUtils]: 52: Hoare triple {94899#false} is_transmit1_triggered_~__retres1~1#1 := 0; {94899#false} is VALID [2022-02-21 04:23:33,340 INFO L290 TraceCheckUtils]: 53: Hoare triple {94899#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {94899#false} is VALID [2022-02-21 04:23:33,340 INFO L290 TraceCheckUtils]: 54: Hoare triple {94899#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {94899#false} is VALID [2022-02-21 04:23:33,340 INFO L290 TraceCheckUtils]: 55: Hoare triple {94899#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {94899#false} is VALID [2022-02-21 04:23:33,341 INFO L290 TraceCheckUtils]: 56: Hoare triple {94899#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {94899#false} is VALID [2022-02-21 04:23:33,341 INFO L290 TraceCheckUtils]: 57: Hoare triple {94899#false} assume 1 == ~t2_pc~0; {94899#false} is VALID [2022-02-21 04:23:33,341 INFO L290 TraceCheckUtils]: 58: Hoare triple {94899#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {94899#false} is VALID [2022-02-21 04:23:33,341 INFO L290 TraceCheckUtils]: 59: Hoare triple {94899#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {94899#false} is VALID [2022-02-21 04:23:33,341 INFO L290 TraceCheckUtils]: 60: Hoare triple {94899#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {94899#false} is VALID [2022-02-21 04:23:33,341 INFO L290 TraceCheckUtils]: 61: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp___1~0#1); {94899#false} is VALID [2022-02-21 04:23:33,341 INFO L290 TraceCheckUtils]: 62: Hoare triple {94899#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {94899#false} is VALID [2022-02-21 04:23:33,341 INFO L290 TraceCheckUtils]: 63: Hoare triple {94899#false} assume !(1 == ~t3_pc~0); {94899#false} is VALID [2022-02-21 04:23:33,341 INFO L290 TraceCheckUtils]: 64: Hoare triple {94899#false} is_transmit3_triggered_~__retres1~3#1 := 0; {94899#false} is VALID [2022-02-21 04:23:33,342 INFO L290 TraceCheckUtils]: 65: Hoare triple {94899#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {94899#false} is VALID [2022-02-21 04:23:33,342 INFO L290 TraceCheckUtils]: 66: Hoare triple {94899#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {94899#false} is VALID [2022-02-21 04:23:33,342 INFO L290 TraceCheckUtils]: 67: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp___2~0#1); {94899#false} is VALID [2022-02-21 04:23:33,342 INFO L290 TraceCheckUtils]: 68: Hoare triple {94899#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {94899#false} is VALID [2022-02-21 04:23:33,342 INFO L290 TraceCheckUtils]: 69: Hoare triple {94899#false} assume 1 == ~t4_pc~0; {94899#false} is VALID [2022-02-21 04:23:33,342 INFO L290 TraceCheckUtils]: 70: Hoare triple {94899#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {94899#false} is VALID [2022-02-21 04:23:33,342 INFO L290 TraceCheckUtils]: 71: Hoare triple {94899#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {94899#false} is VALID [2022-02-21 04:23:33,342 INFO L290 TraceCheckUtils]: 72: Hoare triple {94899#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {94899#false} is VALID [2022-02-21 04:23:33,342 INFO L290 TraceCheckUtils]: 73: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp___3~0#1); {94899#false} is VALID [2022-02-21 04:23:33,343 INFO L290 TraceCheckUtils]: 74: Hoare triple {94899#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {94899#false} is VALID [2022-02-21 04:23:33,343 INFO L290 TraceCheckUtils]: 75: Hoare triple {94899#false} assume !(1 == ~t5_pc~0); {94899#false} is VALID [2022-02-21 04:23:33,343 INFO L290 TraceCheckUtils]: 76: Hoare triple {94899#false} is_transmit5_triggered_~__retres1~5#1 := 0; {94899#false} is VALID [2022-02-21 04:23:33,343 INFO L290 TraceCheckUtils]: 77: Hoare triple {94899#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {94899#false} is VALID [2022-02-21 04:23:33,343 INFO L290 TraceCheckUtils]: 78: Hoare triple {94899#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {94899#false} is VALID [2022-02-21 04:23:33,343 INFO L290 TraceCheckUtils]: 79: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp___4~0#1); {94899#false} is VALID [2022-02-21 04:23:33,343 INFO L290 TraceCheckUtils]: 80: Hoare triple {94899#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {94899#false} is VALID [2022-02-21 04:23:33,343 INFO L290 TraceCheckUtils]: 81: Hoare triple {94899#false} assume 1 == ~t6_pc~0; {94899#false} is VALID [2022-02-21 04:23:33,343 INFO L290 TraceCheckUtils]: 82: Hoare triple {94899#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {94899#false} is VALID [2022-02-21 04:23:33,344 INFO L290 TraceCheckUtils]: 83: Hoare triple {94899#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {94899#false} is VALID [2022-02-21 04:23:33,344 INFO L290 TraceCheckUtils]: 84: Hoare triple {94899#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {94899#false} is VALID [2022-02-21 04:23:33,344 INFO L290 TraceCheckUtils]: 85: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp___5~0#1); {94899#false} is VALID [2022-02-21 04:23:33,344 INFO L290 TraceCheckUtils]: 86: Hoare triple {94899#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {94899#false} is VALID [2022-02-21 04:23:33,344 INFO L290 TraceCheckUtils]: 87: Hoare triple {94899#false} assume 1 == ~t7_pc~0; {94899#false} is VALID [2022-02-21 04:23:33,344 INFO L290 TraceCheckUtils]: 88: Hoare triple {94899#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {94899#false} is VALID [2022-02-21 04:23:33,344 INFO L290 TraceCheckUtils]: 89: Hoare triple {94899#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {94899#false} is VALID [2022-02-21 04:23:33,344 INFO L290 TraceCheckUtils]: 90: Hoare triple {94899#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {94899#false} is VALID [2022-02-21 04:23:33,344 INFO L290 TraceCheckUtils]: 91: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp___6~0#1); {94899#false} is VALID [2022-02-21 04:23:33,345 INFO L290 TraceCheckUtils]: 92: Hoare triple {94899#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {94899#false} is VALID [2022-02-21 04:23:33,345 INFO L290 TraceCheckUtils]: 93: Hoare triple {94899#false} assume !(1 == ~t8_pc~0); {94899#false} is VALID [2022-02-21 04:23:33,345 INFO L290 TraceCheckUtils]: 94: Hoare triple {94899#false} is_transmit8_triggered_~__retres1~8#1 := 0; {94899#false} is VALID [2022-02-21 04:23:33,345 INFO L290 TraceCheckUtils]: 95: Hoare triple {94899#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {94899#false} is VALID [2022-02-21 04:23:33,345 INFO L290 TraceCheckUtils]: 96: Hoare triple {94899#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {94899#false} is VALID [2022-02-21 04:23:33,345 INFO L290 TraceCheckUtils]: 97: Hoare triple {94899#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {94899#false} is VALID [2022-02-21 04:23:33,345 INFO L290 TraceCheckUtils]: 98: Hoare triple {94899#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {94899#false} is VALID [2022-02-21 04:23:33,345 INFO L290 TraceCheckUtils]: 99: Hoare triple {94899#false} assume 1 == ~t9_pc~0; {94899#false} is VALID [2022-02-21 04:23:33,345 INFO L290 TraceCheckUtils]: 100: Hoare triple {94899#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {94899#false} is VALID [2022-02-21 04:23:33,346 INFO L290 TraceCheckUtils]: 101: Hoare triple {94899#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {94899#false} is VALID [2022-02-21 04:23:33,346 INFO L290 TraceCheckUtils]: 102: Hoare triple {94899#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {94899#false} is VALID [2022-02-21 04:23:33,346 INFO L290 TraceCheckUtils]: 103: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp___8~0#1); {94899#false} is VALID [2022-02-21 04:23:33,346 INFO L290 TraceCheckUtils]: 104: Hoare triple {94899#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {94899#false} is VALID [2022-02-21 04:23:33,346 INFO L290 TraceCheckUtils]: 105: Hoare triple {94899#false} assume !(1 == ~t10_pc~0); {94899#false} is VALID [2022-02-21 04:23:33,346 INFO L290 TraceCheckUtils]: 106: Hoare triple {94899#false} is_transmit10_triggered_~__retres1~10#1 := 0; {94899#false} is VALID [2022-02-21 04:23:33,346 INFO L290 TraceCheckUtils]: 107: Hoare triple {94899#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {94899#false} is VALID [2022-02-21 04:23:33,346 INFO L290 TraceCheckUtils]: 108: Hoare triple {94899#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {94899#false} is VALID [2022-02-21 04:23:33,346 INFO L290 TraceCheckUtils]: 109: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp___9~0#1); {94899#false} is VALID [2022-02-21 04:23:33,347 INFO L290 TraceCheckUtils]: 110: Hoare triple {94899#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {94899#false} is VALID [2022-02-21 04:23:33,347 INFO L290 TraceCheckUtils]: 111: Hoare triple {94899#false} assume 1 == ~t11_pc~0; {94899#false} is VALID [2022-02-21 04:23:33,347 INFO L290 TraceCheckUtils]: 112: Hoare triple {94899#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {94899#false} is VALID [2022-02-21 04:23:33,347 INFO L290 TraceCheckUtils]: 113: Hoare triple {94899#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {94899#false} is VALID [2022-02-21 04:23:33,347 INFO L290 TraceCheckUtils]: 114: Hoare triple {94899#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {94899#false} is VALID [2022-02-21 04:23:33,347 INFO L290 TraceCheckUtils]: 115: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp___10~0#1); {94899#false} is VALID [2022-02-21 04:23:33,347 INFO L290 TraceCheckUtils]: 116: Hoare triple {94899#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {94899#false} is VALID [2022-02-21 04:23:33,347 INFO L290 TraceCheckUtils]: 117: Hoare triple {94899#false} assume !(1 == ~t12_pc~0); {94899#false} is VALID [2022-02-21 04:23:33,347 INFO L290 TraceCheckUtils]: 118: Hoare triple {94899#false} is_transmit12_triggered_~__retres1~12#1 := 0; {94899#false} is VALID [2022-02-21 04:23:33,348 INFO L290 TraceCheckUtils]: 119: Hoare triple {94899#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {94899#false} is VALID [2022-02-21 04:23:33,348 INFO L290 TraceCheckUtils]: 120: Hoare triple {94899#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {94899#false} is VALID [2022-02-21 04:23:33,348 INFO L290 TraceCheckUtils]: 121: Hoare triple {94899#false} assume !(0 != activate_threads_~tmp___11~0#1); {94899#false} is VALID [2022-02-21 04:23:33,348 INFO L290 TraceCheckUtils]: 122: Hoare triple {94899#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {94899#false} is VALID [2022-02-21 04:23:33,348 INFO L290 TraceCheckUtils]: 123: Hoare triple {94899#false} assume !(1 == ~M_E~0); {94899#false} is VALID [2022-02-21 04:23:33,348 INFO L290 TraceCheckUtils]: 124: Hoare triple {94899#false} assume !(1 == ~T1_E~0); {94899#false} is VALID [2022-02-21 04:23:33,348 INFO L290 TraceCheckUtils]: 125: Hoare triple {94899#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {94899#false} is VALID [2022-02-21 04:23:33,348 INFO L290 TraceCheckUtils]: 126: Hoare triple {94899#false} assume !(1 == ~T3_E~0); {94899#false} is VALID [2022-02-21 04:23:33,348 INFO L290 TraceCheckUtils]: 127: Hoare triple {94899#false} assume !(1 == ~T4_E~0); {94899#false} is VALID [2022-02-21 04:23:33,349 INFO L290 TraceCheckUtils]: 128: Hoare triple {94899#false} assume !(1 == ~T5_E~0); {94899#false} is VALID [2022-02-21 04:23:33,349 INFO L290 TraceCheckUtils]: 129: Hoare triple {94899#false} assume !(1 == ~T6_E~0); {94899#false} is VALID [2022-02-21 04:23:33,349 INFO L290 TraceCheckUtils]: 130: Hoare triple {94899#false} assume !(1 == ~T7_E~0); {94899#false} is VALID [2022-02-21 04:23:33,349 INFO L290 TraceCheckUtils]: 131: Hoare triple {94899#false} assume !(1 == ~T8_E~0); {94899#false} is VALID [2022-02-21 04:23:33,349 INFO L290 TraceCheckUtils]: 132: Hoare triple {94899#false} assume !(1 == ~T9_E~0); {94899#false} is VALID [2022-02-21 04:23:33,349 INFO L290 TraceCheckUtils]: 133: Hoare triple {94899#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {94899#false} is VALID [2022-02-21 04:23:33,349 INFO L290 TraceCheckUtils]: 134: Hoare triple {94899#false} assume !(1 == ~T11_E~0); {94899#false} is VALID [2022-02-21 04:23:33,349 INFO L290 TraceCheckUtils]: 135: Hoare triple {94899#false} assume !(1 == ~T12_E~0); {94899#false} is VALID [2022-02-21 04:23:33,349 INFO L290 TraceCheckUtils]: 136: Hoare triple {94899#false} assume !(1 == ~E_M~0); {94899#false} is VALID [2022-02-21 04:23:33,350 INFO L290 TraceCheckUtils]: 137: Hoare triple {94899#false} assume !(1 == ~E_1~0); {94899#false} is VALID [2022-02-21 04:23:33,350 INFO L290 TraceCheckUtils]: 138: Hoare triple {94899#false} assume !(1 == ~E_2~0); {94899#false} is VALID [2022-02-21 04:23:33,350 INFO L290 TraceCheckUtils]: 139: Hoare triple {94899#false} assume !(1 == ~E_3~0); {94899#false} is VALID [2022-02-21 04:23:33,350 INFO L290 TraceCheckUtils]: 140: Hoare triple {94899#false} assume !(1 == ~E_4~0); {94899#false} is VALID [2022-02-21 04:23:33,350 INFO L290 TraceCheckUtils]: 141: Hoare triple {94899#false} assume 1 == ~E_5~0;~E_5~0 := 2; {94899#false} is VALID [2022-02-21 04:23:33,350 INFO L290 TraceCheckUtils]: 142: Hoare triple {94899#false} assume !(1 == ~E_6~0); {94899#false} is VALID [2022-02-21 04:23:33,350 INFO L290 TraceCheckUtils]: 143: Hoare triple {94899#false} assume !(1 == ~E_7~0); {94899#false} is VALID [2022-02-21 04:23:33,350 INFO L290 TraceCheckUtils]: 144: Hoare triple {94899#false} assume !(1 == ~E_8~0); {94899#false} is VALID [2022-02-21 04:23:33,350 INFO L290 TraceCheckUtils]: 145: Hoare triple {94899#false} assume !(1 == ~E_9~0); {94899#false} is VALID [2022-02-21 04:23:33,350 INFO L290 TraceCheckUtils]: 146: Hoare triple {94899#false} assume !(1 == ~E_10~0); {94899#false} is VALID [2022-02-21 04:23:33,351 INFO L290 TraceCheckUtils]: 147: Hoare triple {94899#false} assume !(1 == ~E_11~0); {94899#false} is VALID [2022-02-21 04:23:33,351 INFO L290 TraceCheckUtils]: 148: Hoare triple {94899#false} assume !(1 == ~E_12~0); {94899#false} is VALID [2022-02-21 04:23:33,351 INFO L290 TraceCheckUtils]: 149: Hoare triple {94899#false} assume { :end_inline_reset_delta_events } true; {94899#false} is VALID [2022-02-21 04:23:33,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:33,351 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:33,351 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1104476742] [2022-02-21 04:23:33,352 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1104476742] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:33,352 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:33,352 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:33,352 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397348376] [2022-02-21 04:23:33,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:33,353 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:33,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:33,354 INFO L85 PathProgramCache]: Analyzing trace with hash -1158098794, now seen corresponding path program 1 times [2022-02-21 04:23:33,354 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:33,354 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932526477] [2022-02-21 04:23:33,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:33,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:33,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:33,382 INFO L290 TraceCheckUtils]: 0: Hoare triple {94902#true} assume !false; {94902#true} is VALID [2022-02-21 04:23:33,382 INFO L290 TraceCheckUtils]: 1: Hoare triple {94902#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {94902#true} is VALID [2022-02-21 04:23:33,382 INFO L290 TraceCheckUtils]: 2: Hoare triple {94902#true} assume !false; {94902#true} is VALID [2022-02-21 04:23:33,382 INFO L290 TraceCheckUtils]: 3: Hoare triple {94902#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {94902#true} is VALID [2022-02-21 04:23:33,382 INFO L290 TraceCheckUtils]: 4: Hoare triple {94902#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {94902#true} is VALID [2022-02-21 04:23:33,382 INFO L290 TraceCheckUtils]: 5: Hoare triple {94902#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {94902#true} is VALID [2022-02-21 04:23:33,383 INFO L290 TraceCheckUtils]: 6: Hoare triple {94902#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {94902#true} is VALID [2022-02-21 04:23:33,383 INFO L290 TraceCheckUtils]: 7: Hoare triple {94902#true} assume !(0 != eval_~tmp~0#1); {94902#true} is VALID [2022-02-21 04:23:33,383 INFO L290 TraceCheckUtils]: 8: Hoare triple {94902#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {94902#true} is VALID [2022-02-21 04:23:33,383 INFO L290 TraceCheckUtils]: 9: Hoare triple {94902#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {94902#true} is VALID [2022-02-21 04:23:33,383 INFO L290 TraceCheckUtils]: 10: Hoare triple {94902#true} assume 0 == ~M_E~0;~M_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,384 INFO L290 TraceCheckUtils]: 11: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,384 INFO L290 TraceCheckUtils]: 12: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,384 INFO L290 TraceCheckUtils]: 13: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,384 INFO L290 TraceCheckUtils]: 14: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,385 INFO L290 TraceCheckUtils]: 15: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,385 INFO L290 TraceCheckUtils]: 16: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,385 INFO L290 TraceCheckUtils]: 17: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,385 INFO L290 TraceCheckUtils]: 18: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,386 INFO L290 TraceCheckUtils]: 19: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,386 INFO L290 TraceCheckUtils]: 20: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,386 INFO L290 TraceCheckUtils]: 21: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,387 INFO L290 TraceCheckUtils]: 22: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,387 INFO L290 TraceCheckUtils]: 23: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,387 INFO L290 TraceCheckUtils]: 24: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,387 INFO L290 TraceCheckUtils]: 25: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,388 INFO L290 TraceCheckUtils]: 26: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,388 INFO L290 TraceCheckUtils]: 27: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,388 INFO L290 TraceCheckUtils]: 28: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,388 INFO L290 TraceCheckUtils]: 29: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,389 INFO L290 TraceCheckUtils]: 30: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,389 INFO L290 TraceCheckUtils]: 31: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,389 INFO L290 TraceCheckUtils]: 32: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,389 INFO L290 TraceCheckUtils]: 33: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,390 INFO L290 TraceCheckUtils]: 34: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,390 INFO L290 TraceCheckUtils]: 35: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,390 INFO L290 TraceCheckUtils]: 36: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,391 INFO L290 TraceCheckUtils]: 37: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,391 INFO L290 TraceCheckUtils]: 38: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,391 INFO L290 TraceCheckUtils]: 39: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,391 INFO L290 TraceCheckUtils]: 40: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,392 INFO L290 TraceCheckUtils]: 41: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,392 INFO L290 TraceCheckUtils]: 42: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,392 INFO L290 TraceCheckUtils]: 43: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,393 INFO L290 TraceCheckUtils]: 44: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,393 INFO L290 TraceCheckUtils]: 45: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,393 INFO L290 TraceCheckUtils]: 46: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,393 INFO L290 TraceCheckUtils]: 47: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,394 INFO L290 TraceCheckUtils]: 48: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,394 INFO L290 TraceCheckUtils]: 49: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,394 INFO L290 TraceCheckUtils]: 50: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,395 INFO L290 TraceCheckUtils]: 51: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,395 INFO L290 TraceCheckUtils]: 52: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,395 INFO L290 TraceCheckUtils]: 53: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,395 INFO L290 TraceCheckUtils]: 54: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,396 INFO L290 TraceCheckUtils]: 55: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,396 INFO L290 TraceCheckUtils]: 56: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,396 INFO L290 TraceCheckUtils]: 57: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,397 INFO L290 TraceCheckUtils]: 58: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,397 INFO L290 TraceCheckUtils]: 59: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,397 INFO L290 TraceCheckUtils]: 60: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,397 INFO L290 TraceCheckUtils]: 61: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,398 INFO L290 TraceCheckUtils]: 62: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,398 INFO L290 TraceCheckUtils]: 63: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,398 INFO L290 TraceCheckUtils]: 64: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,399 INFO L290 TraceCheckUtils]: 65: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,399 INFO L290 TraceCheckUtils]: 66: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,399 INFO L290 TraceCheckUtils]: 67: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,400 INFO L290 TraceCheckUtils]: 68: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,400 INFO L290 TraceCheckUtils]: 69: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,400 INFO L290 TraceCheckUtils]: 70: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,403 INFO L290 TraceCheckUtils]: 71: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,404 INFO L290 TraceCheckUtils]: 72: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,404 INFO L290 TraceCheckUtils]: 73: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,404 INFO L290 TraceCheckUtils]: 74: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,405 INFO L290 TraceCheckUtils]: 75: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,405 INFO L290 TraceCheckUtils]: 76: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,405 INFO L290 TraceCheckUtils]: 77: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,405 INFO L290 TraceCheckUtils]: 78: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,406 INFO L290 TraceCheckUtils]: 79: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,406 INFO L290 TraceCheckUtils]: 80: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,406 INFO L290 TraceCheckUtils]: 81: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,407 INFO L290 TraceCheckUtils]: 82: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,407 INFO L290 TraceCheckUtils]: 83: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,407 INFO L290 TraceCheckUtils]: 84: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,408 INFO L290 TraceCheckUtils]: 85: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,408 INFO L290 TraceCheckUtils]: 86: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,408 INFO L290 TraceCheckUtils]: 87: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,408 INFO L290 TraceCheckUtils]: 88: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,409 INFO L290 TraceCheckUtils]: 89: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,409 INFO L290 TraceCheckUtils]: 90: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,409 INFO L290 TraceCheckUtils]: 91: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,409 INFO L290 TraceCheckUtils]: 92: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,410 INFO L290 TraceCheckUtils]: 93: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,410 INFO L290 TraceCheckUtils]: 94: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,410 INFO L290 TraceCheckUtils]: 95: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,411 INFO L290 TraceCheckUtils]: 96: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,411 INFO L290 TraceCheckUtils]: 97: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,411 INFO L290 TraceCheckUtils]: 98: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,411 INFO L290 TraceCheckUtils]: 99: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,412 INFO L290 TraceCheckUtils]: 100: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,412 INFO L290 TraceCheckUtils]: 101: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,412 INFO L290 TraceCheckUtils]: 102: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,413 INFO L290 TraceCheckUtils]: 103: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,413 INFO L290 TraceCheckUtils]: 104: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,413 INFO L290 TraceCheckUtils]: 105: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,413 INFO L290 TraceCheckUtils]: 106: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,414 INFO L290 TraceCheckUtils]: 107: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,414 INFO L290 TraceCheckUtils]: 108: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,414 INFO L290 TraceCheckUtils]: 109: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,415 INFO L290 TraceCheckUtils]: 110: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,415 INFO L290 TraceCheckUtils]: 111: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,415 INFO L290 TraceCheckUtils]: 112: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,415 INFO L290 TraceCheckUtils]: 113: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,416 INFO L290 TraceCheckUtils]: 114: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {94904#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:33,416 INFO L290 TraceCheckUtils]: 115: Hoare triple {94904#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {94903#false} is VALID [2022-02-21 04:23:33,416 INFO L290 TraceCheckUtils]: 116: Hoare triple {94903#false} assume !(1 == ~T1_E~0); {94903#false} is VALID [2022-02-21 04:23:33,416 INFO L290 TraceCheckUtils]: 117: Hoare triple {94903#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,416 INFO L290 TraceCheckUtils]: 118: Hoare triple {94903#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,416 INFO L290 TraceCheckUtils]: 119: Hoare triple {94903#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,417 INFO L290 TraceCheckUtils]: 120: Hoare triple {94903#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,417 INFO L290 TraceCheckUtils]: 121: Hoare triple {94903#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,417 INFO L290 TraceCheckUtils]: 122: Hoare triple {94903#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,417 INFO L290 TraceCheckUtils]: 123: Hoare triple {94903#false} assume !(1 == ~T8_E~0); {94903#false} is VALID [2022-02-21 04:23:33,417 INFO L290 TraceCheckUtils]: 124: Hoare triple {94903#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,417 INFO L290 TraceCheckUtils]: 125: Hoare triple {94903#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,417 INFO L290 TraceCheckUtils]: 126: Hoare triple {94903#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,417 INFO L290 TraceCheckUtils]: 127: Hoare triple {94903#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,418 INFO L290 TraceCheckUtils]: 128: Hoare triple {94903#false} assume 1 == ~E_M~0;~E_M~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,418 INFO L290 TraceCheckUtils]: 129: Hoare triple {94903#false} assume 1 == ~E_1~0;~E_1~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,418 INFO L290 TraceCheckUtils]: 130: Hoare triple {94903#false} assume 1 == ~E_2~0;~E_2~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,418 INFO L290 TraceCheckUtils]: 131: Hoare triple {94903#false} assume !(1 == ~E_3~0); {94903#false} is VALID [2022-02-21 04:23:33,418 INFO L290 TraceCheckUtils]: 132: Hoare triple {94903#false} assume 1 == ~E_4~0;~E_4~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,418 INFO L290 TraceCheckUtils]: 133: Hoare triple {94903#false} assume 1 == ~E_5~0;~E_5~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,418 INFO L290 TraceCheckUtils]: 134: Hoare triple {94903#false} assume 1 == ~E_6~0;~E_6~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,418 INFO L290 TraceCheckUtils]: 135: Hoare triple {94903#false} assume 1 == ~E_7~0;~E_7~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,418 INFO L290 TraceCheckUtils]: 136: Hoare triple {94903#false} assume 1 == ~E_8~0;~E_8~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,419 INFO L290 TraceCheckUtils]: 137: Hoare triple {94903#false} assume 1 == ~E_9~0;~E_9~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,419 INFO L290 TraceCheckUtils]: 138: Hoare triple {94903#false} assume 1 == ~E_10~0;~E_10~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,419 INFO L290 TraceCheckUtils]: 139: Hoare triple {94903#false} assume !(1 == ~E_11~0); {94903#false} is VALID [2022-02-21 04:23:33,419 INFO L290 TraceCheckUtils]: 140: Hoare triple {94903#false} assume 1 == ~E_12~0;~E_12~0 := 2; {94903#false} is VALID [2022-02-21 04:23:33,419 INFO L290 TraceCheckUtils]: 141: Hoare triple {94903#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {94903#false} is VALID [2022-02-21 04:23:33,419 INFO L290 TraceCheckUtils]: 142: Hoare triple {94903#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {94903#false} is VALID [2022-02-21 04:23:33,419 INFO L290 TraceCheckUtils]: 143: Hoare triple {94903#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {94903#false} is VALID [2022-02-21 04:23:33,419 INFO L290 TraceCheckUtils]: 144: Hoare triple {94903#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {94903#false} is VALID [2022-02-21 04:23:33,420 INFO L290 TraceCheckUtils]: 145: Hoare triple {94903#false} assume !(0 == start_simulation_~tmp~3#1); {94903#false} is VALID [2022-02-21 04:23:33,420 INFO L290 TraceCheckUtils]: 146: Hoare triple {94903#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {94903#false} is VALID [2022-02-21 04:23:33,420 INFO L290 TraceCheckUtils]: 147: Hoare triple {94903#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {94903#false} is VALID [2022-02-21 04:23:33,420 INFO L290 TraceCheckUtils]: 148: Hoare triple {94903#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {94903#false} is VALID [2022-02-21 04:23:33,420 INFO L290 TraceCheckUtils]: 149: Hoare triple {94903#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {94903#false} is VALID [2022-02-21 04:23:33,420 INFO L290 TraceCheckUtils]: 150: Hoare triple {94903#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {94903#false} is VALID [2022-02-21 04:23:33,420 INFO L290 TraceCheckUtils]: 151: Hoare triple {94903#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {94903#false} is VALID [2022-02-21 04:23:33,420 INFO L290 TraceCheckUtils]: 152: Hoare triple {94903#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {94903#false} is VALID [2022-02-21 04:23:33,420 INFO L290 TraceCheckUtils]: 153: Hoare triple {94903#false} assume !(0 != start_simulation_~tmp___0~1#1); {94903#false} is VALID [2022-02-21 04:23:33,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:33,421 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:33,421 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932526477] [2022-02-21 04:23:33,421 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932526477] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:33,421 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:33,421 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:33,422 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760995653] [2022-02-21 04:23:33,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:33,422 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:33,422 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:33,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:33,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:33,423 INFO L87 Difference]: Start difference. First operand 1788 states and 2635 transitions. cyclomatic complexity: 848 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:36,827 INFO L93 Difference]: Finished difference Result 3437 states and 5058 transitions. [2022-02-21 04:23:36,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:36,827 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,912 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:36,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3437 states and 5058 transitions. [2022-02-21 04:23:37,228 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3250 [2022-02-21 04:23:37,574 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3437 states to 3437 states and 5058 transitions. [2022-02-21 04:23:37,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3437 [2022-02-21 04:23:37,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3437 [2022-02-21 04:23:37,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3437 states and 5058 transitions. [2022-02-21 04:23:37,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:37,579 INFO L681 BuchiCegarLoop]: Abstraction has 3437 states and 5058 transitions. [2022-02-21 04:23:37,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3437 states and 5058 transitions. [2022-02-21 04:23:37,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3437 to 3437. [2022-02-21 04:23:37,640 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:37,643 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3437 states and 5058 transitions. Second operand has 3437 states, 3437 states have (on average 1.4716322374163515) internal successors, (5058), 3436 states have internal predecessors, (5058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,645 INFO L74 IsIncluded]: Start isIncluded. First operand 3437 states and 5058 transitions. Second operand has 3437 states, 3437 states have (on average 1.4716322374163515) internal successors, (5058), 3436 states have internal predecessors, (5058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,647 INFO L87 Difference]: Start difference. First operand 3437 states and 5058 transitions. Second operand has 3437 states, 3437 states have (on average 1.4716322374163515) internal successors, (5058), 3436 states have internal predecessors, (5058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:37,911 INFO L93 Difference]: Finished difference Result 3437 states and 5058 transitions. [2022-02-21 04:23:37,911 INFO L276 IsEmpty]: Start isEmpty. Operand 3437 states and 5058 transitions. [2022-02-21 04:23:37,914 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:37,914 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:37,916 INFO L74 IsIncluded]: Start isIncluded. First operand has 3437 states, 3437 states have (on average 1.4716322374163515) internal successors, (5058), 3436 states have internal predecessors, (5058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3437 states and 5058 transitions. [2022-02-21 04:23:37,918 INFO L87 Difference]: Start difference. First operand has 3437 states, 3437 states have (on average 1.4716322374163515) internal successors, (5058), 3436 states have internal predecessors, (5058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3437 states and 5058 transitions. [2022-02-21 04:23:38,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:38,179 INFO L93 Difference]: Finished difference Result 3437 states and 5058 transitions. [2022-02-21 04:23:38,179 INFO L276 IsEmpty]: Start isEmpty. Operand 3437 states and 5058 transitions. [2022-02-21 04:23:38,182 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:38,182 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:38,182 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:38,183 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:38,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3437 states, 3437 states have (on average 1.4716322374163515) internal successors, (5058), 3436 states have internal predecessors, (5058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3437 states to 3437 states and 5058 transitions. [2022-02-21 04:23:38,461 INFO L704 BuchiCegarLoop]: Abstraction has 3437 states and 5058 transitions. [2022-02-21 04:23:38,462 INFO L587 BuchiCegarLoop]: Abstraction has 3437 states and 5058 transitions. [2022-02-21 04:23:38,462 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:23:38,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3437 states and 5058 transitions. [2022-02-21 04:23:38,467 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3250 [2022-02-21 04:23:38,467 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:38,467 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:38,468 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:38,468 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:38,468 INFO L791 eck$LassoCheckResult]: Stem: 99134#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 99135#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 98654#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 98655#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98709#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 100086#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 99143#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98946#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98344#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98345#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 99570#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 99684#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 100169#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 100170#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 99074#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 99075#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 99600#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 99518#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 99109#L1201 assume !(0 == ~M_E~0); 99110#L1201-2 assume !(0 == ~T1_E~0); 99973#L1206-1 assume !(0 == ~T2_E~0); 99959#L1211-1 assume !(0 == ~T3_E~0); 99960#L1216-1 assume !(0 == ~T4_E~0); 98930#L1221-1 assume !(0 == ~T5_E~0); 98931#L1226-1 assume !(0 == ~T6_E~0); 98569#L1231-1 assume !(0 == ~T7_E~0); 98570#L1236-1 assume !(0 == ~T8_E~0); 100000#L1241-1 assume !(0 == ~T9_E~0); 98967#L1246-1 assume !(0 == ~T10_E~0); 98968#L1251-1 assume !(0 == ~T11_E~0); 99107#L1256-1 assume !(0 == ~T12_E~0); 98355#L1261-1 assume !(0 == ~E_M~0); 98356#L1266-1 assume !(0 == ~E_1~0); 100151#L1271-1 assume !(0 == ~E_2~0); 99668#L1276-1 assume !(0 == ~E_3~0); 99669#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 99614#L1286-1 assume !(0 == ~E_5~0); 98820#L1291-1 assume !(0 == ~E_6~0); 98821#L1296-1 assume !(0 == ~E_7~0); 99398#L1301-1 assume !(0 == ~E_8~0); 99399#L1306-1 assume !(0 == ~E_9~0); 99893#L1311-1 assume !(0 == ~E_10~0); 98771#L1316-1 assume !(0 == ~E_11~0); 98772#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 99417#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99418#L593 assume 1 == ~m_pc~0; 99562#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 98661#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100137#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 99625#L1492 assume !(0 != activate_threads_~tmp~1#1); 99626#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99930#L612 assume !(1 == ~t1_pc~0); 99931#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100080#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99044#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 98665#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 98666#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99086#L631 assume 1 == ~t2_pc~0; 99021#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 98442#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98443#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 99281#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 99282#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98738#L650 assume !(1 == ~t3_pc~0); 98739#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 99442#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98662#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 98395#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 98396#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99592#L669 assume 1 == ~t4_pc~0; 99593#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99965#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99073#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 98604#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 98605#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98830#L688 assume !(1 == ~t5_pc~0); 98620#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 98621#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99542#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 99476#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 99477#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 99607#L707 assume 1 == ~t6_pc~0; 100040#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 99251#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99252#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100038#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 99548#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99108#L726 assume 1 == ~t7_pc~0; 99007#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 98705#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 99755#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 100049#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 98474#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 98475#L745 assume !(1 == ~t8_pc~0); 98923#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 98942#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99790#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99329#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 99330#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 99851#L764 assume 1 == ~t9_pc~0; 99106#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 98948#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 99628#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 100119#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 98494#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 98495#L783 assume !(1 == ~t10_pc~0); 98556#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 98557#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 98598#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 98599#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 99062#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 99967#L802 assume 1 == ~t11_pc~0; 99948#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 98439#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 98440#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 98932#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 98933#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 99043#L821 assume !(1 == ~t12_pc~0); 99295#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 99391#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 98444#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 98445#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 100010#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99637#L1339 assume !(1 == ~M_E~0); 99638#L1339-2 assume !(1 == ~T1_E~0); 100051#L1344-1 assume !(1 == ~T2_E~0); 100052#L1349-1 assume !(1 == ~T3_E~0); 99409#L1354-1 assume !(1 == ~T4_E~0); 99410#L1359-1 assume !(1 == ~T5_E~0); 99822#L1364-1 assume !(1 == ~T6_E~0); 98873#L1369-1 assume !(1 == ~T7_E~0); 98874#L1374-1 assume !(1 == ~T8_E~0); 99412#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 99413#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100455#L1389-1 assume !(1 == ~T11_E~0); 100454#L1394-1 assume !(1 == ~T12_E~0); 100453#L1399-1 assume !(1 == ~E_M~0); 100452#L1404-1 assume !(1 == ~E_1~0); 100451#L1409-1 assume !(1 == ~E_2~0); 100450#L1414-1 assume !(1 == ~E_3~0); 100449#L1419-1 assume !(1 == ~E_4~0); 100448#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 100447#L1429-1 assume !(1 == ~E_6~0); 100446#L1434-1 assume !(1 == ~E_7~0); 100445#L1439-1 assume !(1 == ~E_8~0); 100444#L1444-1 assume !(1 == ~E_9~0); 100443#L1449-1 assume !(1 == ~E_10~0); 100442#L1454-1 assume !(1 == ~E_11~0); 100440#L1459-1 assume !(1 == ~E_12~0); 99547#L1464-1 assume { :end_inline_reset_delta_events } true; 98784#L1810-2 [2022-02-21 04:23:38,469 INFO L793 eck$LassoCheckResult]: Loop: 98784#L1810-2 assume !false; 99229#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 100216#L1176 assume !false; 100215#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 100212#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 99767#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 99033#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 99034#L1003 assume !(0 != eval_~tmp~0#1); 100199#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 100109#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100110#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 99654#L1201-5 assume !(0 == ~T1_E~0); 99655#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 100198#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100766#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 100765#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 100764#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 100763#L1231-3 assume !(0 == ~T7_E~0); 100762#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 100761#L1241-3 assume !(0 == ~T9_E~0); 100760#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 100759#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 100758#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 100757#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 100756#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 100755#L1271-3 assume !(0 == ~E_2~0); 100754#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100753#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 100752#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 100751#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 100750#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 100749#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 100748#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 100747#L1311-3 assume !(0 == ~E_10~0); 100746#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 100745#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 100744#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100743#L593-42 assume 1 == ~m_pc~0; 100741#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 100740#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100739#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100738#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 100737#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100736#L612-42 assume 1 == ~t1_pc~0; 100735#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 100733#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100732#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100731#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 100730#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100728#L631-42 assume !(1 == ~t2_pc~0); 100725#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 100722#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100720#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100718#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100716#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100714#L650-42 assume 1 == ~t3_pc~0; 100711#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 100708#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100706#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100704#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100702#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100700#L669-42 assume !(1 == ~t4_pc~0); 100697#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 100694#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100692#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100690#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 100688#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100686#L688-42 assume !(1 == ~t5_pc~0); 100683#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 100680#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100679#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 100678#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100677#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100676#L707-42 assume !(1 == ~t6_pc~0); 100675#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 100673#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100672#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100671#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 100670#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100669#L726-42 assume 1 == ~t7_pc~0; 100667#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 100666#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100665#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 100664#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 100663#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100662#L745-42 assume 1 == ~t8_pc~0; 100661#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 100659#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100658#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 100657#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 100656#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100655#L764-42 assume 1 == ~t9_pc~0; 100653#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 100652#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100651#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 100650#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 100649#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 100648#L783-42 assume 1 == ~t10_pc~0; 100647#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 100645#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 100644#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 100643#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 100642#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100641#L802-42 assume !(1 == ~t11_pc~0); 100640#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 100638#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 100637#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 100636#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 100635#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 100634#L821-42 assume 1 == ~t12_pc~0; 100633#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 100631#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 100630#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 100629#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 100628#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100627#L1339-3 assume !(1 == ~M_E~0); 100626#L1339-5 assume !(1 == ~T1_E~0); 100625#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 99644#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100624#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100623#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 100622#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100621#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 100620#L1374-3 assume !(1 == ~T8_E~0); 100619#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 98827#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100618#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 100617#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 100616#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 100615#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 100614#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 100613#L1414-3 assume !(1 == ~E_3~0); 100612#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 100611#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 100610#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 100609#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 100608#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 100607#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 100606#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 100605#L1454-3 assume !(1 == ~E_11~0); 100604#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 100603#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 100596#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 100589#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 100588#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 100513#L1829 assume !(0 == start_simulation_~tmp~3#1); 100511#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 100469#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 100464#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 100462#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 100460#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 100458#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 100456#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 98783#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 98784#L1810-2 [2022-02-21 04:23:38,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:38,469 INFO L85 PathProgramCache]: Analyzing trace with hash 907144632, now seen corresponding path program 1 times [2022-02-21 04:23:38,470 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:38,470 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054689370] [2022-02-21 04:23:38,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:38,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:38,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:38,493 INFO L290 TraceCheckUtils]: 0: Hoare triple {108658#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,493 INFO L290 TraceCheckUtils]: 1: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,494 INFO L290 TraceCheckUtils]: 2: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,494 INFO L290 TraceCheckUtils]: 3: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,494 INFO L290 TraceCheckUtils]: 4: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,494 INFO L290 TraceCheckUtils]: 5: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,495 INFO L290 TraceCheckUtils]: 6: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,495 INFO L290 TraceCheckUtils]: 7: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,495 INFO L290 TraceCheckUtils]: 8: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,495 INFO L290 TraceCheckUtils]: 9: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,495 INFO L290 TraceCheckUtils]: 10: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,496 INFO L290 TraceCheckUtils]: 11: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,496 INFO L290 TraceCheckUtils]: 12: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,496 INFO L290 TraceCheckUtils]: 13: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,496 INFO L290 TraceCheckUtils]: 14: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,497 INFO L290 TraceCheckUtils]: 15: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,497 INFO L290 TraceCheckUtils]: 16: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,497 INFO L290 TraceCheckUtils]: 17: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,497 INFO L290 TraceCheckUtils]: 18: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume !(0 == ~M_E~0); {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,498 INFO L290 TraceCheckUtils]: 19: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume !(0 == ~T1_E~0); {108660#(= ~T2_E~0 ~E_4~0)} is VALID [2022-02-21 04:23:38,498 INFO L290 TraceCheckUtils]: 20: Hoare triple {108660#(= ~T2_E~0 ~E_4~0)} assume !(0 == ~T2_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,498 INFO L290 TraceCheckUtils]: 21: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~T3_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,498 INFO L290 TraceCheckUtils]: 22: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~T4_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,499 INFO L290 TraceCheckUtils]: 23: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~T5_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,499 INFO L290 TraceCheckUtils]: 24: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~T6_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,499 INFO L290 TraceCheckUtils]: 25: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~T7_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,499 INFO L290 TraceCheckUtils]: 26: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~T8_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,500 INFO L290 TraceCheckUtils]: 27: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~T9_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,500 INFO L290 TraceCheckUtils]: 28: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~T10_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,500 INFO L290 TraceCheckUtils]: 29: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~T11_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,500 INFO L290 TraceCheckUtils]: 30: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~T12_E~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,501 INFO L290 TraceCheckUtils]: 31: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~E_M~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,501 INFO L290 TraceCheckUtils]: 32: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~E_1~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,501 INFO L290 TraceCheckUtils]: 33: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~E_2~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,501 INFO L290 TraceCheckUtils]: 34: Hoare triple {108661#(not (= ~E_4~0 0))} assume !(0 == ~E_3~0); {108661#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:38,502 INFO L290 TraceCheckUtils]: 35: Hoare triple {108661#(not (= ~E_4~0 0))} assume 0 == ~E_4~0;~E_4~0 := 1; {108659#false} is VALID [2022-02-21 04:23:38,502 INFO L290 TraceCheckUtils]: 36: Hoare triple {108659#false} assume !(0 == ~E_5~0); {108659#false} is VALID [2022-02-21 04:23:38,502 INFO L290 TraceCheckUtils]: 37: Hoare triple {108659#false} assume !(0 == ~E_6~0); {108659#false} is VALID [2022-02-21 04:23:38,502 INFO L290 TraceCheckUtils]: 38: Hoare triple {108659#false} assume !(0 == ~E_7~0); {108659#false} is VALID [2022-02-21 04:23:38,502 INFO L290 TraceCheckUtils]: 39: Hoare triple {108659#false} assume !(0 == ~E_8~0); {108659#false} is VALID [2022-02-21 04:23:38,502 INFO L290 TraceCheckUtils]: 40: Hoare triple {108659#false} assume !(0 == ~E_9~0); {108659#false} is VALID [2022-02-21 04:23:38,502 INFO L290 TraceCheckUtils]: 41: Hoare triple {108659#false} assume !(0 == ~E_10~0); {108659#false} is VALID [2022-02-21 04:23:38,502 INFO L290 TraceCheckUtils]: 42: Hoare triple {108659#false} assume !(0 == ~E_11~0); {108659#false} is VALID [2022-02-21 04:23:38,502 INFO L290 TraceCheckUtils]: 43: Hoare triple {108659#false} assume 0 == ~E_12~0;~E_12~0 := 1; {108659#false} is VALID [2022-02-21 04:23:38,503 INFO L290 TraceCheckUtils]: 44: Hoare triple {108659#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {108659#false} is VALID [2022-02-21 04:23:38,503 INFO L290 TraceCheckUtils]: 45: Hoare triple {108659#false} assume 1 == ~m_pc~0; {108659#false} is VALID [2022-02-21 04:23:38,503 INFO L290 TraceCheckUtils]: 46: Hoare triple {108659#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {108659#false} is VALID [2022-02-21 04:23:38,503 INFO L290 TraceCheckUtils]: 47: Hoare triple {108659#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {108659#false} is VALID [2022-02-21 04:23:38,503 INFO L290 TraceCheckUtils]: 48: Hoare triple {108659#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {108659#false} is VALID [2022-02-21 04:23:38,503 INFO L290 TraceCheckUtils]: 49: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp~1#1); {108659#false} is VALID [2022-02-21 04:23:38,503 INFO L290 TraceCheckUtils]: 50: Hoare triple {108659#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {108659#false} is VALID [2022-02-21 04:23:38,503 INFO L290 TraceCheckUtils]: 51: Hoare triple {108659#false} assume !(1 == ~t1_pc~0); {108659#false} is VALID [2022-02-21 04:23:38,504 INFO L290 TraceCheckUtils]: 52: Hoare triple {108659#false} is_transmit1_triggered_~__retres1~1#1 := 0; {108659#false} is VALID [2022-02-21 04:23:38,504 INFO L290 TraceCheckUtils]: 53: Hoare triple {108659#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {108659#false} is VALID [2022-02-21 04:23:38,504 INFO L290 TraceCheckUtils]: 54: Hoare triple {108659#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {108659#false} is VALID [2022-02-21 04:23:38,504 INFO L290 TraceCheckUtils]: 55: Hoare triple {108659#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {108659#false} is VALID [2022-02-21 04:23:38,504 INFO L290 TraceCheckUtils]: 56: Hoare triple {108659#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {108659#false} is VALID [2022-02-21 04:23:38,504 INFO L290 TraceCheckUtils]: 57: Hoare triple {108659#false} assume 1 == ~t2_pc~0; {108659#false} is VALID [2022-02-21 04:23:38,504 INFO L290 TraceCheckUtils]: 58: Hoare triple {108659#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {108659#false} is VALID [2022-02-21 04:23:38,504 INFO L290 TraceCheckUtils]: 59: Hoare triple {108659#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {108659#false} is VALID [2022-02-21 04:23:38,505 INFO L290 TraceCheckUtils]: 60: Hoare triple {108659#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {108659#false} is VALID [2022-02-21 04:23:38,505 INFO L290 TraceCheckUtils]: 61: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp___1~0#1); {108659#false} is VALID [2022-02-21 04:23:38,505 INFO L290 TraceCheckUtils]: 62: Hoare triple {108659#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {108659#false} is VALID [2022-02-21 04:23:38,505 INFO L290 TraceCheckUtils]: 63: Hoare triple {108659#false} assume !(1 == ~t3_pc~0); {108659#false} is VALID [2022-02-21 04:23:38,505 INFO L290 TraceCheckUtils]: 64: Hoare triple {108659#false} is_transmit3_triggered_~__retres1~3#1 := 0; {108659#false} is VALID [2022-02-21 04:23:38,505 INFO L290 TraceCheckUtils]: 65: Hoare triple {108659#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {108659#false} is VALID [2022-02-21 04:23:38,505 INFO L290 TraceCheckUtils]: 66: Hoare triple {108659#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {108659#false} is VALID [2022-02-21 04:23:38,505 INFO L290 TraceCheckUtils]: 67: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp___2~0#1); {108659#false} is VALID [2022-02-21 04:23:38,505 INFO L290 TraceCheckUtils]: 68: Hoare triple {108659#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {108659#false} is VALID [2022-02-21 04:23:38,506 INFO L290 TraceCheckUtils]: 69: Hoare triple {108659#false} assume 1 == ~t4_pc~0; {108659#false} is VALID [2022-02-21 04:23:38,506 INFO L290 TraceCheckUtils]: 70: Hoare triple {108659#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {108659#false} is VALID [2022-02-21 04:23:38,506 INFO L290 TraceCheckUtils]: 71: Hoare triple {108659#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {108659#false} is VALID [2022-02-21 04:23:38,506 INFO L290 TraceCheckUtils]: 72: Hoare triple {108659#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {108659#false} is VALID [2022-02-21 04:23:38,506 INFO L290 TraceCheckUtils]: 73: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp___3~0#1); {108659#false} is VALID [2022-02-21 04:23:38,506 INFO L290 TraceCheckUtils]: 74: Hoare triple {108659#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {108659#false} is VALID [2022-02-21 04:23:38,506 INFO L290 TraceCheckUtils]: 75: Hoare triple {108659#false} assume !(1 == ~t5_pc~0); {108659#false} is VALID [2022-02-21 04:23:38,506 INFO L290 TraceCheckUtils]: 76: Hoare triple {108659#false} is_transmit5_triggered_~__retres1~5#1 := 0; {108659#false} is VALID [2022-02-21 04:23:38,506 INFO L290 TraceCheckUtils]: 77: Hoare triple {108659#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {108659#false} is VALID [2022-02-21 04:23:38,507 INFO L290 TraceCheckUtils]: 78: Hoare triple {108659#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {108659#false} is VALID [2022-02-21 04:23:38,507 INFO L290 TraceCheckUtils]: 79: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp___4~0#1); {108659#false} is VALID [2022-02-21 04:23:38,507 INFO L290 TraceCheckUtils]: 80: Hoare triple {108659#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {108659#false} is VALID [2022-02-21 04:23:38,507 INFO L290 TraceCheckUtils]: 81: Hoare triple {108659#false} assume 1 == ~t6_pc~0; {108659#false} is VALID [2022-02-21 04:23:38,507 INFO L290 TraceCheckUtils]: 82: Hoare triple {108659#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {108659#false} is VALID [2022-02-21 04:23:38,507 INFO L290 TraceCheckUtils]: 83: Hoare triple {108659#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {108659#false} is VALID [2022-02-21 04:23:38,507 INFO L290 TraceCheckUtils]: 84: Hoare triple {108659#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {108659#false} is VALID [2022-02-21 04:23:38,507 INFO L290 TraceCheckUtils]: 85: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp___5~0#1); {108659#false} is VALID [2022-02-21 04:23:38,507 INFO L290 TraceCheckUtils]: 86: Hoare triple {108659#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {108659#false} is VALID [2022-02-21 04:23:38,508 INFO L290 TraceCheckUtils]: 87: Hoare triple {108659#false} assume 1 == ~t7_pc~0; {108659#false} is VALID [2022-02-21 04:23:38,508 INFO L290 TraceCheckUtils]: 88: Hoare triple {108659#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {108659#false} is VALID [2022-02-21 04:23:38,508 INFO L290 TraceCheckUtils]: 89: Hoare triple {108659#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {108659#false} is VALID [2022-02-21 04:23:38,508 INFO L290 TraceCheckUtils]: 90: Hoare triple {108659#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {108659#false} is VALID [2022-02-21 04:23:38,508 INFO L290 TraceCheckUtils]: 91: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp___6~0#1); {108659#false} is VALID [2022-02-21 04:23:38,508 INFO L290 TraceCheckUtils]: 92: Hoare triple {108659#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {108659#false} is VALID [2022-02-21 04:23:38,508 INFO L290 TraceCheckUtils]: 93: Hoare triple {108659#false} assume !(1 == ~t8_pc~0); {108659#false} is VALID [2022-02-21 04:23:38,508 INFO L290 TraceCheckUtils]: 94: Hoare triple {108659#false} is_transmit8_triggered_~__retres1~8#1 := 0; {108659#false} is VALID [2022-02-21 04:23:38,508 INFO L290 TraceCheckUtils]: 95: Hoare triple {108659#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {108659#false} is VALID [2022-02-21 04:23:38,508 INFO L290 TraceCheckUtils]: 96: Hoare triple {108659#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {108659#false} is VALID [2022-02-21 04:23:38,509 INFO L290 TraceCheckUtils]: 97: Hoare triple {108659#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {108659#false} is VALID [2022-02-21 04:23:38,509 INFO L290 TraceCheckUtils]: 98: Hoare triple {108659#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {108659#false} is VALID [2022-02-21 04:23:38,509 INFO L290 TraceCheckUtils]: 99: Hoare triple {108659#false} assume 1 == ~t9_pc~0; {108659#false} is VALID [2022-02-21 04:23:38,509 INFO L290 TraceCheckUtils]: 100: Hoare triple {108659#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {108659#false} is VALID [2022-02-21 04:23:38,509 INFO L290 TraceCheckUtils]: 101: Hoare triple {108659#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {108659#false} is VALID [2022-02-21 04:23:38,509 INFO L290 TraceCheckUtils]: 102: Hoare triple {108659#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {108659#false} is VALID [2022-02-21 04:23:38,509 INFO L290 TraceCheckUtils]: 103: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp___8~0#1); {108659#false} is VALID [2022-02-21 04:23:38,509 INFO L290 TraceCheckUtils]: 104: Hoare triple {108659#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {108659#false} is VALID [2022-02-21 04:23:38,509 INFO L290 TraceCheckUtils]: 105: Hoare triple {108659#false} assume !(1 == ~t10_pc~0); {108659#false} is VALID [2022-02-21 04:23:38,510 INFO L290 TraceCheckUtils]: 106: Hoare triple {108659#false} is_transmit10_triggered_~__retres1~10#1 := 0; {108659#false} is VALID [2022-02-21 04:23:38,510 INFO L290 TraceCheckUtils]: 107: Hoare triple {108659#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {108659#false} is VALID [2022-02-21 04:23:38,510 INFO L290 TraceCheckUtils]: 108: Hoare triple {108659#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {108659#false} is VALID [2022-02-21 04:23:38,510 INFO L290 TraceCheckUtils]: 109: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp___9~0#1); {108659#false} is VALID [2022-02-21 04:23:38,510 INFO L290 TraceCheckUtils]: 110: Hoare triple {108659#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {108659#false} is VALID [2022-02-21 04:23:38,510 INFO L290 TraceCheckUtils]: 111: Hoare triple {108659#false} assume 1 == ~t11_pc~0; {108659#false} is VALID [2022-02-21 04:23:38,510 INFO L290 TraceCheckUtils]: 112: Hoare triple {108659#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {108659#false} is VALID [2022-02-21 04:23:38,510 INFO L290 TraceCheckUtils]: 113: Hoare triple {108659#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {108659#false} is VALID [2022-02-21 04:23:38,510 INFO L290 TraceCheckUtils]: 114: Hoare triple {108659#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {108659#false} is VALID [2022-02-21 04:23:38,511 INFO L290 TraceCheckUtils]: 115: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp___10~0#1); {108659#false} is VALID [2022-02-21 04:23:38,511 INFO L290 TraceCheckUtils]: 116: Hoare triple {108659#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {108659#false} is VALID [2022-02-21 04:23:38,511 INFO L290 TraceCheckUtils]: 117: Hoare triple {108659#false} assume !(1 == ~t12_pc~0); {108659#false} is VALID [2022-02-21 04:23:38,511 INFO L290 TraceCheckUtils]: 118: Hoare triple {108659#false} is_transmit12_triggered_~__retres1~12#1 := 0; {108659#false} is VALID [2022-02-21 04:23:38,511 INFO L290 TraceCheckUtils]: 119: Hoare triple {108659#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {108659#false} is VALID [2022-02-21 04:23:38,511 INFO L290 TraceCheckUtils]: 120: Hoare triple {108659#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {108659#false} is VALID [2022-02-21 04:23:38,511 INFO L290 TraceCheckUtils]: 121: Hoare triple {108659#false} assume !(0 != activate_threads_~tmp___11~0#1); {108659#false} is VALID [2022-02-21 04:23:38,511 INFO L290 TraceCheckUtils]: 122: Hoare triple {108659#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {108659#false} is VALID [2022-02-21 04:23:38,511 INFO L290 TraceCheckUtils]: 123: Hoare triple {108659#false} assume !(1 == ~M_E~0); {108659#false} is VALID [2022-02-21 04:23:38,512 INFO L290 TraceCheckUtils]: 124: Hoare triple {108659#false} assume !(1 == ~T1_E~0); {108659#false} is VALID [2022-02-21 04:23:38,512 INFO L290 TraceCheckUtils]: 125: Hoare triple {108659#false} assume !(1 == ~T2_E~0); {108659#false} is VALID [2022-02-21 04:23:38,512 INFO L290 TraceCheckUtils]: 126: Hoare triple {108659#false} assume !(1 == ~T3_E~0); {108659#false} is VALID [2022-02-21 04:23:38,512 INFO L290 TraceCheckUtils]: 127: Hoare triple {108659#false} assume !(1 == ~T4_E~0); {108659#false} is VALID [2022-02-21 04:23:38,512 INFO L290 TraceCheckUtils]: 128: Hoare triple {108659#false} assume !(1 == ~T5_E~0); {108659#false} is VALID [2022-02-21 04:23:38,512 INFO L290 TraceCheckUtils]: 129: Hoare triple {108659#false} assume !(1 == ~T6_E~0); {108659#false} is VALID [2022-02-21 04:23:38,512 INFO L290 TraceCheckUtils]: 130: Hoare triple {108659#false} assume !(1 == ~T7_E~0); {108659#false} is VALID [2022-02-21 04:23:38,512 INFO L290 TraceCheckUtils]: 131: Hoare triple {108659#false} assume !(1 == ~T8_E~0); {108659#false} is VALID [2022-02-21 04:23:38,512 INFO L290 TraceCheckUtils]: 132: Hoare triple {108659#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {108659#false} is VALID [2022-02-21 04:23:38,513 INFO L290 TraceCheckUtils]: 133: Hoare triple {108659#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {108659#false} is VALID [2022-02-21 04:23:38,513 INFO L290 TraceCheckUtils]: 134: Hoare triple {108659#false} assume !(1 == ~T11_E~0); {108659#false} is VALID [2022-02-21 04:23:38,513 INFO L290 TraceCheckUtils]: 135: Hoare triple {108659#false} assume !(1 == ~T12_E~0); {108659#false} is VALID [2022-02-21 04:23:38,513 INFO L290 TraceCheckUtils]: 136: Hoare triple {108659#false} assume !(1 == ~E_M~0); {108659#false} is VALID [2022-02-21 04:23:38,513 INFO L290 TraceCheckUtils]: 137: Hoare triple {108659#false} assume !(1 == ~E_1~0); {108659#false} is VALID [2022-02-21 04:23:38,513 INFO L290 TraceCheckUtils]: 138: Hoare triple {108659#false} assume !(1 == ~E_2~0); {108659#false} is VALID [2022-02-21 04:23:38,513 INFO L290 TraceCheckUtils]: 139: Hoare triple {108659#false} assume !(1 == ~E_3~0); {108659#false} is VALID [2022-02-21 04:23:38,513 INFO L290 TraceCheckUtils]: 140: Hoare triple {108659#false} assume !(1 == ~E_4~0); {108659#false} is VALID [2022-02-21 04:23:38,513 INFO L290 TraceCheckUtils]: 141: Hoare triple {108659#false} assume 1 == ~E_5~0;~E_5~0 := 2; {108659#false} is VALID [2022-02-21 04:23:38,514 INFO L290 TraceCheckUtils]: 142: Hoare triple {108659#false} assume !(1 == ~E_6~0); {108659#false} is VALID [2022-02-21 04:23:38,514 INFO L290 TraceCheckUtils]: 143: Hoare triple {108659#false} assume !(1 == ~E_7~0); {108659#false} is VALID [2022-02-21 04:23:38,514 INFO L290 TraceCheckUtils]: 144: Hoare triple {108659#false} assume !(1 == ~E_8~0); {108659#false} is VALID [2022-02-21 04:23:38,514 INFO L290 TraceCheckUtils]: 145: Hoare triple {108659#false} assume !(1 == ~E_9~0); {108659#false} is VALID [2022-02-21 04:23:38,514 INFO L290 TraceCheckUtils]: 146: Hoare triple {108659#false} assume !(1 == ~E_10~0); {108659#false} is VALID [2022-02-21 04:23:38,514 INFO L290 TraceCheckUtils]: 147: Hoare triple {108659#false} assume !(1 == ~E_11~0); {108659#false} is VALID [2022-02-21 04:23:38,514 INFO L290 TraceCheckUtils]: 148: Hoare triple {108659#false} assume !(1 == ~E_12~0); {108659#false} is VALID [2022-02-21 04:23:38,514 INFO L290 TraceCheckUtils]: 149: Hoare triple {108659#false} assume { :end_inline_reset_delta_events } true; {108659#false} is VALID [2022-02-21 04:23:38,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:38,515 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:38,515 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054689370] [2022-02-21 04:23:38,515 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2054689370] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:38,515 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:38,515 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:38,515 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1548656444] [2022-02-21 04:23:38,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:38,516 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:38,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:38,516 INFO L85 PathProgramCache]: Analyzing trace with hash 579323862, now seen corresponding path program 1 times [2022-02-21 04:23:38,516 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:38,516 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016822543] [2022-02-21 04:23:38,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:38,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:38,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:38,538 INFO L290 TraceCheckUtils]: 0: Hoare triple {108662#true} assume !false; {108662#true} is VALID [2022-02-21 04:23:38,538 INFO L290 TraceCheckUtils]: 1: Hoare triple {108662#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {108662#true} is VALID [2022-02-21 04:23:38,538 INFO L290 TraceCheckUtils]: 2: Hoare triple {108662#true} assume !false; {108662#true} is VALID [2022-02-21 04:23:38,539 INFO L290 TraceCheckUtils]: 3: Hoare triple {108662#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {108662#true} is VALID [2022-02-21 04:23:38,539 INFO L290 TraceCheckUtils]: 4: Hoare triple {108662#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {108662#true} is VALID [2022-02-21 04:23:38,539 INFO L290 TraceCheckUtils]: 5: Hoare triple {108662#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {108662#true} is VALID [2022-02-21 04:23:38,539 INFO L290 TraceCheckUtils]: 6: Hoare triple {108662#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {108662#true} is VALID [2022-02-21 04:23:38,539 INFO L290 TraceCheckUtils]: 7: Hoare triple {108662#true} assume !(0 != eval_~tmp~0#1); {108662#true} is VALID [2022-02-21 04:23:38,539 INFO L290 TraceCheckUtils]: 8: Hoare triple {108662#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {108662#true} is VALID [2022-02-21 04:23:38,539 INFO L290 TraceCheckUtils]: 9: Hoare triple {108662#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {108662#true} is VALID [2022-02-21 04:23:38,540 INFO L290 TraceCheckUtils]: 10: Hoare triple {108662#true} assume 0 == ~M_E~0;~M_E~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,540 INFO L290 TraceCheckUtils]: 11: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,540 INFO L290 TraceCheckUtils]: 12: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,540 INFO L290 TraceCheckUtils]: 13: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,541 INFO L290 TraceCheckUtils]: 14: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,541 INFO L290 TraceCheckUtils]: 15: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,541 INFO L290 TraceCheckUtils]: 16: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,541 INFO L290 TraceCheckUtils]: 17: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,542 INFO L290 TraceCheckUtils]: 18: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,542 INFO L290 TraceCheckUtils]: 19: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,542 INFO L290 TraceCheckUtils]: 20: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,542 INFO L290 TraceCheckUtils]: 21: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,543 INFO L290 TraceCheckUtils]: 22: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,543 INFO L290 TraceCheckUtils]: 23: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,543 INFO L290 TraceCheckUtils]: 24: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,543 INFO L290 TraceCheckUtils]: 25: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,544 INFO L290 TraceCheckUtils]: 26: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,544 INFO L290 TraceCheckUtils]: 27: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,544 INFO L290 TraceCheckUtils]: 28: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,544 INFO L290 TraceCheckUtils]: 29: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,545 INFO L290 TraceCheckUtils]: 30: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,545 INFO L290 TraceCheckUtils]: 31: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,545 INFO L290 TraceCheckUtils]: 32: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,546 INFO L290 TraceCheckUtils]: 33: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,546 INFO L290 TraceCheckUtils]: 34: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,546 INFO L290 TraceCheckUtils]: 35: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,546 INFO L290 TraceCheckUtils]: 36: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,547 INFO L290 TraceCheckUtils]: 37: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,547 INFO L290 TraceCheckUtils]: 38: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,547 INFO L290 TraceCheckUtils]: 39: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,547 INFO L290 TraceCheckUtils]: 40: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,548 INFO L290 TraceCheckUtils]: 41: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,548 INFO L290 TraceCheckUtils]: 42: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,548 INFO L290 TraceCheckUtils]: 43: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,548 INFO L290 TraceCheckUtils]: 44: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,549 INFO L290 TraceCheckUtils]: 45: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,549 INFO L290 TraceCheckUtils]: 46: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,549 INFO L290 TraceCheckUtils]: 47: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,549 INFO L290 TraceCheckUtils]: 48: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,550 INFO L290 TraceCheckUtils]: 49: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,550 INFO L290 TraceCheckUtils]: 50: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,550 INFO L290 TraceCheckUtils]: 51: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,550 INFO L290 TraceCheckUtils]: 52: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,550 INFO L290 TraceCheckUtils]: 53: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,551 INFO L290 TraceCheckUtils]: 54: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,551 INFO L290 TraceCheckUtils]: 55: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,551 INFO L290 TraceCheckUtils]: 56: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,551 INFO L290 TraceCheckUtils]: 57: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,552 INFO L290 TraceCheckUtils]: 58: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,552 INFO L290 TraceCheckUtils]: 59: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,552 INFO L290 TraceCheckUtils]: 60: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,552 INFO L290 TraceCheckUtils]: 61: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,553 INFO L290 TraceCheckUtils]: 62: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,553 INFO L290 TraceCheckUtils]: 63: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,553 INFO L290 TraceCheckUtils]: 64: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,553 INFO L290 TraceCheckUtils]: 65: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,554 INFO L290 TraceCheckUtils]: 66: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,554 INFO L290 TraceCheckUtils]: 67: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,554 INFO L290 TraceCheckUtils]: 68: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,554 INFO L290 TraceCheckUtils]: 69: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,555 INFO L290 TraceCheckUtils]: 70: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,555 INFO L290 TraceCheckUtils]: 71: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,555 INFO L290 TraceCheckUtils]: 72: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,555 INFO L290 TraceCheckUtils]: 73: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,556 INFO L290 TraceCheckUtils]: 74: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,556 INFO L290 TraceCheckUtils]: 75: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,556 INFO L290 TraceCheckUtils]: 76: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,556 INFO L290 TraceCheckUtils]: 77: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,557 INFO L290 TraceCheckUtils]: 78: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,557 INFO L290 TraceCheckUtils]: 79: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,557 INFO L290 TraceCheckUtils]: 80: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,557 INFO L290 TraceCheckUtils]: 81: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,558 INFO L290 TraceCheckUtils]: 82: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,558 INFO L290 TraceCheckUtils]: 83: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,558 INFO L290 TraceCheckUtils]: 84: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,558 INFO L290 TraceCheckUtils]: 85: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,558 INFO L290 TraceCheckUtils]: 86: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,559 INFO L290 TraceCheckUtils]: 87: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,559 INFO L290 TraceCheckUtils]: 88: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,559 INFO L290 TraceCheckUtils]: 89: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,559 INFO L290 TraceCheckUtils]: 90: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,560 INFO L290 TraceCheckUtils]: 91: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,560 INFO L290 TraceCheckUtils]: 92: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,560 INFO L290 TraceCheckUtils]: 93: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,560 INFO L290 TraceCheckUtils]: 94: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,561 INFO L290 TraceCheckUtils]: 95: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,561 INFO L290 TraceCheckUtils]: 96: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,561 INFO L290 TraceCheckUtils]: 97: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,561 INFO L290 TraceCheckUtils]: 98: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,562 INFO L290 TraceCheckUtils]: 99: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,562 INFO L290 TraceCheckUtils]: 100: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,562 INFO L290 TraceCheckUtils]: 101: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,562 INFO L290 TraceCheckUtils]: 102: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,563 INFO L290 TraceCheckUtils]: 103: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,563 INFO L290 TraceCheckUtils]: 104: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,563 INFO L290 TraceCheckUtils]: 105: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,563 INFO L290 TraceCheckUtils]: 106: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,564 INFO L290 TraceCheckUtils]: 107: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,564 INFO L290 TraceCheckUtils]: 108: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,564 INFO L290 TraceCheckUtils]: 109: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,565 INFO L290 TraceCheckUtils]: 110: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,565 INFO L290 TraceCheckUtils]: 111: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,565 INFO L290 TraceCheckUtils]: 112: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,565 INFO L290 TraceCheckUtils]: 113: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,566 INFO L290 TraceCheckUtils]: 114: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {108664#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:38,566 INFO L290 TraceCheckUtils]: 115: Hoare triple {108664#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {108663#false} is VALID [2022-02-21 04:23:38,566 INFO L290 TraceCheckUtils]: 116: Hoare triple {108663#false} assume !(1 == ~T1_E~0); {108663#false} is VALID [2022-02-21 04:23:38,566 INFO L290 TraceCheckUtils]: 117: Hoare triple {108663#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,566 INFO L290 TraceCheckUtils]: 118: Hoare triple {108663#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,566 INFO L290 TraceCheckUtils]: 119: Hoare triple {108663#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,566 INFO L290 TraceCheckUtils]: 120: Hoare triple {108663#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,566 INFO L290 TraceCheckUtils]: 121: Hoare triple {108663#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,567 INFO L290 TraceCheckUtils]: 122: Hoare triple {108663#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,567 INFO L290 TraceCheckUtils]: 123: Hoare triple {108663#false} assume !(1 == ~T8_E~0); {108663#false} is VALID [2022-02-21 04:23:38,567 INFO L290 TraceCheckUtils]: 124: Hoare triple {108663#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,567 INFO L290 TraceCheckUtils]: 125: Hoare triple {108663#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,567 INFO L290 TraceCheckUtils]: 126: Hoare triple {108663#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,567 INFO L290 TraceCheckUtils]: 127: Hoare triple {108663#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,567 INFO L290 TraceCheckUtils]: 128: Hoare triple {108663#false} assume 1 == ~E_M~0;~E_M~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,567 INFO L290 TraceCheckUtils]: 129: Hoare triple {108663#false} assume 1 == ~E_1~0;~E_1~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,568 INFO L290 TraceCheckUtils]: 130: Hoare triple {108663#false} assume 1 == ~E_2~0;~E_2~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,568 INFO L290 TraceCheckUtils]: 131: Hoare triple {108663#false} assume !(1 == ~E_3~0); {108663#false} is VALID [2022-02-21 04:23:38,568 INFO L290 TraceCheckUtils]: 132: Hoare triple {108663#false} assume 1 == ~E_4~0;~E_4~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,568 INFO L290 TraceCheckUtils]: 133: Hoare triple {108663#false} assume 1 == ~E_5~0;~E_5~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,568 INFO L290 TraceCheckUtils]: 134: Hoare triple {108663#false} assume 1 == ~E_6~0;~E_6~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,568 INFO L290 TraceCheckUtils]: 135: Hoare triple {108663#false} assume 1 == ~E_7~0;~E_7~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,568 INFO L290 TraceCheckUtils]: 136: Hoare triple {108663#false} assume 1 == ~E_8~0;~E_8~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,568 INFO L290 TraceCheckUtils]: 137: Hoare triple {108663#false} assume 1 == ~E_9~0;~E_9~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,568 INFO L290 TraceCheckUtils]: 138: Hoare triple {108663#false} assume 1 == ~E_10~0;~E_10~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 139: Hoare triple {108663#false} assume !(1 == ~E_11~0); {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 140: Hoare triple {108663#false} assume 1 == ~E_12~0;~E_12~0 := 2; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 141: Hoare triple {108663#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 142: Hoare triple {108663#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 143: Hoare triple {108663#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 144: Hoare triple {108663#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 145: Hoare triple {108663#false} assume !(0 == start_simulation_~tmp~3#1); {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 146: Hoare triple {108663#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 147: Hoare triple {108663#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 148: Hoare triple {108663#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 149: Hoare triple {108663#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 150: Hoare triple {108663#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 151: Hoare triple {108663#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 152: Hoare triple {108663#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {108663#false} is VALID [2022-02-21 04:23:38,569 INFO L290 TraceCheckUtils]: 153: Hoare triple {108663#false} assume !(0 != start_simulation_~tmp___0~1#1); {108663#false} is VALID [2022-02-21 04:23:38,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:38,570 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:38,570 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2016822543] [2022-02-21 04:23:38,570 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2016822543] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:38,570 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:38,570 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:38,570 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [299879371] [2022-02-21 04:23:38,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:38,571 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:38,571 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:38,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:38,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:38,571 INFO L87 Difference]: Start difference. First operand 3437 states and 5058 transitions. cyclomatic complexity: 1623 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:42,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:42,513 INFO L93 Difference]: Finished difference Result 6529 states and 9599 transitions. [2022-02-21 04:23:42,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:42,513 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:42,605 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:42,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6529 states and 9599 transitions. [2022-02-21 04:23:43,735 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6314 [2022-02-21 04:23:44,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6529 states to 6529 states and 9599 transitions. [2022-02-21 04:23:44,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6529 [2022-02-21 04:23:44,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6529 [2022-02-21 04:23:44,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6529 states and 9599 transitions. [2022-02-21 04:23:44,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:44,708 INFO L681 BuchiCegarLoop]: Abstraction has 6529 states and 9599 transitions. [2022-02-21 04:23:44,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6529 states and 9599 transitions. [2022-02-21 04:23:44,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6529 to 6527. [2022-02-21 04:23:44,800 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:44,808 INFO L82 GeneralOperation]: Start isEquivalent. First operand 6529 states and 9599 transitions. Second operand has 6527 states, 6527 states have (on average 1.4703539145089628) internal successors, (9597), 6526 states have internal predecessors, (9597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:44,816 INFO L74 IsIncluded]: Start isIncluded. First operand 6529 states and 9599 transitions. Second operand has 6527 states, 6527 states have (on average 1.4703539145089628) internal successors, (9597), 6526 states have internal predecessors, (9597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:44,823 INFO L87 Difference]: Start difference. First operand 6529 states and 9599 transitions. Second operand has 6527 states, 6527 states have (on average 1.4703539145089628) internal successors, (9597), 6526 states have internal predecessors, (9597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:45,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:45,827 INFO L93 Difference]: Finished difference Result 6529 states and 9599 transitions. [2022-02-21 04:23:45,827 INFO L276 IsEmpty]: Start isEmpty. Operand 6529 states and 9599 transitions. [2022-02-21 04:23:45,833 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:45,833 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:45,840 INFO L74 IsIncluded]: Start isIncluded. First operand has 6527 states, 6527 states have (on average 1.4703539145089628) internal successors, (9597), 6526 states have internal predecessors, (9597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6529 states and 9599 transitions. [2022-02-21 04:23:45,844 INFO L87 Difference]: Start difference. First operand has 6527 states, 6527 states have (on average 1.4703539145089628) internal successors, (9597), 6526 states have internal predecessors, (9597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6529 states and 9599 transitions. [2022-02-21 04:23:46,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:46,876 INFO L93 Difference]: Finished difference Result 6529 states and 9599 transitions. [2022-02-21 04:23:46,876 INFO L276 IsEmpty]: Start isEmpty. Operand 6529 states and 9599 transitions. [2022-02-21 04:23:46,882 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:46,883 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:46,883 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:46,883 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:46,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6527 states, 6527 states have (on average 1.4703539145089628) internal successors, (9597), 6526 states have internal predecessors, (9597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:48,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6527 states to 6527 states and 9597 transitions. [2022-02-21 04:23:48,007 INFO L704 BuchiCegarLoop]: Abstraction has 6527 states and 9597 transitions. [2022-02-21 04:23:48,007 INFO L587 BuchiCegarLoop]: Abstraction has 6527 states and 9597 transitions. [2022-02-21 04:23:48,007 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:23:48,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6527 states and 9597 transitions. [2022-02-21 04:23:48,019 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6314 [2022-02-21 04:23:48,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:48,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:48,021 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:48,021 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:48,021 INFO L791 eck$LassoCheckResult]: Stem: 115996#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 115997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 115508#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115509#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 115563#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 116980#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 116005#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115801#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115196#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115197#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116446#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 116568#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 117062#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 117063#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 115932#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 115933#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 116475#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 116389#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115969#L1201 assume !(0 == ~M_E~0); 115970#L1201-2 assume !(0 == ~T1_E~0); 116860#L1206-1 assume !(0 == ~T2_E~0); 116843#L1211-1 assume !(0 == ~T3_E~0); 116844#L1216-1 assume !(0 == ~T4_E~0); 115785#L1221-1 assume !(0 == ~T5_E~0); 115786#L1226-1 assume !(0 == ~T6_E~0); 115421#L1231-1 assume !(0 == ~T7_E~0); 115422#L1236-1 assume !(0 == ~T8_E~0); 116893#L1241-1 assume !(0 == ~T9_E~0); 115822#L1246-1 assume !(0 == ~T10_E~0); 115823#L1251-1 assume !(0 == ~T11_E~0); 115967#L1256-1 assume !(0 == ~T12_E~0); 115207#L1261-1 assume !(0 == ~E_M~0); 115208#L1266-1 assume !(0 == ~E_1~0); 117045#L1271-1 assume !(0 == ~E_2~0); 116550#L1276-1 assume !(0 == ~E_3~0); 116551#L1281-1 assume !(0 == ~E_4~0); 116492#L1286-1 assume !(0 == ~E_5~0); 115674#L1291-1 assume !(0 == ~E_6~0); 115675#L1296-1 assume !(0 == ~E_7~0); 116267#L1301-1 assume !(0 == ~E_8~0); 116268#L1306-1 assume !(0 == ~E_9~0); 116773#L1311-1 assume !(0 == ~E_10~0); 115625#L1316-1 assume !(0 == ~E_11~0); 115626#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 116285#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116286#L593 assume 1 == ~m_pc~0; 116438#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 115515#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117031#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116503#L1492 assume !(0 != activate_threads_~tmp~1#1); 116504#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116813#L612 assume !(1 == ~t1_pc~0); 116814#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 116975#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115899#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 115519#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 115520#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115944#L631 assume 1 == ~t2_pc~0; 115876#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 115294#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115295#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 116149#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 116150#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115592#L650 assume !(1 == ~t3_pc~0); 115593#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 116311#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115516#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 115247#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 115248#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116467#L669 assume 1 == ~t4_pc~0; 116468#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 116849#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 115931#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 115456#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 115457#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 115684#L688 assume !(1 == ~t5_pc~0); 115472#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 115473#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116415#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 116346#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 116347#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116485#L707 assume 1 == ~t6_pc~0; 116934#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 116118#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116119#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116932#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 116421#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115968#L726 assume 1 == ~t7_pc~0; 115862#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 115559#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116641#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 116942#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 115326#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 115327#L745 assume !(1 == ~t8_pc~0); 115778#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 115797#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 116674#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 116197#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 116198#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 116734#L764 assume 1 == ~t9_pc~0; 115966#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 115803#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 116506#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 117012#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 115346#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 115347#L783 assume !(1 == ~t10_pc~0); 115408#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 115409#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 115450#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 115451#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 115920#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 116852#L802 assume 1 == ~t11_pc~0; 116832#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 115291#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 115292#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 115787#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 115788#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 115898#L821 assume !(1 == ~t12_pc~0); 116163#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 116260#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 115298#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 115299#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 116902#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116515#L1339 assume !(1 == ~M_E~0); 116516#L1339-2 assume !(1 == ~T1_E~0); 116944#L1344-1 assume !(1 == ~T2_E~0); 116945#L1349-1 assume !(1 == ~T3_E~0); 117310#L1354-1 assume !(1 == ~T4_E~0); 117309#L1359-1 assume !(1 == ~T5_E~0); 117308#L1364-1 assume !(1 == ~T6_E~0); 117307#L1369-1 assume !(1 == ~T7_E~0); 117306#L1374-1 assume !(1 == ~T8_E~0); 117305#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 116383#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 116384#L1389-1 assume !(1 == ~T11_E~0); 116896#L1394-1 assume !(1 == ~T12_E~0); 116897#L1399-1 assume !(1 == ~E_M~0); 117297#L1404-1 assume !(1 == ~E_1~0); 117295#L1409-1 assume !(1 == ~E_2~0); 117293#L1414-1 assume !(1 == ~E_3~0); 117291#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 117289#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 117244#L1429-1 assume !(1 == ~E_6~0); 117195#L1434-1 assume !(1 == ~E_7~0); 117181#L1439-1 assume !(1 == ~E_8~0); 117179#L1444-1 assume !(1 == ~E_9~0); 117166#L1449-1 assume !(1 == ~E_10~0); 117154#L1454-1 assume !(1 == ~E_11~0); 117145#L1459-1 assume !(1 == ~E_12~0); 117135#L1464-1 assume { :end_inline_reset_delta_events } true; 117128#L1810-2 [2022-02-21 04:23:48,022 INFO L793 eck$LassoCheckResult]: Loop: 117128#L1810-2 assume !false; 117125#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117121#L1176 assume !false; 117120#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 117117#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 117106#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117105#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 117103#L1003 assume !(0 != eval_~tmp~0#1); 117102#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117101#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117100#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 117099#L1201-5 assume !(0 == ~T1_E~0); 117097#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117098#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 118969#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 118967#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 118965#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 118963#L1231-3 assume !(0 == ~T7_E~0); 118962#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 118961#L1241-3 assume !(0 == ~T9_E~0); 118901#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 118898#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 118896#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 118895#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 118749#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 118747#L1271-3 assume !(0 == ~E_2~0); 118745#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 118676#L1281-3 assume !(0 == ~E_4~0); 118673#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 118671#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 118670#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 118626#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 118580#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 118578#L1311-3 assume !(0 == ~E_10~0); 118576#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 118573#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 118571#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118504#L593-42 assume 1 == ~m_pc~0; 118425#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 118423#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118421#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 118418#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 118416#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118414#L612-42 assume 1 == ~t1_pc~0; 118368#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 118364#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118362#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 118360#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 118358#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118356#L631-42 assume 1 == ~t2_pc~0; 118353#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 118350#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118348#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 118346#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 118344#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118287#L650-42 assume !(1 == ~t3_pc~0); 118229#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 118226#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118168#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 118166#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 118063#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118060#L669-42 assume !(1 == ~t4_pc~0); 118057#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 118054#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118052#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 118050#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 118049#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118048#L688-42 assume !(1 == ~t5_pc~0); 118047#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 118045#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118044#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 118043#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 118042#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117973#L707-42 assume 1 == ~t6_pc~0; 117971#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 117883#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117881#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 117879#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 117877#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 117792#L726-42 assume 1 == ~t7_pc~0; 117789#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 117787#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117785#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 117783#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 117781#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 117778#L745-42 assume 1 == ~t8_pc~0; 117776#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 117773#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 117771#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 117769#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 117767#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 117764#L764-42 assume 1 == ~t9_pc~0; 117761#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 117759#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117757#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 117755#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 117753#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117750#L783-42 assume !(1 == ~t10_pc~0); 117747#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 117745#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 117743#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 117741#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 117739#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 117738#L802-42 assume 1 == ~t11_pc~0; 117735#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 117732#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 117731#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 117728#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 117726#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 117688#L821-42 assume 1 == ~t12_pc~0; 117635#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 117575#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 117573#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 117571#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 117569#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117567#L1339-3 assume !(1 == ~M_E~0); 117510#L1339-5 assume !(1 == ~T1_E~0); 117508#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116523#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 117506#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117461#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 117457#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 117456#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 117454#L1374-3 assume !(1 == ~T8_E~0); 117452#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 117406#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 117403#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 117401#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 117399#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 117357#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 117355#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 117354#L1414-3 assume !(1 == ~E_3~0); 117353#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 117290#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 117288#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 117285#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 117283#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 117281#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 117279#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 117278#L1454-3 assume !(1 == ~E_11~0); 117277#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 117276#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 117236#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 117228#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117226#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 117218#L1829 assume !(0 == start_simulation_~tmp~3#1); 117217#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 117185#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 117180#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117178#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 117165#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117153#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117144#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 117134#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 117128#L1810-2 [2022-02-21 04:23:48,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:48,022 INFO L85 PathProgramCache]: Analyzing trace with hash -1065863428, now seen corresponding path program 1 times [2022-02-21 04:23:48,023 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:48,023 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503263518] [2022-02-21 04:23:48,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:48,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:48,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:48,053 INFO L290 TraceCheckUtils]: 0: Hoare triple {134784#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,054 INFO L290 TraceCheckUtils]: 1: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,054 INFO L290 TraceCheckUtils]: 2: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,054 INFO L290 TraceCheckUtils]: 3: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,055 INFO L290 TraceCheckUtils]: 4: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,055 INFO L290 TraceCheckUtils]: 5: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,055 INFO L290 TraceCheckUtils]: 6: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,056 INFO L290 TraceCheckUtils]: 7: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,056 INFO L290 TraceCheckUtils]: 8: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,056 INFO L290 TraceCheckUtils]: 9: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,056 INFO L290 TraceCheckUtils]: 10: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,057 INFO L290 TraceCheckUtils]: 11: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,057 INFO L290 TraceCheckUtils]: 12: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,057 INFO L290 TraceCheckUtils]: 13: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,058 INFO L290 TraceCheckUtils]: 14: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,058 INFO L290 TraceCheckUtils]: 15: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,058 INFO L290 TraceCheckUtils]: 16: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,058 INFO L290 TraceCheckUtils]: 17: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,059 INFO L290 TraceCheckUtils]: 18: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume !(0 == ~M_E~0); {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,059 INFO L290 TraceCheckUtils]: 19: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume !(0 == ~T1_E~0); {134786#(= ~E_12~0 ~T2_E~0)} is VALID [2022-02-21 04:23:48,059 INFO L290 TraceCheckUtils]: 20: Hoare triple {134786#(= ~E_12~0 ~T2_E~0)} assume !(0 == ~T2_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,059 INFO L290 TraceCheckUtils]: 21: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~T3_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,060 INFO L290 TraceCheckUtils]: 22: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~T4_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,060 INFO L290 TraceCheckUtils]: 23: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~T5_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,060 INFO L290 TraceCheckUtils]: 24: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~T6_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,060 INFO L290 TraceCheckUtils]: 25: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~T7_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,061 INFO L290 TraceCheckUtils]: 26: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~T8_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,061 INFO L290 TraceCheckUtils]: 27: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~T9_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,061 INFO L290 TraceCheckUtils]: 28: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~T10_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,061 INFO L290 TraceCheckUtils]: 29: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~T11_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,062 INFO L290 TraceCheckUtils]: 30: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~T12_E~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,062 INFO L290 TraceCheckUtils]: 31: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_M~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,062 INFO L290 TraceCheckUtils]: 32: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_1~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,063 INFO L290 TraceCheckUtils]: 33: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_2~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,063 INFO L290 TraceCheckUtils]: 34: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_3~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,063 INFO L290 TraceCheckUtils]: 35: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_4~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,063 INFO L290 TraceCheckUtils]: 36: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_5~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,064 INFO L290 TraceCheckUtils]: 37: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_6~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,064 INFO L290 TraceCheckUtils]: 38: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_7~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,064 INFO L290 TraceCheckUtils]: 39: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_8~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,064 INFO L290 TraceCheckUtils]: 40: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_9~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,065 INFO L290 TraceCheckUtils]: 41: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_10~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,065 INFO L290 TraceCheckUtils]: 42: Hoare triple {134787#(not (= ~E_12~0 0))} assume !(0 == ~E_11~0); {134787#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:48,065 INFO L290 TraceCheckUtils]: 43: Hoare triple {134787#(not (= ~E_12~0 0))} assume 0 == ~E_12~0;~E_12~0 := 1; {134785#false} is VALID [2022-02-21 04:23:48,065 INFO L290 TraceCheckUtils]: 44: Hoare triple {134785#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {134785#false} is VALID [2022-02-21 04:23:48,065 INFO L290 TraceCheckUtils]: 45: Hoare triple {134785#false} assume 1 == ~m_pc~0; {134785#false} is VALID [2022-02-21 04:23:48,066 INFO L290 TraceCheckUtils]: 46: Hoare triple {134785#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {134785#false} is VALID [2022-02-21 04:23:48,066 INFO L290 TraceCheckUtils]: 47: Hoare triple {134785#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {134785#false} is VALID [2022-02-21 04:23:48,066 INFO L290 TraceCheckUtils]: 48: Hoare triple {134785#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {134785#false} is VALID [2022-02-21 04:23:48,066 INFO L290 TraceCheckUtils]: 49: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp~1#1); {134785#false} is VALID [2022-02-21 04:23:48,066 INFO L290 TraceCheckUtils]: 50: Hoare triple {134785#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {134785#false} is VALID [2022-02-21 04:23:48,066 INFO L290 TraceCheckUtils]: 51: Hoare triple {134785#false} assume !(1 == ~t1_pc~0); {134785#false} is VALID [2022-02-21 04:23:48,066 INFO L290 TraceCheckUtils]: 52: Hoare triple {134785#false} is_transmit1_triggered_~__retres1~1#1 := 0; {134785#false} is VALID [2022-02-21 04:23:48,066 INFO L290 TraceCheckUtils]: 53: Hoare triple {134785#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {134785#false} is VALID [2022-02-21 04:23:48,066 INFO L290 TraceCheckUtils]: 54: Hoare triple {134785#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {134785#false} is VALID [2022-02-21 04:23:48,067 INFO L290 TraceCheckUtils]: 55: Hoare triple {134785#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {134785#false} is VALID [2022-02-21 04:23:48,067 INFO L290 TraceCheckUtils]: 56: Hoare triple {134785#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {134785#false} is VALID [2022-02-21 04:23:48,067 INFO L290 TraceCheckUtils]: 57: Hoare triple {134785#false} assume 1 == ~t2_pc~0; {134785#false} is VALID [2022-02-21 04:23:48,067 INFO L290 TraceCheckUtils]: 58: Hoare triple {134785#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {134785#false} is VALID [2022-02-21 04:23:48,067 INFO L290 TraceCheckUtils]: 59: Hoare triple {134785#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {134785#false} is VALID [2022-02-21 04:23:48,067 INFO L290 TraceCheckUtils]: 60: Hoare triple {134785#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {134785#false} is VALID [2022-02-21 04:23:48,067 INFO L290 TraceCheckUtils]: 61: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp___1~0#1); {134785#false} is VALID [2022-02-21 04:23:48,067 INFO L290 TraceCheckUtils]: 62: Hoare triple {134785#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {134785#false} is VALID [2022-02-21 04:23:48,067 INFO L290 TraceCheckUtils]: 63: Hoare triple {134785#false} assume !(1 == ~t3_pc~0); {134785#false} is VALID [2022-02-21 04:23:48,068 INFO L290 TraceCheckUtils]: 64: Hoare triple {134785#false} is_transmit3_triggered_~__retres1~3#1 := 0; {134785#false} is VALID [2022-02-21 04:23:48,068 INFO L290 TraceCheckUtils]: 65: Hoare triple {134785#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {134785#false} is VALID [2022-02-21 04:23:48,068 INFO L290 TraceCheckUtils]: 66: Hoare triple {134785#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {134785#false} is VALID [2022-02-21 04:23:48,068 INFO L290 TraceCheckUtils]: 67: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp___2~0#1); {134785#false} is VALID [2022-02-21 04:23:48,068 INFO L290 TraceCheckUtils]: 68: Hoare triple {134785#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {134785#false} is VALID [2022-02-21 04:23:48,068 INFO L290 TraceCheckUtils]: 69: Hoare triple {134785#false} assume 1 == ~t4_pc~0; {134785#false} is VALID [2022-02-21 04:23:48,068 INFO L290 TraceCheckUtils]: 70: Hoare triple {134785#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {134785#false} is VALID [2022-02-21 04:23:48,068 INFO L290 TraceCheckUtils]: 71: Hoare triple {134785#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {134785#false} is VALID [2022-02-21 04:23:48,068 INFO L290 TraceCheckUtils]: 72: Hoare triple {134785#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {134785#false} is VALID [2022-02-21 04:23:48,068 INFO L290 TraceCheckUtils]: 73: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp___3~0#1); {134785#false} is VALID [2022-02-21 04:23:48,069 INFO L290 TraceCheckUtils]: 74: Hoare triple {134785#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {134785#false} is VALID [2022-02-21 04:23:48,069 INFO L290 TraceCheckUtils]: 75: Hoare triple {134785#false} assume !(1 == ~t5_pc~0); {134785#false} is VALID [2022-02-21 04:23:48,069 INFO L290 TraceCheckUtils]: 76: Hoare triple {134785#false} is_transmit5_triggered_~__retres1~5#1 := 0; {134785#false} is VALID [2022-02-21 04:23:48,069 INFO L290 TraceCheckUtils]: 77: Hoare triple {134785#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {134785#false} is VALID [2022-02-21 04:23:48,069 INFO L290 TraceCheckUtils]: 78: Hoare triple {134785#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {134785#false} is VALID [2022-02-21 04:23:48,069 INFO L290 TraceCheckUtils]: 79: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp___4~0#1); {134785#false} is VALID [2022-02-21 04:23:48,069 INFO L290 TraceCheckUtils]: 80: Hoare triple {134785#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {134785#false} is VALID [2022-02-21 04:23:48,069 INFO L290 TraceCheckUtils]: 81: Hoare triple {134785#false} assume 1 == ~t6_pc~0; {134785#false} is VALID [2022-02-21 04:23:48,069 INFO L290 TraceCheckUtils]: 82: Hoare triple {134785#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {134785#false} is VALID [2022-02-21 04:23:48,070 INFO L290 TraceCheckUtils]: 83: Hoare triple {134785#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {134785#false} is VALID [2022-02-21 04:23:48,070 INFO L290 TraceCheckUtils]: 84: Hoare triple {134785#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {134785#false} is VALID [2022-02-21 04:23:48,070 INFO L290 TraceCheckUtils]: 85: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp___5~0#1); {134785#false} is VALID [2022-02-21 04:23:48,070 INFO L290 TraceCheckUtils]: 86: Hoare triple {134785#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {134785#false} is VALID [2022-02-21 04:23:48,070 INFO L290 TraceCheckUtils]: 87: Hoare triple {134785#false} assume 1 == ~t7_pc~0; {134785#false} is VALID [2022-02-21 04:23:48,070 INFO L290 TraceCheckUtils]: 88: Hoare triple {134785#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {134785#false} is VALID [2022-02-21 04:23:48,070 INFO L290 TraceCheckUtils]: 89: Hoare triple {134785#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {134785#false} is VALID [2022-02-21 04:23:48,070 INFO L290 TraceCheckUtils]: 90: Hoare triple {134785#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {134785#false} is VALID [2022-02-21 04:23:48,070 INFO L290 TraceCheckUtils]: 91: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp___6~0#1); {134785#false} is VALID [2022-02-21 04:23:48,071 INFO L290 TraceCheckUtils]: 92: Hoare triple {134785#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {134785#false} is VALID [2022-02-21 04:23:48,071 INFO L290 TraceCheckUtils]: 93: Hoare triple {134785#false} assume !(1 == ~t8_pc~0); {134785#false} is VALID [2022-02-21 04:23:48,071 INFO L290 TraceCheckUtils]: 94: Hoare triple {134785#false} is_transmit8_triggered_~__retres1~8#1 := 0; {134785#false} is VALID [2022-02-21 04:23:48,071 INFO L290 TraceCheckUtils]: 95: Hoare triple {134785#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {134785#false} is VALID [2022-02-21 04:23:48,071 INFO L290 TraceCheckUtils]: 96: Hoare triple {134785#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {134785#false} is VALID [2022-02-21 04:23:48,071 INFO L290 TraceCheckUtils]: 97: Hoare triple {134785#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {134785#false} is VALID [2022-02-21 04:23:48,071 INFO L290 TraceCheckUtils]: 98: Hoare triple {134785#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {134785#false} is VALID [2022-02-21 04:23:48,071 INFO L290 TraceCheckUtils]: 99: Hoare triple {134785#false} assume 1 == ~t9_pc~0; {134785#false} is VALID [2022-02-21 04:23:48,071 INFO L290 TraceCheckUtils]: 100: Hoare triple {134785#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {134785#false} is VALID [2022-02-21 04:23:48,072 INFO L290 TraceCheckUtils]: 101: Hoare triple {134785#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {134785#false} is VALID [2022-02-21 04:23:48,072 INFO L290 TraceCheckUtils]: 102: Hoare triple {134785#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {134785#false} is VALID [2022-02-21 04:23:48,072 INFO L290 TraceCheckUtils]: 103: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp___8~0#1); {134785#false} is VALID [2022-02-21 04:23:48,072 INFO L290 TraceCheckUtils]: 104: Hoare triple {134785#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {134785#false} is VALID [2022-02-21 04:23:48,072 INFO L290 TraceCheckUtils]: 105: Hoare triple {134785#false} assume !(1 == ~t10_pc~0); {134785#false} is VALID [2022-02-21 04:23:48,072 INFO L290 TraceCheckUtils]: 106: Hoare triple {134785#false} is_transmit10_triggered_~__retres1~10#1 := 0; {134785#false} is VALID [2022-02-21 04:23:48,072 INFO L290 TraceCheckUtils]: 107: Hoare triple {134785#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {134785#false} is VALID [2022-02-21 04:23:48,072 INFO L290 TraceCheckUtils]: 108: Hoare triple {134785#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {134785#false} is VALID [2022-02-21 04:23:48,072 INFO L290 TraceCheckUtils]: 109: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp___9~0#1); {134785#false} is VALID [2022-02-21 04:23:48,072 INFO L290 TraceCheckUtils]: 110: Hoare triple {134785#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {134785#false} is VALID [2022-02-21 04:23:48,073 INFO L290 TraceCheckUtils]: 111: Hoare triple {134785#false} assume 1 == ~t11_pc~0; {134785#false} is VALID [2022-02-21 04:23:48,073 INFO L290 TraceCheckUtils]: 112: Hoare triple {134785#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {134785#false} is VALID [2022-02-21 04:23:48,073 INFO L290 TraceCheckUtils]: 113: Hoare triple {134785#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {134785#false} is VALID [2022-02-21 04:23:48,073 INFO L290 TraceCheckUtils]: 114: Hoare triple {134785#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {134785#false} is VALID [2022-02-21 04:23:48,073 INFO L290 TraceCheckUtils]: 115: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp___10~0#1); {134785#false} is VALID [2022-02-21 04:23:48,073 INFO L290 TraceCheckUtils]: 116: Hoare triple {134785#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {134785#false} is VALID [2022-02-21 04:23:48,073 INFO L290 TraceCheckUtils]: 117: Hoare triple {134785#false} assume !(1 == ~t12_pc~0); {134785#false} is VALID [2022-02-21 04:23:48,073 INFO L290 TraceCheckUtils]: 118: Hoare triple {134785#false} is_transmit12_triggered_~__retres1~12#1 := 0; {134785#false} is VALID [2022-02-21 04:23:48,073 INFO L290 TraceCheckUtils]: 119: Hoare triple {134785#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {134785#false} is VALID [2022-02-21 04:23:48,074 INFO L290 TraceCheckUtils]: 120: Hoare triple {134785#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {134785#false} is VALID [2022-02-21 04:23:48,074 INFO L290 TraceCheckUtils]: 121: Hoare triple {134785#false} assume !(0 != activate_threads_~tmp___11~0#1); {134785#false} is VALID [2022-02-21 04:23:48,074 INFO L290 TraceCheckUtils]: 122: Hoare triple {134785#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {134785#false} is VALID [2022-02-21 04:23:48,074 INFO L290 TraceCheckUtils]: 123: Hoare triple {134785#false} assume !(1 == ~M_E~0); {134785#false} is VALID [2022-02-21 04:23:48,074 INFO L290 TraceCheckUtils]: 124: Hoare triple {134785#false} assume !(1 == ~T1_E~0); {134785#false} is VALID [2022-02-21 04:23:48,074 INFO L290 TraceCheckUtils]: 125: Hoare triple {134785#false} assume !(1 == ~T2_E~0); {134785#false} is VALID [2022-02-21 04:23:48,074 INFO L290 TraceCheckUtils]: 126: Hoare triple {134785#false} assume !(1 == ~T3_E~0); {134785#false} is VALID [2022-02-21 04:23:48,074 INFO L290 TraceCheckUtils]: 127: Hoare triple {134785#false} assume !(1 == ~T4_E~0); {134785#false} is VALID [2022-02-21 04:23:48,074 INFO L290 TraceCheckUtils]: 128: Hoare triple {134785#false} assume !(1 == ~T5_E~0); {134785#false} is VALID [2022-02-21 04:23:48,075 INFO L290 TraceCheckUtils]: 129: Hoare triple {134785#false} assume !(1 == ~T6_E~0); {134785#false} is VALID [2022-02-21 04:23:48,075 INFO L290 TraceCheckUtils]: 130: Hoare triple {134785#false} assume !(1 == ~T7_E~0); {134785#false} is VALID [2022-02-21 04:23:48,075 INFO L290 TraceCheckUtils]: 131: Hoare triple {134785#false} assume !(1 == ~T8_E~0); {134785#false} is VALID [2022-02-21 04:23:48,075 INFO L290 TraceCheckUtils]: 132: Hoare triple {134785#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {134785#false} is VALID [2022-02-21 04:23:48,075 INFO L290 TraceCheckUtils]: 133: Hoare triple {134785#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {134785#false} is VALID [2022-02-21 04:23:48,075 INFO L290 TraceCheckUtils]: 134: Hoare triple {134785#false} assume !(1 == ~T11_E~0); {134785#false} is VALID [2022-02-21 04:23:48,075 INFO L290 TraceCheckUtils]: 135: Hoare triple {134785#false} assume !(1 == ~T12_E~0); {134785#false} is VALID [2022-02-21 04:23:48,075 INFO L290 TraceCheckUtils]: 136: Hoare triple {134785#false} assume !(1 == ~E_M~0); {134785#false} is VALID [2022-02-21 04:23:48,075 INFO L290 TraceCheckUtils]: 137: Hoare triple {134785#false} assume !(1 == ~E_1~0); {134785#false} is VALID [2022-02-21 04:23:48,076 INFO L290 TraceCheckUtils]: 138: Hoare triple {134785#false} assume !(1 == ~E_2~0); {134785#false} is VALID [2022-02-21 04:23:48,076 INFO L290 TraceCheckUtils]: 139: Hoare triple {134785#false} assume !(1 == ~E_3~0); {134785#false} is VALID [2022-02-21 04:23:48,076 INFO L290 TraceCheckUtils]: 140: Hoare triple {134785#false} assume 1 == ~E_4~0;~E_4~0 := 2; {134785#false} is VALID [2022-02-21 04:23:48,076 INFO L290 TraceCheckUtils]: 141: Hoare triple {134785#false} assume 1 == ~E_5~0;~E_5~0 := 2; {134785#false} is VALID [2022-02-21 04:23:48,076 INFO L290 TraceCheckUtils]: 142: Hoare triple {134785#false} assume !(1 == ~E_6~0); {134785#false} is VALID [2022-02-21 04:23:48,076 INFO L290 TraceCheckUtils]: 143: Hoare triple {134785#false} assume !(1 == ~E_7~0); {134785#false} is VALID [2022-02-21 04:23:48,076 INFO L290 TraceCheckUtils]: 144: Hoare triple {134785#false} assume !(1 == ~E_8~0); {134785#false} is VALID [2022-02-21 04:23:48,076 INFO L290 TraceCheckUtils]: 145: Hoare triple {134785#false} assume !(1 == ~E_9~0); {134785#false} is VALID [2022-02-21 04:23:48,076 INFO L290 TraceCheckUtils]: 146: Hoare triple {134785#false} assume !(1 == ~E_10~0); {134785#false} is VALID [2022-02-21 04:23:48,076 INFO L290 TraceCheckUtils]: 147: Hoare triple {134785#false} assume !(1 == ~E_11~0); {134785#false} is VALID [2022-02-21 04:23:48,077 INFO L290 TraceCheckUtils]: 148: Hoare triple {134785#false} assume !(1 == ~E_12~0); {134785#false} is VALID [2022-02-21 04:23:48,077 INFO L290 TraceCheckUtils]: 149: Hoare triple {134785#false} assume { :end_inline_reset_delta_events } true; {134785#false} is VALID [2022-02-21 04:23:48,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:48,077 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:48,077 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1503263518] [2022-02-21 04:23:48,077 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1503263518] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:48,078 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:48,078 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:48,078 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1056126023] [2022-02-21 04:23:48,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:48,078 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:48,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:48,079 INFO L85 PathProgramCache]: Analyzing trace with hash -1372093673, now seen corresponding path program 1 times [2022-02-21 04:23:48,079 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:48,079 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465530641] [2022-02-21 04:23:48,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:48,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:48,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:48,104 INFO L290 TraceCheckUtils]: 0: Hoare triple {134788#true} assume !false; {134788#true} is VALID [2022-02-21 04:23:48,104 INFO L290 TraceCheckUtils]: 1: Hoare triple {134788#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {134788#true} is VALID [2022-02-21 04:23:48,105 INFO L290 TraceCheckUtils]: 2: Hoare triple {134788#true} assume !false; {134788#true} is VALID [2022-02-21 04:23:48,105 INFO L290 TraceCheckUtils]: 3: Hoare triple {134788#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {134788#true} is VALID [2022-02-21 04:23:48,105 INFO L290 TraceCheckUtils]: 4: Hoare triple {134788#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {134788#true} is VALID [2022-02-21 04:23:48,105 INFO L290 TraceCheckUtils]: 5: Hoare triple {134788#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {134788#true} is VALID [2022-02-21 04:23:48,105 INFO L290 TraceCheckUtils]: 6: Hoare triple {134788#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {134788#true} is VALID [2022-02-21 04:23:48,105 INFO L290 TraceCheckUtils]: 7: Hoare triple {134788#true} assume !(0 != eval_~tmp~0#1); {134788#true} is VALID [2022-02-21 04:23:48,105 INFO L290 TraceCheckUtils]: 8: Hoare triple {134788#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {134788#true} is VALID [2022-02-21 04:23:48,105 INFO L290 TraceCheckUtils]: 9: Hoare triple {134788#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {134788#true} is VALID [2022-02-21 04:23:48,106 INFO L290 TraceCheckUtils]: 10: Hoare triple {134788#true} assume 0 == ~M_E~0;~M_E~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,106 INFO L290 TraceCheckUtils]: 11: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,106 INFO L290 TraceCheckUtils]: 12: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,106 INFO L290 TraceCheckUtils]: 13: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,107 INFO L290 TraceCheckUtils]: 14: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,107 INFO L290 TraceCheckUtils]: 15: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,107 INFO L290 TraceCheckUtils]: 16: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,107 INFO L290 TraceCheckUtils]: 17: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,108 INFO L290 TraceCheckUtils]: 18: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,108 INFO L290 TraceCheckUtils]: 19: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,108 INFO L290 TraceCheckUtils]: 20: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,109 INFO L290 TraceCheckUtils]: 21: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,109 INFO L290 TraceCheckUtils]: 22: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,109 INFO L290 TraceCheckUtils]: 23: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,109 INFO L290 TraceCheckUtils]: 24: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,110 INFO L290 TraceCheckUtils]: 25: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,110 INFO L290 TraceCheckUtils]: 26: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,110 INFO L290 TraceCheckUtils]: 27: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,110 INFO L290 TraceCheckUtils]: 28: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,111 INFO L290 TraceCheckUtils]: 29: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,111 INFO L290 TraceCheckUtils]: 30: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,111 INFO L290 TraceCheckUtils]: 31: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,111 INFO L290 TraceCheckUtils]: 32: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,112 INFO L290 TraceCheckUtils]: 33: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_10~0); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,112 INFO L290 TraceCheckUtils]: 34: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,112 INFO L290 TraceCheckUtils]: 35: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,112 INFO L290 TraceCheckUtils]: 36: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,113 INFO L290 TraceCheckUtils]: 37: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,113 INFO L290 TraceCheckUtils]: 38: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,113 INFO L290 TraceCheckUtils]: 39: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,113 INFO L290 TraceCheckUtils]: 40: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,114 INFO L290 TraceCheckUtils]: 41: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,114 INFO L290 TraceCheckUtils]: 42: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,114 INFO L290 TraceCheckUtils]: 43: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,114 INFO L290 TraceCheckUtils]: 44: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,115 INFO L290 TraceCheckUtils]: 45: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,115 INFO L290 TraceCheckUtils]: 46: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,115 INFO L290 TraceCheckUtils]: 47: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,115 INFO L290 TraceCheckUtils]: 48: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,116 INFO L290 TraceCheckUtils]: 49: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,116 INFO L290 TraceCheckUtils]: 50: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,116 INFO L290 TraceCheckUtils]: 51: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,116 INFO L290 TraceCheckUtils]: 52: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,117 INFO L290 TraceCheckUtils]: 53: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,117 INFO L290 TraceCheckUtils]: 54: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,117 INFO L290 TraceCheckUtils]: 55: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,117 INFO L290 TraceCheckUtils]: 56: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,118 INFO L290 TraceCheckUtils]: 57: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,118 INFO L290 TraceCheckUtils]: 58: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,118 INFO L290 TraceCheckUtils]: 59: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,118 INFO L290 TraceCheckUtils]: 60: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,119 INFO L290 TraceCheckUtils]: 61: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,119 INFO L290 TraceCheckUtils]: 62: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,119 INFO L290 TraceCheckUtils]: 63: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,120 INFO L290 TraceCheckUtils]: 64: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,120 INFO L290 TraceCheckUtils]: 65: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,120 INFO L290 TraceCheckUtils]: 66: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,120 INFO L290 TraceCheckUtils]: 67: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,121 INFO L290 TraceCheckUtils]: 68: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,121 INFO L290 TraceCheckUtils]: 69: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,121 INFO L290 TraceCheckUtils]: 70: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,121 INFO L290 TraceCheckUtils]: 71: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,122 INFO L290 TraceCheckUtils]: 72: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,122 INFO L290 TraceCheckUtils]: 73: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,122 INFO L290 TraceCheckUtils]: 74: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,122 INFO L290 TraceCheckUtils]: 75: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,123 INFO L290 TraceCheckUtils]: 76: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,123 INFO L290 TraceCheckUtils]: 77: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,123 INFO L290 TraceCheckUtils]: 78: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,123 INFO L290 TraceCheckUtils]: 79: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,124 INFO L290 TraceCheckUtils]: 80: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,124 INFO L290 TraceCheckUtils]: 81: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,124 INFO L290 TraceCheckUtils]: 82: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,124 INFO L290 TraceCheckUtils]: 83: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,125 INFO L290 TraceCheckUtils]: 84: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,125 INFO L290 TraceCheckUtils]: 85: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,125 INFO L290 TraceCheckUtils]: 86: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,126 INFO L290 TraceCheckUtils]: 87: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,126 INFO L290 TraceCheckUtils]: 88: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,126 INFO L290 TraceCheckUtils]: 89: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,126 INFO L290 TraceCheckUtils]: 90: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,127 INFO L290 TraceCheckUtils]: 91: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,127 INFO L290 TraceCheckUtils]: 92: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,127 INFO L290 TraceCheckUtils]: 93: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,128 INFO L290 TraceCheckUtils]: 94: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,128 INFO L290 TraceCheckUtils]: 95: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,128 INFO L290 TraceCheckUtils]: 96: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,128 INFO L290 TraceCheckUtils]: 97: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,129 INFO L290 TraceCheckUtils]: 98: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,129 INFO L290 TraceCheckUtils]: 99: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,129 INFO L290 TraceCheckUtils]: 100: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,130 INFO L290 TraceCheckUtils]: 101: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,130 INFO L290 TraceCheckUtils]: 102: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,130 INFO L290 TraceCheckUtils]: 103: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,131 INFO L290 TraceCheckUtils]: 104: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,131 INFO L290 TraceCheckUtils]: 105: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,131 INFO L290 TraceCheckUtils]: 106: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,131 INFO L290 TraceCheckUtils]: 107: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,132 INFO L290 TraceCheckUtils]: 108: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,132 INFO L290 TraceCheckUtils]: 109: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,132 INFO L290 TraceCheckUtils]: 110: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,133 INFO L290 TraceCheckUtils]: 111: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,133 INFO L290 TraceCheckUtils]: 112: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,133 INFO L290 TraceCheckUtils]: 113: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,133 INFO L290 TraceCheckUtils]: 114: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {134790#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:23:48,134 INFO L290 TraceCheckUtils]: 115: Hoare triple {134790#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {134789#false} is VALID [2022-02-21 04:23:48,134 INFO L290 TraceCheckUtils]: 116: Hoare triple {134789#false} assume !(1 == ~T1_E~0); {134789#false} is VALID [2022-02-21 04:23:48,134 INFO L290 TraceCheckUtils]: 117: Hoare triple {134789#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,134 INFO L290 TraceCheckUtils]: 118: Hoare triple {134789#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,134 INFO L290 TraceCheckUtils]: 119: Hoare triple {134789#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,134 INFO L290 TraceCheckUtils]: 120: Hoare triple {134789#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,135 INFO L290 TraceCheckUtils]: 121: Hoare triple {134789#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,135 INFO L290 TraceCheckUtils]: 122: Hoare triple {134789#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,135 INFO L290 TraceCheckUtils]: 123: Hoare triple {134789#false} assume !(1 == ~T8_E~0); {134789#false} is VALID [2022-02-21 04:23:48,135 INFO L290 TraceCheckUtils]: 124: Hoare triple {134789#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,135 INFO L290 TraceCheckUtils]: 125: Hoare triple {134789#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,135 INFO L290 TraceCheckUtils]: 126: Hoare triple {134789#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,135 INFO L290 TraceCheckUtils]: 127: Hoare triple {134789#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,135 INFO L290 TraceCheckUtils]: 128: Hoare triple {134789#false} assume 1 == ~E_M~0;~E_M~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,136 INFO L290 TraceCheckUtils]: 129: Hoare triple {134789#false} assume 1 == ~E_1~0;~E_1~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,136 INFO L290 TraceCheckUtils]: 130: Hoare triple {134789#false} assume 1 == ~E_2~0;~E_2~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,136 INFO L290 TraceCheckUtils]: 131: Hoare triple {134789#false} assume !(1 == ~E_3~0); {134789#false} is VALID [2022-02-21 04:23:48,136 INFO L290 TraceCheckUtils]: 132: Hoare triple {134789#false} assume 1 == ~E_4~0;~E_4~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,136 INFO L290 TraceCheckUtils]: 133: Hoare triple {134789#false} assume 1 == ~E_5~0;~E_5~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,136 INFO L290 TraceCheckUtils]: 134: Hoare triple {134789#false} assume 1 == ~E_6~0;~E_6~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,136 INFO L290 TraceCheckUtils]: 135: Hoare triple {134789#false} assume 1 == ~E_7~0;~E_7~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,137 INFO L290 TraceCheckUtils]: 136: Hoare triple {134789#false} assume 1 == ~E_8~0;~E_8~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,137 INFO L290 TraceCheckUtils]: 137: Hoare triple {134789#false} assume 1 == ~E_9~0;~E_9~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,137 INFO L290 TraceCheckUtils]: 138: Hoare triple {134789#false} assume 1 == ~E_10~0;~E_10~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,137 INFO L290 TraceCheckUtils]: 139: Hoare triple {134789#false} assume !(1 == ~E_11~0); {134789#false} is VALID [2022-02-21 04:23:48,137 INFO L290 TraceCheckUtils]: 140: Hoare triple {134789#false} assume 1 == ~E_12~0;~E_12~0 := 2; {134789#false} is VALID [2022-02-21 04:23:48,137 INFO L290 TraceCheckUtils]: 141: Hoare triple {134789#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {134789#false} is VALID [2022-02-21 04:23:48,137 INFO L290 TraceCheckUtils]: 142: Hoare triple {134789#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {134789#false} is VALID [2022-02-21 04:23:48,137 INFO L290 TraceCheckUtils]: 143: Hoare triple {134789#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {134789#false} is VALID [2022-02-21 04:23:48,138 INFO L290 TraceCheckUtils]: 144: Hoare triple {134789#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {134789#false} is VALID [2022-02-21 04:23:48,138 INFO L290 TraceCheckUtils]: 145: Hoare triple {134789#false} assume !(0 == start_simulation_~tmp~3#1); {134789#false} is VALID [2022-02-21 04:23:48,138 INFO L290 TraceCheckUtils]: 146: Hoare triple {134789#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {134789#false} is VALID [2022-02-21 04:23:48,138 INFO L290 TraceCheckUtils]: 147: Hoare triple {134789#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {134789#false} is VALID [2022-02-21 04:23:48,138 INFO L290 TraceCheckUtils]: 148: Hoare triple {134789#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {134789#false} is VALID [2022-02-21 04:23:48,138 INFO L290 TraceCheckUtils]: 149: Hoare triple {134789#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {134789#false} is VALID [2022-02-21 04:23:48,138 INFO L290 TraceCheckUtils]: 150: Hoare triple {134789#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {134789#false} is VALID [2022-02-21 04:23:48,138 INFO L290 TraceCheckUtils]: 151: Hoare triple {134789#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {134789#false} is VALID [2022-02-21 04:23:48,139 INFO L290 TraceCheckUtils]: 152: Hoare triple {134789#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {134789#false} is VALID [2022-02-21 04:23:48,139 INFO L290 TraceCheckUtils]: 153: Hoare triple {134789#false} assume !(0 != start_simulation_~tmp___0~1#1); {134789#false} is VALID [2022-02-21 04:23:48,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:48,139 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:48,139 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465530641] [2022-02-21 04:23:48,140 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1465530641] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:48,140 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:48,140 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:48,140 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411534436] [2022-02-21 04:23:48,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:48,140 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:48,140 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:48,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:48,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:48,141 INFO L87 Difference]: Start difference. First operand 6527 states and 9597 transitions. cyclomatic complexity: 3074 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:54,538 INFO L93 Difference]: Finished difference Result 12485 states and 18332 transitions. [2022-02-21 04:23:54,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:54,538 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,626 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:54,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12485 states and 18332 transitions. [2022-02-21 04:23:58,247 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12256 [2022-02-21 04:24:01,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12485 states to 12485 states and 18332 transitions. [2022-02-21 04:24:01,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12485 [2022-02-21 04:24:01,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12485 [2022-02-21 04:24:01,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12485 states and 18332 transitions. [2022-02-21 04:24:01,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:01,785 INFO L681 BuchiCegarLoop]: Abstraction has 12485 states and 18332 transitions. [2022-02-21 04:24:01,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12485 states and 18332 transitions. [2022-02-21 04:24:01,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12485 to 12481. [2022-02-21 04:24:01,896 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:01,909 INFO L82 GeneralOperation]: Start isEquivalent. First operand 12485 states and 18332 transitions. Second operand has 12481 states, 12481 states have (on average 1.468472077557888) internal successors, (18328), 12480 states have internal predecessors, (18328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,924 INFO L74 IsIncluded]: Start isIncluded. First operand 12485 states and 18332 transitions. Second operand has 12481 states, 12481 states have (on average 1.468472077557888) internal successors, (18328), 12480 states have internal predecessors, (18328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,937 INFO L87 Difference]: Start difference. First operand 12485 states and 18332 transitions. Second operand has 12481 states, 12481 states have (on average 1.468472077557888) internal successors, (18328), 12480 states have internal predecessors, (18328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:05,610 INFO L93 Difference]: Finished difference Result 12485 states and 18332 transitions. [2022-02-21 04:24:05,610 INFO L276 IsEmpty]: Start isEmpty. Operand 12485 states and 18332 transitions. [2022-02-21 04:24:05,620 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:05,620 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:05,635 INFO L74 IsIncluded]: Start isIncluded. First operand has 12481 states, 12481 states have (on average 1.468472077557888) internal successors, (18328), 12480 states have internal predecessors, (18328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 12485 states and 18332 transitions. [2022-02-21 04:24:05,649 INFO L87 Difference]: Start difference. First operand has 12481 states, 12481 states have (on average 1.468472077557888) internal successors, (18328), 12480 states have internal predecessors, (18328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 12485 states and 18332 transitions. [2022-02-21 04:24:09,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:09,533 INFO L93 Difference]: Finished difference Result 12485 states and 18332 transitions. [2022-02-21 04:24:09,533 INFO L276 IsEmpty]: Start isEmpty. Operand 12485 states and 18332 transitions. [2022-02-21 04:24:09,546 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:09,546 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:09,546 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:09,546 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:09,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12481 states, 12481 states have (on average 1.468472077557888) internal successors, (18328), 12480 states have internal predecessors, (18328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)