./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.15.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.15.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:23:07,835 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:23:07,836 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:23:07,868 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:23:07,872 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:23:07,873 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:23:07,874 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:23:07,875 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:23:07,876 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:23:07,877 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:23:07,877 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:23:07,878 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:23:07,878 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:23:07,879 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:23:07,879 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:23:07,880 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:23:07,881 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:23:07,881 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:23:07,882 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:23:07,883 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:23:07,884 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:23:07,885 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:23:07,886 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:23:07,887 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:23:07,888 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:23:07,888 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:23:07,889 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:23:07,889 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:23:07,889 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:23:07,890 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:23:07,890 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:23:07,891 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:23:07,891 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:23:07,892 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:23:07,892 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:23:07,893 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:23:07,893 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:23:07,893 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:23:07,893 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:23:07,894 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:23:07,894 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:23:07,897 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:23:07,916 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:23:07,916 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:23:07,916 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:23:07,917 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:23:07,918 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:23:07,918 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:23:07,918 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:23:07,918 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:23:07,918 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:23:07,919 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:23:07,919 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:23:07,919 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:23:07,919 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:23:07,920 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:23:07,920 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:23:07,920 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:23:07,920 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:23:07,920 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:23:07,920 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:23:07,920 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:23:07,921 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:23:07,921 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:23:07,921 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:23:07,921 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:23:07,921 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:23:07,921 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:23:07,921 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:23:07,922 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:23:07,922 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:23:07,922 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:23:07,922 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:23:07,923 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:23:07,923 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 [2022-02-21 04:23:08,128 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:23:08,141 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:23:08,144 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:23:08,145 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:23:08,146 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:23:08,146 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.15.cil.c [2022-02-21 04:23:08,201 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0e70bb82a/19a18798412444a88e73df64d7c005e9/FLAGf5a6c1efe [2022-02-21 04:23:08,546 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:23:08,547 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.15.cil.c [2022-02-21 04:23:08,562 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0e70bb82a/19a18798412444a88e73df64d7c005e9/FLAGf5a6c1efe [2022-02-21 04:23:08,943 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0e70bb82a/19a18798412444a88e73df64d7c005e9 [2022-02-21 04:23:08,945 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:23:08,946 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:23:08,958 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:08,958 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:23:08,961 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:23:08,961 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:08" (1/1) ... [2022-02-21 04:23:08,962 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1d4efdf1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:08, skipping insertion in model container [2022-02-21 04:23:08,962 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:08" (1/1) ... [2022-02-21 04:23:08,966 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:23:08,995 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:23:09,121 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.15.cil.c[669,682] [2022-02-21 04:23:09,271 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:09,287 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:23:09,294 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.15.cil.c[669,682] [2022-02-21 04:23:09,359 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:09,384 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:23:09,384 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09 WrapperNode [2022-02-21 04:23:09,384 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:09,385 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:09,385 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:23:09,385 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:23:09,391 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (1/1) ... [2022-02-21 04:23:09,400 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (1/1) ... [2022-02-21 04:23:09,515 INFO L137 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4663 [2022-02-21 04:23:09,516 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:09,516 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:23:09,517 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:23:09,517 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:23:09,522 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (1/1) ... [2022-02-21 04:23:09,523 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (1/1) ... [2022-02-21 04:23:09,533 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (1/1) ... [2022-02-21 04:23:09,533 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (1/1) ... [2022-02-21 04:23:09,576 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (1/1) ... [2022-02-21 04:23:09,613 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (1/1) ... [2022-02-21 04:23:09,621 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (1/1) ... [2022-02-21 04:23:09,634 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:23:09,635 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:23:09,635 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:23:09,635 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:23:09,636 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (1/1) ... [2022-02-21 04:23:09,642 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:23:09,648 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:23:09,659 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:23:09,669 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:23:09,690 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:23:09,690 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:23:09,690 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:23:09,690 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:23:09,783 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:23:09,796 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:23:11,492 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:23:11,512 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:23:11,512 INFO L299 CfgBuilder]: Removed 16 assume(true) statements. [2022-02-21 04:23:11,515 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:11 BoogieIcfgContainer [2022-02-21 04:23:11,515 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:23:11,516 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:23:11,516 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:23:11,518 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:23:11,519 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:11,519 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:23:08" (1/3) ... [2022-02-21 04:23:11,520 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1595cb7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:11, skipping insertion in model container [2022-02-21 04:23:11,520 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:11,520 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:09" (2/3) ... [2022-02-21 04:23:11,520 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1595cb7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:11, skipping insertion in model container [2022-02-21 04:23:11,520 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:11,520 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:11" (3/3) ... [2022-02-21 04:23:11,521 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.15.cil.c [2022-02-21 04:23:11,550 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:23:11,550 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:23:11,551 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:23:11,551 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:23:11,551 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:23:11,551 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:23:11,551 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:23:11,551 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:23:11,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1850 [2022-02-21 04:23:11,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:11,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:11,905 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,906 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,906 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:23:11,911 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:12,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1850 [2022-02-21 04:23:12,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:12,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:12,140 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:12,141 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:12,147 INFO L791 eck$LassoCheckResult]: Stem: 462#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1953#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 302#L1898true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1870#L902true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1830#L909true assume !(1 == ~m_i~0);~m_st~0 := 2; 1941#L909-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 410#L914-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 434#L919-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1230#L924-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1102#L929-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1858#L934-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1268#L939-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1672#L944-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 305#L949-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1321#L954-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1962#L959-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 631#L964-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1172#L969-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 1763#L974-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1911#L1286true assume 0 == ~M_E~0;~M_E~0 := 1; 1445#L1286-2true assume !(0 == ~T1_E~0); 257#L1291-1true assume !(0 == ~T2_E~0); 1845#L1296-1true assume !(0 == ~T3_E~0); 691#L1301-1true assume !(0 == ~T4_E~0); 1217#L1306-1true assume !(0 == ~T5_E~0); 1185#L1311-1true assume !(0 == ~T6_E~0); 235#L1316-1true assume !(0 == ~T7_E~0); 1681#L1321-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 706#L1326-1true assume !(0 == ~T9_E~0); 141#L1331-1true assume !(0 == ~T10_E~0); 5#L1336-1true assume !(0 == ~T11_E~0); 1065#L1341-1true assume !(0 == ~T12_E~0); 29#L1346-1true assume !(0 == ~T13_E~0); 1489#L1351-1true assume !(0 == ~E_M~0); 205#L1356-1true assume !(0 == ~E_1~0); 1970#L1361-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1648#L1366-1true assume !(0 == ~E_3~0); 230#L1371-1true assume !(0 == ~E_4~0); 1452#L1376-1true assume !(0 == ~E_5~0); 743#L1381-1true assume !(0 == ~E_6~0); 1738#L1386-1true assume !(0 == ~E_7~0); 1882#L1391-1true assume !(0 == ~E_8~0); 1794#L1396-1true assume !(0 == ~E_9~0); 654#L1401-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1280#L1406-1true assume !(0 == ~E_11~0); 901#L1411-1true assume !(0 == ~E_12~0); 1704#L1416-1true assume !(0 == ~E_13~0); 606#L1421-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 499#L635true assume !(1 == ~m_pc~0); 38#L635-2true is_master_triggered_~__retres1~0#1 := 0; 201#L646true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 584#L647true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1305#L1598true assume !(0 != activate_threads_~tmp~1#1); 121#L1598-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 569#L654true assume 1 == ~t1_pc~0; 510#L655true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1728#L665true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1924#L666true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 568#L1606true assume !(0 != activate_threads_~tmp___0~0#1); 818#L1606-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143#L673true assume 1 == ~t2_pc~0; 1785#L674true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 871#L684true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1857#L685true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1885#L1614true assume !(0 != activate_threads_~tmp___1~0#1); 1985#L1614-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 621#L692true assume !(1 == ~t3_pc~0); 500#L692-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1777#L703true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 412#L704true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 390#L1622true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1710#L1622-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154#L711true assume 1 == ~t4_pc~0; 421#L712true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1316#L722true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 723#L723true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16#L1630true assume !(0 != activate_threads_~tmp___3~0#1); 1831#L1630-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1828#L730true assume !(1 == ~t5_pc~0); 1966#L730-2true is_transmit5_triggered_~__retres1~5#1 := 0; 101#L741true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 276#L742true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 158#L1638true assume !(0 != activate_threads_~tmp___4~0#1); 342#L1638-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 869#L749true assume 1 == ~t6_pc~0; 218#L750true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 411#L760true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 325#L761true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1448#L1646true assume !(0 != activate_threads_~tmp___5~0#1); 458#L1646-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7#L768true assume !(1 == ~t7_pc~0); 1661#L768-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1384#L779true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 118#L780true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1360#L1654true assume !(0 != activate_threads_~tmp___6~0#1); 780#L1654-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 236#L787true assume 1 == ~t8_pc~0; 1118#L788true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1690#L798true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1373#L799true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1900#L1662true assume !(0 != activate_threads_~tmp___7~0#1); 28#L1662-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1186#L806true assume 1 == ~t9_pc~0; 1131#L807true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45#L817true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 806#L818true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 159#L1670true assume !(0 != activate_threads_~tmp___8~0#1); 1593#L1670-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1110#L825true assume !(1 == ~t10_pc~0); 1378#L825-2true is_transmit10_triggered_~__retres1~10#1 := 0; 736#L836true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 845#L837true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 202#L1678true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2017#L1678-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 541#L844true assume 1 == ~t11_pc~0; 353#L845true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1259#L855true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 588#L856true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1168#L1686true assume !(0 != activate_threads_~tmp___10~0#1); 1097#L1686-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1400#L863true assume !(1 == ~t12_pc~0); 1460#L863-2true is_transmit12_triggered_~__retres1~12#1 := 0; 195#L874true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1526#L875true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1224#L1694true assume !(0 != activate_threads_~tmp___11~0#1); 1617#L1694-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 629#L882true assume 1 == ~t13_pc~0; 900#L883true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1852#L893true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1548#L894true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1175#L1702true assume !(0 != activate_threads_~tmp___12~0#1); 842#L1702-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1574#L1434true assume !(1 == ~M_E~0); 1940#L1434-2true assume !(1 == ~T1_E~0); 1850#L1439-1true assume !(1 == ~T2_E~0); 151#L1444-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 905#L1449-1true assume !(1 == ~T4_E~0); 388#L1454-1true assume !(1 == ~T5_E~0); 1484#L1459-1true assume !(1 == ~T6_E~0); 781#L1464-1true assume !(1 == ~T7_E~0); 851#L1469-1true assume !(1 == ~T8_E~0); 1725#L1474-1true assume !(1 == ~T9_E~0); 607#L1479-1true assume !(1 == ~T10_E~0); 789#L1484-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1248#L1489-1true assume !(1 == ~T12_E~0); 520#L1494-1true assume !(1 == ~T13_E~0); 1836#L1499-1true assume !(1 == ~E_M~0); 645#L1504-1true assume !(1 == ~E_1~0); 1534#L1509-1true assume !(1 == ~E_2~0); 1247#L1514-1true assume !(1 == ~E_3~0); 880#L1519-1true assume !(1 == ~E_4~0); 1954#L1524-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1692#L1529-1true assume !(1 == ~E_6~0); 1767#L1534-1true assume !(1 == ~E_7~0); 53#L1539-1true assume !(1 == ~E_8~0); 267#L1544-1true assume !(1 == ~E_9~0); 1609#L1549-1true assume !(1 == ~E_10~0); 1633#L1554-1true assume !(1 == ~E_11~0); 1606#L1559-1true assume !(1 == ~E_12~0); 1306#L1564-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1673#L1569-1true assume { :end_inline_reset_delta_events } true; 1981#L1935-2true [2022-02-21 04:23:12,149 INFO L793 eck$LassoCheckResult]: Loop: 1981#L1935-2true assume !false; 57#L1936true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1722#L1261true assume false; 814#L1276true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1261#L902-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1349#L1286-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1483#L1286-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 965#L1291-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1861#L1296-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1772#L1301-3true assume !(0 == ~T4_E~0); 1632#L1306-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 579#L1311-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 165#L1316-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 222#L1321-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 667#L1326-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1597#L1331-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 883#L1336-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1519#L1341-3true assume !(0 == ~T12_E~0); 384#L1346-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 376#L1351-3true assume 0 == ~E_M~0;~E_M~0 := 1; 348#L1356-3true assume 0 == ~E_1~0;~E_1~0 := 1; 728#L1361-3true assume 0 == ~E_2~0;~E_2~0 := 1; 757#L1366-3true assume 0 == ~E_3~0;~E_3~0 := 1; 23#L1371-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1276#L1376-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1563#L1381-3true assume !(0 == ~E_6~0); 1068#L1386-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1696#L1391-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1325#L1396-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1977#L1401-3true assume 0 == ~E_10~0;~E_10~0 := 1; 200#L1406-3true assume 0 == ~E_11~0;~E_11~0 := 1; 122#L1411-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1771#L1416-3true assume 0 == ~E_13~0;~E_13~0 := 1; 466#L1421-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66#L635-45true assume !(1 == ~m_pc~0); 758#L635-47true is_master_triggered_~__retres1~0#1 := 0; 843#L646-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1406#L647-15true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1096#L1598-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 211#L1598-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 720#L654-45true assume 1 == ~t1_pc~0; 1750#L655-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1038#L665-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#L666-15true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59#L1606-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1446#L1606-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505#L673-45true assume !(1 == ~t2_pc~0); 1343#L673-47true is_transmit2_triggered_~__retres1~2#1 := 0; 732#L684-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1561#L685-15true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1497#L1614-45true assume !(0 != activate_threads_~tmp___1~0#1); 1171#L1614-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 282#L692-45true assume !(1 == ~t3_pc~0); 139#L692-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1201#L703-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 786#L704-15true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 309#L1622-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 498#L1622-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2013#L711-45true assume !(1 == ~t4_pc~0); 627#L711-47true is_transmit4_triggered_~__retres1~4#1 := 0; 1971#L722-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 484#L723-15true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1695#L1630-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 765#L1630-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224#L730-45true assume 1 == ~t5_pc~0; 144#L731-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2031#L741-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 359#L742-15true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 888#L1638-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 991#L1638-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132#L749-45true assume !(1 == ~t6_pc~0); 1542#L749-47true is_transmit6_triggered_~__retres1~6#1 := 0; 1205#L760-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 866#L761-15true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1413#L1646-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1014#L1646-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 295#L768-45true assume 1 == ~t7_pc~0; 368#L769-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1173#L779-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 954#L780-15true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1841#L1654-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 993#L1654-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1898#L787-45true assume !(1 == ~t8_pc~0); 2020#L787-47true is_transmit8_triggered_~__retres1~8#1 := 0; 373#L798-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1683#L799-15true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 644#L1662-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 887#L1662-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1765#L806-45true assume !(1 == ~t9_pc~0); 74#L806-47true is_transmit9_triggered_~__retres1~9#1 := 0; 521#L817-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1136#L818-15true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 418#L1670-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 361#L1670-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1817#L825-45true assume 1 == ~t10_pc~0; 777#L826-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1837#L836-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 793#L837-15true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 922#L1678-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1015#L1678-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 171#L844-45true assume !(1 == ~t11_pc~0); 1536#L844-47true is_transmit11_triggered_~__retres1~11#1 := 0; 467#L855-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 477#L856-15true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 762#L1686-45true assume !(0 != activate_threads_~tmp___10~0#1); 1330#L1686-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 189#L863-45true assume !(1 == ~t12_pc~0); 648#L863-47true is_transmit12_triggered_~__retres1~12#1 := 0; 4#L874-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1423#L875-15true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 255#L1694-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 769#L1694-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1107#L882-45true assume 1 == ~t13_pc~0; 1367#L883-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12#L893-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 316#L894-15true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1315#L1702-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1369#L1702-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 855#L1434-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1071#L1434-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1036#L1439-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 149#L1444-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 231#L1449-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1631#L1454-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 848#L1459-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 2008#L1464-3true assume !(1 == ~T7_E~0); 1407#L1469-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1279#L1474-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1639#L1479-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1415#L1484-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 582#L1489-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1167#L1494-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1791#L1499-3true assume 1 == ~E_M~0;~E_M~0 := 2; 795#L1504-3true assume !(1 == ~E_1~0); 1294#L1509-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1358#L1514-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1892#L1519-3true assume 1 == ~E_4~0;~E_4~0 := 2; 522#L1524-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1470#L1529-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1691#L1534-3true assume 1 == ~E_7~0;~E_7~0 := 2; 735#L1539-3true assume 1 == ~E_8~0;~E_8~0 := 2; 369#L1544-3true assume !(1 == ~E_9~0); 1422#L1549-3true assume 1 == ~E_10~0;~E_10~0 := 2; 707#L1554-3true assume 1 == ~E_11~0;~E_11~0 := 2; 173#L1559-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1192#L1564-3true assume 1 == ~E_13~0;~E_13~0 := 2; 933#L1569-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1111#L987-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 427#L1059-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1099#L1060-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 914#L1954true assume !(0 == start_simulation_~tmp~3#1); 1674#L1954-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1194#L987-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 990#L1059-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1381#L1060-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1150#L1909true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1288#L1916true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1398#L1917true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1793#L1967true assume !(0 != start_simulation_~tmp___0~1#1); 1981#L1935-2true [2022-02-21 04:23:12,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:12,159 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2022-02-21 04:23:12,166 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:12,167 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806223209] [2022-02-21 04:23:12,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:12,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:12,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:12,352 INFO L290 TraceCheckUtils]: 0: Hoare triple {2033#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {2033#true} is VALID [2022-02-21 04:23:12,353 INFO L290 TraceCheckUtils]: 1: Hoare triple {2033#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {2035#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:12,355 INFO L290 TraceCheckUtils]: 2: Hoare triple {2035#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {2035#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:12,357 INFO L290 TraceCheckUtils]: 3: Hoare triple {2035#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {2035#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:12,357 INFO L290 TraceCheckUtils]: 4: Hoare triple {2035#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,358 INFO L290 TraceCheckUtils]: 5: Hoare triple {2034#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {2034#false} is VALID [2022-02-21 04:23:12,358 INFO L290 TraceCheckUtils]: 6: Hoare triple {2034#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,358 INFO L290 TraceCheckUtils]: 7: Hoare triple {2034#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,358 INFO L290 TraceCheckUtils]: 8: Hoare triple {2034#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,358 INFO L290 TraceCheckUtils]: 9: Hoare triple {2034#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,359 INFO L290 TraceCheckUtils]: 10: Hoare triple {2034#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,359 INFO L290 TraceCheckUtils]: 11: Hoare triple {2034#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,359 INFO L290 TraceCheckUtils]: 12: Hoare triple {2034#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,359 INFO L290 TraceCheckUtils]: 13: Hoare triple {2034#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {2034#false} is VALID [2022-02-21 04:23:12,359 INFO L290 TraceCheckUtils]: 14: Hoare triple {2034#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,360 INFO L290 TraceCheckUtils]: 15: Hoare triple {2034#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,360 INFO L290 TraceCheckUtils]: 16: Hoare triple {2034#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,360 INFO L290 TraceCheckUtils]: 17: Hoare triple {2034#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,360 INFO L290 TraceCheckUtils]: 18: Hoare triple {2034#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {2034#false} is VALID [2022-02-21 04:23:12,360 INFO L290 TraceCheckUtils]: 19: Hoare triple {2034#false} assume 0 == ~M_E~0;~M_E~0 := 1; {2034#false} is VALID [2022-02-21 04:23:12,361 INFO L290 TraceCheckUtils]: 20: Hoare triple {2034#false} assume !(0 == ~T1_E~0); {2034#false} is VALID [2022-02-21 04:23:12,361 INFO L290 TraceCheckUtils]: 21: Hoare triple {2034#false} assume !(0 == ~T2_E~0); {2034#false} is VALID [2022-02-21 04:23:12,362 INFO L290 TraceCheckUtils]: 22: Hoare triple {2034#false} assume !(0 == ~T3_E~0); {2034#false} is VALID [2022-02-21 04:23:12,362 INFO L290 TraceCheckUtils]: 23: Hoare triple {2034#false} assume !(0 == ~T4_E~0); {2034#false} is VALID [2022-02-21 04:23:12,362 INFO L290 TraceCheckUtils]: 24: Hoare triple {2034#false} assume !(0 == ~T5_E~0); {2034#false} is VALID [2022-02-21 04:23:12,362 INFO L290 TraceCheckUtils]: 25: Hoare triple {2034#false} assume !(0 == ~T6_E~0); {2034#false} is VALID [2022-02-21 04:23:12,362 INFO L290 TraceCheckUtils]: 26: Hoare triple {2034#false} assume !(0 == ~T7_E~0); {2034#false} is VALID [2022-02-21 04:23:12,363 INFO L290 TraceCheckUtils]: 27: Hoare triple {2034#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {2034#false} is VALID [2022-02-21 04:23:12,363 INFO L290 TraceCheckUtils]: 28: Hoare triple {2034#false} assume !(0 == ~T9_E~0); {2034#false} is VALID [2022-02-21 04:23:12,363 INFO L290 TraceCheckUtils]: 29: Hoare triple {2034#false} assume !(0 == ~T10_E~0); {2034#false} is VALID [2022-02-21 04:23:12,363 INFO L290 TraceCheckUtils]: 30: Hoare triple {2034#false} assume !(0 == ~T11_E~0); {2034#false} is VALID [2022-02-21 04:23:12,363 INFO L290 TraceCheckUtils]: 31: Hoare triple {2034#false} assume !(0 == ~T12_E~0); {2034#false} is VALID [2022-02-21 04:23:12,364 INFO L290 TraceCheckUtils]: 32: Hoare triple {2034#false} assume !(0 == ~T13_E~0); {2034#false} is VALID [2022-02-21 04:23:12,364 INFO L290 TraceCheckUtils]: 33: Hoare triple {2034#false} assume !(0 == ~E_M~0); {2034#false} is VALID [2022-02-21 04:23:12,364 INFO L290 TraceCheckUtils]: 34: Hoare triple {2034#false} assume !(0 == ~E_1~0); {2034#false} is VALID [2022-02-21 04:23:12,364 INFO L290 TraceCheckUtils]: 35: Hoare triple {2034#false} assume 0 == ~E_2~0;~E_2~0 := 1; {2034#false} is VALID [2022-02-21 04:23:12,364 INFO L290 TraceCheckUtils]: 36: Hoare triple {2034#false} assume !(0 == ~E_3~0); {2034#false} is VALID [2022-02-21 04:23:12,364 INFO L290 TraceCheckUtils]: 37: Hoare triple {2034#false} assume !(0 == ~E_4~0); {2034#false} is VALID [2022-02-21 04:23:12,365 INFO L290 TraceCheckUtils]: 38: Hoare triple {2034#false} assume !(0 == ~E_5~0); {2034#false} is VALID [2022-02-21 04:23:12,365 INFO L290 TraceCheckUtils]: 39: Hoare triple {2034#false} assume !(0 == ~E_6~0); {2034#false} is VALID [2022-02-21 04:23:12,365 INFO L290 TraceCheckUtils]: 40: Hoare triple {2034#false} assume !(0 == ~E_7~0); {2034#false} is VALID [2022-02-21 04:23:12,365 INFO L290 TraceCheckUtils]: 41: Hoare triple {2034#false} assume !(0 == ~E_8~0); {2034#false} is VALID [2022-02-21 04:23:12,366 INFO L290 TraceCheckUtils]: 42: Hoare triple {2034#false} assume !(0 == ~E_9~0); {2034#false} is VALID [2022-02-21 04:23:12,366 INFO L290 TraceCheckUtils]: 43: Hoare triple {2034#false} assume 0 == ~E_10~0;~E_10~0 := 1; {2034#false} is VALID [2022-02-21 04:23:12,366 INFO L290 TraceCheckUtils]: 44: Hoare triple {2034#false} assume !(0 == ~E_11~0); {2034#false} is VALID [2022-02-21 04:23:12,367 INFO L290 TraceCheckUtils]: 45: Hoare triple {2034#false} assume !(0 == ~E_12~0); {2034#false} is VALID [2022-02-21 04:23:12,367 INFO L290 TraceCheckUtils]: 46: Hoare triple {2034#false} assume !(0 == ~E_13~0); {2034#false} is VALID [2022-02-21 04:23:12,367 INFO L290 TraceCheckUtils]: 47: Hoare triple {2034#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2034#false} is VALID [2022-02-21 04:23:12,367 INFO L290 TraceCheckUtils]: 48: Hoare triple {2034#false} assume !(1 == ~m_pc~0); {2034#false} is VALID [2022-02-21 04:23:12,370 INFO L290 TraceCheckUtils]: 49: Hoare triple {2034#false} is_master_triggered_~__retres1~0#1 := 0; {2034#false} is VALID [2022-02-21 04:23:12,371 INFO L290 TraceCheckUtils]: 50: Hoare triple {2034#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2034#false} is VALID [2022-02-21 04:23:12,371 INFO L290 TraceCheckUtils]: 51: Hoare triple {2034#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {2034#false} is VALID [2022-02-21 04:23:12,373 INFO L290 TraceCheckUtils]: 52: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp~1#1); {2034#false} is VALID [2022-02-21 04:23:12,373 INFO L290 TraceCheckUtils]: 53: Hoare triple {2034#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2034#false} is VALID [2022-02-21 04:23:12,373 INFO L290 TraceCheckUtils]: 54: Hoare triple {2034#false} assume 1 == ~t1_pc~0; {2034#false} is VALID [2022-02-21 04:23:12,374 INFO L290 TraceCheckUtils]: 55: Hoare triple {2034#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {2034#false} is VALID [2022-02-21 04:23:12,374 INFO L290 TraceCheckUtils]: 56: Hoare triple {2034#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2034#false} is VALID [2022-02-21 04:23:12,374 INFO L290 TraceCheckUtils]: 57: Hoare triple {2034#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {2034#false} is VALID [2022-02-21 04:23:12,374 INFO L290 TraceCheckUtils]: 58: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___0~0#1); {2034#false} is VALID [2022-02-21 04:23:12,375 INFO L290 TraceCheckUtils]: 59: Hoare triple {2034#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2034#false} is VALID [2022-02-21 04:23:12,375 INFO L290 TraceCheckUtils]: 60: Hoare triple {2034#false} assume 1 == ~t2_pc~0; {2034#false} is VALID [2022-02-21 04:23:12,375 INFO L290 TraceCheckUtils]: 61: Hoare triple {2034#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2034#false} is VALID [2022-02-21 04:23:12,375 INFO L290 TraceCheckUtils]: 62: Hoare triple {2034#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2034#false} is VALID [2022-02-21 04:23:12,376 INFO L290 TraceCheckUtils]: 63: Hoare triple {2034#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {2034#false} is VALID [2022-02-21 04:23:12,376 INFO L290 TraceCheckUtils]: 64: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___1~0#1); {2034#false} is VALID [2022-02-21 04:23:12,378 INFO L290 TraceCheckUtils]: 65: Hoare triple {2034#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2034#false} is VALID [2022-02-21 04:23:12,378 INFO L290 TraceCheckUtils]: 66: Hoare triple {2034#false} assume !(1 == ~t3_pc~0); {2034#false} is VALID [2022-02-21 04:23:12,379 INFO L290 TraceCheckUtils]: 67: Hoare triple {2034#false} is_transmit3_triggered_~__retres1~3#1 := 0; {2034#false} is VALID [2022-02-21 04:23:12,379 INFO L290 TraceCheckUtils]: 68: Hoare triple {2034#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2034#false} is VALID [2022-02-21 04:23:12,380 INFO L290 TraceCheckUtils]: 69: Hoare triple {2034#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {2034#false} is VALID [2022-02-21 04:23:12,380 INFO L290 TraceCheckUtils]: 70: Hoare triple {2034#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {2034#false} is VALID [2022-02-21 04:23:12,380 INFO L290 TraceCheckUtils]: 71: Hoare triple {2034#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2034#false} is VALID [2022-02-21 04:23:12,380 INFO L290 TraceCheckUtils]: 72: Hoare triple {2034#false} assume 1 == ~t4_pc~0; {2034#false} is VALID [2022-02-21 04:23:12,380 INFO L290 TraceCheckUtils]: 73: Hoare triple {2034#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {2034#false} is VALID [2022-02-21 04:23:12,384 INFO L290 TraceCheckUtils]: 74: Hoare triple {2034#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2034#false} is VALID [2022-02-21 04:23:12,384 INFO L290 TraceCheckUtils]: 75: Hoare triple {2034#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {2034#false} is VALID [2022-02-21 04:23:12,385 INFO L290 TraceCheckUtils]: 76: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___3~0#1); {2034#false} is VALID [2022-02-21 04:23:12,385 INFO L290 TraceCheckUtils]: 77: Hoare triple {2034#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {2034#false} is VALID [2022-02-21 04:23:12,385 INFO L290 TraceCheckUtils]: 78: Hoare triple {2034#false} assume !(1 == ~t5_pc~0); {2034#false} is VALID [2022-02-21 04:23:12,385 INFO L290 TraceCheckUtils]: 79: Hoare triple {2034#false} is_transmit5_triggered_~__retres1~5#1 := 0; {2034#false} is VALID [2022-02-21 04:23:12,385 INFO L290 TraceCheckUtils]: 80: Hoare triple {2034#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {2034#false} is VALID [2022-02-21 04:23:12,386 INFO L290 TraceCheckUtils]: 81: Hoare triple {2034#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {2034#false} is VALID [2022-02-21 04:23:12,386 INFO L290 TraceCheckUtils]: 82: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___4~0#1); {2034#false} is VALID [2022-02-21 04:23:12,386 INFO L290 TraceCheckUtils]: 83: Hoare triple {2034#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {2034#false} is VALID [2022-02-21 04:23:12,386 INFO L290 TraceCheckUtils]: 84: Hoare triple {2034#false} assume 1 == ~t6_pc~0; {2034#false} is VALID [2022-02-21 04:23:12,388 INFO L290 TraceCheckUtils]: 85: Hoare triple {2034#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {2034#false} is VALID [2022-02-21 04:23:12,388 INFO L290 TraceCheckUtils]: 86: Hoare triple {2034#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {2034#false} is VALID [2022-02-21 04:23:12,388 INFO L290 TraceCheckUtils]: 87: Hoare triple {2034#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {2034#false} is VALID [2022-02-21 04:23:12,388 INFO L290 TraceCheckUtils]: 88: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___5~0#1); {2034#false} is VALID [2022-02-21 04:23:12,389 INFO L290 TraceCheckUtils]: 89: Hoare triple {2034#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {2034#false} is VALID [2022-02-21 04:23:12,389 INFO L290 TraceCheckUtils]: 90: Hoare triple {2034#false} assume !(1 == ~t7_pc~0); {2034#false} is VALID [2022-02-21 04:23:12,389 INFO L290 TraceCheckUtils]: 91: Hoare triple {2034#false} is_transmit7_triggered_~__retres1~7#1 := 0; {2034#false} is VALID [2022-02-21 04:23:12,389 INFO L290 TraceCheckUtils]: 92: Hoare triple {2034#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {2034#false} is VALID [2022-02-21 04:23:12,389 INFO L290 TraceCheckUtils]: 93: Hoare triple {2034#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {2034#false} is VALID [2022-02-21 04:23:12,390 INFO L290 TraceCheckUtils]: 94: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___6~0#1); {2034#false} is VALID [2022-02-21 04:23:12,390 INFO L290 TraceCheckUtils]: 95: Hoare triple {2034#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {2034#false} is VALID [2022-02-21 04:23:12,390 INFO L290 TraceCheckUtils]: 96: Hoare triple {2034#false} assume 1 == ~t8_pc~0; {2034#false} is VALID [2022-02-21 04:23:12,390 INFO L290 TraceCheckUtils]: 97: Hoare triple {2034#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {2034#false} is VALID [2022-02-21 04:23:12,391 INFO L290 TraceCheckUtils]: 98: Hoare triple {2034#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {2034#false} is VALID [2022-02-21 04:23:12,391 INFO L290 TraceCheckUtils]: 99: Hoare triple {2034#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {2034#false} is VALID [2022-02-21 04:23:12,391 INFO L290 TraceCheckUtils]: 100: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___7~0#1); {2034#false} is VALID [2022-02-21 04:23:12,391 INFO L290 TraceCheckUtils]: 101: Hoare triple {2034#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {2034#false} is VALID [2022-02-21 04:23:12,391 INFO L290 TraceCheckUtils]: 102: Hoare triple {2034#false} assume 1 == ~t9_pc~0; {2034#false} is VALID [2022-02-21 04:23:12,392 INFO L290 TraceCheckUtils]: 103: Hoare triple {2034#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {2034#false} is VALID [2022-02-21 04:23:12,392 INFO L290 TraceCheckUtils]: 104: Hoare triple {2034#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {2034#false} is VALID [2022-02-21 04:23:12,393 INFO L290 TraceCheckUtils]: 105: Hoare triple {2034#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {2034#false} is VALID [2022-02-21 04:23:12,394 INFO L290 TraceCheckUtils]: 106: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___8~0#1); {2034#false} is VALID [2022-02-21 04:23:12,394 INFO L290 TraceCheckUtils]: 107: Hoare triple {2034#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {2034#false} is VALID [2022-02-21 04:23:12,394 INFO L290 TraceCheckUtils]: 108: Hoare triple {2034#false} assume !(1 == ~t10_pc~0); {2034#false} is VALID [2022-02-21 04:23:12,394 INFO L290 TraceCheckUtils]: 109: Hoare triple {2034#false} is_transmit10_triggered_~__retres1~10#1 := 0; {2034#false} is VALID [2022-02-21 04:23:12,394 INFO L290 TraceCheckUtils]: 110: Hoare triple {2034#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {2034#false} is VALID [2022-02-21 04:23:12,395 INFO L290 TraceCheckUtils]: 111: Hoare triple {2034#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {2034#false} is VALID [2022-02-21 04:23:12,396 INFO L290 TraceCheckUtils]: 112: Hoare triple {2034#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {2034#false} is VALID [2022-02-21 04:23:12,396 INFO L290 TraceCheckUtils]: 113: Hoare triple {2034#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {2034#false} is VALID [2022-02-21 04:23:12,397 INFO L290 TraceCheckUtils]: 114: Hoare triple {2034#false} assume 1 == ~t11_pc~0; {2034#false} is VALID [2022-02-21 04:23:12,397 INFO L290 TraceCheckUtils]: 115: Hoare triple {2034#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {2034#false} is VALID [2022-02-21 04:23:12,403 INFO L290 TraceCheckUtils]: 116: Hoare triple {2034#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {2034#false} is VALID [2022-02-21 04:23:12,404 INFO L290 TraceCheckUtils]: 117: Hoare triple {2034#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {2034#false} is VALID [2022-02-21 04:23:12,405 INFO L290 TraceCheckUtils]: 118: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___10~0#1); {2034#false} is VALID [2022-02-21 04:23:12,405 INFO L290 TraceCheckUtils]: 119: Hoare triple {2034#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {2034#false} is VALID [2022-02-21 04:23:12,406 INFO L290 TraceCheckUtils]: 120: Hoare triple {2034#false} assume !(1 == ~t12_pc~0); {2034#false} is VALID [2022-02-21 04:23:12,406 INFO L290 TraceCheckUtils]: 121: Hoare triple {2034#false} is_transmit12_triggered_~__retres1~12#1 := 0; {2034#false} is VALID [2022-02-21 04:23:12,406 INFO L290 TraceCheckUtils]: 122: Hoare triple {2034#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {2034#false} is VALID [2022-02-21 04:23:12,406 INFO L290 TraceCheckUtils]: 123: Hoare triple {2034#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {2034#false} is VALID [2022-02-21 04:23:12,406 INFO L290 TraceCheckUtils]: 124: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___11~0#1); {2034#false} is VALID [2022-02-21 04:23:12,406 INFO L290 TraceCheckUtils]: 125: Hoare triple {2034#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {2034#false} is VALID [2022-02-21 04:23:12,407 INFO L290 TraceCheckUtils]: 126: Hoare triple {2034#false} assume 1 == ~t13_pc~0; {2034#false} is VALID [2022-02-21 04:23:12,407 INFO L290 TraceCheckUtils]: 127: Hoare triple {2034#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {2034#false} is VALID [2022-02-21 04:23:12,407 INFO L290 TraceCheckUtils]: 128: Hoare triple {2034#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {2034#false} is VALID [2022-02-21 04:23:12,408 INFO L290 TraceCheckUtils]: 129: Hoare triple {2034#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {2034#false} is VALID [2022-02-21 04:23:12,408 INFO L290 TraceCheckUtils]: 130: Hoare triple {2034#false} assume !(0 != activate_threads_~tmp___12~0#1); {2034#false} is VALID [2022-02-21 04:23:12,408 INFO L290 TraceCheckUtils]: 131: Hoare triple {2034#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2034#false} is VALID [2022-02-21 04:23:12,408 INFO L290 TraceCheckUtils]: 132: Hoare triple {2034#false} assume !(1 == ~M_E~0); {2034#false} is VALID [2022-02-21 04:23:12,408 INFO L290 TraceCheckUtils]: 133: Hoare triple {2034#false} assume !(1 == ~T1_E~0); {2034#false} is VALID [2022-02-21 04:23:12,408 INFO L290 TraceCheckUtils]: 134: Hoare triple {2034#false} assume !(1 == ~T2_E~0); {2034#false} is VALID [2022-02-21 04:23:12,408 INFO L290 TraceCheckUtils]: 135: Hoare triple {2034#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,409 INFO L290 TraceCheckUtils]: 136: Hoare triple {2034#false} assume !(1 == ~T4_E~0); {2034#false} is VALID [2022-02-21 04:23:12,409 INFO L290 TraceCheckUtils]: 137: Hoare triple {2034#false} assume !(1 == ~T5_E~0); {2034#false} is VALID [2022-02-21 04:23:12,410 INFO L290 TraceCheckUtils]: 138: Hoare triple {2034#false} assume !(1 == ~T6_E~0); {2034#false} is VALID [2022-02-21 04:23:12,410 INFO L290 TraceCheckUtils]: 139: Hoare triple {2034#false} assume !(1 == ~T7_E~0); {2034#false} is VALID [2022-02-21 04:23:12,410 INFO L290 TraceCheckUtils]: 140: Hoare triple {2034#false} assume !(1 == ~T8_E~0); {2034#false} is VALID [2022-02-21 04:23:12,410 INFO L290 TraceCheckUtils]: 141: Hoare triple {2034#false} assume !(1 == ~T9_E~0); {2034#false} is VALID [2022-02-21 04:23:12,410 INFO L290 TraceCheckUtils]: 142: Hoare triple {2034#false} assume !(1 == ~T10_E~0); {2034#false} is VALID [2022-02-21 04:23:12,411 INFO L290 TraceCheckUtils]: 143: Hoare triple {2034#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,411 INFO L290 TraceCheckUtils]: 144: Hoare triple {2034#false} assume !(1 == ~T12_E~0); {2034#false} is VALID [2022-02-21 04:23:12,411 INFO L290 TraceCheckUtils]: 145: Hoare triple {2034#false} assume !(1 == ~T13_E~0); {2034#false} is VALID [2022-02-21 04:23:12,411 INFO L290 TraceCheckUtils]: 146: Hoare triple {2034#false} assume !(1 == ~E_M~0); {2034#false} is VALID [2022-02-21 04:23:12,411 INFO L290 TraceCheckUtils]: 147: Hoare triple {2034#false} assume !(1 == ~E_1~0); {2034#false} is VALID [2022-02-21 04:23:12,411 INFO L290 TraceCheckUtils]: 148: Hoare triple {2034#false} assume !(1 == ~E_2~0); {2034#false} is VALID [2022-02-21 04:23:12,411 INFO L290 TraceCheckUtils]: 149: Hoare triple {2034#false} assume !(1 == ~E_3~0); {2034#false} is VALID [2022-02-21 04:23:12,412 INFO L290 TraceCheckUtils]: 150: Hoare triple {2034#false} assume !(1 == ~E_4~0); {2034#false} is VALID [2022-02-21 04:23:12,412 INFO L290 TraceCheckUtils]: 151: Hoare triple {2034#false} assume 1 == ~E_5~0;~E_5~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,412 INFO L290 TraceCheckUtils]: 152: Hoare triple {2034#false} assume !(1 == ~E_6~0); {2034#false} is VALID [2022-02-21 04:23:12,412 INFO L290 TraceCheckUtils]: 153: Hoare triple {2034#false} assume !(1 == ~E_7~0); {2034#false} is VALID [2022-02-21 04:23:12,412 INFO L290 TraceCheckUtils]: 154: Hoare triple {2034#false} assume !(1 == ~E_8~0); {2034#false} is VALID [2022-02-21 04:23:12,412 INFO L290 TraceCheckUtils]: 155: Hoare triple {2034#false} assume !(1 == ~E_9~0); {2034#false} is VALID [2022-02-21 04:23:12,412 INFO L290 TraceCheckUtils]: 156: Hoare triple {2034#false} assume !(1 == ~E_10~0); {2034#false} is VALID [2022-02-21 04:23:12,413 INFO L290 TraceCheckUtils]: 157: Hoare triple {2034#false} assume !(1 == ~E_11~0); {2034#false} is VALID [2022-02-21 04:23:12,413 INFO L290 TraceCheckUtils]: 158: Hoare triple {2034#false} assume !(1 == ~E_12~0); {2034#false} is VALID [2022-02-21 04:23:12,413 INFO L290 TraceCheckUtils]: 159: Hoare triple {2034#false} assume 1 == ~E_13~0;~E_13~0 := 2; {2034#false} is VALID [2022-02-21 04:23:12,413 INFO L290 TraceCheckUtils]: 160: Hoare triple {2034#false} assume { :end_inline_reset_delta_events } true; {2034#false} is VALID [2022-02-21 04:23:12,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:12,415 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:12,415 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806223209] [2022-02-21 04:23:12,416 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806223209] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:12,416 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:12,416 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:12,418 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710937020] [2022-02-21 04:23:12,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:12,422 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:12,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:12,424 INFO L85 PathProgramCache]: Analyzing trace with hash -855363910, now seen corresponding path program 1 times [2022-02-21 04:23:12,425 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:12,425 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52467551] [2022-02-21 04:23:12,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:12,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:12,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:12,473 INFO L290 TraceCheckUtils]: 0: Hoare triple {2036#true} assume !false; {2036#true} is VALID [2022-02-21 04:23:12,474 INFO L290 TraceCheckUtils]: 1: Hoare triple {2036#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {2036#true} is VALID [2022-02-21 04:23:12,474 INFO L290 TraceCheckUtils]: 2: Hoare triple {2036#true} assume false; {2037#false} is VALID [2022-02-21 04:23:12,474 INFO L290 TraceCheckUtils]: 3: Hoare triple {2037#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {2037#false} is VALID [2022-02-21 04:23:12,475 INFO L290 TraceCheckUtils]: 4: Hoare triple {2037#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {2037#false} is VALID [2022-02-21 04:23:12,475 INFO L290 TraceCheckUtils]: 5: Hoare triple {2037#false} assume 0 == ~M_E~0;~M_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,475 INFO L290 TraceCheckUtils]: 6: Hoare triple {2037#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,475 INFO L290 TraceCheckUtils]: 7: Hoare triple {2037#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,475 INFO L290 TraceCheckUtils]: 8: Hoare triple {2037#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,476 INFO L290 TraceCheckUtils]: 9: Hoare triple {2037#false} assume !(0 == ~T4_E~0); {2037#false} is VALID [2022-02-21 04:23:12,476 INFO L290 TraceCheckUtils]: 10: Hoare triple {2037#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,476 INFO L290 TraceCheckUtils]: 11: Hoare triple {2037#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,476 INFO L290 TraceCheckUtils]: 12: Hoare triple {2037#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,476 INFO L290 TraceCheckUtils]: 13: Hoare triple {2037#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,476 INFO L290 TraceCheckUtils]: 14: Hoare triple {2037#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,476 INFO L290 TraceCheckUtils]: 15: Hoare triple {2037#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,476 INFO L290 TraceCheckUtils]: 16: Hoare triple {2037#false} assume 0 == ~T11_E~0;~T11_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,476 INFO L290 TraceCheckUtils]: 17: Hoare triple {2037#false} assume !(0 == ~T12_E~0); {2037#false} is VALID [2022-02-21 04:23:12,477 INFO L290 TraceCheckUtils]: 18: Hoare triple {2037#false} assume 0 == ~T13_E~0;~T13_E~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,477 INFO L290 TraceCheckUtils]: 19: Hoare triple {2037#false} assume 0 == ~E_M~0;~E_M~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,477 INFO L290 TraceCheckUtils]: 20: Hoare triple {2037#false} assume 0 == ~E_1~0;~E_1~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,477 INFO L290 TraceCheckUtils]: 21: Hoare triple {2037#false} assume 0 == ~E_2~0;~E_2~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,477 INFO L290 TraceCheckUtils]: 22: Hoare triple {2037#false} assume 0 == ~E_3~0;~E_3~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,477 INFO L290 TraceCheckUtils]: 23: Hoare triple {2037#false} assume 0 == ~E_4~0;~E_4~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,477 INFO L290 TraceCheckUtils]: 24: Hoare triple {2037#false} assume 0 == ~E_5~0;~E_5~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,477 INFO L290 TraceCheckUtils]: 25: Hoare triple {2037#false} assume !(0 == ~E_6~0); {2037#false} is VALID [2022-02-21 04:23:12,477 INFO L290 TraceCheckUtils]: 26: Hoare triple {2037#false} assume 0 == ~E_7~0;~E_7~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,478 INFO L290 TraceCheckUtils]: 27: Hoare triple {2037#false} assume 0 == ~E_8~0;~E_8~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,478 INFO L290 TraceCheckUtils]: 28: Hoare triple {2037#false} assume 0 == ~E_9~0;~E_9~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,478 INFO L290 TraceCheckUtils]: 29: Hoare triple {2037#false} assume 0 == ~E_10~0;~E_10~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,478 INFO L290 TraceCheckUtils]: 30: Hoare triple {2037#false} assume 0 == ~E_11~0;~E_11~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,478 INFO L290 TraceCheckUtils]: 31: Hoare triple {2037#false} assume 0 == ~E_12~0;~E_12~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,478 INFO L290 TraceCheckUtils]: 32: Hoare triple {2037#false} assume 0 == ~E_13~0;~E_13~0 := 1; {2037#false} is VALID [2022-02-21 04:23:12,478 INFO L290 TraceCheckUtils]: 33: Hoare triple {2037#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2037#false} is VALID [2022-02-21 04:23:12,478 INFO L290 TraceCheckUtils]: 34: Hoare triple {2037#false} assume !(1 == ~m_pc~0); {2037#false} is VALID [2022-02-21 04:23:12,478 INFO L290 TraceCheckUtils]: 35: Hoare triple {2037#false} is_master_triggered_~__retres1~0#1 := 0; {2037#false} is VALID [2022-02-21 04:23:12,479 INFO L290 TraceCheckUtils]: 36: Hoare triple {2037#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2037#false} is VALID [2022-02-21 04:23:12,479 INFO L290 TraceCheckUtils]: 37: Hoare triple {2037#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {2037#false} is VALID [2022-02-21 04:23:12,479 INFO L290 TraceCheckUtils]: 38: Hoare triple {2037#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,479 INFO L290 TraceCheckUtils]: 39: Hoare triple {2037#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2037#false} is VALID [2022-02-21 04:23:12,479 INFO L290 TraceCheckUtils]: 40: Hoare triple {2037#false} assume 1 == ~t1_pc~0; {2037#false} is VALID [2022-02-21 04:23:12,479 INFO L290 TraceCheckUtils]: 41: Hoare triple {2037#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {2037#false} is VALID [2022-02-21 04:23:12,479 INFO L290 TraceCheckUtils]: 42: Hoare triple {2037#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2037#false} is VALID [2022-02-21 04:23:12,479 INFO L290 TraceCheckUtils]: 43: Hoare triple {2037#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {2037#false} is VALID [2022-02-21 04:23:12,479 INFO L290 TraceCheckUtils]: 44: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,480 INFO L290 TraceCheckUtils]: 45: Hoare triple {2037#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2037#false} is VALID [2022-02-21 04:23:12,480 INFO L290 TraceCheckUtils]: 46: Hoare triple {2037#false} assume !(1 == ~t2_pc~0); {2037#false} is VALID [2022-02-21 04:23:12,480 INFO L290 TraceCheckUtils]: 47: Hoare triple {2037#false} is_transmit2_triggered_~__retres1~2#1 := 0; {2037#false} is VALID [2022-02-21 04:23:12,480 INFO L290 TraceCheckUtils]: 48: Hoare triple {2037#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2037#false} is VALID [2022-02-21 04:23:12,480 INFO L290 TraceCheckUtils]: 49: Hoare triple {2037#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {2037#false} is VALID [2022-02-21 04:23:12,480 INFO L290 TraceCheckUtils]: 50: Hoare triple {2037#false} assume !(0 != activate_threads_~tmp___1~0#1); {2037#false} is VALID [2022-02-21 04:23:12,480 INFO L290 TraceCheckUtils]: 51: Hoare triple {2037#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2037#false} is VALID [2022-02-21 04:23:12,480 INFO L290 TraceCheckUtils]: 52: Hoare triple {2037#false} assume !(1 == ~t3_pc~0); {2037#false} is VALID [2022-02-21 04:23:12,480 INFO L290 TraceCheckUtils]: 53: Hoare triple {2037#false} is_transmit3_triggered_~__retres1~3#1 := 0; {2037#false} is VALID [2022-02-21 04:23:12,481 INFO L290 TraceCheckUtils]: 54: Hoare triple {2037#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2037#false} is VALID [2022-02-21 04:23:12,481 INFO L290 TraceCheckUtils]: 55: Hoare triple {2037#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {2037#false} is VALID [2022-02-21 04:23:12,481 INFO L290 TraceCheckUtils]: 56: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,481 INFO L290 TraceCheckUtils]: 57: Hoare triple {2037#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2037#false} is VALID [2022-02-21 04:23:12,481 INFO L290 TraceCheckUtils]: 58: Hoare triple {2037#false} assume !(1 == ~t4_pc~0); {2037#false} is VALID [2022-02-21 04:23:12,481 INFO L290 TraceCheckUtils]: 59: Hoare triple {2037#false} is_transmit4_triggered_~__retres1~4#1 := 0; {2037#false} is VALID [2022-02-21 04:23:12,481 INFO L290 TraceCheckUtils]: 60: Hoare triple {2037#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2037#false} is VALID [2022-02-21 04:23:12,481 INFO L290 TraceCheckUtils]: 61: Hoare triple {2037#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {2037#false} is VALID [2022-02-21 04:23:12,481 INFO L290 TraceCheckUtils]: 62: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,482 INFO L290 TraceCheckUtils]: 63: Hoare triple {2037#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {2037#false} is VALID [2022-02-21 04:23:12,482 INFO L290 TraceCheckUtils]: 64: Hoare triple {2037#false} assume 1 == ~t5_pc~0; {2037#false} is VALID [2022-02-21 04:23:12,482 INFO L290 TraceCheckUtils]: 65: Hoare triple {2037#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {2037#false} is VALID [2022-02-21 04:23:12,482 INFO L290 TraceCheckUtils]: 66: Hoare triple {2037#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {2037#false} is VALID [2022-02-21 04:23:12,482 INFO L290 TraceCheckUtils]: 67: Hoare triple {2037#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {2037#false} is VALID [2022-02-21 04:23:12,482 INFO L290 TraceCheckUtils]: 68: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,482 INFO L290 TraceCheckUtils]: 69: Hoare triple {2037#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {2037#false} is VALID [2022-02-21 04:23:12,482 INFO L290 TraceCheckUtils]: 70: Hoare triple {2037#false} assume !(1 == ~t6_pc~0); {2037#false} is VALID [2022-02-21 04:23:12,482 INFO L290 TraceCheckUtils]: 71: Hoare triple {2037#false} is_transmit6_triggered_~__retres1~6#1 := 0; {2037#false} is VALID [2022-02-21 04:23:12,482 INFO L290 TraceCheckUtils]: 72: Hoare triple {2037#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {2037#false} is VALID [2022-02-21 04:23:12,483 INFO L290 TraceCheckUtils]: 73: Hoare triple {2037#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {2037#false} is VALID [2022-02-21 04:23:12,483 INFO L290 TraceCheckUtils]: 74: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,483 INFO L290 TraceCheckUtils]: 75: Hoare triple {2037#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {2037#false} is VALID [2022-02-21 04:23:12,483 INFO L290 TraceCheckUtils]: 76: Hoare triple {2037#false} assume 1 == ~t7_pc~0; {2037#false} is VALID [2022-02-21 04:23:12,483 INFO L290 TraceCheckUtils]: 77: Hoare triple {2037#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {2037#false} is VALID [2022-02-21 04:23:12,483 INFO L290 TraceCheckUtils]: 78: Hoare triple {2037#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {2037#false} is VALID [2022-02-21 04:23:12,484 INFO L290 TraceCheckUtils]: 79: Hoare triple {2037#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {2037#false} is VALID [2022-02-21 04:23:12,484 INFO L290 TraceCheckUtils]: 80: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,484 INFO L290 TraceCheckUtils]: 81: Hoare triple {2037#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {2037#false} is VALID [2022-02-21 04:23:12,484 INFO L290 TraceCheckUtils]: 82: Hoare triple {2037#false} assume !(1 == ~t8_pc~0); {2037#false} is VALID [2022-02-21 04:23:12,484 INFO L290 TraceCheckUtils]: 83: Hoare triple {2037#false} is_transmit8_triggered_~__retres1~8#1 := 0; {2037#false} is VALID [2022-02-21 04:23:12,484 INFO L290 TraceCheckUtils]: 84: Hoare triple {2037#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {2037#false} is VALID [2022-02-21 04:23:12,485 INFO L290 TraceCheckUtils]: 85: Hoare triple {2037#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {2037#false} is VALID [2022-02-21 04:23:12,485 INFO L290 TraceCheckUtils]: 86: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,485 INFO L290 TraceCheckUtils]: 87: Hoare triple {2037#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {2037#false} is VALID [2022-02-21 04:23:12,485 INFO L290 TraceCheckUtils]: 88: Hoare triple {2037#false} assume !(1 == ~t9_pc~0); {2037#false} is VALID [2022-02-21 04:23:12,485 INFO L290 TraceCheckUtils]: 89: Hoare triple {2037#false} is_transmit9_triggered_~__retres1~9#1 := 0; {2037#false} is VALID [2022-02-21 04:23:12,485 INFO L290 TraceCheckUtils]: 90: Hoare triple {2037#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {2037#false} is VALID [2022-02-21 04:23:12,486 INFO L290 TraceCheckUtils]: 91: Hoare triple {2037#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {2037#false} is VALID [2022-02-21 04:23:12,486 INFO L290 TraceCheckUtils]: 92: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,486 INFO L290 TraceCheckUtils]: 93: Hoare triple {2037#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {2037#false} is VALID [2022-02-21 04:23:12,486 INFO L290 TraceCheckUtils]: 94: Hoare triple {2037#false} assume 1 == ~t10_pc~0; {2037#false} is VALID [2022-02-21 04:23:12,486 INFO L290 TraceCheckUtils]: 95: Hoare triple {2037#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {2037#false} is VALID [2022-02-21 04:23:12,486 INFO L290 TraceCheckUtils]: 96: Hoare triple {2037#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {2037#false} is VALID [2022-02-21 04:23:12,487 INFO L290 TraceCheckUtils]: 97: Hoare triple {2037#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {2037#false} is VALID [2022-02-21 04:23:12,487 INFO L290 TraceCheckUtils]: 98: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,487 INFO L290 TraceCheckUtils]: 99: Hoare triple {2037#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {2037#false} is VALID [2022-02-21 04:23:12,487 INFO L290 TraceCheckUtils]: 100: Hoare triple {2037#false} assume !(1 == ~t11_pc~0); {2037#false} is VALID [2022-02-21 04:23:12,487 INFO L290 TraceCheckUtils]: 101: Hoare triple {2037#false} is_transmit11_triggered_~__retres1~11#1 := 0; {2037#false} is VALID [2022-02-21 04:23:12,488 INFO L290 TraceCheckUtils]: 102: Hoare triple {2037#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {2037#false} is VALID [2022-02-21 04:23:12,488 INFO L290 TraceCheckUtils]: 103: Hoare triple {2037#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {2037#false} is VALID [2022-02-21 04:23:12,488 INFO L290 TraceCheckUtils]: 104: Hoare triple {2037#false} assume !(0 != activate_threads_~tmp___10~0#1); {2037#false} is VALID [2022-02-21 04:23:12,488 INFO L290 TraceCheckUtils]: 105: Hoare triple {2037#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {2037#false} is VALID [2022-02-21 04:23:12,488 INFO L290 TraceCheckUtils]: 106: Hoare triple {2037#false} assume !(1 == ~t12_pc~0); {2037#false} is VALID [2022-02-21 04:23:12,488 INFO L290 TraceCheckUtils]: 107: Hoare triple {2037#false} is_transmit12_triggered_~__retres1~12#1 := 0; {2037#false} is VALID [2022-02-21 04:23:12,489 INFO L290 TraceCheckUtils]: 108: Hoare triple {2037#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {2037#false} is VALID [2022-02-21 04:23:12,489 INFO L290 TraceCheckUtils]: 109: Hoare triple {2037#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {2037#false} is VALID [2022-02-21 04:23:12,489 INFO L290 TraceCheckUtils]: 110: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,489 INFO L290 TraceCheckUtils]: 111: Hoare triple {2037#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {2037#false} is VALID [2022-02-21 04:23:12,489 INFO L290 TraceCheckUtils]: 112: Hoare triple {2037#false} assume 1 == ~t13_pc~0; {2037#false} is VALID [2022-02-21 04:23:12,489 INFO L290 TraceCheckUtils]: 113: Hoare triple {2037#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {2037#false} is VALID [2022-02-21 04:23:12,490 INFO L290 TraceCheckUtils]: 114: Hoare triple {2037#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {2037#false} is VALID [2022-02-21 04:23:12,490 INFO L290 TraceCheckUtils]: 115: Hoare triple {2037#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {2037#false} is VALID [2022-02-21 04:23:12,490 INFO L290 TraceCheckUtils]: 116: Hoare triple {2037#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {2037#false} is VALID [2022-02-21 04:23:12,490 INFO L290 TraceCheckUtils]: 117: Hoare triple {2037#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2037#false} is VALID [2022-02-21 04:23:12,490 INFO L290 TraceCheckUtils]: 118: Hoare triple {2037#false} assume 1 == ~M_E~0;~M_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,491 INFO L290 TraceCheckUtils]: 119: Hoare triple {2037#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,491 INFO L290 TraceCheckUtils]: 120: Hoare triple {2037#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,491 INFO L290 TraceCheckUtils]: 121: Hoare triple {2037#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,491 INFO L290 TraceCheckUtils]: 122: Hoare triple {2037#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,491 INFO L290 TraceCheckUtils]: 123: Hoare triple {2037#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,492 INFO L290 TraceCheckUtils]: 124: Hoare triple {2037#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,492 INFO L290 TraceCheckUtils]: 125: Hoare triple {2037#false} assume !(1 == ~T7_E~0); {2037#false} is VALID [2022-02-21 04:23:12,492 INFO L290 TraceCheckUtils]: 126: Hoare triple {2037#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,502 INFO L290 TraceCheckUtils]: 127: Hoare triple {2037#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,503 INFO L290 TraceCheckUtils]: 128: Hoare triple {2037#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,503 INFO L290 TraceCheckUtils]: 129: Hoare triple {2037#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,503 INFO L290 TraceCheckUtils]: 130: Hoare triple {2037#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,503 INFO L290 TraceCheckUtils]: 131: Hoare triple {2037#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,503 INFO L290 TraceCheckUtils]: 132: Hoare triple {2037#false} assume 1 == ~E_M~0;~E_M~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,504 INFO L290 TraceCheckUtils]: 133: Hoare triple {2037#false} assume !(1 == ~E_1~0); {2037#false} is VALID [2022-02-21 04:23:12,504 INFO L290 TraceCheckUtils]: 134: Hoare triple {2037#false} assume 1 == ~E_2~0;~E_2~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,504 INFO L290 TraceCheckUtils]: 135: Hoare triple {2037#false} assume 1 == ~E_3~0;~E_3~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,504 INFO L290 TraceCheckUtils]: 136: Hoare triple {2037#false} assume 1 == ~E_4~0;~E_4~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,504 INFO L290 TraceCheckUtils]: 137: Hoare triple {2037#false} assume 1 == ~E_5~0;~E_5~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,504 INFO L290 TraceCheckUtils]: 138: Hoare triple {2037#false} assume 1 == ~E_6~0;~E_6~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,505 INFO L290 TraceCheckUtils]: 139: Hoare triple {2037#false} assume 1 == ~E_7~0;~E_7~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,505 INFO L290 TraceCheckUtils]: 140: Hoare triple {2037#false} assume 1 == ~E_8~0;~E_8~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,505 INFO L290 TraceCheckUtils]: 141: Hoare triple {2037#false} assume !(1 == ~E_9~0); {2037#false} is VALID [2022-02-21 04:23:12,506 INFO L290 TraceCheckUtils]: 142: Hoare triple {2037#false} assume 1 == ~E_10~0;~E_10~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,508 INFO L290 TraceCheckUtils]: 143: Hoare triple {2037#false} assume 1 == ~E_11~0;~E_11~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,509 INFO L290 TraceCheckUtils]: 144: Hoare triple {2037#false} assume 1 == ~E_12~0;~E_12~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,509 INFO L290 TraceCheckUtils]: 145: Hoare triple {2037#false} assume 1 == ~E_13~0;~E_13~0 := 2; {2037#false} is VALID [2022-02-21 04:23:12,509 INFO L290 TraceCheckUtils]: 146: Hoare triple {2037#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {2037#false} is VALID [2022-02-21 04:23:12,510 INFO L290 TraceCheckUtils]: 147: Hoare triple {2037#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {2037#false} is VALID [2022-02-21 04:23:12,510 INFO L290 TraceCheckUtils]: 148: Hoare triple {2037#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {2037#false} is VALID [2022-02-21 04:23:12,510 INFO L290 TraceCheckUtils]: 149: Hoare triple {2037#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {2037#false} is VALID [2022-02-21 04:23:12,510 INFO L290 TraceCheckUtils]: 150: Hoare triple {2037#false} assume !(0 == start_simulation_~tmp~3#1); {2037#false} is VALID [2022-02-21 04:23:12,510 INFO L290 TraceCheckUtils]: 151: Hoare triple {2037#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {2037#false} is VALID [2022-02-21 04:23:12,512 INFO L290 TraceCheckUtils]: 152: Hoare triple {2037#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {2037#false} is VALID [2022-02-21 04:23:12,512 INFO L290 TraceCheckUtils]: 153: Hoare triple {2037#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {2037#false} is VALID [2022-02-21 04:23:12,512 INFO L290 TraceCheckUtils]: 154: Hoare triple {2037#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {2037#false} is VALID [2022-02-21 04:23:12,512 INFO L290 TraceCheckUtils]: 155: Hoare triple {2037#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {2037#false} is VALID [2022-02-21 04:23:12,512 INFO L290 TraceCheckUtils]: 156: Hoare triple {2037#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {2037#false} is VALID [2022-02-21 04:23:12,513 INFO L290 TraceCheckUtils]: 157: Hoare triple {2037#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {2037#false} is VALID [2022-02-21 04:23:12,513 INFO L290 TraceCheckUtils]: 158: Hoare triple {2037#false} assume !(0 != start_simulation_~tmp___0~1#1); {2037#false} is VALID [2022-02-21 04:23:12,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:12,515 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:12,516 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [52467551] [2022-02-21 04:23:12,516 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [52467551] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:12,516 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:12,516 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:12,516 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408859000] [2022-02-21 04:23:12,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:12,518 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:12,519 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:12,538 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-21 04:23:12,538 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-21 04:23:12,544 INFO L87 Difference]: Start difference. First operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,519 INFO L93 Difference]: Finished difference Result 2027 states and 2998 transitions. [2022-02-21 04:23:13,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-21 04:23:13,520 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,621 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:13,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2027 states and 2998 transitions. [2022-02-21 04:23:13,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:13,886 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2027 states to 2021 states and 2992 transitions. [2022-02-21 04:23:13,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:13,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:13,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2992 transitions. [2022-02-21 04:23:13,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:13,893 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2022-02-21 04:23:13,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2992 transitions. [2022-02-21 04:23:13,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:13,958 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:13,962 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2992 transitions. Second operand has 2021 states, 2021 states have (on average 1.4804552201880257) internal successors, (2992), 2020 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,965 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2992 transitions. Second operand has 2021 states, 2021 states have (on average 1.4804552201880257) internal successors, (2992), 2020 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,968 INFO L87 Difference]: Start difference. First operand 2021 states and 2992 transitions. Second operand has 2021 states, 2021 states have (on average 1.4804552201880257) internal successors, (2992), 2020 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,065 INFO L93 Difference]: Finished difference Result 2021 states and 2992 transitions. [2022-02-21 04:23:14,066 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2992 transitions. [2022-02-21 04:23:14,071 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,071 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,074 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.4804552201880257) internal successors, (2992), 2020 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2992 transitions. [2022-02-21 04:23:14,093 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.4804552201880257) internal successors, (2992), 2020 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2992 transitions. [2022-02-21 04:23:14,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,185 INFO L93 Difference]: Finished difference Result 2021 states and 2992 transitions. [2022-02-21 04:23:14,185 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2992 transitions. [2022-02-21 04:23:14,187 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,187 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,188 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:14,188 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:14,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4804552201880257) internal successors, (2992), 2020 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2992 transitions. [2022-02-21 04:23:14,278 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2022-02-21 04:23:14,278 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2022-02-21 04:23:14,278 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:23:14,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2992 transitions. [2022-02-21 04:23:14,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:14,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:14,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:14,290 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:14,290 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:14,290 INFO L791 eck$LassoCheckResult]: Stem: 4941#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4942#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4673#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4674#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6064#L909 assume !(1 == ~m_i~0);~m_st~0 := 2; 6065#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4860#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4861#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4895#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5732#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5733#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5845#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5846#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4679#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4680#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5882#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5204#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5205#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5786#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6052#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 5942#L1286-2 assume !(0 == ~T1_E~0); 4588#L1291-1 assume !(0 == ~T2_E~0); 4589#L1296-1 assume !(0 == ~T3_E~0); 5294#L1301-1 assume !(0 == ~T4_E~0); 5295#L1306-1 assume !(0 == ~T5_E~0); 5795#L1311-1 assume !(0 == ~T6_E~0); 4548#L1316-1 assume !(0 == ~T7_E~0); 4549#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5314#L1326-1 assume !(0 == ~T9_E~0); 4363#L1331-1 assume !(0 == ~T10_E~0); 4069#L1336-1 assume !(0 == ~T11_E~0); 4070#L1341-1 assume !(0 == ~T12_E~0); 4121#L1346-1 assume !(0 == ~T13_E~0); 4122#L1351-1 assume !(0 == ~E_M~0); 4495#L1356-1 assume !(0 == ~E_1~0); 4496#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 6015#L1366-1 assume !(0 == ~E_3~0); 4541#L1371-1 assume !(0 == ~E_4~0); 4542#L1376-1 assume !(0 == ~E_5~0); 5355#L1381-1 assume !(0 == ~E_6~0); 5356#L1386-1 assume !(0 == ~E_7~0); 6043#L1391-1 assume !(0 == ~E_8~0); 6056#L1396-1 assume !(0 == ~E_9~0); 5238#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5239#L1406-1 assume !(0 == ~E_11~0); 5541#L1411-1 assume !(0 == ~E_12~0); 5542#L1416-1 assume !(0 == ~E_13~0); 5162#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5000#L635 assume !(1 == ~m_pc~0); 4139#L635-2 is_master_triggered_~__retres1~0#1 := 0; 4140#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4490#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5126#L1598 assume !(0 != activate_threads_~tmp~1#1); 4318#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4319#L654 assume 1 == ~t1_pc~0; 5024#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5025#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6040#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5106#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 5107#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4366#L673 assume 1 == ~t2_pc~0; 4367#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5511#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5512#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6070#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 6077#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5185#L692 assume !(1 == ~t3_pc~0); 5002#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5003#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4862#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4830#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4831#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4391#L711 assume 1 == ~t4_pc~0; 4392#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4875#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5332#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4094#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 4095#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6063#L730 assume !(1 == ~t5_pc~0); 5445#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4273#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4274#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4401#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 4402#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4744#L749 assume 1 == ~t6_pc~0; 4518#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4278#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4710#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4711#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 4933#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4074#L768 assume !(1 == ~t7_pc~0); 4075#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5379#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4311#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4312#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 5398#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4550#L787 assume 1 == ~t8_pc~0; 4551#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5746#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5910#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5911#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 4119#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4120#L806 assume 1 == ~t9_pc~0; 5757#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4154#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4155#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4403#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 4404#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5740#L825 assume !(1 == ~t10_pc~0); 5741#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5346#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5347#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4491#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4492#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5075#L844 assume 1 == ~t11_pc~0; 4765#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4766#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5132#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5133#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 5728#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5729#L863 assume !(1 == ~t12_pc~0); 4254#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4253#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4481#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5820#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 5821#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5199#L882 assume 1 == ~t13_pc~0; 5200#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5484#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5985#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5788#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 5471#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5472#L1434 assume !(1 == ~M_E~0); 5993#L1434-2 assume !(1 == ~T1_E~0); 6069#L1439-1 assume !(1 == ~T2_E~0); 4384#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4385#L1449-1 assume !(1 == ~T4_E~0); 4827#L1454-1 assume !(1 == ~T5_E~0); 4828#L1459-1 assume !(1 == ~T6_E~0); 5399#L1464-1 assume !(1 == ~T7_E~0); 5400#L1469-1 assume !(1 == ~T8_E~0); 5485#L1474-1 assume !(1 == ~T9_E~0); 5163#L1479-1 assume !(1 == ~T10_E~0); 5164#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5407#L1489-1 assume !(1 == ~T12_E~0); 5041#L1494-1 assume !(1 == ~T13_E~0); 5042#L1499-1 assume !(1 == ~E_M~0); 5223#L1504-1 assume !(1 == ~E_1~0); 5224#L1509-1 assume !(1 == ~E_2~0); 5837#L1514-1 assume !(1 == ~E_3~0); 5522#L1519-1 assume !(1 == ~E_4~0); 5523#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6027#L1529-1 assume !(1 == ~E_6~0); 6028#L1534-1 assume !(1 == ~E_7~0); 4174#L1539-1 assume !(1 == ~E_8~0); 4175#L1544-1 assume !(1 == ~E_9~0); 4605#L1549-1 assume !(1 == ~E_10~0); 6005#L1554-1 assume !(1 == ~E_11~0); 6003#L1559-1 assume !(1 == ~E_12~0); 5865#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 5866#L1569-1 assume { :end_inline_reset_delta_events } true; 6021#L1935-2 [2022-02-21 04:23:14,292 INFO L793 eck$LassoCheckResult]: Loop: 6021#L1935-2 assume !false; 4183#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4184#L1261 assume !false; 5411#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5412#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4314#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4484#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4485#L1074 assume !(0 != eval_~tmp~0#1); 4842#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5440#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5841#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5897#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5616#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5617#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6053#L1301-3 assume !(0 == ~T4_E~0); 6011#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5119#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4418#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4419#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4524#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5260#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5525#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5526#L1341-3 assume !(0 == ~T12_E~0); 4820#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4811#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4755#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4756#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5336#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4109#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4110#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5852#L1381-3 assume !(0 == ~E_6~0); 5701#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5702#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5883#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5884#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4489#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4320#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4321#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 4948#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4198#L635-45 assume 1 == ~m_pc~0; 4199#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4993#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5473#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5727#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4507#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4508#L654-45 assume 1 == ~t1_pc~0; 5328#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5676#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4161#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4162#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4187#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5014#L673-45 assume !(1 == ~t2_pc~0); 5015#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5339#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5340#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5965#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 5785#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4632#L692-45 assume !(1 == ~t3_pc~0); 4358#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 4359#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5403#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4686#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4687#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4999#L711-45 assume 1 == ~t4_pc~0; 5123#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5124#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4976#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4977#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5380#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4531#L730-45 assume 1 == ~t5_pc~0; 4369#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4370#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4779#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4780#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5531#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4342#L749-45 assume !(1 == ~t6_pc~0); 4343#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 5743#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5506#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5507#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5658#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4658#L768-45 assume 1 == ~t7_pc~0; 4659#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4798#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5602#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5603#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5642#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5643#L787-45 assume 1 == ~t8_pc~0; 5811#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4804#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4805#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5221#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5222#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5530#L806-45 assume 1 == ~t9_pc~0; 6006#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4218#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5043#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4871#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4783#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4784#L825-45 assume 1 == ~t10_pc~0; 5395#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5308#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5413#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5414#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5566#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4426#L844-45 assume !(1 == ~t11_pc~0); 4427#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4949#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4950#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4966#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 5377#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4466#L863-45 assume 1 == ~t12_pc~0; 4467#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4067#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4068#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4583#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4584#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5383#L882-45 assume !(1 == ~t13_pc~0); 4913#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 4086#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4087#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4695#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5874#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5490#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5491#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5675#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4380#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4381#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4543#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5480#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5481#L1464-3 assume !(1 == ~T7_E~0); 5927#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5854#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5855#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5929#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5121#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5122#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5782#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5417#L1504-3 assume !(1 == ~E_1~0); 5418#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5863#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5903#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5044#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5045#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5950#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5345#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4799#L1544-3 assume !(1 == ~E_9~0); 4800#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5315#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4431#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4432#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5581#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5582#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4316#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4881#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5552#L1954 assume !(0 == start_simulation_~tmp~3#1); 5554#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5804#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4599#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5640#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5770#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5771#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5861#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5923#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 6021#L1935-2 [2022-02-21 04:23:14,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:14,293 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2022-02-21 04:23:14,293 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:14,293 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063395808] [2022-02-21 04:23:14,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:14,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:14,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:14,366 INFO L290 TraceCheckUtils]: 0: Hoare triple {10131#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {10131#true} is VALID [2022-02-21 04:23:14,366 INFO L290 TraceCheckUtils]: 1: Hoare triple {10131#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {10133#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 2: Hoare triple {10133#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10133#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 3: Hoare triple {10133#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10133#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 4: Hoare triple {10133#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 5: Hoare triple {10132#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10132#false} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 6: Hoare triple {10132#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 7: Hoare triple {10132#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 8: Hoare triple {10132#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 9: Hoare triple {10132#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 10: Hoare triple {10132#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 11: Hoare triple {10132#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 12: Hoare triple {10132#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 13: Hoare triple {10132#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {10132#false} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 14: Hoare triple {10132#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 15: Hoare triple {10132#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 16: Hoare triple {10132#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 17: Hoare triple {10132#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 18: Hoare triple {10132#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10132#false} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 19: Hoare triple {10132#false} assume 0 == ~M_E~0;~M_E~0 := 1; {10132#false} is VALID [2022-02-21 04:23:14,370 INFO L290 TraceCheckUtils]: 20: Hoare triple {10132#false} assume !(0 == ~T1_E~0); {10132#false} is VALID [2022-02-21 04:23:14,374 INFO L290 TraceCheckUtils]: 21: Hoare triple {10132#false} assume !(0 == ~T2_E~0); {10132#false} is VALID [2022-02-21 04:23:14,374 INFO L290 TraceCheckUtils]: 22: Hoare triple {10132#false} assume !(0 == ~T3_E~0); {10132#false} is VALID [2022-02-21 04:23:14,375 INFO L290 TraceCheckUtils]: 23: Hoare triple {10132#false} assume !(0 == ~T4_E~0); {10132#false} is VALID [2022-02-21 04:23:14,375 INFO L290 TraceCheckUtils]: 24: Hoare triple {10132#false} assume !(0 == ~T5_E~0); {10132#false} is VALID [2022-02-21 04:23:14,375 INFO L290 TraceCheckUtils]: 25: Hoare triple {10132#false} assume !(0 == ~T6_E~0); {10132#false} is VALID [2022-02-21 04:23:14,375 INFO L290 TraceCheckUtils]: 26: Hoare triple {10132#false} assume !(0 == ~T7_E~0); {10132#false} is VALID [2022-02-21 04:23:14,375 INFO L290 TraceCheckUtils]: 27: Hoare triple {10132#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {10132#false} is VALID [2022-02-21 04:23:14,375 INFO L290 TraceCheckUtils]: 28: Hoare triple {10132#false} assume !(0 == ~T9_E~0); {10132#false} is VALID [2022-02-21 04:23:14,376 INFO L290 TraceCheckUtils]: 29: Hoare triple {10132#false} assume !(0 == ~T10_E~0); {10132#false} is VALID [2022-02-21 04:23:14,376 INFO L290 TraceCheckUtils]: 30: Hoare triple {10132#false} assume !(0 == ~T11_E~0); {10132#false} is VALID [2022-02-21 04:23:14,376 INFO L290 TraceCheckUtils]: 31: Hoare triple {10132#false} assume !(0 == ~T12_E~0); {10132#false} is VALID [2022-02-21 04:23:14,376 INFO L290 TraceCheckUtils]: 32: Hoare triple {10132#false} assume !(0 == ~T13_E~0); {10132#false} is VALID [2022-02-21 04:23:14,376 INFO L290 TraceCheckUtils]: 33: Hoare triple {10132#false} assume !(0 == ~E_M~0); {10132#false} is VALID [2022-02-21 04:23:14,376 INFO L290 TraceCheckUtils]: 34: Hoare triple {10132#false} assume !(0 == ~E_1~0); {10132#false} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 35: Hoare triple {10132#false} assume 0 == ~E_2~0;~E_2~0 := 1; {10132#false} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 36: Hoare triple {10132#false} assume !(0 == ~E_3~0); {10132#false} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 37: Hoare triple {10132#false} assume !(0 == ~E_4~0); {10132#false} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 38: Hoare triple {10132#false} assume !(0 == ~E_5~0); {10132#false} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 39: Hoare triple {10132#false} assume !(0 == ~E_6~0); {10132#false} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 40: Hoare triple {10132#false} assume !(0 == ~E_7~0); {10132#false} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 41: Hoare triple {10132#false} assume !(0 == ~E_8~0); {10132#false} is VALID [2022-02-21 04:23:14,378 INFO L290 TraceCheckUtils]: 42: Hoare triple {10132#false} assume !(0 == ~E_9~0); {10132#false} is VALID [2022-02-21 04:23:14,378 INFO L290 TraceCheckUtils]: 43: Hoare triple {10132#false} assume 0 == ~E_10~0;~E_10~0 := 1; {10132#false} is VALID [2022-02-21 04:23:14,378 INFO L290 TraceCheckUtils]: 44: Hoare triple {10132#false} assume !(0 == ~E_11~0); {10132#false} is VALID [2022-02-21 04:23:14,378 INFO L290 TraceCheckUtils]: 45: Hoare triple {10132#false} assume !(0 == ~E_12~0); {10132#false} is VALID [2022-02-21 04:23:14,378 INFO L290 TraceCheckUtils]: 46: Hoare triple {10132#false} assume !(0 == ~E_13~0); {10132#false} is VALID [2022-02-21 04:23:14,378 INFO L290 TraceCheckUtils]: 47: Hoare triple {10132#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10132#false} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 48: Hoare triple {10132#false} assume !(1 == ~m_pc~0); {10132#false} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 49: Hoare triple {10132#false} is_master_triggered_~__retres1~0#1 := 0; {10132#false} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 50: Hoare triple {10132#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10132#false} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 51: Hoare triple {10132#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10132#false} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 52: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp~1#1); {10132#false} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 53: Hoare triple {10132#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10132#false} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 54: Hoare triple {10132#false} assume 1 == ~t1_pc~0; {10132#false} is VALID [2022-02-21 04:23:14,380 INFO L290 TraceCheckUtils]: 55: Hoare triple {10132#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10132#false} is VALID [2022-02-21 04:23:14,380 INFO L290 TraceCheckUtils]: 56: Hoare triple {10132#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10132#false} is VALID [2022-02-21 04:23:14,384 INFO L290 TraceCheckUtils]: 57: Hoare triple {10132#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10132#false} is VALID [2022-02-21 04:23:14,384 INFO L290 TraceCheckUtils]: 58: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___0~0#1); {10132#false} is VALID [2022-02-21 04:23:14,385 INFO L290 TraceCheckUtils]: 59: Hoare triple {10132#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10132#false} is VALID [2022-02-21 04:23:14,385 INFO L290 TraceCheckUtils]: 60: Hoare triple {10132#false} assume 1 == ~t2_pc~0; {10132#false} is VALID [2022-02-21 04:23:14,385 INFO L290 TraceCheckUtils]: 61: Hoare triple {10132#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10132#false} is VALID [2022-02-21 04:23:14,385 INFO L290 TraceCheckUtils]: 62: Hoare triple {10132#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10132#false} is VALID [2022-02-21 04:23:14,385 INFO L290 TraceCheckUtils]: 63: Hoare triple {10132#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {10132#false} is VALID [2022-02-21 04:23:14,385 INFO L290 TraceCheckUtils]: 64: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___1~0#1); {10132#false} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 65: Hoare triple {10132#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10132#false} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 66: Hoare triple {10132#false} assume !(1 == ~t3_pc~0); {10132#false} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 67: Hoare triple {10132#false} is_transmit3_triggered_~__retres1~3#1 := 0; {10132#false} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 68: Hoare triple {10132#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10132#false} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 69: Hoare triple {10132#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {10132#false} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 70: Hoare triple {10132#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10132#false} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 71: Hoare triple {10132#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10132#false} is VALID [2022-02-21 04:23:14,387 INFO L290 TraceCheckUtils]: 72: Hoare triple {10132#false} assume 1 == ~t4_pc~0; {10132#false} is VALID [2022-02-21 04:23:14,387 INFO L290 TraceCheckUtils]: 73: Hoare triple {10132#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10132#false} is VALID [2022-02-21 04:23:14,387 INFO L290 TraceCheckUtils]: 74: Hoare triple {10132#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10132#false} is VALID [2022-02-21 04:23:14,387 INFO L290 TraceCheckUtils]: 75: Hoare triple {10132#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {10132#false} is VALID [2022-02-21 04:23:14,387 INFO L290 TraceCheckUtils]: 76: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___3~0#1); {10132#false} is VALID [2022-02-21 04:23:14,387 INFO L290 TraceCheckUtils]: 77: Hoare triple {10132#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10132#false} is VALID [2022-02-21 04:23:14,388 INFO L290 TraceCheckUtils]: 78: Hoare triple {10132#false} assume !(1 == ~t5_pc~0); {10132#false} is VALID [2022-02-21 04:23:14,388 INFO L290 TraceCheckUtils]: 79: Hoare triple {10132#false} is_transmit5_triggered_~__retres1~5#1 := 0; {10132#false} is VALID [2022-02-21 04:23:14,388 INFO L290 TraceCheckUtils]: 80: Hoare triple {10132#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10132#false} is VALID [2022-02-21 04:23:14,388 INFO L290 TraceCheckUtils]: 81: Hoare triple {10132#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {10132#false} is VALID [2022-02-21 04:23:14,388 INFO L290 TraceCheckUtils]: 82: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___4~0#1); {10132#false} is VALID [2022-02-21 04:23:14,388 INFO L290 TraceCheckUtils]: 83: Hoare triple {10132#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10132#false} is VALID [2022-02-21 04:23:14,388 INFO L290 TraceCheckUtils]: 84: Hoare triple {10132#false} assume 1 == ~t6_pc~0; {10132#false} is VALID [2022-02-21 04:23:14,389 INFO L290 TraceCheckUtils]: 85: Hoare triple {10132#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10132#false} is VALID [2022-02-21 04:23:14,389 INFO L290 TraceCheckUtils]: 86: Hoare triple {10132#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10132#false} is VALID [2022-02-21 04:23:14,389 INFO L290 TraceCheckUtils]: 87: Hoare triple {10132#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {10132#false} is VALID [2022-02-21 04:23:14,389 INFO L290 TraceCheckUtils]: 88: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___5~0#1); {10132#false} is VALID [2022-02-21 04:23:14,389 INFO L290 TraceCheckUtils]: 89: Hoare triple {10132#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10132#false} is VALID [2022-02-21 04:23:14,391 INFO L290 TraceCheckUtils]: 90: Hoare triple {10132#false} assume !(1 == ~t7_pc~0); {10132#false} is VALID [2022-02-21 04:23:14,391 INFO L290 TraceCheckUtils]: 91: Hoare triple {10132#false} is_transmit7_triggered_~__retres1~7#1 := 0; {10132#false} is VALID [2022-02-21 04:23:14,391 INFO L290 TraceCheckUtils]: 92: Hoare triple {10132#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10132#false} is VALID [2022-02-21 04:23:14,391 INFO L290 TraceCheckUtils]: 93: Hoare triple {10132#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {10132#false} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 94: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___6~0#1); {10132#false} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 95: Hoare triple {10132#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {10132#false} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 96: Hoare triple {10132#false} assume 1 == ~t8_pc~0; {10132#false} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 97: Hoare triple {10132#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {10132#false} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 98: Hoare triple {10132#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {10132#false} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 99: Hoare triple {10132#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {10132#false} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 100: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___7~0#1); {10132#false} is VALID [2022-02-21 04:23:14,393 INFO L290 TraceCheckUtils]: 101: Hoare triple {10132#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {10132#false} is VALID [2022-02-21 04:23:14,393 INFO L290 TraceCheckUtils]: 102: Hoare triple {10132#false} assume 1 == ~t9_pc~0; {10132#false} is VALID [2022-02-21 04:23:14,393 INFO L290 TraceCheckUtils]: 103: Hoare triple {10132#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {10132#false} is VALID [2022-02-21 04:23:14,393 INFO L290 TraceCheckUtils]: 104: Hoare triple {10132#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {10132#false} is VALID [2022-02-21 04:23:14,393 INFO L290 TraceCheckUtils]: 105: Hoare triple {10132#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {10132#false} is VALID [2022-02-21 04:23:14,393 INFO L290 TraceCheckUtils]: 106: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___8~0#1); {10132#false} is VALID [2022-02-21 04:23:14,393 INFO L290 TraceCheckUtils]: 107: Hoare triple {10132#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {10132#false} is VALID [2022-02-21 04:23:14,394 INFO L290 TraceCheckUtils]: 108: Hoare triple {10132#false} assume !(1 == ~t10_pc~0); {10132#false} is VALID [2022-02-21 04:23:14,394 INFO L290 TraceCheckUtils]: 109: Hoare triple {10132#false} is_transmit10_triggered_~__retres1~10#1 := 0; {10132#false} is VALID [2022-02-21 04:23:14,394 INFO L290 TraceCheckUtils]: 110: Hoare triple {10132#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {10132#false} is VALID [2022-02-21 04:23:14,394 INFO L290 TraceCheckUtils]: 111: Hoare triple {10132#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {10132#false} is VALID [2022-02-21 04:23:14,394 INFO L290 TraceCheckUtils]: 112: Hoare triple {10132#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {10132#false} is VALID [2022-02-21 04:23:14,395 INFO L290 TraceCheckUtils]: 113: Hoare triple {10132#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {10132#false} is VALID [2022-02-21 04:23:14,395 INFO L290 TraceCheckUtils]: 114: Hoare triple {10132#false} assume 1 == ~t11_pc~0; {10132#false} is VALID [2022-02-21 04:23:14,395 INFO L290 TraceCheckUtils]: 115: Hoare triple {10132#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {10132#false} is VALID [2022-02-21 04:23:14,395 INFO L290 TraceCheckUtils]: 116: Hoare triple {10132#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {10132#false} is VALID [2022-02-21 04:23:14,396 INFO L290 TraceCheckUtils]: 117: Hoare triple {10132#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {10132#false} is VALID [2022-02-21 04:23:14,396 INFO L290 TraceCheckUtils]: 118: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___10~0#1); {10132#false} is VALID [2022-02-21 04:23:14,396 INFO L290 TraceCheckUtils]: 119: Hoare triple {10132#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {10132#false} is VALID [2022-02-21 04:23:14,396 INFO L290 TraceCheckUtils]: 120: Hoare triple {10132#false} assume !(1 == ~t12_pc~0); {10132#false} is VALID [2022-02-21 04:23:14,396 INFO L290 TraceCheckUtils]: 121: Hoare triple {10132#false} is_transmit12_triggered_~__retres1~12#1 := 0; {10132#false} is VALID [2022-02-21 04:23:14,396 INFO L290 TraceCheckUtils]: 122: Hoare triple {10132#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {10132#false} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 123: Hoare triple {10132#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {10132#false} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 124: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___11~0#1); {10132#false} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 125: Hoare triple {10132#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {10132#false} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 126: Hoare triple {10132#false} assume 1 == ~t13_pc~0; {10132#false} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 127: Hoare triple {10132#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {10132#false} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 128: Hoare triple {10132#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {10132#false} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 129: Hoare triple {10132#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {10132#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 130: Hoare triple {10132#false} assume !(0 != activate_threads_~tmp___12~0#1); {10132#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 131: Hoare triple {10132#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10132#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 132: Hoare triple {10132#false} assume !(1 == ~M_E~0); {10132#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 133: Hoare triple {10132#false} assume !(1 == ~T1_E~0); {10132#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 134: Hoare triple {10132#false} assume !(1 == ~T2_E~0); {10132#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 135: Hoare triple {10132#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 136: Hoare triple {10132#false} assume !(1 == ~T4_E~0); {10132#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 137: Hoare triple {10132#false} assume !(1 == ~T5_E~0); {10132#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 138: Hoare triple {10132#false} assume !(1 == ~T6_E~0); {10132#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 139: Hoare triple {10132#false} assume !(1 == ~T7_E~0); {10132#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 140: Hoare triple {10132#false} assume !(1 == ~T8_E~0); {10132#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 141: Hoare triple {10132#false} assume !(1 == ~T9_E~0); {10132#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 142: Hoare triple {10132#false} assume !(1 == ~T10_E~0); {10132#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 143: Hoare triple {10132#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 144: Hoare triple {10132#false} assume !(1 == ~T12_E~0); {10132#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 145: Hoare triple {10132#false} assume !(1 == ~T13_E~0); {10132#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 146: Hoare triple {10132#false} assume !(1 == ~E_M~0); {10132#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 147: Hoare triple {10132#false} assume !(1 == ~E_1~0); {10132#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 148: Hoare triple {10132#false} assume !(1 == ~E_2~0); {10132#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 149: Hoare triple {10132#false} assume !(1 == ~E_3~0); {10132#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 150: Hoare triple {10132#false} assume !(1 == ~E_4~0); {10132#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 151: Hoare triple {10132#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 152: Hoare triple {10132#false} assume !(1 == ~E_6~0); {10132#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 153: Hoare triple {10132#false} assume !(1 == ~E_7~0); {10132#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 154: Hoare triple {10132#false} assume !(1 == ~E_8~0); {10132#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 155: Hoare triple {10132#false} assume !(1 == ~E_9~0); {10132#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 156: Hoare triple {10132#false} assume !(1 == ~E_10~0); {10132#false} is VALID [2022-02-21 04:23:14,402 INFO L290 TraceCheckUtils]: 157: Hoare triple {10132#false} assume !(1 == ~E_11~0); {10132#false} is VALID [2022-02-21 04:23:14,402 INFO L290 TraceCheckUtils]: 158: Hoare triple {10132#false} assume !(1 == ~E_12~0); {10132#false} is VALID [2022-02-21 04:23:14,402 INFO L290 TraceCheckUtils]: 159: Hoare triple {10132#false} assume 1 == ~E_13~0;~E_13~0 := 2; {10132#false} is VALID [2022-02-21 04:23:14,402 INFO L290 TraceCheckUtils]: 160: Hoare triple {10132#false} assume { :end_inline_reset_delta_events } true; {10132#false} is VALID [2022-02-21 04:23:14,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:14,406 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:14,406 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063395808] [2022-02-21 04:23:14,406 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2063395808] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:14,407 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:14,407 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:14,407 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508736380] [2022-02-21 04:23:14,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:14,408 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:14,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:14,409 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 1 times [2022-02-21 04:23:14,409 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:14,409 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014553691] [2022-02-21 04:23:14,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:14,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:14,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 0: Hoare triple {10134#true} assume !false; {10134#true} is VALID [2022-02-21 04:23:14,521 INFO L290 TraceCheckUtils]: 1: Hoare triple {10134#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10134#true} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 2: Hoare triple {10134#true} assume !false; {10134#true} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 3: Hoare triple {10134#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {10134#true} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 4: Hoare triple {10134#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {10134#true} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 5: Hoare triple {10134#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {10134#true} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 6: Hoare triple {10134#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {10134#true} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 7: Hoare triple {10134#true} assume !(0 != eval_~tmp~0#1); {10134#true} is VALID [2022-02-21 04:23:14,522 INFO L290 TraceCheckUtils]: 8: Hoare triple {10134#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10134#true} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 9: Hoare triple {10134#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10134#true} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 10: Hoare triple {10134#true} assume 0 == ~M_E~0;~M_E~0 := 1; {10134#true} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 11: Hoare triple {10134#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {10134#true} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 12: Hoare triple {10134#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {10134#true} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 13: Hoare triple {10134#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10134#true} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 14: Hoare triple {10134#true} assume !(0 == ~T4_E~0); {10134#true} is VALID [2022-02-21 04:23:14,523 INFO L290 TraceCheckUtils]: 15: Hoare triple {10134#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {10134#true} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 16: Hoare triple {10134#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10134#true} is VALID [2022-02-21 04:23:14,524 INFO L290 TraceCheckUtils]: 17: Hoare triple {10134#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,525 INFO L290 TraceCheckUtils]: 18: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 19: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,529 INFO L290 TraceCheckUtils]: 20: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 21: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 22: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,530 INFO L290 TraceCheckUtils]: 23: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 24: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 25: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,531 INFO L290 TraceCheckUtils]: 26: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,533 INFO L290 TraceCheckUtils]: 27: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 28: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 29: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,534 INFO L290 TraceCheckUtils]: 30: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 31: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 32: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 33: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,535 INFO L290 TraceCheckUtils]: 34: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,536 INFO L290 TraceCheckUtils]: 35: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,536 INFO L290 TraceCheckUtils]: 36: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,536 INFO L290 TraceCheckUtils]: 37: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,541 INFO L290 TraceCheckUtils]: 38: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,542 INFO L290 TraceCheckUtils]: 39: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,542 INFO L290 TraceCheckUtils]: 40: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,542 INFO L290 TraceCheckUtils]: 41: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,543 INFO L290 TraceCheckUtils]: 42: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,543 INFO L290 TraceCheckUtils]: 43: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,543 INFO L290 TraceCheckUtils]: 44: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,543 INFO L290 TraceCheckUtils]: 45: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,544 INFO L290 TraceCheckUtils]: 46: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,544 INFO L290 TraceCheckUtils]: 47: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,544 INFO L290 TraceCheckUtils]: 48: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,545 INFO L290 TraceCheckUtils]: 49: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,545 INFO L290 TraceCheckUtils]: 50: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,545 INFO L290 TraceCheckUtils]: 51: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,545 INFO L290 TraceCheckUtils]: 52: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,546 INFO L290 TraceCheckUtils]: 53: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,546 INFO L290 TraceCheckUtils]: 54: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,546 INFO L290 TraceCheckUtils]: 55: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,547 INFO L290 TraceCheckUtils]: 56: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,547 INFO L290 TraceCheckUtils]: 57: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,547 INFO L290 TraceCheckUtils]: 58: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,547 INFO L290 TraceCheckUtils]: 59: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,548 INFO L290 TraceCheckUtils]: 60: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,548 INFO L290 TraceCheckUtils]: 61: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,548 INFO L290 TraceCheckUtils]: 62: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,549 INFO L290 TraceCheckUtils]: 63: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,549 INFO L290 TraceCheckUtils]: 64: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,550 INFO L290 TraceCheckUtils]: 65: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,550 INFO L290 TraceCheckUtils]: 66: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,550 INFO L290 TraceCheckUtils]: 67: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,551 INFO L290 TraceCheckUtils]: 68: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,551 INFO L290 TraceCheckUtils]: 69: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,551 INFO L290 TraceCheckUtils]: 70: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,551 INFO L290 TraceCheckUtils]: 71: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,552 INFO L290 TraceCheckUtils]: 72: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,552 INFO L290 TraceCheckUtils]: 73: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,552 INFO L290 TraceCheckUtils]: 74: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,553 INFO L290 TraceCheckUtils]: 75: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,553 INFO L290 TraceCheckUtils]: 76: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,553 INFO L290 TraceCheckUtils]: 77: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,553 INFO L290 TraceCheckUtils]: 78: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,554 INFO L290 TraceCheckUtils]: 79: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,554 INFO L290 TraceCheckUtils]: 80: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,554 INFO L290 TraceCheckUtils]: 81: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,555 INFO L290 TraceCheckUtils]: 82: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,555 INFO L290 TraceCheckUtils]: 83: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,555 INFO L290 TraceCheckUtils]: 84: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,556 INFO L290 TraceCheckUtils]: 85: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,556 INFO L290 TraceCheckUtils]: 86: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,556 INFO L290 TraceCheckUtils]: 87: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t8_pc~0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,557 INFO L290 TraceCheckUtils]: 88: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,557 INFO L290 TraceCheckUtils]: 89: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,557 INFO L290 TraceCheckUtils]: 90: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,557 INFO L290 TraceCheckUtils]: 91: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,558 INFO L290 TraceCheckUtils]: 92: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,558 INFO L290 TraceCheckUtils]: 93: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,558 INFO L290 TraceCheckUtils]: 94: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,559 INFO L290 TraceCheckUtils]: 95: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,559 INFO L290 TraceCheckUtils]: 96: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,559 INFO L290 TraceCheckUtils]: 97: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,560 INFO L290 TraceCheckUtils]: 98: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,560 INFO L290 TraceCheckUtils]: 99: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t10_pc~0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,560 INFO L290 TraceCheckUtils]: 100: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,560 INFO L290 TraceCheckUtils]: 101: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,561 INFO L290 TraceCheckUtils]: 102: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,561 INFO L290 TraceCheckUtils]: 103: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,561 INFO L290 TraceCheckUtils]: 104: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,562 INFO L290 TraceCheckUtils]: 105: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,562 INFO L290 TraceCheckUtils]: 106: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,562 INFO L290 TraceCheckUtils]: 107: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,562 INFO L290 TraceCheckUtils]: 108: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,563 INFO L290 TraceCheckUtils]: 109: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,563 INFO L290 TraceCheckUtils]: 110: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,563 INFO L290 TraceCheckUtils]: 111: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,564 INFO L290 TraceCheckUtils]: 112: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,564 INFO L290 TraceCheckUtils]: 113: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,564 INFO L290 TraceCheckUtils]: 114: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,564 INFO L290 TraceCheckUtils]: 115: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,565 INFO L290 TraceCheckUtils]: 116: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,565 INFO L290 TraceCheckUtils]: 117: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t13_pc~0); {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,565 INFO L290 TraceCheckUtils]: 118: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,565 INFO L290 TraceCheckUtils]: 119: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,566 INFO L290 TraceCheckUtils]: 120: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,566 INFO L290 TraceCheckUtils]: 121: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,566 INFO L290 TraceCheckUtils]: 122: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,567 INFO L290 TraceCheckUtils]: 123: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,567 INFO L290 TraceCheckUtils]: 124: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,567 INFO L290 TraceCheckUtils]: 125: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,567 INFO L290 TraceCheckUtils]: 126: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,568 INFO L290 TraceCheckUtils]: 127: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,568 INFO L290 TraceCheckUtils]: 128: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,568 INFO L290 TraceCheckUtils]: 129: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {10136#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:14,569 INFO L290 TraceCheckUtils]: 130: Hoare triple {10136#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {10135#false} is VALID [2022-02-21 04:23:14,569 INFO L290 TraceCheckUtils]: 131: Hoare triple {10135#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,569 INFO L290 TraceCheckUtils]: 132: Hoare triple {10135#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,569 INFO L290 TraceCheckUtils]: 133: Hoare triple {10135#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,569 INFO L290 TraceCheckUtils]: 134: Hoare triple {10135#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,569 INFO L290 TraceCheckUtils]: 135: Hoare triple {10135#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,569 INFO L290 TraceCheckUtils]: 136: Hoare triple {10135#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,570 INFO L290 TraceCheckUtils]: 137: Hoare triple {10135#false} assume 1 == ~E_M~0;~E_M~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,570 INFO L290 TraceCheckUtils]: 138: Hoare triple {10135#false} assume !(1 == ~E_1~0); {10135#false} is VALID [2022-02-21 04:23:14,570 INFO L290 TraceCheckUtils]: 139: Hoare triple {10135#false} assume 1 == ~E_2~0;~E_2~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,570 INFO L290 TraceCheckUtils]: 140: Hoare triple {10135#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,570 INFO L290 TraceCheckUtils]: 141: Hoare triple {10135#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,570 INFO L290 TraceCheckUtils]: 142: Hoare triple {10135#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,570 INFO L290 TraceCheckUtils]: 143: Hoare triple {10135#false} assume 1 == ~E_6~0;~E_6~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,570 INFO L290 TraceCheckUtils]: 144: Hoare triple {10135#false} assume 1 == ~E_7~0;~E_7~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,571 INFO L290 TraceCheckUtils]: 145: Hoare triple {10135#false} assume 1 == ~E_8~0;~E_8~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,572 INFO L290 TraceCheckUtils]: 146: Hoare triple {10135#false} assume !(1 == ~E_9~0); {10135#false} is VALID [2022-02-21 04:23:14,572 INFO L290 TraceCheckUtils]: 147: Hoare triple {10135#false} assume 1 == ~E_10~0;~E_10~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,572 INFO L290 TraceCheckUtils]: 148: Hoare triple {10135#false} assume 1 == ~E_11~0;~E_11~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,572 INFO L290 TraceCheckUtils]: 149: Hoare triple {10135#false} assume 1 == ~E_12~0;~E_12~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,572 INFO L290 TraceCheckUtils]: 150: Hoare triple {10135#false} assume 1 == ~E_13~0;~E_13~0 := 2; {10135#false} is VALID [2022-02-21 04:23:14,572 INFO L290 TraceCheckUtils]: 151: Hoare triple {10135#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {10135#false} is VALID [2022-02-21 04:23:14,572 INFO L290 TraceCheckUtils]: 152: Hoare triple {10135#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {10135#false} is VALID [2022-02-21 04:23:14,573 INFO L290 TraceCheckUtils]: 153: Hoare triple {10135#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {10135#false} is VALID [2022-02-21 04:23:14,573 INFO L290 TraceCheckUtils]: 154: Hoare triple {10135#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {10135#false} is VALID [2022-02-21 04:23:14,573 INFO L290 TraceCheckUtils]: 155: Hoare triple {10135#false} assume !(0 == start_simulation_~tmp~3#1); {10135#false} is VALID [2022-02-21 04:23:14,573 INFO L290 TraceCheckUtils]: 156: Hoare triple {10135#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {10135#false} is VALID [2022-02-21 04:23:14,573 INFO L290 TraceCheckUtils]: 157: Hoare triple {10135#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {10135#false} is VALID [2022-02-21 04:23:14,573 INFO L290 TraceCheckUtils]: 158: Hoare triple {10135#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {10135#false} is VALID [2022-02-21 04:23:14,573 INFO L290 TraceCheckUtils]: 159: Hoare triple {10135#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {10135#false} is VALID [2022-02-21 04:23:14,573 INFO L290 TraceCheckUtils]: 160: Hoare triple {10135#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {10135#false} is VALID [2022-02-21 04:23:14,574 INFO L290 TraceCheckUtils]: 161: Hoare triple {10135#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10135#false} is VALID [2022-02-21 04:23:14,574 INFO L290 TraceCheckUtils]: 162: Hoare triple {10135#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {10135#false} is VALID [2022-02-21 04:23:14,574 INFO L290 TraceCheckUtils]: 163: Hoare triple {10135#false} assume !(0 != start_simulation_~tmp___0~1#1); {10135#false} is VALID [2022-02-21 04:23:14,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:14,575 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:14,575 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014553691] [2022-02-21 04:23:14,575 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014553691] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:14,577 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:14,577 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:14,577 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378705694] [2022-02-21 04:23:14,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:14,578 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:14,578 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:14,578 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:14,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:14,579 INFO L87 Difference]: Start difference. First operand 2021 states and 2992 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,056 INFO L93 Difference]: Finished difference Result 2021 states and 2991 transitions. [2022-02-21 04:23:16,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:16,057 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,152 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:16,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2991 transitions. [2022-02-21 04:23:16,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:16,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2991 transitions. [2022-02-21 04:23:16,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:16,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:16,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2991 transitions. [2022-02-21 04:23:16,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:16,348 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2022-02-21 04:23:16,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2991 transitions. [2022-02-21 04:23:16,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:16,367 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:16,371 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2991 transitions. Second operand has 2021 states, 2021 states have (on average 1.479960415635824) internal successors, (2991), 2020 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,373 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2991 transitions. Second operand has 2021 states, 2021 states have (on average 1.479960415635824) internal successors, (2991), 2020 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,375 INFO L87 Difference]: Start difference. First operand 2021 states and 2991 transitions. Second operand has 2021 states, 2021 states have (on average 1.479960415635824) internal successors, (2991), 2020 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,464 INFO L93 Difference]: Finished difference Result 2021 states and 2991 transitions. [2022-02-21 04:23:16,465 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2991 transitions. [2022-02-21 04:23:16,467 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:16,467 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:16,470 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.479960415635824) internal successors, (2991), 2020 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2991 transitions. [2022-02-21 04:23:16,472 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.479960415635824) internal successors, (2991), 2020 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2991 transitions. [2022-02-21 04:23:16,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,559 INFO L93 Difference]: Finished difference Result 2021 states and 2991 transitions. [2022-02-21 04:23:16,559 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2991 transitions. [2022-02-21 04:23:16,562 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:16,562 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:16,562 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:16,562 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:16,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.479960415635824) internal successors, (2991), 2020 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2991 transitions. [2022-02-21 04:23:16,690 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2022-02-21 04:23:16,690 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2022-02-21 04:23:16,690 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:23:16,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2991 transitions. [2022-02-21 04:23:16,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:16,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:16,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:16,699 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:16,699 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:16,700 INFO L791 eck$LassoCheckResult]: Stem: 13034#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 13035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12766#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12767#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14157#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 14158#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12953#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 12954#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12988#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13825#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13826#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13938#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13939#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12772#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12773#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13975#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13297#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13298#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13879#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14145#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 14035#L1286-2 assume !(0 == ~T1_E~0); 12681#L1291-1 assume !(0 == ~T2_E~0); 12682#L1296-1 assume !(0 == ~T3_E~0); 13387#L1301-1 assume !(0 == ~T4_E~0); 13388#L1306-1 assume !(0 == ~T5_E~0); 13888#L1311-1 assume !(0 == ~T6_E~0); 12641#L1316-1 assume !(0 == ~T7_E~0); 12642#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13407#L1326-1 assume !(0 == ~T9_E~0); 12456#L1331-1 assume !(0 == ~T10_E~0); 12162#L1336-1 assume !(0 == ~T11_E~0); 12163#L1341-1 assume !(0 == ~T12_E~0); 12214#L1346-1 assume !(0 == ~T13_E~0); 12215#L1351-1 assume !(0 == ~E_M~0); 12588#L1356-1 assume !(0 == ~E_1~0); 12589#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14108#L1366-1 assume !(0 == ~E_3~0); 12634#L1371-1 assume !(0 == ~E_4~0); 12635#L1376-1 assume !(0 == ~E_5~0); 13448#L1381-1 assume !(0 == ~E_6~0); 13449#L1386-1 assume !(0 == ~E_7~0); 14136#L1391-1 assume !(0 == ~E_8~0); 14149#L1396-1 assume !(0 == ~E_9~0); 13331#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13332#L1406-1 assume !(0 == ~E_11~0); 13634#L1411-1 assume !(0 == ~E_12~0); 13635#L1416-1 assume !(0 == ~E_13~0); 13255#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13093#L635 assume !(1 == ~m_pc~0); 12232#L635-2 is_master_triggered_~__retres1~0#1 := 0; 12233#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12583#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13219#L1598 assume !(0 != activate_threads_~tmp~1#1); 12411#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12412#L654 assume 1 == ~t1_pc~0; 13117#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13118#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14133#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13199#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 13200#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12459#L673 assume 1 == ~t2_pc~0; 12460#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13604#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13605#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14163#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 14170#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13278#L692 assume !(1 == ~t3_pc~0); 13095#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13096#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12955#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12923#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12924#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12484#L711 assume 1 == ~t4_pc~0; 12485#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12968#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13425#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12187#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 12188#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14156#L730 assume !(1 == ~t5_pc~0); 13538#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12366#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12367#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12494#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 12495#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12837#L749 assume 1 == ~t6_pc~0; 12611#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12371#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12803#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12804#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 13026#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12167#L768 assume !(1 == ~t7_pc~0); 12168#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13472#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12404#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12405#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 13491#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12643#L787 assume 1 == ~t8_pc~0; 12644#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13839#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14003#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14004#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 12212#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12213#L806 assume 1 == ~t9_pc~0; 13850#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12247#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12248#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12496#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 12497#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13833#L825 assume !(1 == ~t10_pc~0); 13834#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13439#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13440#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12584#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12585#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13168#L844 assume 1 == ~t11_pc~0; 12858#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12859#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13225#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13226#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 13821#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13822#L863 assume !(1 == ~t12_pc~0); 12347#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12346#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12574#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13913#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 13914#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13292#L882 assume 1 == ~t13_pc~0; 13293#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13577#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 14078#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13881#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 13564#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13565#L1434 assume !(1 == ~M_E~0); 14086#L1434-2 assume !(1 == ~T1_E~0); 14162#L1439-1 assume !(1 == ~T2_E~0); 12477#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12478#L1449-1 assume !(1 == ~T4_E~0); 12920#L1454-1 assume !(1 == ~T5_E~0); 12921#L1459-1 assume !(1 == ~T6_E~0); 13492#L1464-1 assume !(1 == ~T7_E~0); 13493#L1469-1 assume !(1 == ~T8_E~0); 13578#L1474-1 assume !(1 == ~T9_E~0); 13256#L1479-1 assume !(1 == ~T10_E~0); 13257#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13500#L1489-1 assume !(1 == ~T12_E~0); 13134#L1494-1 assume !(1 == ~T13_E~0); 13135#L1499-1 assume !(1 == ~E_M~0); 13316#L1504-1 assume !(1 == ~E_1~0); 13317#L1509-1 assume !(1 == ~E_2~0); 13930#L1514-1 assume !(1 == ~E_3~0); 13615#L1519-1 assume !(1 == ~E_4~0); 13616#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14120#L1529-1 assume !(1 == ~E_6~0); 14121#L1534-1 assume !(1 == ~E_7~0); 12267#L1539-1 assume !(1 == ~E_8~0); 12268#L1544-1 assume !(1 == ~E_9~0); 12698#L1549-1 assume !(1 == ~E_10~0); 14098#L1554-1 assume !(1 == ~E_11~0); 14096#L1559-1 assume !(1 == ~E_12~0); 13958#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 13959#L1569-1 assume { :end_inline_reset_delta_events } true; 14114#L1935-2 [2022-02-21 04:23:16,700 INFO L793 eck$LassoCheckResult]: Loop: 14114#L1935-2 assume !false; 12276#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12277#L1261 assume !false; 13504#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13505#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12407#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12577#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12578#L1074 assume !(0 != eval_~tmp~0#1); 12935#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13533#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13934#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13990#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13709#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13710#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14146#L1301-3 assume !(0 == ~T4_E~0); 14104#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13212#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12511#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12512#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12617#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13353#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13618#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13619#L1341-3 assume !(0 == ~T12_E~0); 12913#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12904#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12848#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12849#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13429#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12202#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12203#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13945#L1381-3 assume !(0 == ~E_6~0); 13794#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13795#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13976#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13977#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12582#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12413#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 12414#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13041#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12291#L635-45 assume 1 == ~m_pc~0; 12292#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13086#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13566#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13820#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12600#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12601#L654-45 assume 1 == ~t1_pc~0; 13421#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13769#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12254#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12255#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12280#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13107#L673-45 assume !(1 == ~t2_pc~0); 13108#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 13432#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13433#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14058#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 13878#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12725#L692-45 assume !(1 == ~t3_pc~0); 12451#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 12452#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13496#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12779#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12780#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13092#L711-45 assume 1 == ~t4_pc~0; 13216#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13217#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13069#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13070#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13473#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12624#L730-45 assume !(1 == ~t5_pc~0); 12464#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 12463#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12872#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12873#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13624#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12435#L749-45 assume !(1 == ~t6_pc~0); 12436#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 13836#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13599#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13600#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13751#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12751#L768-45 assume 1 == ~t7_pc~0; 12752#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12891#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13695#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13696#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13735#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13736#L787-45 assume 1 == ~t8_pc~0; 13904#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12897#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12898#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13314#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13315#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13623#L806-45 assume 1 == ~t9_pc~0; 14099#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12311#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13136#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12964#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12876#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12877#L825-45 assume 1 == ~t10_pc~0; 13488#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13401#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13506#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13507#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13659#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12519#L844-45 assume !(1 == ~t11_pc~0); 12520#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 13042#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13043#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13059#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 13470#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12559#L863-45 assume 1 == ~t12_pc~0; 12560#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12160#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12161#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12676#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12677#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13476#L882-45 assume 1 == ~t13_pc~0; 13830#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12179#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12180#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12788#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 13967#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13583#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13584#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13768#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12473#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12474#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12636#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13573#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13574#L1464-3 assume !(1 == ~T7_E~0); 14020#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13947#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13948#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14022#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13214#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13215#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13875#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13510#L1504-3 assume !(1 == ~E_1~0); 13511#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13956#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13996#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13137#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13138#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14043#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13438#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12892#L1544-3 assume !(1 == ~E_9~0); 12893#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13408#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12524#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12525#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13674#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13675#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12409#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12974#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13645#L1954 assume !(0 == start_simulation_~tmp~3#1); 13647#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13897#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12692#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13733#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13863#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13864#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13954#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14016#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 14114#L1935-2 [2022-02-21 04:23:16,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:16,701 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2022-02-21 04:23:16,701 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:16,701 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900828909] [2022-02-21 04:23:16,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:16,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:16,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:16,731 INFO L290 TraceCheckUtils]: 0: Hoare triple {18224#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {18224#true} is VALID [2022-02-21 04:23:16,732 INFO L290 TraceCheckUtils]: 1: Hoare triple {18224#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {18226#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:16,732 INFO L290 TraceCheckUtils]: 2: Hoare triple {18226#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {18226#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:16,733 INFO L290 TraceCheckUtils]: 3: Hoare triple {18226#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {18226#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:16,733 INFO L290 TraceCheckUtils]: 4: Hoare triple {18226#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {18226#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:16,733 INFO L290 TraceCheckUtils]: 5: Hoare triple {18226#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {18226#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:16,734 INFO L290 TraceCheckUtils]: 6: Hoare triple {18226#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,734 INFO L290 TraceCheckUtils]: 7: Hoare triple {18225#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,734 INFO L290 TraceCheckUtils]: 8: Hoare triple {18225#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,734 INFO L290 TraceCheckUtils]: 9: Hoare triple {18225#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,734 INFO L290 TraceCheckUtils]: 10: Hoare triple {18225#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,734 INFO L290 TraceCheckUtils]: 11: Hoare triple {18225#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,735 INFO L290 TraceCheckUtils]: 12: Hoare triple {18225#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,735 INFO L290 TraceCheckUtils]: 13: Hoare triple {18225#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {18225#false} is VALID [2022-02-21 04:23:16,735 INFO L290 TraceCheckUtils]: 14: Hoare triple {18225#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,735 INFO L290 TraceCheckUtils]: 15: Hoare triple {18225#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,735 INFO L290 TraceCheckUtils]: 16: Hoare triple {18225#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,735 INFO L290 TraceCheckUtils]: 17: Hoare triple {18225#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,735 INFO L290 TraceCheckUtils]: 18: Hoare triple {18225#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {18225#false} is VALID [2022-02-21 04:23:16,736 INFO L290 TraceCheckUtils]: 19: Hoare triple {18225#false} assume 0 == ~M_E~0;~M_E~0 := 1; {18225#false} is VALID [2022-02-21 04:23:16,736 INFO L290 TraceCheckUtils]: 20: Hoare triple {18225#false} assume !(0 == ~T1_E~0); {18225#false} is VALID [2022-02-21 04:23:16,736 INFO L290 TraceCheckUtils]: 21: Hoare triple {18225#false} assume !(0 == ~T2_E~0); {18225#false} is VALID [2022-02-21 04:23:16,736 INFO L290 TraceCheckUtils]: 22: Hoare triple {18225#false} assume !(0 == ~T3_E~0); {18225#false} is VALID [2022-02-21 04:23:16,736 INFO L290 TraceCheckUtils]: 23: Hoare triple {18225#false} assume !(0 == ~T4_E~0); {18225#false} is VALID [2022-02-21 04:23:16,736 INFO L290 TraceCheckUtils]: 24: Hoare triple {18225#false} assume !(0 == ~T5_E~0); {18225#false} is VALID [2022-02-21 04:23:16,736 INFO L290 TraceCheckUtils]: 25: Hoare triple {18225#false} assume !(0 == ~T6_E~0); {18225#false} is VALID [2022-02-21 04:23:16,737 INFO L290 TraceCheckUtils]: 26: Hoare triple {18225#false} assume !(0 == ~T7_E~0); {18225#false} is VALID [2022-02-21 04:23:16,737 INFO L290 TraceCheckUtils]: 27: Hoare triple {18225#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {18225#false} is VALID [2022-02-21 04:23:16,737 INFO L290 TraceCheckUtils]: 28: Hoare triple {18225#false} assume !(0 == ~T9_E~0); {18225#false} is VALID [2022-02-21 04:23:16,737 INFO L290 TraceCheckUtils]: 29: Hoare triple {18225#false} assume !(0 == ~T10_E~0); {18225#false} is VALID [2022-02-21 04:23:16,737 INFO L290 TraceCheckUtils]: 30: Hoare triple {18225#false} assume !(0 == ~T11_E~0); {18225#false} is VALID [2022-02-21 04:23:16,737 INFO L290 TraceCheckUtils]: 31: Hoare triple {18225#false} assume !(0 == ~T12_E~0); {18225#false} is VALID [2022-02-21 04:23:16,738 INFO L290 TraceCheckUtils]: 32: Hoare triple {18225#false} assume !(0 == ~T13_E~0); {18225#false} is VALID [2022-02-21 04:23:16,738 INFO L290 TraceCheckUtils]: 33: Hoare triple {18225#false} assume !(0 == ~E_M~0); {18225#false} is VALID [2022-02-21 04:23:16,738 INFO L290 TraceCheckUtils]: 34: Hoare triple {18225#false} assume !(0 == ~E_1~0); {18225#false} is VALID [2022-02-21 04:23:16,738 INFO L290 TraceCheckUtils]: 35: Hoare triple {18225#false} assume 0 == ~E_2~0;~E_2~0 := 1; {18225#false} is VALID [2022-02-21 04:23:16,738 INFO L290 TraceCheckUtils]: 36: Hoare triple {18225#false} assume !(0 == ~E_3~0); {18225#false} is VALID [2022-02-21 04:23:16,738 INFO L290 TraceCheckUtils]: 37: Hoare triple {18225#false} assume !(0 == ~E_4~0); {18225#false} is VALID [2022-02-21 04:23:16,738 INFO L290 TraceCheckUtils]: 38: Hoare triple {18225#false} assume !(0 == ~E_5~0); {18225#false} is VALID [2022-02-21 04:23:16,739 INFO L290 TraceCheckUtils]: 39: Hoare triple {18225#false} assume !(0 == ~E_6~0); {18225#false} is VALID [2022-02-21 04:23:16,739 INFO L290 TraceCheckUtils]: 40: Hoare triple {18225#false} assume !(0 == ~E_7~0); {18225#false} is VALID [2022-02-21 04:23:16,739 INFO L290 TraceCheckUtils]: 41: Hoare triple {18225#false} assume !(0 == ~E_8~0); {18225#false} is VALID [2022-02-21 04:23:16,739 INFO L290 TraceCheckUtils]: 42: Hoare triple {18225#false} assume !(0 == ~E_9~0); {18225#false} is VALID [2022-02-21 04:23:16,739 INFO L290 TraceCheckUtils]: 43: Hoare triple {18225#false} assume 0 == ~E_10~0;~E_10~0 := 1; {18225#false} is VALID [2022-02-21 04:23:16,739 INFO L290 TraceCheckUtils]: 44: Hoare triple {18225#false} assume !(0 == ~E_11~0); {18225#false} is VALID [2022-02-21 04:23:16,740 INFO L290 TraceCheckUtils]: 45: Hoare triple {18225#false} assume !(0 == ~E_12~0); {18225#false} is VALID [2022-02-21 04:23:16,740 INFO L290 TraceCheckUtils]: 46: Hoare triple {18225#false} assume !(0 == ~E_13~0); {18225#false} is VALID [2022-02-21 04:23:16,740 INFO L290 TraceCheckUtils]: 47: Hoare triple {18225#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18225#false} is VALID [2022-02-21 04:23:16,740 INFO L290 TraceCheckUtils]: 48: Hoare triple {18225#false} assume !(1 == ~m_pc~0); {18225#false} is VALID [2022-02-21 04:23:16,740 INFO L290 TraceCheckUtils]: 49: Hoare triple {18225#false} is_master_triggered_~__retres1~0#1 := 0; {18225#false} is VALID [2022-02-21 04:23:16,740 INFO L290 TraceCheckUtils]: 50: Hoare triple {18225#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18225#false} is VALID [2022-02-21 04:23:16,741 INFO L290 TraceCheckUtils]: 51: Hoare triple {18225#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {18225#false} is VALID [2022-02-21 04:23:16,741 INFO L290 TraceCheckUtils]: 52: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp~1#1); {18225#false} is VALID [2022-02-21 04:23:16,741 INFO L290 TraceCheckUtils]: 53: Hoare triple {18225#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18225#false} is VALID [2022-02-21 04:23:16,741 INFO L290 TraceCheckUtils]: 54: Hoare triple {18225#false} assume 1 == ~t1_pc~0; {18225#false} is VALID [2022-02-21 04:23:16,741 INFO L290 TraceCheckUtils]: 55: Hoare triple {18225#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {18225#false} is VALID [2022-02-21 04:23:16,741 INFO L290 TraceCheckUtils]: 56: Hoare triple {18225#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18225#false} is VALID [2022-02-21 04:23:16,741 INFO L290 TraceCheckUtils]: 57: Hoare triple {18225#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {18225#false} is VALID [2022-02-21 04:23:16,742 INFO L290 TraceCheckUtils]: 58: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___0~0#1); {18225#false} is VALID [2022-02-21 04:23:16,742 INFO L290 TraceCheckUtils]: 59: Hoare triple {18225#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18225#false} is VALID [2022-02-21 04:23:16,742 INFO L290 TraceCheckUtils]: 60: Hoare triple {18225#false} assume 1 == ~t2_pc~0; {18225#false} is VALID [2022-02-21 04:23:16,742 INFO L290 TraceCheckUtils]: 61: Hoare triple {18225#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {18225#false} is VALID [2022-02-21 04:23:16,742 INFO L290 TraceCheckUtils]: 62: Hoare triple {18225#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18225#false} is VALID [2022-02-21 04:23:16,742 INFO L290 TraceCheckUtils]: 63: Hoare triple {18225#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {18225#false} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 64: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___1~0#1); {18225#false} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 65: Hoare triple {18225#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18225#false} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 66: Hoare triple {18225#false} assume !(1 == ~t3_pc~0); {18225#false} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 67: Hoare triple {18225#false} is_transmit3_triggered_~__retres1~3#1 := 0; {18225#false} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 68: Hoare triple {18225#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18225#false} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 69: Hoare triple {18225#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {18225#false} is VALID [2022-02-21 04:23:16,743 INFO L290 TraceCheckUtils]: 70: Hoare triple {18225#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {18225#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 71: Hoare triple {18225#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {18225#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 72: Hoare triple {18225#false} assume 1 == ~t4_pc~0; {18225#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 73: Hoare triple {18225#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {18225#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 74: Hoare triple {18225#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {18225#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 75: Hoare triple {18225#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {18225#false} is VALID [2022-02-21 04:23:16,744 INFO L290 TraceCheckUtils]: 76: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___3~0#1); {18225#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 77: Hoare triple {18225#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {18225#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 78: Hoare triple {18225#false} assume !(1 == ~t5_pc~0); {18225#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 79: Hoare triple {18225#false} is_transmit5_triggered_~__retres1~5#1 := 0; {18225#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 80: Hoare triple {18225#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {18225#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 81: Hoare triple {18225#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {18225#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 82: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___4~0#1); {18225#false} is VALID [2022-02-21 04:23:16,745 INFO L290 TraceCheckUtils]: 83: Hoare triple {18225#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {18225#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 84: Hoare triple {18225#false} assume 1 == ~t6_pc~0; {18225#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 85: Hoare triple {18225#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {18225#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 86: Hoare triple {18225#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {18225#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 87: Hoare triple {18225#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {18225#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 88: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___5~0#1); {18225#false} is VALID [2022-02-21 04:23:16,746 INFO L290 TraceCheckUtils]: 89: Hoare triple {18225#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {18225#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 90: Hoare triple {18225#false} assume !(1 == ~t7_pc~0); {18225#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 91: Hoare triple {18225#false} is_transmit7_triggered_~__retres1~7#1 := 0; {18225#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 92: Hoare triple {18225#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {18225#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 93: Hoare triple {18225#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {18225#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 94: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___6~0#1); {18225#false} is VALID [2022-02-21 04:23:16,747 INFO L290 TraceCheckUtils]: 95: Hoare triple {18225#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {18225#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 96: Hoare triple {18225#false} assume 1 == ~t8_pc~0; {18225#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 97: Hoare triple {18225#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {18225#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 98: Hoare triple {18225#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {18225#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 99: Hoare triple {18225#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {18225#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 100: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___7~0#1); {18225#false} is VALID [2022-02-21 04:23:16,748 INFO L290 TraceCheckUtils]: 101: Hoare triple {18225#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {18225#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 102: Hoare triple {18225#false} assume 1 == ~t9_pc~0; {18225#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 103: Hoare triple {18225#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {18225#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 104: Hoare triple {18225#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {18225#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 105: Hoare triple {18225#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {18225#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 106: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___8~0#1); {18225#false} is VALID [2022-02-21 04:23:16,749 INFO L290 TraceCheckUtils]: 107: Hoare triple {18225#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {18225#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 108: Hoare triple {18225#false} assume !(1 == ~t10_pc~0); {18225#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 109: Hoare triple {18225#false} is_transmit10_triggered_~__retres1~10#1 := 0; {18225#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 110: Hoare triple {18225#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {18225#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 111: Hoare triple {18225#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {18225#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 112: Hoare triple {18225#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {18225#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 113: Hoare triple {18225#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {18225#false} is VALID [2022-02-21 04:23:16,750 INFO L290 TraceCheckUtils]: 114: Hoare triple {18225#false} assume 1 == ~t11_pc~0; {18225#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 115: Hoare triple {18225#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {18225#false} is VALID [2022-02-21 04:23:16,751 INFO L290 TraceCheckUtils]: 116: Hoare triple {18225#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {18225#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 117: Hoare triple {18225#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {18225#false} is VALID [2022-02-21 04:23:16,753 INFO L290 TraceCheckUtils]: 118: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___10~0#1); {18225#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 119: Hoare triple {18225#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {18225#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 120: Hoare triple {18225#false} assume !(1 == ~t12_pc~0); {18225#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 121: Hoare triple {18225#false} is_transmit12_triggered_~__retres1~12#1 := 0; {18225#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 122: Hoare triple {18225#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {18225#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 123: Hoare triple {18225#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {18225#false} is VALID [2022-02-21 04:23:16,754 INFO L290 TraceCheckUtils]: 124: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___11~0#1); {18225#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 125: Hoare triple {18225#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {18225#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 126: Hoare triple {18225#false} assume 1 == ~t13_pc~0; {18225#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 127: Hoare triple {18225#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {18225#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 128: Hoare triple {18225#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {18225#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 129: Hoare triple {18225#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {18225#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 130: Hoare triple {18225#false} assume !(0 != activate_threads_~tmp___12~0#1); {18225#false} is VALID [2022-02-21 04:23:16,755 INFO L290 TraceCheckUtils]: 131: Hoare triple {18225#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18225#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 132: Hoare triple {18225#false} assume !(1 == ~M_E~0); {18225#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 133: Hoare triple {18225#false} assume !(1 == ~T1_E~0); {18225#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 134: Hoare triple {18225#false} assume !(1 == ~T2_E~0); {18225#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 135: Hoare triple {18225#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 136: Hoare triple {18225#false} assume !(1 == ~T4_E~0); {18225#false} is VALID [2022-02-21 04:23:16,756 INFO L290 TraceCheckUtils]: 137: Hoare triple {18225#false} assume !(1 == ~T5_E~0); {18225#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 138: Hoare triple {18225#false} assume !(1 == ~T6_E~0); {18225#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 139: Hoare triple {18225#false} assume !(1 == ~T7_E~0); {18225#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 140: Hoare triple {18225#false} assume !(1 == ~T8_E~0); {18225#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 141: Hoare triple {18225#false} assume !(1 == ~T9_E~0); {18225#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 142: Hoare triple {18225#false} assume !(1 == ~T10_E~0); {18225#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 143: Hoare triple {18225#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,757 INFO L290 TraceCheckUtils]: 144: Hoare triple {18225#false} assume !(1 == ~T12_E~0); {18225#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 145: Hoare triple {18225#false} assume !(1 == ~T13_E~0); {18225#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 146: Hoare triple {18225#false} assume !(1 == ~E_M~0); {18225#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 147: Hoare triple {18225#false} assume !(1 == ~E_1~0); {18225#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 148: Hoare triple {18225#false} assume !(1 == ~E_2~0); {18225#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 149: Hoare triple {18225#false} assume !(1 == ~E_3~0); {18225#false} is VALID [2022-02-21 04:23:16,758 INFO L290 TraceCheckUtils]: 150: Hoare triple {18225#false} assume !(1 == ~E_4~0); {18225#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 151: Hoare triple {18225#false} assume 1 == ~E_5~0;~E_5~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 152: Hoare triple {18225#false} assume !(1 == ~E_6~0); {18225#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 153: Hoare triple {18225#false} assume !(1 == ~E_7~0); {18225#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 154: Hoare triple {18225#false} assume !(1 == ~E_8~0); {18225#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 155: Hoare triple {18225#false} assume !(1 == ~E_9~0); {18225#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 156: Hoare triple {18225#false} assume !(1 == ~E_10~0); {18225#false} is VALID [2022-02-21 04:23:16,759 INFO L290 TraceCheckUtils]: 157: Hoare triple {18225#false} assume !(1 == ~E_11~0); {18225#false} is VALID [2022-02-21 04:23:16,760 INFO L290 TraceCheckUtils]: 158: Hoare triple {18225#false} assume !(1 == ~E_12~0); {18225#false} is VALID [2022-02-21 04:23:16,760 INFO L290 TraceCheckUtils]: 159: Hoare triple {18225#false} assume 1 == ~E_13~0;~E_13~0 := 2; {18225#false} is VALID [2022-02-21 04:23:16,760 INFO L290 TraceCheckUtils]: 160: Hoare triple {18225#false} assume { :end_inline_reset_delta_events } true; {18225#false} is VALID [2022-02-21 04:23:16,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:16,761 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:16,761 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [900828909] [2022-02-21 04:23:16,761 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [900828909] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:16,761 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:16,761 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:16,761 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [617053028] [2022-02-21 04:23:16,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:16,762 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:16,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:16,763 INFO L85 PathProgramCache]: Analyzing trace with hash -1762520861, now seen corresponding path program 1 times [2022-02-21 04:23:16,763 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:16,763 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [764819175] [2022-02-21 04:23:16,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:16,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:16,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:16,823 INFO L290 TraceCheckUtils]: 0: Hoare triple {18227#true} assume !false; {18227#true} is VALID [2022-02-21 04:23:16,823 INFO L290 TraceCheckUtils]: 1: Hoare triple {18227#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {18227#true} is VALID [2022-02-21 04:23:16,823 INFO L290 TraceCheckUtils]: 2: Hoare triple {18227#true} assume !false; {18227#true} is VALID [2022-02-21 04:23:16,823 INFO L290 TraceCheckUtils]: 3: Hoare triple {18227#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {18227#true} is VALID [2022-02-21 04:23:16,823 INFO L290 TraceCheckUtils]: 4: Hoare triple {18227#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {18227#true} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 5: Hoare triple {18227#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {18227#true} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 6: Hoare triple {18227#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {18227#true} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 7: Hoare triple {18227#true} assume !(0 != eval_~tmp~0#1); {18227#true} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 8: Hoare triple {18227#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {18227#true} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 9: Hoare triple {18227#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {18227#true} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 10: Hoare triple {18227#true} assume 0 == ~M_E~0;~M_E~0 := 1; {18227#true} is VALID [2022-02-21 04:23:16,824 INFO L290 TraceCheckUtils]: 11: Hoare triple {18227#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {18227#true} is VALID [2022-02-21 04:23:16,825 INFO L290 TraceCheckUtils]: 12: Hoare triple {18227#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {18227#true} is VALID [2022-02-21 04:23:16,825 INFO L290 TraceCheckUtils]: 13: Hoare triple {18227#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {18227#true} is VALID [2022-02-21 04:23:16,825 INFO L290 TraceCheckUtils]: 14: Hoare triple {18227#true} assume !(0 == ~T4_E~0); {18227#true} is VALID [2022-02-21 04:23:16,825 INFO L290 TraceCheckUtils]: 15: Hoare triple {18227#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {18227#true} is VALID [2022-02-21 04:23:16,825 INFO L290 TraceCheckUtils]: 16: Hoare triple {18227#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {18227#true} is VALID [2022-02-21 04:23:16,826 INFO L290 TraceCheckUtils]: 17: Hoare triple {18227#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,826 INFO L290 TraceCheckUtils]: 18: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,826 INFO L290 TraceCheckUtils]: 19: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,827 INFO L290 TraceCheckUtils]: 20: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,827 INFO L290 TraceCheckUtils]: 21: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,827 INFO L290 TraceCheckUtils]: 22: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,828 INFO L290 TraceCheckUtils]: 23: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,828 INFO L290 TraceCheckUtils]: 24: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,828 INFO L290 TraceCheckUtils]: 25: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,829 INFO L290 TraceCheckUtils]: 26: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,829 INFO L290 TraceCheckUtils]: 27: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,829 INFO L290 TraceCheckUtils]: 28: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,830 INFO L290 TraceCheckUtils]: 29: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,830 INFO L290 TraceCheckUtils]: 30: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,830 INFO L290 TraceCheckUtils]: 31: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,831 INFO L290 TraceCheckUtils]: 32: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,831 INFO L290 TraceCheckUtils]: 33: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,831 INFO L290 TraceCheckUtils]: 34: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,832 INFO L290 TraceCheckUtils]: 35: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,832 INFO L290 TraceCheckUtils]: 36: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,833 INFO L290 TraceCheckUtils]: 37: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,833 INFO L290 TraceCheckUtils]: 38: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,833 INFO L290 TraceCheckUtils]: 39: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,834 INFO L290 TraceCheckUtils]: 40: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,834 INFO L290 TraceCheckUtils]: 41: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,834 INFO L290 TraceCheckUtils]: 42: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,835 INFO L290 TraceCheckUtils]: 43: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,835 INFO L290 TraceCheckUtils]: 44: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,835 INFO L290 TraceCheckUtils]: 45: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,836 INFO L290 TraceCheckUtils]: 46: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,836 INFO L290 TraceCheckUtils]: 47: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,836 INFO L290 TraceCheckUtils]: 48: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,837 INFO L290 TraceCheckUtils]: 49: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,837 INFO L290 TraceCheckUtils]: 50: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,837 INFO L290 TraceCheckUtils]: 51: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,838 INFO L290 TraceCheckUtils]: 52: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,838 INFO L290 TraceCheckUtils]: 53: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,838 INFO L290 TraceCheckUtils]: 54: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,839 INFO L290 TraceCheckUtils]: 55: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,839 INFO L290 TraceCheckUtils]: 56: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,839 INFO L290 TraceCheckUtils]: 57: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 58: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 59: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 60: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,840 INFO L290 TraceCheckUtils]: 61: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 62: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 63: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,841 INFO L290 TraceCheckUtils]: 64: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 65: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 66: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,842 INFO L290 TraceCheckUtils]: 67: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 68: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 69: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t5_pc~0); {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 70: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,843 INFO L290 TraceCheckUtils]: 71: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,844 INFO L290 TraceCheckUtils]: 72: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,844 INFO L290 TraceCheckUtils]: 73: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,844 INFO L290 TraceCheckUtils]: 74: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,845 INFO L290 TraceCheckUtils]: 75: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,845 INFO L290 TraceCheckUtils]: 76: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,845 INFO L290 TraceCheckUtils]: 77: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,845 INFO L290 TraceCheckUtils]: 78: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,846 INFO L290 TraceCheckUtils]: 79: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,846 INFO L290 TraceCheckUtils]: 80: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,846 INFO L290 TraceCheckUtils]: 81: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,846 INFO L290 TraceCheckUtils]: 82: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,847 INFO L290 TraceCheckUtils]: 83: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,847 INFO L290 TraceCheckUtils]: 84: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,847 INFO L290 TraceCheckUtils]: 85: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,848 INFO L290 TraceCheckUtils]: 86: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,848 INFO L290 TraceCheckUtils]: 87: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t8_pc~0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,848 INFO L290 TraceCheckUtils]: 88: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,848 INFO L290 TraceCheckUtils]: 89: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,849 INFO L290 TraceCheckUtils]: 90: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,849 INFO L290 TraceCheckUtils]: 91: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,850 INFO L290 TraceCheckUtils]: 92: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,850 INFO L290 TraceCheckUtils]: 93: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,850 INFO L290 TraceCheckUtils]: 94: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,851 INFO L290 TraceCheckUtils]: 95: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,851 INFO L290 TraceCheckUtils]: 96: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,851 INFO L290 TraceCheckUtils]: 97: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,852 INFO L290 TraceCheckUtils]: 98: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,852 INFO L290 TraceCheckUtils]: 99: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t10_pc~0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,852 INFO L290 TraceCheckUtils]: 100: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,852 INFO L290 TraceCheckUtils]: 101: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,853 INFO L290 TraceCheckUtils]: 102: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,853 INFO L290 TraceCheckUtils]: 103: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,853 INFO L290 TraceCheckUtils]: 104: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,853 INFO L290 TraceCheckUtils]: 105: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,854 INFO L290 TraceCheckUtils]: 106: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,854 INFO L290 TraceCheckUtils]: 107: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,854 INFO L290 TraceCheckUtils]: 108: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,855 INFO L290 TraceCheckUtils]: 109: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,855 INFO L290 TraceCheckUtils]: 110: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,855 INFO L290 TraceCheckUtils]: 111: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,855 INFO L290 TraceCheckUtils]: 112: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,856 INFO L290 TraceCheckUtils]: 113: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,856 INFO L290 TraceCheckUtils]: 114: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,856 INFO L290 TraceCheckUtils]: 115: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,857 INFO L290 TraceCheckUtils]: 116: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,857 INFO L290 TraceCheckUtils]: 117: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t13_pc~0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,857 INFO L290 TraceCheckUtils]: 118: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,857 INFO L290 TraceCheckUtils]: 119: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,858 INFO L290 TraceCheckUtils]: 120: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,858 INFO L290 TraceCheckUtils]: 121: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,858 INFO L290 TraceCheckUtils]: 122: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,859 INFO L290 TraceCheckUtils]: 123: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,859 INFO L290 TraceCheckUtils]: 124: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,859 INFO L290 TraceCheckUtils]: 125: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,859 INFO L290 TraceCheckUtils]: 126: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,860 INFO L290 TraceCheckUtils]: 127: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,860 INFO L290 TraceCheckUtils]: 128: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,860 INFO L290 TraceCheckUtils]: 129: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {18229#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:16,861 INFO L290 TraceCheckUtils]: 130: Hoare triple {18229#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {18228#false} is VALID [2022-02-21 04:23:16,861 INFO L290 TraceCheckUtils]: 131: Hoare triple {18228#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,861 INFO L290 TraceCheckUtils]: 132: Hoare triple {18228#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,861 INFO L290 TraceCheckUtils]: 133: Hoare triple {18228#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,861 INFO L290 TraceCheckUtils]: 134: Hoare triple {18228#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,861 INFO L290 TraceCheckUtils]: 135: Hoare triple {18228#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,861 INFO L290 TraceCheckUtils]: 136: Hoare triple {18228#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,861 INFO L290 TraceCheckUtils]: 137: Hoare triple {18228#false} assume 1 == ~E_M~0;~E_M~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,862 INFO L290 TraceCheckUtils]: 138: Hoare triple {18228#false} assume !(1 == ~E_1~0); {18228#false} is VALID [2022-02-21 04:23:16,862 INFO L290 TraceCheckUtils]: 139: Hoare triple {18228#false} assume 1 == ~E_2~0;~E_2~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,862 INFO L290 TraceCheckUtils]: 140: Hoare triple {18228#false} assume 1 == ~E_3~0;~E_3~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,862 INFO L290 TraceCheckUtils]: 141: Hoare triple {18228#false} assume 1 == ~E_4~0;~E_4~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,862 INFO L290 TraceCheckUtils]: 142: Hoare triple {18228#false} assume 1 == ~E_5~0;~E_5~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,862 INFO L290 TraceCheckUtils]: 143: Hoare triple {18228#false} assume 1 == ~E_6~0;~E_6~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,862 INFO L290 TraceCheckUtils]: 144: Hoare triple {18228#false} assume 1 == ~E_7~0;~E_7~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,863 INFO L290 TraceCheckUtils]: 145: Hoare triple {18228#false} assume 1 == ~E_8~0;~E_8~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,863 INFO L290 TraceCheckUtils]: 146: Hoare triple {18228#false} assume !(1 == ~E_9~0); {18228#false} is VALID [2022-02-21 04:23:16,863 INFO L290 TraceCheckUtils]: 147: Hoare triple {18228#false} assume 1 == ~E_10~0;~E_10~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,863 INFO L290 TraceCheckUtils]: 148: Hoare triple {18228#false} assume 1 == ~E_11~0;~E_11~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,863 INFO L290 TraceCheckUtils]: 149: Hoare triple {18228#false} assume 1 == ~E_12~0;~E_12~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,863 INFO L290 TraceCheckUtils]: 150: Hoare triple {18228#false} assume 1 == ~E_13~0;~E_13~0 := 2; {18228#false} is VALID [2022-02-21 04:23:16,863 INFO L290 TraceCheckUtils]: 151: Hoare triple {18228#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {18228#false} is VALID [2022-02-21 04:23:16,863 INFO L290 TraceCheckUtils]: 152: Hoare triple {18228#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {18228#false} is VALID [2022-02-21 04:23:16,864 INFO L290 TraceCheckUtils]: 153: Hoare triple {18228#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {18228#false} is VALID [2022-02-21 04:23:16,864 INFO L290 TraceCheckUtils]: 154: Hoare triple {18228#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {18228#false} is VALID [2022-02-21 04:23:16,864 INFO L290 TraceCheckUtils]: 155: Hoare triple {18228#false} assume !(0 == start_simulation_~tmp~3#1); {18228#false} is VALID [2022-02-21 04:23:16,864 INFO L290 TraceCheckUtils]: 156: Hoare triple {18228#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {18228#false} is VALID [2022-02-21 04:23:16,864 INFO L290 TraceCheckUtils]: 157: Hoare triple {18228#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {18228#false} is VALID [2022-02-21 04:23:16,864 INFO L290 TraceCheckUtils]: 158: Hoare triple {18228#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {18228#false} is VALID [2022-02-21 04:23:16,864 INFO L290 TraceCheckUtils]: 159: Hoare triple {18228#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {18228#false} is VALID [2022-02-21 04:23:16,864 INFO L290 TraceCheckUtils]: 160: Hoare triple {18228#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {18228#false} is VALID [2022-02-21 04:23:16,865 INFO L290 TraceCheckUtils]: 161: Hoare triple {18228#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {18228#false} is VALID [2022-02-21 04:23:16,865 INFO L290 TraceCheckUtils]: 162: Hoare triple {18228#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {18228#false} is VALID [2022-02-21 04:23:16,865 INFO L290 TraceCheckUtils]: 163: Hoare triple {18228#false} assume !(0 != start_simulation_~tmp___0~1#1); {18228#false} is VALID [2022-02-21 04:23:16,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:16,866 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:16,866 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [764819175] [2022-02-21 04:23:16,866 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [764819175] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:16,867 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:16,867 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:16,867 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [518468072] [2022-02-21 04:23:16,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:16,867 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:16,868 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:16,868 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:16,868 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:16,869 INFO L87 Difference]: Start difference. First operand 2021 states and 2991 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:18,296 INFO L93 Difference]: Finished difference Result 2021 states and 2990 transitions. [2022-02-21 04:23:18,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:18,296 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,395 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:18,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2990 transitions. [2022-02-21 04:23:18,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:18,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2990 transitions. [2022-02-21 04:23:18,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:18,583 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:18,583 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2990 transitions. [2022-02-21 04:23:18,585 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:18,585 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2022-02-21 04:23:18,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2990 transitions. [2022-02-21 04:23:18,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:18,601 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:18,603 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2990 transitions. Second operand has 2021 states, 2021 states have (on average 1.479465611083622) internal successors, (2990), 2020 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,605 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2990 transitions. Second operand has 2021 states, 2021 states have (on average 1.479465611083622) internal successors, (2990), 2020 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,606 INFO L87 Difference]: Start difference. First operand 2021 states and 2990 transitions. Second operand has 2021 states, 2021 states have (on average 1.479465611083622) internal successors, (2990), 2020 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:18,689 INFO L93 Difference]: Finished difference Result 2021 states and 2990 transitions. [2022-02-21 04:23:18,689 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2990 transitions. [2022-02-21 04:23:18,691 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:18,691 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:18,694 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.479465611083622) internal successors, (2990), 2020 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2990 transitions. [2022-02-21 04:23:18,695 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.479465611083622) internal successors, (2990), 2020 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2990 transitions. [2022-02-21 04:23:18,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:18,780 INFO L93 Difference]: Finished difference Result 2021 states and 2990 transitions. [2022-02-21 04:23:18,780 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2990 transitions. [2022-02-21 04:23:18,782 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:18,782 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:18,782 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:18,782 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:18,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.479465611083622) internal successors, (2990), 2020 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2990 transitions. [2022-02-21 04:23:18,868 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2022-02-21 04:23:18,868 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2022-02-21 04:23:18,869 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:23:18,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2990 transitions. [2022-02-21 04:23:18,873 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:18,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:18,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:18,875 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:18,875 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:18,875 INFO L791 eck$LassoCheckResult]: Stem: 21127#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 21128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20859#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20860#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22250#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 22251#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21046#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21047#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 21081#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 21918#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21919#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22031#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22032#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20865#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20866#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22068#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21390#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21391#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21972#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22238#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 22128#L1286-2 assume !(0 == ~T1_E~0); 20774#L1291-1 assume !(0 == ~T2_E~0); 20775#L1296-1 assume !(0 == ~T3_E~0); 21480#L1301-1 assume !(0 == ~T4_E~0); 21481#L1306-1 assume !(0 == ~T5_E~0); 21981#L1311-1 assume !(0 == ~T6_E~0); 20734#L1316-1 assume !(0 == ~T7_E~0); 20735#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21500#L1326-1 assume !(0 == ~T9_E~0); 20549#L1331-1 assume !(0 == ~T10_E~0); 20255#L1336-1 assume !(0 == ~T11_E~0); 20256#L1341-1 assume !(0 == ~T12_E~0); 20307#L1346-1 assume !(0 == ~T13_E~0); 20308#L1351-1 assume !(0 == ~E_M~0); 20681#L1356-1 assume !(0 == ~E_1~0); 20682#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22201#L1366-1 assume !(0 == ~E_3~0); 20727#L1371-1 assume !(0 == ~E_4~0); 20728#L1376-1 assume !(0 == ~E_5~0); 21541#L1381-1 assume !(0 == ~E_6~0); 21542#L1386-1 assume !(0 == ~E_7~0); 22229#L1391-1 assume !(0 == ~E_8~0); 22242#L1396-1 assume !(0 == ~E_9~0); 21424#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21425#L1406-1 assume !(0 == ~E_11~0); 21727#L1411-1 assume !(0 == ~E_12~0); 21728#L1416-1 assume !(0 == ~E_13~0); 21348#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21186#L635 assume !(1 == ~m_pc~0); 20325#L635-2 is_master_triggered_~__retres1~0#1 := 0; 20326#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20676#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21312#L1598 assume !(0 != activate_threads_~tmp~1#1); 20504#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20505#L654 assume 1 == ~t1_pc~0; 21210#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21211#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22226#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21292#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 21293#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20552#L673 assume 1 == ~t2_pc~0; 20553#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21697#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21698#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22256#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 22263#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21371#L692 assume !(1 == ~t3_pc~0); 21188#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21189#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21048#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21016#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21017#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20577#L711 assume 1 == ~t4_pc~0; 20578#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21061#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21518#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20280#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 20281#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22249#L730 assume !(1 == ~t5_pc~0); 21631#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20459#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20460#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20587#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 20588#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20930#L749 assume 1 == ~t6_pc~0; 20704#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20464#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20896#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20897#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 21119#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20260#L768 assume !(1 == ~t7_pc~0); 20261#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21565#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20497#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20498#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 21584#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20736#L787 assume 1 == ~t8_pc~0; 20737#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21932#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22096#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22097#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 20305#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20306#L806 assume 1 == ~t9_pc~0; 21943#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20340#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20341#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20589#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 20590#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21926#L825 assume !(1 == ~t10_pc~0); 21927#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21532#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21533#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20677#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20678#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21261#L844 assume 1 == ~t11_pc~0; 20951#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20952#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21318#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21319#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 21914#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21915#L863 assume !(1 == ~t12_pc~0); 20440#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 20439#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20667#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22006#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 22007#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21385#L882 assume 1 == ~t13_pc~0; 21386#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21670#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 22171#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21974#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 21657#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21658#L1434 assume !(1 == ~M_E~0); 22179#L1434-2 assume !(1 == ~T1_E~0); 22255#L1439-1 assume !(1 == ~T2_E~0); 20570#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20571#L1449-1 assume !(1 == ~T4_E~0); 21013#L1454-1 assume !(1 == ~T5_E~0); 21014#L1459-1 assume !(1 == ~T6_E~0); 21585#L1464-1 assume !(1 == ~T7_E~0); 21586#L1469-1 assume !(1 == ~T8_E~0); 21671#L1474-1 assume !(1 == ~T9_E~0); 21349#L1479-1 assume !(1 == ~T10_E~0); 21350#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21593#L1489-1 assume !(1 == ~T12_E~0); 21227#L1494-1 assume !(1 == ~T13_E~0); 21228#L1499-1 assume !(1 == ~E_M~0); 21409#L1504-1 assume !(1 == ~E_1~0); 21410#L1509-1 assume !(1 == ~E_2~0); 22023#L1514-1 assume !(1 == ~E_3~0); 21708#L1519-1 assume !(1 == ~E_4~0); 21709#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22213#L1529-1 assume !(1 == ~E_6~0); 22214#L1534-1 assume !(1 == ~E_7~0); 20360#L1539-1 assume !(1 == ~E_8~0); 20361#L1544-1 assume !(1 == ~E_9~0); 20791#L1549-1 assume !(1 == ~E_10~0); 22191#L1554-1 assume !(1 == ~E_11~0); 22189#L1559-1 assume !(1 == ~E_12~0); 22051#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22052#L1569-1 assume { :end_inline_reset_delta_events } true; 22207#L1935-2 [2022-02-21 04:23:18,876 INFO L793 eck$LassoCheckResult]: Loop: 22207#L1935-2 assume !false; 20369#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20370#L1261 assume !false; 21597#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21598#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20500#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20670#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 20671#L1074 assume !(0 != eval_~tmp~0#1); 21028#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21626#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22027#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22083#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21802#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21803#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22239#L1301-3 assume !(0 == ~T4_E~0); 22197#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21305#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20604#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20605#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20710#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21446#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21711#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21712#L1341-3 assume !(0 == ~T12_E~0); 21006#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 20997#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20941#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20942#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21522#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20295#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20296#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22038#L1381-3 assume !(0 == ~E_6~0); 21887#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21888#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22069#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22070#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20675#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20506#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 20507#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21134#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20384#L635-45 assume 1 == ~m_pc~0; 20385#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21179#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21659#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21913#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20693#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20694#L654-45 assume 1 == ~t1_pc~0; 21514#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21862#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20347#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20348#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20373#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21200#L673-45 assume !(1 == ~t2_pc~0); 21201#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21525#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21526#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22151#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 21971#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20818#L692-45 assume !(1 == ~t3_pc~0); 20544#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 20545#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21589#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20872#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20873#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21185#L711-45 assume 1 == ~t4_pc~0; 21309#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21310#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21162#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21163#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21566#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20717#L730-45 assume 1 == ~t5_pc~0; 20555#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20556#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20965#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20966#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21717#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20528#L749-45 assume !(1 == ~t6_pc~0); 20529#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 21929#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21692#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21693#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21844#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20844#L768-45 assume 1 == ~t7_pc~0; 20845#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20984#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21788#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21789#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21828#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21829#L787-45 assume 1 == ~t8_pc~0; 21997#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20990#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20991#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21407#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21408#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21716#L806-45 assume 1 == ~t9_pc~0; 22192#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20404#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21229#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21057#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20969#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20970#L825-45 assume !(1 == ~t10_pc~0); 21493#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 21494#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21599#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21600#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21752#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20612#L844-45 assume !(1 == ~t11_pc~0); 20613#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 21135#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21136#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21152#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 21563#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20652#L863-45 assume 1 == ~t12_pc~0; 20653#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20253#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20254#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20769#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20770#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21569#L882-45 assume 1 == ~t13_pc~0; 21923#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20272#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20273#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 20881#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22060#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21676#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21677#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21861#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20566#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20567#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20729#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21666#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21667#L1464-3 assume !(1 == ~T7_E~0); 22113#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22040#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22041#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22115#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21307#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21308#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21968#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21603#L1504-3 assume !(1 == ~E_1~0); 21604#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22049#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22089#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21230#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21231#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22136#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21531#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20985#L1544-3 assume !(1 == ~E_9~0); 20986#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21501#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20617#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20618#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21767#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21768#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20502#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21067#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 21738#L1954 assume !(0 == start_simulation_~tmp~3#1); 21740#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21990#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20785#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21826#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21956#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21957#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22047#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22109#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 22207#L1935-2 [2022-02-21 04:23:18,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:18,876 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2022-02-21 04:23:18,877 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:18,877 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686625826] [2022-02-21 04:23:18,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:18,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:18,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:18,907 INFO L290 TraceCheckUtils]: 0: Hoare triple {26317#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {26317#true} is VALID [2022-02-21 04:23:18,907 INFO L290 TraceCheckUtils]: 1: Hoare triple {26317#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {26319#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:18,908 INFO L290 TraceCheckUtils]: 2: Hoare triple {26319#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {26319#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:18,908 INFO L290 TraceCheckUtils]: 3: Hoare triple {26319#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {26319#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:18,908 INFO L290 TraceCheckUtils]: 4: Hoare triple {26319#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {26319#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:18,909 INFO L290 TraceCheckUtils]: 5: Hoare triple {26319#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {26319#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:18,909 INFO L290 TraceCheckUtils]: 6: Hoare triple {26319#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {26319#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:18,909 INFO L290 TraceCheckUtils]: 7: Hoare triple {26319#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,909 INFO L290 TraceCheckUtils]: 8: Hoare triple {26318#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,909 INFO L290 TraceCheckUtils]: 9: Hoare triple {26318#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,909 INFO L290 TraceCheckUtils]: 10: Hoare triple {26318#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,910 INFO L290 TraceCheckUtils]: 11: Hoare triple {26318#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,910 INFO L290 TraceCheckUtils]: 12: Hoare triple {26318#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,910 INFO L290 TraceCheckUtils]: 13: Hoare triple {26318#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {26318#false} is VALID [2022-02-21 04:23:18,910 INFO L290 TraceCheckUtils]: 14: Hoare triple {26318#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,910 INFO L290 TraceCheckUtils]: 15: Hoare triple {26318#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,910 INFO L290 TraceCheckUtils]: 16: Hoare triple {26318#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,910 INFO L290 TraceCheckUtils]: 17: Hoare triple {26318#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,911 INFO L290 TraceCheckUtils]: 18: Hoare triple {26318#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {26318#false} is VALID [2022-02-21 04:23:18,911 INFO L290 TraceCheckUtils]: 19: Hoare triple {26318#false} assume 0 == ~M_E~0;~M_E~0 := 1; {26318#false} is VALID [2022-02-21 04:23:18,911 INFO L290 TraceCheckUtils]: 20: Hoare triple {26318#false} assume !(0 == ~T1_E~0); {26318#false} is VALID [2022-02-21 04:23:18,911 INFO L290 TraceCheckUtils]: 21: Hoare triple {26318#false} assume !(0 == ~T2_E~0); {26318#false} is VALID [2022-02-21 04:23:18,911 INFO L290 TraceCheckUtils]: 22: Hoare triple {26318#false} assume !(0 == ~T3_E~0); {26318#false} is VALID [2022-02-21 04:23:18,911 INFO L290 TraceCheckUtils]: 23: Hoare triple {26318#false} assume !(0 == ~T4_E~0); {26318#false} is VALID [2022-02-21 04:23:18,911 INFO L290 TraceCheckUtils]: 24: Hoare triple {26318#false} assume !(0 == ~T5_E~0); {26318#false} is VALID [2022-02-21 04:23:18,911 INFO L290 TraceCheckUtils]: 25: Hoare triple {26318#false} assume !(0 == ~T6_E~0); {26318#false} is VALID [2022-02-21 04:23:18,912 INFO L290 TraceCheckUtils]: 26: Hoare triple {26318#false} assume !(0 == ~T7_E~0); {26318#false} is VALID [2022-02-21 04:23:18,912 INFO L290 TraceCheckUtils]: 27: Hoare triple {26318#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {26318#false} is VALID [2022-02-21 04:23:18,912 INFO L290 TraceCheckUtils]: 28: Hoare triple {26318#false} assume !(0 == ~T9_E~0); {26318#false} is VALID [2022-02-21 04:23:18,912 INFO L290 TraceCheckUtils]: 29: Hoare triple {26318#false} assume !(0 == ~T10_E~0); {26318#false} is VALID [2022-02-21 04:23:18,912 INFO L290 TraceCheckUtils]: 30: Hoare triple {26318#false} assume !(0 == ~T11_E~0); {26318#false} is VALID [2022-02-21 04:23:18,912 INFO L290 TraceCheckUtils]: 31: Hoare triple {26318#false} assume !(0 == ~T12_E~0); {26318#false} is VALID [2022-02-21 04:23:18,912 INFO L290 TraceCheckUtils]: 32: Hoare triple {26318#false} assume !(0 == ~T13_E~0); {26318#false} is VALID [2022-02-21 04:23:18,913 INFO L290 TraceCheckUtils]: 33: Hoare triple {26318#false} assume !(0 == ~E_M~0); {26318#false} is VALID [2022-02-21 04:23:18,913 INFO L290 TraceCheckUtils]: 34: Hoare triple {26318#false} assume !(0 == ~E_1~0); {26318#false} is VALID [2022-02-21 04:23:18,913 INFO L290 TraceCheckUtils]: 35: Hoare triple {26318#false} assume 0 == ~E_2~0;~E_2~0 := 1; {26318#false} is VALID [2022-02-21 04:23:18,913 INFO L290 TraceCheckUtils]: 36: Hoare triple {26318#false} assume !(0 == ~E_3~0); {26318#false} is VALID [2022-02-21 04:23:18,913 INFO L290 TraceCheckUtils]: 37: Hoare triple {26318#false} assume !(0 == ~E_4~0); {26318#false} is VALID [2022-02-21 04:23:18,913 INFO L290 TraceCheckUtils]: 38: Hoare triple {26318#false} assume !(0 == ~E_5~0); {26318#false} is VALID [2022-02-21 04:23:18,913 INFO L290 TraceCheckUtils]: 39: Hoare triple {26318#false} assume !(0 == ~E_6~0); {26318#false} is VALID [2022-02-21 04:23:18,913 INFO L290 TraceCheckUtils]: 40: Hoare triple {26318#false} assume !(0 == ~E_7~0); {26318#false} is VALID [2022-02-21 04:23:18,914 INFO L290 TraceCheckUtils]: 41: Hoare triple {26318#false} assume !(0 == ~E_8~0); {26318#false} is VALID [2022-02-21 04:23:18,914 INFO L290 TraceCheckUtils]: 42: Hoare triple {26318#false} assume !(0 == ~E_9~0); {26318#false} is VALID [2022-02-21 04:23:18,914 INFO L290 TraceCheckUtils]: 43: Hoare triple {26318#false} assume 0 == ~E_10~0;~E_10~0 := 1; {26318#false} is VALID [2022-02-21 04:23:18,914 INFO L290 TraceCheckUtils]: 44: Hoare triple {26318#false} assume !(0 == ~E_11~0); {26318#false} is VALID [2022-02-21 04:23:18,914 INFO L290 TraceCheckUtils]: 45: Hoare triple {26318#false} assume !(0 == ~E_12~0); {26318#false} is VALID [2022-02-21 04:23:18,914 INFO L290 TraceCheckUtils]: 46: Hoare triple {26318#false} assume !(0 == ~E_13~0); {26318#false} is VALID [2022-02-21 04:23:18,914 INFO L290 TraceCheckUtils]: 47: Hoare triple {26318#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26318#false} is VALID [2022-02-21 04:23:18,914 INFO L290 TraceCheckUtils]: 48: Hoare triple {26318#false} assume !(1 == ~m_pc~0); {26318#false} is VALID [2022-02-21 04:23:18,915 INFO L290 TraceCheckUtils]: 49: Hoare triple {26318#false} is_master_triggered_~__retres1~0#1 := 0; {26318#false} is VALID [2022-02-21 04:23:18,915 INFO L290 TraceCheckUtils]: 50: Hoare triple {26318#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26318#false} is VALID [2022-02-21 04:23:18,915 INFO L290 TraceCheckUtils]: 51: Hoare triple {26318#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26318#false} is VALID [2022-02-21 04:23:18,915 INFO L290 TraceCheckUtils]: 52: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp~1#1); {26318#false} is VALID [2022-02-21 04:23:18,915 INFO L290 TraceCheckUtils]: 53: Hoare triple {26318#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26318#false} is VALID [2022-02-21 04:23:18,915 INFO L290 TraceCheckUtils]: 54: Hoare triple {26318#false} assume 1 == ~t1_pc~0; {26318#false} is VALID [2022-02-21 04:23:18,915 INFO L290 TraceCheckUtils]: 55: Hoare triple {26318#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {26318#false} is VALID [2022-02-21 04:23:18,916 INFO L290 TraceCheckUtils]: 56: Hoare triple {26318#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26318#false} is VALID [2022-02-21 04:23:18,916 INFO L290 TraceCheckUtils]: 57: Hoare triple {26318#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26318#false} is VALID [2022-02-21 04:23:18,916 INFO L290 TraceCheckUtils]: 58: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___0~0#1); {26318#false} is VALID [2022-02-21 04:23:18,916 INFO L290 TraceCheckUtils]: 59: Hoare triple {26318#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26318#false} is VALID [2022-02-21 04:23:18,916 INFO L290 TraceCheckUtils]: 60: Hoare triple {26318#false} assume 1 == ~t2_pc~0; {26318#false} is VALID [2022-02-21 04:23:18,916 INFO L290 TraceCheckUtils]: 61: Hoare triple {26318#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26318#false} is VALID [2022-02-21 04:23:18,916 INFO L290 TraceCheckUtils]: 62: Hoare triple {26318#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26318#false} is VALID [2022-02-21 04:23:18,917 INFO L290 TraceCheckUtils]: 63: Hoare triple {26318#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26318#false} is VALID [2022-02-21 04:23:18,917 INFO L290 TraceCheckUtils]: 64: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___1~0#1); {26318#false} is VALID [2022-02-21 04:23:18,917 INFO L290 TraceCheckUtils]: 65: Hoare triple {26318#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26318#false} is VALID [2022-02-21 04:23:18,917 INFO L290 TraceCheckUtils]: 66: Hoare triple {26318#false} assume !(1 == ~t3_pc~0); {26318#false} is VALID [2022-02-21 04:23:18,917 INFO L290 TraceCheckUtils]: 67: Hoare triple {26318#false} is_transmit3_triggered_~__retres1~3#1 := 0; {26318#false} is VALID [2022-02-21 04:23:18,917 INFO L290 TraceCheckUtils]: 68: Hoare triple {26318#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26318#false} is VALID [2022-02-21 04:23:18,917 INFO L290 TraceCheckUtils]: 69: Hoare triple {26318#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26318#false} is VALID [2022-02-21 04:23:18,917 INFO L290 TraceCheckUtils]: 70: Hoare triple {26318#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26318#false} is VALID [2022-02-21 04:23:18,918 INFO L290 TraceCheckUtils]: 71: Hoare triple {26318#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26318#false} is VALID [2022-02-21 04:23:18,918 INFO L290 TraceCheckUtils]: 72: Hoare triple {26318#false} assume 1 == ~t4_pc~0; {26318#false} is VALID [2022-02-21 04:23:18,918 INFO L290 TraceCheckUtils]: 73: Hoare triple {26318#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26318#false} is VALID [2022-02-21 04:23:18,918 INFO L290 TraceCheckUtils]: 74: Hoare triple {26318#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26318#false} is VALID [2022-02-21 04:23:18,918 INFO L290 TraceCheckUtils]: 75: Hoare triple {26318#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26318#false} is VALID [2022-02-21 04:23:18,918 INFO L290 TraceCheckUtils]: 76: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___3~0#1); {26318#false} is VALID [2022-02-21 04:23:18,918 INFO L290 TraceCheckUtils]: 77: Hoare triple {26318#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26318#false} is VALID [2022-02-21 04:23:18,918 INFO L290 TraceCheckUtils]: 78: Hoare triple {26318#false} assume !(1 == ~t5_pc~0); {26318#false} is VALID [2022-02-21 04:23:18,919 INFO L290 TraceCheckUtils]: 79: Hoare triple {26318#false} is_transmit5_triggered_~__retres1~5#1 := 0; {26318#false} is VALID [2022-02-21 04:23:18,919 INFO L290 TraceCheckUtils]: 80: Hoare triple {26318#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26318#false} is VALID [2022-02-21 04:23:18,919 INFO L290 TraceCheckUtils]: 81: Hoare triple {26318#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26318#false} is VALID [2022-02-21 04:23:18,919 INFO L290 TraceCheckUtils]: 82: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___4~0#1); {26318#false} is VALID [2022-02-21 04:23:18,919 INFO L290 TraceCheckUtils]: 83: Hoare triple {26318#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26318#false} is VALID [2022-02-21 04:23:18,919 INFO L290 TraceCheckUtils]: 84: Hoare triple {26318#false} assume 1 == ~t6_pc~0; {26318#false} is VALID [2022-02-21 04:23:18,919 INFO L290 TraceCheckUtils]: 85: Hoare triple {26318#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {26318#false} is VALID [2022-02-21 04:23:18,920 INFO L290 TraceCheckUtils]: 86: Hoare triple {26318#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26318#false} is VALID [2022-02-21 04:23:18,920 INFO L290 TraceCheckUtils]: 87: Hoare triple {26318#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {26318#false} is VALID [2022-02-21 04:23:18,920 INFO L290 TraceCheckUtils]: 88: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___5~0#1); {26318#false} is VALID [2022-02-21 04:23:18,920 INFO L290 TraceCheckUtils]: 89: Hoare triple {26318#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26318#false} is VALID [2022-02-21 04:23:18,920 INFO L290 TraceCheckUtils]: 90: Hoare triple {26318#false} assume !(1 == ~t7_pc~0); {26318#false} is VALID [2022-02-21 04:23:18,920 INFO L290 TraceCheckUtils]: 91: Hoare triple {26318#false} is_transmit7_triggered_~__retres1~7#1 := 0; {26318#false} is VALID [2022-02-21 04:23:18,920 INFO L290 TraceCheckUtils]: 92: Hoare triple {26318#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26318#false} is VALID [2022-02-21 04:23:18,921 INFO L290 TraceCheckUtils]: 93: Hoare triple {26318#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {26318#false} is VALID [2022-02-21 04:23:18,921 INFO L290 TraceCheckUtils]: 94: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___6~0#1); {26318#false} is VALID [2022-02-21 04:23:18,921 INFO L290 TraceCheckUtils]: 95: Hoare triple {26318#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26318#false} is VALID [2022-02-21 04:23:18,921 INFO L290 TraceCheckUtils]: 96: Hoare triple {26318#false} assume 1 == ~t8_pc~0; {26318#false} is VALID [2022-02-21 04:23:18,921 INFO L290 TraceCheckUtils]: 97: Hoare triple {26318#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {26318#false} is VALID [2022-02-21 04:23:18,921 INFO L290 TraceCheckUtils]: 98: Hoare triple {26318#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26318#false} is VALID [2022-02-21 04:23:18,921 INFO L290 TraceCheckUtils]: 99: Hoare triple {26318#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {26318#false} is VALID [2022-02-21 04:23:18,921 INFO L290 TraceCheckUtils]: 100: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___7~0#1); {26318#false} is VALID [2022-02-21 04:23:18,922 INFO L290 TraceCheckUtils]: 101: Hoare triple {26318#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26318#false} is VALID [2022-02-21 04:23:18,922 INFO L290 TraceCheckUtils]: 102: Hoare triple {26318#false} assume 1 == ~t9_pc~0; {26318#false} is VALID [2022-02-21 04:23:18,922 INFO L290 TraceCheckUtils]: 103: Hoare triple {26318#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26318#false} is VALID [2022-02-21 04:23:18,922 INFO L290 TraceCheckUtils]: 104: Hoare triple {26318#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26318#false} is VALID [2022-02-21 04:23:18,922 INFO L290 TraceCheckUtils]: 105: Hoare triple {26318#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {26318#false} is VALID [2022-02-21 04:23:18,922 INFO L290 TraceCheckUtils]: 106: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___8~0#1); {26318#false} is VALID [2022-02-21 04:23:18,922 INFO L290 TraceCheckUtils]: 107: Hoare triple {26318#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26318#false} is VALID [2022-02-21 04:23:18,923 INFO L290 TraceCheckUtils]: 108: Hoare triple {26318#false} assume !(1 == ~t10_pc~0); {26318#false} is VALID [2022-02-21 04:23:18,923 INFO L290 TraceCheckUtils]: 109: Hoare triple {26318#false} is_transmit10_triggered_~__retres1~10#1 := 0; {26318#false} is VALID [2022-02-21 04:23:18,923 INFO L290 TraceCheckUtils]: 110: Hoare triple {26318#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26318#false} is VALID [2022-02-21 04:23:18,923 INFO L290 TraceCheckUtils]: 111: Hoare triple {26318#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {26318#false} is VALID [2022-02-21 04:23:18,923 INFO L290 TraceCheckUtils]: 112: Hoare triple {26318#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {26318#false} is VALID [2022-02-21 04:23:18,923 INFO L290 TraceCheckUtils]: 113: Hoare triple {26318#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {26318#false} is VALID [2022-02-21 04:23:18,923 INFO L290 TraceCheckUtils]: 114: Hoare triple {26318#false} assume 1 == ~t11_pc~0; {26318#false} is VALID [2022-02-21 04:23:18,923 INFO L290 TraceCheckUtils]: 115: Hoare triple {26318#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {26318#false} is VALID [2022-02-21 04:23:18,924 INFO L290 TraceCheckUtils]: 116: Hoare triple {26318#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {26318#false} is VALID [2022-02-21 04:23:18,924 INFO L290 TraceCheckUtils]: 117: Hoare triple {26318#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {26318#false} is VALID [2022-02-21 04:23:18,924 INFO L290 TraceCheckUtils]: 118: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___10~0#1); {26318#false} is VALID [2022-02-21 04:23:18,924 INFO L290 TraceCheckUtils]: 119: Hoare triple {26318#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {26318#false} is VALID [2022-02-21 04:23:18,924 INFO L290 TraceCheckUtils]: 120: Hoare triple {26318#false} assume !(1 == ~t12_pc~0); {26318#false} is VALID [2022-02-21 04:23:18,924 INFO L290 TraceCheckUtils]: 121: Hoare triple {26318#false} is_transmit12_triggered_~__retres1~12#1 := 0; {26318#false} is VALID [2022-02-21 04:23:18,924 INFO L290 TraceCheckUtils]: 122: Hoare triple {26318#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {26318#false} is VALID [2022-02-21 04:23:18,925 INFO L290 TraceCheckUtils]: 123: Hoare triple {26318#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {26318#false} is VALID [2022-02-21 04:23:18,925 INFO L290 TraceCheckUtils]: 124: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___11~0#1); {26318#false} is VALID [2022-02-21 04:23:18,925 INFO L290 TraceCheckUtils]: 125: Hoare triple {26318#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {26318#false} is VALID [2022-02-21 04:23:18,925 INFO L290 TraceCheckUtils]: 126: Hoare triple {26318#false} assume 1 == ~t13_pc~0; {26318#false} is VALID [2022-02-21 04:23:18,925 INFO L290 TraceCheckUtils]: 127: Hoare triple {26318#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {26318#false} is VALID [2022-02-21 04:23:18,925 INFO L290 TraceCheckUtils]: 128: Hoare triple {26318#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {26318#false} is VALID [2022-02-21 04:23:18,925 INFO L290 TraceCheckUtils]: 129: Hoare triple {26318#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {26318#false} is VALID [2022-02-21 04:23:18,925 INFO L290 TraceCheckUtils]: 130: Hoare triple {26318#false} assume !(0 != activate_threads_~tmp___12~0#1); {26318#false} is VALID [2022-02-21 04:23:18,926 INFO L290 TraceCheckUtils]: 131: Hoare triple {26318#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26318#false} is VALID [2022-02-21 04:23:18,926 INFO L290 TraceCheckUtils]: 132: Hoare triple {26318#false} assume !(1 == ~M_E~0); {26318#false} is VALID [2022-02-21 04:23:18,926 INFO L290 TraceCheckUtils]: 133: Hoare triple {26318#false} assume !(1 == ~T1_E~0); {26318#false} is VALID [2022-02-21 04:23:18,926 INFO L290 TraceCheckUtils]: 134: Hoare triple {26318#false} assume !(1 == ~T2_E~0); {26318#false} is VALID [2022-02-21 04:23:18,926 INFO L290 TraceCheckUtils]: 135: Hoare triple {26318#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,926 INFO L290 TraceCheckUtils]: 136: Hoare triple {26318#false} assume !(1 == ~T4_E~0); {26318#false} is VALID [2022-02-21 04:23:18,926 INFO L290 TraceCheckUtils]: 137: Hoare triple {26318#false} assume !(1 == ~T5_E~0); {26318#false} is VALID [2022-02-21 04:23:18,927 INFO L290 TraceCheckUtils]: 138: Hoare triple {26318#false} assume !(1 == ~T6_E~0); {26318#false} is VALID [2022-02-21 04:23:18,927 INFO L290 TraceCheckUtils]: 139: Hoare triple {26318#false} assume !(1 == ~T7_E~0); {26318#false} is VALID [2022-02-21 04:23:18,927 INFO L290 TraceCheckUtils]: 140: Hoare triple {26318#false} assume !(1 == ~T8_E~0); {26318#false} is VALID [2022-02-21 04:23:18,927 INFO L290 TraceCheckUtils]: 141: Hoare triple {26318#false} assume !(1 == ~T9_E~0); {26318#false} is VALID [2022-02-21 04:23:18,927 INFO L290 TraceCheckUtils]: 142: Hoare triple {26318#false} assume !(1 == ~T10_E~0); {26318#false} is VALID [2022-02-21 04:23:18,927 INFO L290 TraceCheckUtils]: 143: Hoare triple {26318#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,927 INFO L290 TraceCheckUtils]: 144: Hoare triple {26318#false} assume !(1 == ~T12_E~0); {26318#false} is VALID [2022-02-21 04:23:18,927 INFO L290 TraceCheckUtils]: 145: Hoare triple {26318#false} assume !(1 == ~T13_E~0); {26318#false} is VALID [2022-02-21 04:23:18,928 INFO L290 TraceCheckUtils]: 146: Hoare triple {26318#false} assume !(1 == ~E_M~0); {26318#false} is VALID [2022-02-21 04:23:18,928 INFO L290 TraceCheckUtils]: 147: Hoare triple {26318#false} assume !(1 == ~E_1~0); {26318#false} is VALID [2022-02-21 04:23:18,928 INFO L290 TraceCheckUtils]: 148: Hoare triple {26318#false} assume !(1 == ~E_2~0); {26318#false} is VALID [2022-02-21 04:23:18,928 INFO L290 TraceCheckUtils]: 149: Hoare triple {26318#false} assume !(1 == ~E_3~0); {26318#false} is VALID [2022-02-21 04:23:18,928 INFO L290 TraceCheckUtils]: 150: Hoare triple {26318#false} assume !(1 == ~E_4~0); {26318#false} is VALID [2022-02-21 04:23:18,928 INFO L290 TraceCheckUtils]: 151: Hoare triple {26318#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,928 INFO L290 TraceCheckUtils]: 152: Hoare triple {26318#false} assume !(1 == ~E_6~0); {26318#false} is VALID [2022-02-21 04:23:18,929 INFO L290 TraceCheckUtils]: 153: Hoare triple {26318#false} assume !(1 == ~E_7~0); {26318#false} is VALID [2022-02-21 04:23:18,929 INFO L290 TraceCheckUtils]: 154: Hoare triple {26318#false} assume !(1 == ~E_8~0); {26318#false} is VALID [2022-02-21 04:23:18,929 INFO L290 TraceCheckUtils]: 155: Hoare triple {26318#false} assume !(1 == ~E_9~0); {26318#false} is VALID [2022-02-21 04:23:18,929 INFO L290 TraceCheckUtils]: 156: Hoare triple {26318#false} assume !(1 == ~E_10~0); {26318#false} is VALID [2022-02-21 04:23:18,929 INFO L290 TraceCheckUtils]: 157: Hoare triple {26318#false} assume !(1 == ~E_11~0); {26318#false} is VALID [2022-02-21 04:23:18,929 INFO L290 TraceCheckUtils]: 158: Hoare triple {26318#false} assume !(1 == ~E_12~0); {26318#false} is VALID [2022-02-21 04:23:18,929 INFO L290 TraceCheckUtils]: 159: Hoare triple {26318#false} assume 1 == ~E_13~0;~E_13~0 := 2; {26318#false} is VALID [2022-02-21 04:23:18,929 INFO L290 TraceCheckUtils]: 160: Hoare triple {26318#false} assume { :end_inline_reset_delta_events } true; {26318#false} is VALID [2022-02-21 04:23:18,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:18,930 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:18,930 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686625826] [2022-02-21 04:23:18,931 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686625826] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:18,931 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:18,931 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:18,931 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114924827] [2022-02-21 04:23:18,932 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:18,932 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:18,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:18,932 INFO L85 PathProgramCache]: Analyzing trace with hash -1257801565, now seen corresponding path program 1 times [2022-02-21 04:23:18,933 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:18,935 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677422781] [2022-02-21 04:23:18,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:18,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:18,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:18,986 INFO L290 TraceCheckUtils]: 0: Hoare triple {26320#true} assume !false; {26320#true} is VALID [2022-02-21 04:23:18,987 INFO L290 TraceCheckUtils]: 1: Hoare triple {26320#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {26320#true} is VALID [2022-02-21 04:23:18,987 INFO L290 TraceCheckUtils]: 2: Hoare triple {26320#true} assume !false; {26320#true} is VALID [2022-02-21 04:23:18,987 INFO L290 TraceCheckUtils]: 3: Hoare triple {26320#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {26320#true} is VALID [2022-02-21 04:23:18,987 INFO L290 TraceCheckUtils]: 4: Hoare triple {26320#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {26320#true} is VALID [2022-02-21 04:23:18,987 INFO L290 TraceCheckUtils]: 5: Hoare triple {26320#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {26320#true} is VALID [2022-02-21 04:23:18,987 INFO L290 TraceCheckUtils]: 6: Hoare triple {26320#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {26320#true} is VALID [2022-02-21 04:23:18,988 INFO L290 TraceCheckUtils]: 7: Hoare triple {26320#true} assume !(0 != eval_~tmp~0#1); {26320#true} is VALID [2022-02-21 04:23:18,988 INFO L290 TraceCheckUtils]: 8: Hoare triple {26320#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {26320#true} is VALID [2022-02-21 04:23:18,988 INFO L290 TraceCheckUtils]: 9: Hoare triple {26320#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {26320#true} is VALID [2022-02-21 04:23:18,988 INFO L290 TraceCheckUtils]: 10: Hoare triple {26320#true} assume 0 == ~M_E~0;~M_E~0 := 1; {26320#true} is VALID [2022-02-21 04:23:18,988 INFO L290 TraceCheckUtils]: 11: Hoare triple {26320#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {26320#true} is VALID [2022-02-21 04:23:18,988 INFO L290 TraceCheckUtils]: 12: Hoare triple {26320#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {26320#true} is VALID [2022-02-21 04:23:18,988 INFO L290 TraceCheckUtils]: 13: Hoare triple {26320#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {26320#true} is VALID [2022-02-21 04:23:18,988 INFO L290 TraceCheckUtils]: 14: Hoare triple {26320#true} assume !(0 == ~T4_E~0); {26320#true} is VALID [2022-02-21 04:23:18,989 INFO L290 TraceCheckUtils]: 15: Hoare triple {26320#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {26320#true} is VALID [2022-02-21 04:23:18,989 INFO L290 TraceCheckUtils]: 16: Hoare triple {26320#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {26320#true} is VALID [2022-02-21 04:23:18,989 INFO L290 TraceCheckUtils]: 17: Hoare triple {26320#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,989 INFO L290 TraceCheckUtils]: 18: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,990 INFO L290 TraceCheckUtils]: 19: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,990 INFO L290 TraceCheckUtils]: 20: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,990 INFO L290 TraceCheckUtils]: 21: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,990 INFO L290 TraceCheckUtils]: 22: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,991 INFO L290 TraceCheckUtils]: 23: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,991 INFO L290 TraceCheckUtils]: 24: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,991 INFO L290 TraceCheckUtils]: 25: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,992 INFO L290 TraceCheckUtils]: 26: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,992 INFO L290 TraceCheckUtils]: 27: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,992 INFO L290 TraceCheckUtils]: 28: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,992 INFO L290 TraceCheckUtils]: 29: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,993 INFO L290 TraceCheckUtils]: 30: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,993 INFO L290 TraceCheckUtils]: 31: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,993 INFO L290 TraceCheckUtils]: 32: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,994 INFO L290 TraceCheckUtils]: 33: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,994 INFO L290 TraceCheckUtils]: 34: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,994 INFO L290 TraceCheckUtils]: 35: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,994 INFO L290 TraceCheckUtils]: 36: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,995 INFO L290 TraceCheckUtils]: 37: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,995 INFO L290 TraceCheckUtils]: 38: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,995 INFO L290 TraceCheckUtils]: 39: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,996 INFO L290 TraceCheckUtils]: 40: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,996 INFO L290 TraceCheckUtils]: 41: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,996 INFO L290 TraceCheckUtils]: 42: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,996 INFO L290 TraceCheckUtils]: 43: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,997 INFO L290 TraceCheckUtils]: 44: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,997 INFO L290 TraceCheckUtils]: 45: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,997 INFO L290 TraceCheckUtils]: 46: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,997 INFO L290 TraceCheckUtils]: 47: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,998 INFO L290 TraceCheckUtils]: 48: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,998 INFO L290 TraceCheckUtils]: 49: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,998 INFO L290 TraceCheckUtils]: 50: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,999 INFO L290 TraceCheckUtils]: 51: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,999 INFO L290 TraceCheckUtils]: 52: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,999 INFO L290 TraceCheckUtils]: 53: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:18,999 INFO L290 TraceCheckUtils]: 54: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,000 INFO L290 TraceCheckUtils]: 55: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,000 INFO L290 TraceCheckUtils]: 56: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,000 INFO L290 TraceCheckUtils]: 57: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,001 INFO L290 TraceCheckUtils]: 58: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,001 INFO L290 TraceCheckUtils]: 59: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,001 INFO L290 TraceCheckUtils]: 60: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,001 INFO L290 TraceCheckUtils]: 61: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,002 INFO L290 TraceCheckUtils]: 62: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,002 INFO L290 TraceCheckUtils]: 63: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,002 INFO L290 TraceCheckUtils]: 64: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,002 INFO L290 TraceCheckUtils]: 65: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,003 INFO L290 TraceCheckUtils]: 66: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,003 INFO L290 TraceCheckUtils]: 67: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,003 INFO L290 TraceCheckUtils]: 68: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,004 INFO L290 TraceCheckUtils]: 69: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,004 INFO L290 TraceCheckUtils]: 70: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,004 INFO L290 TraceCheckUtils]: 71: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,004 INFO L290 TraceCheckUtils]: 72: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,005 INFO L290 TraceCheckUtils]: 73: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,005 INFO L290 TraceCheckUtils]: 74: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,005 INFO L290 TraceCheckUtils]: 75: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,006 INFO L290 TraceCheckUtils]: 76: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,006 INFO L290 TraceCheckUtils]: 77: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,006 INFO L290 TraceCheckUtils]: 78: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,006 INFO L290 TraceCheckUtils]: 79: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,007 INFO L290 TraceCheckUtils]: 80: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,007 INFO L290 TraceCheckUtils]: 81: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,007 INFO L290 TraceCheckUtils]: 82: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,007 INFO L290 TraceCheckUtils]: 83: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,008 INFO L290 TraceCheckUtils]: 84: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,008 INFO L290 TraceCheckUtils]: 85: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,008 INFO L290 TraceCheckUtils]: 86: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,009 INFO L290 TraceCheckUtils]: 87: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t8_pc~0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,009 INFO L290 TraceCheckUtils]: 88: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,009 INFO L290 TraceCheckUtils]: 89: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,009 INFO L290 TraceCheckUtils]: 90: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,010 INFO L290 TraceCheckUtils]: 91: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,010 INFO L290 TraceCheckUtils]: 92: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,010 INFO L290 TraceCheckUtils]: 93: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,011 INFO L290 TraceCheckUtils]: 94: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,011 INFO L290 TraceCheckUtils]: 95: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,011 INFO L290 TraceCheckUtils]: 96: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,011 INFO L290 TraceCheckUtils]: 97: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,012 INFO L290 TraceCheckUtils]: 98: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,012 INFO L290 TraceCheckUtils]: 99: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t10_pc~0); {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,012 INFO L290 TraceCheckUtils]: 100: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 101: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 102: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 103: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,013 INFO L290 TraceCheckUtils]: 104: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 105: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 106: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 107: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,014 INFO L290 TraceCheckUtils]: 108: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 109: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 110: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,015 INFO L290 TraceCheckUtils]: 111: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 112: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 113: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 114: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,016 INFO L290 TraceCheckUtils]: 115: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 116: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 117: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t13_pc~0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,017 INFO L290 TraceCheckUtils]: 118: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 119: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 120: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 121: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,018 INFO L290 TraceCheckUtils]: 122: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 123: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 124: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 125: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,019 INFO L290 TraceCheckUtils]: 126: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 127: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 128: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,020 INFO L290 TraceCheckUtils]: 129: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {26322#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 130: Hoare triple {26322#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {26321#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 131: Hoare triple {26321#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 132: Hoare triple {26321#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 133: Hoare triple {26321#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 134: Hoare triple {26321#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 135: Hoare triple {26321#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,021 INFO L290 TraceCheckUtils]: 136: Hoare triple {26321#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 137: Hoare triple {26321#false} assume 1 == ~E_M~0;~E_M~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 138: Hoare triple {26321#false} assume !(1 == ~E_1~0); {26321#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 139: Hoare triple {26321#false} assume 1 == ~E_2~0;~E_2~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 140: Hoare triple {26321#false} assume 1 == ~E_3~0;~E_3~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 141: Hoare triple {26321#false} assume 1 == ~E_4~0;~E_4~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 142: Hoare triple {26321#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,022 INFO L290 TraceCheckUtils]: 143: Hoare triple {26321#false} assume 1 == ~E_6~0;~E_6~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 144: Hoare triple {26321#false} assume 1 == ~E_7~0;~E_7~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 145: Hoare triple {26321#false} assume 1 == ~E_8~0;~E_8~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 146: Hoare triple {26321#false} assume !(1 == ~E_9~0); {26321#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 147: Hoare triple {26321#false} assume 1 == ~E_10~0;~E_10~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 148: Hoare triple {26321#false} assume 1 == ~E_11~0;~E_11~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 149: Hoare triple {26321#false} assume 1 == ~E_12~0;~E_12~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 150: Hoare triple {26321#false} assume 1 == ~E_13~0;~E_13~0 := 2; {26321#false} is VALID [2022-02-21 04:23:19,023 INFO L290 TraceCheckUtils]: 151: Hoare triple {26321#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {26321#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 152: Hoare triple {26321#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {26321#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 153: Hoare triple {26321#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {26321#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 154: Hoare triple {26321#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {26321#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 155: Hoare triple {26321#false} assume !(0 == start_simulation_~tmp~3#1); {26321#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 156: Hoare triple {26321#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {26321#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 157: Hoare triple {26321#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {26321#false} is VALID [2022-02-21 04:23:19,024 INFO L290 TraceCheckUtils]: 158: Hoare triple {26321#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {26321#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 159: Hoare triple {26321#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {26321#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 160: Hoare triple {26321#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {26321#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 161: Hoare triple {26321#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {26321#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 162: Hoare triple {26321#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {26321#false} is VALID [2022-02-21 04:23:19,025 INFO L290 TraceCheckUtils]: 163: Hoare triple {26321#false} assume !(0 != start_simulation_~tmp___0~1#1); {26321#false} is VALID [2022-02-21 04:23:19,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:19,026 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:19,026 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677422781] [2022-02-21 04:23:19,026 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1677422781] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:19,026 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:19,027 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:19,027 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1061841197] [2022-02-21 04:23:19,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:19,027 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:19,027 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:19,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:19,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:19,028 INFO L87 Difference]: Start difference. First operand 2021 states and 2990 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:20,395 INFO L93 Difference]: Finished difference Result 2021 states and 2989 transitions. [2022-02-21 04:23:20,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:20,395 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,494 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:20,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2989 transitions. [2022-02-21 04:23:20,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:20,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2989 transitions. [2022-02-21 04:23:20,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:20,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:20,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2989 transitions. [2022-02-21 04:23:20,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:20,701 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2022-02-21 04:23:20,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2989 transitions. [2022-02-21 04:23:20,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:20,718 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:20,720 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2989 transitions. Second operand has 2021 states, 2021 states have (on average 1.47897080653142) internal successors, (2989), 2020 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,722 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2989 transitions. Second operand has 2021 states, 2021 states have (on average 1.47897080653142) internal successors, (2989), 2020 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,723 INFO L87 Difference]: Start difference. First operand 2021 states and 2989 transitions. Second operand has 2021 states, 2021 states have (on average 1.47897080653142) internal successors, (2989), 2020 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:20,807 INFO L93 Difference]: Finished difference Result 2021 states and 2989 transitions. [2022-02-21 04:23:20,807 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2989 transitions. [2022-02-21 04:23:20,808 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:20,808 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:20,811 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.47897080653142) internal successors, (2989), 2020 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2989 transitions. [2022-02-21 04:23:20,812 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.47897080653142) internal successors, (2989), 2020 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2989 transitions. [2022-02-21 04:23:20,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:20,915 INFO L93 Difference]: Finished difference Result 2021 states and 2989 transitions. [2022-02-21 04:23:20,915 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2989 transitions. [2022-02-21 04:23:20,916 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:20,916 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:20,917 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:20,917 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:20,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.47897080653142) internal successors, (2989), 2020 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2989 transitions. [2022-02-21 04:23:21,001 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2022-02-21 04:23:21,001 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2022-02-21 04:23:21,001 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:23:21,001 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2989 transitions. [2022-02-21 04:23:21,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:21,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:21,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:21,006 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:21,006 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:21,007 INFO L791 eck$LassoCheckResult]: Stem: 29220#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 29221#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28952#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28953#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30343#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 30344#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29139#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29140#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29174#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 30011#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 30012#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 30124#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30125#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28958#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28959#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30161#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29483#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29484#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 30065#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30331#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 30221#L1286-2 assume !(0 == ~T1_E~0); 28867#L1291-1 assume !(0 == ~T2_E~0); 28868#L1296-1 assume !(0 == ~T3_E~0); 29573#L1301-1 assume !(0 == ~T4_E~0); 29574#L1306-1 assume !(0 == ~T5_E~0); 30074#L1311-1 assume !(0 == ~T6_E~0); 28827#L1316-1 assume !(0 == ~T7_E~0); 28828#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29593#L1326-1 assume !(0 == ~T9_E~0); 28642#L1331-1 assume !(0 == ~T10_E~0); 28348#L1336-1 assume !(0 == ~T11_E~0); 28349#L1341-1 assume !(0 == ~T12_E~0); 28400#L1346-1 assume !(0 == ~T13_E~0); 28401#L1351-1 assume !(0 == ~E_M~0); 28774#L1356-1 assume !(0 == ~E_1~0); 28775#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 30294#L1366-1 assume !(0 == ~E_3~0); 28820#L1371-1 assume !(0 == ~E_4~0); 28821#L1376-1 assume !(0 == ~E_5~0); 29634#L1381-1 assume !(0 == ~E_6~0); 29635#L1386-1 assume !(0 == ~E_7~0); 30322#L1391-1 assume !(0 == ~E_8~0); 30335#L1396-1 assume !(0 == ~E_9~0); 29517#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 29518#L1406-1 assume !(0 == ~E_11~0); 29820#L1411-1 assume !(0 == ~E_12~0); 29821#L1416-1 assume !(0 == ~E_13~0); 29441#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29279#L635 assume !(1 == ~m_pc~0); 28418#L635-2 is_master_triggered_~__retres1~0#1 := 0; 28419#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28769#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29405#L1598 assume !(0 != activate_threads_~tmp~1#1); 28597#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28598#L654 assume 1 == ~t1_pc~0; 29303#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29304#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30319#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29385#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 29386#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28645#L673 assume 1 == ~t2_pc~0; 28646#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29790#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29791#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30349#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 30356#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29464#L692 assume !(1 == ~t3_pc~0); 29281#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29282#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29141#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29109#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29110#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28670#L711 assume 1 == ~t4_pc~0; 28671#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29154#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29611#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28373#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 28374#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30342#L730 assume !(1 == ~t5_pc~0); 29724#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28552#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28553#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28680#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 28681#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29023#L749 assume 1 == ~t6_pc~0; 28797#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28557#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28989#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28990#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 29212#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28353#L768 assume !(1 == ~t7_pc~0); 28354#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 29658#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28590#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28591#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 29677#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28829#L787 assume 1 == ~t8_pc~0; 28830#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30025#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30189#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30190#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 28398#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28399#L806 assume 1 == ~t9_pc~0; 30036#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28433#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28434#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28682#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 28683#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30019#L825 assume !(1 == ~t10_pc~0); 30020#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29625#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29626#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28770#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28771#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29354#L844 assume 1 == ~t11_pc~0; 29044#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29045#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29411#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29412#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 30007#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30008#L863 assume !(1 == ~t12_pc~0); 28533#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 28532#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28760#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30099#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 30100#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29478#L882 assume 1 == ~t13_pc~0; 29479#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29763#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30264#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30067#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 29750#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29751#L1434 assume !(1 == ~M_E~0); 30272#L1434-2 assume !(1 == ~T1_E~0); 30348#L1439-1 assume !(1 == ~T2_E~0); 28663#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28664#L1449-1 assume !(1 == ~T4_E~0); 29106#L1454-1 assume !(1 == ~T5_E~0); 29107#L1459-1 assume !(1 == ~T6_E~0); 29678#L1464-1 assume !(1 == ~T7_E~0); 29679#L1469-1 assume !(1 == ~T8_E~0); 29764#L1474-1 assume !(1 == ~T9_E~0); 29442#L1479-1 assume !(1 == ~T10_E~0); 29443#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29686#L1489-1 assume !(1 == ~T12_E~0); 29320#L1494-1 assume !(1 == ~T13_E~0); 29321#L1499-1 assume !(1 == ~E_M~0); 29502#L1504-1 assume !(1 == ~E_1~0); 29503#L1509-1 assume !(1 == ~E_2~0); 30116#L1514-1 assume !(1 == ~E_3~0); 29801#L1519-1 assume !(1 == ~E_4~0); 29802#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30306#L1529-1 assume !(1 == ~E_6~0); 30307#L1534-1 assume !(1 == ~E_7~0); 28453#L1539-1 assume !(1 == ~E_8~0); 28454#L1544-1 assume !(1 == ~E_9~0); 28884#L1549-1 assume !(1 == ~E_10~0); 30284#L1554-1 assume !(1 == ~E_11~0); 30282#L1559-1 assume !(1 == ~E_12~0); 30144#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30145#L1569-1 assume { :end_inline_reset_delta_events } true; 30300#L1935-2 [2022-02-21 04:23:21,007 INFO L793 eck$LassoCheckResult]: Loop: 30300#L1935-2 assume !false; 28462#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28463#L1261 assume !false; 29690#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29691#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28593#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28763#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28764#L1074 assume !(0 != eval_~tmp~0#1); 29121#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29719#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30120#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30176#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29895#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29896#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30332#L1301-3 assume !(0 == ~T4_E~0); 30290#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29398#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28697#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28698#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28803#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29539#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29804#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29805#L1341-3 assume !(0 == ~T12_E~0); 29099#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29090#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29034#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29035#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29615#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28388#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28389#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30131#L1381-3 assume !(0 == ~E_6~0); 29980#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29981#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30162#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30163#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28768#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28599#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28600#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29227#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28477#L635-45 assume 1 == ~m_pc~0; 28478#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29272#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29752#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30006#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28786#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28787#L654-45 assume 1 == ~t1_pc~0; 29607#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29955#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28440#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28441#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28466#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29293#L673-45 assume !(1 == ~t2_pc~0); 29294#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29618#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29619#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30244#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 30064#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28911#L692-45 assume 1 == ~t3_pc~0; 28912#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28638#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29682#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28965#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28966#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29278#L711-45 assume 1 == ~t4_pc~0; 29402#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29403#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29255#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29256#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29659#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28810#L730-45 assume 1 == ~t5_pc~0; 28648#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28649#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29058#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29059#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29810#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28621#L749-45 assume !(1 == ~t6_pc~0); 28622#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 30022#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29785#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29786#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29937#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28937#L768-45 assume 1 == ~t7_pc~0; 28938#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29077#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29881#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29882#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29921#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29922#L787-45 assume 1 == ~t8_pc~0; 30090#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29083#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29084#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29500#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29501#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29809#L806-45 assume !(1 == ~t9_pc~0); 28496#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 28497#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29322#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29150#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29062#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29063#L825-45 assume !(1 == ~t10_pc~0); 29586#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 29587#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29692#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29693#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29845#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28705#L844-45 assume !(1 == ~t11_pc~0); 28706#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29228#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29229#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29245#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 29656#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28745#L863-45 assume 1 == ~t12_pc~0; 28746#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28346#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28347#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28862#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28863#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29662#L882-45 assume 1 == ~t13_pc~0; 30016#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 28365#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 28366#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 28974#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30153#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29769#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29770#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29954#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28659#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28660#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28822#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29759#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29760#L1464-3 assume !(1 == ~T7_E~0); 30206#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30133#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30134#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30208#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29400#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29401#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 30061#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29696#L1504-3 assume !(1 == ~E_1~0); 29697#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30142#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30182#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29323#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29324#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30229#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29624#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29078#L1544-3 assume !(1 == ~E_9~0); 29079#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29594#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28710#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28711#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29860#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29861#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28595#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29160#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29831#L1954 assume !(0 == start_simulation_~tmp~3#1); 29833#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 30083#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28878#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29919#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 30049#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30050#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30140#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30202#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 30300#L1935-2 [2022-02-21 04:23:21,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:21,008 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2022-02-21 04:23:21,008 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:21,008 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816986630] [2022-02-21 04:23:21,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:21,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:21,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:21,027 INFO L290 TraceCheckUtils]: 0: Hoare triple {34410#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {34410#true} is VALID [2022-02-21 04:23:21,028 INFO L290 TraceCheckUtils]: 1: Hoare triple {34410#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {34412#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:21,028 INFO L290 TraceCheckUtils]: 2: Hoare triple {34412#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {34412#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:21,028 INFO L290 TraceCheckUtils]: 3: Hoare triple {34412#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {34412#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:21,028 INFO L290 TraceCheckUtils]: 4: Hoare triple {34412#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {34412#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:21,029 INFO L290 TraceCheckUtils]: 5: Hoare triple {34412#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {34412#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:21,029 INFO L290 TraceCheckUtils]: 6: Hoare triple {34412#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {34412#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:21,029 INFO L290 TraceCheckUtils]: 7: Hoare triple {34412#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {34412#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:21,029 INFO L290 TraceCheckUtils]: 8: Hoare triple {34412#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,030 INFO L290 TraceCheckUtils]: 9: Hoare triple {34411#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,030 INFO L290 TraceCheckUtils]: 10: Hoare triple {34411#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,030 INFO L290 TraceCheckUtils]: 11: Hoare triple {34411#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,030 INFO L290 TraceCheckUtils]: 12: Hoare triple {34411#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,030 INFO L290 TraceCheckUtils]: 13: Hoare triple {34411#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {34411#false} is VALID [2022-02-21 04:23:21,030 INFO L290 TraceCheckUtils]: 14: Hoare triple {34411#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,030 INFO L290 TraceCheckUtils]: 15: Hoare triple {34411#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,031 INFO L290 TraceCheckUtils]: 16: Hoare triple {34411#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,031 INFO L290 TraceCheckUtils]: 17: Hoare triple {34411#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,031 INFO L290 TraceCheckUtils]: 18: Hoare triple {34411#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {34411#false} is VALID [2022-02-21 04:23:21,031 INFO L290 TraceCheckUtils]: 19: Hoare triple {34411#false} assume 0 == ~M_E~0;~M_E~0 := 1; {34411#false} is VALID [2022-02-21 04:23:21,031 INFO L290 TraceCheckUtils]: 20: Hoare triple {34411#false} assume !(0 == ~T1_E~0); {34411#false} is VALID [2022-02-21 04:23:21,031 INFO L290 TraceCheckUtils]: 21: Hoare triple {34411#false} assume !(0 == ~T2_E~0); {34411#false} is VALID [2022-02-21 04:23:21,031 INFO L290 TraceCheckUtils]: 22: Hoare triple {34411#false} assume !(0 == ~T3_E~0); {34411#false} is VALID [2022-02-21 04:23:21,031 INFO L290 TraceCheckUtils]: 23: Hoare triple {34411#false} assume !(0 == ~T4_E~0); {34411#false} is VALID [2022-02-21 04:23:21,032 INFO L290 TraceCheckUtils]: 24: Hoare triple {34411#false} assume !(0 == ~T5_E~0); {34411#false} is VALID [2022-02-21 04:23:21,032 INFO L290 TraceCheckUtils]: 25: Hoare triple {34411#false} assume !(0 == ~T6_E~0); {34411#false} is VALID [2022-02-21 04:23:21,032 INFO L290 TraceCheckUtils]: 26: Hoare triple {34411#false} assume !(0 == ~T7_E~0); {34411#false} is VALID [2022-02-21 04:23:21,032 INFO L290 TraceCheckUtils]: 27: Hoare triple {34411#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {34411#false} is VALID [2022-02-21 04:23:21,032 INFO L290 TraceCheckUtils]: 28: Hoare triple {34411#false} assume !(0 == ~T9_E~0); {34411#false} is VALID [2022-02-21 04:23:21,032 INFO L290 TraceCheckUtils]: 29: Hoare triple {34411#false} assume !(0 == ~T10_E~0); {34411#false} is VALID [2022-02-21 04:23:21,032 INFO L290 TraceCheckUtils]: 30: Hoare triple {34411#false} assume !(0 == ~T11_E~0); {34411#false} is VALID [2022-02-21 04:23:21,033 INFO L290 TraceCheckUtils]: 31: Hoare triple {34411#false} assume !(0 == ~T12_E~0); {34411#false} is VALID [2022-02-21 04:23:21,033 INFO L290 TraceCheckUtils]: 32: Hoare triple {34411#false} assume !(0 == ~T13_E~0); {34411#false} is VALID [2022-02-21 04:23:21,033 INFO L290 TraceCheckUtils]: 33: Hoare triple {34411#false} assume !(0 == ~E_M~0); {34411#false} is VALID [2022-02-21 04:23:21,033 INFO L290 TraceCheckUtils]: 34: Hoare triple {34411#false} assume !(0 == ~E_1~0); {34411#false} is VALID [2022-02-21 04:23:21,033 INFO L290 TraceCheckUtils]: 35: Hoare triple {34411#false} assume 0 == ~E_2~0;~E_2~0 := 1; {34411#false} is VALID [2022-02-21 04:23:21,033 INFO L290 TraceCheckUtils]: 36: Hoare triple {34411#false} assume !(0 == ~E_3~0); {34411#false} is VALID [2022-02-21 04:23:21,033 INFO L290 TraceCheckUtils]: 37: Hoare triple {34411#false} assume !(0 == ~E_4~0); {34411#false} is VALID [2022-02-21 04:23:21,033 INFO L290 TraceCheckUtils]: 38: Hoare triple {34411#false} assume !(0 == ~E_5~0); {34411#false} is VALID [2022-02-21 04:23:21,034 INFO L290 TraceCheckUtils]: 39: Hoare triple {34411#false} assume !(0 == ~E_6~0); {34411#false} is VALID [2022-02-21 04:23:21,034 INFO L290 TraceCheckUtils]: 40: Hoare triple {34411#false} assume !(0 == ~E_7~0); {34411#false} is VALID [2022-02-21 04:23:21,034 INFO L290 TraceCheckUtils]: 41: Hoare triple {34411#false} assume !(0 == ~E_8~0); {34411#false} is VALID [2022-02-21 04:23:21,034 INFO L290 TraceCheckUtils]: 42: Hoare triple {34411#false} assume !(0 == ~E_9~0); {34411#false} is VALID [2022-02-21 04:23:21,034 INFO L290 TraceCheckUtils]: 43: Hoare triple {34411#false} assume 0 == ~E_10~0;~E_10~0 := 1; {34411#false} is VALID [2022-02-21 04:23:21,034 INFO L290 TraceCheckUtils]: 44: Hoare triple {34411#false} assume !(0 == ~E_11~0); {34411#false} is VALID [2022-02-21 04:23:21,034 INFO L290 TraceCheckUtils]: 45: Hoare triple {34411#false} assume !(0 == ~E_12~0); {34411#false} is VALID [2022-02-21 04:23:21,035 INFO L290 TraceCheckUtils]: 46: Hoare triple {34411#false} assume !(0 == ~E_13~0); {34411#false} is VALID [2022-02-21 04:23:21,035 INFO L290 TraceCheckUtils]: 47: Hoare triple {34411#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34411#false} is VALID [2022-02-21 04:23:21,035 INFO L290 TraceCheckUtils]: 48: Hoare triple {34411#false} assume !(1 == ~m_pc~0); {34411#false} is VALID [2022-02-21 04:23:21,035 INFO L290 TraceCheckUtils]: 49: Hoare triple {34411#false} is_master_triggered_~__retres1~0#1 := 0; {34411#false} is VALID [2022-02-21 04:23:21,035 INFO L290 TraceCheckUtils]: 50: Hoare triple {34411#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34411#false} is VALID [2022-02-21 04:23:21,035 INFO L290 TraceCheckUtils]: 51: Hoare triple {34411#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34411#false} is VALID [2022-02-21 04:23:21,035 INFO L290 TraceCheckUtils]: 52: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp~1#1); {34411#false} is VALID [2022-02-21 04:23:21,035 INFO L290 TraceCheckUtils]: 53: Hoare triple {34411#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34411#false} is VALID [2022-02-21 04:23:21,036 INFO L290 TraceCheckUtils]: 54: Hoare triple {34411#false} assume 1 == ~t1_pc~0; {34411#false} is VALID [2022-02-21 04:23:21,036 INFO L290 TraceCheckUtils]: 55: Hoare triple {34411#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34411#false} is VALID [2022-02-21 04:23:21,036 INFO L290 TraceCheckUtils]: 56: Hoare triple {34411#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34411#false} is VALID [2022-02-21 04:23:21,036 INFO L290 TraceCheckUtils]: 57: Hoare triple {34411#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34411#false} is VALID [2022-02-21 04:23:21,036 INFO L290 TraceCheckUtils]: 58: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___0~0#1); {34411#false} is VALID [2022-02-21 04:23:21,036 INFO L290 TraceCheckUtils]: 59: Hoare triple {34411#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34411#false} is VALID [2022-02-21 04:23:21,036 INFO L290 TraceCheckUtils]: 60: Hoare triple {34411#false} assume 1 == ~t2_pc~0; {34411#false} is VALID [2022-02-21 04:23:21,037 INFO L290 TraceCheckUtils]: 61: Hoare triple {34411#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34411#false} is VALID [2022-02-21 04:23:21,037 INFO L290 TraceCheckUtils]: 62: Hoare triple {34411#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34411#false} is VALID [2022-02-21 04:23:21,037 INFO L290 TraceCheckUtils]: 63: Hoare triple {34411#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34411#false} is VALID [2022-02-21 04:23:21,037 INFO L290 TraceCheckUtils]: 64: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___1~0#1); {34411#false} is VALID [2022-02-21 04:23:21,037 INFO L290 TraceCheckUtils]: 65: Hoare triple {34411#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34411#false} is VALID [2022-02-21 04:23:21,037 INFO L290 TraceCheckUtils]: 66: Hoare triple {34411#false} assume !(1 == ~t3_pc~0); {34411#false} is VALID [2022-02-21 04:23:21,037 INFO L290 TraceCheckUtils]: 67: Hoare triple {34411#false} is_transmit3_triggered_~__retres1~3#1 := 0; {34411#false} is VALID [2022-02-21 04:23:21,037 INFO L290 TraceCheckUtils]: 68: Hoare triple {34411#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34411#false} is VALID [2022-02-21 04:23:21,038 INFO L290 TraceCheckUtils]: 69: Hoare triple {34411#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34411#false} is VALID [2022-02-21 04:23:21,038 INFO L290 TraceCheckUtils]: 70: Hoare triple {34411#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34411#false} is VALID [2022-02-21 04:23:21,038 INFO L290 TraceCheckUtils]: 71: Hoare triple {34411#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34411#false} is VALID [2022-02-21 04:23:21,038 INFO L290 TraceCheckUtils]: 72: Hoare triple {34411#false} assume 1 == ~t4_pc~0; {34411#false} is VALID [2022-02-21 04:23:21,038 INFO L290 TraceCheckUtils]: 73: Hoare triple {34411#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34411#false} is VALID [2022-02-21 04:23:21,038 INFO L290 TraceCheckUtils]: 74: Hoare triple {34411#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34411#false} is VALID [2022-02-21 04:23:21,038 INFO L290 TraceCheckUtils]: 75: Hoare triple {34411#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34411#false} is VALID [2022-02-21 04:23:21,039 INFO L290 TraceCheckUtils]: 76: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___3~0#1); {34411#false} is VALID [2022-02-21 04:23:21,039 INFO L290 TraceCheckUtils]: 77: Hoare triple {34411#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34411#false} is VALID [2022-02-21 04:23:21,039 INFO L290 TraceCheckUtils]: 78: Hoare triple {34411#false} assume !(1 == ~t5_pc~0); {34411#false} is VALID [2022-02-21 04:23:21,039 INFO L290 TraceCheckUtils]: 79: Hoare triple {34411#false} is_transmit5_triggered_~__retres1~5#1 := 0; {34411#false} is VALID [2022-02-21 04:23:21,039 INFO L290 TraceCheckUtils]: 80: Hoare triple {34411#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34411#false} is VALID [2022-02-21 04:23:21,039 INFO L290 TraceCheckUtils]: 81: Hoare triple {34411#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34411#false} is VALID [2022-02-21 04:23:21,039 INFO L290 TraceCheckUtils]: 82: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___4~0#1); {34411#false} is VALID [2022-02-21 04:23:21,039 INFO L290 TraceCheckUtils]: 83: Hoare triple {34411#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34411#false} is VALID [2022-02-21 04:23:21,040 INFO L290 TraceCheckUtils]: 84: Hoare triple {34411#false} assume 1 == ~t6_pc~0; {34411#false} is VALID [2022-02-21 04:23:21,040 INFO L290 TraceCheckUtils]: 85: Hoare triple {34411#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {34411#false} is VALID [2022-02-21 04:23:21,040 INFO L290 TraceCheckUtils]: 86: Hoare triple {34411#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34411#false} is VALID [2022-02-21 04:23:21,040 INFO L290 TraceCheckUtils]: 87: Hoare triple {34411#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34411#false} is VALID [2022-02-21 04:23:21,040 INFO L290 TraceCheckUtils]: 88: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___5~0#1); {34411#false} is VALID [2022-02-21 04:23:21,040 INFO L290 TraceCheckUtils]: 89: Hoare triple {34411#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34411#false} is VALID [2022-02-21 04:23:21,040 INFO L290 TraceCheckUtils]: 90: Hoare triple {34411#false} assume !(1 == ~t7_pc~0); {34411#false} is VALID [2022-02-21 04:23:21,040 INFO L290 TraceCheckUtils]: 91: Hoare triple {34411#false} is_transmit7_triggered_~__retres1~7#1 := 0; {34411#false} is VALID [2022-02-21 04:23:21,041 INFO L290 TraceCheckUtils]: 92: Hoare triple {34411#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34411#false} is VALID [2022-02-21 04:23:21,041 INFO L290 TraceCheckUtils]: 93: Hoare triple {34411#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {34411#false} is VALID [2022-02-21 04:23:21,041 INFO L290 TraceCheckUtils]: 94: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___6~0#1); {34411#false} is VALID [2022-02-21 04:23:21,041 INFO L290 TraceCheckUtils]: 95: Hoare triple {34411#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34411#false} is VALID [2022-02-21 04:23:21,041 INFO L290 TraceCheckUtils]: 96: Hoare triple {34411#false} assume 1 == ~t8_pc~0; {34411#false} is VALID [2022-02-21 04:23:21,041 INFO L290 TraceCheckUtils]: 97: Hoare triple {34411#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {34411#false} is VALID [2022-02-21 04:23:21,041 INFO L290 TraceCheckUtils]: 98: Hoare triple {34411#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34411#false} is VALID [2022-02-21 04:23:21,042 INFO L290 TraceCheckUtils]: 99: Hoare triple {34411#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {34411#false} is VALID [2022-02-21 04:23:21,042 INFO L290 TraceCheckUtils]: 100: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___7~0#1); {34411#false} is VALID [2022-02-21 04:23:21,042 INFO L290 TraceCheckUtils]: 101: Hoare triple {34411#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34411#false} is VALID [2022-02-21 04:23:21,042 INFO L290 TraceCheckUtils]: 102: Hoare triple {34411#false} assume 1 == ~t9_pc~0; {34411#false} is VALID [2022-02-21 04:23:21,042 INFO L290 TraceCheckUtils]: 103: Hoare triple {34411#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {34411#false} is VALID [2022-02-21 04:23:21,042 INFO L290 TraceCheckUtils]: 104: Hoare triple {34411#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34411#false} is VALID [2022-02-21 04:23:21,042 INFO L290 TraceCheckUtils]: 105: Hoare triple {34411#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {34411#false} is VALID [2022-02-21 04:23:21,042 INFO L290 TraceCheckUtils]: 106: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___8~0#1); {34411#false} is VALID [2022-02-21 04:23:21,043 INFO L290 TraceCheckUtils]: 107: Hoare triple {34411#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34411#false} is VALID [2022-02-21 04:23:21,043 INFO L290 TraceCheckUtils]: 108: Hoare triple {34411#false} assume !(1 == ~t10_pc~0); {34411#false} is VALID [2022-02-21 04:23:21,043 INFO L290 TraceCheckUtils]: 109: Hoare triple {34411#false} is_transmit10_triggered_~__retres1~10#1 := 0; {34411#false} is VALID [2022-02-21 04:23:21,043 INFO L290 TraceCheckUtils]: 110: Hoare triple {34411#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34411#false} is VALID [2022-02-21 04:23:21,043 INFO L290 TraceCheckUtils]: 111: Hoare triple {34411#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {34411#false} is VALID [2022-02-21 04:23:21,043 INFO L290 TraceCheckUtils]: 112: Hoare triple {34411#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {34411#false} is VALID [2022-02-21 04:23:21,043 INFO L290 TraceCheckUtils]: 113: Hoare triple {34411#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {34411#false} is VALID [2022-02-21 04:23:21,044 INFO L290 TraceCheckUtils]: 114: Hoare triple {34411#false} assume 1 == ~t11_pc~0; {34411#false} is VALID [2022-02-21 04:23:21,044 INFO L290 TraceCheckUtils]: 115: Hoare triple {34411#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {34411#false} is VALID [2022-02-21 04:23:21,044 INFO L290 TraceCheckUtils]: 116: Hoare triple {34411#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {34411#false} is VALID [2022-02-21 04:23:21,044 INFO L290 TraceCheckUtils]: 117: Hoare triple {34411#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {34411#false} is VALID [2022-02-21 04:23:21,044 INFO L290 TraceCheckUtils]: 118: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___10~0#1); {34411#false} is VALID [2022-02-21 04:23:21,044 INFO L290 TraceCheckUtils]: 119: Hoare triple {34411#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {34411#false} is VALID [2022-02-21 04:23:21,044 INFO L290 TraceCheckUtils]: 120: Hoare triple {34411#false} assume !(1 == ~t12_pc~0); {34411#false} is VALID [2022-02-21 04:23:21,044 INFO L290 TraceCheckUtils]: 121: Hoare triple {34411#false} is_transmit12_triggered_~__retres1~12#1 := 0; {34411#false} is VALID [2022-02-21 04:23:21,045 INFO L290 TraceCheckUtils]: 122: Hoare triple {34411#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {34411#false} is VALID [2022-02-21 04:23:21,045 INFO L290 TraceCheckUtils]: 123: Hoare triple {34411#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {34411#false} is VALID [2022-02-21 04:23:21,045 INFO L290 TraceCheckUtils]: 124: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___11~0#1); {34411#false} is VALID [2022-02-21 04:23:21,045 INFO L290 TraceCheckUtils]: 125: Hoare triple {34411#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {34411#false} is VALID [2022-02-21 04:23:21,045 INFO L290 TraceCheckUtils]: 126: Hoare triple {34411#false} assume 1 == ~t13_pc~0; {34411#false} is VALID [2022-02-21 04:23:21,045 INFO L290 TraceCheckUtils]: 127: Hoare triple {34411#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {34411#false} is VALID [2022-02-21 04:23:21,045 INFO L290 TraceCheckUtils]: 128: Hoare triple {34411#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {34411#false} is VALID [2022-02-21 04:23:21,046 INFO L290 TraceCheckUtils]: 129: Hoare triple {34411#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {34411#false} is VALID [2022-02-21 04:23:21,046 INFO L290 TraceCheckUtils]: 130: Hoare triple {34411#false} assume !(0 != activate_threads_~tmp___12~0#1); {34411#false} is VALID [2022-02-21 04:23:21,046 INFO L290 TraceCheckUtils]: 131: Hoare triple {34411#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34411#false} is VALID [2022-02-21 04:23:21,046 INFO L290 TraceCheckUtils]: 132: Hoare triple {34411#false} assume !(1 == ~M_E~0); {34411#false} is VALID [2022-02-21 04:23:21,046 INFO L290 TraceCheckUtils]: 133: Hoare triple {34411#false} assume !(1 == ~T1_E~0); {34411#false} is VALID [2022-02-21 04:23:21,046 INFO L290 TraceCheckUtils]: 134: Hoare triple {34411#false} assume !(1 == ~T2_E~0); {34411#false} is VALID [2022-02-21 04:23:21,046 INFO L290 TraceCheckUtils]: 135: Hoare triple {34411#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,046 INFO L290 TraceCheckUtils]: 136: Hoare triple {34411#false} assume !(1 == ~T4_E~0); {34411#false} is VALID [2022-02-21 04:23:21,047 INFO L290 TraceCheckUtils]: 137: Hoare triple {34411#false} assume !(1 == ~T5_E~0); {34411#false} is VALID [2022-02-21 04:23:21,047 INFO L290 TraceCheckUtils]: 138: Hoare triple {34411#false} assume !(1 == ~T6_E~0); {34411#false} is VALID [2022-02-21 04:23:21,047 INFO L290 TraceCheckUtils]: 139: Hoare triple {34411#false} assume !(1 == ~T7_E~0); {34411#false} is VALID [2022-02-21 04:23:21,047 INFO L290 TraceCheckUtils]: 140: Hoare triple {34411#false} assume !(1 == ~T8_E~0); {34411#false} is VALID [2022-02-21 04:23:21,047 INFO L290 TraceCheckUtils]: 141: Hoare triple {34411#false} assume !(1 == ~T9_E~0); {34411#false} is VALID [2022-02-21 04:23:21,047 INFO L290 TraceCheckUtils]: 142: Hoare triple {34411#false} assume !(1 == ~T10_E~0); {34411#false} is VALID [2022-02-21 04:23:21,047 INFO L290 TraceCheckUtils]: 143: Hoare triple {34411#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,047 INFO L290 TraceCheckUtils]: 144: Hoare triple {34411#false} assume !(1 == ~T12_E~0); {34411#false} is VALID [2022-02-21 04:23:21,048 INFO L290 TraceCheckUtils]: 145: Hoare triple {34411#false} assume !(1 == ~T13_E~0); {34411#false} is VALID [2022-02-21 04:23:21,048 INFO L290 TraceCheckUtils]: 146: Hoare triple {34411#false} assume !(1 == ~E_M~0); {34411#false} is VALID [2022-02-21 04:23:21,048 INFO L290 TraceCheckUtils]: 147: Hoare triple {34411#false} assume !(1 == ~E_1~0); {34411#false} is VALID [2022-02-21 04:23:21,048 INFO L290 TraceCheckUtils]: 148: Hoare triple {34411#false} assume !(1 == ~E_2~0); {34411#false} is VALID [2022-02-21 04:23:21,048 INFO L290 TraceCheckUtils]: 149: Hoare triple {34411#false} assume !(1 == ~E_3~0); {34411#false} is VALID [2022-02-21 04:23:21,048 INFO L290 TraceCheckUtils]: 150: Hoare triple {34411#false} assume !(1 == ~E_4~0); {34411#false} is VALID [2022-02-21 04:23:21,048 INFO L290 TraceCheckUtils]: 151: Hoare triple {34411#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,049 INFO L290 TraceCheckUtils]: 152: Hoare triple {34411#false} assume !(1 == ~E_6~0); {34411#false} is VALID [2022-02-21 04:23:21,049 INFO L290 TraceCheckUtils]: 153: Hoare triple {34411#false} assume !(1 == ~E_7~0); {34411#false} is VALID [2022-02-21 04:23:21,049 INFO L290 TraceCheckUtils]: 154: Hoare triple {34411#false} assume !(1 == ~E_8~0); {34411#false} is VALID [2022-02-21 04:23:21,049 INFO L290 TraceCheckUtils]: 155: Hoare triple {34411#false} assume !(1 == ~E_9~0); {34411#false} is VALID [2022-02-21 04:23:21,049 INFO L290 TraceCheckUtils]: 156: Hoare triple {34411#false} assume !(1 == ~E_10~0); {34411#false} is VALID [2022-02-21 04:23:21,049 INFO L290 TraceCheckUtils]: 157: Hoare triple {34411#false} assume !(1 == ~E_11~0); {34411#false} is VALID [2022-02-21 04:23:21,049 INFO L290 TraceCheckUtils]: 158: Hoare triple {34411#false} assume !(1 == ~E_12~0); {34411#false} is VALID [2022-02-21 04:23:21,049 INFO L290 TraceCheckUtils]: 159: Hoare triple {34411#false} assume 1 == ~E_13~0;~E_13~0 := 2; {34411#false} is VALID [2022-02-21 04:23:21,050 INFO L290 TraceCheckUtils]: 160: Hoare triple {34411#false} assume { :end_inline_reset_delta_events } true; {34411#false} is VALID [2022-02-21 04:23:21,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,050 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,050 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816986630] [2022-02-21 04:23:21,050 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816986630] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,050 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,051 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,051 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776629609] [2022-02-21 04:23:21,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,051 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:21,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:21,052 INFO L85 PathProgramCache]: Analyzing trace with hash -289217245, now seen corresponding path program 1 times [2022-02-21 04:23:21,052 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:21,052 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136571745] [2022-02-21 04:23:21,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:21,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:21,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:21,081 INFO L290 TraceCheckUtils]: 0: Hoare triple {34413#true} assume !false; {34413#true} is VALID [2022-02-21 04:23:21,081 INFO L290 TraceCheckUtils]: 1: Hoare triple {34413#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {34413#true} is VALID [2022-02-21 04:23:21,082 INFO L290 TraceCheckUtils]: 2: Hoare triple {34413#true} assume !false; {34413#true} is VALID [2022-02-21 04:23:21,082 INFO L290 TraceCheckUtils]: 3: Hoare triple {34413#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {34413#true} is VALID [2022-02-21 04:23:21,082 INFO L290 TraceCheckUtils]: 4: Hoare triple {34413#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {34413#true} is VALID [2022-02-21 04:23:21,082 INFO L290 TraceCheckUtils]: 5: Hoare triple {34413#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {34413#true} is VALID [2022-02-21 04:23:21,082 INFO L290 TraceCheckUtils]: 6: Hoare triple {34413#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {34413#true} is VALID [2022-02-21 04:23:21,082 INFO L290 TraceCheckUtils]: 7: Hoare triple {34413#true} assume !(0 != eval_~tmp~0#1); {34413#true} is VALID [2022-02-21 04:23:21,082 INFO L290 TraceCheckUtils]: 8: Hoare triple {34413#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {34413#true} is VALID [2022-02-21 04:23:21,082 INFO L290 TraceCheckUtils]: 9: Hoare triple {34413#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {34413#true} is VALID [2022-02-21 04:23:21,083 INFO L290 TraceCheckUtils]: 10: Hoare triple {34413#true} assume 0 == ~M_E~0;~M_E~0 := 1; {34413#true} is VALID [2022-02-21 04:23:21,083 INFO L290 TraceCheckUtils]: 11: Hoare triple {34413#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {34413#true} is VALID [2022-02-21 04:23:21,083 INFO L290 TraceCheckUtils]: 12: Hoare triple {34413#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {34413#true} is VALID [2022-02-21 04:23:21,083 INFO L290 TraceCheckUtils]: 13: Hoare triple {34413#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34413#true} is VALID [2022-02-21 04:23:21,083 INFO L290 TraceCheckUtils]: 14: Hoare triple {34413#true} assume !(0 == ~T4_E~0); {34413#true} is VALID [2022-02-21 04:23:21,083 INFO L290 TraceCheckUtils]: 15: Hoare triple {34413#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {34413#true} is VALID [2022-02-21 04:23:21,083 INFO L290 TraceCheckUtils]: 16: Hoare triple {34413#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {34413#true} is VALID [2022-02-21 04:23:21,084 INFO L290 TraceCheckUtils]: 17: Hoare triple {34413#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,084 INFO L290 TraceCheckUtils]: 18: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,084 INFO L290 TraceCheckUtils]: 19: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,084 INFO L290 TraceCheckUtils]: 20: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,085 INFO L290 TraceCheckUtils]: 21: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,085 INFO L290 TraceCheckUtils]: 22: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,085 INFO L290 TraceCheckUtils]: 23: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,086 INFO L290 TraceCheckUtils]: 24: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,086 INFO L290 TraceCheckUtils]: 25: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,086 INFO L290 TraceCheckUtils]: 26: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,086 INFO L290 TraceCheckUtils]: 27: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,087 INFO L290 TraceCheckUtils]: 28: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,087 INFO L290 TraceCheckUtils]: 29: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,087 INFO L290 TraceCheckUtils]: 30: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,087 INFO L290 TraceCheckUtils]: 31: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,088 INFO L290 TraceCheckUtils]: 32: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,088 INFO L290 TraceCheckUtils]: 33: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,088 INFO L290 TraceCheckUtils]: 34: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,089 INFO L290 TraceCheckUtils]: 35: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,089 INFO L290 TraceCheckUtils]: 36: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,089 INFO L290 TraceCheckUtils]: 37: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,089 INFO L290 TraceCheckUtils]: 38: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,090 INFO L290 TraceCheckUtils]: 39: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,090 INFO L290 TraceCheckUtils]: 40: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,090 INFO L290 TraceCheckUtils]: 41: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,090 INFO L290 TraceCheckUtils]: 42: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,091 INFO L290 TraceCheckUtils]: 43: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,091 INFO L290 TraceCheckUtils]: 44: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,091 INFO L290 TraceCheckUtils]: 45: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,091 INFO L290 TraceCheckUtils]: 46: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,092 INFO L290 TraceCheckUtils]: 47: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,092 INFO L290 TraceCheckUtils]: 48: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,092 INFO L290 TraceCheckUtils]: 49: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,093 INFO L290 TraceCheckUtils]: 50: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,093 INFO L290 TraceCheckUtils]: 51: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,093 INFO L290 TraceCheckUtils]: 52: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,093 INFO L290 TraceCheckUtils]: 53: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,094 INFO L290 TraceCheckUtils]: 54: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,094 INFO L290 TraceCheckUtils]: 55: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,094 INFO L290 TraceCheckUtils]: 56: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,094 INFO L290 TraceCheckUtils]: 57: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,095 INFO L290 TraceCheckUtils]: 58: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,095 INFO L290 TraceCheckUtils]: 59: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,095 INFO L290 TraceCheckUtils]: 60: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,095 INFO L290 TraceCheckUtils]: 61: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,096 INFO L290 TraceCheckUtils]: 62: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,096 INFO L290 TraceCheckUtils]: 63: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,096 INFO L290 TraceCheckUtils]: 64: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,097 INFO L290 TraceCheckUtils]: 65: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,097 INFO L290 TraceCheckUtils]: 66: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,097 INFO L290 TraceCheckUtils]: 67: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,097 INFO L290 TraceCheckUtils]: 68: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,098 INFO L290 TraceCheckUtils]: 69: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,098 INFO L290 TraceCheckUtils]: 70: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,098 INFO L290 TraceCheckUtils]: 71: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,098 INFO L290 TraceCheckUtils]: 72: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,099 INFO L290 TraceCheckUtils]: 73: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,099 INFO L290 TraceCheckUtils]: 74: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,099 INFO L290 TraceCheckUtils]: 75: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,099 INFO L290 TraceCheckUtils]: 76: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,100 INFO L290 TraceCheckUtils]: 77: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,100 INFO L290 TraceCheckUtils]: 78: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,100 INFO L290 TraceCheckUtils]: 79: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,101 INFO L290 TraceCheckUtils]: 80: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,101 INFO L290 TraceCheckUtils]: 81: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,101 INFO L290 TraceCheckUtils]: 82: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,101 INFO L290 TraceCheckUtils]: 83: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,102 INFO L290 TraceCheckUtils]: 84: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,102 INFO L290 TraceCheckUtils]: 85: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,102 INFO L290 TraceCheckUtils]: 86: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,102 INFO L290 TraceCheckUtils]: 87: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t8_pc~0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,103 INFO L290 TraceCheckUtils]: 88: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,103 INFO L290 TraceCheckUtils]: 89: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,103 INFO L290 TraceCheckUtils]: 90: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,103 INFO L290 TraceCheckUtils]: 91: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,104 INFO L290 TraceCheckUtils]: 92: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,104 INFO L290 TraceCheckUtils]: 93: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t9_pc~0); {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,104 INFO L290 TraceCheckUtils]: 94: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,105 INFO L290 TraceCheckUtils]: 95: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,105 INFO L290 TraceCheckUtils]: 96: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,105 INFO L290 TraceCheckUtils]: 97: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,105 INFO L290 TraceCheckUtils]: 98: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,106 INFO L290 TraceCheckUtils]: 99: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t10_pc~0); {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,106 INFO L290 TraceCheckUtils]: 100: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,106 INFO L290 TraceCheckUtils]: 101: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,106 INFO L290 TraceCheckUtils]: 102: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,107 INFO L290 TraceCheckUtils]: 103: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,107 INFO L290 TraceCheckUtils]: 104: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,107 INFO L290 TraceCheckUtils]: 105: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,107 INFO L290 TraceCheckUtils]: 106: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,108 INFO L290 TraceCheckUtils]: 107: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,108 INFO L290 TraceCheckUtils]: 108: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,108 INFO L290 TraceCheckUtils]: 109: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,109 INFO L290 TraceCheckUtils]: 110: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,109 INFO L290 TraceCheckUtils]: 111: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,109 INFO L290 TraceCheckUtils]: 112: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,109 INFO L290 TraceCheckUtils]: 113: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,110 INFO L290 TraceCheckUtils]: 114: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,110 INFO L290 TraceCheckUtils]: 115: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,110 INFO L290 TraceCheckUtils]: 116: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,110 INFO L290 TraceCheckUtils]: 117: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t13_pc~0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,111 INFO L290 TraceCheckUtils]: 118: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,111 INFO L290 TraceCheckUtils]: 119: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,111 INFO L290 TraceCheckUtils]: 120: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,111 INFO L290 TraceCheckUtils]: 121: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,112 INFO L290 TraceCheckUtils]: 122: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,112 INFO L290 TraceCheckUtils]: 123: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,112 INFO L290 TraceCheckUtils]: 124: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,113 INFO L290 TraceCheckUtils]: 125: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,113 INFO L290 TraceCheckUtils]: 126: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,113 INFO L290 TraceCheckUtils]: 127: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,113 INFO L290 TraceCheckUtils]: 128: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,114 INFO L290 TraceCheckUtils]: 129: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {34415#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:21,114 INFO L290 TraceCheckUtils]: 130: Hoare triple {34415#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {34414#false} is VALID [2022-02-21 04:23:21,114 INFO L290 TraceCheckUtils]: 131: Hoare triple {34414#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,114 INFO L290 TraceCheckUtils]: 132: Hoare triple {34414#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,114 INFO L290 TraceCheckUtils]: 133: Hoare triple {34414#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,114 INFO L290 TraceCheckUtils]: 134: Hoare triple {34414#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,115 INFO L290 TraceCheckUtils]: 135: Hoare triple {34414#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,115 INFO L290 TraceCheckUtils]: 136: Hoare triple {34414#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,115 INFO L290 TraceCheckUtils]: 137: Hoare triple {34414#false} assume 1 == ~E_M~0;~E_M~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,115 INFO L290 TraceCheckUtils]: 138: Hoare triple {34414#false} assume !(1 == ~E_1~0); {34414#false} is VALID [2022-02-21 04:23:21,115 INFO L290 TraceCheckUtils]: 139: Hoare triple {34414#false} assume 1 == ~E_2~0;~E_2~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,115 INFO L290 TraceCheckUtils]: 140: Hoare triple {34414#false} assume 1 == ~E_3~0;~E_3~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,115 INFO L290 TraceCheckUtils]: 141: Hoare triple {34414#false} assume 1 == ~E_4~0;~E_4~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,115 INFO L290 TraceCheckUtils]: 142: Hoare triple {34414#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,116 INFO L290 TraceCheckUtils]: 143: Hoare triple {34414#false} assume 1 == ~E_6~0;~E_6~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,116 INFO L290 TraceCheckUtils]: 144: Hoare triple {34414#false} assume 1 == ~E_7~0;~E_7~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,116 INFO L290 TraceCheckUtils]: 145: Hoare triple {34414#false} assume 1 == ~E_8~0;~E_8~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,116 INFO L290 TraceCheckUtils]: 146: Hoare triple {34414#false} assume !(1 == ~E_9~0); {34414#false} is VALID [2022-02-21 04:23:21,116 INFO L290 TraceCheckUtils]: 147: Hoare triple {34414#false} assume 1 == ~E_10~0;~E_10~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,116 INFO L290 TraceCheckUtils]: 148: Hoare triple {34414#false} assume 1 == ~E_11~0;~E_11~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,116 INFO L290 TraceCheckUtils]: 149: Hoare triple {34414#false} assume 1 == ~E_12~0;~E_12~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,117 INFO L290 TraceCheckUtils]: 150: Hoare triple {34414#false} assume 1 == ~E_13~0;~E_13~0 := 2; {34414#false} is VALID [2022-02-21 04:23:21,117 INFO L290 TraceCheckUtils]: 151: Hoare triple {34414#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {34414#false} is VALID [2022-02-21 04:23:21,117 INFO L290 TraceCheckUtils]: 152: Hoare triple {34414#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {34414#false} is VALID [2022-02-21 04:23:21,117 INFO L290 TraceCheckUtils]: 153: Hoare triple {34414#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {34414#false} is VALID [2022-02-21 04:23:21,117 INFO L290 TraceCheckUtils]: 154: Hoare triple {34414#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {34414#false} is VALID [2022-02-21 04:23:21,117 INFO L290 TraceCheckUtils]: 155: Hoare triple {34414#false} assume !(0 == start_simulation_~tmp~3#1); {34414#false} is VALID [2022-02-21 04:23:21,117 INFO L290 TraceCheckUtils]: 156: Hoare triple {34414#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {34414#false} is VALID [2022-02-21 04:23:21,117 INFO L290 TraceCheckUtils]: 157: Hoare triple {34414#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {34414#false} is VALID [2022-02-21 04:23:21,118 INFO L290 TraceCheckUtils]: 158: Hoare triple {34414#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {34414#false} is VALID [2022-02-21 04:23:21,118 INFO L290 TraceCheckUtils]: 159: Hoare triple {34414#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {34414#false} is VALID [2022-02-21 04:23:21,118 INFO L290 TraceCheckUtils]: 160: Hoare triple {34414#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {34414#false} is VALID [2022-02-21 04:23:21,118 INFO L290 TraceCheckUtils]: 161: Hoare triple {34414#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {34414#false} is VALID [2022-02-21 04:23:21,118 INFO L290 TraceCheckUtils]: 162: Hoare triple {34414#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {34414#false} is VALID [2022-02-21 04:23:21,118 INFO L290 TraceCheckUtils]: 163: Hoare triple {34414#false} assume !(0 != start_simulation_~tmp___0~1#1); {34414#false} is VALID [2022-02-21 04:23:21,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,119 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,119 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136571745] [2022-02-21 04:23:21,119 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136571745] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,119 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,119 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,120 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373992512] [2022-02-21 04:23:21,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,120 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:21,120 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:21,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:21,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:21,121 INFO L87 Difference]: Start difference. First operand 2021 states and 2989 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:22,408 INFO L93 Difference]: Finished difference Result 2021 states and 2988 transitions. [2022-02-21 04:23:22,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:22,408 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,528 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:22,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2988 transitions. [2022-02-21 04:23:22,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:22,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2988 transitions. [2022-02-21 04:23:22,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:22,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:22,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2988 transitions. [2022-02-21 04:23:22,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:22,699 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2022-02-21 04:23:22,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2988 transitions. [2022-02-21 04:23:22,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:22,714 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:22,716 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2988 transitions. Second operand has 2021 states, 2021 states have (on average 1.4784760019792182) internal successors, (2988), 2020 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,718 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2988 transitions. Second operand has 2021 states, 2021 states have (on average 1.4784760019792182) internal successors, (2988), 2020 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,720 INFO L87 Difference]: Start difference. First operand 2021 states and 2988 transitions. Second operand has 2021 states, 2021 states have (on average 1.4784760019792182) internal successors, (2988), 2020 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:22,802 INFO L93 Difference]: Finished difference Result 2021 states and 2988 transitions. [2022-02-21 04:23:22,803 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2988 transitions. [2022-02-21 04:23:22,804 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:22,804 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:22,806 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.4784760019792182) internal successors, (2988), 2020 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2988 transitions. [2022-02-21 04:23:22,808 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.4784760019792182) internal successors, (2988), 2020 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2988 transitions. [2022-02-21 04:23:22,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:22,891 INFO L93 Difference]: Finished difference Result 2021 states and 2988 transitions. [2022-02-21 04:23:22,891 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2988 transitions. [2022-02-21 04:23:22,892 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:22,892 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:22,893 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:22,893 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:22,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4784760019792182) internal successors, (2988), 2020 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2988 transitions. [2022-02-21 04:23:22,976 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2022-02-21 04:23:22,976 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2022-02-21 04:23:22,977 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:23:22,977 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2988 transitions. [2022-02-21 04:23:22,980 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:22,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:22,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:22,982 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:22,983 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:22,983 INFO L791 eck$LassoCheckResult]: Stem: 37313#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37314#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37045#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37046#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38436#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 38437#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37232#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37233#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37267#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38104#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 38105#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 38217#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 38218#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 37051#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37052#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 38254#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37576#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37577#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38158#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38424#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 38314#L1286-2 assume !(0 == ~T1_E~0); 36960#L1291-1 assume !(0 == ~T2_E~0); 36961#L1296-1 assume !(0 == ~T3_E~0); 37666#L1301-1 assume !(0 == ~T4_E~0); 37667#L1306-1 assume !(0 == ~T5_E~0); 38167#L1311-1 assume !(0 == ~T6_E~0); 36920#L1316-1 assume !(0 == ~T7_E~0); 36921#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37686#L1326-1 assume !(0 == ~T9_E~0); 36735#L1331-1 assume !(0 == ~T10_E~0); 36441#L1336-1 assume !(0 == ~T11_E~0); 36442#L1341-1 assume !(0 == ~T12_E~0); 36493#L1346-1 assume !(0 == ~T13_E~0); 36494#L1351-1 assume !(0 == ~E_M~0); 36867#L1356-1 assume !(0 == ~E_1~0); 36868#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 38387#L1366-1 assume !(0 == ~E_3~0); 36913#L1371-1 assume !(0 == ~E_4~0); 36914#L1376-1 assume !(0 == ~E_5~0); 37727#L1381-1 assume !(0 == ~E_6~0); 37728#L1386-1 assume !(0 == ~E_7~0); 38415#L1391-1 assume !(0 == ~E_8~0); 38428#L1396-1 assume !(0 == ~E_9~0); 37610#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 37611#L1406-1 assume !(0 == ~E_11~0); 37913#L1411-1 assume !(0 == ~E_12~0); 37914#L1416-1 assume !(0 == ~E_13~0); 37534#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37372#L635 assume !(1 == ~m_pc~0); 36511#L635-2 is_master_triggered_~__retres1~0#1 := 0; 36512#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36862#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37498#L1598 assume !(0 != activate_threads_~tmp~1#1); 36690#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36691#L654 assume 1 == ~t1_pc~0; 37396#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37397#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38412#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37478#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 37479#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36738#L673 assume 1 == ~t2_pc~0; 36739#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37883#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37884#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38442#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 38449#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37557#L692 assume !(1 == ~t3_pc~0); 37374#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37375#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37234#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37202#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37203#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36763#L711 assume 1 == ~t4_pc~0; 36764#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37247#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37704#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36466#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 36467#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38435#L730 assume !(1 == ~t5_pc~0); 37817#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36645#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36646#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36773#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 36774#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37116#L749 assume 1 == ~t6_pc~0; 36890#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36650#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37082#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37083#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 37305#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36446#L768 assume !(1 == ~t7_pc~0); 36447#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37751#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36683#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36684#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 37770#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36922#L787 assume 1 == ~t8_pc~0; 36923#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38118#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38282#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38283#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 36491#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36492#L806 assume 1 == ~t9_pc~0; 38129#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36526#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36527#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36775#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 36776#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38112#L825 assume !(1 == ~t10_pc~0); 38113#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37718#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37719#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36863#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36864#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37447#L844 assume 1 == ~t11_pc~0; 37137#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37138#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37504#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37505#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 38100#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38101#L863 assume !(1 == ~t12_pc~0); 36626#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36625#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36853#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38192#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 38193#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37571#L882 assume 1 == ~t13_pc~0; 37572#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37856#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38357#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38160#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 37843#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37844#L1434 assume !(1 == ~M_E~0); 38365#L1434-2 assume !(1 == ~T1_E~0); 38441#L1439-1 assume !(1 == ~T2_E~0); 36756#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36757#L1449-1 assume !(1 == ~T4_E~0); 37199#L1454-1 assume !(1 == ~T5_E~0); 37200#L1459-1 assume !(1 == ~T6_E~0); 37771#L1464-1 assume !(1 == ~T7_E~0); 37772#L1469-1 assume !(1 == ~T8_E~0); 37857#L1474-1 assume !(1 == ~T9_E~0); 37535#L1479-1 assume !(1 == ~T10_E~0); 37536#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37779#L1489-1 assume !(1 == ~T12_E~0); 37413#L1494-1 assume !(1 == ~T13_E~0); 37414#L1499-1 assume !(1 == ~E_M~0); 37595#L1504-1 assume !(1 == ~E_1~0); 37596#L1509-1 assume !(1 == ~E_2~0); 38209#L1514-1 assume !(1 == ~E_3~0); 37894#L1519-1 assume !(1 == ~E_4~0); 37895#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38399#L1529-1 assume !(1 == ~E_6~0); 38400#L1534-1 assume !(1 == ~E_7~0); 36546#L1539-1 assume !(1 == ~E_8~0); 36547#L1544-1 assume !(1 == ~E_9~0); 36977#L1549-1 assume !(1 == ~E_10~0); 38377#L1554-1 assume !(1 == ~E_11~0); 38375#L1559-1 assume !(1 == ~E_12~0); 38237#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38238#L1569-1 assume { :end_inline_reset_delta_events } true; 38393#L1935-2 [2022-02-21 04:23:22,984 INFO L793 eck$LassoCheckResult]: Loop: 38393#L1935-2 assume !false; 36555#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36556#L1261 assume !false; 37783#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37784#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36686#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36856#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36857#L1074 assume !(0 != eval_~tmp~0#1); 37214#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37812#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38213#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38269#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37988#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37989#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38425#L1301-3 assume !(0 == ~T4_E~0); 38383#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37491#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36790#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36791#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36896#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37632#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37897#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37898#L1341-3 assume !(0 == ~T12_E~0); 37192#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37183#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37127#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37128#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37708#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36481#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36482#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38224#L1381-3 assume !(0 == ~E_6~0); 38073#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38074#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38255#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38256#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36861#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36692#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36693#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37320#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36570#L635-45 assume 1 == ~m_pc~0; 36571#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37365#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37845#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38099#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36879#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36880#L654-45 assume 1 == ~t1_pc~0; 37700#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38048#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36533#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36534#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36559#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37386#L673-45 assume !(1 == ~t2_pc~0); 37387#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 37711#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37712#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38337#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 38157#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37004#L692-45 assume !(1 == ~t3_pc~0); 36730#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 36731#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37775#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37058#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37059#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37371#L711-45 assume 1 == ~t4_pc~0; 37495#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37496#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37348#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37349#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37752#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36903#L730-45 assume 1 == ~t5_pc~0; 36741#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36742#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37151#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37152#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37903#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36714#L749-45 assume !(1 == ~t6_pc~0); 36715#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 38115#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37878#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37879#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38030#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37030#L768-45 assume 1 == ~t7_pc~0; 37031#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37170#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37974#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37975#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38014#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38015#L787-45 assume 1 == ~t8_pc~0; 38183#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37176#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37177#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37593#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37594#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37902#L806-45 assume 1 == ~t9_pc~0; 38378#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36590#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37415#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37243#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37155#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37156#L825-45 assume 1 == ~t10_pc~0; 37767#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37680#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37785#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37786#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37938#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36798#L844-45 assume 1 == ~t11_pc~0; 36800#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37321#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37322#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37338#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 37749#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36838#L863-45 assume 1 == ~t12_pc~0; 36839#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36439#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36440#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 36955#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36956#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37755#L882-45 assume !(1 == ~t13_pc~0); 37285#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 36458#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 36459#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37067#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38246#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37862#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37863#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38047#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36752#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36753#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36915#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37852#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37853#L1464-3 assume !(1 == ~T7_E~0); 38299#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38226#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38227#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38301#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37493#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37494#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38154#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37789#L1504-3 assume !(1 == ~E_1~0); 37790#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38235#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38275#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37416#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37417#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38322#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37717#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37171#L1544-3 assume !(1 == ~E_9~0); 37172#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37687#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36803#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 36804#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37953#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37954#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36688#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37253#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37924#L1954 assume !(0 == start_simulation_~tmp~3#1); 37926#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38176#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36971#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38012#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38142#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38143#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38233#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38295#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 38393#L1935-2 [2022-02-21 04:23:22,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:22,984 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2022-02-21 04:23:22,984 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:22,984 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74382205] [2022-02-21 04:23:22,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:22,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:22,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:23,007 INFO L290 TraceCheckUtils]: 0: Hoare triple {42503#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {42503#true} is VALID [2022-02-21 04:23:23,007 INFO L290 TraceCheckUtils]: 1: Hoare triple {42503#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {42505#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:23,008 INFO L290 TraceCheckUtils]: 2: Hoare triple {42505#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {42505#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:23,008 INFO L290 TraceCheckUtils]: 3: Hoare triple {42505#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {42505#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:23,008 INFO L290 TraceCheckUtils]: 4: Hoare triple {42505#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {42505#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:23,008 INFO L290 TraceCheckUtils]: 5: Hoare triple {42505#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {42505#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:23,009 INFO L290 TraceCheckUtils]: 6: Hoare triple {42505#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {42505#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:23,009 INFO L290 TraceCheckUtils]: 7: Hoare triple {42505#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {42505#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:23,009 INFO L290 TraceCheckUtils]: 8: Hoare triple {42505#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {42505#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:23,009 INFO L290 TraceCheckUtils]: 9: Hoare triple {42505#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,010 INFO L290 TraceCheckUtils]: 10: Hoare triple {42504#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,010 INFO L290 TraceCheckUtils]: 11: Hoare triple {42504#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,010 INFO L290 TraceCheckUtils]: 12: Hoare triple {42504#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,010 INFO L290 TraceCheckUtils]: 13: Hoare triple {42504#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {42504#false} is VALID [2022-02-21 04:23:23,010 INFO L290 TraceCheckUtils]: 14: Hoare triple {42504#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,010 INFO L290 TraceCheckUtils]: 15: Hoare triple {42504#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,010 INFO L290 TraceCheckUtils]: 16: Hoare triple {42504#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,011 INFO L290 TraceCheckUtils]: 17: Hoare triple {42504#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,011 INFO L290 TraceCheckUtils]: 18: Hoare triple {42504#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {42504#false} is VALID [2022-02-21 04:23:23,011 INFO L290 TraceCheckUtils]: 19: Hoare triple {42504#false} assume 0 == ~M_E~0;~M_E~0 := 1; {42504#false} is VALID [2022-02-21 04:23:23,011 INFO L290 TraceCheckUtils]: 20: Hoare triple {42504#false} assume !(0 == ~T1_E~0); {42504#false} is VALID [2022-02-21 04:23:23,011 INFO L290 TraceCheckUtils]: 21: Hoare triple {42504#false} assume !(0 == ~T2_E~0); {42504#false} is VALID [2022-02-21 04:23:23,011 INFO L290 TraceCheckUtils]: 22: Hoare triple {42504#false} assume !(0 == ~T3_E~0); {42504#false} is VALID [2022-02-21 04:23:23,011 INFO L290 TraceCheckUtils]: 23: Hoare triple {42504#false} assume !(0 == ~T4_E~0); {42504#false} is VALID [2022-02-21 04:23:23,011 INFO L290 TraceCheckUtils]: 24: Hoare triple {42504#false} assume !(0 == ~T5_E~0); {42504#false} is VALID [2022-02-21 04:23:23,012 INFO L290 TraceCheckUtils]: 25: Hoare triple {42504#false} assume !(0 == ~T6_E~0); {42504#false} is VALID [2022-02-21 04:23:23,012 INFO L290 TraceCheckUtils]: 26: Hoare triple {42504#false} assume !(0 == ~T7_E~0); {42504#false} is VALID [2022-02-21 04:23:23,012 INFO L290 TraceCheckUtils]: 27: Hoare triple {42504#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {42504#false} is VALID [2022-02-21 04:23:23,012 INFO L290 TraceCheckUtils]: 28: Hoare triple {42504#false} assume !(0 == ~T9_E~0); {42504#false} is VALID [2022-02-21 04:23:23,012 INFO L290 TraceCheckUtils]: 29: Hoare triple {42504#false} assume !(0 == ~T10_E~0); {42504#false} is VALID [2022-02-21 04:23:23,012 INFO L290 TraceCheckUtils]: 30: Hoare triple {42504#false} assume !(0 == ~T11_E~0); {42504#false} is VALID [2022-02-21 04:23:23,012 INFO L290 TraceCheckUtils]: 31: Hoare triple {42504#false} assume !(0 == ~T12_E~0); {42504#false} is VALID [2022-02-21 04:23:23,013 INFO L290 TraceCheckUtils]: 32: Hoare triple {42504#false} assume !(0 == ~T13_E~0); {42504#false} is VALID [2022-02-21 04:23:23,013 INFO L290 TraceCheckUtils]: 33: Hoare triple {42504#false} assume !(0 == ~E_M~0); {42504#false} is VALID [2022-02-21 04:23:23,013 INFO L290 TraceCheckUtils]: 34: Hoare triple {42504#false} assume !(0 == ~E_1~0); {42504#false} is VALID [2022-02-21 04:23:23,013 INFO L290 TraceCheckUtils]: 35: Hoare triple {42504#false} assume 0 == ~E_2~0;~E_2~0 := 1; {42504#false} is VALID [2022-02-21 04:23:23,013 INFO L290 TraceCheckUtils]: 36: Hoare triple {42504#false} assume !(0 == ~E_3~0); {42504#false} is VALID [2022-02-21 04:23:23,013 INFO L290 TraceCheckUtils]: 37: Hoare triple {42504#false} assume !(0 == ~E_4~0); {42504#false} is VALID [2022-02-21 04:23:23,013 INFO L290 TraceCheckUtils]: 38: Hoare triple {42504#false} assume !(0 == ~E_5~0); {42504#false} is VALID [2022-02-21 04:23:23,013 INFO L290 TraceCheckUtils]: 39: Hoare triple {42504#false} assume !(0 == ~E_6~0); {42504#false} is VALID [2022-02-21 04:23:23,014 INFO L290 TraceCheckUtils]: 40: Hoare triple {42504#false} assume !(0 == ~E_7~0); {42504#false} is VALID [2022-02-21 04:23:23,014 INFO L290 TraceCheckUtils]: 41: Hoare triple {42504#false} assume !(0 == ~E_8~0); {42504#false} is VALID [2022-02-21 04:23:23,014 INFO L290 TraceCheckUtils]: 42: Hoare triple {42504#false} assume !(0 == ~E_9~0); {42504#false} is VALID [2022-02-21 04:23:23,014 INFO L290 TraceCheckUtils]: 43: Hoare triple {42504#false} assume 0 == ~E_10~0;~E_10~0 := 1; {42504#false} is VALID [2022-02-21 04:23:23,014 INFO L290 TraceCheckUtils]: 44: Hoare triple {42504#false} assume !(0 == ~E_11~0); {42504#false} is VALID [2022-02-21 04:23:23,014 INFO L290 TraceCheckUtils]: 45: Hoare triple {42504#false} assume !(0 == ~E_12~0); {42504#false} is VALID [2022-02-21 04:23:23,014 INFO L290 TraceCheckUtils]: 46: Hoare triple {42504#false} assume !(0 == ~E_13~0); {42504#false} is VALID [2022-02-21 04:23:23,015 INFO L290 TraceCheckUtils]: 47: Hoare triple {42504#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {42504#false} is VALID [2022-02-21 04:23:23,015 INFO L290 TraceCheckUtils]: 48: Hoare triple {42504#false} assume !(1 == ~m_pc~0); {42504#false} is VALID [2022-02-21 04:23:23,015 INFO L290 TraceCheckUtils]: 49: Hoare triple {42504#false} is_master_triggered_~__retres1~0#1 := 0; {42504#false} is VALID [2022-02-21 04:23:23,015 INFO L290 TraceCheckUtils]: 50: Hoare triple {42504#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {42504#false} is VALID [2022-02-21 04:23:23,015 INFO L290 TraceCheckUtils]: 51: Hoare triple {42504#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {42504#false} is VALID [2022-02-21 04:23:23,015 INFO L290 TraceCheckUtils]: 52: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp~1#1); {42504#false} is VALID [2022-02-21 04:23:23,015 INFO L290 TraceCheckUtils]: 53: Hoare triple {42504#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {42504#false} is VALID [2022-02-21 04:23:23,015 INFO L290 TraceCheckUtils]: 54: Hoare triple {42504#false} assume 1 == ~t1_pc~0; {42504#false} is VALID [2022-02-21 04:23:23,016 INFO L290 TraceCheckUtils]: 55: Hoare triple {42504#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {42504#false} is VALID [2022-02-21 04:23:23,016 INFO L290 TraceCheckUtils]: 56: Hoare triple {42504#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {42504#false} is VALID [2022-02-21 04:23:23,016 INFO L290 TraceCheckUtils]: 57: Hoare triple {42504#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {42504#false} is VALID [2022-02-21 04:23:23,016 INFO L290 TraceCheckUtils]: 58: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___0~0#1); {42504#false} is VALID [2022-02-21 04:23:23,016 INFO L290 TraceCheckUtils]: 59: Hoare triple {42504#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {42504#false} is VALID [2022-02-21 04:23:23,016 INFO L290 TraceCheckUtils]: 60: Hoare triple {42504#false} assume 1 == ~t2_pc~0; {42504#false} is VALID [2022-02-21 04:23:23,016 INFO L290 TraceCheckUtils]: 61: Hoare triple {42504#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {42504#false} is VALID [2022-02-21 04:23:23,017 INFO L290 TraceCheckUtils]: 62: Hoare triple {42504#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {42504#false} is VALID [2022-02-21 04:23:23,017 INFO L290 TraceCheckUtils]: 63: Hoare triple {42504#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {42504#false} is VALID [2022-02-21 04:23:23,017 INFO L290 TraceCheckUtils]: 64: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___1~0#1); {42504#false} is VALID [2022-02-21 04:23:23,017 INFO L290 TraceCheckUtils]: 65: Hoare triple {42504#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {42504#false} is VALID [2022-02-21 04:23:23,017 INFO L290 TraceCheckUtils]: 66: Hoare triple {42504#false} assume !(1 == ~t3_pc~0); {42504#false} is VALID [2022-02-21 04:23:23,017 INFO L290 TraceCheckUtils]: 67: Hoare triple {42504#false} is_transmit3_triggered_~__retres1~3#1 := 0; {42504#false} is VALID [2022-02-21 04:23:23,017 INFO L290 TraceCheckUtils]: 68: Hoare triple {42504#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {42504#false} is VALID [2022-02-21 04:23:23,018 INFO L290 TraceCheckUtils]: 69: Hoare triple {42504#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {42504#false} is VALID [2022-02-21 04:23:23,018 INFO L290 TraceCheckUtils]: 70: Hoare triple {42504#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {42504#false} is VALID [2022-02-21 04:23:23,018 INFO L290 TraceCheckUtils]: 71: Hoare triple {42504#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {42504#false} is VALID [2022-02-21 04:23:23,018 INFO L290 TraceCheckUtils]: 72: Hoare triple {42504#false} assume 1 == ~t4_pc~0; {42504#false} is VALID [2022-02-21 04:23:23,018 INFO L290 TraceCheckUtils]: 73: Hoare triple {42504#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {42504#false} is VALID [2022-02-21 04:23:23,018 INFO L290 TraceCheckUtils]: 74: Hoare triple {42504#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {42504#false} is VALID [2022-02-21 04:23:23,018 INFO L290 TraceCheckUtils]: 75: Hoare triple {42504#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {42504#false} is VALID [2022-02-21 04:23:23,018 INFO L290 TraceCheckUtils]: 76: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___3~0#1); {42504#false} is VALID [2022-02-21 04:23:23,019 INFO L290 TraceCheckUtils]: 77: Hoare triple {42504#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {42504#false} is VALID [2022-02-21 04:23:23,019 INFO L290 TraceCheckUtils]: 78: Hoare triple {42504#false} assume !(1 == ~t5_pc~0); {42504#false} is VALID [2022-02-21 04:23:23,019 INFO L290 TraceCheckUtils]: 79: Hoare triple {42504#false} is_transmit5_triggered_~__retres1~5#1 := 0; {42504#false} is VALID [2022-02-21 04:23:23,019 INFO L290 TraceCheckUtils]: 80: Hoare triple {42504#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {42504#false} is VALID [2022-02-21 04:23:23,019 INFO L290 TraceCheckUtils]: 81: Hoare triple {42504#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {42504#false} is VALID [2022-02-21 04:23:23,019 INFO L290 TraceCheckUtils]: 82: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___4~0#1); {42504#false} is VALID [2022-02-21 04:23:23,019 INFO L290 TraceCheckUtils]: 83: Hoare triple {42504#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {42504#false} is VALID [2022-02-21 04:23:23,020 INFO L290 TraceCheckUtils]: 84: Hoare triple {42504#false} assume 1 == ~t6_pc~0; {42504#false} is VALID [2022-02-21 04:23:23,020 INFO L290 TraceCheckUtils]: 85: Hoare triple {42504#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {42504#false} is VALID [2022-02-21 04:23:23,020 INFO L290 TraceCheckUtils]: 86: Hoare triple {42504#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {42504#false} is VALID [2022-02-21 04:23:23,020 INFO L290 TraceCheckUtils]: 87: Hoare triple {42504#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {42504#false} is VALID [2022-02-21 04:23:23,020 INFO L290 TraceCheckUtils]: 88: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___5~0#1); {42504#false} is VALID [2022-02-21 04:23:23,020 INFO L290 TraceCheckUtils]: 89: Hoare triple {42504#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {42504#false} is VALID [2022-02-21 04:23:23,020 INFO L290 TraceCheckUtils]: 90: Hoare triple {42504#false} assume !(1 == ~t7_pc~0); {42504#false} is VALID [2022-02-21 04:23:23,020 INFO L290 TraceCheckUtils]: 91: Hoare triple {42504#false} is_transmit7_triggered_~__retres1~7#1 := 0; {42504#false} is VALID [2022-02-21 04:23:23,021 INFO L290 TraceCheckUtils]: 92: Hoare triple {42504#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {42504#false} is VALID [2022-02-21 04:23:23,021 INFO L290 TraceCheckUtils]: 93: Hoare triple {42504#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {42504#false} is VALID [2022-02-21 04:23:23,021 INFO L290 TraceCheckUtils]: 94: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___6~0#1); {42504#false} is VALID [2022-02-21 04:23:23,021 INFO L290 TraceCheckUtils]: 95: Hoare triple {42504#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {42504#false} is VALID [2022-02-21 04:23:23,021 INFO L290 TraceCheckUtils]: 96: Hoare triple {42504#false} assume 1 == ~t8_pc~0; {42504#false} is VALID [2022-02-21 04:23:23,021 INFO L290 TraceCheckUtils]: 97: Hoare triple {42504#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {42504#false} is VALID [2022-02-21 04:23:23,021 INFO L290 TraceCheckUtils]: 98: Hoare triple {42504#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {42504#false} is VALID [2022-02-21 04:23:23,022 INFO L290 TraceCheckUtils]: 99: Hoare triple {42504#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {42504#false} is VALID [2022-02-21 04:23:23,022 INFO L290 TraceCheckUtils]: 100: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___7~0#1); {42504#false} is VALID [2022-02-21 04:23:23,022 INFO L290 TraceCheckUtils]: 101: Hoare triple {42504#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {42504#false} is VALID [2022-02-21 04:23:23,022 INFO L290 TraceCheckUtils]: 102: Hoare triple {42504#false} assume 1 == ~t9_pc~0; {42504#false} is VALID [2022-02-21 04:23:23,022 INFO L290 TraceCheckUtils]: 103: Hoare triple {42504#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {42504#false} is VALID [2022-02-21 04:23:23,022 INFO L290 TraceCheckUtils]: 104: Hoare triple {42504#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {42504#false} is VALID [2022-02-21 04:23:23,022 INFO L290 TraceCheckUtils]: 105: Hoare triple {42504#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {42504#false} is VALID [2022-02-21 04:23:23,022 INFO L290 TraceCheckUtils]: 106: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___8~0#1); {42504#false} is VALID [2022-02-21 04:23:23,023 INFO L290 TraceCheckUtils]: 107: Hoare triple {42504#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {42504#false} is VALID [2022-02-21 04:23:23,023 INFO L290 TraceCheckUtils]: 108: Hoare triple {42504#false} assume !(1 == ~t10_pc~0); {42504#false} is VALID [2022-02-21 04:23:23,023 INFO L290 TraceCheckUtils]: 109: Hoare triple {42504#false} is_transmit10_triggered_~__retres1~10#1 := 0; {42504#false} is VALID [2022-02-21 04:23:23,023 INFO L290 TraceCheckUtils]: 110: Hoare triple {42504#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {42504#false} is VALID [2022-02-21 04:23:23,023 INFO L290 TraceCheckUtils]: 111: Hoare triple {42504#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {42504#false} is VALID [2022-02-21 04:23:23,023 INFO L290 TraceCheckUtils]: 112: Hoare triple {42504#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {42504#false} is VALID [2022-02-21 04:23:23,023 INFO L290 TraceCheckUtils]: 113: Hoare triple {42504#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {42504#false} is VALID [2022-02-21 04:23:23,024 INFO L290 TraceCheckUtils]: 114: Hoare triple {42504#false} assume 1 == ~t11_pc~0; {42504#false} is VALID [2022-02-21 04:23:23,024 INFO L290 TraceCheckUtils]: 115: Hoare triple {42504#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {42504#false} is VALID [2022-02-21 04:23:23,024 INFO L290 TraceCheckUtils]: 116: Hoare triple {42504#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {42504#false} is VALID [2022-02-21 04:23:23,024 INFO L290 TraceCheckUtils]: 117: Hoare triple {42504#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {42504#false} is VALID [2022-02-21 04:23:23,024 INFO L290 TraceCheckUtils]: 118: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___10~0#1); {42504#false} is VALID [2022-02-21 04:23:23,024 INFO L290 TraceCheckUtils]: 119: Hoare triple {42504#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {42504#false} is VALID [2022-02-21 04:23:23,024 INFO L290 TraceCheckUtils]: 120: Hoare triple {42504#false} assume !(1 == ~t12_pc~0); {42504#false} is VALID [2022-02-21 04:23:23,024 INFO L290 TraceCheckUtils]: 121: Hoare triple {42504#false} is_transmit12_triggered_~__retres1~12#1 := 0; {42504#false} is VALID [2022-02-21 04:23:23,025 INFO L290 TraceCheckUtils]: 122: Hoare triple {42504#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {42504#false} is VALID [2022-02-21 04:23:23,025 INFO L290 TraceCheckUtils]: 123: Hoare triple {42504#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {42504#false} is VALID [2022-02-21 04:23:23,025 INFO L290 TraceCheckUtils]: 124: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___11~0#1); {42504#false} is VALID [2022-02-21 04:23:23,025 INFO L290 TraceCheckUtils]: 125: Hoare triple {42504#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {42504#false} is VALID [2022-02-21 04:23:23,025 INFO L290 TraceCheckUtils]: 126: Hoare triple {42504#false} assume 1 == ~t13_pc~0; {42504#false} is VALID [2022-02-21 04:23:23,025 INFO L290 TraceCheckUtils]: 127: Hoare triple {42504#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {42504#false} is VALID [2022-02-21 04:23:23,025 INFO L290 TraceCheckUtils]: 128: Hoare triple {42504#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {42504#false} is VALID [2022-02-21 04:23:23,026 INFO L290 TraceCheckUtils]: 129: Hoare triple {42504#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {42504#false} is VALID [2022-02-21 04:23:23,026 INFO L290 TraceCheckUtils]: 130: Hoare triple {42504#false} assume !(0 != activate_threads_~tmp___12~0#1); {42504#false} is VALID [2022-02-21 04:23:23,026 INFO L290 TraceCheckUtils]: 131: Hoare triple {42504#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {42504#false} is VALID [2022-02-21 04:23:23,026 INFO L290 TraceCheckUtils]: 132: Hoare triple {42504#false} assume !(1 == ~M_E~0); {42504#false} is VALID [2022-02-21 04:23:23,026 INFO L290 TraceCheckUtils]: 133: Hoare triple {42504#false} assume !(1 == ~T1_E~0); {42504#false} is VALID [2022-02-21 04:23:23,026 INFO L290 TraceCheckUtils]: 134: Hoare triple {42504#false} assume !(1 == ~T2_E~0); {42504#false} is VALID [2022-02-21 04:23:23,026 INFO L290 TraceCheckUtils]: 135: Hoare triple {42504#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,026 INFO L290 TraceCheckUtils]: 136: Hoare triple {42504#false} assume !(1 == ~T4_E~0); {42504#false} is VALID [2022-02-21 04:23:23,027 INFO L290 TraceCheckUtils]: 137: Hoare triple {42504#false} assume !(1 == ~T5_E~0); {42504#false} is VALID [2022-02-21 04:23:23,027 INFO L290 TraceCheckUtils]: 138: Hoare triple {42504#false} assume !(1 == ~T6_E~0); {42504#false} is VALID [2022-02-21 04:23:23,027 INFO L290 TraceCheckUtils]: 139: Hoare triple {42504#false} assume !(1 == ~T7_E~0); {42504#false} is VALID [2022-02-21 04:23:23,027 INFO L290 TraceCheckUtils]: 140: Hoare triple {42504#false} assume !(1 == ~T8_E~0); {42504#false} is VALID [2022-02-21 04:23:23,027 INFO L290 TraceCheckUtils]: 141: Hoare triple {42504#false} assume !(1 == ~T9_E~0); {42504#false} is VALID [2022-02-21 04:23:23,027 INFO L290 TraceCheckUtils]: 142: Hoare triple {42504#false} assume !(1 == ~T10_E~0); {42504#false} is VALID [2022-02-21 04:23:23,027 INFO L290 TraceCheckUtils]: 143: Hoare triple {42504#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,028 INFO L290 TraceCheckUtils]: 144: Hoare triple {42504#false} assume !(1 == ~T12_E~0); {42504#false} is VALID [2022-02-21 04:23:23,028 INFO L290 TraceCheckUtils]: 145: Hoare triple {42504#false} assume !(1 == ~T13_E~0); {42504#false} is VALID [2022-02-21 04:23:23,028 INFO L290 TraceCheckUtils]: 146: Hoare triple {42504#false} assume !(1 == ~E_M~0); {42504#false} is VALID [2022-02-21 04:23:23,028 INFO L290 TraceCheckUtils]: 147: Hoare triple {42504#false} assume !(1 == ~E_1~0); {42504#false} is VALID [2022-02-21 04:23:23,028 INFO L290 TraceCheckUtils]: 148: Hoare triple {42504#false} assume !(1 == ~E_2~0); {42504#false} is VALID [2022-02-21 04:23:23,028 INFO L290 TraceCheckUtils]: 149: Hoare triple {42504#false} assume !(1 == ~E_3~0); {42504#false} is VALID [2022-02-21 04:23:23,028 INFO L290 TraceCheckUtils]: 150: Hoare triple {42504#false} assume !(1 == ~E_4~0); {42504#false} is VALID [2022-02-21 04:23:23,028 INFO L290 TraceCheckUtils]: 151: Hoare triple {42504#false} assume 1 == ~E_5~0;~E_5~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,029 INFO L290 TraceCheckUtils]: 152: Hoare triple {42504#false} assume !(1 == ~E_6~0); {42504#false} is VALID [2022-02-21 04:23:23,029 INFO L290 TraceCheckUtils]: 153: Hoare triple {42504#false} assume !(1 == ~E_7~0); {42504#false} is VALID [2022-02-21 04:23:23,029 INFO L290 TraceCheckUtils]: 154: Hoare triple {42504#false} assume !(1 == ~E_8~0); {42504#false} is VALID [2022-02-21 04:23:23,029 INFO L290 TraceCheckUtils]: 155: Hoare triple {42504#false} assume !(1 == ~E_9~0); {42504#false} is VALID [2022-02-21 04:23:23,029 INFO L290 TraceCheckUtils]: 156: Hoare triple {42504#false} assume !(1 == ~E_10~0); {42504#false} is VALID [2022-02-21 04:23:23,029 INFO L290 TraceCheckUtils]: 157: Hoare triple {42504#false} assume !(1 == ~E_11~0); {42504#false} is VALID [2022-02-21 04:23:23,029 INFO L290 TraceCheckUtils]: 158: Hoare triple {42504#false} assume !(1 == ~E_12~0); {42504#false} is VALID [2022-02-21 04:23:23,030 INFO L290 TraceCheckUtils]: 159: Hoare triple {42504#false} assume 1 == ~E_13~0;~E_13~0 := 2; {42504#false} is VALID [2022-02-21 04:23:23,030 INFO L290 TraceCheckUtils]: 160: Hoare triple {42504#false} assume { :end_inline_reset_delta_events } true; {42504#false} is VALID [2022-02-21 04:23:23,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:23,030 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:23,030 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [74382205] [2022-02-21 04:23:23,031 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [74382205] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:23,031 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:23,031 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:23,031 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [712170781] [2022-02-21 04:23:23,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:23,031 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:23,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:23,032 INFO L85 PathProgramCache]: Analyzing trace with hash 1797411554, now seen corresponding path program 1 times [2022-02-21 04:23:23,032 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:23,035 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856600479] [2022-02-21 04:23:23,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:23,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:23,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 0: Hoare triple {42506#true} assume !false; {42506#true} is VALID [2022-02-21 04:23:23,077 INFO L290 TraceCheckUtils]: 1: Hoare triple {42506#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {42506#true} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 2: Hoare triple {42506#true} assume !false; {42506#true} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 3: Hoare triple {42506#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {42506#true} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 4: Hoare triple {42506#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {42506#true} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 5: Hoare triple {42506#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {42506#true} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 6: Hoare triple {42506#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {42506#true} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 7: Hoare triple {42506#true} assume !(0 != eval_~tmp~0#1); {42506#true} is VALID [2022-02-21 04:23:23,078 INFO L290 TraceCheckUtils]: 8: Hoare triple {42506#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {42506#true} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 9: Hoare triple {42506#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {42506#true} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 10: Hoare triple {42506#true} assume 0 == ~M_E~0;~M_E~0 := 1; {42506#true} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 11: Hoare triple {42506#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {42506#true} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 12: Hoare triple {42506#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {42506#true} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 13: Hoare triple {42506#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {42506#true} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 14: Hoare triple {42506#true} assume !(0 == ~T4_E~0); {42506#true} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 15: Hoare triple {42506#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {42506#true} is VALID [2022-02-21 04:23:23,079 INFO L290 TraceCheckUtils]: 16: Hoare triple {42506#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {42506#true} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 17: Hoare triple {42506#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 18: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,080 INFO L290 TraceCheckUtils]: 19: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 20: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 21: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,081 INFO L290 TraceCheckUtils]: 22: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 23: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 24: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 25: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,082 INFO L290 TraceCheckUtils]: 26: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 27: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 28: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,083 INFO L290 TraceCheckUtils]: 29: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 30: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 31: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 32: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,084 INFO L290 TraceCheckUtils]: 33: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 34: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 35: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 36: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,085 INFO L290 TraceCheckUtils]: 37: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 38: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 39: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,086 INFO L290 TraceCheckUtils]: 40: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,087 INFO L290 TraceCheckUtils]: 41: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,087 INFO L290 TraceCheckUtils]: 42: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,087 INFO L290 TraceCheckUtils]: 43: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,087 INFO L290 TraceCheckUtils]: 44: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,088 INFO L290 TraceCheckUtils]: 45: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,088 INFO L290 TraceCheckUtils]: 46: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,088 INFO L290 TraceCheckUtils]: 47: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,089 INFO L290 TraceCheckUtils]: 48: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,089 INFO L290 TraceCheckUtils]: 49: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,089 INFO L290 TraceCheckUtils]: 50: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,089 INFO L290 TraceCheckUtils]: 51: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,090 INFO L290 TraceCheckUtils]: 52: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,090 INFO L290 TraceCheckUtils]: 53: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,090 INFO L290 TraceCheckUtils]: 54: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,091 INFO L290 TraceCheckUtils]: 55: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,091 INFO L290 TraceCheckUtils]: 56: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,091 INFO L290 TraceCheckUtils]: 57: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,091 INFO L290 TraceCheckUtils]: 58: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,092 INFO L290 TraceCheckUtils]: 59: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,092 INFO L290 TraceCheckUtils]: 60: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,092 INFO L290 TraceCheckUtils]: 61: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,092 INFO L290 TraceCheckUtils]: 62: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,093 INFO L290 TraceCheckUtils]: 63: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,093 INFO L290 TraceCheckUtils]: 64: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,093 INFO L290 TraceCheckUtils]: 65: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,094 INFO L290 TraceCheckUtils]: 66: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,094 INFO L290 TraceCheckUtils]: 67: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,094 INFO L290 TraceCheckUtils]: 68: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,094 INFO L290 TraceCheckUtils]: 69: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,095 INFO L290 TraceCheckUtils]: 70: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,095 INFO L290 TraceCheckUtils]: 71: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,095 INFO L290 TraceCheckUtils]: 72: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,096 INFO L290 TraceCheckUtils]: 73: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,096 INFO L290 TraceCheckUtils]: 74: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,096 INFO L290 TraceCheckUtils]: 75: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,096 INFO L290 TraceCheckUtils]: 76: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,097 INFO L290 TraceCheckUtils]: 77: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,097 INFO L290 TraceCheckUtils]: 78: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,097 INFO L290 TraceCheckUtils]: 79: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,097 INFO L290 TraceCheckUtils]: 80: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,098 INFO L290 TraceCheckUtils]: 81: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,098 INFO L290 TraceCheckUtils]: 82: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,098 INFO L290 TraceCheckUtils]: 83: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,099 INFO L290 TraceCheckUtils]: 84: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,099 INFO L290 TraceCheckUtils]: 85: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,099 INFO L290 TraceCheckUtils]: 86: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,099 INFO L290 TraceCheckUtils]: 87: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t8_pc~0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,100 INFO L290 TraceCheckUtils]: 88: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,100 INFO L290 TraceCheckUtils]: 89: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,100 INFO L290 TraceCheckUtils]: 90: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,101 INFO L290 TraceCheckUtils]: 91: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,101 INFO L290 TraceCheckUtils]: 92: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,101 INFO L290 TraceCheckUtils]: 93: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,101 INFO L290 TraceCheckUtils]: 94: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,102 INFO L290 TraceCheckUtils]: 95: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,102 INFO L290 TraceCheckUtils]: 96: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,102 INFO L290 TraceCheckUtils]: 97: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,103 INFO L290 TraceCheckUtils]: 98: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,103 INFO L290 TraceCheckUtils]: 99: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t10_pc~0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,103 INFO L290 TraceCheckUtils]: 100: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,103 INFO L290 TraceCheckUtils]: 101: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,104 INFO L290 TraceCheckUtils]: 102: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,104 INFO L290 TraceCheckUtils]: 103: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,104 INFO L290 TraceCheckUtils]: 104: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,104 INFO L290 TraceCheckUtils]: 105: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t11_pc~0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,105 INFO L290 TraceCheckUtils]: 106: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,105 INFO L290 TraceCheckUtils]: 107: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,105 INFO L290 TraceCheckUtils]: 108: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,106 INFO L290 TraceCheckUtils]: 109: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,106 INFO L290 TraceCheckUtils]: 110: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,106 INFO L290 TraceCheckUtils]: 111: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,106 INFO L290 TraceCheckUtils]: 112: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,107 INFO L290 TraceCheckUtils]: 113: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,107 INFO L290 TraceCheckUtils]: 114: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,107 INFO L290 TraceCheckUtils]: 115: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,108 INFO L290 TraceCheckUtils]: 116: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,108 INFO L290 TraceCheckUtils]: 117: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t13_pc~0); {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,108 INFO L290 TraceCheckUtils]: 118: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,108 INFO L290 TraceCheckUtils]: 119: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,109 INFO L290 TraceCheckUtils]: 120: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,109 INFO L290 TraceCheckUtils]: 121: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,109 INFO L290 TraceCheckUtils]: 122: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,109 INFO L290 TraceCheckUtils]: 123: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,110 INFO L290 TraceCheckUtils]: 124: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,110 INFO L290 TraceCheckUtils]: 125: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,110 INFO L290 TraceCheckUtils]: 126: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,111 INFO L290 TraceCheckUtils]: 127: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,111 INFO L290 TraceCheckUtils]: 128: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,111 INFO L290 TraceCheckUtils]: 129: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {42508#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:23,111 INFO L290 TraceCheckUtils]: 130: Hoare triple {42508#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {42507#false} is VALID [2022-02-21 04:23:23,112 INFO L290 TraceCheckUtils]: 131: Hoare triple {42507#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,112 INFO L290 TraceCheckUtils]: 132: Hoare triple {42507#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,112 INFO L290 TraceCheckUtils]: 133: Hoare triple {42507#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,112 INFO L290 TraceCheckUtils]: 134: Hoare triple {42507#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,112 INFO L290 TraceCheckUtils]: 135: Hoare triple {42507#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,112 INFO L290 TraceCheckUtils]: 136: Hoare triple {42507#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,112 INFO L290 TraceCheckUtils]: 137: Hoare triple {42507#false} assume 1 == ~E_M~0;~E_M~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,112 INFO L290 TraceCheckUtils]: 138: Hoare triple {42507#false} assume !(1 == ~E_1~0); {42507#false} is VALID [2022-02-21 04:23:23,113 INFO L290 TraceCheckUtils]: 139: Hoare triple {42507#false} assume 1 == ~E_2~0;~E_2~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,113 INFO L290 TraceCheckUtils]: 140: Hoare triple {42507#false} assume 1 == ~E_3~0;~E_3~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,113 INFO L290 TraceCheckUtils]: 141: Hoare triple {42507#false} assume 1 == ~E_4~0;~E_4~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,113 INFO L290 TraceCheckUtils]: 142: Hoare triple {42507#false} assume 1 == ~E_5~0;~E_5~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,113 INFO L290 TraceCheckUtils]: 143: Hoare triple {42507#false} assume 1 == ~E_6~0;~E_6~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,113 INFO L290 TraceCheckUtils]: 144: Hoare triple {42507#false} assume 1 == ~E_7~0;~E_7~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,113 INFO L290 TraceCheckUtils]: 145: Hoare triple {42507#false} assume 1 == ~E_8~0;~E_8~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,113 INFO L290 TraceCheckUtils]: 146: Hoare triple {42507#false} assume !(1 == ~E_9~0); {42507#false} is VALID [2022-02-21 04:23:23,114 INFO L290 TraceCheckUtils]: 147: Hoare triple {42507#false} assume 1 == ~E_10~0;~E_10~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,114 INFO L290 TraceCheckUtils]: 148: Hoare triple {42507#false} assume 1 == ~E_11~0;~E_11~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,114 INFO L290 TraceCheckUtils]: 149: Hoare triple {42507#false} assume 1 == ~E_12~0;~E_12~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,114 INFO L290 TraceCheckUtils]: 150: Hoare triple {42507#false} assume 1 == ~E_13~0;~E_13~0 := 2; {42507#false} is VALID [2022-02-21 04:23:23,114 INFO L290 TraceCheckUtils]: 151: Hoare triple {42507#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {42507#false} is VALID [2022-02-21 04:23:23,114 INFO L290 TraceCheckUtils]: 152: Hoare triple {42507#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {42507#false} is VALID [2022-02-21 04:23:23,114 INFO L290 TraceCheckUtils]: 153: Hoare triple {42507#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {42507#false} is VALID [2022-02-21 04:23:23,115 INFO L290 TraceCheckUtils]: 154: Hoare triple {42507#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {42507#false} is VALID [2022-02-21 04:23:23,115 INFO L290 TraceCheckUtils]: 155: Hoare triple {42507#false} assume !(0 == start_simulation_~tmp~3#1); {42507#false} is VALID [2022-02-21 04:23:23,115 INFO L290 TraceCheckUtils]: 156: Hoare triple {42507#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {42507#false} is VALID [2022-02-21 04:23:23,115 INFO L290 TraceCheckUtils]: 157: Hoare triple {42507#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {42507#false} is VALID [2022-02-21 04:23:23,115 INFO L290 TraceCheckUtils]: 158: Hoare triple {42507#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {42507#false} is VALID [2022-02-21 04:23:23,115 INFO L290 TraceCheckUtils]: 159: Hoare triple {42507#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {42507#false} is VALID [2022-02-21 04:23:23,115 INFO L290 TraceCheckUtils]: 160: Hoare triple {42507#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {42507#false} is VALID [2022-02-21 04:23:23,115 INFO L290 TraceCheckUtils]: 161: Hoare triple {42507#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {42507#false} is VALID [2022-02-21 04:23:23,116 INFO L290 TraceCheckUtils]: 162: Hoare triple {42507#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {42507#false} is VALID [2022-02-21 04:23:23,116 INFO L290 TraceCheckUtils]: 163: Hoare triple {42507#false} assume !(0 != start_simulation_~tmp___0~1#1); {42507#false} is VALID [2022-02-21 04:23:23,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:23,116 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:23,116 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856600479] [2022-02-21 04:23:23,117 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856600479] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:23,117 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:23,117 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:23,117 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [356232279] [2022-02-21 04:23:23,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:23,118 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:23,118 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:23,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:23,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:23,119 INFO L87 Difference]: Start difference. First operand 2021 states and 2988 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,505 INFO L93 Difference]: Finished difference Result 2021 states and 2987 transitions. [2022-02-21 04:23:24,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:24,505 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,593 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:24,594 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2987 transitions. [2022-02-21 04:23:24,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:24,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2987 transitions. [2022-02-21 04:23:24,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:24,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:24,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2987 transitions. [2022-02-21 04:23:24,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:24,789 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2022-02-21 04:23:24,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2987 transitions. [2022-02-21 04:23:24,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:24,804 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:24,806 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2987 transitions. Second operand has 2021 states, 2021 states have (on average 1.4779811974270163) internal successors, (2987), 2020 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,807 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2987 transitions. Second operand has 2021 states, 2021 states have (on average 1.4779811974270163) internal successors, (2987), 2020 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,808 INFO L87 Difference]: Start difference. First operand 2021 states and 2987 transitions. Second operand has 2021 states, 2021 states have (on average 1.4779811974270163) internal successors, (2987), 2020 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,890 INFO L93 Difference]: Finished difference Result 2021 states and 2987 transitions. [2022-02-21 04:23:24,890 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2987 transitions. [2022-02-21 04:23:24,892 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:24,892 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:24,894 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.4779811974270163) internal successors, (2987), 2020 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2987 transitions. [2022-02-21 04:23:24,895 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.4779811974270163) internal successors, (2987), 2020 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2987 transitions. [2022-02-21 04:23:24,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,977 INFO L93 Difference]: Finished difference Result 2021 states and 2987 transitions. [2022-02-21 04:23:24,977 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2987 transitions. [2022-02-21 04:23:24,979 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:24,979 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:24,979 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:24,979 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:24,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4779811974270163) internal successors, (2987), 2020 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2987 transitions. [2022-02-21 04:23:25,061 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2022-02-21 04:23:25,061 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2022-02-21 04:23:25,061 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:23:25,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2987 transitions. [2022-02-21 04:23:25,064 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:25,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:25,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:25,065 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:25,065 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:25,066 INFO L791 eck$LassoCheckResult]: Stem: 45406#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 45138#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45139#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46529#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 46530#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45325#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45326#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45360#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46197#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46198#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 46310#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 46311#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 45144#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45145#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 46347#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 45669#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45670#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46251#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46517#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 46407#L1286-2 assume !(0 == ~T1_E~0); 45053#L1291-1 assume !(0 == ~T2_E~0); 45054#L1296-1 assume !(0 == ~T3_E~0); 45759#L1301-1 assume !(0 == ~T4_E~0); 45760#L1306-1 assume !(0 == ~T5_E~0); 46260#L1311-1 assume !(0 == ~T6_E~0); 45013#L1316-1 assume !(0 == ~T7_E~0); 45014#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45779#L1326-1 assume !(0 == ~T9_E~0); 44828#L1331-1 assume !(0 == ~T10_E~0); 44534#L1336-1 assume !(0 == ~T11_E~0); 44535#L1341-1 assume !(0 == ~T12_E~0); 44586#L1346-1 assume !(0 == ~T13_E~0); 44587#L1351-1 assume !(0 == ~E_M~0); 44960#L1356-1 assume !(0 == ~E_1~0); 44961#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 46480#L1366-1 assume !(0 == ~E_3~0); 45006#L1371-1 assume !(0 == ~E_4~0); 45007#L1376-1 assume !(0 == ~E_5~0); 45820#L1381-1 assume !(0 == ~E_6~0); 45821#L1386-1 assume !(0 == ~E_7~0); 46508#L1391-1 assume !(0 == ~E_8~0); 46521#L1396-1 assume !(0 == ~E_9~0); 45703#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 45704#L1406-1 assume !(0 == ~E_11~0); 46006#L1411-1 assume !(0 == ~E_12~0); 46007#L1416-1 assume !(0 == ~E_13~0); 45627#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45465#L635 assume !(1 == ~m_pc~0); 44604#L635-2 is_master_triggered_~__retres1~0#1 := 0; 44605#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44955#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45591#L1598 assume !(0 != activate_threads_~tmp~1#1); 44783#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44784#L654 assume 1 == ~t1_pc~0; 45489#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45490#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46505#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45571#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 45572#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44831#L673 assume 1 == ~t2_pc~0; 44832#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45976#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45977#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46535#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 46542#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45650#L692 assume !(1 == ~t3_pc~0); 45467#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45468#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45327#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45295#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45296#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44856#L711 assume 1 == ~t4_pc~0; 44857#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45340#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45797#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44559#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 44560#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46528#L730 assume !(1 == ~t5_pc~0); 45910#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 44738#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44739#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44866#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 44867#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45209#L749 assume 1 == ~t6_pc~0; 44983#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44743#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45175#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45176#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 45398#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44539#L768 assume !(1 == ~t7_pc~0); 44540#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45844#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44776#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44777#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 45863#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45015#L787 assume 1 == ~t8_pc~0; 45016#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46211#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46375#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46376#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 44584#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44585#L806 assume 1 == ~t9_pc~0; 46222#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44619#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44620#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44868#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 44869#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46205#L825 assume !(1 == ~t10_pc~0); 46206#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45811#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45812#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44956#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44957#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45540#L844 assume 1 == ~t11_pc~0; 45230#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45231#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45597#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45598#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 46193#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46194#L863 assume !(1 == ~t12_pc~0); 44719#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44718#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44946#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46285#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 46286#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45664#L882 assume 1 == ~t13_pc~0; 45665#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45949#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46450#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46253#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 45936#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45937#L1434 assume !(1 == ~M_E~0); 46458#L1434-2 assume !(1 == ~T1_E~0); 46534#L1439-1 assume !(1 == ~T2_E~0); 44849#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44850#L1449-1 assume !(1 == ~T4_E~0); 45292#L1454-1 assume !(1 == ~T5_E~0); 45293#L1459-1 assume !(1 == ~T6_E~0); 45864#L1464-1 assume !(1 == ~T7_E~0); 45865#L1469-1 assume !(1 == ~T8_E~0); 45950#L1474-1 assume !(1 == ~T9_E~0); 45628#L1479-1 assume !(1 == ~T10_E~0); 45629#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45872#L1489-1 assume !(1 == ~T12_E~0); 45506#L1494-1 assume !(1 == ~T13_E~0); 45507#L1499-1 assume !(1 == ~E_M~0); 45688#L1504-1 assume !(1 == ~E_1~0); 45689#L1509-1 assume !(1 == ~E_2~0); 46302#L1514-1 assume !(1 == ~E_3~0); 45987#L1519-1 assume !(1 == ~E_4~0); 45988#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46492#L1529-1 assume !(1 == ~E_6~0); 46493#L1534-1 assume !(1 == ~E_7~0); 44639#L1539-1 assume !(1 == ~E_8~0); 44640#L1544-1 assume !(1 == ~E_9~0); 45070#L1549-1 assume !(1 == ~E_10~0); 46470#L1554-1 assume !(1 == ~E_11~0); 46468#L1559-1 assume !(1 == ~E_12~0); 46330#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46331#L1569-1 assume { :end_inline_reset_delta_events } true; 46486#L1935-2 [2022-02-21 04:23:25,066 INFO L793 eck$LassoCheckResult]: Loop: 46486#L1935-2 assume !false; 44648#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44649#L1261 assume !false; 45876#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45877#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44779#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44949#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44950#L1074 assume !(0 != eval_~tmp~0#1); 45307#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45905#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46306#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46362#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46081#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46082#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46518#L1301-3 assume !(0 == ~T4_E~0); 46476#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45584#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44883#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44884#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44989#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45725#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45990#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45991#L1341-3 assume !(0 == ~T12_E~0); 45285#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45276#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45220#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45221#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45801#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44574#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44575#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46317#L1381-3 assume !(0 == ~E_6~0); 46166#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46167#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46348#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46349#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44954#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44785#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44786#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45413#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44663#L635-45 assume 1 == ~m_pc~0; 44664#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45458#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45938#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46192#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44972#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44973#L654-45 assume 1 == ~t1_pc~0; 45793#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46141#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44626#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44627#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44652#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45479#L673-45 assume !(1 == ~t2_pc~0); 45480#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 45804#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45805#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46430#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 46250#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45097#L692-45 assume !(1 == ~t3_pc~0); 44823#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 44824#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45868#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45151#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45152#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45464#L711-45 assume 1 == ~t4_pc~0; 45588#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45589#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45441#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45442#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45845#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44996#L730-45 assume 1 == ~t5_pc~0; 44834#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44835#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45244#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45245#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45996#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44807#L749-45 assume !(1 == ~t6_pc~0); 44808#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 46208#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45971#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45972#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46123#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45123#L768-45 assume 1 == ~t7_pc~0; 45124#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45263#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46067#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46068#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46107#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46108#L787-45 assume 1 == ~t8_pc~0; 46276#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45269#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45270#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45686#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45687#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45995#L806-45 assume 1 == ~t9_pc~0; 46471#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44683#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45508#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45336#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45248#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45249#L825-45 assume 1 == ~t10_pc~0; 45860#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45773#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45878#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45879#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46031#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44891#L844-45 assume !(1 == ~t11_pc~0); 44892#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45414#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45415#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45431#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 45842#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44931#L863-45 assume 1 == ~t12_pc~0; 44932#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44532#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44533#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45048#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45049#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45848#L882-45 assume !(1 == ~t13_pc~0); 45378#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 44551#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 44552#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45160#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46339#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45955#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45956#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46140#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44845#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44846#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45008#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45945#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45946#L1464-3 assume !(1 == ~T7_E~0); 46392#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46319#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46320#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46394#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45586#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45587#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46247#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45882#L1504-3 assume !(1 == ~E_1~0); 45883#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46328#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46368#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45509#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45510#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46415#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45810#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45264#L1544-3 assume !(1 == ~E_9~0); 45265#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 45780#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44896#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44897#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46046#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46047#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44781#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45346#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46017#L1954 assume !(0 == start_simulation_~tmp~3#1); 46019#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46269#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45064#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46105#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46235#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46236#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46326#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46388#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 46486#L1935-2 [2022-02-21 04:23:25,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:25,067 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2022-02-21 04:23:25,067 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:25,067 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320889025] [2022-02-21 04:23:25,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:25,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:25,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:25,086 INFO L290 TraceCheckUtils]: 0: Hoare triple {50596#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {50596#true} is VALID [2022-02-21 04:23:25,086 INFO L290 TraceCheckUtils]: 1: Hoare triple {50596#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {50598#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:25,086 INFO L290 TraceCheckUtils]: 2: Hoare triple {50598#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {50598#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:25,087 INFO L290 TraceCheckUtils]: 3: Hoare triple {50598#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {50598#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:25,087 INFO L290 TraceCheckUtils]: 4: Hoare triple {50598#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {50598#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:25,087 INFO L290 TraceCheckUtils]: 5: Hoare triple {50598#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {50598#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:25,087 INFO L290 TraceCheckUtils]: 6: Hoare triple {50598#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {50598#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:25,088 INFO L290 TraceCheckUtils]: 7: Hoare triple {50598#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {50598#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:25,088 INFO L290 TraceCheckUtils]: 8: Hoare triple {50598#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {50598#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:25,088 INFO L290 TraceCheckUtils]: 9: Hoare triple {50598#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {50598#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:25,088 INFO L290 TraceCheckUtils]: 10: Hoare triple {50598#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 11: Hoare triple {50597#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 12: Hoare triple {50597#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 13: Hoare triple {50597#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {50597#false} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 14: Hoare triple {50597#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 15: Hoare triple {50597#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 16: Hoare triple {50597#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 17: Hoare triple {50597#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 18: Hoare triple {50597#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {50597#false} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 19: Hoare triple {50597#false} assume 0 == ~M_E~0;~M_E~0 := 1; {50597#false} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 20: Hoare triple {50597#false} assume !(0 == ~T1_E~0); {50597#false} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 21: Hoare triple {50597#false} assume !(0 == ~T2_E~0); {50597#false} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 22: Hoare triple {50597#false} assume !(0 == ~T3_E~0); {50597#false} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 23: Hoare triple {50597#false} assume !(0 == ~T4_E~0); {50597#false} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 24: Hoare triple {50597#false} assume !(0 == ~T5_E~0); {50597#false} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 25: Hoare triple {50597#false} assume !(0 == ~T6_E~0); {50597#false} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 26: Hoare triple {50597#false} assume !(0 == ~T7_E~0); {50597#false} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 27: Hoare triple {50597#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {50597#false} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 28: Hoare triple {50597#false} assume !(0 == ~T9_E~0); {50597#false} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 29: Hoare triple {50597#false} assume !(0 == ~T10_E~0); {50597#false} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 30: Hoare triple {50597#false} assume !(0 == ~T11_E~0); {50597#false} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 31: Hoare triple {50597#false} assume !(0 == ~T12_E~0); {50597#false} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 32: Hoare triple {50597#false} assume !(0 == ~T13_E~0); {50597#false} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 33: Hoare triple {50597#false} assume !(0 == ~E_M~0); {50597#false} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 34: Hoare triple {50597#false} assume !(0 == ~E_1~0); {50597#false} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 35: Hoare triple {50597#false} assume 0 == ~E_2~0;~E_2~0 := 1; {50597#false} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 36: Hoare triple {50597#false} assume !(0 == ~E_3~0); {50597#false} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 37: Hoare triple {50597#false} assume !(0 == ~E_4~0); {50597#false} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 38: Hoare triple {50597#false} assume !(0 == ~E_5~0); {50597#false} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 39: Hoare triple {50597#false} assume !(0 == ~E_6~0); {50597#false} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 40: Hoare triple {50597#false} assume !(0 == ~E_7~0); {50597#false} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 41: Hoare triple {50597#false} assume !(0 == ~E_8~0); {50597#false} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 42: Hoare triple {50597#false} assume !(0 == ~E_9~0); {50597#false} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 43: Hoare triple {50597#false} assume 0 == ~E_10~0;~E_10~0 := 1; {50597#false} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 44: Hoare triple {50597#false} assume !(0 == ~E_11~0); {50597#false} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 45: Hoare triple {50597#false} assume !(0 == ~E_12~0); {50597#false} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 46: Hoare triple {50597#false} assume !(0 == ~E_13~0); {50597#false} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 47: Hoare triple {50597#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {50597#false} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 48: Hoare triple {50597#false} assume !(1 == ~m_pc~0); {50597#false} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 49: Hoare triple {50597#false} is_master_triggered_~__retres1~0#1 := 0; {50597#false} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 50: Hoare triple {50597#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {50597#false} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 51: Hoare triple {50597#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {50597#false} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 52: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp~1#1); {50597#false} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 53: Hoare triple {50597#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {50597#false} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 54: Hoare triple {50597#false} assume 1 == ~t1_pc~0; {50597#false} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 55: Hoare triple {50597#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {50597#false} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 56: Hoare triple {50597#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {50597#false} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 57: Hoare triple {50597#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {50597#false} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 58: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___0~0#1); {50597#false} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 59: Hoare triple {50597#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {50597#false} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 60: Hoare triple {50597#false} assume 1 == ~t2_pc~0; {50597#false} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 61: Hoare triple {50597#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {50597#false} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 62: Hoare triple {50597#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {50597#false} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 63: Hoare triple {50597#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {50597#false} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 64: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___1~0#1); {50597#false} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 65: Hoare triple {50597#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {50597#false} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 66: Hoare triple {50597#false} assume !(1 == ~t3_pc~0); {50597#false} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 67: Hoare triple {50597#false} is_transmit3_triggered_~__retres1~3#1 := 0; {50597#false} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 68: Hoare triple {50597#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {50597#false} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 69: Hoare triple {50597#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {50597#false} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 70: Hoare triple {50597#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {50597#false} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 71: Hoare triple {50597#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {50597#false} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 72: Hoare triple {50597#false} assume 1 == ~t4_pc~0; {50597#false} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 73: Hoare triple {50597#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {50597#false} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 74: Hoare triple {50597#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {50597#false} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 75: Hoare triple {50597#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {50597#false} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 76: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___3~0#1); {50597#false} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 77: Hoare triple {50597#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {50597#false} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 78: Hoare triple {50597#false} assume !(1 == ~t5_pc~0); {50597#false} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 79: Hoare triple {50597#false} is_transmit5_triggered_~__retres1~5#1 := 0; {50597#false} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 80: Hoare triple {50597#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {50597#false} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 81: Hoare triple {50597#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {50597#false} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 82: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___4~0#1); {50597#false} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 83: Hoare triple {50597#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {50597#false} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 84: Hoare triple {50597#false} assume 1 == ~t6_pc~0; {50597#false} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 85: Hoare triple {50597#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {50597#false} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 86: Hoare triple {50597#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {50597#false} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 87: Hoare triple {50597#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {50597#false} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 88: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___5~0#1); {50597#false} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 89: Hoare triple {50597#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {50597#false} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 90: Hoare triple {50597#false} assume !(1 == ~t7_pc~0); {50597#false} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 91: Hoare triple {50597#false} is_transmit7_triggered_~__retres1~7#1 := 0; {50597#false} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 92: Hoare triple {50597#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {50597#false} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 93: Hoare triple {50597#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {50597#false} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 94: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___6~0#1); {50597#false} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 95: Hoare triple {50597#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {50597#false} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 96: Hoare triple {50597#false} assume 1 == ~t8_pc~0; {50597#false} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 97: Hoare triple {50597#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {50597#false} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 98: Hoare triple {50597#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {50597#false} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 99: Hoare triple {50597#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {50597#false} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 100: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___7~0#1); {50597#false} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 101: Hoare triple {50597#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {50597#false} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 102: Hoare triple {50597#false} assume 1 == ~t9_pc~0; {50597#false} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 103: Hoare triple {50597#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {50597#false} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 104: Hoare triple {50597#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {50597#false} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 105: Hoare triple {50597#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {50597#false} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 106: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___8~0#1); {50597#false} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 107: Hoare triple {50597#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {50597#false} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 108: Hoare triple {50597#false} assume !(1 == ~t10_pc~0); {50597#false} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 109: Hoare triple {50597#false} is_transmit10_triggered_~__retres1~10#1 := 0; {50597#false} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 110: Hoare triple {50597#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {50597#false} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 111: Hoare triple {50597#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {50597#false} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 112: Hoare triple {50597#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {50597#false} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 113: Hoare triple {50597#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {50597#false} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 114: Hoare triple {50597#false} assume 1 == ~t11_pc~0; {50597#false} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 115: Hoare triple {50597#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {50597#false} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 116: Hoare triple {50597#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {50597#false} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 117: Hoare triple {50597#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {50597#false} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 118: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___10~0#1); {50597#false} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 119: Hoare triple {50597#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {50597#false} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 120: Hoare triple {50597#false} assume !(1 == ~t12_pc~0); {50597#false} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 121: Hoare triple {50597#false} is_transmit12_triggered_~__retres1~12#1 := 0; {50597#false} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 122: Hoare triple {50597#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {50597#false} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 123: Hoare triple {50597#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {50597#false} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 124: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___11~0#1); {50597#false} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 125: Hoare triple {50597#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {50597#false} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 126: Hoare triple {50597#false} assume 1 == ~t13_pc~0; {50597#false} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 127: Hoare triple {50597#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {50597#false} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 128: Hoare triple {50597#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {50597#false} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 129: Hoare triple {50597#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {50597#false} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 130: Hoare triple {50597#false} assume !(0 != activate_threads_~tmp___12~0#1); {50597#false} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 131: Hoare triple {50597#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {50597#false} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 132: Hoare triple {50597#false} assume !(1 == ~M_E~0); {50597#false} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 133: Hoare triple {50597#false} assume !(1 == ~T1_E~0); {50597#false} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 134: Hoare triple {50597#false} assume !(1 == ~T2_E~0); {50597#false} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 135: Hoare triple {50597#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 136: Hoare triple {50597#false} assume !(1 == ~T4_E~0); {50597#false} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 137: Hoare triple {50597#false} assume !(1 == ~T5_E~0); {50597#false} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 138: Hoare triple {50597#false} assume !(1 == ~T6_E~0); {50597#false} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 139: Hoare triple {50597#false} assume !(1 == ~T7_E~0); {50597#false} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 140: Hoare triple {50597#false} assume !(1 == ~T8_E~0); {50597#false} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 141: Hoare triple {50597#false} assume !(1 == ~T9_E~0); {50597#false} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 142: Hoare triple {50597#false} assume !(1 == ~T10_E~0); {50597#false} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 143: Hoare triple {50597#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 144: Hoare triple {50597#false} assume !(1 == ~T12_E~0); {50597#false} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 145: Hoare triple {50597#false} assume !(1 == ~T13_E~0); {50597#false} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 146: Hoare triple {50597#false} assume !(1 == ~E_M~0); {50597#false} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 147: Hoare triple {50597#false} assume !(1 == ~E_1~0); {50597#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 148: Hoare triple {50597#false} assume !(1 == ~E_2~0); {50597#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 149: Hoare triple {50597#false} assume !(1 == ~E_3~0); {50597#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 150: Hoare triple {50597#false} assume !(1 == ~E_4~0); {50597#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 151: Hoare triple {50597#false} assume 1 == ~E_5~0;~E_5~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 152: Hoare triple {50597#false} assume !(1 == ~E_6~0); {50597#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 153: Hoare triple {50597#false} assume !(1 == ~E_7~0); {50597#false} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 154: Hoare triple {50597#false} assume !(1 == ~E_8~0); {50597#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 155: Hoare triple {50597#false} assume !(1 == ~E_9~0); {50597#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 156: Hoare triple {50597#false} assume !(1 == ~E_10~0); {50597#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 157: Hoare triple {50597#false} assume !(1 == ~E_11~0); {50597#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 158: Hoare triple {50597#false} assume !(1 == ~E_12~0); {50597#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 159: Hoare triple {50597#false} assume 1 == ~E_13~0;~E_13~0 := 2; {50597#false} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 160: Hoare triple {50597#false} assume { :end_inline_reset_delta_events } true; {50597#false} is VALID [2022-02-21 04:23:25,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:25,109 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:25,109 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [320889025] [2022-02-21 04:23:25,109 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [320889025] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:25,109 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:25,109 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:25,109 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1169947364] [2022-02-21 04:23:25,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:25,110 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:25,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:25,110 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 2 times [2022-02-21 04:23:25,110 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:25,111 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373645683] [2022-02-21 04:23:25,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:25,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:25,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:25,144 INFO L290 TraceCheckUtils]: 0: Hoare triple {50599#true} assume !false; {50599#true} is VALID [2022-02-21 04:23:25,145 INFO L290 TraceCheckUtils]: 1: Hoare triple {50599#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {50599#true} is VALID [2022-02-21 04:23:25,145 INFO L290 TraceCheckUtils]: 2: Hoare triple {50599#true} assume !false; {50599#true} is VALID [2022-02-21 04:23:25,145 INFO L290 TraceCheckUtils]: 3: Hoare triple {50599#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {50599#true} is VALID [2022-02-21 04:23:25,145 INFO L290 TraceCheckUtils]: 4: Hoare triple {50599#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {50599#true} is VALID [2022-02-21 04:23:25,145 INFO L290 TraceCheckUtils]: 5: Hoare triple {50599#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {50599#true} is VALID [2022-02-21 04:23:25,145 INFO L290 TraceCheckUtils]: 6: Hoare triple {50599#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {50599#true} is VALID [2022-02-21 04:23:25,145 INFO L290 TraceCheckUtils]: 7: Hoare triple {50599#true} assume !(0 != eval_~tmp~0#1); {50599#true} is VALID [2022-02-21 04:23:25,145 INFO L290 TraceCheckUtils]: 8: Hoare triple {50599#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {50599#true} is VALID [2022-02-21 04:23:25,146 INFO L290 TraceCheckUtils]: 9: Hoare triple {50599#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {50599#true} is VALID [2022-02-21 04:23:25,146 INFO L290 TraceCheckUtils]: 10: Hoare triple {50599#true} assume 0 == ~M_E~0;~M_E~0 := 1; {50599#true} is VALID [2022-02-21 04:23:25,146 INFO L290 TraceCheckUtils]: 11: Hoare triple {50599#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {50599#true} is VALID [2022-02-21 04:23:25,146 INFO L290 TraceCheckUtils]: 12: Hoare triple {50599#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {50599#true} is VALID [2022-02-21 04:23:25,146 INFO L290 TraceCheckUtils]: 13: Hoare triple {50599#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {50599#true} is VALID [2022-02-21 04:23:25,146 INFO L290 TraceCheckUtils]: 14: Hoare triple {50599#true} assume !(0 == ~T4_E~0); {50599#true} is VALID [2022-02-21 04:23:25,146 INFO L290 TraceCheckUtils]: 15: Hoare triple {50599#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {50599#true} is VALID [2022-02-21 04:23:25,147 INFO L290 TraceCheckUtils]: 16: Hoare triple {50599#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {50599#true} is VALID [2022-02-21 04:23:25,147 INFO L290 TraceCheckUtils]: 17: Hoare triple {50599#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,147 INFO L290 TraceCheckUtils]: 18: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,147 INFO L290 TraceCheckUtils]: 19: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,148 INFO L290 TraceCheckUtils]: 20: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,148 INFO L290 TraceCheckUtils]: 21: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,148 INFO L290 TraceCheckUtils]: 22: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,149 INFO L290 TraceCheckUtils]: 23: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,149 INFO L290 TraceCheckUtils]: 24: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,149 INFO L290 TraceCheckUtils]: 25: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,149 INFO L290 TraceCheckUtils]: 26: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,150 INFO L290 TraceCheckUtils]: 27: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,150 INFO L290 TraceCheckUtils]: 28: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,150 INFO L290 TraceCheckUtils]: 29: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,151 INFO L290 TraceCheckUtils]: 30: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,151 INFO L290 TraceCheckUtils]: 31: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,151 INFO L290 TraceCheckUtils]: 32: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,151 INFO L290 TraceCheckUtils]: 33: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,152 INFO L290 TraceCheckUtils]: 34: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,152 INFO L290 TraceCheckUtils]: 35: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,152 INFO L290 TraceCheckUtils]: 36: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,153 INFO L290 TraceCheckUtils]: 37: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,153 INFO L290 TraceCheckUtils]: 38: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,153 INFO L290 TraceCheckUtils]: 39: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,153 INFO L290 TraceCheckUtils]: 40: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,154 INFO L290 TraceCheckUtils]: 41: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,154 INFO L290 TraceCheckUtils]: 42: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,154 INFO L290 TraceCheckUtils]: 43: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,155 INFO L290 TraceCheckUtils]: 44: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,155 INFO L290 TraceCheckUtils]: 45: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,155 INFO L290 TraceCheckUtils]: 46: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,155 INFO L290 TraceCheckUtils]: 47: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,156 INFO L290 TraceCheckUtils]: 48: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,156 INFO L290 TraceCheckUtils]: 49: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,156 INFO L290 TraceCheckUtils]: 50: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,157 INFO L290 TraceCheckUtils]: 51: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,157 INFO L290 TraceCheckUtils]: 52: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,157 INFO L290 TraceCheckUtils]: 53: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,157 INFO L290 TraceCheckUtils]: 54: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,158 INFO L290 TraceCheckUtils]: 55: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,158 INFO L290 TraceCheckUtils]: 56: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,158 INFO L290 TraceCheckUtils]: 57: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,159 INFO L290 TraceCheckUtils]: 58: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,159 INFO L290 TraceCheckUtils]: 59: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,159 INFO L290 TraceCheckUtils]: 60: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,159 INFO L290 TraceCheckUtils]: 61: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,160 INFO L290 TraceCheckUtils]: 62: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,160 INFO L290 TraceCheckUtils]: 63: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,160 INFO L290 TraceCheckUtils]: 64: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,161 INFO L290 TraceCheckUtils]: 65: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,161 INFO L290 TraceCheckUtils]: 66: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,161 INFO L290 TraceCheckUtils]: 67: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,161 INFO L290 TraceCheckUtils]: 68: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,162 INFO L290 TraceCheckUtils]: 69: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,162 INFO L290 TraceCheckUtils]: 70: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,162 INFO L290 TraceCheckUtils]: 71: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,163 INFO L290 TraceCheckUtils]: 72: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,163 INFO L290 TraceCheckUtils]: 73: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,163 INFO L290 TraceCheckUtils]: 74: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,163 INFO L290 TraceCheckUtils]: 75: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,164 INFO L290 TraceCheckUtils]: 76: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,164 INFO L290 TraceCheckUtils]: 77: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,164 INFO L290 TraceCheckUtils]: 78: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,165 INFO L290 TraceCheckUtils]: 79: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,165 INFO L290 TraceCheckUtils]: 80: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,165 INFO L290 TraceCheckUtils]: 81: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,165 INFO L290 TraceCheckUtils]: 82: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,166 INFO L290 TraceCheckUtils]: 83: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,166 INFO L290 TraceCheckUtils]: 84: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,166 INFO L290 TraceCheckUtils]: 85: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,167 INFO L290 TraceCheckUtils]: 86: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,167 INFO L290 TraceCheckUtils]: 87: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t8_pc~0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,167 INFO L290 TraceCheckUtils]: 88: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,167 INFO L290 TraceCheckUtils]: 89: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,168 INFO L290 TraceCheckUtils]: 90: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,168 INFO L290 TraceCheckUtils]: 91: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,168 INFO L290 TraceCheckUtils]: 92: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,169 INFO L290 TraceCheckUtils]: 93: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,169 INFO L290 TraceCheckUtils]: 94: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,169 INFO L290 TraceCheckUtils]: 95: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,170 INFO L290 TraceCheckUtils]: 96: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,170 INFO L290 TraceCheckUtils]: 97: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,170 INFO L290 TraceCheckUtils]: 98: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,170 INFO L290 TraceCheckUtils]: 99: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t10_pc~0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,171 INFO L290 TraceCheckUtils]: 100: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,171 INFO L290 TraceCheckUtils]: 101: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,171 INFO L290 TraceCheckUtils]: 102: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,172 INFO L290 TraceCheckUtils]: 103: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,172 INFO L290 TraceCheckUtils]: 104: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,172 INFO L290 TraceCheckUtils]: 105: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,172 INFO L290 TraceCheckUtils]: 106: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,173 INFO L290 TraceCheckUtils]: 107: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,173 INFO L290 TraceCheckUtils]: 108: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,173 INFO L290 TraceCheckUtils]: 109: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,174 INFO L290 TraceCheckUtils]: 110: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,174 INFO L290 TraceCheckUtils]: 111: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,174 INFO L290 TraceCheckUtils]: 112: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,174 INFO L290 TraceCheckUtils]: 113: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,175 INFO L290 TraceCheckUtils]: 114: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,175 INFO L290 TraceCheckUtils]: 115: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,175 INFO L290 TraceCheckUtils]: 116: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,176 INFO L290 TraceCheckUtils]: 117: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t13_pc~0); {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,176 INFO L290 TraceCheckUtils]: 118: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,176 INFO L290 TraceCheckUtils]: 119: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,176 INFO L290 TraceCheckUtils]: 120: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,177 INFO L290 TraceCheckUtils]: 121: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,177 INFO L290 TraceCheckUtils]: 122: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,177 INFO L290 TraceCheckUtils]: 123: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,178 INFO L290 TraceCheckUtils]: 124: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,178 INFO L290 TraceCheckUtils]: 125: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,178 INFO L290 TraceCheckUtils]: 126: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,178 INFO L290 TraceCheckUtils]: 127: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,179 INFO L290 TraceCheckUtils]: 128: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,179 INFO L290 TraceCheckUtils]: 129: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {50601#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:25,179 INFO L290 TraceCheckUtils]: 130: Hoare triple {50601#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {50600#false} is VALID [2022-02-21 04:23:25,179 INFO L290 TraceCheckUtils]: 131: Hoare triple {50600#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,180 INFO L290 TraceCheckUtils]: 132: Hoare triple {50600#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,180 INFO L290 TraceCheckUtils]: 133: Hoare triple {50600#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,180 INFO L290 TraceCheckUtils]: 134: Hoare triple {50600#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,180 INFO L290 TraceCheckUtils]: 135: Hoare triple {50600#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,180 INFO L290 TraceCheckUtils]: 136: Hoare triple {50600#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,180 INFO L290 TraceCheckUtils]: 137: Hoare triple {50600#false} assume 1 == ~E_M~0;~E_M~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,180 INFO L290 TraceCheckUtils]: 138: Hoare triple {50600#false} assume !(1 == ~E_1~0); {50600#false} is VALID [2022-02-21 04:23:25,181 INFO L290 TraceCheckUtils]: 139: Hoare triple {50600#false} assume 1 == ~E_2~0;~E_2~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,181 INFO L290 TraceCheckUtils]: 140: Hoare triple {50600#false} assume 1 == ~E_3~0;~E_3~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,181 INFO L290 TraceCheckUtils]: 141: Hoare triple {50600#false} assume 1 == ~E_4~0;~E_4~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,181 INFO L290 TraceCheckUtils]: 142: Hoare triple {50600#false} assume 1 == ~E_5~0;~E_5~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,181 INFO L290 TraceCheckUtils]: 143: Hoare triple {50600#false} assume 1 == ~E_6~0;~E_6~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,181 INFO L290 TraceCheckUtils]: 144: Hoare triple {50600#false} assume 1 == ~E_7~0;~E_7~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,181 INFO L290 TraceCheckUtils]: 145: Hoare triple {50600#false} assume 1 == ~E_8~0;~E_8~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,181 INFO L290 TraceCheckUtils]: 146: Hoare triple {50600#false} assume !(1 == ~E_9~0); {50600#false} is VALID [2022-02-21 04:23:25,182 INFO L290 TraceCheckUtils]: 147: Hoare triple {50600#false} assume 1 == ~E_10~0;~E_10~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,182 INFO L290 TraceCheckUtils]: 148: Hoare triple {50600#false} assume 1 == ~E_11~0;~E_11~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,182 INFO L290 TraceCheckUtils]: 149: Hoare triple {50600#false} assume 1 == ~E_12~0;~E_12~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,182 INFO L290 TraceCheckUtils]: 150: Hoare triple {50600#false} assume 1 == ~E_13~0;~E_13~0 := 2; {50600#false} is VALID [2022-02-21 04:23:25,182 INFO L290 TraceCheckUtils]: 151: Hoare triple {50600#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {50600#false} is VALID [2022-02-21 04:23:25,182 INFO L290 TraceCheckUtils]: 152: Hoare triple {50600#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {50600#false} is VALID [2022-02-21 04:23:25,182 INFO L290 TraceCheckUtils]: 153: Hoare triple {50600#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {50600#false} is VALID [2022-02-21 04:23:25,182 INFO L290 TraceCheckUtils]: 154: Hoare triple {50600#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {50600#false} is VALID [2022-02-21 04:23:25,183 INFO L290 TraceCheckUtils]: 155: Hoare triple {50600#false} assume !(0 == start_simulation_~tmp~3#1); {50600#false} is VALID [2022-02-21 04:23:25,183 INFO L290 TraceCheckUtils]: 156: Hoare triple {50600#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {50600#false} is VALID [2022-02-21 04:23:25,183 INFO L290 TraceCheckUtils]: 157: Hoare triple {50600#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {50600#false} is VALID [2022-02-21 04:23:25,183 INFO L290 TraceCheckUtils]: 158: Hoare triple {50600#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {50600#false} is VALID [2022-02-21 04:23:25,183 INFO L290 TraceCheckUtils]: 159: Hoare triple {50600#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {50600#false} is VALID [2022-02-21 04:23:25,183 INFO L290 TraceCheckUtils]: 160: Hoare triple {50600#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {50600#false} is VALID [2022-02-21 04:23:25,183 INFO L290 TraceCheckUtils]: 161: Hoare triple {50600#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {50600#false} is VALID [2022-02-21 04:23:25,184 INFO L290 TraceCheckUtils]: 162: Hoare triple {50600#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {50600#false} is VALID [2022-02-21 04:23:25,184 INFO L290 TraceCheckUtils]: 163: Hoare triple {50600#false} assume !(0 != start_simulation_~tmp___0~1#1); {50600#false} is VALID [2022-02-21 04:23:25,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:25,184 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:25,184 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1373645683] [2022-02-21 04:23:25,185 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1373645683] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:25,185 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:25,185 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:25,185 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447772506] [2022-02-21 04:23:25,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:25,185 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:25,186 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:25,186 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:25,186 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:25,186 INFO L87 Difference]: Start difference. First operand 2021 states and 2987 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,461 INFO L93 Difference]: Finished difference Result 2021 states and 2986 transitions. [2022-02-21 04:23:26,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:26,461 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,557 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:26,560 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2986 transitions. [2022-02-21 04:23:26,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:26,773 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2986 transitions. [2022-02-21 04:23:26,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:26,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:26,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2986 transitions. [2022-02-21 04:23:26,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:26,775 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2022-02-21 04:23:26,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2986 transitions. [2022-02-21 04:23:26,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:26,790 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:26,791 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2986 transitions. Second operand has 2021 states, 2021 states have (on average 1.4774863928748145) internal successors, (2986), 2020 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,792 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2986 transitions. Second operand has 2021 states, 2021 states have (on average 1.4774863928748145) internal successors, (2986), 2020 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,793 INFO L87 Difference]: Start difference. First operand 2021 states and 2986 transitions. Second operand has 2021 states, 2021 states have (on average 1.4774863928748145) internal successors, (2986), 2020 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,875 INFO L93 Difference]: Finished difference Result 2021 states and 2986 transitions. [2022-02-21 04:23:26,875 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2986 transitions. [2022-02-21 04:23:26,877 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:26,877 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:26,878 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.4774863928748145) internal successors, (2986), 2020 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2986 transitions. [2022-02-21 04:23:26,879 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.4774863928748145) internal successors, (2986), 2020 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2986 transitions. [2022-02-21 04:23:26,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,961 INFO L93 Difference]: Finished difference Result 2021 states and 2986 transitions. [2022-02-21 04:23:26,962 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2986 transitions. [2022-02-21 04:23:26,963 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:26,963 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:26,963 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:26,963 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:26,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4774863928748145) internal successors, (2986), 2020 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:27,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2986 transitions. [2022-02-21 04:23:27,047 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2022-02-21 04:23:27,047 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2022-02-21 04:23:27,047 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:23:27,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2986 transitions. [2022-02-21 04:23:27,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:27,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:27,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:27,051 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:27,051 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:27,052 INFO L791 eck$LassoCheckResult]: Stem: 53499#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53500#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 53231#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53232#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54622#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 54623#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53418#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53419#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53453#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54290#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54291#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54403#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 54404#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 53237#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53238#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 54440#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 53762#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 53763#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 54344#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54610#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 54500#L1286-2 assume !(0 == ~T1_E~0); 53146#L1291-1 assume !(0 == ~T2_E~0); 53147#L1296-1 assume !(0 == ~T3_E~0); 53852#L1301-1 assume !(0 == ~T4_E~0); 53853#L1306-1 assume !(0 == ~T5_E~0); 54353#L1311-1 assume !(0 == ~T6_E~0); 53106#L1316-1 assume !(0 == ~T7_E~0); 53107#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53872#L1326-1 assume !(0 == ~T9_E~0); 52921#L1331-1 assume !(0 == ~T10_E~0); 52627#L1336-1 assume !(0 == ~T11_E~0); 52628#L1341-1 assume !(0 == ~T12_E~0); 52679#L1346-1 assume !(0 == ~T13_E~0); 52680#L1351-1 assume !(0 == ~E_M~0); 53053#L1356-1 assume !(0 == ~E_1~0); 53054#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 54573#L1366-1 assume !(0 == ~E_3~0); 53099#L1371-1 assume !(0 == ~E_4~0); 53100#L1376-1 assume !(0 == ~E_5~0); 53913#L1381-1 assume !(0 == ~E_6~0); 53914#L1386-1 assume !(0 == ~E_7~0); 54601#L1391-1 assume !(0 == ~E_8~0); 54614#L1396-1 assume !(0 == ~E_9~0); 53796#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 53797#L1406-1 assume !(0 == ~E_11~0); 54099#L1411-1 assume !(0 == ~E_12~0); 54100#L1416-1 assume !(0 == ~E_13~0); 53720#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53558#L635 assume !(1 == ~m_pc~0); 52697#L635-2 is_master_triggered_~__retres1~0#1 := 0; 52698#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53048#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53684#L1598 assume !(0 != activate_threads_~tmp~1#1); 52876#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52877#L654 assume 1 == ~t1_pc~0; 53582#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53583#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54598#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53664#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 53665#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52924#L673 assume 1 == ~t2_pc~0; 52925#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54069#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54070#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54628#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 54635#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53743#L692 assume !(1 == ~t3_pc~0); 53560#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53561#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53420#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53388#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53389#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52949#L711 assume 1 == ~t4_pc~0; 52950#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53433#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53890#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52652#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 52653#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54621#L730 assume !(1 == ~t5_pc~0); 54003#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52831#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52832#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52959#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 52960#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53302#L749 assume 1 == ~t6_pc~0; 53076#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52836#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53268#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53269#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 53491#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52632#L768 assume !(1 == ~t7_pc~0); 52633#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53937#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52869#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52870#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 53956#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53108#L787 assume 1 == ~t8_pc~0; 53109#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54304#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54468#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54469#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 52677#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52678#L806 assume 1 == ~t9_pc~0; 54315#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52712#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52713#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52961#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 52962#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54298#L825 assume !(1 == ~t10_pc~0); 54299#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53904#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53905#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53049#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53050#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53633#L844 assume 1 == ~t11_pc~0; 53323#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53324#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53690#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53691#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 54286#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54287#L863 assume !(1 == ~t12_pc~0); 52812#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52811#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53039#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54378#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 54379#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53757#L882 assume 1 == ~t13_pc~0; 53758#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54042#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54543#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54346#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 54029#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54030#L1434 assume !(1 == ~M_E~0); 54551#L1434-2 assume !(1 == ~T1_E~0); 54627#L1439-1 assume !(1 == ~T2_E~0); 52942#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52943#L1449-1 assume !(1 == ~T4_E~0); 53385#L1454-1 assume !(1 == ~T5_E~0); 53386#L1459-1 assume !(1 == ~T6_E~0); 53957#L1464-1 assume !(1 == ~T7_E~0); 53958#L1469-1 assume !(1 == ~T8_E~0); 54043#L1474-1 assume !(1 == ~T9_E~0); 53721#L1479-1 assume !(1 == ~T10_E~0); 53722#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53965#L1489-1 assume !(1 == ~T12_E~0); 53599#L1494-1 assume !(1 == ~T13_E~0); 53600#L1499-1 assume !(1 == ~E_M~0); 53781#L1504-1 assume !(1 == ~E_1~0); 53782#L1509-1 assume !(1 == ~E_2~0); 54395#L1514-1 assume !(1 == ~E_3~0); 54080#L1519-1 assume !(1 == ~E_4~0); 54081#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54585#L1529-1 assume !(1 == ~E_6~0); 54586#L1534-1 assume !(1 == ~E_7~0); 52732#L1539-1 assume !(1 == ~E_8~0); 52733#L1544-1 assume !(1 == ~E_9~0); 53163#L1549-1 assume !(1 == ~E_10~0); 54563#L1554-1 assume !(1 == ~E_11~0); 54561#L1559-1 assume !(1 == ~E_12~0); 54423#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 54424#L1569-1 assume { :end_inline_reset_delta_events } true; 54579#L1935-2 [2022-02-21 04:23:27,052 INFO L793 eck$LassoCheckResult]: Loop: 54579#L1935-2 assume !false; 52741#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52742#L1261 assume !false; 53969#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53970#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52872#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53042#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53043#L1074 assume !(0 != eval_~tmp~0#1); 53400#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53998#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54399#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54455#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54174#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54175#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54611#L1301-3 assume !(0 == ~T4_E~0); 54569#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53677#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52976#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52977#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53082#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53818#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54083#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54084#L1341-3 assume !(0 == ~T12_E~0); 53378#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53369#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53313#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53314#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53894#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52667#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52668#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54410#L1381-3 assume !(0 == ~E_6~0); 54259#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54260#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54441#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54442#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53047#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52878#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52879#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53506#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52756#L635-45 assume 1 == ~m_pc~0; 52757#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53551#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54031#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54285#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53065#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53066#L654-45 assume 1 == ~t1_pc~0; 53886#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54234#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52719#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52720#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52745#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53572#L673-45 assume !(1 == ~t2_pc~0); 53573#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 53897#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53898#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54523#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 54343#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53190#L692-45 assume !(1 == ~t3_pc~0); 52916#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 52917#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53961#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53244#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53245#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53557#L711-45 assume 1 == ~t4_pc~0; 53681#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53682#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53534#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53535#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53938#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53089#L730-45 assume !(1 == ~t5_pc~0); 52929#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 52928#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53337#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53338#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54089#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52900#L749-45 assume !(1 == ~t6_pc~0); 52901#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 54301#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54064#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54065#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54216#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53216#L768-45 assume 1 == ~t7_pc~0; 53217#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53356#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54160#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54161#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54200#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54201#L787-45 assume 1 == ~t8_pc~0; 54369#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53362#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53363#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53779#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53780#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54088#L806-45 assume 1 == ~t9_pc~0; 54564#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52776#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53601#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53429#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53341#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53342#L825-45 assume 1 == ~t10_pc~0; 53953#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53866#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53971#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53972#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54124#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52984#L844-45 assume !(1 == ~t11_pc~0); 52985#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53507#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53508#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53524#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 53935#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53024#L863-45 assume 1 == ~t12_pc~0; 53025#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52625#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52626#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53141#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53142#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53941#L882-45 assume 1 == ~t13_pc~0; 54295#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 52644#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 52645#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 53253#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54432#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54048#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54049#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54233#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52938#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52939#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53101#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54038#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54039#L1464-3 assume !(1 == ~T7_E~0); 54485#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54412#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54413#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54487#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53679#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53680#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54340#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53975#L1504-3 assume !(1 == ~E_1~0); 53976#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54421#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54461#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53602#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53603#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54508#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53903#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53357#L1544-3 assume !(1 == ~E_9~0); 53358#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53873#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 52989#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 52990#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54139#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54140#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52874#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53439#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54110#L1954 assume !(0 == start_simulation_~tmp~3#1); 54112#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54362#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53157#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54198#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54328#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54329#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54419#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54481#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 54579#L1935-2 [2022-02-21 04:23:27,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:27,053 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2022-02-21 04:23:27,053 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:27,053 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776711619] [2022-02-21 04:23:27,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:27,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:27,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:27,089 INFO L290 TraceCheckUtils]: 0: Hoare triple {58689#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {58689#true} is VALID [2022-02-21 04:23:27,089 INFO L290 TraceCheckUtils]: 1: Hoare triple {58689#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {58691#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,090 INFO L290 TraceCheckUtils]: 2: Hoare triple {58691#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {58691#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,090 INFO L290 TraceCheckUtils]: 3: Hoare triple {58691#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {58691#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,090 INFO L290 TraceCheckUtils]: 4: Hoare triple {58691#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {58691#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,090 INFO L290 TraceCheckUtils]: 5: Hoare triple {58691#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {58691#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,091 INFO L290 TraceCheckUtils]: 6: Hoare triple {58691#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {58691#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,091 INFO L290 TraceCheckUtils]: 7: Hoare triple {58691#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {58691#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,091 INFO L290 TraceCheckUtils]: 8: Hoare triple {58691#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {58691#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,092 INFO L290 TraceCheckUtils]: 9: Hoare triple {58691#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {58691#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,092 INFO L290 TraceCheckUtils]: 10: Hoare triple {58691#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {58691#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:27,092 INFO L290 TraceCheckUtils]: 11: Hoare triple {58691#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {58690#false} is VALID [2022-02-21 04:23:27,092 INFO L290 TraceCheckUtils]: 12: Hoare triple {58690#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {58690#false} is VALID [2022-02-21 04:23:27,092 INFO L290 TraceCheckUtils]: 13: Hoare triple {58690#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {58690#false} is VALID [2022-02-21 04:23:27,093 INFO L290 TraceCheckUtils]: 14: Hoare triple {58690#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {58690#false} is VALID [2022-02-21 04:23:27,093 INFO L290 TraceCheckUtils]: 15: Hoare triple {58690#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {58690#false} is VALID [2022-02-21 04:23:27,093 INFO L290 TraceCheckUtils]: 16: Hoare triple {58690#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {58690#false} is VALID [2022-02-21 04:23:27,093 INFO L290 TraceCheckUtils]: 17: Hoare triple {58690#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {58690#false} is VALID [2022-02-21 04:23:27,093 INFO L290 TraceCheckUtils]: 18: Hoare triple {58690#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {58690#false} is VALID [2022-02-21 04:23:27,093 INFO L290 TraceCheckUtils]: 19: Hoare triple {58690#false} assume 0 == ~M_E~0;~M_E~0 := 1; {58690#false} is VALID [2022-02-21 04:23:27,093 INFO L290 TraceCheckUtils]: 20: Hoare triple {58690#false} assume !(0 == ~T1_E~0); {58690#false} is VALID [2022-02-21 04:23:27,093 INFO L290 TraceCheckUtils]: 21: Hoare triple {58690#false} assume !(0 == ~T2_E~0); {58690#false} is VALID [2022-02-21 04:23:27,094 INFO L290 TraceCheckUtils]: 22: Hoare triple {58690#false} assume !(0 == ~T3_E~0); {58690#false} is VALID [2022-02-21 04:23:27,094 INFO L290 TraceCheckUtils]: 23: Hoare triple {58690#false} assume !(0 == ~T4_E~0); {58690#false} is VALID [2022-02-21 04:23:27,094 INFO L290 TraceCheckUtils]: 24: Hoare triple {58690#false} assume !(0 == ~T5_E~0); {58690#false} is VALID [2022-02-21 04:23:27,094 INFO L290 TraceCheckUtils]: 25: Hoare triple {58690#false} assume !(0 == ~T6_E~0); {58690#false} is VALID [2022-02-21 04:23:27,094 INFO L290 TraceCheckUtils]: 26: Hoare triple {58690#false} assume !(0 == ~T7_E~0); {58690#false} is VALID [2022-02-21 04:23:27,094 INFO L290 TraceCheckUtils]: 27: Hoare triple {58690#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {58690#false} is VALID [2022-02-21 04:23:27,094 INFO L290 TraceCheckUtils]: 28: Hoare triple {58690#false} assume !(0 == ~T9_E~0); {58690#false} is VALID [2022-02-21 04:23:27,094 INFO L290 TraceCheckUtils]: 29: Hoare triple {58690#false} assume !(0 == ~T10_E~0); {58690#false} is VALID [2022-02-21 04:23:27,095 INFO L290 TraceCheckUtils]: 30: Hoare triple {58690#false} assume !(0 == ~T11_E~0); {58690#false} is VALID [2022-02-21 04:23:27,095 INFO L290 TraceCheckUtils]: 31: Hoare triple {58690#false} assume !(0 == ~T12_E~0); {58690#false} is VALID [2022-02-21 04:23:27,095 INFO L290 TraceCheckUtils]: 32: Hoare triple {58690#false} assume !(0 == ~T13_E~0); {58690#false} is VALID [2022-02-21 04:23:27,095 INFO L290 TraceCheckUtils]: 33: Hoare triple {58690#false} assume !(0 == ~E_M~0); {58690#false} is VALID [2022-02-21 04:23:27,095 INFO L290 TraceCheckUtils]: 34: Hoare triple {58690#false} assume !(0 == ~E_1~0); {58690#false} is VALID [2022-02-21 04:23:27,095 INFO L290 TraceCheckUtils]: 35: Hoare triple {58690#false} assume 0 == ~E_2~0;~E_2~0 := 1; {58690#false} is VALID [2022-02-21 04:23:27,095 INFO L290 TraceCheckUtils]: 36: Hoare triple {58690#false} assume !(0 == ~E_3~0); {58690#false} is VALID [2022-02-21 04:23:27,096 INFO L290 TraceCheckUtils]: 37: Hoare triple {58690#false} assume !(0 == ~E_4~0); {58690#false} is VALID [2022-02-21 04:23:27,096 INFO L290 TraceCheckUtils]: 38: Hoare triple {58690#false} assume !(0 == ~E_5~0); {58690#false} is VALID [2022-02-21 04:23:27,096 INFO L290 TraceCheckUtils]: 39: Hoare triple {58690#false} assume !(0 == ~E_6~0); {58690#false} is VALID [2022-02-21 04:23:27,096 INFO L290 TraceCheckUtils]: 40: Hoare triple {58690#false} assume !(0 == ~E_7~0); {58690#false} is VALID [2022-02-21 04:23:27,096 INFO L290 TraceCheckUtils]: 41: Hoare triple {58690#false} assume !(0 == ~E_8~0); {58690#false} is VALID [2022-02-21 04:23:27,096 INFO L290 TraceCheckUtils]: 42: Hoare triple {58690#false} assume !(0 == ~E_9~0); {58690#false} is VALID [2022-02-21 04:23:27,096 INFO L290 TraceCheckUtils]: 43: Hoare triple {58690#false} assume 0 == ~E_10~0;~E_10~0 := 1; {58690#false} is VALID [2022-02-21 04:23:27,096 INFO L290 TraceCheckUtils]: 44: Hoare triple {58690#false} assume !(0 == ~E_11~0); {58690#false} is VALID [2022-02-21 04:23:27,097 INFO L290 TraceCheckUtils]: 45: Hoare triple {58690#false} assume !(0 == ~E_12~0); {58690#false} is VALID [2022-02-21 04:23:27,097 INFO L290 TraceCheckUtils]: 46: Hoare triple {58690#false} assume !(0 == ~E_13~0); {58690#false} is VALID [2022-02-21 04:23:27,097 INFO L290 TraceCheckUtils]: 47: Hoare triple {58690#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {58690#false} is VALID [2022-02-21 04:23:27,097 INFO L290 TraceCheckUtils]: 48: Hoare triple {58690#false} assume !(1 == ~m_pc~0); {58690#false} is VALID [2022-02-21 04:23:27,097 INFO L290 TraceCheckUtils]: 49: Hoare triple {58690#false} is_master_triggered_~__retres1~0#1 := 0; {58690#false} is VALID [2022-02-21 04:23:27,097 INFO L290 TraceCheckUtils]: 50: Hoare triple {58690#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {58690#false} is VALID [2022-02-21 04:23:27,097 INFO L290 TraceCheckUtils]: 51: Hoare triple {58690#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {58690#false} is VALID [2022-02-21 04:23:27,098 INFO L290 TraceCheckUtils]: 52: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp~1#1); {58690#false} is VALID [2022-02-21 04:23:27,098 INFO L290 TraceCheckUtils]: 53: Hoare triple {58690#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {58690#false} is VALID [2022-02-21 04:23:27,098 INFO L290 TraceCheckUtils]: 54: Hoare triple {58690#false} assume 1 == ~t1_pc~0; {58690#false} is VALID [2022-02-21 04:23:27,098 INFO L290 TraceCheckUtils]: 55: Hoare triple {58690#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {58690#false} is VALID [2022-02-21 04:23:27,098 INFO L290 TraceCheckUtils]: 56: Hoare triple {58690#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {58690#false} is VALID [2022-02-21 04:23:27,098 INFO L290 TraceCheckUtils]: 57: Hoare triple {58690#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {58690#false} is VALID [2022-02-21 04:23:27,098 INFO L290 TraceCheckUtils]: 58: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___0~0#1); {58690#false} is VALID [2022-02-21 04:23:27,098 INFO L290 TraceCheckUtils]: 59: Hoare triple {58690#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {58690#false} is VALID [2022-02-21 04:23:27,099 INFO L290 TraceCheckUtils]: 60: Hoare triple {58690#false} assume 1 == ~t2_pc~0; {58690#false} is VALID [2022-02-21 04:23:27,099 INFO L290 TraceCheckUtils]: 61: Hoare triple {58690#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {58690#false} is VALID [2022-02-21 04:23:27,099 INFO L290 TraceCheckUtils]: 62: Hoare triple {58690#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {58690#false} is VALID [2022-02-21 04:23:27,099 INFO L290 TraceCheckUtils]: 63: Hoare triple {58690#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {58690#false} is VALID [2022-02-21 04:23:27,099 INFO L290 TraceCheckUtils]: 64: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___1~0#1); {58690#false} is VALID [2022-02-21 04:23:27,099 INFO L290 TraceCheckUtils]: 65: Hoare triple {58690#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {58690#false} is VALID [2022-02-21 04:23:27,099 INFO L290 TraceCheckUtils]: 66: Hoare triple {58690#false} assume !(1 == ~t3_pc~0); {58690#false} is VALID [2022-02-21 04:23:27,099 INFO L290 TraceCheckUtils]: 67: Hoare triple {58690#false} is_transmit3_triggered_~__retres1~3#1 := 0; {58690#false} is VALID [2022-02-21 04:23:27,100 INFO L290 TraceCheckUtils]: 68: Hoare triple {58690#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {58690#false} is VALID [2022-02-21 04:23:27,100 INFO L290 TraceCheckUtils]: 69: Hoare triple {58690#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {58690#false} is VALID [2022-02-21 04:23:27,100 INFO L290 TraceCheckUtils]: 70: Hoare triple {58690#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {58690#false} is VALID [2022-02-21 04:23:27,100 INFO L290 TraceCheckUtils]: 71: Hoare triple {58690#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {58690#false} is VALID [2022-02-21 04:23:27,100 INFO L290 TraceCheckUtils]: 72: Hoare triple {58690#false} assume 1 == ~t4_pc~0; {58690#false} is VALID [2022-02-21 04:23:27,100 INFO L290 TraceCheckUtils]: 73: Hoare triple {58690#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {58690#false} is VALID [2022-02-21 04:23:27,100 INFO L290 TraceCheckUtils]: 74: Hoare triple {58690#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {58690#false} is VALID [2022-02-21 04:23:27,101 INFO L290 TraceCheckUtils]: 75: Hoare triple {58690#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {58690#false} is VALID [2022-02-21 04:23:27,101 INFO L290 TraceCheckUtils]: 76: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___3~0#1); {58690#false} is VALID [2022-02-21 04:23:27,101 INFO L290 TraceCheckUtils]: 77: Hoare triple {58690#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {58690#false} is VALID [2022-02-21 04:23:27,101 INFO L290 TraceCheckUtils]: 78: Hoare triple {58690#false} assume !(1 == ~t5_pc~0); {58690#false} is VALID [2022-02-21 04:23:27,101 INFO L290 TraceCheckUtils]: 79: Hoare triple {58690#false} is_transmit5_triggered_~__retres1~5#1 := 0; {58690#false} is VALID [2022-02-21 04:23:27,101 INFO L290 TraceCheckUtils]: 80: Hoare triple {58690#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {58690#false} is VALID [2022-02-21 04:23:27,101 INFO L290 TraceCheckUtils]: 81: Hoare triple {58690#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {58690#false} is VALID [2022-02-21 04:23:27,101 INFO L290 TraceCheckUtils]: 82: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___4~0#1); {58690#false} is VALID [2022-02-21 04:23:27,102 INFO L290 TraceCheckUtils]: 83: Hoare triple {58690#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {58690#false} is VALID [2022-02-21 04:23:27,102 INFO L290 TraceCheckUtils]: 84: Hoare triple {58690#false} assume 1 == ~t6_pc~0; {58690#false} is VALID [2022-02-21 04:23:27,102 INFO L290 TraceCheckUtils]: 85: Hoare triple {58690#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {58690#false} is VALID [2022-02-21 04:23:27,102 INFO L290 TraceCheckUtils]: 86: Hoare triple {58690#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {58690#false} is VALID [2022-02-21 04:23:27,102 INFO L290 TraceCheckUtils]: 87: Hoare triple {58690#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {58690#false} is VALID [2022-02-21 04:23:27,102 INFO L290 TraceCheckUtils]: 88: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___5~0#1); {58690#false} is VALID [2022-02-21 04:23:27,102 INFO L290 TraceCheckUtils]: 89: Hoare triple {58690#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {58690#false} is VALID [2022-02-21 04:23:27,103 INFO L290 TraceCheckUtils]: 90: Hoare triple {58690#false} assume !(1 == ~t7_pc~0); {58690#false} is VALID [2022-02-21 04:23:27,103 INFO L290 TraceCheckUtils]: 91: Hoare triple {58690#false} is_transmit7_triggered_~__retres1~7#1 := 0; {58690#false} is VALID [2022-02-21 04:23:27,103 INFO L290 TraceCheckUtils]: 92: Hoare triple {58690#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {58690#false} is VALID [2022-02-21 04:23:27,103 INFO L290 TraceCheckUtils]: 93: Hoare triple {58690#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {58690#false} is VALID [2022-02-21 04:23:27,103 INFO L290 TraceCheckUtils]: 94: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___6~0#1); {58690#false} is VALID [2022-02-21 04:23:27,103 INFO L290 TraceCheckUtils]: 95: Hoare triple {58690#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {58690#false} is VALID [2022-02-21 04:23:27,103 INFO L290 TraceCheckUtils]: 96: Hoare triple {58690#false} assume 1 == ~t8_pc~0; {58690#false} is VALID [2022-02-21 04:23:27,103 INFO L290 TraceCheckUtils]: 97: Hoare triple {58690#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {58690#false} is VALID [2022-02-21 04:23:27,104 INFO L290 TraceCheckUtils]: 98: Hoare triple {58690#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {58690#false} is VALID [2022-02-21 04:23:27,104 INFO L290 TraceCheckUtils]: 99: Hoare triple {58690#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {58690#false} is VALID [2022-02-21 04:23:27,104 INFO L290 TraceCheckUtils]: 100: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___7~0#1); {58690#false} is VALID [2022-02-21 04:23:27,104 INFO L290 TraceCheckUtils]: 101: Hoare triple {58690#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {58690#false} is VALID [2022-02-21 04:23:27,104 INFO L290 TraceCheckUtils]: 102: Hoare triple {58690#false} assume 1 == ~t9_pc~0; {58690#false} is VALID [2022-02-21 04:23:27,104 INFO L290 TraceCheckUtils]: 103: Hoare triple {58690#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {58690#false} is VALID [2022-02-21 04:23:27,104 INFO L290 TraceCheckUtils]: 104: Hoare triple {58690#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {58690#false} is VALID [2022-02-21 04:23:27,104 INFO L290 TraceCheckUtils]: 105: Hoare triple {58690#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {58690#false} is VALID [2022-02-21 04:23:27,105 INFO L290 TraceCheckUtils]: 106: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___8~0#1); {58690#false} is VALID [2022-02-21 04:23:27,105 INFO L290 TraceCheckUtils]: 107: Hoare triple {58690#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {58690#false} is VALID [2022-02-21 04:23:27,105 INFO L290 TraceCheckUtils]: 108: Hoare triple {58690#false} assume !(1 == ~t10_pc~0); {58690#false} is VALID [2022-02-21 04:23:27,105 INFO L290 TraceCheckUtils]: 109: Hoare triple {58690#false} is_transmit10_triggered_~__retres1~10#1 := 0; {58690#false} is VALID [2022-02-21 04:23:27,105 INFO L290 TraceCheckUtils]: 110: Hoare triple {58690#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {58690#false} is VALID [2022-02-21 04:23:27,105 INFO L290 TraceCheckUtils]: 111: Hoare triple {58690#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {58690#false} is VALID [2022-02-21 04:23:27,105 INFO L290 TraceCheckUtils]: 112: Hoare triple {58690#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {58690#false} is VALID [2022-02-21 04:23:27,106 INFO L290 TraceCheckUtils]: 113: Hoare triple {58690#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {58690#false} is VALID [2022-02-21 04:23:27,106 INFO L290 TraceCheckUtils]: 114: Hoare triple {58690#false} assume 1 == ~t11_pc~0; {58690#false} is VALID [2022-02-21 04:23:27,106 INFO L290 TraceCheckUtils]: 115: Hoare triple {58690#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {58690#false} is VALID [2022-02-21 04:23:27,106 INFO L290 TraceCheckUtils]: 116: Hoare triple {58690#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {58690#false} is VALID [2022-02-21 04:23:27,106 INFO L290 TraceCheckUtils]: 117: Hoare triple {58690#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {58690#false} is VALID [2022-02-21 04:23:27,106 INFO L290 TraceCheckUtils]: 118: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___10~0#1); {58690#false} is VALID [2022-02-21 04:23:27,106 INFO L290 TraceCheckUtils]: 119: Hoare triple {58690#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {58690#false} is VALID [2022-02-21 04:23:27,106 INFO L290 TraceCheckUtils]: 120: Hoare triple {58690#false} assume !(1 == ~t12_pc~0); {58690#false} is VALID [2022-02-21 04:23:27,107 INFO L290 TraceCheckUtils]: 121: Hoare triple {58690#false} is_transmit12_triggered_~__retres1~12#1 := 0; {58690#false} is VALID [2022-02-21 04:23:27,107 INFO L290 TraceCheckUtils]: 122: Hoare triple {58690#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {58690#false} is VALID [2022-02-21 04:23:27,107 INFO L290 TraceCheckUtils]: 123: Hoare triple {58690#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {58690#false} is VALID [2022-02-21 04:23:27,107 INFO L290 TraceCheckUtils]: 124: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___11~0#1); {58690#false} is VALID [2022-02-21 04:23:27,107 INFO L290 TraceCheckUtils]: 125: Hoare triple {58690#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {58690#false} is VALID [2022-02-21 04:23:27,107 INFO L290 TraceCheckUtils]: 126: Hoare triple {58690#false} assume 1 == ~t13_pc~0; {58690#false} is VALID [2022-02-21 04:23:27,107 INFO L290 TraceCheckUtils]: 127: Hoare triple {58690#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {58690#false} is VALID [2022-02-21 04:23:27,107 INFO L290 TraceCheckUtils]: 128: Hoare triple {58690#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {58690#false} is VALID [2022-02-21 04:23:27,108 INFO L290 TraceCheckUtils]: 129: Hoare triple {58690#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {58690#false} is VALID [2022-02-21 04:23:27,108 INFO L290 TraceCheckUtils]: 130: Hoare triple {58690#false} assume !(0 != activate_threads_~tmp___12~0#1); {58690#false} is VALID [2022-02-21 04:23:27,108 INFO L290 TraceCheckUtils]: 131: Hoare triple {58690#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {58690#false} is VALID [2022-02-21 04:23:27,108 INFO L290 TraceCheckUtils]: 132: Hoare triple {58690#false} assume !(1 == ~M_E~0); {58690#false} is VALID [2022-02-21 04:23:27,108 INFO L290 TraceCheckUtils]: 133: Hoare triple {58690#false} assume !(1 == ~T1_E~0); {58690#false} is VALID [2022-02-21 04:23:27,108 INFO L290 TraceCheckUtils]: 134: Hoare triple {58690#false} assume !(1 == ~T2_E~0); {58690#false} is VALID [2022-02-21 04:23:27,108 INFO L290 TraceCheckUtils]: 135: Hoare triple {58690#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {58690#false} is VALID [2022-02-21 04:23:27,109 INFO L290 TraceCheckUtils]: 136: Hoare triple {58690#false} assume !(1 == ~T4_E~0); {58690#false} is VALID [2022-02-21 04:23:27,109 INFO L290 TraceCheckUtils]: 137: Hoare triple {58690#false} assume !(1 == ~T5_E~0); {58690#false} is VALID [2022-02-21 04:23:27,109 INFO L290 TraceCheckUtils]: 138: Hoare triple {58690#false} assume !(1 == ~T6_E~0); {58690#false} is VALID [2022-02-21 04:23:27,109 INFO L290 TraceCheckUtils]: 139: Hoare triple {58690#false} assume !(1 == ~T7_E~0); {58690#false} is VALID [2022-02-21 04:23:27,109 INFO L290 TraceCheckUtils]: 140: Hoare triple {58690#false} assume !(1 == ~T8_E~0); {58690#false} is VALID [2022-02-21 04:23:27,109 INFO L290 TraceCheckUtils]: 141: Hoare triple {58690#false} assume !(1 == ~T9_E~0); {58690#false} is VALID [2022-02-21 04:23:27,109 INFO L290 TraceCheckUtils]: 142: Hoare triple {58690#false} assume !(1 == ~T10_E~0); {58690#false} is VALID [2022-02-21 04:23:27,109 INFO L290 TraceCheckUtils]: 143: Hoare triple {58690#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {58690#false} is VALID [2022-02-21 04:23:27,110 INFO L290 TraceCheckUtils]: 144: Hoare triple {58690#false} assume !(1 == ~T12_E~0); {58690#false} is VALID [2022-02-21 04:23:27,110 INFO L290 TraceCheckUtils]: 145: Hoare triple {58690#false} assume !(1 == ~T13_E~0); {58690#false} is VALID [2022-02-21 04:23:27,110 INFO L290 TraceCheckUtils]: 146: Hoare triple {58690#false} assume !(1 == ~E_M~0); {58690#false} is VALID [2022-02-21 04:23:27,110 INFO L290 TraceCheckUtils]: 147: Hoare triple {58690#false} assume !(1 == ~E_1~0); {58690#false} is VALID [2022-02-21 04:23:27,110 INFO L290 TraceCheckUtils]: 148: Hoare triple {58690#false} assume !(1 == ~E_2~0); {58690#false} is VALID [2022-02-21 04:23:27,110 INFO L290 TraceCheckUtils]: 149: Hoare triple {58690#false} assume !(1 == ~E_3~0); {58690#false} is VALID [2022-02-21 04:23:27,110 INFO L290 TraceCheckUtils]: 150: Hoare triple {58690#false} assume !(1 == ~E_4~0); {58690#false} is VALID [2022-02-21 04:23:27,111 INFO L290 TraceCheckUtils]: 151: Hoare triple {58690#false} assume 1 == ~E_5~0;~E_5~0 := 2; {58690#false} is VALID [2022-02-21 04:23:27,111 INFO L290 TraceCheckUtils]: 152: Hoare triple {58690#false} assume !(1 == ~E_6~0); {58690#false} is VALID [2022-02-21 04:23:27,111 INFO L290 TraceCheckUtils]: 153: Hoare triple {58690#false} assume !(1 == ~E_7~0); {58690#false} is VALID [2022-02-21 04:23:27,111 INFO L290 TraceCheckUtils]: 154: Hoare triple {58690#false} assume !(1 == ~E_8~0); {58690#false} is VALID [2022-02-21 04:23:27,111 INFO L290 TraceCheckUtils]: 155: Hoare triple {58690#false} assume !(1 == ~E_9~0); {58690#false} is VALID [2022-02-21 04:23:27,111 INFO L290 TraceCheckUtils]: 156: Hoare triple {58690#false} assume !(1 == ~E_10~0); {58690#false} is VALID [2022-02-21 04:23:27,111 INFO L290 TraceCheckUtils]: 157: Hoare triple {58690#false} assume !(1 == ~E_11~0); {58690#false} is VALID [2022-02-21 04:23:27,111 INFO L290 TraceCheckUtils]: 158: Hoare triple {58690#false} assume !(1 == ~E_12~0); {58690#false} is VALID [2022-02-21 04:23:27,112 INFO L290 TraceCheckUtils]: 159: Hoare triple {58690#false} assume 1 == ~E_13~0;~E_13~0 := 2; {58690#false} is VALID [2022-02-21 04:23:27,112 INFO L290 TraceCheckUtils]: 160: Hoare triple {58690#false} assume { :end_inline_reset_delta_events } true; {58690#false} is VALID [2022-02-21 04:23:27,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:27,112 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:27,112 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776711619] [2022-02-21 04:23:27,112 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776711619] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:27,113 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:27,113 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:27,114 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1321295148] [2022-02-21 04:23:27,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:27,114 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:27,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:27,115 INFO L85 PathProgramCache]: Analyzing trace with hash -1762520861, now seen corresponding path program 2 times [2022-02-21 04:23:27,115 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:27,115 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412594256] [2022-02-21 04:23:27,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:27,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:27,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:27,140 INFO L290 TraceCheckUtils]: 0: Hoare triple {58692#true} assume !false; {58692#true} is VALID [2022-02-21 04:23:27,140 INFO L290 TraceCheckUtils]: 1: Hoare triple {58692#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {58692#true} is VALID [2022-02-21 04:23:27,140 INFO L290 TraceCheckUtils]: 2: Hoare triple {58692#true} assume !false; {58692#true} is VALID [2022-02-21 04:23:27,140 INFO L290 TraceCheckUtils]: 3: Hoare triple {58692#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {58692#true} is VALID [2022-02-21 04:23:27,140 INFO L290 TraceCheckUtils]: 4: Hoare triple {58692#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {58692#true} is VALID [2022-02-21 04:23:27,141 INFO L290 TraceCheckUtils]: 5: Hoare triple {58692#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {58692#true} is VALID [2022-02-21 04:23:27,141 INFO L290 TraceCheckUtils]: 6: Hoare triple {58692#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {58692#true} is VALID [2022-02-21 04:23:27,141 INFO L290 TraceCheckUtils]: 7: Hoare triple {58692#true} assume !(0 != eval_~tmp~0#1); {58692#true} is VALID [2022-02-21 04:23:27,141 INFO L290 TraceCheckUtils]: 8: Hoare triple {58692#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {58692#true} is VALID [2022-02-21 04:23:27,141 INFO L290 TraceCheckUtils]: 9: Hoare triple {58692#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {58692#true} is VALID [2022-02-21 04:23:27,141 INFO L290 TraceCheckUtils]: 10: Hoare triple {58692#true} assume 0 == ~M_E~0;~M_E~0 := 1; {58692#true} is VALID [2022-02-21 04:23:27,141 INFO L290 TraceCheckUtils]: 11: Hoare triple {58692#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {58692#true} is VALID [2022-02-21 04:23:27,142 INFO L290 TraceCheckUtils]: 12: Hoare triple {58692#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {58692#true} is VALID [2022-02-21 04:23:27,142 INFO L290 TraceCheckUtils]: 13: Hoare triple {58692#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {58692#true} is VALID [2022-02-21 04:23:27,142 INFO L290 TraceCheckUtils]: 14: Hoare triple {58692#true} assume !(0 == ~T4_E~0); {58692#true} is VALID [2022-02-21 04:23:27,142 INFO L290 TraceCheckUtils]: 15: Hoare triple {58692#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {58692#true} is VALID [2022-02-21 04:23:27,142 INFO L290 TraceCheckUtils]: 16: Hoare triple {58692#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {58692#true} is VALID [2022-02-21 04:23:27,142 INFO L290 TraceCheckUtils]: 17: Hoare triple {58692#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,143 INFO L290 TraceCheckUtils]: 18: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,143 INFO L290 TraceCheckUtils]: 19: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,143 INFO L290 TraceCheckUtils]: 20: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,144 INFO L290 TraceCheckUtils]: 21: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,144 INFO L290 TraceCheckUtils]: 22: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,144 INFO L290 TraceCheckUtils]: 23: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,144 INFO L290 TraceCheckUtils]: 24: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,145 INFO L290 TraceCheckUtils]: 25: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,145 INFO L290 TraceCheckUtils]: 26: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,145 INFO L290 TraceCheckUtils]: 27: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,146 INFO L290 TraceCheckUtils]: 28: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,146 INFO L290 TraceCheckUtils]: 29: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,146 INFO L290 TraceCheckUtils]: 30: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,146 INFO L290 TraceCheckUtils]: 31: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,147 INFO L290 TraceCheckUtils]: 32: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,147 INFO L290 TraceCheckUtils]: 33: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,147 INFO L290 TraceCheckUtils]: 34: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,148 INFO L290 TraceCheckUtils]: 35: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,148 INFO L290 TraceCheckUtils]: 36: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,148 INFO L290 TraceCheckUtils]: 37: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,148 INFO L290 TraceCheckUtils]: 38: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,149 INFO L290 TraceCheckUtils]: 39: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,149 INFO L290 TraceCheckUtils]: 40: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,149 INFO L290 TraceCheckUtils]: 41: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,150 INFO L290 TraceCheckUtils]: 42: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,150 INFO L290 TraceCheckUtils]: 43: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,150 INFO L290 TraceCheckUtils]: 44: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,151 INFO L290 TraceCheckUtils]: 45: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,151 INFO L290 TraceCheckUtils]: 46: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,151 INFO L290 TraceCheckUtils]: 47: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,151 INFO L290 TraceCheckUtils]: 48: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,152 INFO L290 TraceCheckUtils]: 49: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,152 INFO L290 TraceCheckUtils]: 50: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,152 INFO L290 TraceCheckUtils]: 51: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,153 INFO L290 TraceCheckUtils]: 52: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,153 INFO L290 TraceCheckUtils]: 53: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,153 INFO L290 TraceCheckUtils]: 54: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,153 INFO L290 TraceCheckUtils]: 55: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,154 INFO L290 TraceCheckUtils]: 56: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,154 INFO L290 TraceCheckUtils]: 57: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,154 INFO L290 TraceCheckUtils]: 58: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,155 INFO L290 TraceCheckUtils]: 59: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,155 INFO L290 TraceCheckUtils]: 60: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,155 INFO L290 TraceCheckUtils]: 61: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,155 INFO L290 TraceCheckUtils]: 62: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,156 INFO L290 TraceCheckUtils]: 63: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,156 INFO L290 TraceCheckUtils]: 64: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,156 INFO L290 TraceCheckUtils]: 65: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,157 INFO L290 TraceCheckUtils]: 66: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,157 INFO L290 TraceCheckUtils]: 67: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,157 INFO L290 TraceCheckUtils]: 68: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,157 INFO L290 TraceCheckUtils]: 69: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t5_pc~0); {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,158 INFO L290 TraceCheckUtils]: 70: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,158 INFO L290 TraceCheckUtils]: 71: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,158 INFO L290 TraceCheckUtils]: 72: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,159 INFO L290 TraceCheckUtils]: 73: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,159 INFO L290 TraceCheckUtils]: 74: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,159 INFO L290 TraceCheckUtils]: 75: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,160 INFO L290 TraceCheckUtils]: 76: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,160 INFO L290 TraceCheckUtils]: 77: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,160 INFO L290 TraceCheckUtils]: 78: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,160 INFO L290 TraceCheckUtils]: 79: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,161 INFO L290 TraceCheckUtils]: 80: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,161 INFO L290 TraceCheckUtils]: 81: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,161 INFO L290 TraceCheckUtils]: 82: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,162 INFO L290 TraceCheckUtils]: 83: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,162 INFO L290 TraceCheckUtils]: 84: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,162 INFO L290 TraceCheckUtils]: 85: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,162 INFO L290 TraceCheckUtils]: 86: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,163 INFO L290 TraceCheckUtils]: 87: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t8_pc~0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,163 INFO L290 TraceCheckUtils]: 88: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,163 INFO L290 TraceCheckUtils]: 89: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,164 INFO L290 TraceCheckUtils]: 90: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,164 INFO L290 TraceCheckUtils]: 91: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,164 INFO L290 TraceCheckUtils]: 92: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,164 INFO L290 TraceCheckUtils]: 93: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,165 INFO L290 TraceCheckUtils]: 94: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,165 INFO L290 TraceCheckUtils]: 95: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,165 INFO L290 TraceCheckUtils]: 96: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,166 INFO L290 TraceCheckUtils]: 97: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,166 INFO L290 TraceCheckUtils]: 98: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,166 INFO L290 TraceCheckUtils]: 99: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t10_pc~0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,166 INFO L290 TraceCheckUtils]: 100: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,167 INFO L290 TraceCheckUtils]: 101: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,167 INFO L290 TraceCheckUtils]: 102: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,167 INFO L290 TraceCheckUtils]: 103: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,168 INFO L290 TraceCheckUtils]: 104: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,168 INFO L290 TraceCheckUtils]: 105: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,168 INFO L290 TraceCheckUtils]: 106: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,169 INFO L290 TraceCheckUtils]: 107: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,169 INFO L290 TraceCheckUtils]: 108: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,169 INFO L290 TraceCheckUtils]: 109: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,169 INFO L290 TraceCheckUtils]: 110: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,170 INFO L290 TraceCheckUtils]: 111: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,170 INFO L290 TraceCheckUtils]: 112: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,170 INFO L290 TraceCheckUtils]: 113: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,171 INFO L290 TraceCheckUtils]: 114: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,171 INFO L290 TraceCheckUtils]: 115: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,171 INFO L290 TraceCheckUtils]: 116: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,171 INFO L290 TraceCheckUtils]: 117: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t13_pc~0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,172 INFO L290 TraceCheckUtils]: 118: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,172 INFO L290 TraceCheckUtils]: 119: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,172 INFO L290 TraceCheckUtils]: 120: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,173 INFO L290 TraceCheckUtils]: 121: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,173 INFO L290 TraceCheckUtils]: 122: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,173 INFO L290 TraceCheckUtils]: 123: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,173 INFO L290 TraceCheckUtils]: 124: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,174 INFO L290 TraceCheckUtils]: 125: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,174 INFO L290 TraceCheckUtils]: 126: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,174 INFO L290 TraceCheckUtils]: 127: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 128: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 129: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {58694#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 130: Hoare triple {58694#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {58693#false} is VALID [2022-02-21 04:23:27,175 INFO L290 TraceCheckUtils]: 131: Hoare triple {58693#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 132: Hoare triple {58693#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 133: Hoare triple {58693#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 134: Hoare triple {58693#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 135: Hoare triple {58693#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 136: Hoare triple {58693#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 137: Hoare triple {58693#false} assume 1 == ~E_M~0;~E_M~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,176 INFO L290 TraceCheckUtils]: 138: Hoare triple {58693#false} assume !(1 == ~E_1~0); {58693#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 139: Hoare triple {58693#false} assume 1 == ~E_2~0;~E_2~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 140: Hoare triple {58693#false} assume 1 == ~E_3~0;~E_3~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 141: Hoare triple {58693#false} assume 1 == ~E_4~0;~E_4~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 142: Hoare triple {58693#false} assume 1 == ~E_5~0;~E_5~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 143: Hoare triple {58693#false} assume 1 == ~E_6~0;~E_6~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 144: Hoare triple {58693#false} assume 1 == ~E_7~0;~E_7~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 145: Hoare triple {58693#false} assume 1 == ~E_8~0;~E_8~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,177 INFO L290 TraceCheckUtils]: 146: Hoare triple {58693#false} assume !(1 == ~E_9~0); {58693#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 147: Hoare triple {58693#false} assume 1 == ~E_10~0;~E_10~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 148: Hoare triple {58693#false} assume 1 == ~E_11~0;~E_11~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 149: Hoare triple {58693#false} assume 1 == ~E_12~0;~E_12~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 150: Hoare triple {58693#false} assume 1 == ~E_13~0;~E_13~0 := 2; {58693#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 151: Hoare triple {58693#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {58693#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 152: Hoare triple {58693#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {58693#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 153: Hoare triple {58693#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {58693#false} is VALID [2022-02-21 04:23:27,178 INFO L290 TraceCheckUtils]: 154: Hoare triple {58693#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {58693#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 155: Hoare triple {58693#false} assume !(0 == start_simulation_~tmp~3#1); {58693#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 156: Hoare triple {58693#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {58693#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 157: Hoare triple {58693#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {58693#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 158: Hoare triple {58693#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {58693#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 159: Hoare triple {58693#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {58693#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 160: Hoare triple {58693#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {58693#false} is VALID [2022-02-21 04:23:27,179 INFO L290 TraceCheckUtils]: 161: Hoare triple {58693#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {58693#false} is VALID [2022-02-21 04:23:27,180 INFO L290 TraceCheckUtils]: 162: Hoare triple {58693#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {58693#false} is VALID [2022-02-21 04:23:27,180 INFO L290 TraceCheckUtils]: 163: Hoare triple {58693#false} assume !(0 != start_simulation_~tmp___0~1#1); {58693#false} is VALID [2022-02-21 04:23:27,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:27,180 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:27,182 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412594256] [2022-02-21 04:23:27,183 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412594256] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:27,183 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:27,183 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:27,184 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445450998] [2022-02-21 04:23:27,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:27,184 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:27,184 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:27,185 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:27,185 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:27,185 INFO L87 Difference]: Start difference. First operand 2021 states and 2986 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:28,520 INFO L93 Difference]: Finished difference Result 2021 states and 2985 transitions. [2022-02-21 04:23:28,520 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:28,521 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,611 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:28,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2985 transitions. [2022-02-21 04:23:28,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:28,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2985 transitions. [2022-02-21 04:23:28,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:28,815 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:28,815 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2985 transitions. [2022-02-21 04:23:28,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:28,817 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2022-02-21 04:23:28,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2985 transitions. [2022-02-21 04:23:28,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:28,832 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:28,834 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2985 transitions. Second operand has 2021 states, 2021 states have (on average 1.4769915883226126) internal successors, (2985), 2020 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,835 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2985 transitions. Second operand has 2021 states, 2021 states have (on average 1.4769915883226126) internal successors, (2985), 2020 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,836 INFO L87 Difference]: Start difference. First operand 2021 states and 2985 transitions. Second operand has 2021 states, 2021 states have (on average 1.4769915883226126) internal successors, (2985), 2020 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:28,932 INFO L93 Difference]: Finished difference Result 2021 states and 2985 transitions. [2022-02-21 04:23:28,932 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2985 transitions. [2022-02-21 04:23:28,933 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:28,933 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:28,934 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.4769915883226126) internal successors, (2985), 2020 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2985 transitions. [2022-02-21 04:23:28,935 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.4769915883226126) internal successors, (2985), 2020 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2985 transitions. [2022-02-21 04:23:29,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,016 INFO L93 Difference]: Finished difference Result 2021 states and 2985 transitions. [2022-02-21 04:23:29,017 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2985 transitions. [2022-02-21 04:23:29,018 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:29,018 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:29,018 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:29,018 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:29,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4769915883226126) internal successors, (2985), 2020 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2985 transitions. [2022-02-21 04:23:29,100 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2022-02-21 04:23:29,100 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2022-02-21 04:23:29,100 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:23:29,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2985 transitions. [2022-02-21 04:23:29,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:29,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:29,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:29,104 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:29,104 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:29,104 INFO L791 eck$LassoCheckResult]: Stem: 61592#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 61593#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 61324#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61325#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62715#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 62716#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61511#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61512#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61546#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62383#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62384#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62496#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 62497#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 61330#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 61331#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 62533#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 61855#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 61856#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 62437#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62703#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 62593#L1286-2 assume !(0 == ~T1_E~0); 61239#L1291-1 assume !(0 == ~T2_E~0); 61240#L1296-1 assume !(0 == ~T3_E~0); 61945#L1301-1 assume !(0 == ~T4_E~0); 61946#L1306-1 assume !(0 == ~T5_E~0); 62446#L1311-1 assume !(0 == ~T6_E~0); 61199#L1316-1 assume !(0 == ~T7_E~0); 61200#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 61965#L1326-1 assume !(0 == ~T9_E~0); 61014#L1331-1 assume !(0 == ~T10_E~0); 60720#L1336-1 assume !(0 == ~T11_E~0); 60721#L1341-1 assume !(0 == ~T12_E~0); 60772#L1346-1 assume !(0 == ~T13_E~0); 60773#L1351-1 assume !(0 == ~E_M~0); 61146#L1356-1 assume !(0 == ~E_1~0); 61147#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 62666#L1366-1 assume !(0 == ~E_3~0); 61192#L1371-1 assume !(0 == ~E_4~0); 61193#L1376-1 assume !(0 == ~E_5~0); 62006#L1381-1 assume !(0 == ~E_6~0); 62007#L1386-1 assume !(0 == ~E_7~0); 62694#L1391-1 assume !(0 == ~E_8~0); 62707#L1396-1 assume !(0 == ~E_9~0); 61889#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 61890#L1406-1 assume !(0 == ~E_11~0); 62192#L1411-1 assume !(0 == ~E_12~0); 62193#L1416-1 assume !(0 == ~E_13~0); 61813#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61651#L635 assume !(1 == ~m_pc~0); 60790#L635-2 is_master_triggered_~__retres1~0#1 := 0; 60791#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61141#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61777#L1598 assume !(0 != activate_threads_~tmp~1#1); 60969#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60970#L654 assume 1 == ~t1_pc~0; 61675#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 61676#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62691#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61757#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 61758#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61017#L673 assume 1 == ~t2_pc~0; 61018#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62162#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62163#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62721#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 62728#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61836#L692 assume !(1 == ~t3_pc~0); 61653#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 61654#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61513#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61481#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61482#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61042#L711 assume 1 == ~t4_pc~0; 61043#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61526#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61983#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60745#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 60746#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62714#L730 assume !(1 == ~t5_pc~0); 62096#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 60924#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60925#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 61052#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 61053#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61395#L749 assume 1 == ~t6_pc~0; 61169#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60929#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61361#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61362#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 61584#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60725#L768 assume !(1 == ~t7_pc~0); 60726#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 62030#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60962#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60963#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 62049#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61201#L787 assume 1 == ~t8_pc~0; 61202#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62397#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62561#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62562#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 60770#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60771#L806 assume 1 == ~t9_pc~0; 62408#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60805#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60806#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61054#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 61055#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62391#L825 assume !(1 == ~t10_pc~0); 62392#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 61997#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61998#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61142#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61143#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61726#L844 assume 1 == ~t11_pc~0; 61416#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61417#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61783#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61784#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 62379#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62380#L863 assume !(1 == ~t12_pc~0); 60905#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 60904#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61132#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 62471#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 62472#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61850#L882 assume 1 == ~t13_pc~0; 61851#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 62135#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 62636#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 62439#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 62122#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62123#L1434 assume !(1 == ~M_E~0); 62644#L1434-2 assume !(1 == ~T1_E~0); 62720#L1439-1 assume !(1 == ~T2_E~0); 61035#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61036#L1449-1 assume !(1 == ~T4_E~0); 61478#L1454-1 assume !(1 == ~T5_E~0); 61479#L1459-1 assume !(1 == ~T6_E~0); 62050#L1464-1 assume !(1 == ~T7_E~0); 62051#L1469-1 assume !(1 == ~T8_E~0); 62136#L1474-1 assume !(1 == ~T9_E~0); 61814#L1479-1 assume !(1 == ~T10_E~0); 61815#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 62058#L1489-1 assume !(1 == ~T12_E~0); 61692#L1494-1 assume !(1 == ~T13_E~0); 61693#L1499-1 assume !(1 == ~E_M~0); 61874#L1504-1 assume !(1 == ~E_1~0); 61875#L1509-1 assume !(1 == ~E_2~0); 62488#L1514-1 assume !(1 == ~E_3~0); 62173#L1519-1 assume !(1 == ~E_4~0); 62174#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 62678#L1529-1 assume !(1 == ~E_6~0); 62679#L1534-1 assume !(1 == ~E_7~0); 60825#L1539-1 assume !(1 == ~E_8~0); 60826#L1544-1 assume !(1 == ~E_9~0); 61256#L1549-1 assume !(1 == ~E_10~0); 62656#L1554-1 assume !(1 == ~E_11~0); 62654#L1559-1 assume !(1 == ~E_12~0); 62516#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 62517#L1569-1 assume { :end_inline_reset_delta_events } true; 62672#L1935-2 [2022-02-21 04:23:29,104 INFO L793 eck$LassoCheckResult]: Loop: 62672#L1935-2 assume !false; 60834#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60835#L1261 assume !false; 62062#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 62063#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60965#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61135#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 61136#L1074 assume !(0 != eval_~tmp~0#1); 61493#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 62091#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62492#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 62548#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62267#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62268#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62704#L1301-3 assume !(0 == ~T4_E~0); 62662#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61770#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61069#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61070#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 61175#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 61911#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62176#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62177#L1341-3 assume !(0 == ~T12_E~0); 61471#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 61462#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 61406#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61407#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61987#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60760#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60761#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62503#L1381-3 assume !(0 == ~E_6~0); 62352#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62353#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62534#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62535#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 61140#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60971#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 60972#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 61599#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60849#L635-45 assume 1 == ~m_pc~0; 60850#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61644#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62124#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62378#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61158#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61159#L654-45 assume 1 == ~t1_pc~0; 61979#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 62327#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60812#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60813#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60838#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61665#L673-45 assume !(1 == ~t2_pc~0); 61666#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 61990#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61991#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62616#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 62436#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61283#L692-45 assume !(1 == ~t3_pc~0); 61009#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 61010#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62054#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61337#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61338#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61650#L711-45 assume !(1 == ~t4_pc~0); 61776#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 61775#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61627#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61628#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62031#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61182#L730-45 assume 1 == ~t5_pc~0; 61020#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 61021#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61430#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 61431#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62182#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60993#L749-45 assume !(1 == ~t6_pc~0); 60994#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 62394#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62157#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62158#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62309#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61309#L768-45 assume 1 == ~t7_pc~0; 61310#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61449#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62253#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62254#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62293#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62294#L787-45 assume 1 == ~t8_pc~0; 62462#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61455#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61456#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 61872#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61873#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62181#L806-45 assume 1 == ~t9_pc~0; 62657#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60869#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61694#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61522#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61434#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61435#L825-45 assume !(1 == ~t10_pc~0); 61958#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 61959#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62064#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62065#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 62217#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61077#L844-45 assume !(1 == ~t11_pc~0); 61078#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 61600#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61601#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61617#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 62028#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61117#L863-45 assume 1 == ~t12_pc~0; 61118#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 60718#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60719#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 61234#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61235#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 62034#L882-45 assume 1 == ~t13_pc~0; 62388#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 60737#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60738#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 61346#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 62525#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62141#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62142#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62326#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61031#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61032#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61194#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62131#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62132#L1464-3 assume !(1 == ~T7_E~0); 62578#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62505#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62506#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62580#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61772#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 61773#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 62433#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62068#L1504-3 assume !(1 == ~E_1~0); 62069#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62514#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62554#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61695#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61696#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62601#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 61996#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61450#L1544-3 assume !(1 == ~E_9~0); 61451#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 61966#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 61082#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 61083#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 62232#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 62233#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60967#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61532#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 62203#L1954 assume !(0 == start_simulation_~tmp~3#1); 62205#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 62455#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61250#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 62291#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 62421#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 62422#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 62512#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 62574#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 62672#L1935-2 [2022-02-21 04:23:29,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:29,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2022-02-21 04:23:29,105 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:29,105 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950125665] [2022-02-21 04:23:29,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:29,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:29,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:29,122 INFO L290 TraceCheckUtils]: 0: Hoare triple {66782#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {66782#true} is VALID [2022-02-21 04:23:29,123 INFO L290 TraceCheckUtils]: 1: Hoare triple {66782#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,123 INFO L290 TraceCheckUtils]: 2: Hoare triple {66784#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,123 INFO L290 TraceCheckUtils]: 3: Hoare triple {66784#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,124 INFO L290 TraceCheckUtils]: 4: Hoare triple {66784#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,124 INFO L290 TraceCheckUtils]: 5: Hoare triple {66784#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,124 INFO L290 TraceCheckUtils]: 6: Hoare triple {66784#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,125 INFO L290 TraceCheckUtils]: 7: Hoare triple {66784#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,125 INFO L290 TraceCheckUtils]: 8: Hoare triple {66784#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,125 INFO L290 TraceCheckUtils]: 9: Hoare triple {66784#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,125 INFO L290 TraceCheckUtils]: 10: Hoare triple {66784#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,126 INFO L290 TraceCheckUtils]: 11: Hoare triple {66784#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {66784#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:29,126 INFO L290 TraceCheckUtils]: 12: Hoare triple {66784#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {66783#false} is VALID [2022-02-21 04:23:29,126 INFO L290 TraceCheckUtils]: 13: Hoare triple {66783#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {66783#false} is VALID [2022-02-21 04:23:29,126 INFO L290 TraceCheckUtils]: 14: Hoare triple {66783#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {66783#false} is VALID [2022-02-21 04:23:29,126 INFO L290 TraceCheckUtils]: 15: Hoare triple {66783#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {66783#false} is VALID [2022-02-21 04:23:29,126 INFO L290 TraceCheckUtils]: 16: Hoare triple {66783#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {66783#false} is VALID [2022-02-21 04:23:29,127 INFO L290 TraceCheckUtils]: 17: Hoare triple {66783#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {66783#false} is VALID [2022-02-21 04:23:29,127 INFO L290 TraceCheckUtils]: 18: Hoare triple {66783#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {66783#false} is VALID [2022-02-21 04:23:29,127 INFO L290 TraceCheckUtils]: 19: Hoare triple {66783#false} assume 0 == ~M_E~0;~M_E~0 := 1; {66783#false} is VALID [2022-02-21 04:23:29,127 INFO L290 TraceCheckUtils]: 20: Hoare triple {66783#false} assume !(0 == ~T1_E~0); {66783#false} is VALID [2022-02-21 04:23:29,127 INFO L290 TraceCheckUtils]: 21: Hoare triple {66783#false} assume !(0 == ~T2_E~0); {66783#false} is VALID [2022-02-21 04:23:29,127 INFO L290 TraceCheckUtils]: 22: Hoare triple {66783#false} assume !(0 == ~T3_E~0); {66783#false} is VALID [2022-02-21 04:23:29,127 INFO L290 TraceCheckUtils]: 23: Hoare triple {66783#false} assume !(0 == ~T4_E~0); {66783#false} is VALID [2022-02-21 04:23:29,127 INFO L290 TraceCheckUtils]: 24: Hoare triple {66783#false} assume !(0 == ~T5_E~0); {66783#false} is VALID [2022-02-21 04:23:29,128 INFO L290 TraceCheckUtils]: 25: Hoare triple {66783#false} assume !(0 == ~T6_E~0); {66783#false} is VALID [2022-02-21 04:23:29,128 INFO L290 TraceCheckUtils]: 26: Hoare triple {66783#false} assume !(0 == ~T7_E~0); {66783#false} is VALID [2022-02-21 04:23:29,128 INFO L290 TraceCheckUtils]: 27: Hoare triple {66783#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {66783#false} is VALID [2022-02-21 04:23:29,128 INFO L290 TraceCheckUtils]: 28: Hoare triple {66783#false} assume !(0 == ~T9_E~0); {66783#false} is VALID [2022-02-21 04:23:29,128 INFO L290 TraceCheckUtils]: 29: Hoare triple {66783#false} assume !(0 == ~T10_E~0); {66783#false} is VALID [2022-02-21 04:23:29,128 INFO L290 TraceCheckUtils]: 30: Hoare triple {66783#false} assume !(0 == ~T11_E~0); {66783#false} is VALID [2022-02-21 04:23:29,128 INFO L290 TraceCheckUtils]: 31: Hoare triple {66783#false} assume !(0 == ~T12_E~0); {66783#false} is VALID [2022-02-21 04:23:29,128 INFO L290 TraceCheckUtils]: 32: Hoare triple {66783#false} assume !(0 == ~T13_E~0); {66783#false} is VALID [2022-02-21 04:23:29,129 INFO L290 TraceCheckUtils]: 33: Hoare triple {66783#false} assume !(0 == ~E_M~0); {66783#false} is VALID [2022-02-21 04:23:29,129 INFO L290 TraceCheckUtils]: 34: Hoare triple {66783#false} assume !(0 == ~E_1~0); {66783#false} is VALID [2022-02-21 04:23:29,129 INFO L290 TraceCheckUtils]: 35: Hoare triple {66783#false} assume 0 == ~E_2~0;~E_2~0 := 1; {66783#false} is VALID [2022-02-21 04:23:29,129 INFO L290 TraceCheckUtils]: 36: Hoare triple {66783#false} assume !(0 == ~E_3~0); {66783#false} is VALID [2022-02-21 04:23:29,129 INFO L290 TraceCheckUtils]: 37: Hoare triple {66783#false} assume !(0 == ~E_4~0); {66783#false} is VALID [2022-02-21 04:23:29,129 INFO L290 TraceCheckUtils]: 38: Hoare triple {66783#false} assume !(0 == ~E_5~0); {66783#false} is VALID [2022-02-21 04:23:29,129 INFO L290 TraceCheckUtils]: 39: Hoare triple {66783#false} assume !(0 == ~E_6~0); {66783#false} is VALID [2022-02-21 04:23:29,130 INFO L290 TraceCheckUtils]: 40: Hoare triple {66783#false} assume !(0 == ~E_7~0); {66783#false} is VALID [2022-02-21 04:23:29,130 INFO L290 TraceCheckUtils]: 41: Hoare triple {66783#false} assume !(0 == ~E_8~0); {66783#false} is VALID [2022-02-21 04:23:29,130 INFO L290 TraceCheckUtils]: 42: Hoare triple {66783#false} assume !(0 == ~E_9~0); {66783#false} is VALID [2022-02-21 04:23:29,130 INFO L290 TraceCheckUtils]: 43: Hoare triple {66783#false} assume 0 == ~E_10~0;~E_10~0 := 1; {66783#false} is VALID [2022-02-21 04:23:29,130 INFO L290 TraceCheckUtils]: 44: Hoare triple {66783#false} assume !(0 == ~E_11~0); {66783#false} is VALID [2022-02-21 04:23:29,130 INFO L290 TraceCheckUtils]: 45: Hoare triple {66783#false} assume !(0 == ~E_12~0); {66783#false} is VALID [2022-02-21 04:23:29,130 INFO L290 TraceCheckUtils]: 46: Hoare triple {66783#false} assume !(0 == ~E_13~0); {66783#false} is VALID [2022-02-21 04:23:29,130 INFO L290 TraceCheckUtils]: 47: Hoare triple {66783#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66783#false} is VALID [2022-02-21 04:23:29,131 INFO L290 TraceCheckUtils]: 48: Hoare triple {66783#false} assume !(1 == ~m_pc~0); {66783#false} is VALID [2022-02-21 04:23:29,131 INFO L290 TraceCheckUtils]: 49: Hoare triple {66783#false} is_master_triggered_~__retres1~0#1 := 0; {66783#false} is VALID [2022-02-21 04:23:29,131 INFO L290 TraceCheckUtils]: 50: Hoare triple {66783#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66783#false} is VALID [2022-02-21 04:23:29,131 INFO L290 TraceCheckUtils]: 51: Hoare triple {66783#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {66783#false} is VALID [2022-02-21 04:23:29,131 INFO L290 TraceCheckUtils]: 52: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp~1#1); {66783#false} is VALID [2022-02-21 04:23:29,131 INFO L290 TraceCheckUtils]: 53: Hoare triple {66783#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66783#false} is VALID [2022-02-21 04:23:29,131 INFO L290 TraceCheckUtils]: 54: Hoare triple {66783#false} assume 1 == ~t1_pc~0; {66783#false} is VALID [2022-02-21 04:23:29,132 INFO L290 TraceCheckUtils]: 55: Hoare triple {66783#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {66783#false} is VALID [2022-02-21 04:23:29,132 INFO L290 TraceCheckUtils]: 56: Hoare triple {66783#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66783#false} is VALID [2022-02-21 04:23:29,132 INFO L290 TraceCheckUtils]: 57: Hoare triple {66783#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {66783#false} is VALID [2022-02-21 04:23:29,132 INFO L290 TraceCheckUtils]: 58: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___0~0#1); {66783#false} is VALID [2022-02-21 04:23:29,132 INFO L290 TraceCheckUtils]: 59: Hoare triple {66783#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66783#false} is VALID [2022-02-21 04:23:29,132 INFO L290 TraceCheckUtils]: 60: Hoare triple {66783#false} assume 1 == ~t2_pc~0; {66783#false} is VALID [2022-02-21 04:23:29,132 INFO L290 TraceCheckUtils]: 61: Hoare triple {66783#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {66783#false} is VALID [2022-02-21 04:23:29,132 INFO L290 TraceCheckUtils]: 62: Hoare triple {66783#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66783#false} is VALID [2022-02-21 04:23:29,133 INFO L290 TraceCheckUtils]: 63: Hoare triple {66783#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {66783#false} is VALID [2022-02-21 04:23:29,133 INFO L290 TraceCheckUtils]: 64: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___1~0#1); {66783#false} is VALID [2022-02-21 04:23:29,133 INFO L290 TraceCheckUtils]: 65: Hoare triple {66783#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66783#false} is VALID [2022-02-21 04:23:29,133 INFO L290 TraceCheckUtils]: 66: Hoare triple {66783#false} assume !(1 == ~t3_pc~0); {66783#false} is VALID [2022-02-21 04:23:29,133 INFO L290 TraceCheckUtils]: 67: Hoare triple {66783#false} is_transmit3_triggered_~__retres1~3#1 := 0; {66783#false} is VALID [2022-02-21 04:23:29,133 INFO L290 TraceCheckUtils]: 68: Hoare triple {66783#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66783#false} is VALID [2022-02-21 04:23:29,133 INFO L290 TraceCheckUtils]: 69: Hoare triple {66783#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {66783#false} is VALID [2022-02-21 04:23:29,133 INFO L290 TraceCheckUtils]: 70: Hoare triple {66783#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {66783#false} is VALID [2022-02-21 04:23:29,134 INFO L290 TraceCheckUtils]: 71: Hoare triple {66783#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66783#false} is VALID [2022-02-21 04:23:29,134 INFO L290 TraceCheckUtils]: 72: Hoare triple {66783#false} assume 1 == ~t4_pc~0; {66783#false} is VALID [2022-02-21 04:23:29,134 INFO L290 TraceCheckUtils]: 73: Hoare triple {66783#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {66783#false} is VALID [2022-02-21 04:23:29,134 INFO L290 TraceCheckUtils]: 74: Hoare triple {66783#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66783#false} is VALID [2022-02-21 04:23:29,134 INFO L290 TraceCheckUtils]: 75: Hoare triple {66783#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {66783#false} is VALID [2022-02-21 04:23:29,134 INFO L290 TraceCheckUtils]: 76: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___3~0#1); {66783#false} is VALID [2022-02-21 04:23:29,134 INFO L290 TraceCheckUtils]: 77: Hoare triple {66783#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66783#false} is VALID [2022-02-21 04:23:29,135 INFO L290 TraceCheckUtils]: 78: Hoare triple {66783#false} assume !(1 == ~t5_pc~0); {66783#false} is VALID [2022-02-21 04:23:29,135 INFO L290 TraceCheckUtils]: 79: Hoare triple {66783#false} is_transmit5_triggered_~__retres1~5#1 := 0; {66783#false} is VALID [2022-02-21 04:23:29,135 INFO L290 TraceCheckUtils]: 80: Hoare triple {66783#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66783#false} is VALID [2022-02-21 04:23:29,135 INFO L290 TraceCheckUtils]: 81: Hoare triple {66783#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {66783#false} is VALID [2022-02-21 04:23:29,135 INFO L290 TraceCheckUtils]: 82: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___4~0#1); {66783#false} is VALID [2022-02-21 04:23:29,135 INFO L290 TraceCheckUtils]: 83: Hoare triple {66783#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66783#false} is VALID [2022-02-21 04:23:29,135 INFO L290 TraceCheckUtils]: 84: Hoare triple {66783#false} assume 1 == ~t6_pc~0; {66783#false} is VALID [2022-02-21 04:23:29,135 INFO L290 TraceCheckUtils]: 85: Hoare triple {66783#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {66783#false} is VALID [2022-02-21 04:23:29,136 INFO L290 TraceCheckUtils]: 86: Hoare triple {66783#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66783#false} is VALID [2022-02-21 04:23:29,136 INFO L290 TraceCheckUtils]: 87: Hoare triple {66783#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {66783#false} is VALID [2022-02-21 04:23:29,136 INFO L290 TraceCheckUtils]: 88: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___5~0#1); {66783#false} is VALID [2022-02-21 04:23:29,136 INFO L290 TraceCheckUtils]: 89: Hoare triple {66783#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {66783#false} is VALID [2022-02-21 04:23:29,136 INFO L290 TraceCheckUtils]: 90: Hoare triple {66783#false} assume !(1 == ~t7_pc~0); {66783#false} is VALID [2022-02-21 04:23:29,136 INFO L290 TraceCheckUtils]: 91: Hoare triple {66783#false} is_transmit7_triggered_~__retres1~7#1 := 0; {66783#false} is VALID [2022-02-21 04:23:29,136 INFO L290 TraceCheckUtils]: 92: Hoare triple {66783#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {66783#false} is VALID [2022-02-21 04:23:29,137 INFO L290 TraceCheckUtils]: 93: Hoare triple {66783#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {66783#false} is VALID [2022-02-21 04:23:29,137 INFO L290 TraceCheckUtils]: 94: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___6~0#1); {66783#false} is VALID [2022-02-21 04:23:29,137 INFO L290 TraceCheckUtils]: 95: Hoare triple {66783#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {66783#false} is VALID [2022-02-21 04:23:29,137 INFO L290 TraceCheckUtils]: 96: Hoare triple {66783#false} assume 1 == ~t8_pc~0; {66783#false} is VALID [2022-02-21 04:23:29,137 INFO L290 TraceCheckUtils]: 97: Hoare triple {66783#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {66783#false} is VALID [2022-02-21 04:23:29,137 INFO L290 TraceCheckUtils]: 98: Hoare triple {66783#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {66783#false} is VALID [2022-02-21 04:23:29,137 INFO L290 TraceCheckUtils]: 99: Hoare triple {66783#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {66783#false} is VALID [2022-02-21 04:23:29,137 INFO L290 TraceCheckUtils]: 100: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___7~0#1); {66783#false} is VALID [2022-02-21 04:23:29,138 INFO L290 TraceCheckUtils]: 101: Hoare triple {66783#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {66783#false} is VALID [2022-02-21 04:23:29,138 INFO L290 TraceCheckUtils]: 102: Hoare triple {66783#false} assume 1 == ~t9_pc~0; {66783#false} is VALID [2022-02-21 04:23:29,138 INFO L290 TraceCheckUtils]: 103: Hoare triple {66783#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {66783#false} is VALID [2022-02-21 04:23:29,138 INFO L290 TraceCheckUtils]: 104: Hoare triple {66783#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {66783#false} is VALID [2022-02-21 04:23:29,138 INFO L290 TraceCheckUtils]: 105: Hoare triple {66783#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {66783#false} is VALID [2022-02-21 04:23:29,138 INFO L290 TraceCheckUtils]: 106: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___8~0#1); {66783#false} is VALID [2022-02-21 04:23:29,138 INFO L290 TraceCheckUtils]: 107: Hoare triple {66783#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {66783#false} is VALID [2022-02-21 04:23:29,138 INFO L290 TraceCheckUtils]: 108: Hoare triple {66783#false} assume !(1 == ~t10_pc~0); {66783#false} is VALID [2022-02-21 04:23:29,139 INFO L290 TraceCheckUtils]: 109: Hoare triple {66783#false} is_transmit10_triggered_~__retres1~10#1 := 0; {66783#false} is VALID [2022-02-21 04:23:29,139 INFO L290 TraceCheckUtils]: 110: Hoare triple {66783#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {66783#false} is VALID [2022-02-21 04:23:29,139 INFO L290 TraceCheckUtils]: 111: Hoare triple {66783#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {66783#false} is VALID [2022-02-21 04:23:29,139 INFO L290 TraceCheckUtils]: 112: Hoare triple {66783#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {66783#false} is VALID [2022-02-21 04:23:29,139 INFO L290 TraceCheckUtils]: 113: Hoare triple {66783#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {66783#false} is VALID [2022-02-21 04:23:29,139 INFO L290 TraceCheckUtils]: 114: Hoare triple {66783#false} assume 1 == ~t11_pc~0; {66783#false} is VALID [2022-02-21 04:23:29,139 INFO L290 TraceCheckUtils]: 115: Hoare triple {66783#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {66783#false} is VALID [2022-02-21 04:23:29,140 INFO L290 TraceCheckUtils]: 116: Hoare triple {66783#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {66783#false} is VALID [2022-02-21 04:23:29,140 INFO L290 TraceCheckUtils]: 117: Hoare triple {66783#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {66783#false} is VALID [2022-02-21 04:23:29,140 INFO L290 TraceCheckUtils]: 118: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___10~0#1); {66783#false} is VALID [2022-02-21 04:23:29,140 INFO L290 TraceCheckUtils]: 119: Hoare triple {66783#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {66783#false} is VALID [2022-02-21 04:23:29,140 INFO L290 TraceCheckUtils]: 120: Hoare triple {66783#false} assume !(1 == ~t12_pc~0); {66783#false} is VALID [2022-02-21 04:23:29,140 INFO L290 TraceCheckUtils]: 121: Hoare triple {66783#false} is_transmit12_triggered_~__retres1~12#1 := 0; {66783#false} is VALID [2022-02-21 04:23:29,140 INFO L290 TraceCheckUtils]: 122: Hoare triple {66783#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {66783#false} is VALID [2022-02-21 04:23:29,140 INFO L290 TraceCheckUtils]: 123: Hoare triple {66783#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {66783#false} is VALID [2022-02-21 04:23:29,141 INFO L290 TraceCheckUtils]: 124: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___11~0#1); {66783#false} is VALID [2022-02-21 04:23:29,141 INFO L290 TraceCheckUtils]: 125: Hoare triple {66783#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {66783#false} is VALID [2022-02-21 04:23:29,141 INFO L290 TraceCheckUtils]: 126: Hoare triple {66783#false} assume 1 == ~t13_pc~0; {66783#false} is VALID [2022-02-21 04:23:29,141 INFO L290 TraceCheckUtils]: 127: Hoare triple {66783#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {66783#false} is VALID [2022-02-21 04:23:29,141 INFO L290 TraceCheckUtils]: 128: Hoare triple {66783#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {66783#false} is VALID [2022-02-21 04:23:29,141 INFO L290 TraceCheckUtils]: 129: Hoare triple {66783#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {66783#false} is VALID [2022-02-21 04:23:29,141 INFO L290 TraceCheckUtils]: 130: Hoare triple {66783#false} assume !(0 != activate_threads_~tmp___12~0#1); {66783#false} is VALID [2022-02-21 04:23:29,141 INFO L290 TraceCheckUtils]: 131: Hoare triple {66783#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66783#false} is VALID [2022-02-21 04:23:29,142 INFO L290 TraceCheckUtils]: 132: Hoare triple {66783#false} assume !(1 == ~M_E~0); {66783#false} is VALID [2022-02-21 04:23:29,142 INFO L290 TraceCheckUtils]: 133: Hoare triple {66783#false} assume !(1 == ~T1_E~0); {66783#false} is VALID [2022-02-21 04:23:29,142 INFO L290 TraceCheckUtils]: 134: Hoare triple {66783#false} assume !(1 == ~T2_E~0); {66783#false} is VALID [2022-02-21 04:23:29,142 INFO L290 TraceCheckUtils]: 135: Hoare triple {66783#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {66783#false} is VALID [2022-02-21 04:23:29,142 INFO L290 TraceCheckUtils]: 136: Hoare triple {66783#false} assume !(1 == ~T4_E~0); {66783#false} is VALID [2022-02-21 04:23:29,142 INFO L290 TraceCheckUtils]: 137: Hoare triple {66783#false} assume !(1 == ~T5_E~0); {66783#false} is VALID [2022-02-21 04:23:29,142 INFO L290 TraceCheckUtils]: 138: Hoare triple {66783#false} assume !(1 == ~T6_E~0); {66783#false} is VALID [2022-02-21 04:23:29,142 INFO L290 TraceCheckUtils]: 139: Hoare triple {66783#false} assume !(1 == ~T7_E~0); {66783#false} is VALID [2022-02-21 04:23:29,143 INFO L290 TraceCheckUtils]: 140: Hoare triple {66783#false} assume !(1 == ~T8_E~0); {66783#false} is VALID [2022-02-21 04:23:29,143 INFO L290 TraceCheckUtils]: 141: Hoare triple {66783#false} assume !(1 == ~T9_E~0); {66783#false} is VALID [2022-02-21 04:23:29,143 INFO L290 TraceCheckUtils]: 142: Hoare triple {66783#false} assume !(1 == ~T10_E~0); {66783#false} is VALID [2022-02-21 04:23:29,143 INFO L290 TraceCheckUtils]: 143: Hoare triple {66783#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {66783#false} is VALID [2022-02-21 04:23:29,143 INFO L290 TraceCheckUtils]: 144: Hoare triple {66783#false} assume !(1 == ~T12_E~0); {66783#false} is VALID [2022-02-21 04:23:29,143 INFO L290 TraceCheckUtils]: 145: Hoare triple {66783#false} assume !(1 == ~T13_E~0); {66783#false} is VALID [2022-02-21 04:23:29,143 INFO L290 TraceCheckUtils]: 146: Hoare triple {66783#false} assume !(1 == ~E_M~0); {66783#false} is VALID [2022-02-21 04:23:29,144 INFO L290 TraceCheckUtils]: 147: Hoare triple {66783#false} assume !(1 == ~E_1~0); {66783#false} is VALID [2022-02-21 04:23:29,144 INFO L290 TraceCheckUtils]: 148: Hoare triple {66783#false} assume !(1 == ~E_2~0); {66783#false} is VALID [2022-02-21 04:23:29,144 INFO L290 TraceCheckUtils]: 149: Hoare triple {66783#false} assume !(1 == ~E_3~0); {66783#false} is VALID [2022-02-21 04:23:29,144 INFO L290 TraceCheckUtils]: 150: Hoare triple {66783#false} assume !(1 == ~E_4~0); {66783#false} is VALID [2022-02-21 04:23:29,144 INFO L290 TraceCheckUtils]: 151: Hoare triple {66783#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66783#false} is VALID [2022-02-21 04:23:29,144 INFO L290 TraceCheckUtils]: 152: Hoare triple {66783#false} assume !(1 == ~E_6~0); {66783#false} is VALID [2022-02-21 04:23:29,144 INFO L290 TraceCheckUtils]: 153: Hoare triple {66783#false} assume !(1 == ~E_7~0); {66783#false} is VALID [2022-02-21 04:23:29,144 INFO L290 TraceCheckUtils]: 154: Hoare triple {66783#false} assume !(1 == ~E_8~0); {66783#false} is VALID [2022-02-21 04:23:29,145 INFO L290 TraceCheckUtils]: 155: Hoare triple {66783#false} assume !(1 == ~E_9~0); {66783#false} is VALID [2022-02-21 04:23:29,145 INFO L290 TraceCheckUtils]: 156: Hoare triple {66783#false} assume !(1 == ~E_10~0); {66783#false} is VALID [2022-02-21 04:23:29,145 INFO L290 TraceCheckUtils]: 157: Hoare triple {66783#false} assume !(1 == ~E_11~0); {66783#false} is VALID [2022-02-21 04:23:29,145 INFO L290 TraceCheckUtils]: 158: Hoare triple {66783#false} assume !(1 == ~E_12~0); {66783#false} is VALID [2022-02-21 04:23:29,145 INFO L290 TraceCheckUtils]: 159: Hoare triple {66783#false} assume 1 == ~E_13~0;~E_13~0 := 2; {66783#false} is VALID [2022-02-21 04:23:29,145 INFO L290 TraceCheckUtils]: 160: Hoare triple {66783#false} assume { :end_inline_reset_delta_events } true; {66783#false} is VALID [2022-02-21 04:23:29,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:29,146 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:29,146 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950125665] [2022-02-21 04:23:29,146 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950125665] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:29,146 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:29,146 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:29,146 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1773631471] [2022-02-21 04:23:29,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:29,147 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:29,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:29,147 INFO L85 PathProgramCache]: Analyzing trace with hash 2007173988, now seen corresponding path program 1 times [2022-02-21 04:23:29,147 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:29,148 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735286891] [2022-02-21 04:23:29,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:29,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:29,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:29,171 INFO L290 TraceCheckUtils]: 0: Hoare triple {66785#true} assume !false; {66785#true} is VALID [2022-02-21 04:23:29,171 INFO L290 TraceCheckUtils]: 1: Hoare triple {66785#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {66785#true} is VALID [2022-02-21 04:23:29,172 INFO L290 TraceCheckUtils]: 2: Hoare triple {66785#true} assume !false; {66785#true} is VALID [2022-02-21 04:23:29,172 INFO L290 TraceCheckUtils]: 3: Hoare triple {66785#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {66785#true} is VALID [2022-02-21 04:23:29,172 INFO L290 TraceCheckUtils]: 4: Hoare triple {66785#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {66785#true} is VALID [2022-02-21 04:23:29,172 INFO L290 TraceCheckUtils]: 5: Hoare triple {66785#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {66785#true} is VALID [2022-02-21 04:23:29,172 INFO L290 TraceCheckUtils]: 6: Hoare triple {66785#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {66785#true} is VALID [2022-02-21 04:23:29,172 INFO L290 TraceCheckUtils]: 7: Hoare triple {66785#true} assume !(0 != eval_~tmp~0#1); {66785#true} is VALID [2022-02-21 04:23:29,172 INFO L290 TraceCheckUtils]: 8: Hoare triple {66785#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {66785#true} is VALID [2022-02-21 04:23:29,172 INFO L290 TraceCheckUtils]: 9: Hoare triple {66785#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {66785#true} is VALID [2022-02-21 04:23:29,173 INFO L290 TraceCheckUtils]: 10: Hoare triple {66785#true} assume 0 == ~M_E~0;~M_E~0 := 1; {66785#true} is VALID [2022-02-21 04:23:29,173 INFO L290 TraceCheckUtils]: 11: Hoare triple {66785#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {66785#true} is VALID [2022-02-21 04:23:29,173 INFO L290 TraceCheckUtils]: 12: Hoare triple {66785#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {66785#true} is VALID [2022-02-21 04:23:29,173 INFO L290 TraceCheckUtils]: 13: Hoare triple {66785#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {66785#true} is VALID [2022-02-21 04:23:29,173 INFO L290 TraceCheckUtils]: 14: Hoare triple {66785#true} assume !(0 == ~T4_E~0); {66785#true} is VALID [2022-02-21 04:23:29,173 INFO L290 TraceCheckUtils]: 15: Hoare triple {66785#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {66785#true} is VALID [2022-02-21 04:23:29,173 INFO L290 TraceCheckUtils]: 16: Hoare triple {66785#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {66785#true} is VALID [2022-02-21 04:23:29,174 INFO L290 TraceCheckUtils]: 17: Hoare triple {66785#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,174 INFO L290 TraceCheckUtils]: 18: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,174 INFO L290 TraceCheckUtils]: 19: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,175 INFO L290 TraceCheckUtils]: 20: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,175 INFO L290 TraceCheckUtils]: 21: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,175 INFO L290 TraceCheckUtils]: 22: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,175 INFO L290 TraceCheckUtils]: 23: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,176 INFO L290 TraceCheckUtils]: 24: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,176 INFO L290 TraceCheckUtils]: 25: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,176 INFO L290 TraceCheckUtils]: 26: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,176 INFO L290 TraceCheckUtils]: 27: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,177 INFO L290 TraceCheckUtils]: 28: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,177 INFO L290 TraceCheckUtils]: 29: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,177 INFO L290 TraceCheckUtils]: 30: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,177 INFO L290 TraceCheckUtils]: 31: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,178 INFO L290 TraceCheckUtils]: 32: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,178 INFO L290 TraceCheckUtils]: 33: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,178 INFO L290 TraceCheckUtils]: 34: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,178 INFO L290 TraceCheckUtils]: 35: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,179 INFO L290 TraceCheckUtils]: 36: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,179 INFO L290 TraceCheckUtils]: 37: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,179 INFO L290 TraceCheckUtils]: 38: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,180 INFO L290 TraceCheckUtils]: 39: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,180 INFO L290 TraceCheckUtils]: 40: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,180 INFO L290 TraceCheckUtils]: 41: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,180 INFO L290 TraceCheckUtils]: 42: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,181 INFO L290 TraceCheckUtils]: 43: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,181 INFO L290 TraceCheckUtils]: 44: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,181 INFO L290 TraceCheckUtils]: 45: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,181 INFO L290 TraceCheckUtils]: 46: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,182 INFO L290 TraceCheckUtils]: 47: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,182 INFO L290 TraceCheckUtils]: 48: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,182 INFO L290 TraceCheckUtils]: 49: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,182 INFO L290 TraceCheckUtils]: 50: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,183 INFO L290 TraceCheckUtils]: 51: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,183 INFO L290 TraceCheckUtils]: 52: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,183 INFO L290 TraceCheckUtils]: 53: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,184 INFO L290 TraceCheckUtils]: 54: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,184 INFO L290 TraceCheckUtils]: 55: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,184 INFO L290 TraceCheckUtils]: 56: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,184 INFO L290 TraceCheckUtils]: 57: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,185 INFO L290 TraceCheckUtils]: 58: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,185 INFO L290 TraceCheckUtils]: 59: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,185 INFO L290 TraceCheckUtils]: 60: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,185 INFO L290 TraceCheckUtils]: 61: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,186 INFO L290 TraceCheckUtils]: 62: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,186 INFO L290 TraceCheckUtils]: 63: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t4_pc~0); {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,186 INFO L290 TraceCheckUtils]: 64: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,186 INFO L290 TraceCheckUtils]: 65: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,187 INFO L290 TraceCheckUtils]: 66: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,187 INFO L290 TraceCheckUtils]: 67: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,187 INFO L290 TraceCheckUtils]: 68: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,187 INFO L290 TraceCheckUtils]: 69: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,188 INFO L290 TraceCheckUtils]: 70: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,188 INFO L290 TraceCheckUtils]: 71: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,188 INFO L290 TraceCheckUtils]: 72: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,189 INFO L290 TraceCheckUtils]: 73: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,189 INFO L290 TraceCheckUtils]: 74: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,189 INFO L290 TraceCheckUtils]: 75: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,189 INFO L290 TraceCheckUtils]: 76: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,190 INFO L290 TraceCheckUtils]: 77: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,190 INFO L290 TraceCheckUtils]: 78: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,190 INFO L290 TraceCheckUtils]: 79: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,190 INFO L290 TraceCheckUtils]: 80: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,191 INFO L290 TraceCheckUtils]: 81: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,191 INFO L290 TraceCheckUtils]: 82: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,191 INFO L290 TraceCheckUtils]: 83: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,192 INFO L290 TraceCheckUtils]: 84: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,192 INFO L290 TraceCheckUtils]: 85: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,192 INFO L290 TraceCheckUtils]: 86: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,192 INFO L290 TraceCheckUtils]: 87: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t8_pc~0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,193 INFO L290 TraceCheckUtils]: 88: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,193 INFO L290 TraceCheckUtils]: 89: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,193 INFO L290 TraceCheckUtils]: 90: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,193 INFO L290 TraceCheckUtils]: 91: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,194 INFO L290 TraceCheckUtils]: 92: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,194 INFO L290 TraceCheckUtils]: 93: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,194 INFO L290 TraceCheckUtils]: 94: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,194 INFO L290 TraceCheckUtils]: 95: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,195 INFO L290 TraceCheckUtils]: 96: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,195 INFO L290 TraceCheckUtils]: 97: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,195 INFO L290 TraceCheckUtils]: 98: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,196 INFO L290 TraceCheckUtils]: 99: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t10_pc~0); {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,196 INFO L290 TraceCheckUtils]: 100: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,196 INFO L290 TraceCheckUtils]: 101: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,196 INFO L290 TraceCheckUtils]: 102: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,197 INFO L290 TraceCheckUtils]: 103: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,197 INFO L290 TraceCheckUtils]: 104: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,197 INFO L290 TraceCheckUtils]: 105: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,197 INFO L290 TraceCheckUtils]: 106: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,198 INFO L290 TraceCheckUtils]: 107: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,198 INFO L290 TraceCheckUtils]: 108: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,198 INFO L290 TraceCheckUtils]: 109: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,198 INFO L290 TraceCheckUtils]: 110: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,199 INFO L290 TraceCheckUtils]: 111: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,199 INFO L290 TraceCheckUtils]: 112: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,199 INFO L290 TraceCheckUtils]: 113: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,199 INFO L290 TraceCheckUtils]: 114: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,200 INFO L290 TraceCheckUtils]: 115: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,200 INFO L290 TraceCheckUtils]: 116: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,200 INFO L290 TraceCheckUtils]: 117: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t13_pc~0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,201 INFO L290 TraceCheckUtils]: 118: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,201 INFO L290 TraceCheckUtils]: 119: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,201 INFO L290 TraceCheckUtils]: 120: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,201 INFO L290 TraceCheckUtils]: 121: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,202 INFO L290 TraceCheckUtils]: 122: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,202 INFO L290 TraceCheckUtils]: 123: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,202 INFO L290 TraceCheckUtils]: 124: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,202 INFO L290 TraceCheckUtils]: 125: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,203 INFO L290 TraceCheckUtils]: 126: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,203 INFO L290 TraceCheckUtils]: 127: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,203 INFO L290 TraceCheckUtils]: 128: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,203 INFO L290 TraceCheckUtils]: 129: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {66787#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:29,204 INFO L290 TraceCheckUtils]: 130: Hoare triple {66787#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {66786#false} is VALID [2022-02-21 04:23:29,204 INFO L290 TraceCheckUtils]: 131: Hoare triple {66786#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,204 INFO L290 TraceCheckUtils]: 132: Hoare triple {66786#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,204 INFO L290 TraceCheckUtils]: 133: Hoare triple {66786#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,204 INFO L290 TraceCheckUtils]: 134: Hoare triple {66786#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,204 INFO L290 TraceCheckUtils]: 135: Hoare triple {66786#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,204 INFO L290 TraceCheckUtils]: 136: Hoare triple {66786#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,205 INFO L290 TraceCheckUtils]: 137: Hoare triple {66786#false} assume 1 == ~E_M~0;~E_M~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,205 INFO L290 TraceCheckUtils]: 138: Hoare triple {66786#false} assume !(1 == ~E_1~0); {66786#false} is VALID [2022-02-21 04:23:29,205 INFO L290 TraceCheckUtils]: 139: Hoare triple {66786#false} assume 1 == ~E_2~0;~E_2~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,205 INFO L290 TraceCheckUtils]: 140: Hoare triple {66786#false} assume 1 == ~E_3~0;~E_3~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,205 INFO L290 TraceCheckUtils]: 141: Hoare triple {66786#false} assume 1 == ~E_4~0;~E_4~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,205 INFO L290 TraceCheckUtils]: 142: Hoare triple {66786#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,205 INFO L290 TraceCheckUtils]: 143: Hoare triple {66786#false} assume 1 == ~E_6~0;~E_6~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,206 INFO L290 TraceCheckUtils]: 144: Hoare triple {66786#false} assume 1 == ~E_7~0;~E_7~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,206 INFO L290 TraceCheckUtils]: 145: Hoare triple {66786#false} assume 1 == ~E_8~0;~E_8~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,206 INFO L290 TraceCheckUtils]: 146: Hoare triple {66786#false} assume !(1 == ~E_9~0); {66786#false} is VALID [2022-02-21 04:23:29,206 INFO L290 TraceCheckUtils]: 147: Hoare triple {66786#false} assume 1 == ~E_10~0;~E_10~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,206 INFO L290 TraceCheckUtils]: 148: Hoare triple {66786#false} assume 1 == ~E_11~0;~E_11~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,206 INFO L290 TraceCheckUtils]: 149: Hoare triple {66786#false} assume 1 == ~E_12~0;~E_12~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,206 INFO L290 TraceCheckUtils]: 150: Hoare triple {66786#false} assume 1 == ~E_13~0;~E_13~0 := 2; {66786#false} is VALID [2022-02-21 04:23:29,206 INFO L290 TraceCheckUtils]: 151: Hoare triple {66786#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {66786#false} is VALID [2022-02-21 04:23:29,207 INFO L290 TraceCheckUtils]: 152: Hoare triple {66786#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {66786#false} is VALID [2022-02-21 04:23:29,207 INFO L290 TraceCheckUtils]: 153: Hoare triple {66786#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {66786#false} is VALID [2022-02-21 04:23:29,207 INFO L290 TraceCheckUtils]: 154: Hoare triple {66786#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {66786#false} is VALID [2022-02-21 04:23:29,207 INFO L290 TraceCheckUtils]: 155: Hoare triple {66786#false} assume !(0 == start_simulation_~tmp~3#1); {66786#false} is VALID [2022-02-21 04:23:29,207 INFO L290 TraceCheckUtils]: 156: Hoare triple {66786#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {66786#false} is VALID [2022-02-21 04:23:29,207 INFO L290 TraceCheckUtils]: 157: Hoare triple {66786#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {66786#false} is VALID [2022-02-21 04:23:29,207 INFO L290 TraceCheckUtils]: 158: Hoare triple {66786#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {66786#false} is VALID [2022-02-21 04:23:29,208 INFO L290 TraceCheckUtils]: 159: Hoare triple {66786#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {66786#false} is VALID [2022-02-21 04:23:29,208 INFO L290 TraceCheckUtils]: 160: Hoare triple {66786#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {66786#false} is VALID [2022-02-21 04:23:29,208 INFO L290 TraceCheckUtils]: 161: Hoare triple {66786#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {66786#false} is VALID [2022-02-21 04:23:29,208 INFO L290 TraceCheckUtils]: 162: Hoare triple {66786#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {66786#false} is VALID [2022-02-21 04:23:29,208 INFO L290 TraceCheckUtils]: 163: Hoare triple {66786#false} assume !(0 != start_simulation_~tmp___0~1#1); {66786#false} is VALID [2022-02-21 04:23:29,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:29,209 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:29,209 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [735286891] [2022-02-21 04:23:29,209 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [735286891] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:29,209 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:29,209 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:29,209 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [543301775] [2022-02-21 04:23:29,209 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:29,210 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:29,210 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:29,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:29,210 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:29,211 INFO L87 Difference]: Start difference. First operand 2021 states and 2985 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:30,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:30,478 INFO L93 Difference]: Finished difference Result 2021 states and 2984 transitions. [2022-02-21 04:23:30,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:30,478 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:30,565 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:30,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2984 transitions. [2022-02-21 04:23:30,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:30,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2984 transitions. [2022-02-21 04:23:30,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:30,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:30,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2984 transitions. [2022-02-21 04:23:30,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:30,733 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2022-02-21 04:23:30,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2984 transitions. [2022-02-21 04:23:30,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:30,749 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:30,751 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2984 transitions. Second operand has 2021 states, 2021 states have (on average 1.4764967837704106) internal successors, (2984), 2020 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:30,752 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2984 transitions. Second operand has 2021 states, 2021 states have (on average 1.4764967837704106) internal successors, (2984), 2020 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:30,754 INFO L87 Difference]: Start difference. First operand 2021 states and 2984 transitions. Second operand has 2021 states, 2021 states have (on average 1.4764967837704106) internal successors, (2984), 2020 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:30,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:30,835 INFO L93 Difference]: Finished difference Result 2021 states and 2984 transitions. [2022-02-21 04:23:30,836 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2984 transitions. [2022-02-21 04:23:30,837 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:30,837 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:30,839 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.4764967837704106) internal successors, (2984), 2020 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2984 transitions. [2022-02-21 04:23:30,840 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.4764967837704106) internal successors, (2984), 2020 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2984 transitions. [2022-02-21 04:23:30,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:30,923 INFO L93 Difference]: Finished difference Result 2021 states and 2984 transitions. [2022-02-21 04:23:30,924 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2984 transitions. [2022-02-21 04:23:30,925 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:30,926 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:30,926 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:30,926 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:30,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4764967837704106) internal successors, (2984), 2020 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2984 transitions. [2022-02-21 04:23:31,009 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2022-02-21 04:23:31,009 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2022-02-21 04:23:31,009 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:23:31,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2984 transitions. [2022-02-21 04:23:31,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:31,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:31,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:31,013 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:31,013 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:31,014 INFO L791 eck$LassoCheckResult]: Stem: 69685#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 69686#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69417#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69418#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70808#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 70809#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69604#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69605#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69639#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 70476#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 70477#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 70589#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 70590#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 69423#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 69424#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 70626#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 69948#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 69949#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 70530#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 70796#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 70686#L1286-2 assume !(0 == ~T1_E~0); 69332#L1291-1 assume !(0 == ~T2_E~0); 69333#L1296-1 assume !(0 == ~T3_E~0); 70038#L1301-1 assume !(0 == ~T4_E~0); 70039#L1306-1 assume !(0 == ~T5_E~0); 70539#L1311-1 assume !(0 == ~T6_E~0); 69292#L1316-1 assume !(0 == ~T7_E~0); 69293#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 70058#L1326-1 assume !(0 == ~T9_E~0); 69107#L1331-1 assume !(0 == ~T10_E~0); 68813#L1336-1 assume !(0 == ~T11_E~0); 68814#L1341-1 assume !(0 == ~T12_E~0); 68865#L1346-1 assume !(0 == ~T13_E~0); 68866#L1351-1 assume !(0 == ~E_M~0); 69239#L1356-1 assume !(0 == ~E_1~0); 69240#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 70759#L1366-1 assume !(0 == ~E_3~0); 69285#L1371-1 assume !(0 == ~E_4~0); 69286#L1376-1 assume !(0 == ~E_5~0); 70099#L1381-1 assume !(0 == ~E_6~0); 70100#L1386-1 assume !(0 == ~E_7~0); 70787#L1391-1 assume !(0 == ~E_8~0); 70800#L1396-1 assume !(0 == ~E_9~0); 69982#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69983#L1406-1 assume !(0 == ~E_11~0); 70285#L1411-1 assume !(0 == ~E_12~0); 70286#L1416-1 assume !(0 == ~E_13~0); 69906#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69744#L635 assume !(1 == ~m_pc~0); 68883#L635-2 is_master_triggered_~__retres1~0#1 := 0; 68884#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69234#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69870#L1598 assume !(0 != activate_threads_~tmp~1#1); 69062#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69063#L654 assume 1 == ~t1_pc~0; 69768#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 69769#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70784#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69850#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 69851#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69110#L673 assume 1 == ~t2_pc~0; 69111#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 70255#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70256#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70814#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 70821#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69929#L692 assume !(1 == ~t3_pc~0); 69746#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69747#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69606#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69574#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69575#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69135#L711 assume 1 == ~t4_pc~0; 69136#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 69619#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70076#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68838#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 68839#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70807#L730 assume !(1 == ~t5_pc~0); 70189#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69017#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69018#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69145#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 69146#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69488#L749 assume 1 == ~t6_pc~0; 69262#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69022#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69454#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69455#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 69677#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68818#L768 assume !(1 == ~t7_pc~0); 68819#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 70123#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69055#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69056#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 70142#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69294#L787 assume 1 == ~t8_pc~0; 69295#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 70490#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70654#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70655#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 68863#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68864#L806 assume 1 == ~t9_pc~0; 70501#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68898#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68899#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69147#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 69148#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70484#L825 assume !(1 == ~t10_pc~0); 70485#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 70090#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70091#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69235#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69236#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69819#L844 assume 1 == ~t11_pc~0; 69509#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 69510#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69876#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69877#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 70472#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 70473#L863 assume !(1 == ~t12_pc~0); 68998#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 68997#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69225#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 70564#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 70565#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69943#L882 assume 1 == ~t13_pc~0; 69944#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 70228#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 70729#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 70532#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 70215#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70216#L1434 assume !(1 == ~M_E~0); 70737#L1434-2 assume !(1 == ~T1_E~0); 70813#L1439-1 assume !(1 == ~T2_E~0); 69128#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69129#L1449-1 assume !(1 == ~T4_E~0); 69571#L1454-1 assume !(1 == ~T5_E~0); 69572#L1459-1 assume !(1 == ~T6_E~0); 70143#L1464-1 assume !(1 == ~T7_E~0); 70144#L1469-1 assume !(1 == ~T8_E~0); 70229#L1474-1 assume !(1 == ~T9_E~0); 69907#L1479-1 assume !(1 == ~T10_E~0); 69908#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 70151#L1489-1 assume !(1 == ~T12_E~0); 69785#L1494-1 assume !(1 == ~T13_E~0); 69786#L1499-1 assume !(1 == ~E_M~0); 69967#L1504-1 assume !(1 == ~E_1~0); 69968#L1509-1 assume !(1 == ~E_2~0); 70581#L1514-1 assume !(1 == ~E_3~0); 70266#L1519-1 assume !(1 == ~E_4~0); 70267#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 70771#L1529-1 assume !(1 == ~E_6~0); 70772#L1534-1 assume !(1 == ~E_7~0); 68918#L1539-1 assume !(1 == ~E_8~0); 68919#L1544-1 assume !(1 == ~E_9~0); 69349#L1549-1 assume !(1 == ~E_10~0); 70749#L1554-1 assume !(1 == ~E_11~0); 70747#L1559-1 assume !(1 == ~E_12~0); 70609#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 70610#L1569-1 assume { :end_inline_reset_delta_events } true; 70765#L1935-2 [2022-02-21 04:23:31,014 INFO L793 eck$LassoCheckResult]: Loop: 70765#L1935-2 assume !false; 68927#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68928#L1261 assume !false; 70155#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 70156#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69058#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69228#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 69229#L1074 assume !(0 != eval_~tmp~0#1); 69586#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70184#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70585#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 70641#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 70360#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70361#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70797#L1301-3 assume !(0 == ~T4_E~0); 70755#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69863#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69162#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69163#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 69268#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 70004#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 70269#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 70270#L1341-3 assume !(0 == ~T12_E~0); 69564#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 69555#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69499#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69500#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70080#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68853#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 68854#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70596#L1381-3 assume !(0 == ~E_6~0); 70445#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70446#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 70627#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 70628#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 69233#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69064#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 69065#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 69692#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68942#L635-45 assume !(1 == ~m_pc~0); 68944#L635-47 is_master_triggered_~__retres1~0#1 := 0; 69737#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70217#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70471#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69251#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69252#L654-45 assume !(1 == ~t1_pc~0); 70073#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 70420#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68905#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68906#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68931#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69758#L673-45 assume 1 == ~t2_pc~0; 69760#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 70083#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70084#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70709#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 70529#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69376#L692-45 assume 1 == ~t3_pc~0; 69377#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69103#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70147#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69430#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69431#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69743#L711-45 assume 1 == ~t4_pc~0; 69867#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 69868#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69720#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69721#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70124#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69275#L730-45 assume 1 == ~t5_pc~0; 69113#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69114#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69523#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69524#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70275#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69086#L749-45 assume 1 == ~t6_pc~0; 69088#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 70487#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70250#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70251#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 70402#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69402#L768-45 assume 1 == ~t7_pc~0; 69403#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69542#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70346#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70347#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 70386#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70387#L787-45 assume 1 == ~t8_pc~0; 70555#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69548#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69549#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69965#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 69966#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70274#L806-45 assume !(1 == ~t9_pc~0); 68961#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 68962#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69787#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69615#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69527#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69528#L825-45 assume !(1 == ~t10_pc~0); 70051#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 70052#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70157#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 70158#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 70310#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69170#L844-45 assume !(1 == ~t11_pc~0); 69171#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 69693#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69694#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69710#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 70121#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69210#L863-45 assume 1 == ~t12_pc~0; 69211#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 68811#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68812#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69327#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69328#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70127#L882-45 assume 1 == ~t13_pc~0; 70481#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68830#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68831#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69439#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 70618#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70234#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 70235#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70419#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69124#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69125#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69287#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70224#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70225#L1464-3 assume !(1 == ~T7_E~0); 70671#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70598#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70599#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 70673#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69865#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 69866#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 70526#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70161#L1504-3 assume !(1 == ~E_1~0); 70162#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70607#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70647#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69788#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69789#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70694#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70089#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 69543#L1544-3 assume !(1 == ~E_9~0); 69544#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 70059#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69175#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69176#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 70325#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 70326#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69060#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69625#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 70296#L1954 assume !(0 == start_simulation_~tmp~3#1); 70298#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 70548#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69343#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 70384#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 70514#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70515#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70605#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 70667#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 70765#L1935-2 [2022-02-21 04:23:31,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:31,015 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2022-02-21 04:23:31,015 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:31,015 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343788039] [2022-02-21 04:23:31,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:31,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:31,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:31,033 INFO L290 TraceCheckUtils]: 0: Hoare triple {74875#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {74875#true} is VALID [2022-02-21 04:23:31,033 INFO L290 TraceCheckUtils]: 1: Hoare triple {74875#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,034 INFO L290 TraceCheckUtils]: 2: Hoare triple {74877#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,034 INFO L290 TraceCheckUtils]: 3: Hoare triple {74877#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,034 INFO L290 TraceCheckUtils]: 4: Hoare triple {74877#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,034 INFO L290 TraceCheckUtils]: 5: Hoare triple {74877#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,035 INFO L290 TraceCheckUtils]: 6: Hoare triple {74877#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,035 INFO L290 TraceCheckUtils]: 7: Hoare triple {74877#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,035 INFO L290 TraceCheckUtils]: 8: Hoare triple {74877#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,036 INFO L290 TraceCheckUtils]: 9: Hoare triple {74877#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,036 INFO L290 TraceCheckUtils]: 10: Hoare triple {74877#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,036 INFO L290 TraceCheckUtils]: 11: Hoare triple {74877#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,036 INFO L290 TraceCheckUtils]: 12: Hoare triple {74877#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,037 INFO L290 TraceCheckUtils]: 13: Hoare triple {74877#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {74877#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:31,037 INFO L290 TraceCheckUtils]: 14: Hoare triple {74877#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {74876#false} is VALID [2022-02-21 04:23:31,037 INFO L290 TraceCheckUtils]: 15: Hoare triple {74876#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {74876#false} is VALID [2022-02-21 04:23:31,037 INFO L290 TraceCheckUtils]: 16: Hoare triple {74876#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {74876#false} is VALID [2022-02-21 04:23:31,037 INFO L290 TraceCheckUtils]: 17: Hoare triple {74876#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {74876#false} is VALID [2022-02-21 04:23:31,037 INFO L290 TraceCheckUtils]: 18: Hoare triple {74876#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {74876#false} is VALID [2022-02-21 04:23:31,038 INFO L290 TraceCheckUtils]: 19: Hoare triple {74876#false} assume 0 == ~M_E~0;~M_E~0 := 1; {74876#false} is VALID [2022-02-21 04:23:31,038 INFO L290 TraceCheckUtils]: 20: Hoare triple {74876#false} assume !(0 == ~T1_E~0); {74876#false} is VALID [2022-02-21 04:23:31,038 INFO L290 TraceCheckUtils]: 21: Hoare triple {74876#false} assume !(0 == ~T2_E~0); {74876#false} is VALID [2022-02-21 04:23:31,038 INFO L290 TraceCheckUtils]: 22: Hoare triple {74876#false} assume !(0 == ~T3_E~0); {74876#false} is VALID [2022-02-21 04:23:31,038 INFO L290 TraceCheckUtils]: 23: Hoare triple {74876#false} assume !(0 == ~T4_E~0); {74876#false} is VALID [2022-02-21 04:23:31,038 INFO L290 TraceCheckUtils]: 24: Hoare triple {74876#false} assume !(0 == ~T5_E~0); {74876#false} is VALID [2022-02-21 04:23:31,038 INFO L290 TraceCheckUtils]: 25: Hoare triple {74876#false} assume !(0 == ~T6_E~0); {74876#false} is VALID [2022-02-21 04:23:31,038 INFO L290 TraceCheckUtils]: 26: Hoare triple {74876#false} assume !(0 == ~T7_E~0); {74876#false} is VALID [2022-02-21 04:23:31,039 INFO L290 TraceCheckUtils]: 27: Hoare triple {74876#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {74876#false} is VALID [2022-02-21 04:23:31,039 INFO L290 TraceCheckUtils]: 28: Hoare triple {74876#false} assume !(0 == ~T9_E~0); {74876#false} is VALID [2022-02-21 04:23:31,039 INFO L290 TraceCheckUtils]: 29: Hoare triple {74876#false} assume !(0 == ~T10_E~0); {74876#false} is VALID [2022-02-21 04:23:31,039 INFO L290 TraceCheckUtils]: 30: Hoare triple {74876#false} assume !(0 == ~T11_E~0); {74876#false} is VALID [2022-02-21 04:23:31,039 INFO L290 TraceCheckUtils]: 31: Hoare triple {74876#false} assume !(0 == ~T12_E~0); {74876#false} is VALID [2022-02-21 04:23:31,039 INFO L290 TraceCheckUtils]: 32: Hoare triple {74876#false} assume !(0 == ~T13_E~0); {74876#false} is VALID [2022-02-21 04:23:31,039 INFO L290 TraceCheckUtils]: 33: Hoare triple {74876#false} assume !(0 == ~E_M~0); {74876#false} is VALID [2022-02-21 04:23:31,039 INFO L290 TraceCheckUtils]: 34: Hoare triple {74876#false} assume !(0 == ~E_1~0); {74876#false} is VALID [2022-02-21 04:23:31,040 INFO L290 TraceCheckUtils]: 35: Hoare triple {74876#false} assume 0 == ~E_2~0;~E_2~0 := 1; {74876#false} is VALID [2022-02-21 04:23:31,040 INFO L290 TraceCheckUtils]: 36: Hoare triple {74876#false} assume !(0 == ~E_3~0); {74876#false} is VALID [2022-02-21 04:23:31,040 INFO L290 TraceCheckUtils]: 37: Hoare triple {74876#false} assume !(0 == ~E_4~0); {74876#false} is VALID [2022-02-21 04:23:31,040 INFO L290 TraceCheckUtils]: 38: Hoare triple {74876#false} assume !(0 == ~E_5~0); {74876#false} is VALID [2022-02-21 04:23:31,040 INFO L290 TraceCheckUtils]: 39: Hoare triple {74876#false} assume !(0 == ~E_6~0); {74876#false} is VALID [2022-02-21 04:23:31,040 INFO L290 TraceCheckUtils]: 40: Hoare triple {74876#false} assume !(0 == ~E_7~0); {74876#false} is VALID [2022-02-21 04:23:31,040 INFO L290 TraceCheckUtils]: 41: Hoare triple {74876#false} assume !(0 == ~E_8~0); {74876#false} is VALID [2022-02-21 04:23:31,041 INFO L290 TraceCheckUtils]: 42: Hoare triple {74876#false} assume !(0 == ~E_9~0); {74876#false} is VALID [2022-02-21 04:23:31,041 INFO L290 TraceCheckUtils]: 43: Hoare triple {74876#false} assume 0 == ~E_10~0;~E_10~0 := 1; {74876#false} is VALID [2022-02-21 04:23:31,041 INFO L290 TraceCheckUtils]: 44: Hoare triple {74876#false} assume !(0 == ~E_11~0); {74876#false} is VALID [2022-02-21 04:23:31,041 INFO L290 TraceCheckUtils]: 45: Hoare triple {74876#false} assume !(0 == ~E_12~0); {74876#false} is VALID [2022-02-21 04:23:31,041 INFO L290 TraceCheckUtils]: 46: Hoare triple {74876#false} assume !(0 == ~E_13~0); {74876#false} is VALID [2022-02-21 04:23:31,041 INFO L290 TraceCheckUtils]: 47: Hoare triple {74876#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {74876#false} is VALID [2022-02-21 04:23:31,041 INFO L290 TraceCheckUtils]: 48: Hoare triple {74876#false} assume !(1 == ~m_pc~0); {74876#false} is VALID [2022-02-21 04:23:31,041 INFO L290 TraceCheckUtils]: 49: Hoare triple {74876#false} is_master_triggered_~__retres1~0#1 := 0; {74876#false} is VALID [2022-02-21 04:23:31,042 INFO L290 TraceCheckUtils]: 50: Hoare triple {74876#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {74876#false} is VALID [2022-02-21 04:23:31,042 INFO L290 TraceCheckUtils]: 51: Hoare triple {74876#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {74876#false} is VALID [2022-02-21 04:23:31,042 INFO L290 TraceCheckUtils]: 52: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp~1#1); {74876#false} is VALID [2022-02-21 04:23:31,042 INFO L290 TraceCheckUtils]: 53: Hoare triple {74876#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {74876#false} is VALID [2022-02-21 04:23:31,042 INFO L290 TraceCheckUtils]: 54: Hoare triple {74876#false} assume 1 == ~t1_pc~0; {74876#false} is VALID [2022-02-21 04:23:31,042 INFO L290 TraceCheckUtils]: 55: Hoare triple {74876#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {74876#false} is VALID [2022-02-21 04:23:31,042 INFO L290 TraceCheckUtils]: 56: Hoare triple {74876#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {74876#false} is VALID [2022-02-21 04:23:31,042 INFO L290 TraceCheckUtils]: 57: Hoare triple {74876#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {74876#false} is VALID [2022-02-21 04:23:31,043 INFO L290 TraceCheckUtils]: 58: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___0~0#1); {74876#false} is VALID [2022-02-21 04:23:31,043 INFO L290 TraceCheckUtils]: 59: Hoare triple {74876#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {74876#false} is VALID [2022-02-21 04:23:31,043 INFO L290 TraceCheckUtils]: 60: Hoare triple {74876#false} assume 1 == ~t2_pc~0; {74876#false} is VALID [2022-02-21 04:23:31,043 INFO L290 TraceCheckUtils]: 61: Hoare triple {74876#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {74876#false} is VALID [2022-02-21 04:23:31,043 INFO L290 TraceCheckUtils]: 62: Hoare triple {74876#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {74876#false} is VALID [2022-02-21 04:23:31,043 INFO L290 TraceCheckUtils]: 63: Hoare triple {74876#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {74876#false} is VALID [2022-02-21 04:23:31,043 INFO L290 TraceCheckUtils]: 64: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___1~0#1); {74876#false} is VALID [2022-02-21 04:23:31,044 INFO L290 TraceCheckUtils]: 65: Hoare triple {74876#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {74876#false} is VALID [2022-02-21 04:23:31,044 INFO L290 TraceCheckUtils]: 66: Hoare triple {74876#false} assume !(1 == ~t3_pc~0); {74876#false} is VALID [2022-02-21 04:23:31,044 INFO L290 TraceCheckUtils]: 67: Hoare triple {74876#false} is_transmit3_triggered_~__retres1~3#1 := 0; {74876#false} is VALID [2022-02-21 04:23:31,044 INFO L290 TraceCheckUtils]: 68: Hoare triple {74876#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {74876#false} is VALID [2022-02-21 04:23:31,044 INFO L290 TraceCheckUtils]: 69: Hoare triple {74876#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {74876#false} is VALID [2022-02-21 04:23:31,044 INFO L290 TraceCheckUtils]: 70: Hoare triple {74876#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {74876#false} is VALID [2022-02-21 04:23:31,044 INFO L290 TraceCheckUtils]: 71: Hoare triple {74876#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {74876#false} is VALID [2022-02-21 04:23:31,044 INFO L290 TraceCheckUtils]: 72: Hoare triple {74876#false} assume 1 == ~t4_pc~0; {74876#false} is VALID [2022-02-21 04:23:31,045 INFO L290 TraceCheckUtils]: 73: Hoare triple {74876#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {74876#false} is VALID [2022-02-21 04:23:31,045 INFO L290 TraceCheckUtils]: 74: Hoare triple {74876#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {74876#false} is VALID [2022-02-21 04:23:31,045 INFO L290 TraceCheckUtils]: 75: Hoare triple {74876#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {74876#false} is VALID [2022-02-21 04:23:31,045 INFO L290 TraceCheckUtils]: 76: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___3~0#1); {74876#false} is VALID [2022-02-21 04:23:31,045 INFO L290 TraceCheckUtils]: 77: Hoare triple {74876#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {74876#false} is VALID [2022-02-21 04:23:31,045 INFO L290 TraceCheckUtils]: 78: Hoare triple {74876#false} assume !(1 == ~t5_pc~0); {74876#false} is VALID [2022-02-21 04:23:31,045 INFO L290 TraceCheckUtils]: 79: Hoare triple {74876#false} is_transmit5_triggered_~__retres1~5#1 := 0; {74876#false} is VALID [2022-02-21 04:23:31,046 INFO L290 TraceCheckUtils]: 80: Hoare triple {74876#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {74876#false} is VALID [2022-02-21 04:23:31,046 INFO L290 TraceCheckUtils]: 81: Hoare triple {74876#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {74876#false} is VALID [2022-02-21 04:23:31,046 INFO L290 TraceCheckUtils]: 82: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___4~0#1); {74876#false} is VALID [2022-02-21 04:23:31,046 INFO L290 TraceCheckUtils]: 83: Hoare triple {74876#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {74876#false} is VALID [2022-02-21 04:23:31,046 INFO L290 TraceCheckUtils]: 84: Hoare triple {74876#false} assume 1 == ~t6_pc~0; {74876#false} is VALID [2022-02-21 04:23:31,046 INFO L290 TraceCheckUtils]: 85: Hoare triple {74876#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {74876#false} is VALID [2022-02-21 04:23:31,046 INFO L290 TraceCheckUtils]: 86: Hoare triple {74876#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {74876#false} is VALID [2022-02-21 04:23:31,046 INFO L290 TraceCheckUtils]: 87: Hoare triple {74876#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {74876#false} is VALID [2022-02-21 04:23:31,047 INFO L290 TraceCheckUtils]: 88: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___5~0#1); {74876#false} is VALID [2022-02-21 04:23:31,047 INFO L290 TraceCheckUtils]: 89: Hoare triple {74876#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {74876#false} is VALID [2022-02-21 04:23:31,047 INFO L290 TraceCheckUtils]: 90: Hoare triple {74876#false} assume !(1 == ~t7_pc~0); {74876#false} is VALID [2022-02-21 04:23:31,047 INFO L290 TraceCheckUtils]: 91: Hoare triple {74876#false} is_transmit7_triggered_~__retres1~7#1 := 0; {74876#false} is VALID [2022-02-21 04:23:31,047 INFO L290 TraceCheckUtils]: 92: Hoare triple {74876#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {74876#false} is VALID [2022-02-21 04:23:31,047 INFO L290 TraceCheckUtils]: 93: Hoare triple {74876#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {74876#false} is VALID [2022-02-21 04:23:31,047 INFO L290 TraceCheckUtils]: 94: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___6~0#1); {74876#false} is VALID [2022-02-21 04:23:31,048 INFO L290 TraceCheckUtils]: 95: Hoare triple {74876#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {74876#false} is VALID [2022-02-21 04:23:31,048 INFO L290 TraceCheckUtils]: 96: Hoare triple {74876#false} assume 1 == ~t8_pc~0; {74876#false} is VALID [2022-02-21 04:23:31,048 INFO L290 TraceCheckUtils]: 97: Hoare triple {74876#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {74876#false} is VALID [2022-02-21 04:23:31,048 INFO L290 TraceCheckUtils]: 98: Hoare triple {74876#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {74876#false} is VALID [2022-02-21 04:23:31,048 INFO L290 TraceCheckUtils]: 99: Hoare triple {74876#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {74876#false} is VALID [2022-02-21 04:23:31,048 INFO L290 TraceCheckUtils]: 100: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___7~0#1); {74876#false} is VALID [2022-02-21 04:23:31,048 INFO L290 TraceCheckUtils]: 101: Hoare triple {74876#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {74876#false} is VALID [2022-02-21 04:23:31,048 INFO L290 TraceCheckUtils]: 102: Hoare triple {74876#false} assume 1 == ~t9_pc~0; {74876#false} is VALID [2022-02-21 04:23:31,049 INFO L290 TraceCheckUtils]: 103: Hoare triple {74876#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {74876#false} is VALID [2022-02-21 04:23:31,049 INFO L290 TraceCheckUtils]: 104: Hoare triple {74876#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {74876#false} is VALID [2022-02-21 04:23:31,049 INFO L290 TraceCheckUtils]: 105: Hoare triple {74876#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {74876#false} is VALID [2022-02-21 04:23:31,049 INFO L290 TraceCheckUtils]: 106: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___8~0#1); {74876#false} is VALID [2022-02-21 04:23:31,049 INFO L290 TraceCheckUtils]: 107: Hoare triple {74876#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {74876#false} is VALID [2022-02-21 04:23:31,049 INFO L290 TraceCheckUtils]: 108: Hoare triple {74876#false} assume !(1 == ~t10_pc~0); {74876#false} is VALID [2022-02-21 04:23:31,049 INFO L290 TraceCheckUtils]: 109: Hoare triple {74876#false} is_transmit10_triggered_~__retres1~10#1 := 0; {74876#false} is VALID [2022-02-21 04:23:31,049 INFO L290 TraceCheckUtils]: 110: Hoare triple {74876#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {74876#false} is VALID [2022-02-21 04:23:31,050 INFO L290 TraceCheckUtils]: 111: Hoare triple {74876#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {74876#false} is VALID [2022-02-21 04:23:31,050 INFO L290 TraceCheckUtils]: 112: Hoare triple {74876#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {74876#false} is VALID [2022-02-21 04:23:31,050 INFO L290 TraceCheckUtils]: 113: Hoare triple {74876#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {74876#false} is VALID [2022-02-21 04:23:31,050 INFO L290 TraceCheckUtils]: 114: Hoare triple {74876#false} assume 1 == ~t11_pc~0; {74876#false} is VALID [2022-02-21 04:23:31,050 INFO L290 TraceCheckUtils]: 115: Hoare triple {74876#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {74876#false} is VALID [2022-02-21 04:23:31,050 INFO L290 TraceCheckUtils]: 116: Hoare triple {74876#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {74876#false} is VALID [2022-02-21 04:23:31,050 INFO L290 TraceCheckUtils]: 117: Hoare triple {74876#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {74876#false} is VALID [2022-02-21 04:23:31,051 INFO L290 TraceCheckUtils]: 118: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___10~0#1); {74876#false} is VALID [2022-02-21 04:23:31,051 INFO L290 TraceCheckUtils]: 119: Hoare triple {74876#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {74876#false} is VALID [2022-02-21 04:23:31,051 INFO L290 TraceCheckUtils]: 120: Hoare triple {74876#false} assume !(1 == ~t12_pc~0); {74876#false} is VALID [2022-02-21 04:23:31,051 INFO L290 TraceCheckUtils]: 121: Hoare triple {74876#false} is_transmit12_triggered_~__retres1~12#1 := 0; {74876#false} is VALID [2022-02-21 04:23:31,051 INFO L290 TraceCheckUtils]: 122: Hoare triple {74876#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {74876#false} is VALID [2022-02-21 04:23:31,051 INFO L290 TraceCheckUtils]: 123: Hoare triple {74876#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {74876#false} is VALID [2022-02-21 04:23:31,051 INFO L290 TraceCheckUtils]: 124: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___11~0#1); {74876#false} is VALID [2022-02-21 04:23:31,051 INFO L290 TraceCheckUtils]: 125: Hoare triple {74876#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {74876#false} is VALID [2022-02-21 04:23:31,052 INFO L290 TraceCheckUtils]: 126: Hoare triple {74876#false} assume 1 == ~t13_pc~0; {74876#false} is VALID [2022-02-21 04:23:31,052 INFO L290 TraceCheckUtils]: 127: Hoare triple {74876#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {74876#false} is VALID [2022-02-21 04:23:31,052 INFO L290 TraceCheckUtils]: 128: Hoare triple {74876#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {74876#false} is VALID [2022-02-21 04:23:31,052 INFO L290 TraceCheckUtils]: 129: Hoare triple {74876#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {74876#false} is VALID [2022-02-21 04:23:31,052 INFO L290 TraceCheckUtils]: 130: Hoare triple {74876#false} assume !(0 != activate_threads_~tmp___12~0#1); {74876#false} is VALID [2022-02-21 04:23:31,052 INFO L290 TraceCheckUtils]: 131: Hoare triple {74876#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {74876#false} is VALID [2022-02-21 04:23:31,052 INFO L290 TraceCheckUtils]: 132: Hoare triple {74876#false} assume !(1 == ~M_E~0); {74876#false} is VALID [2022-02-21 04:23:31,052 INFO L290 TraceCheckUtils]: 133: Hoare triple {74876#false} assume !(1 == ~T1_E~0); {74876#false} is VALID [2022-02-21 04:23:31,053 INFO L290 TraceCheckUtils]: 134: Hoare triple {74876#false} assume !(1 == ~T2_E~0); {74876#false} is VALID [2022-02-21 04:23:31,053 INFO L290 TraceCheckUtils]: 135: Hoare triple {74876#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {74876#false} is VALID [2022-02-21 04:23:31,053 INFO L290 TraceCheckUtils]: 136: Hoare triple {74876#false} assume !(1 == ~T4_E~0); {74876#false} is VALID [2022-02-21 04:23:31,053 INFO L290 TraceCheckUtils]: 137: Hoare triple {74876#false} assume !(1 == ~T5_E~0); {74876#false} is VALID [2022-02-21 04:23:31,053 INFO L290 TraceCheckUtils]: 138: Hoare triple {74876#false} assume !(1 == ~T6_E~0); {74876#false} is VALID [2022-02-21 04:23:31,053 INFO L290 TraceCheckUtils]: 139: Hoare triple {74876#false} assume !(1 == ~T7_E~0); {74876#false} is VALID [2022-02-21 04:23:31,053 INFO L290 TraceCheckUtils]: 140: Hoare triple {74876#false} assume !(1 == ~T8_E~0); {74876#false} is VALID [2022-02-21 04:23:31,054 INFO L290 TraceCheckUtils]: 141: Hoare triple {74876#false} assume !(1 == ~T9_E~0); {74876#false} is VALID [2022-02-21 04:23:31,054 INFO L290 TraceCheckUtils]: 142: Hoare triple {74876#false} assume !(1 == ~T10_E~0); {74876#false} is VALID [2022-02-21 04:23:31,054 INFO L290 TraceCheckUtils]: 143: Hoare triple {74876#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {74876#false} is VALID [2022-02-21 04:23:31,054 INFO L290 TraceCheckUtils]: 144: Hoare triple {74876#false} assume !(1 == ~T12_E~0); {74876#false} is VALID [2022-02-21 04:23:31,054 INFO L290 TraceCheckUtils]: 145: Hoare triple {74876#false} assume !(1 == ~T13_E~0); {74876#false} is VALID [2022-02-21 04:23:31,054 INFO L290 TraceCheckUtils]: 146: Hoare triple {74876#false} assume !(1 == ~E_M~0); {74876#false} is VALID [2022-02-21 04:23:31,054 INFO L290 TraceCheckUtils]: 147: Hoare triple {74876#false} assume !(1 == ~E_1~0); {74876#false} is VALID [2022-02-21 04:23:31,054 INFO L290 TraceCheckUtils]: 148: Hoare triple {74876#false} assume !(1 == ~E_2~0); {74876#false} is VALID [2022-02-21 04:23:31,055 INFO L290 TraceCheckUtils]: 149: Hoare triple {74876#false} assume !(1 == ~E_3~0); {74876#false} is VALID [2022-02-21 04:23:31,055 INFO L290 TraceCheckUtils]: 150: Hoare triple {74876#false} assume !(1 == ~E_4~0); {74876#false} is VALID [2022-02-21 04:23:31,055 INFO L290 TraceCheckUtils]: 151: Hoare triple {74876#false} assume 1 == ~E_5~0;~E_5~0 := 2; {74876#false} is VALID [2022-02-21 04:23:31,055 INFO L290 TraceCheckUtils]: 152: Hoare triple {74876#false} assume !(1 == ~E_6~0); {74876#false} is VALID [2022-02-21 04:23:31,055 INFO L290 TraceCheckUtils]: 153: Hoare triple {74876#false} assume !(1 == ~E_7~0); {74876#false} is VALID [2022-02-21 04:23:31,055 INFO L290 TraceCheckUtils]: 154: Hoare triple {74876#false} assume !(1 == ~E_8~0); {74876#false} is VALID [2022-02-21 04:23:31,055 INFO L290 TraceCheckUtils]: 155: Hoare triple {74876#false} assume !(1 == ~E_9~0); {74876#false} is VALID [2022-02-21 04:23:31,056 INFO L290 TraceCheckUtils]: 156: Hoare triple {74876#false} assume !(1 == ~E_10~0); {74876#false} is VALID [2022-02-21 04:23:31,056 INFO L290 TraceCheckUtils]: 157: Hoare triple {74876#false} assume !(1 == ~E_11~0); {74876#false} is VALID [2022-02-21 04:23:31,056 INFO L290 TraceCheckUtils]: 158: Hoare triple {74876#false} assume !(1 == ~E_12~0); {74876#false} is VALID [2022-02-21 04:23:31,056 INFO L290 TraceCheckUtils]: 159: Hoare triple {74876#false} assume 1 == ~E_13~0;~E_13~0 := 2; {74876#false} is VALID [2022-02-21 04:23:31,056 INFO L290 TraceCheckUtils]: 160: Hoare triple {74876#false} assume { :end_inline_reset_delta_events } true; {74876#false} is VALID [2022-02-21 04:23:31,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:31,057 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:31,057 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343788039] [2022-02-21 04:23:31,057 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [343788039] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:31,057 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:31,057 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:31,057 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675929294] [2022-02-21 04:23:31,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:31,058 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:31,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:31,058 INFO L85 PathProgramCache]: Analyzing trace with hash 1171252195, now seen corresponding path program 1 times [2022-02-21 04:23:31,058 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:31,058 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797535868] [2022-02-21 04:23:31,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:31,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:31,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:31,082 INFO L290 TraceCheckUtils]: 0: Hoare triple {74878#true} assume !false; {74878#true} is VALID [2022-02-21 04:23:31,082 INFO L290 TraceCheckUtils]: 1: Hoare triple {74878#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {74878#true} is VALID [2022-02-21 04:23:31,082 INFO L290 TraceCheckUtils]: 2: Hoare triple {74878#true} assume !false; {74878#true} is VALID [2022-02-21 04:23:31,082 INFO L290 TraceCheckUtils]: 3: Hoare triple {74878#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {74878#true} is VALID [2022-02-21 04:23:31,082 INFO L290 TraceCheckUtils]: 4: Hoare triple {74878#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {74878#true} is VALID [2022-02-21 04:23:31,083 INFO L290 TraceCheckUtils]: 5: Hoare triple {74878#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {74878#true} is VALID [2022-02-21 04:23:31,083 INFO L290 TraceCheckUtils]: 6: Hoare triple {74878#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {74878#true} is VALID [2022-02-21 04:23:31,083 INFO L290 TraceCheckUtils]: 7: Hoare triple {74878#true} assume !(0 != eval_~tmp~0#1); {74878#true} is VALID [2022-02-21 04:23:31,083 INFO L290 TraceCheckUtils]: 8: Hoare triple {74878#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {74878#true} is VALID [2022-02-21 04:23:31,083 INFO L290 TraceCheckUtils]: 9: Hoare triple {74878#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {74878#true} is VALID [2022-02-21 04:23:31,083 INFO L290 TraceCheckUtils]: 10: Hoare triple {74878#true} assume 0 == ~M_E~0;~M_E~0 := 1; {74878#true} is VALID [2022-02-21 04:23:31,083 INFO L290 TraceCheckUtils]: 11: Hoare triple {74878#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {74878#true} is VALID [2022-02-21 04:23:31,084 INFO L290 TraceCheckUtils]: 12: Hoare triple {74878#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {74878#true} is VALID [2022-02-21 04:23:31,084 INFO L290 TraceCheckUtils]: 13: Hoare triple {74878#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {74878#true} is VALID [2022-02-21 04:23:31,084 INFO L290 TraceCheckUtils]: 14: Hoare triple {74878#true} assume !(0 == ~T4_E~0); {74878#true} is VALID [2022-02-21 04:23:31,084 INFO L290 TraceCheckUtils]: 15: Hoare triple {74878#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {74878#true} is VALID [2022-02-21 04:23:31,084 INFO L290 TraceCheckUtils]: 16: Hoare triple {74878#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {74878#true} is VALID [2022-02-21 04:23:31,085 INFO L290 TraceCheckUtils]: 17: Hoare triple {74878#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,085 INFO L290 TraceCheckUtils]: 18: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,085 INFO L290 TraceCheckUtils]: 19: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,085 INFO L290 TraceCheckUtils]: 20: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,086 INFO L290 TraceCheckUtils]: 21: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,086 INFO L290 TraceCheckUtils]: 22: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,086 INFO L290 TraceCheckUtils]: 23: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,086 INFO L290 TraceCheckUtils]: 24: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,087 INFO L290 TraceCheckUtils]: 25: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,087 INFO L290 TraceCheckUtils]: 26: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,087 INFO L290 TraceCheckUtils]: 27: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,087 INFO L290 TraceCheckUtils]: 28: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,088 INFO L290 TraceCheckUtils]: 29: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,088 INFO L290 TraceCheckUtils]: 30: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,088 INFO L290 TraceCheckUtils]: 31: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,088 INFO L290 TraceCheckUtils]: 32: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,089 INFO L290 TraceCheckUtils]: 33: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,089 INFO L290 TraceCheckUtils]: 34: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,089 INFO L290 TraceCheckUtils]: 35: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,090 INFO L290 TraceCheckUtils]: 36: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,090 INFO L290 TraceCheckUtils]: 37: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,090 INFO L290 TraceCheckUtils]: 38: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,090 INFO L290 TraceCheckUtils]: 39: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~m_pc~0); {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,091 INFO L290 TraceCheckUtils]: 40: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,091 INFO L290 TraceCheckUtils]: 41: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,091 INFO L290 TraceCheckUtils]: 42: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,091 INFO L290 TraceCheckUtils]: 43: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,092 INFO L290 TraceCheckUtils]: 44: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,092 INFO L290 TraceCheckUtils]: 45: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t1_pc~0); {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,092 INFO L290 TraceCheckUtils]: 46: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,092 INFO L290 TraceCheckUtils]: 47: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,093 INFO L290 TraceCheckUtils]: 48: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,093 INFO L290 TraceCheckUtils]: 49: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,093 INFO L290 TraceCheckUtils]: 50: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,094 INFO L290 TraceCheckUtils]: 51: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t2_pc~0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,094 INFO L290 TraceCheckUtils]: 52: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,094 INFO L290 TraceCheckUtils]: 53: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,094 INFO L290 TraceCheckUtils]: 54: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,095 INFO L290 TraceCheckUtils]: 55: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,095 INFO L290 TraceCheckUtils]: 56: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,095 INFO L290 TraceCheckUtils]: 57: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,095 INFO L290 TraceCheckUtils]: 58: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,096 INFO L290 TraceCheckUtils]: 59: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,096 INFO L290 TraceCheckUtils]: 60: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,096 INFO L290 TraceCheckUtils]: 61: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,097 INFO L290 TraceCheckUtils]: 62: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,097 INFO L290 TraceCheckUtils]: 63: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,097 INFO L290 TraceCheckUtils]: 64: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,097 INFO L290 TraceCheckUtils]: 65: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,098 INFO L290 TraceCheckUtils]: 66: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,098 INFO L290 TraceCheckUtils]: 67: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,098 INFO L290 TraceCheckUtils]: 68: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,098 INFO L290 TraceCheckUtils]: 69: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,099 INFO L290 TraceCheckUtils]: 70: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,099 INFO L290 TraceCheckUtils]: 71: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,099 INFO L290 TraceCheckUtils]: 72: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,099 INFO L290 TraceCheckUtils]: 73: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,100 INFO L290 TraceCheckUtils]: 74: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,100 INFO L290 TraceCheckUtils]: 75: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,100 INFO L290 TraceCheckUtils]: 76: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,101 INFO L290 TraceCheckUtils]: 77: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,101 INFO L290 TraceCheckUtils]: 78: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,101 INFO L290 TraceCheckUtils]: 79: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,101 INFO L290 TraceCheckUtils]: 80: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,102 INFO L290 TraceCheckUtils]: 81: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,102 INFO L290 TraceCheckUtils]: 82: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,102 INFO L290 TraceCheckUtils]: 83: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,102 INFO L290 TraceCheckUtils]: 84: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,103 INFO L290 TraceCheckUtils]: 85: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,103 INFO L290 TraceCheckUtils]: 86: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,103 INFO L290 TraceCheckUtils]: 87: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t8_pc~0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,103 INFO L290 TraceCheckUtils]: 88: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,104 INFO L290 TraceCheckUtils]: 89: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,104 INFO L290 TraceCheckUtils]: 90: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,104 INFO L290 TraceCheckUtils]: 91: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,105 INFO L290 TraceCheckUtils]: 92: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,105 INFO L290 TraceCheckUtils]: 93: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t9_pc~0); {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,105 INFO L290 TraceCheckUtils]: 94: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,105 INFO L290 TraceCheckUtils]: 95: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,106 INFO L290 TraceCheckUtils]: 96: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,106 INFO L290 TraceCheckUtils]: 97: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,106 INFO L290 TraceCheckUtils]: 98: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,106 INFO L290 TraceCheckUtils]: 99: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t10_pc~0); {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,107 INFO L290 TraceCheckUtils]: 100: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,107 INFO L290 TraceCheckUtils]: 101: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,107 INFO L290 TraceCheckUtils]: 102: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,107 INFO L290 TraceCheckUtils]: 103: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,108 INFO L290 TraceCheckUtils]: 104: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,108 INFO L290 TraceCheckUtils]: 105: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,108 INFO L290 TraceCheckUtils]: 106: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,109 INFO L290 TraceCheckUtils]: 107: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,109 INFO L290 TraceCheckUtils]: 108: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,109 INFO L290 TraceCheckUtils]: 109: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,109 INFO L290 TraceCheckUtils]: 110: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,110 INFO L290 TraceCheckUtils]: 111: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,110 INFO L290 TraceCheckUtils]: 112: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,110 INFO L290 TraceCheckUtils]: 113: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,110 INFO L290 TraceCheckUtils]: 114: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,111 INFO L290 TraceCheckUtils]: 115: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,111 INFO L290 TraceCheckUtils]: 116: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,111 INFO L290 TraceCheckUtils]: 117: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t13_pc~0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,111 INFO L290 TraceCheckUtils]: 118: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,112 INFO L290 TraceCheckUtils]: 119: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,112 INFO L290 TraceCheckUtils]: 120: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,112 INFO L290 TraceCheckUtils]: 121: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,113 INFO L290 TraceCheckUtils]: 122: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,113 INFO L290 TraceCheckUtils]: 123: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,113 INFO L290 TraceCheckUtils]: 124: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,113 INFO L290 TraceCheckUtils]: 125: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,114 INFO L290 TraceCheckUtils]: 126: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,114 INFO L290 TraceCheckUtils]: 127: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,114 INFO L290 TraceCheckUtils]: 128: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,114 INFO L290 TraceCheckUtils]: 129: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {74880#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:31,115 INFO L290 TraceCheckUtils]: 130: Hoare triple {74880#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {74879#false} is VALID [2022-02-21 04:23:31,115 INFO L290 TraceCheckUtils]: 131: Hoare triple {74879#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,115 INFO L290 TraceCheckUtils]: 132: Hoare triple {74879#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,115 INFO L290 TraceCheckUtils]: 133: Hoare triple {74879#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,115 INFO L290 TraceCheckUtils]: 134: Hoare triple {74879#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,115 INFO L290 TraceCheckUtils]: 135: Hoare triple {74879#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,115 INFO L290 TraceCheckUtils]: 136: Hoare triple {74879#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,116 INFO L290 TraceCheckUtils]: 137: Hoare triple {74879#false} assume 1 == ~E_M~0;~E_M~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,116 INFO L290 TraceCheckUtils]: 138: Hoare triple {74879#false} assume !(1 == ~E_1~0); {74879#false} is VALID [2022-02-21 04:23:31,116 INFO L290 TraceCheckUtils]: 139: Hoare triple {74879#false} assume 1 == ~E_2~0;~E_2~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,116 INFO L290 TraceCheckUtils]: 140: Hoare triple {74879#false} assume 1 == ~E_3~0;~E_3~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,116 INFO L290 TraceCheckUtils]: 141: Hoare triple {74879#false} assume 1 == ~E_4~0;~E_4~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,116 INFO L290 TraceCheckUtils]: 142: Hoare triple {74879#false} assume 1 == ~E_5~0;~E_5~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,116 INFO L290 TraceCheckUtils]: 143: Hoare triple {74879#false} assume 1 == ~E_6~0;~E_6~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,117 INFO L290 TraceCheckUtils]: 144: Hoare triple {74879#false} assume 1 == ~E_7~0;~E_7~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,117 INFO L290 TraceCheckUtils]: 145: Hoare triple {74879#false} assume 1 == ~E_8~0;~E_8~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,117 INFO L290 TraceCheckUtils]: 146: Hoare triple {74879#false} assume !(1 == ~E_9~0); {74879#false} is VALID [2022-02-21 04:23:31,117 INFO L290 TraceCheckUtils]: 147: Hoare triple {74879#false} assume 1 == ~E_10~0;~E_10~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,117 INFO L290 TraceCheckUtils]: 148: Hoare triple {74879#false} assume 1 == ~E_11~0;~E_11~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,117 INFO L290 TraceCheckUtils]: 149: Hoare triple {74879#false} assume 1 == ~E_12~0;~E_12~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,117 INFO L290 TraceCheckUtils]: 150: Hoare triple {74879#false} assume 1 == ~E_13~0;~E_13~0 := 2; {74879#false} is VALID [2022-02-21 04:23:31,117 INFO L290 TraceCheckUtils]: 151: Hoare triple {74879#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {74879#false} is VALID [2022-02-21 04:23:31,118 INFO L290 TraceCheckUtils]: 152: Hoare triple {74879#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {74879#false} is VALID [2022-02-21 04:23:31,118 INFO L290 TraceCheckUtils]: 153: Hoare triple {74879#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {74879#false} is VALID [2022-02-21 04:23:31,118 INFO L290 TraceCheckUtils]: 154: Hoare triple {74879#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {74879#false} is VALID [2022-02-21 04:23:31,118 INFO L290 TraceCheckUtils]: 155: Hoare triple {74879#false} assume !(0 == start_simulation_~tmp~3#1); {74879#false} is VALID [2022-02-21 04:23:31,118 INFO L290 TraceCheckUtils]: 156: Hoare triple {74879#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {74879#false} is VALID [2022-02-21 04:23:31,118 INFO L290 TraceCheckUtils]: 157: Hoare triple {74879#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {74879#false} is VALID [2022-02-21 04:23:31,118 INFO L290 TraceCheckUtils]: 158: Hoare triple {74879#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {74879#false} is VALID [2022-02-21 04:23:31,119 INFO L290 TraceCheckUtils]: 159: Hoare triple {74879#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {74879#false} is VALID [2022-02-21 04:23:31,119 INFO L290 TraceCheckUtils]: 160: Hoare triple {74879#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {74879#false} is VALID [2022-02-21 04:23:31,119 INFO L290 TraceCheckUtils]: 161: Hoare triple {74879#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {74879#false} is VALID [2022-02-21 04:23:31,119 INFO L290 TraceCheckUtils]: 162: Hoare triple {74879#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {74879#false} is VALID [2022-02-21 04:23:31,119 INFO L290 TraceCheckUtils]: 163: Hoare triple {74879#false} assume !(0 != start_simulation_~tmp___0~1#1); {74879#false} is VALID [2022-02-21 04:23:31,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:31,120 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:31,120 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797535868] [2022-02-21 04:23:31,120 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797535868] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:31,120 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:31,120 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:31,120 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [524082179] [2022-02-21 04:23:31,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:31,121 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:31,121 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:31,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:31,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:31,122 INFO L87 Difference]: Start difference. First operand 2021 states and 2984 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:32,389 INFO L93 Difference]: Finished difference Result 2021 states and 2983 transitions. [2022-02-21 04:23:32,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:32,389 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,472 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:32,472 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2983 transitions. [2022-02-21 04:23:32,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:32,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2983 transitions. [2022-02-21 04:23:32,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:32,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:32,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2983 transitions. [2022-02-21 04:23:32,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:32,640 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2022-02-21 04:23:32,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2983 transitions. [2022-02-21 04:23:32,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:32,654 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:32,656 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2983 transitions. Second operand has 2021 states, 2021 states have (on average 1.4760019792182089) internal successors, (2983), 2020 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,657 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2983 transitions. Second operand has 2021 states, 2021 states have (on average 1.4760019792182089) internal successors, (2983), 2020 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,658 INFO L87 Difference]: Start difference. First operand 2021 states and 2983 transitions. Second operand has 2021 states, 2021 states have (on average 1.4760019792182089) internal successors, (2983), 2020 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:32,739 INFO L93 Difference]: Finished difference Result 2021 states and 2983 transitions. [2022-02-21 04:23:32,739 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2983 transitions. [2022-02-21 04:23:32,741 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:32,741 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:32,743 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.4760019792182089) internal successors, (2983), 2020 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2983 transitions. [2022-02-21 04:23:32,744 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.4760019792182089) internal successors, (2983), 2020 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2983 transitions. [2022-02-21 04:23:32,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:32,826 INFO L93 Difference]: Finished difference Result 2021 states and 2983 transitions. [2022-02-21 04:23:32,826 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2983 transitions. [2022-02-21 04:23:32,827 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:32,827 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:32,827 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:32,828 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:32,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4760019792182089) internal successors, (2983), 2020 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2983 transitions. [2022-02-21 04:23:32,909 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2022-02-21 04:23:32,910 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2022-02-21 04:23:32,910 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:23:32,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2983 transitions. [2022-02-21 04:23:32,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:32,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:32,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:32,913 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:32,913 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:32,914 INFO L791 eck$LassoCheckResult]: Stem: 77778#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 77779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 77510#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77511#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78901#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 78902#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77697#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77698#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77732#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78569#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78570#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 78682#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 78683#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77516#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77517#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 78719#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 78041#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 78042#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 78623#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 78889#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 78779#L1286-2 assume !(0 == ~T1_E~0); 77425#L1291-1 assume !(0 == ~T2_E~0); 77426#L1296-1 assume !(0 == ~T3_E~0); 78131#L1301-1 assume !(0 == ~T4_E~0); 78132#L1306-1 assume !(0 == ~T5_E~0); 78632#L1311-1 assume !(0 == ~T6_E~0); 77385#L1316-1 assume !(0 == ~T7_E~0); 77386#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 78151#L1326-1 assume !(0 == ~T9_E~0); 77200#L1331-1 assume !(0 == ~T10_E~0); 76906#L1336-1 assume !(0 == ~T11_E~0); 76907#L1341-1 assume !(0 == ~T12_E~0); 76958#L1346-1 assume !(0 == ~T13_E~0); 76959#L1351-1 assume !(0 == ~E_M~0); 77332#L1356-1 assume !(0 == ~E_1~0); 77333#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 78852#L1366-1 assume !(0 == ~E_3~0); 77378#L1371-1 assume !(0 == ~E_4~0); 77379#L1376-1 assume !(0 == ~E_5~0); 78192#L1381-1 assume !(0 == ~E_6~0); 78193#L1386-1 assume !(0 == ~E_7~0); 78880#L1391-1 assume !(0 == ~E_8~0); 78893#L1396-1 assume !(0 == ~E_9~0); 78075#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 78076#L1406-1 assume !(0 == ~E_11~0); 78378#L1411-1 assume !(0 == ~E_12~0); 78379#L1416-1 assume !(0 == ~E_13~0); 77999#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77837#L635 assume !(1 == ~m_pc~0); 76976#L635-2 is_master_triggered_~__retres1~0#1 := 0; 76977#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77327#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77963#L1598 assume !(0 != activate_threads_~tmp~1#1); 77155#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77156#L654 assume 1 == ~t1_pc~0; 77861#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77862#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78877#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77943#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 77944#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77203#L673 assume 1 == ~t2_pc~0; 77204#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78348#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78349#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78907#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 78914#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78022#L692 assume !(1 == ~t3_pc~0); 77839#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77840#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77699#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77667#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77668#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77228#L711 assume 1 == ~t4_pc~0; 77229#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77712#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78169#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76931#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 76932#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78900#L730 assume !(1 == ~t5_pc~0); 78282#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 77110#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77111#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77238#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 77239#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77581#L749 assume 1 == ~t6_pc~0; 77355#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77115#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77547#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77548#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 77770#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76911#L768 assume !(1 == ~t7_pc~0); 76912#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 78216#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77148#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77149#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 78235#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77387#L787 assume 1 == ~t8_pc~0; 77388#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 78583#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78747#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78748#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 76956#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76957#L806 assume 1 == ~t9_pc~0; 78594#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76991#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76992#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77240#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 77241#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78577#L825 assume !(1 == ~t10_pc~0); 78578#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 78183#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78184#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 77328#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77329#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77912#L844 assume 1 == ~t11_pc~0; 77602#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77603#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77969#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77970#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 78565#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78566#L863 assume !(1 == ~t12_pc~0); 77091#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 77090#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77318#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 78657#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 78658#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78036#L882 assume 1 == ~t13_pc~0; 78037#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 78321#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78822#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 78625#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 78308#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78309#L1434 assume !(1 == ~M_E~0); 78830#L1434-2 assume !(1 == ~T1_E~0); 78906#L1439-1 assume !(1 == ~T2_E~0); 77221#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77222#L1449-1 assume !(1 == ~T4_E~0); 77664#L1454-1 assume !(1 == ~T5_E~0); 77665#L1459-1 assume !(1 == ~T6_E~0); 78236#L1464-1 assume !(1 == ~T7_E~0); 78237#L1469-1 assume !(1 == ~T8_E~0); 78322#L1474-1 assume !(1 == ~T9_E~0); 78000#L1479-1 assume !(1 == ~T10_E~0); 78001#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78244#L1489-1 assume !(1 == ~T12_E~0); 77878#L1494-1 assume !(1 == ~T13_E~0); 77879#L1499-1 assume !(1 == ~E_M~0); 78060#L1504-1 assume !(1 == ~E_1~0); 78061#L1509-1 assume !(1 == ~E_2~0); 78674#L1514-1 assume !(1 == ~E_3~0); 78359#L1519-1 assume !(1 == ~E_4~0); 78360#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 78864#L1529-1 assume !(1 == ~E_6~0); 78865#L1534-1 assume !(1 == ~E_7~0); 77011#L1539-1 assume !(1 == ~E_8~0); 77012#L1544-1 assume !(1 == ~E_9~0); 77442#L1549-1 assume !(1 == ~E_10~0); 78842#L1554-1 assume !(1 == ~E_11~0); 78840#L1559-1 assume !(1 == ~E_12~0); 78702#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 78703#L1569-1 assume { :end_inline_reset_delta_events } true; 78858#L1935-2 [2022-02-21 04:23:32,914 INFO L793 eck$LassoCheckResult]: Loop: 78858#L1935-2 assume !false; 77020#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77021#L1261 assume !false; 78248#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 78249#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77151#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77321#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77322#L1074 assume !(0 != eval_~tmp~0#1); 77679#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78277#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78678#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 78734#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78453#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 78454#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78890#L1301-3 assume !(0 == ~T4_E~0); 78848#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77956#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 77255#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 77256#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 77361#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78097#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 78362#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 78363#L1341-3 assume !(0 == ~T12_E~0); 77657#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 77648#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 77592#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77593#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 78173#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76946#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76947#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78689#L1381-3 assume !(0 == ~E_6~0); 78538#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 78539#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 78720#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 78721#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77326#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77157#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 77158#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 77785#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77035#L635-45 assume !(1 == ~m_pc~0); 77037#L635-47 is_master_triggered_~__retres1~0#1 := 0; 77830#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78310#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78564#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77344#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77345#L654-45 assume 1 == ~t1_pc~0; 78165#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 78513#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76998#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76999#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77024#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77851#L673-45 assume 1 == ~t2_pc~0; 77853#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78176#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78177#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78802#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 78622#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77469#L692-45 assume !(1 == ~t3_pc~0); 77195#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 77196#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78240#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77523#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77524#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77836#L711-45 assume 1 == ~t4_pc~0; 77960#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77961#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77813#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77814#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78217#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77368#L730-45 assume 1 == ~t5_pc~0; 77206#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77207#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77616#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77617#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78368#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77179#L749-45 assume 1 == ~t6_pc~0; 77181#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 78580#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78343#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78344#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78495#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77495#L768-45 assume !(1 == ~t7_pc~0); 77497#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 77635#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78439#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78440#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78479#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78480#L787-45 assume !(1 == ~t8_pc~0); 78649#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 77641#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77642#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78058#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78059#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78367#L806-45 assume 1 == ~t9_pc~0; 78843#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77055#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77880#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77708#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77620#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77621#L825-45 assume !(1 == ~t10_pc~0); 78144#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 78145#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78250#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78251#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78403#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77263#L844-45 assume 1 == ~t11_pc~0; 77265#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77786#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77787#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77803#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 78214#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77303#L863-45 assume !(1 == ~t12_pc~0); 77305#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 76904#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76905#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77420#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 77421#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78220#L882-45 assume !(1 == ~t13_pc~0); 77750#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 76923#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76924#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 77532#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 78711#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78327#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 78328#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78512#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77217#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77218#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77380#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78317#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78318#L1464-3 assume !(1 == ~T7_E~0); 78764#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78691#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78692#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78766#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77958#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 77959#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 78619#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78254#L1504-3 assume !(1 == ~E_1~0); 78255#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78700#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78740#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77881#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77882#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78787#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 78182#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77636#L1544-3 assume !(1 == ~E_9~0); 77637#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 78152#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 77268#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 77269#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 78418#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 78419#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77153#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77718#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 78389#L1954 assume !(0 == start_simulation_~tmp~3#1); 78391#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 78641#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77436#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 78477#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 78607#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78608#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78698#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 78760#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 78858#L1935-2 [2022-02-21 04:23:32,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:32,915 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2022-02-21 04:23:32,915 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:32,915 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542769464] [2022-02-21 04:23:32,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:32,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:32,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:32,935 INFO L290 TraceCheckUtils]: 0: Hoare triple {82968#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {82968#true} is VALID [2022-02-21 04:23:32,936 INFO L290 TraceCheckUtils]: 1: Hoare triple {82968#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,936 INFO L290 TraceCheckUtils]: 2: Hoare triple {82970#(= ~t11_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,936 INFO L290 TraceCheckUtils]: 3: Hoare triple {82970#(= ~t11_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,936 INFO L290 TraceCheckUtils]: 4: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,937 INFO L290 TraceCheckUtils]: 5: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,937 INFO L290 TraceCheckUtils]: 6: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,937 INFO L290 TraceCheckUtils]: 7: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,938 INFO L290 TraceCheckUtils]: 8: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,938 INFO L290 TraceCheckUtils]: 9: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,939 INFO L290 TraceCheckUtils]: 10: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,939 INFO L290 TraceCheckUtils]: 11: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,940 INFO L290 TraceCheckUtils]: 12: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,940 INFO L290 TraceCheckUtils]: 13: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,940 INFO L290 TraceCheckUtils]: 14: Hoare triple {82970#(= ~t11_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {82970#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:32,940 INFO L290 TraceCheckUtils]: 15: Hoare triple {82970#(= ~t11_i~0 1)} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {82969#false} is VALID [2022-02-21 04:23:32,941 INFO L290 TraceCheckUtils]: 16: Hoare triple {82969#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {82969#false} is VALID [2022-02-21 04:23:32,941 INFO L290 TraceCheckUtils]: 17: Hoare triple {82969#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {82969#false} is VALID [2022-02-21 04:23:32,941 INFO L290 TraceCheckUtils]: 18: Hoare triple {82969#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {82969#false} is VALID [2022-02-21 04:23:32,941 INFO L290 TraceCheckUtils]: 19: Hoare triple {82969#false} assume 0 == ~M_E~0;~M_E~0 := 1; {82969#false} is VALID [2022-02-21 04:23:32,941 INFO L290 TraceCheckUtils]: 20: Hoare triple {82969#false} assume !(0 == ~T1_E~0); {82969#false} is VALID [2022-02-21 04:23:32,941 INFO L290 TraceCheckUtils]: 21: Hoare triple {82969#false} assume !(0 == ~T2_E~0); {82969#false} is VALID [2022-02-21 04:23:32,941 INFO L290 TraceCheckUtils]: 22: Hoare triple {82969#false} assume !(0 == ~T3_E~0); {82969#false} is VALID [2022-02-21 04:23:32,941 INFO L290 TraceCheckUtils]: 23: Hoare triple {82969#false} assume !(0 == ~T4_E~0); {82969#false} is VALID [2022-02-21 04:23:32,942 INFO L290 TraceCheckUtils]: 24: Hoare triple {82969#false} assume !(0 == ~T5_E~0); {82969#false} is VALID [2022-02-21 04:23:32,942 INFO L290 TraceCheckUtils]: 25: Hoare triple {82969#false} assume !(0 == ~T6_E~0); {82969#false} is VALID [2022-02-21 04:23:32,942 INFO L290 TraceCheckUtils]: 26: Hoare triple {82969#false} assume !(0 == ~T7_E~0); {82969#false} is VALID [2022-02-21 04:23:32,942 INFO L290 TraceCheckUtils]: 27: Hoare triple {82969#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {82969#false} is VALID [2022-02-21 04:23:32,942 INFO L290 TraceCheckUtils]: 28: Hoare triple {82969#false} assume !(0 == ~T9_E~0); {82969#false} is VALID [2022-02-21 04:23:32,942 INFO L290 TraceCheckUtils]: 29: Hoare triple {82969#false} assume !(0 == ~T10_E~0); {82969#false} is VALID [2022-02-21 04:23:32,942 INFO L290 TraceCheckUtils]: 30: Hoare triple {82969#false} assume !(0 == ~T11_E~0); {82969#false} is VALID [2022-02-21 04:23:32,943 INFO L290 TraceCheckUtils]: 31: Hoare triple {82969#false} assume !(0 == ~T12_E~0); {82969#false} is VALID [2022-02-21 04:23:32,943 INFO L290 TraceCheckUtils]: 32: Hoare triple {82969#false} assume !(0 == ~T13_E~0); {82969#false} is VALID [2022-02-21 04:23:32,943 INFO L290 TraceCheckUtils]: 33: Hoare triple {82969#false} assume !(0 == ~E_M~0); {82969#false} is VALID [2022-02-21 04:23:32,943 INFO L290 TraceCheckUtils]: 34: Hoare triple {82969#false} assume !(0 == ~E_1~0); {82969#false} is VALID [2022-02-21 04:23:32,943 INFO L290 TraceCheckUtils]: 35: Hoare triple {82969#false} assume 0 == ~E_2~0;~E_2~0 := 1; {82969#false} is VALID [2022-02-21 04:23:32,943 INFO L290 TraceCheckUtils]: 36: Hoare triple {82969#false} assume !(0 == ~E_3~0); {82969#false} is VALID [2022-02-21 04:23:32,943 INFO L290 TraceCheckUtils]: 37: Hoare triple {82969#false} assume !(0 == ~E_4~0); {82969#false} is VALID [2022-02-21 04:23:32,949 INFO L290 TraceCheckUtils]: 38: Hoare triple {82969#false} assume !(0 == ~E_5~0); {82969#false} is VALID [2022-02-21 04:23:32,950 INFO L290 TraceCheckUtils]: 39: Hoare triple {82969#false} assume !(0 == ~E_6~0); {82969#false} is VALID [2022-02-21 04:23:32,950 INFO L290 TraceCheckUtils]: 40: Hoare triple {82969#false} assume !(0 == ~E_7~0); {82969#false} is VALID [2022-02-21 04:23:32,950 INFO L290 TraceCheckUtils]: 41: Hoare triple {82969#false} assume !(0 == ~E_8~0); {82969#false} is VALID [2022-02-21 04:23:32,950 INFO L290 TraceCheckUtils]: 42: Hoare triple {82969#false} assume !(0 == ~E_9~0); {82969#false} is VALID [2022-02-21 04:23:32,950 INFO L290 TraceCheckUtils]: 43: Hoare triple {82969#false} assume 0 == ~E_10~0;~E_10~0 := 1; {82969#false} is VALID [2022-02-21 04:23:32,950 INFO L290 TraceCheckUtils]: 44: Hoare triple {82969#false} assume !(0 == ~E_11~0); {82969#false} is VALID [2022-02-21 04:23:32,951 INFO L290 TraceCheckUtils]: 45: Hoare triple {82969#false} assume !(0 == ~E_12~0); {82969#false} is VALID [2022-02-21 04:23:32,951 INFO L290 TraceCheckUtils]: 46: Hoare triple {82969#false} assume !(0 == ~E_13~0); {82969#false} is VALID [2022-02-21 04:23:32,951 INFO L290 TraceCheckUtils]: 47: Hoare triple {82969#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {82969#false} is VALID [2022-02-21 04:23:32,951 INFO L290 TraceCheckUtils]: 48: Hoare triple {82969#false} assume !(1 == ~m_pc~0); {82969#false} is VALID [2022-02-21 04:23:32,951 INFO L290 TraceCheckUtils]: 49: Hoare triple {82969#false} is_master_triggered_~__retres1~0#1 := 0; {82969#false} is VALID [2022-02-21 04:23:32,951 INFO L290 TraceCheckUtils]: 50: Hoare triple {82969#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {82969#false} is VALID [2022-02-21 04:23:32,951 INFO L290 TraceCheckUtils]: 51: Hoare triple {82969#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {82969#false} is VALID [2022-02-21 04:23:32,952 INFO L290 TraceCheckUtils]: 52: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp~1#1); {82969#false} is VALID [2022-02-21 04:23:32,952 INFO L290 TraceCheckUtils]: 53: Hoare triple {82969#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {82969#false} is VALID [2022-02-21 04:23:32,952 INFO L290 TraceCheckUtils]: 54: Hoare triple {82969#false} assume 1 == ~t1_pc~0; {82969#false} is VALID [2022-02-21 04:23:32,952 INFO L290 TraceCheckUtils]: 55: Hoare triple {82969#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {82969#false} is VALID [2022-02-21 04:23:32,952 INFO L290 TraceCheckUtils]: 56: Hoare triple {82969#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {82969#false} is VALID [2022-02-21 04:23:32,952 INFO L290 TraceCheckUtils]: 57: Hoare triple {82969#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {82969#false} is VALID [2022-02-21 04:23:32,952 INFO L290 TraceCheckUtils]: 58: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___0~0#1); {82969#false} is VALID [2022-02-21 04:23:32,952 INFO L290 TraceCheckUtils]: 59: Hoare triple {82969#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {82969#false} is VALID [2022-02-21 04:23:32,953 INFO L290 TraceCheckUtils]: 60: Hoare triple {82969#false} assume 1 == ~t2_pc~0; {82969#false} is VALID [2022-02-21 04:23:32,953 INFO L290 TraceCheckUtils]: 61: Hoare triple {82969#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {82969#false} is VALID [2022-02-21 04:23:32,953 INFO L290 TraceCheckUtils]: 62: Hoare triple {82969#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {82969#false} is VALID [2022-02-21 04:23:32,953 INFO L290 TraceCheckUtils]: 63: Hoare triple {82969#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {82969#false} is VALID [2022-02-21 04:23:32,953 INFO L290 TraceCheckUtils]: 64: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___1~0#1); {82969#false} is VALID [2022-02-21 04:23:32,953 INFO L290 TraceCheckUtils]: 65: Hoare triple {82969#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {82969#false} is VALID [2022-02-21 04:23:32,953 INFO L290 TraceCheckUtils]: 66: Hoare triple {82969#false} assume !(1 == ~t3_pc~0); {82969#false} is VALID [2022-02-21 04:23:32,953 INFO L290 TraceCheckUtils]: 67: Hoare triple {82969#false} is_transmit3_triggered_~__retres1~3#1 := 0; {82969#false} is VALID [2022-02-21 04:23:32,954 INFO L290 TraceCheckUtils]: 68: Hoare triple {82969#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {82969#false} is VALID [2022-02-21 04:23:32,954 INFO L290 TraceCheckUtils]: 69: Hoare triple {82969#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {82969#false} is VALID [2022-02-21 04:23:32,954 INFO L290 TraceCheckUtils]: 70: Hoare triple {82969#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {82969#false} is VALID [2022-02-21 04:23:32,954 INFO L290 TraceCheckUtils]: 71: Hoare triple {82969#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {82969#false} is VALID [2022-02-21 04:23:32,954 INFO L290 TraceCheckUtils]: 72: Hoare triple {82969#false} assume 1 == ~t4_pc~0; {82969#false} is VALID [2022-02-21 04:23:32,954 INFO L290 TraceCheckUtils]: 73: Hoare triple {82969#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {82969#false} is VALID [2022-02-21 04:23:32,954 INFO L290 TraceCheckUtils]: 74: Hoare triple {82969#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {82969#false} is VALID [2022-02-21 04:23:32,955 INFO L290 TraceCheckUtils]: 75: Hoare triple {82969#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {82969#false} is VALID [2022-02-21 04:23:32,955 INFO L290 TraceCheckUtils]: 76: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___3~0#1); {82969#false} is VALID [2022-02-21 04:23:32,955 INFO L290 TraceCheckUtils]: 77: Hoare triple {82969#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {82969#false} is VALID [2022-02-21 04:23:32,955 INFO L290 TraceCheckUtils]: 78: Hoare triple {82969#false} assume !(1 == ~t5_pc~0); {82969#false} is VALID [2022-02-21 04:23:32,955 INFO L290 TraceCheckUtils]: 79: Hoare triple {82969#false} is_transmit5_triggered_~__retres1~5#1 := 0; {82969#false} is VALID [2022-02-21 04:23:32,955 INFO L290 TraceCheckUtils]: 80: Hoare triple {82969#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {82969#false} is VALID [2022-02-21 04:23:32,955 INFO L290 TraceCheckUtils]: 81: Hoare triple {82969#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {82969#false} is VALID [2022-02-21 04:23:32,955 INFO L290 TraceCheckUtils]: 82: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___4~0#1); {82969#false} is VALID [2022-02-21 04:23:32,956 INFO L290 TraceCheckUtils]: 83: Hoare triple {82969#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {82969#false} is VALID [2022-02-21 04:23:32,956 INFO L290 TraceCheckUtils]: 84: Hoare triple {82969#false} assume 1 == ~t6_pc~0; {82969#false} is VALID [2022-02-21 04:23:32,956 INFO L290 TraceCheckUtils]: 85: Hoare triple {82969#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {82969#false} is VALID [2022-02-21 04:23:32,956 INFO L290 TraceCheckUtils]: 86: Hoare triple {82969#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {82969#false} is VALID [2022-02-21 04:23:32,956 INFO L290 TraceCheckUtils]: 87: Hoare triple {82969#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {82969#false} is VALID [2022-02-21 04:23:32,956 INFO L290 TraceCheckUtils]: 88: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___5~0#1); {82969#false} is VALID [2022-02-21 04:23:32,956 INFO L290 TraceCheckUtils]: 89: Hoare triple {82969#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {82969#false} is VALID [2022-02-21 04:23:32,956 INFO L290 TraceCheckUtils]: 90: Hoare triple {82969#false} assume !(1 == ~t7_pc~0); {82969#false} is VALID [2022-02-21 04:23:32,957 INFO L290 TraceCheckUtils]: 91: Hoare triple {82969#false} is_transmit7_triggered_~__retres1~7#1 := 0; {82969#false} is VALID [2022-02-21 04:23:32,957 INFO L290 TraceCheckUtils]: 92: Hoare triple {82969#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {82969#false} is VALID [2022-02-21 04:23:32,957 INFO L290 TraceCheckUtils]: 93: Hoare triple {82969#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {82969#false} is VALID [2022-02-21 04:23:32,957 INFO L290 TraceCheckUtils]: 94: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___6~0#1); {82969#false} is VALID [2022-02-21 04:23:32,957 INFO L290 TraceCheckUtils]: 95: Hoare triple {82969#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {82969#false} is VALID [2022-02-21 04:23:32,957 INFO L290 TraceCheckUtils]: 96: Hoare triple {82969#false} assume 1 == ~t8_pc~0; {82969#false} is VALID [2022-02-21 04:23:32,957 INFO L290 TraceCheckUtils]: 97: Hoare triple {82969#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {82969#false} is VALID [2022-02-21 04:23:32,958 INFO L290 TraceCheckUtils]: 98: Hoare triple {82969#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {82969#false} is VALID [2022-02-21 04:23:32,958 INFO L290 TraceCheckUtils]: 99: Hoare triple {82969#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {82969#false} is VALID [2022-02-21 04:23:32,958 INFO L290 TraceCheckUtils]: 100: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___7~0#1); {82969#false} is VALID [2022-02-21 04:23:32,958 INFO L290 TraceCheckUtils]: 101: Hoare triple {82969#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {82969#false} is VALID [2022-02-21 04:23:32,958 INFO L290 TraceCheckUtils]: 102: Hoare triple {82969#false} assume 1 == ~t9_pc~0; {82969#false} is VALID [2022-02-21 04:23:32,958 INFO L290 TraceCheckUtils]: 103: Hoare triple {82969#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {82969#false} is VALID [2022-02-21 04:23:32,958 INFO L290 TraceCheckUtils]: 104: Hoare triple {82969#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {82969#false} is VALID [2022-02-21 04:23:32,958 INFO L290 TraceCheckUtils]: 105: Hoare triple {82969#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {82969#false} is VALID [2022-02-21 04:23:32,959 INFO L290 TraceCheckUtils]: 106: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___8~0#1); {82969#false} is VALID [2022-02-21 04:23:32,959 INFO L290 TraceCheckUtils]: 107: Hoare triple {82969#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {82969#false} is VALID [2022-02-21 04:23:32,959 INFO L290 TraceCheckUtils]: 108: Hoare triple {82969#false} assume !(1 == ~t10_pc~0); {82969#false} is VALID [2022-02-21 04:23:32,959 INFO L290 TraceCheckUtils]: 109: Hoare triple {82969#false} is_transmit10_triggered_~__retres1~10#1 := 0; {82969#false} is VALID [2022-02-21 04:23:32,959 INFO L290 TraceCheckUtils]: 110: Hoare triple {82969#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {82969#false} is VALID [2022-02-21 04:23:32,959 INFO L290 TraceCheckUtils]: 111: Hoare triple {82969#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {82969#false} is VALID [2022-02-21 04:23:32,959 INFO L290 TraceCheckUtils]: 112: Hoare triple {82969#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {82969#false} is VALID [2022-02-21 04:23:32,959 INFO L290 TraceCheckUtils]: 113: Hoare triple {82969#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {82969#false} is VALID [2022-02-21 04:23:32,960 INFO L290 TraceCheckUtils]: 114: Hoare triple {82969#false} assume 1 == ~t11_pc~0; {82969#false} is VALID [2022-02-21 04:23:32,960 INFO L290 TraceCheckUtils]: 115: Hoare triple {82969#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {82969#false} is VALID [2022-02-21 04:23:32,960 INFO L290 TraceCheckUtils]: 116: Hoare triple {82969#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {82969#false} is VALID [2022-02-21 04:23:32,960 INFO L290 TraceCheckUtils]: 117: Hoare triple {82969#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {82969#false} is VALID [2022-02-21 04:23:32,960 INFO L290 TraceCheckUtils]: 118: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___10~0#1); {82969#false} is VALID [2022-02-21 04:23:32,960 INFO L290 TraceCheckUtils]: 119: Hoare triple {82969#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {82969#false} is VALID [2022-02-21 04:23:32,960 INFO L290 TraceCheckUtils]: 120: Hoare triple {82969#false} assume !(1 == ~t12_pc~0); {82969#false} is VALID [2022-02-21 04:23:32,961 INFO L290 TraceCheckUtils]: 121: Hoare triple {82969#false} is_transmit12_triggered_~__retres1~12#1 := 0; {82969#false} is VALID [2022-02-21 04:23:32,961 INFO L290 TraceCheckUtils]: 122: Hoare triple {82969#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {82969#false} is VALID [2022-02-21 04:23:32,961 INFO L290 TraceCheckUtils]: 123: Hoare triple {82969#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {82969#false} is VALID [2022-02-21 04:23:32,961 INFO L290 TraceCheckUtils]: 124: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___11~0#1); {82969#false} is VALID [2022-02-21 04:23:32,961 INFO L290 TraceCheckUtils]: 125: Hoare triple {82969#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {82969#false} is VALID [2022-02-21 04:23:32,961 INFO L290 TraceCheckUtils]: 126: Hoare triple {82969#false} assume 1 == ~t13_pc~0; {82969#false} is VALID [2022-02-21 04:23:32,961 INFO L290 TraceCheckUtils]: 127: Hoare triple {82969#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {82969#false} is VALID [2022-02-21 04:23:32,961 INFO L290 TraceCheckUtils]: 128: Hoare triple {82969#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {82969#false} is VALID [2022-02-21 04:23:32,962 INFO L290 TraceCheckUtils]: 129: Hoare triple {82969#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {82969#false} is VALID [2022-02-21 04:23:32,962 INFO L290 TraceCheckUtils]: 130: Hoare triple {82969#false} assume !(0 != activate_threads_~tmp___12~0#1); {82969#false} is VALID [2022-02-21 04:23:32,962 INFO L290 TraceCheckUtils]: 131: Hoare triple {82969#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {82969#false} is VALID [2022-02-21 04:23:32,962 INFO L290 TraceCheckUtils]: 132: Hoare triple {82969#false} assume !(1 == ~M_E~0); {82969#false} is VALID [2022-02-21 04:23:32,962 INFO L290 TraceCheckUtils]: 133: Hoare triple {82969#false} assume !(1 == ~T1_E~0); {82969#false} is VALID [2022-02-21 04:23:32,962 INFO L290 TraceCheckUtils]: 134: Hoare triple {82969#false} assume !(1 == ~T2_E~0); {82969#false} is VALID [2022-02-21 04:23:32,962 INFO L290 TraceCheckUtils]: 135: Hoare triple {82969#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {82969#false} is VALID [2022-02-21 04:23:32,962 INFO L290 TraceCheckUtils]: 136: Hoare triple {82969#false} assume !(1 == ~T4_E~0); {82969#false} is VALID [2022-02-21 04:23:32,963 INFO L290 TraceCheckUtils]: 137: Hoare triple {82969#false} assume !(1 == ~T5_E~0); {82969#false} is VALID [2022-02-21 04:23:32,963 INFO L290 TraceCheckUtils]: 138: Hoare triple {82969#false} assume !(1 == ~T6_E~0); {82969#false} is VALID [2022-02-21 04:23:32,963 INFO L290 TraceCheckUtils]: 139: Hoare triple {82969#false} assume !(1 == ~T7_E~0); {82969#false} is VALID [2022-02-21 04:23:32,963 INFO L290 TraceCheckUtils]: 140: Hoare triple {82969#false} assume !(1 == ~T8_E~0); {82969#false} is VALID [2022-02-21 04:23:32,963 INFO L290 TraceCheckUtils]: 141: Hoare triple {82969#false} assume !(1 == ~T9_E~0); {82969#false} is VALID [2022-02-21 04:23:32,963 INFO L290 TraceCheckUtils]: 142: Hoare triple {82969#false} assume !(1 == ~T10_E~0); {82969#false} is VALID [2022-02-21 04:23:32,963 INFO L290 TraceCheckUtils]: 143: Hoare triple {82969#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {82969#false} is VALID [2022-02-21 04:23:32,963 INFO L290 TraceCheckUtils]: 144: Hoare triple {82969#false} assume !(1 == ~T12_E~0); {82969#false} is VALID [2022-02-21 04:23:32,964 INFO L290 TraceCheckUtils]: 145: Hoare triple {82969#false} assume !(1 == ~T13_E~0); {82969#false} is VALID [2022-02-21 04:23:32,964 INFO L290 TraceCheckUtils]: 146: Hoare triple {82969#false} assume !(1 == ~E_M~0); {82969#false} is VALID [2022-02-21 04:23:32,964 INFO L290 TraceCheckUtils]: 147: Hoare triple {82969#false} assume !(1 == ~E_1~0); {82969#false} is VALID [2022-02-21 04:23:32,964 INFO L290 TraceCheckUtils]: 148: Hoare triple {82969#false} assume !(1 == ~E_2~0); {82969#false} is VALID [2022-02-21 04:23:32,964 INFO L290 TraceCheckUtils]: 149: Hoare triple {82969#false} assume !(1 == ~E_3~0); {82969#false} is VALID [2022-02-21 04:23:32,964 INFO L290 TraceCheckUtils]: 150: Hoare triple {82969#false} assume !(1 == ~E_4~0); {82969#false} is VALID [2022-02-21 04:23:32,964 INFO L290 TraceCheckUtils]: 151: Hoare triple {82969#false} assume 1 == ~E_5~0;~E_5~0 := 2; {82969#false} is VALID [2022-02-21 04:23:32,965 INFO L290 TraceCheckUtils]: 152: Hoare triple {82969#false} assume !(1 == ~E_6~0); {82969#false} is VALID [2022-02-21 04:23:32,965 INFO L290 TraceCheckUtils]: 153: Hoare triple {82969#false} assume !(1 == ~E_7~0); {82969#false} is VALID [2022-02-21 04:23:32,965 INFO L290 TraceCheckUtils]: 154: Hoare triple {82969#false} assume !(1 == ~E_8~0); {82969#false} is VALID [2022-02-21 04:23:32,965 INFO L290 TraceCheckUtils]: 155: Hoare triple {82969#false} assume !(1 == ~E_9~0); {82969#false} is VALID [2022-02-21 04:23:32,965 INFO L290 TraceCheckUtils]: 156: Hoare triple {82969#false} assume !(1 == ~E_10~0); {82969#false} is VALID [2022-02-21 04:23:32,965 INFO L290 TraceCheckUtils]: 157: Hoare triple {82969#false} assume !(1 == ~E_11~0); {82969#false} is VALID [2022-02-21 04:23:32,965 INFO L290 TraceCheckUtils]: 158: Hoare triple {82969#false} assume !(1 == ~E_12~0); {82969#false} is VALID [2022-02-21 04:23:32,965 INFO L290 TraceCheckUtils]: 159: Hoare triple {82969#false} assume 1 == ~E_13~0;~E_13~0 := 2; {82969#false} is VALID [2022-02-21 04:23:32,966 INFO L290 TraceCheckUtils]: 160: Hoare triple {82969#false} assume { :end_inline_reset_delta_events } true; {82969#false} is VALID [2022-02-21 04:23:32,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:32,966 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:32,966 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542769464] [2022-02-21 04:23:32,966 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542769464] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:32,966 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:32,967 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:32,967 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103915794] [2022-02-21 04:23:32,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:32,967 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:32,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:32,968 INFO L85 PathProgramCache]: Analyzing trace with hash 1544379365, now seen corresponding path program 1 times [2022-02-21 04:23:32,968 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:32,968 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331451711] [2022-02-21 04:23:32,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:32,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:32,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:33,003 INFO L290 TraceCheckUtils]: 0: Hoare triple {82971#true} assume !false; {82971#true} is VALID [2022-02-21 04:23:33,003 INFO L290 TraceCheckUtils]: 1: Hoare triple {82971#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {82971#true} is VALID [2022-02-21 04:23:33,004 INFO L290 TraceCheckUtils]: 2: Hoare triple {82971#true} assume !false; {82971#true} is VALID [2022-02-21 04:23:33,004 INFO L290 TraceCheckUtils]: 3: Hoare triple {82971#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {82971#true} is VALID [2022-02-21 04:23:33,004 INFO L290 TraceCheckUtils]: 4: Hoare triple {82971#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {82971#true} is VALID [2022-02-21 04:23:33,004 INFO L290 TraceCheckUtils]: 5: Hoare triple {82971#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {82971#true} is VALID [2022-02-21 04:23:33,004 INFO L290 TraceCheckUtils]: 6: Hoare triple {82971#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {82971#true} is VALID [2022-02-21 04:23:33,004 INFO L290 TraceCheckUtils]: 7: Hoare triple {82971#true} assume !(0 != eval_~tmp~0#1); {82971#true} is VALID [2022-02-21 04:23:33,004 INFO L290 TraceCheckUtils]: 8: Hoare triple {82971#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {82971#true} is VALID [2022-02-21 04:23:33,005 INFO L290 TraceCheckUtils]: 9: Hoare triple {82971#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {82971#true} is VALID [2022-02-21 04:23:33,005 INFO L290 TraceCheckUtils]: 10: Hoare triple {82971#true} assume 0 == ~M_E~0;~M_E~0 := 1; {82971#true} is VALID [2022-02-21 04:23:33,005 INFO L290 TraceCheckUtils]: 11: Hoare triple {82971#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {82971#true} is VALID [2022-02-21 04:23:33,005 INFO L290 TraceCheckUtils]: 12: Hoare triple {82971#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {82971#true} is VALID [2022-02-21 04:23:33,005 INFO L290 TraceCheckUtils]: 13: Hoare triple {82971#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {82971#true} is VALID [2022-02-21 04:23:33,005 INFO L290 TraceCheckUtils]: 14: Hoare triple {82971#true} assume !(0 == ~T4_E~0); {82971#true} is VALID [2022-02-21 04:23:33,005 INFO L290 TraceCheckUtils]: 15: Hoare triple {82971#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {82971#true} is VALID [2022-02-21 04:23:33,005 INFO L290 TraceCheckUtils]: 16: Hoare triple {82971#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {82971#true} is VALID [2022-02-21 04:23:33,006 INFO L290 TraceCheckUtils]: 17: Hoare triple {82971#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,006 INFO L290 TraceCheckUtils]: 18: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,006 INFO L290 TraceCheckUtils]: 19: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,007 INFO L290 TraceCheckUtils]: 20: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,007 INFO L290 TraceCheckUtils]: 21: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,007 INFO L290 TraceCheckUtils]: 22: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,007 INFO L290 TraceCheckUtils]: 23: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,008 INFO L290 TraceCheckUtils]: 24: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,008 INFO L290 TraceCheckUtils]: 25: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,008 INFO L290 TraceCheckUtils]: 26: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,009 INFO L290 TraceCheckUtils]: 27: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,009 INFO L290 TraceCheckUtils]: 28: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,009 INFO L290 TraceCheckUtils]: 29: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,009 INFO L290 TraceCheckUtils]: 30: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,010 INFO L290 TraceCheckUtils]: 31: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,010 INFO L290 TraceCheckUtils]: 32: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,010 INFO L290 TraceCheckUtils]: 33: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,010 INFO L290 TraceCheckUtils]: 34: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,011 INFO L290 TraceCheckUtils]: 35: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,011 INFO L290 TraceCheckUtils]: 36: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,011 INFO L290 TraceCheckUtils]: 37: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,011 INFO L290 TraceCheckUtils]: 38: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,012 INFO L290 TraceCheckUtils]: 39: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~m_pc~0); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,012 INFO L290 TraceCheckUtils]: 40: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,012 INFO L290 TraceCheckUtils]: 41: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,013 INFO L290 TraceCheckUtils]: 42: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,013 INFO L290 TraceCheckUtils]: 43: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,013 INFO L290 TraceCheckUtils]: 44: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,013 INFO L290 TraceCheckUtils]: 45: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,014 INFO L290 TraceCheckUtils]: 46: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,014 INFO L290 TraceCheckUtils]: 47: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,014 INFO L290 TraceCheckUtils]: 48: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,014 INFO L290 TraceCheckUtils]: 49: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,015 INFO L290 TraceCheckUtils]: 50: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,015 INFO L290 TraceCheckUtils]: 51: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t2_pc~0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,015 INFO L290 TraceCheckUtils]: 52: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,016 INFO L290 TraceCheckUtils]: 53: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,016 INFO L290 TraceCheckUtils]: 54: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,016 INFO L290 TraceCheckUtils]: 55: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,016 INFO L290 TraceCheckUtils]: 56: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,017 INFO L290 TraceCheckUtils]: 57: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,017 INFO L290 TraceCheckUtils]: 58: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,017 INFO L290 TraceCheckUtils]: 59: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,017 INFO L290 TraceCheckUtils]: 60: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,018 INFO L290 TraceCheckUtils]: 61: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,018 INFO L290 TraceCheckUtils]: 62: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,018 INFO L290 TraceCheckUtils]: 63: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,018 INFO L290 TraceCheckUtils]: 64: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,019 INFO L290 TraceCheckUtils]: 65: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,019 INFO L290 TraceCheckUtils]: 66: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,019 INFO L290 TraceCheckUtils]: 67: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,020 INFO L290 TraceCheckUtils]: 68: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,020 INFO L290 TraceCheckUtils]: 69: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,020 INFO L290 TraceCheckUtils]: 70: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,020 INFO L290 TraceCheckUtils]: 71: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,021 INFO L290 TraceCheckUtils]: 72: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,021 INFO L290 TraceCheckUtils]: 73: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,021 INFO L290 TraceCheckUtils]: 74: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,021 INFO L290 TraceCheckUtils]: 75: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,022 INFO L290 TraceCheckUtils]: 76: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,022 INFO L290 TraceCheckUtils]: 77: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,022 INFO L290 TraceCheckUtils]: 78: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,023 INFO L290 TraceCheckUtils]: 79: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,023 INFO L290 TraceCheckUtils]: 80: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,023 INFO L290 TraceCheckUtils]: 81: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,023 INFO L290 TraceCheckUtils]: 82: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,024 INFO L290 TraceCheckUtils]: 83: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,024 INFO L290 TraceCheckUtils]: 84: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,024 INFO L290 TraceCheckUtils]: 85: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,024 INFO L290 TraceCheckUtils]: 86: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,025 INFO L290 TraceCheckUtils]: 87: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t8_pc~0); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,025 INFO L290 TraceCheckUtils]: 88: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,025 INFO L290 TraceCheckUtils]: 89: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,026 INFO L290 TraceCheckUtils]: 90: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,026 INFO L290 TraceCheckUtils]: 91: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,026 INFO L290 TraceCheckUtils]: 92: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,026 INFO L290 TraceCheckUtils]: 93: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,027 INFO L290 TraceCheckUtils]: 94: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,027 INFO L290 TraceCheckUtils]: 95: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,027 INFO L290 TraceCheckUtils]: 96: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,027 INFO L290 TraceCheckUtils]: 97: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,028 INFO L290 TraceCheckUtils]: 98: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,028 INFO L290 TraceCheckUtils]: 99: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t10_pc~0); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,028 INFO L290 TraceCheckUtils]: 100: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,029 INFO L290 TraceCheckUtils]: 101: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,029 INFO L290 TraceCheckUtils]: 102: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,029 INFO L290 TraceCheckUtils]: 103: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,029 INFO L290 TraceCheckUtils]: 104: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,030 INFO L290 TraceCheckUtils]: 105: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t11_pc~0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,030 INFO L290 TraceCheckUtils]: 106: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,030 INFO L290 TraceCheckUtils]: 107: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,030 INFO L290 TraceCheckUtils]: 108: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,031 INFO L290 TraceCheckUtils]: 109: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,031 INFO L290 TraceCheckUtils]: 110: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,031 INFO L290 TraceCheckUtils]: 111: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t12_pc~0); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,032 INFO L290 TraceCheckUtils]: 112: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,032 INFO L290 TraceCheckUtils]: 113: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,032 INFO L290 TraceCheckUtils]: 114: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,032 INFO L290 TraceCheckUtils]: 115: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,033 INFO L290 TraceCheckUtils]: 116: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,033 INFO L290 TraceCheckUtils]: 117: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t13_pc~0); {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,033 INFO L290 TraceCheckUtils]: 118: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,033 INFO L290 TraceCheckUtils]: 119: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,034 INFO L290 TraceCheckUtils]: 120: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,034 INFO L290 TraceCheckUtils]: 121: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,034 INFO L290 TraceCheckUtils]: 122: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,034 INFO L290 TraceCheckUtils]: 123: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,035 INFO L290 TraceCheckUtils]: 124: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,035 INFO L290 TraceCheckUtils]: 125: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,035 INFO L290 TraceCheckUtils]: 126: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,036 INFO L290 TraceCheckUtils]: 127: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,036 INFO L290 TraceCheckUtils]: 128: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,036 INFO L290 TraceCheckUtils]: 129: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {82973#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:33,036 INFO L290 TraceCheckUtils]: 130: Hoare triple {82973#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {82972#false} is VALID [2022-02-21 04:23:33,037 INFO L290 TraceCheckUtils]: 131: Hoare triple {82972#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,037 INFO L290 TraceCheckUtils]: 132: Hoare triple {82972#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,037 INFO L290 TraceCheckUtils]: 133: Hoare triple {82972#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,037 INFO L290 TraceCheckUtils]: 134: Hoare triple {82972#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,037 INFO L290 TraceCheckUtils]: 135: Hoare triple {82972#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,037 INFO L290 TraceCheckUtils]: 136: Hoare triple {82972#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,037 INFO L290 TraceCheckUtils]: 137: Hoare triple {82972#false} assume 1 == ~E_M~0;~E_M~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,037 INFO L290 TraceCheckUtils]: 138: Hoare triple {82972#false} assume !(1 == ~E_1~0); {82972#false} is VALID [2022-02-21 04:23:33,038 INFO L290 TraceCheckUtils]: 139: Hoare triple {82972#false} assume 1 == ~E_2~0;~E_2~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,038 INFO L290 TraceCheckUtils]: 140: Hoare triple {82972#false} assume 1 == ~E_3~0;~E_3~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,038 INFO L290 TraceCheckUtils]: 141: Hoare triple {82972#false} assume 1 == ~E_4~0;~E_4~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,038 INFO L290 TraceCheckUtils]: 142: Hoare triple {82972#false} assume 1 == ~E_5~0;~E_5~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,038 INFO L290 TraceCheckUtils]: 143: Hoare triple {82972#false} assume 1 == ~E_6~0;~E_6~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,038 INFO L290 TraceCheckUtils]: 144: Hoare triple {82972#false} assume 1 == ~E_7~0;~E_7~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,038 INFO L290 TraceCheckUtils]: 145: Hoare triple {82972#false} assume 1 == ~E_8~0;~E_8~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,038 INFO L290 TraceCheckUtils]: 146: Hoare triple {82972#false} assume !(1 == ~E_9~0); {82972#false} is VALID [2022-02-21 04:23:33,039 INFO L290 TraceCheckUtils]: 147: Hoare triple {82972#false} assume 1 == ~E_10~0;~E_10~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,039 INFO L290 TraceCheckUtils]: 148: Hoare triple {82972#false} assume 1 == ~E_11~0;~E_11~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,039 INFO L290 TraceCheckUtils]: 149: Hoare triple {82972#false} assume 1 == ~E_12~0;~E_12~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,039 INFO L290 TraceCheckUtils]: 150: Hoare triple {82972#false} assume 1 == ~E_13~0;~E_13~0 := 2; {82972#false} is VALID [2022-02-21 04:23:33,039 INFO L290 TraceCheckUtils]: 151: Hoare triple {82972#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {82972#false} is VALID [2022-02-21 04:23:33,039 INFO L290 TraceCheckUtils]: 152: Hoare triple {82972#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {82972#false} is VALID [2022-02-21 04:23:33,039 INFO L290 TraceCheckUtils]: 153: Hoare triple {82972#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {82972#false} is VALID [2022-02-21 04:23:33,040 INFO L290 TraceCheckUtils]: 154: Hoare triple {82972#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {82972#false} is VALID [2022-02-21 04:23:33,040 INFO L290 TraceCheckUtils]: 155: Hoare triple {82972#false} assume !(0 == start_simulation_~tmp~3#1); {82972#false} is VALID [2022-02-21 04:23:33,040 INFO L290 TraceCheckUtils]: 156: Hoare triple {82972#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {82972#false} is VALID [2022-02-21 04:23:33,040 INFO L290 TraceCheckUtils]: 157: Hoare triple {82972#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {82972#false} is VALID [2022-02-21 04:23:33,040 INFO L290 TraceCheckUtils]: 158: Hoare triple {82972#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {82972#false} is VALID [2022-02-21 04:23:33,040 INFO L290 TraceCheckUtils]: 159: Hoare triple {82972#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {82972#false} is VALID [2022-02-21 04:23:33,040 INFO L290 TraceCheckUtils]: 160: Hoare triple {82972#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {82972#false} is VALID [2022-02-21 04:23:33,040 INFO L290 TraceCheckUtils]: 161: Hoare triple {82972#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {82972#false} is VALID [2022-02-21 04:23:33,041 INFO L290 TraceCheckUtils]: 162: Hoare triple {82972#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {82972#false} is VALID [2022-02-21 04:23:33,041 INFO L290 TraceCheckUtils]: 163: Hoare triple {82972#false} assume !(0 != start_simulation_~tmp___0~1#1); {82972#false} is VALID [2022-02-21 04:23:33,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:33,041 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:33,041 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1331451711] [2022-02-21 04:23:33,042 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1331451711] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:33,042 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:33,042 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:33,042 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [959481029] [2022-02-21 04:23:33,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:33,042 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:33,042 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:33,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:33,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:33,043 INFO L87 Difference]: Start difference. First operand 2021 states and 2983 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:34,329 INFO L93 Difference]: Finished difference Result 2021 states and 2982 transitions. [2022-02-21 04:23:34,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:34,330 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,423 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:34,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2982 transitions. [2022-02-21 04:23:34,509 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:34,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2982 transitions. [2022-02-21 04:23:34,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:34,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:34,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2982 transitions. [2022-02-21 04:23:34,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:34,596 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2022-02-21 04:23:34,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2982 transitions. [2022-02-21 04:23:34,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:34,610 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:34,612 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2982 transitions. Second operand has 2021 states, 2021 states have (on average 1.475507174666007) internal successors, (2982), 2020 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,613 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2982 transitions. Second operand has 2021 states, 2021 states have (on average 1.475507174666007) internal successors, (2982), 2020 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,614 INFO L87 Difference]: Start difference. First operand 2021 states and 2982 transitions. Second operand has 2021 states, 2021 states have (on average 1.475507174666007) internal successors, (2982), 2020 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:34,695 INFO L93 Difference]: Finished difference Result 2021 states and 2982 transitions. [2022-02-21 04:23:34,695 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2982 transitions. [2022-02-21 04:23:34,697 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:34,697 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:34,699 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.475507174666007) internal successors, (2982), 2020 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2982 transitions. [2022-02-21 04:23:34,700 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.475507174666007) internal successors, (2982), 2020 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2982 transitions. [2022-02-21 04:23:34,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:34,782 INFO L93 Difference]: Finished difference Result 2021 states and 2982 transitions. [2022-02-21 04:23:34,782 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2982 transitions. [2022-02-21 04:23:34,784 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:34,784 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:34,784 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:34,784 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:34,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.475507174666007) internal successors, (2982), 2020 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2982 transitions. [2022-02-21 04:23:34,867 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2022-02-21 04:23:34,867 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2022-02-21 04:23:34,867 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:23:34,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2982 transitions. [2022-02-21 04:23:34,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:34,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:34,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:34,871 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:34,871 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:34,872 INFO L791 eck$LassoCheckResult]: Stem: 85871#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85872#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 85603#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85604#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86994#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 86995#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85790#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85791#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85825#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86662#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86663#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86775#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86776#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85609#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 85610#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86812#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 86134#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 86135#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 86716#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86982#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 86872#L1286-2 assume !(0 == ~T1_E~0); 85518#L1291-1 assume !(0 == ~T2_E~0); 85519#L1296-1 assume !(0 == ~T3_E~0); 86224#L1301-1 assume !(0 == ~T4_E~0); 86225#L1306-1 assume !(0 == ~T5_E~0); 86725#L1311-1 assume !(0 == ~T6_E~0); 85478#L1316-1 assume !(0 == ~T7_E~0); 85479#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 86244#L1326-1 assume !(0 == ~T9_E~0); 85293#L1331-1 assume !(0 == ~T10_E~0); 84999#L1336-1 assume !(0 == ~T11_E~0); 85000#L1341-1 assume !(0 == ~T12_E~0); 85051#L1346-1 assume !(0 == ~T13_E~0); 85052#L1351-1 assume !(0 == ~E_M~0); 85425#L1356-1 assume !(0 == ~E_1~0); 85426#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 86945#L1366-1 assume !(0 == ~E_3~0); 85471#L1371-1 assume !(0 == ~E_4~0); 85472#L1376-1 assume !(0 == ~E_5~0); 86285#L1381-1 assume !(0 == ~E_6~0); 86286#L1386-1 assume !(0 == ~E_7~0); 86973#L1391-1 assume !(0 == ~E_8~0); 86986#L1396-1 assume !(0 == ~E_9~0); 86168#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 86169#L1406-1 assume !(0 == ~E_11~0); 86471#L1411-1 assume !(0 == ~E_12~0); 86472#L1416-1 assume !(0 == ~E_13~0); 86092#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85930#L635 assume !(1 == ~m_pc~0); 85069#L635-2 is_master_triggered_~__retres1~0#1 := 0; 85070#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85420#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86056#L1598 assume !(0 != activate_threads_~tmp~1#1); 85248#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85249#L654 assume 1 == ~t1_pc~0; 85954#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85955#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86970#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86036#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 86037#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85296#L673 assume 1 == ~t2_pc~0; 85297#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86441#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86442#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87000#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 87007#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86115#L692 assume !(1 == ~t3_pc~0); 85932#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85933#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85792#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85760#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85761#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85321#L711 assume 1 == ~t4_pc~0; 85322#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85805#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86262#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85024#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 85025#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86993#L730 assume !(1 == ~t5_pc~0); 86375#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 85203#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85204#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85331#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 85332#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85674#L749 assume 1 == ~t6_pc~0; 85448#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85208#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85640#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85641#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 85863#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85004#L768 assume !(1 == ~t7_pc~0); 85005#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 86309#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85241#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 85242#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 86328#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85480#L787 assume 1 == ~t8_pc~0; 85481#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86676#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86840#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86841#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 85049#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85050#L806 assume 1 == ~t9_pc~0; 86687#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85084#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85085#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85333#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 85334#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86670#L825 assume !(1 == ~t10_pc~0); 86671#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 86276#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86277#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85421#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85422#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86005#L844 assume 1 == ~t11_pc~0; 85695#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85696#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86062#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86063#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 86658#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86659#L863 assume !(1 == ~t12_pc~0); 85184#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 85183#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85411#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86750#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 86751#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86129#L882 assume 1 == ~t13_pc~0; 86130#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86414#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86915#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86718#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 86401#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86402#L1434 assume !(1 == ~M_E~0); 86923#L1434-2 assume !(1 == ~T1_E~0); 86999#L1439-1 assume !(1 == ~T2_E~0); 85314#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85315#L1449-1 assume !(1 == ~T4_E~0); 85757#L1454-1 assume !(1 == ~T5_E~0); 85758#L1459-1 assume !(1 == ~T6_E~0); 86329#L1464-1 assume !(1 == ~T7_E~0); 86330#L1469-1 assume !(1 == ~T8_E~0); 86415#L1474-1 assume !(1 == ~T9_E~0); 86093#L1479-1 assume !(1 == ~T10_E~0); 86094#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86337#L1489-1 assume !(1 == ~T12_E~0); 85971#L1494-1 assume !(1 == ~T13_E~0); 85972#L1499-1 assume !(1 == ~E_M~0); 86153#L1504-1 assume !(1 == ~E_1~0); 86154#L1509-1 assume !(1 == ~E_2~0); 86767#L1514-1 assume !(1 == ~E_3~0); 86452#L1519-1 assume !(1 == ~E_4~0); 86453#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86957#L1529-1 assume !(1 == ~E_6~0); 86958#L1534-1 assume !(1 == ~E_7~0); 85104#L1539-1 assume !(1 == ~E_8~0); 85105#L1544-1 assume !(1 == ~E_9~0); 85535#L1549-1 assume !(1 == ~E_10~0); 86935#L1554-1 assume !(1 == ~E_11~0); 86933#L1559-1 assume !(1 == ~E_12~0); 86795#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 86796#L1569-1 assume { :end_inline_reset_delta_events } true; 86951#L1935-2 [2022-02-21 04:23:34,872 INFO L793 eck$LassoCheckResult]: Loop: 86951#L1935-2 assume !false; 85113#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85114#L1261 assume !false; 86341#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86342#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85244#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85414#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 85415#L1074 assume !(0 != eval_~tmp~0#1); 85772#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86370#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86771#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 86827#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 86546#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 86547#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 86983#L1301-3 assume !(0 == ~T4_E~0); 86941#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86049#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85348#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85349#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 85454#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86190#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 86455#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 86456#L1341-3 assume !(0 == ~T12_E~0); 85750#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85741#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85685#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85686#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 86266#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85039#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 85040#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86782#L1381-3 assume !(0 == ~E_6~0); 86631#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 86632#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86813#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 86814#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 85419#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 85250#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 85251#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 85878#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85128#L635-45 assume 1 == ~m_pc~0; 85129#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 85923#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86403#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86657#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85437#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85438#L654-45 assume !(1 == ~t1_pc~0); 86259#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 86606#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85091#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85092#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 85117#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85944#L673-45 assume !(1 == ~t2_pc~0); 85945#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 86269#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86270#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86895#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 86715#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85562#L692-45 assume !(1 == ~t3_pc~0); 85288#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 85289#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86333#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85616#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85617#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85929#L711-45 assume 1 == ~t4_pc~0; 86053#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 86054#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85906#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85907#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86310#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85461#L730-45 assume 1 == ~t5_pc~0; 85299#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 85300#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85709#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85710#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 86461#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85272#L749-45 assume !(1 == ~t6_pc~0); 85273#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 86673#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86436#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86437#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86588#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85588#L768-45 assume 1 == ~t7_pc~0; 85589#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85728#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86532#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86533#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86572#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86573#L787-45 assume 1 == ~t8_pc~0; 86741#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85734#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85735#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86151#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 86152#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86460#L806-45 assume 1 == ~t9_pc~0; 86936#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85148#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85973#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85801#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85713#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85714#L825-45 assume 1 == ~t10_pc~0; 86325#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 86238#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86343#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86344#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86496#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85356#L844-45 assume !(1 == ~t11_pc~0); 85357#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 85879#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85880#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85896#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 86307#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85396#L863-45 assume 1 == ~t12_pc~0; 85397#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 84997#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84998#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85513#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 85514#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86313#L882-45 assume !(1 == ~t13_pc~0); 85843#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 85016#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85017#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 85625#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86804#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86420#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 86421#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86605#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85310#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85311#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85473#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86410#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 86411#L1464-3 assume !(1 == ~T7_E~0); 86857#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86784#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86785#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86859#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86051#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 86052#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 86712#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 86347#L1504-3 assume !(1 == ~E_1~0); 86348#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86793#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86833#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85974#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85975#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86880#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86275#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85729#L1544-3 assume !(1 == ~E_9~0); 85730#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86245#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85361#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 85362#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 86511#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86512#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85246#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85811#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 86482#L1954 assume !(0 == start_simulation_~tmp~3#1); 86484#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86734#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85529#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86570#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 86700#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86701#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86791#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 86853#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 86951#L1935-2 [2022-02-21 04:23:34,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:34,873 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2022-02-21 04:23:34,873 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:34,873 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083791887] [2022-02-21 04:23:34,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:34,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:34,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:34,891 INFO L290 TraceCheckUtils]: 0: Hoare triple {91061#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {91061#true} is VALID [2022-02-21 04:23:34,892 INFO L290 TraceCheckUtils]: 1: Hoare triple {91061#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,892 INFO L290 TraceCheckUtils]: 2: Hoare triple {91063#(= ~t12_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,893 INFO L290 TraceCheckUtils]: 3: Hoare triple {91063#(= ~t12_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,893 INFO L290 TraceCheckUtils]: 4: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,893 INFO L290 TraceCheckUtils]: 5: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,893 INFO L290 TraceCheckUtils]: 6: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,894 INFO L290 TraceCheckUtils]: 7: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,894 INFO L290 TraceCheckUtils]: 8: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,894 INFO L290 TraceCheckUtils]: 9: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,894 INFO L290 TraceCheckUtils]: 10: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,895 INFO L290 TraceCheckUtils]: 11: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,895 INFO L290 TraceCheckUtils]: 12: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,895 INFO L290 TraceCheckUtils]: 13: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,895 INFO L290 TraceCheckUtils]: 14: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,896 INFO L290 TraceCheckUtils]: 15: Hoare triple {91063#(= ~t12_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {91063#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:34,896 INFO L290 TraceCheckUtils]: 16: Hoare triple {91063#(= ~t12_i~0 1)} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {91062#false} is VALID [2022-02-21 04:23:34,896 INFO L290 TraceCheckUtils]: 17: Hoare triple {91062#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {91062#false} is VALID [2022-02-21 04:23:34,896 INFO L290 TraceCheckUtils]: 18: Hoare triple {91062#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {91062#false} is VALID [2022-02-21 04:23:34,896 INFO L290 TraceCheckUtils]: 19: Hoare triple {91062#false} assume 0 == ~M_E~0;~M_E~0 := 1; {91062#false} is VALID [2022-02-21 04:23:34,896 INFO L290 TraceCheckUtils]: 20: Hoare triple {91062#false} assume !(0 == ~T1_E~0); {91062#false} is VALID [2022-02-21 04:23:34,897 INFO L290 TraceCheckUtils]: 21: Hoare triple {91062#false} assume !(0 == ~T2_E~0); {91062#false} is VALID [2022-02-21 04:23:34,897 INFO L290 TraceCheckUtils]: 22: Hoare triple {91062#false} assume !(0 == ~T3_E~0); {91062#false} is VALID [2022-02-21 04:23:34,897 INFO L290 TraceCheckUtils]: 23: Hoare triple {91062#false} assume !(0 == ~T4_E~0); {91062#false} is VALID [2022-02-21 04:23:34,897 INFO L290 TraceCheckUtils]: 24: Hoare triple {91062#false} assume !(0 == ~T5_E~0); {91062#false} is VALID [2022-02-21 04:23:34,897 INFO L290 TraceCheckUtils]: 25: Hoare triple {91062#false} assume !(0 == ~T6_E~0); {91062#false} is VALID [2022-02-21 04:23:34,897 INFO L290 TraceCheckUtils]: 26: Hoare triple {91062#false} assume !(0 == ~T7_E~0); {91062#false} is VALID [2022-02-21 04:23:34,897 INFO L290 TraceCheckUtils]: 27: Hoare triple {91062#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {91062#false} is VALID [2022-02-21 04:23:34,898 INFO L290 TraceCheckUtils]: 28: Hoare triple {91062#false} assume !(0 == ~T9_E~0); {91062#false} is VALID [2022-02-21 04:23:34,898 INFO L290 TraceCheckUtils]: 29: Hoare triple {91062#false} assume !(0 == ~T10_E~0); {91062#false} is VALID [2022-02-21 04:23:34,898 INFO L290 TraceCheckUtils]: 30: Hoare triple {91062#false} assume !(0 == ~T11_E~0); {91062#false} is VALID [2022-02-21 04:23:34,898 INFO L290 TraceCheckUtils]: 31: Hoare triple {91062#false} assume !(0 == ~T12_E~0); {91062#false} is VALID [2022-02-21 04:23:34,898 INFO L290 TraceCheckUtils]: 32: Hoare triple {91062#false} assume !(0 == ~T13_E~0); {91062#false} is VALID [2022-02-21 04:23:34,898 INFO L290 TraceCheckUtils]: 33: Hoare triple {91062#false} assume !(0 == ~E_M~0); {91062#false} is VALID [2022-02-21 04:23:34,898 INFO L290 TraceCheckUtils]: 34: Hoare triple {91062#false} assume !(0 == ~E_1~0); {91062#false} is VALID [2022-02-21 04:23:34,898 INFO L290 TraceCheckUtils]: 35: Hoare triple {91062#false} assume 0 == ~E_2~0;~E_2~0 := 1; {91062#false} is VALID [2022-02-21 04:23:34,899 INFO L290 TraceCheckUtils]: 36: Hoare triple {91062#false} assume !(0 == ~E_3~0); {91062#false} is VALID [2022-02-21 04:23:34,899 INFO L290 TraceCheckUtils]: 37: Hoare triple {91062#false} assume !(0 == ~E_4~0); {91062#false} is VALID [2022-02-21 04:23:34,899 INFO L290 TraceCheckUtils]: 38: Hoare triple {91062#false} assume !(0 == ~E_5~0); {91062#false} is VALID [2022-02-21 04:23:34,899 INFO L290 TraceCheckUtils]: 39: Hoare triple {91062#false} assume !(0 == ~E_6~0); {91062#false} is VALID [2022-02-21 04:23:34,899 INFO L290 TraceCheckUtils]: 40: Hoare triple {91062#false} assume !(0 == ~E_7~0); {91062#false} is VALID [2022-02-21 04:23:34,899 INFO L290 TraceCheckUtils]: 41: Hoare triple {91062#false} assume !(0 == ~E_8~0); {91062#false} is VALID [2022-02-21 04:23:34,899 INFO L290 TraceCheckUtils]: 42: Hoare triple {91062#false} assume !(0 == ~E_9~0); {91062#false} is VALID [2022-02-21 04:23:34,899 INFO L290 TraceCheckUtils]: 43: Hoare triple {91062#false} assume 0 == ~E_10~0;~E_10~0 := 1; {91062#false} is VALID [2022-02-21 04:23:34,900 INFO L290 TraceCheckUtils]: 44: Hoare triple {91062#false} assume !(0 == ~E_11~0); {91062#false} is VALID [2022-02-21 04:23:34,900 INFO L290 TraceCheckUtils]: 45: Hoare triple {91062#false} assume !(0 == ~E_12~0); {91062#false} is VALID [2022-02-21 04:23:34,900 INFO L290 TraceCheckUtils]: 46: Hoare triple {91062#false} assume !(0 == ~E_13~0); {91062#false} is VALID [2022-02-21 04:23:34,900 INFO L290 TraceCheckUtils]: 47: Hoare triple {91062#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {91062#false} is VALID [2022-02-21 04:23:34,900 INFO L290 TraceCheckUtils]: 48: Hoare triple {91062#false} assume !(1 == ~m_pc~0); {91062#false} is VALID [2022-02-21 04:23:34,900 INFO L290 TraceCheckUtils]: 49: Hoare triple {91062#false} is_master_triggered_~__retres1~0#1 := 0; {91062#false} is VALID [2022-02-21 04:23:34,900 INFO L290 TraceCheckUtils]: 50: Hoare triple {91062#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {91062#false} is VALID [2022-02-21 04:23:34,900 INFO L290 TraceCheckUtils]: 51: Hoare triple {91062#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {91062#false} is VALID [2022-02-21 04:23:34,901 INFO L290 TraceCheckUtils]: 52: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp~1#1); {91062#false} is VALID [2022-02-21 04:23:34,901 INFO L290 TraceCheckUtils]: 53: Hoare triple {91062#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {91062#false} is VALID [2022-02-21 04:23:34,901 INFO L290 TraceCheckUtils]: 54: Hoare triple {91062#false} assume 1 == ~t1_pc~0; {91062#false} is VALID [2022-02-21 04:23:34,901 INFO L290 TraceCheckUtils]: 55: Hoare triple {91062#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {91062#false} is VALID [2022-02-21 04:23:34,901 INFO L290 TraceCheckUtils]: 56: Hoare triple {91062#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {91062#false} is VALID [2022-02-21 04:23:34,901 INFO L290 TraceCheckUtils]: 57: Hoare triple {91062#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {91062#false} is VALID [2022-02-21 04:23:34,901 INFO L290 TraceCheckUtils]: 58: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___0~0#1); {91062#false} is VALID [2022-02-21 04:23:34,901 INFO L290 TraceCheckUtils]: 59: Hoare triple {91062#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {91062#false} is VALID [2022-02-21 04:23:34,902 INFO L290 TraceCheckUtils]: 60: Hoare triple {91062#false} assume 1 == ~t2_pc~0; {91062#false} is VALID [2022-02-21 04:23:34,902 INFO L290 TraceCheckUtils]: 61: Hoare triple {91062#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {91062#false} is VALID [2022-02-21 04:23:34,902 INFO L290 TraceCheckUtils]: 62: Hoare triple {91062#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {91062#false} is VALID [2022-02-21 04:23:34,902 INFO L290 TraceCheckUtils]: 63: Hoare triple {91062#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {91062#false} is VALID [2022-02-21 04:23:34,902 INFO L290 TraceCheckUtils]: 64: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___1~0#1); {91062#false} is VALID [2022-02-21 04:23:34,902 INFO L290 TraceCheckUtils]: 65: Hoare triple {91062#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {91062#false} is VALID [2022-02-21 04:23:34,902 INFO L290 TraceCheckUtils]: 66: Hoare triple {91062#false} assume !(1 == ~t3_pc~0); {91062#false} is VALID [2022-02-21 04:23:34,902 INFO L290 TraceCheckUtils]: 67: Hoare triple {91062#false} is_transmit3_triggered_~__retres1~3#1 := 0; {91062#false} is VALID [2022-02-21 04:23:34,903 INFO L290 TraceCheckUtils]: 68: Hoare triple {91062#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {91062#false} is VALID [2022-02-21 04:23:34,903 INFO L290 TraceCheckUtils]: 69: Hoare triple {91062#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {91062#false} is VALID [2022-02-21 04:23:34,903 INFO L290 TraceCheckUtils]: 70: Hoare triple {91062#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {91062#false} is VALID [2022-02-21 04:23:34,903 INFO L290 TraceCheckUtils]: 71: Hoare triple {91062#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {91062#false} is VALID [2022-02-21 04:23:34,903 INFO L290 TraceCheckUtils]: 72: Hoare triple {91062#false} assume 1 == ~t4_pc~0; {91062#false} is VALID [2022-02-21 04:23:34,903 INFO L290 TraceCheckUtils]: 73: Hoare triple {91062#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {91062#false} is VALID [2022-02-21 04:23:34,903 INFO L290 TraceCheckUtils]: 74: Hoare triple {91062#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {91062#false} is VALID [2022-02-21 04:23:34,904 INFO L290 TraceCheckUtils]: 75: Hoare triple {91062#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {91062#false} is VALID [2022-02-21 04:23:34,904 INFO L290 TraceCheckUtils]: 76: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___3~0#1); {91062#false} is VALID [2022-02-21 04:23:34,904 INFO L290 TraceCheckUtils]: 77: Hoare triple {91062#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {91062#false} is VALID [2022-02-21 04:23:34,904 INFO L290 TraceCheckUtils]: 78: Hoare triple {91062#false} assume !(1 == ~t5_pc~0); {91062#false} is VALID [2022-02-21 04:23:34,904 INFO L290 TraceCheckUtils]: 79: Hoare triple {91062#false} is_transmit5_triggered_~__retres1~5#1 := 0; {91062#false} is VALID [2022-02-21 04:23:34,904 INFO L290 TraceCheckUtils]: 80: Hoare triple {91062#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {91062#false} is VALID [2022-02-21 04:23:34,904 INFO L290 TraceCheckUtils]: 81: Hoare triple {91062#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {91062#false} is VALID [2022-02-21 04:23:34,904 INFO L290 TraceCheckUtils]: 82: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___4~0#1); {91062#false} is VALID [2022-02-21 04:23:34,905 INFO L290 TraceCheckUtils]: 83: Hoare triple {91062#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {91062#false} is VALID [2022-02-21 04:23:34,905 INFO L290 TraceCheckUtils]: 84: Hoare triple {91062#false} assume 1 == ~t6_pc~0; {91062#false} is VALID [2022-02-21 04:23:34,905 INFO L290 TraceCheckUtils]: 85: Hoare triple {91062#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {91062#false} is VALID [2022-02-21 04:23:34,905 INFO L290 TraceCheckUtils]: 86: Hoare triple {91062#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {91062#false} is VALID [2022-02-21 04:23:34,905 INFO L290 TraceCheckUtils]: 87: Hoare triple {91062#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {91062#false} is VALID [2022-02-21 04:23:34,905 INFO L290 TraceCheckUtils]: 88: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___5~0#1); {91062#false} is VALID [2022-02-21 04:23:34,905 INFO L290 TraceCheckUtils]: 89: Hoare triple {91062#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {91062#false} is VALID [2022-02-21 04:23:34,905 INFO L290 TraceCheckUtils]: 90: Hoare triple {91062#false} assume !(1 == ~t7_pc~0); {91062#false} is VALID [2022-02-21 04:23:34,906 INFO L290 TraceCheckUtils]: 91: Hoare triple {91062#false} is_transmit7_triggered_~__retres1~7#1 := 0; {91062#false} is VALID [2022-02-21 04:23:34,906 INFO L290 TraceCheckUtils]: 92: Hoare triple {91062#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {91062#false} is VALID [2022-02-21 04:23:34,906 INFO L290 TraceCheckUtils]: 93: Hoare triple {91062#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {91062#false} is VALID [2022-02-21 04:23:34,906 INFO L290 TraceCheckUtils]: 94: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___6~0#1); {91062#false} is VALID [2022-02-21 04:23:34,906 INFO L290 TraceCheckUtils]: 95: Hoare triple {91062#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {91062#false} is VALID [2022-02-21 04:23:34,906 INFO L290 TraceCheckUtils]: 96: Hoare triple {91062#false} assume 1 == ~t8_pc~0; {91062#false} is VALID [2022-02-21 04:23:34,906 INFO L290 TraceCheckUtils]: 97: Hoare triple {91062#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {91062#false} is VALID [2022-02-21 04:23:34,906 INFO L290 TraceCheckUtils]: 98: Hoare triple {91062#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {91062#false} is VALID [2022-02-21 04:23:34,907 INFO L290 TraceCheckUtils]: 99: Hoare triple {91062#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {91062#false} is VALID [2022-02-21 04:23:34,907 INFO L290 TraceCheckUtils]: 100: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___7~0#1); {91062#false} is VALID [2022-02-21 04:23:34,907 INFO L290 TraceCheckUtils]: 101: Hoare triple {91062#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {91062#false} is VALID [2022-02-21 04:23:34,907 INFO L290 TraceCheckUtils]: 102: Hoare triple {91062#false} assume 1 == ~t9_pc~0; {91062#false} is VALID [2022-02-21 04:23:34,907 INFO L290 TraceCheckUtils]: 103: Hoare triple {91062#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {91062#false} is VALID [2022-02-21 04:23:34,907 INFO L290 TraceCheckUtils]: 104: Hoare triple {91062#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {91062#false} is VALID [2022-02-21 04:23:34,907 INFO L290 TraceCheckUtils]: 105: Hoare triple {91062#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {91062#false} is VALID [2022-02-21 04:23:34,907 INFO L290 TraceCheckUtils]: 106: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___8~0#1); {91062#false} is VALID [2022-02-21 04:23:34,908 INFO L290 TraceCheckUtils]: 107: Hoare triple {91062#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {91062#false} is VALID [2022-02-21 04:23:34,908 INFO L290 TraceCheckUtils]: 108: Hoare triple {91062#false} assume !(1 == ~t10_pc~0); {91062#false} is VALID [2022-02-21 04:23:34,908 INFO L290 TraceCheckUtils]: 109: Hoare triple {91062#false} is_transmit10_triggered_~__retres1~10#1 := 0; {91062#false} is VALID [2022-02-21 04:23:34,908 INFO L290 TraceCheckUtils]: 110: Hoare triple {91062#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {91062#false} is VALID [2022-02-21 04:23:34,908 INFO L290 TraceCheckUtils]: 111: Hoare triple {91062#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {91062#false} is VALID [2022-02-21 04:23:34,908 INFO L290 TraceCheckUtils]: 112: Hoare triple {91062#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {91062#false} is VALID [2022-02-21 04:23:34,908 INFO L290 TraceCheckUtils]: 113: Hoare triple {91062#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {91062#false} is VALID [2022-02-21 04:23:34,908 INFO L290 TraceCheckUtils]: 114: Hoare triple {91062#false} assume 1 == ~t11_pc~0; {91062#false} is VALID [2022-02-21 04:23:34,909 INFO L290 TraceCheckUtils]: 115: Hoare triple {91062#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {91062#false} is VALID [2022-02-21 04:23:34,909 INFO L290 TraceCheckUtils]: 116: Hoare triple {91062#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {91062#false} is VALID [2022-02-21 04:23:34,909 INFO L290 TraceCheckUtils]: 117: Hoare triple {91062#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {91062#false} is VALID [2022-02-21 04:23:34,909 INFO L290 TraceCheckUtils]: 118: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___10~0#1); {91062#false} is VALID [2022-02-21 04:23:34,909 INFO L290 TraceCheckUtils]: 119: Hoare triple {91062#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {91062#false} is VALID [2022-02-21 04:23:34,909 INFO L290 TraceCheckUtils]: 120: Hoare triple {91062#false} assume !(1 == ~t12_pc~0); {91062#false} is VALID [2022-02-21 04:23:34,909 INFO L290 TraceCheckUtils]: 121: Hoare triple {91062#false} is_transmit12_triggered_~__retres1~12#1 := 0; {91062#false} is VALID [2022-02-21 04:23:34,910 INFO L290 TraceCheckUtils]: 122: Hoare triple {91062#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {91062#false} is VALID [2022-02-21 04:23:34,910 INFO L290 TraceCheckUtils]: 123: Hoare triple {91062#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {91062#false} is VALID [2022-02-21 04:23:34,910 INFO L290 TraceCheckUtils]: 124: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___11~0#1); {91062#false} is VALID [2022-02-21 04:23:34,910 INFO L290 TraceCheckUtils]: 125: Hoare triple {91062#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {91062#false} is VALID [2022-02-21 04:23:34,910 INFO L290 TraceCheckUtils]: 126: Hoare triple {91062#false} assume 1 == ~t13_pc~0; {91062#false} is VALID [2022-02-21 04:23:34,910 INFO L290 TraceCheckUtils]: 127: Hoare triple {91062#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {91062#false} is VALID [2022-02-21 04:23:34,910 INFO L290 TraceCheckUtils]: 128: Hoare triple {91062#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {91062#false} is VALID [2022-02-21 04:23:34,910 INFO L290 TraceCheckUtils]: 129: Hoare triple {91062#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {91062#false} is VALID [2022-02-21 04:23:34,911 INFO L290 TraceCheckUtils]: 130: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___12~0#1); {91062#false} is VALID [2022-02-21 04:23:34,911 INFO L290 TraceCheckUtils]: 131: Hoare triple {91062#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {91062#false} is VALID [2022-02-21 04:23:34,911 INFO L290 TraceCheckUtils]: 132: Hoare triple {91062#false} assume !(1 == ~M_E~0); {91062#false} is VALID [2022-02-21 04:23:34,911 INFO L290 TraceCheckUtils]: 133: Hoare triple {91062#false} assume !(1 == ~T1_E~0); {91062#false} is VALID [2022-02-21 04:23:34,911 INFO L290 TraceCheckUtils]: 134: Hoare triple {91062#false} assume !(1 == ~T2_E~0); {91062#false} is VALID [2022-02-21 04:23:34,911 INFO L290 TraceCheckUtils]: 135: Hoare triple {91062#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {91062#false} is VALID [2022-02-21 04:23:34,911 INFO L290 TraceCheckUtils]: 136: Hoare triple {91062#false} assume !(1 == ~T4_E~0); {91062#false} is VALID [2022-02-21 04:23:34,911 INFO L290 TraceCheckUtils]: 137: Hoare triple {91062#false} assume !(1 == ~T5_E~0); {91062#false} is VALID [2022-02-21 04:23:34,912 INFO L290 TraceCheckUtils]: 138: Hoare triple {91062#false} assume !(1 == ~T6_E~0); {91062#false} is VALID [2022-02-21 04:23:34,912 INFO L290 TraceCheckUtils]: 139: Hoare triple {91062#false} assume !(1 == ~T7_E~0); {91062#false} is VALID [2022-02-21 04:23:34,912 INFO L290 TraceCheckUtils]: 140: Hoare triple {91062#false} assume !(1 == ~T8_E~0); {91062#false} is VALID [2022-02-21 04:23:34,912 INFO L290 TraceCheckUtils]: 141: Hoare triple {91062#false} assume !(1 == ~T9_E~0); {91062#false} is VALID [2022-02-21 04:23:34,912 INFO L290 TraceCheckUtils]: 142: Hoare triple {91062#false} assume !(1 == ~T10_E~0); {91062#false} is VALID [2022-02-21 04:23:34,912 INFO L290 TraceCheckUtils]: 143: Hoare triple {91062#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {91062#false} is VALID [2022-02-21 04:23:34,912 INFO L290 TraceCheckUtils]: 144: Hoare triple {91062#false} assume !(1 == ~T12_E~0); {91062#false} is VALID [2022-02-21 04:23:34,912 INFO L290 TraceCheckUtils]: 145: Hoare triple {91062#false} assume !(1 == ~T13_E~0); {91062#false} is VALID [2022-02-21 04:23:34,913 INFO L290 TraceCheckUtils]: 146: Hoare triple {91062#false} assume !(1 == ~E_M~0); {91062#false} is VALID [2022-02-21 04:23:34,913 INFO L290 TraceCheckUtils]: 147: Hoare triple {91062#false} assume !(1 == ~E_1~0); {91062#false} is VALID [2022-02-21 04:23:34,913 INFO L290 TraceCheckUtils]: 148: Hoare triple {91062#false} assume !(1 == ~E_2~0); {91062#false} is VALID [2022-02-21 04:23:34,913 INFO L290 TraceCheckUtils]: 149: Hoare triple {91062#false} assume !(1 == ~E_3~0); {91062#false} is VALID [2022-02-21 04:23:34,913 INFO L290 TraceCheckUtils]: 150: Hoare triple {91062#false} assume !(1 == ~E_4~0); {91062#false} is VALID [2022-02-21 04:23:34,913 INFO L290 TraceCheckUtils]: 151: Hoare triple {91062#false} assume 1 == ~E_5~0;~E_5~0 := 2; {91062#false} is VALID [2022-02-21 04:23:34,913 INFO L290 TraceCheckUtils]: 152: Hoare triple {91062#false} assume !(1 == ~E_6~0); {91062#false} is VALID [2022-02-21 04:23:34,913 INFO L290 TraceCheckUtils]: 153: Hoare triple {91062#false} assume !(1 == ~E_7~0); {91062#false} is VALID [2022-02-21 04:23:34,914 INFO L290 TraceCheckUtils]: 154: Hoare triple {91062#false} assume !(1 == ~E_8~0); {91062#false} is VALID [2022-02-21 04:23:34,914 INFO L290 TraceCheckUtils]: 155: Hoare triple {91062#false} assume !(1 == ~E_9~0); {91062#false} is VALID [2022-02-21 04:23:34,914 INFO L290 TraceCheckUtils]: 156: Hoare triple {91062#false} assume !(1 == ~E_10~0); {91062#false} is VALID [2022-02-21 04:23:34,914 INFO L290 TraceCheckUtils]: 157: Hoare triple {91062#false} assume !(1 == ~E_11~0); {91062#false} is VALID [2022-02-21 04:23:34,914 INFO L290 TraceCheckUtils]: 158: Hoare triple {91062#false} assume !(1 == ~E_12~0); {91062#false} is VALID [2022-02-21 04:23:34,914 INFO L290 TraceCheckUtils]: 159: Hoare triple {91062#false} assume 1 == ~E_13~0;~E_13~0 := 2; {91062#false} is VALID [2022-02-21 04:23:34,914 INFO L290 TraceCheckUtils]: 160: Hoare triple {91062#false} assume { :end_inline_reset_delta_events } true; {91062#false} is VALID [2022-02-21 04:23:34,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:34,915 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:34,915 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083791887] [2022-02-21 04:23:34,915 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083791887] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:34,915 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:34,915 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:34,916 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [274590171] [2022-02-21 04:23:34,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:34,916 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:34,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:34,916 INFO L85 PathProgramCache]: Analyzing trace with hash -659014812, now seen corresponding path program 1 times [2022-02-21 04:23:34,917 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:34,917 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611436916] [2022-02-21 04:23:34,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:34,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:34,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:34,939 INFO L290 TraceCheckUtils]: 0: Hoare triple {91064#true} assume !false; {91064#true} is VALID [2022-02-21 04:23:34,940 INFO L290 TraceCheckUtils]: 1: Hoare triple {91064#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {91064#true} is VALID [2022-02-21 04:23:34,940 INFO L290 TraceCheckUtils]: 2: Hoare triple {91064#true} assume !false; {91064#true} is VALID [2022-02-21 04:23:34,940 INFO L290 TraceCheckUtils]: 3: Hoare triple {91064#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {91064#true} is VALID [2022-02-21 04:23:34,940 INFO L290 TraceCheckUtils]: 4: Hoare triple {91064#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {91064#true} is VALID [2022-02-21 04:23:34,940 INFO L290 TraceCheckUtils]: 5: Hoare triple {91064#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {91064#true} is VALID [2022-02-21 04:23:34,940 INFO L290 TraceCheckUtils]: 6: Hoare triple {91064#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {91064#true} is VALID [2022-02-21 04:23:34,940 INFO L290 TraceCheckUtils]: 7: Hoare triple {91064#true} assume !(0 != eval_~tmp~0#1); {91064#true} is VALID [2022-02-21 04:23:34,941 INFO L290 TraceCheckUtils]: 8: Hoare triple {91064#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {91064#true} is VALID [2022-02-21 04:23:34,941 INFO L290 TraceCheckUtils]: 9: Hoare triple {91064#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {91064#true} is VALID [2022-02-21 04:23:34,941 INFO L290 TraceCheckUtils]: 10: Hoare triple {91064#true} assume 0 == ~M_E~0;~M_E~0 := 1; {91064#true} is VALID [2022-02-21 04:23:34,941 INFO L290 TraceCheckUtils]: 11: Hoare triple {91064#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {91064#true} is VALID [2022-02-21 04:23:34,941 INFO L290 TraceCheckUtils]: 12: Hoare triple {91064#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {91064#true} is VALID [2022-02-21 04:23:34,941 INFO L290 TraceCheckUtils]: 13: Hoare triple {91064#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {91064#true} is VALID [2022-02-21 04:23:34,941 INFO L290 TraceCheckUtils]: 14: Hoare triple {91064#true} assume !(0 == ~T4_E~0); {91064#true} is VALID [2022-02-21 04:23:34,941 INFO L290 TraceCheckUtils]: 15: Hoare triple {91064#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {91064#true} is VALID [2022-02-21 04:23:34,942 INFO L290 TraceCheckUtils]: 16: Hoare triple {91064#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {91064#true} is VALID [2022-02-21 04:23:34,942 INFO L290 TraceCheckUtils]: 17: Hoare triple {91064#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,942 INFO L290 TraceCheckUtils]: 18: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,942 INFO L290 TraceCheckUtils]: 19: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,943 INFO L290 TraceCheckUtils]: 20: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,943 INFO L290 TraceCheckUtils]: 21: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,943 INFO L290 TraceCheckUtils]: 22: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,944 INFO L290 TraceCheckUtils]: 23: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,944 INFO L290 TraceCheckUtils]: 24: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,944 INFO L290 TraceCheckUtils]: 25: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,944 INFO L290 TraceCheckUtils]: 26: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,945 INFO L290 TraceCheckUtils]: 27: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,945 INFO L290 TraceCheckUtils]: 28: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,945 INFO L290 TraceCheckUtils]: 29: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,945 INFO L290 TraceCheckUtils]: 30: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,946 INFO L290 TraceCheckUtils]: 31: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,946 INFO L290 TraceCheckUtils]: 32: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,946 INFO L290 TraceCheckUtils]: 33: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,946 INFO L290 TraceCheckUtils]: 34: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,947 INFO L290 TraceCheckUtils]: 35: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,947 INFO L290 TraceCheckUtils]: 36: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,947 INFO L290 TraceCheckUtils]: 37: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,948 INFO L290 TraceCheckUtils]: 38: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,948 INFO L290 TraceCheckUtils]: 39: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,948 INFO L290 TraceCheckUtils]: 40: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,948 INFO L290 TraceCheckUtils]: 41: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,949 INFO L290 TraceCheckUtils]: 42: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,949 INFO L290 TraceCheckUtils]: 43: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,949 INFO L290 TraceCheckUtils]: 44: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,949 INFO L290 TraceCheckUtils]: 45: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t1_pc~0); {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,950 INFO L290 TraceCheckUtils]: 46: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,950 INFO L290 TraceCheckUtils]: 47: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,950 INFO L290 TraceCheckUtils]: 48: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,950 INFO L290 TraceCheckUtils]: 49: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,951 INFO L290 TraceCheckUtils]: 50: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,951 INFO L290 TraceCheckUtils]: 51: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,951 INFO L290 TraceCheckUtils]: 52: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,952 INFO L290 TraceCheckUtils]: 53: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,952 INFO L290 TraceCheckUtils]: 54: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,952 INFO L290 TraceCheckUtils]: 55: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,952 INFO L290 TraceCheckUtils]: 56: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,953 INFO L290 TraceCheckUtils]: 57: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,953 INFO L290 TraceCheckUtils]: 58: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,953 INFO L290 TraceCheckUtils]: 59: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,953 INFO L290 TraceCheckUtils]: 60: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,954 INFO L290 TraceCheckUtils]: 61: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,954 INFO L290 TraceCheckUtils]: 62: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,954 INFO L290 TraceCheckUtils]: 63: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,954 INFO L290 TraceCheckUtils]: 64: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,955 INFO L290 TraceCheckUtils]: 65: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,955 INFO L290 TraceCheckUtils]: 66: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,955 INFO L290 TraceCheckUtils]: 67: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,956 INFO L290 TraceCheckUtils]: 68: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,956 INFO L290 TraceCheckUtils]: 69: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,956 INFO L290 TraceCheckUtils]: 70: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,956 INFO L290 TraceCheckUtils]: 71: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,957 INFO L290 TraceCheckUtils]: 72: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,957 INFO L290 TraceCheckUtils]: 73: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,957 INFO L290 TraceCheckUtils]: 74: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,957 INFO L290 TraceCheckUtils]: 75: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,958 INFO L290 TraceCheckUtils]: 76: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,958 INFO L290 TraceCheckUtils]: 77: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,958 INFO L290 TraceCheckUtils]: 78: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,958 INFO L290 TraceCheckUtils]: 79: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,959 INFO L290 TraceCheckUtils]: 80: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,959 INFO L290 TraceCheckUtils]: 81: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,959 INFO L290 TraceCheckUtils]: 82: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,960 INFO L290 TraceCheckUtils]: 83: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,960 INFO L290 TraceCheckUtils]: 84: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,960 INFO L290 TraceCheckUtils]: 85: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,960 INFO L290 TraceCheckUtils]: 86: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,961 INFO L290 TraceCheckUtils]: 87: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t8_pc~0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,961 INFO L290 TraceCheckUtils]: 88: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,961 INFO L290 TraceCheckUtils]: 89: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,961 INFO L290 TraceCheckUtils]: 90: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,962 INFO L290 TraceCheckUtils]: 91: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,962 INFO L290 TraceCheckUtils]: 92: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,962 INFO L290 TraceCheckUtils]: 93: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,962 INFO L290 TraceCheckUtils]: 94: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,963 INFO L290 TraceCheckUtils]: 95: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,963 INFO L290 TraceCheckUtils]: 96: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,963 INFO L290 TraceCheckUtils]: 97: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,964 INFO L290 TraceCheckUtils]: 98: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,964 INFO L290 TraceCheckUtils]: 99: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t10_pc~0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,964 INFO L290 TraceCheckUtils]: 100: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,964 INFO L290 TraceCheckUtils]: 101: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,965 INFO L290 TraceCheckUtils]: 102: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,965 INFO L290 TraceCheckUtils]: 103: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,965 INFO L290 TraceCheckUtils]: 104: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,965 INFO L290 TraceCheckUtils]: 105: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,966 INFO L290 TraceCheckUtils]: 106: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,966 INFO L290 TraceCheckUtils]: 107: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,966 INFO L290 TraceCheckUtils]: 108: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,966 INFO L290 TraceCheckUtils]: 109: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,967 INFO L290 TraceCheckUtils]: 110: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,967 INFO L290 TraceCheckUtils]: 111: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,967 INFO L290 TraceCheckUtils]: 112: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,968 INFO L290 TraceCheckUtils]: 113: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,968 INFO L290 TraceCheckUtils]: 114: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,968 INFO L290 TraceCheckUtils]: 115: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,968 INFO L290 TraceCheckUtils]: 116: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,969 INFO L290 TraceCheckUtils]: 117: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t13_pc~0); {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,969 INFO L290 TraceCheckUtils]: 118: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,969 INFO L290 TraceCheckUtils]: 119: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,969 INFO L290 TraceCheckUtils]: 120: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,970 INFO L290 TraceCheckUtils]: 121: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,970 INFO L290 TraceCheckUtils]: 122: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,970 INFO L290 TraceCheckUtils]: 123: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,970 INFO L290 TraceCheckUtils]: 124: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,971 INFO L290 TraceCheckUtils]: 125: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,971 INFO L290 TraceCheckUtils]: 126: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,971 INFO L290 TraceCheckUtils]: 127: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,972 INFO L290 TraceCheckUtils]: 128: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,972 INFO L290 TraceCheckUtils]: 129: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {91066#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:34,972 INFO L290 TraceCheckUtils]: 130: Hoare triple {91066#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {91065#false} is VALID [2022-02-21 04:23:34,972 INFO L290 TraceCheckUtils]: 131: Hoare triple {91065#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,972 INFO L290 TraceCheckUtils]: 132: Hoare triple {91065#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,972 INFO L290 TraceCheckUtils]: 133: Hoare triple {91065#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,973 INFO L290 TraceCheckUtils]: 134: Hoare triple {91065#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,973 INFO L290 TraceCheckUtils]: 135: Hoare triple {91065#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,973 INFO L290 TraceCheckUtils]: 136: Hoare triple {91065#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,973 INFO L290 TraceCheckUtils]: 137: Hoare triple {91065#false} assume 1 == ~E_M~0;~E_M~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,973 INFO L290 TraceCheckUtils]: 138: Hoare triple {91065#false} assume !(1 == ~E_1~0); {91065#false} is VALID [2022-02-21 04:23:34,973 INFO L290 TraceCheckUtils]: 139: Hoare triple {91065#false} assume 1 == ~E_2~0;~E_2~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,973 INFO L290 TraceCheckUtils]: 140: Hoare triple {91065#false} assume 1 == ~E_3~0;~E_3~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,973 INFO L290 TraceCheckUtils]: 141: Hoare triple {91065#false} assume 1 == ~E_4~0;~E_4~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,974 INFO L290 TraceCheckUtils]: 142: Hoare triple {91065#false} assume 1 == ~E_5~0;~E_5~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,974 INFO L290 TraceCheckUtils]: 143: Hoare triple {91065#false} assume 1 == ~E_6~0;~E_6~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,974 INFO L290 TraceCheckUtils]: 144: Hoare triple {91065#false} assume 1 == ~E_7~0;~E_7~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,974 INFO L290 TraceCheckUtils]: 145: Hoare triple {91065#false} assume 1 == ~E_8~0;~E_8~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,974 INFO L290 TraceCheckUtils]: 146: Hoare triple {91065#false} assume !(1 == ~E_9~0); {91065#false} is VALID [2022-02-21 04:23:34,974 INFO L290 TraceCheckUtils]: 147: Hoare triple {91065#false} assume 1 == ~E_10~0;~E_10~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,974 INFO L290 TraceCheckUtils]: 148: Hoare triple {91065#false} assume 1 == ~E_11~0;~E_11~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,975 INFO L290 TraceCheckUtils]: 149: Hoare triple {91065#false} assume 1 == ~E_12~0;~E_12~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,975 INFO L290 TraceCheckUtils]: 150: Hoare triple {91065#false} assume 1 == ~E_13~0;~E_13~0 := 2; {91065#false} is VALID [2022-02-21 04:23:34,975 INFO L290 TraceCheckUtils]: 151: Hoare triple {91065#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {91065#false} is VALID [2022-02-21 04:23:34,975 INFO L290 TraceCheckUtils]: 152: Hoare triple {91065#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {91065#false} is VALID [2022-02-21 04:23:34,975 INFO L290 TraceCheckUtils]: 153: Hoare triple {91065#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {91065#false} is VALID [2022-02-21 04:23:34,975 INFO L290 TraceCheckUtils]: 154: Hoare triple {91065#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {91065#false} is VALID [2022-02-21 04:23:34,975 INFO L290 TraceCheckUtils]: 155: Hoare triple {91065#false} assume !(0 == start_simulation_~tmp~3#1); {91065#false} is VALID [2022-02-21 04:23:34,975 INFO L290 TraceCheckUtils]: 156: Hoare triple {91065#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {91065#false} is VALID [2022-02-21 04:23:34,976 INFO L290 TraceCheckUtils]: 157: Hoare triple {91065#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {91065#false} is VALID [2022-02-21 04:23:34,976 INFO L290 TraceCheckUtils]: 158: Hoare triple {91065#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {91065#false} is VALID [2022-02-21 04:23:34,976 INFO L290 TraceCheckUtils]: 159: Hoare triple {91065#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {91065#false} is VALID [2022-02-21 04:23:34,976 INFO L290 TraceCheckUtils]: 160: Hoare triple {91065#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {91065#false} is VALID [2022-02-21 04:23:34,976 INFO L290 TraceCheckUtils]: 161: Hoare triple {91065#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {91065#false} is VALID [2022-02-21 04:23:34,976 INFO L290 TraceCheckUtils]: 162: Hoare triple {91065#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {91065#false} is VALID [2022-02-21 04:23:34,976 INFO L290 TraceCheckUtils]: 163: Hoare triple {91065#false} assume !(0 != start_simulation_~tmp___0~1#1); {91065#false} is VALID [2022-02-21 04:23:34,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:34,977 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:34,977 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611436916] [2022-02-21 04:23:34,977 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [611436916] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:34,977 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:34,977 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:34,978 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588570909] [2022-02-21 04:23:34,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:34,978 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:34,978 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:34,978 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:34,979 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:34,979 INFO L87 Difference]: Start difference. First operand 2021 states and 2982 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:36,309 INFO L93 Difference]: Finished difference Result 2021 states and 2981 transitions. [2022-02-21 04:23:36,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:36,309 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,454 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:36,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2981 transitions. [2022-02-21 04:23:36,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:36,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2981 transitions. [2022-02-21 04:23:36,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:36,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:36,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2981 transitions. [2022-02-21 04:23:36,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:36,643 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2022-02-21 04:23:36,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2981 transitions. [2022-02-21 04:23:36,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:36,657 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:36,659 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2981 transitions. Second operand has 2021 states, 2021 states have (on average 1.4750123701138051) internal successors, (2981), 2020 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,660 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2981 transitions. Second operand has 2021 states, 2021 states have (on average 1.4750123701138051) internal successors, (2981), 2020 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,661 INFO L87 Difference]: Start difference. First operand 2021 states and 2981 transitions. Second operand has 2021 states, 2021 states have (on average 1.4750123701138051) internal successors, (2981), 2020 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:36,742 INFO L93 Difference]: Finished difference Result 2021 states and 2981 transitions. [2022-02-21 04:23:36,742 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2981 transitions. [2022-02-21 04:23:36,744 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:36,744 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:36,746 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.4750123701138051) internal successors, (2981), 2020 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2981 transitions. [2022-02-21 04:23:36,747 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.4750123701138051) internal successors, (2981), 2020 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2981 transitions. [2022-02-21 04:23:36,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:36,830 INFO L93 Difference]: Finished difference Result 2021 states and 2981 transitions. [2022-02-21 04:23:36,830 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2981 transitions. [2022-02-21 04:23:36,832 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:36,832 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:36,832 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:36,832 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:36,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4750123701138051) internal successors, (2981), 2020 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:36,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2981 transitions. [2022-02-21 04:23:36,917 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2022-02-21 04:23:36,917 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2022-02-21 04:23:36,917 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:23:36,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2981 transitions. [2022-02-21 04:23:36,920 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:36,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:36,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:36,921 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:36,921 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:36,922 INFO L791 eck$LassoCheckResult]: Stem: 93964#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 93965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 93696#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 93697#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95087#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 95088#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93883#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93884#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93918#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94755#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94756#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 94868#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 94869#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 93702#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 93703#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 94905#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 94227#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 94228#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 94809#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95075#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 94965#L1286-2 assume !(0 == ~T1_E~0); 93611#L1291-1 assume !(0 == ~T2_E~0); 93612#L1296-1 assume !(0 == ~T3_E~0); 94317#L1301-1 assume !(0 == ~T4_E~0); 94318#L1306-1 assume !(0 == ~T5_E~0); 94818#L1311-1 assume !(0 == ~T6_E~0); 93571#L1316-1 assume !(0 == ~T7_E~0); 93572#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 94337#L1326-1 assume !(0 == ~T9_E~0); 93386#L1331-1 assume !(0 == ~T10_E~0); 93092#L1336-1 assume !(0 == ~T11_E~0); 93093#L1341-1 assume !(0 == ~T12_E~0); 93144#L1346-1 assume !(0 == ~T13_E~0); 93145#L1351-1 assume !(0 == ~E_M~0); 93518#L1356-1 assume !(0 == ~E_1~0); 93519#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 95038#L1366-1 assume !(0 == ~E_3~0); 93564#L1371-1 assume !(0 == ~E_4~0); 93565#L1376-1 assume !(0 == ~E_5~0); 94378#L1381-1 assume !(0 == ~E_6~0); 94379#L1386-1 assume !(0 == ~E_7~0); 95066#L1391-1 assume !(0 == ~E_8~0); 95079#L1396-1 assume !(0 == ~E_9~0); 94261#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 94262#L1406-1 assume !(0 == ~E_11~0); 94564#L1411-1 assume !(0 == ~E_12~0); 94565#L1416-1 assume !(0 == ~E_13~0); 94185#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94023#L635 assume !(1 == ~m_pc~0); 93162#L635-2 is_master_triggered_~__retres1~0#1 := 0; 93163#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93513#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94149#L1598 assume !(0 != activate_threads_~tmp~1#1); 93341#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93342#L654 assume 1 == ~t1_pc~0; 94047#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 94048#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95063#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94129#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 94130#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93389#L673 assume 1 == ~t2_pc~0; 93390#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 94534#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94535#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95093#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 95100#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94208#L692 assume !(1 == ~t3_pc~0); 94025#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94026#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93885#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 93853#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 93854#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93414#L711 assume 1 == ~t4_pc~0; 93415#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 93898#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94355#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 93117#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 93118#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95086#L730 assume !(1 == ~t5_pc~0); 94468#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 93296#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 93297#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 93424#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 93425#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 93767#L749 assume 1 == ~t6_pc~0; 93541#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 93301#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 93733#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93734#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 93956#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 93097#L768 assume !(1 == ~t7_pc~0); 93098#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 94402#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 93334#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 93335#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 94421#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 93573#L787 assume 1 == ~t8_pc~0; 93574#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 94769#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 94933#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 94934#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 93142#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 93143#L806 assume 1 == ~t9_pc~0; 94780#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 93177#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 93178#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 93426#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 93427#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 94763#L825 assume !(1 == ~t10_pc~0); 94764#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 94369#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94370#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 93514#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 93515#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 94098#L844 assume 1 == ~t11_pc~0; 93788#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 93789#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 94155#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 94156#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 94751#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 94752#L863 assume !(1 == ~t12_pc~0); 93277#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 93276#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 93504#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 94843#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 94844#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 94222#L882 assume 1 == ~t13_pc~0; 94223#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 94507#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 95008#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 94811#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 94494#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94495#L1434 assume !(1 == ~M_E~0); 95016#L1434-2 assume !(1 == ~T1_E~0); 95092#L1439-1 assume !(1 == ~T2_E~0); 93407#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93408#L1449-1 assume !(1 == ~T4_E~0); 93850#L1454-1 assume !(1 == ~T5_E~0); 93851#L1459-1 assume !(1 == ~T6_E~0); 94422#L1464-1 assume !(1 == ~T7_E~0); 94423#L1469-1 assume !(1 == ~T8_E~0); 94508#L1474-1 assume !(1 == ~T9_E~0); 94186#L1479-1 assume !(1 == ~T10_E~0); 94187#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94430#L1489-1 assume !(1 == ~T12_E~0); 94064#L1494-1 assume !(1 == ~T13_E~0); 94065#L1499-1 assume !(1 == ~E_M~0); 94246#L1504-1 assume !(1 == ~E_1~0); 94247#L1509-1 assume !(1 == ~E_2~0); 94860#L1514-1 assume !(1 == ~E_3~0); 94545#L1519-1 assume !(1 == ~E_4~0); 94546#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 95050#L1529-1 assume !(1 == ~E_6~0); 95051#L1534-1 assume !(1 == ~E_7~0); 93197#L1539-1 assume !(1 == ~E_8~0); 93198#L1544-1 assume !(1 == ~E_9~0); 93628#L1549-1 assume !(1 == ~E_10~0); 95028#L1554-1 assume !(1 == ~E_11~0); 95026#L1559-1 assume !(1 == ~E_12~0); 94888#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 94889#L1569-1 assume { :end_inline_reset_delta_events } true; 95044#L1935-2 [2022-02-21 04:23:36,922 INFO L793 eck$LassoCheckResult]: Loop: 95044#L1935-2 assume !false; 93206#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93207#L1261 assume !false; 94434#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 94435#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93337#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 93507#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 93508#L1074 assume !(0 != eval_~tmp~0#1); 93865#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94463#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94864#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 94920#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 94639#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 94640#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 95076#L1301-3 assume !(0 == ~T4_E~0); 95034#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94142#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 93441#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 93442#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 93547#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 94283#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 94548#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 94549#L1341-3 assume !(0 == ~T12_E~0); 93843#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 93834#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 93778#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 93779#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 94359#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 93132#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 93133#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 94875#L1381-3 assume !(0 == ~E_6~0); 94724#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 94725#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 94906#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 94907#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 93512#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 93343#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 93344#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 93971#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93221#L635-45 assume !(1 == ~m_pc~0); 93223#L635-47 is_master_triggered_~__retres1~0#1 := 0; 94016#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94496#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94750#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 93530#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93531#L654-45 assume !(1 == ~t1_pc~0); 94352#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 94699#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93184#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 93185#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 93210#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94037#L673-45 assume 1 == ~t2_pc~0; 94039#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 94362#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94363#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94988#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 94808#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 93655#L692-45 assume !(1 == ~t3_pc~0); 93381#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 93382#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94426#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 93709#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 93710#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94022#L711-45 assume 1 == ~t4_pc~0; 94146#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 94147#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93999#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 94000#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94403#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 93554#L730-45 assume 1 == ~t5_pc~0; 93392#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 93393#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 93802#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 93803#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 94554#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 93365#L749-45 assume 1 == ~t6_pc~0; 93367#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 94766#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94529#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94530#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 94681#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 93681#L768-45 assume !(1 == ~t7_pc~0); 93683#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 93821#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94625#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94626#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 94665#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94666#L787-45 assume !(1 == ~t8_pc~0); 94835#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 93827#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 93828#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 94244#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 94245#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94553#L806-45 assume 1 == ~t9_pc~0; 95029#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 93241#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94066#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 93894#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 93806#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 93807#L825-45 assume 1 == ~t10_pc~0; 94418#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 94331#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94436#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 94437#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 94589#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 93449#L844-45 assume 1 == ~t11_pc~0; 93451#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 93972#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 93973#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 93989#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 94400#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 93489#L863-45 assume !(1 == ~t12_pc~0); 93491#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 93090#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 93091#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 93606#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 93607#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 94406#L882-45 assume !(1 == ~t13_pc~0); 93936#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 93109#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 93110#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 93718#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 94897#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94513#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 94514#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 94698#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 93403#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93404#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 93566#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94503#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 94504#L1464-3 assume !(1 == ~T7_E~0); 94950#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 94877#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 94878#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 94952#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94144#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 94145#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 94805#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 94440#L1504-3 assume !(1 == ~E_1~0); 94441#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 94886#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94926#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 94067#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 94068#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 94973#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 94368#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 93822#L1544-3 assume !(1 == ~E_9~0); 93823#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 94338#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 93454#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 93455#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 94604#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 94605#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93339#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 93904#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 94575#L1954 assume !(0 == start_simulation_~tmp~3#1); 94577#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 94827#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93622#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 94663#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 94793#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 94794#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 94884#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 94946#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 95044#L1935-2 [2022-02-21 04:23:36,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:36,923 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2022-02-21 04:23:36,923 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:36,923 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382754918] [2022-02-21 04:23:36,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:36,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:36,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:36,942 INFO L290 TraceCheckUtils]: 0: Hoare triple {99154#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {99154#true} is VALID [2022-02-21 04:23:36,942 INFO L290 TraceCheckUtils]: 1: Hoare triple {99154#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,942 INFO L290 TraceCheckUtils]: 2: Hoare triple {99156#(= ~t13_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,943 INFO L290 TraceCheckUtils]: 3: Hoare triple {99156#(= ~t13_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,943 INFO L290 TraceCheckUtils]: 4: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,943 INFO L290 TraceCheckUtils]: 5: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,943 INFO L290 TraceCheckUtils]: 6: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,944 INFO L290 TraceCheckUtils]: 7: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,944 INFO L290 TraceCheckUtils]: 8: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,944 INFO L290 TraceCheckUtils]: 9: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,945 INFO L290 TraceCheckUtils]: 10: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,945 INFO L290 TraceCheckUtils]: 11: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,945 INFO L290 TraceCheckUtils]: 12: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,945 INFO L290 TraceCheckUtils]: 13: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,946 INFO L290 TraceCheckUtils]: 14: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,946 INFO L290 TraceCheckUtils]: 15: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,946 INFO L290 TraceCheckUtils]: 16: Hoare triple {99156#(= ~t13_i~0 1)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {99156#(= ~t13_i~0 1)} is VALID [2022-02-21 04:23:36,946 INFO L290 TraceCheckUtils]: 17: Hoare triple {99156#(= ~t13_i~0 1)} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {99155#false} is VALID [2022-02-21 04:23:36,947 INFO L290 TraceCheckUtils]: 18: Hoare triple {99155#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {99155#false} is VALID [2022-02-21 04:23:36,947 INFO L290 TraceCheckUtils]: 19: Hoare triple {99155#false} assume 0 == ~M_E~0;~M_E~0 := 1; {99155#false} is VALID [2022-02-21 04:23:36,947 INFO L290 TraceCheckUtils]: 20: Hoare triple {99155#false} assume !(0 == ~T1_E~0); {99155#false} is VALID [2022-02-21 04:23:36,947 INFO L290 TraceCheckUtils]: 21: Hoare triple {99155#false} assume !(0 == ~T2_E~0); {99155#false} is VALID [2022-02-21 04:23:36,947 INFO L290 TraceCheckUtils]: 22: Hoare triple {99155#false} assume !(0 == ~T3_E~0); {99155#false} is VALID [2022-02-21 04:23:36,947 INFO L290 TraceCheckUtils]: 23: Hoare triple {99155#false} assume !(0 == ~T4_E~0); {99155#false} is VALID [2022-02-21 04:23:36,947 INFO L290 TraceCheckUtils]: 24: Hoare triple {99155#false} assume !(0 == ~T5_E~0); {99155#false} is VALID [2022-02-21 04:23:36,947 INFO L290 TraceCheckUtils]: 25: Hoare triple {99155#false} assume !(0 == ~T6_E~0); {99155#false} is VALID [2022-02-21 04:23:36,948 INFO L290 TraceCheckUtils]: 26: Hoare triple {99155#false} assume !(0 == ~T7_E~0); {99155#false} is VALID [2022-02-21 04:23:36,948 INFO L290 TraceCheckUtils]: 27: Hoare triple {99155#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {99155#false} is VALID [2022-02-21 04:23:36,948 INFO L290 TraceCheckUtils]: 28: Hoare triple {99155#false} assume !(0 == ~T9_E~0); {99155#false} is VALID [2022-02-21 04:23:36,948 INFO L290 TraceCheckUtils]: 29: Hoare triple {99155#false} assume !(0 == ~T10_E~0); {99155#false} is VALID [2022-02-21 04:23:36,948 INFO L290 TraceCheckUtils]: 30: Hoare triple {99155#false} assume !(0 == ~T11_E~0); {99155#false} is VALID [2022-02-21 04:23:36,948 INFO L290 TraceCheckUtils]: 31: Hoare triple {99155#false} assume !(0 == ~T12_E~0); {99155#false} is VALID [2022-02-21 04:23:36,948 INFO L290 TraceCheckUtils]: 32: Hoare triple {99155#false} assume !(0 == ~T13_E~0); {99155#false} is VALID [2022-02-21 04:23:36,948 INFO L290 TraceCheckUtils]: 33: Hoare triple {99155#false} assume !(0 == ~E_M~0); {99155#false} is VALID [2022-02-21 04:23:36,949 INFO L290 TraceCheckUtils]: 34: Hoare triple {99155#false} assume !(0 == ~E_1~0); {99155#false} is VALID [2022-02-21 04:23:36,949 INFO L290 TraceCheckUtils]: 35: Hoare triple {99155#false} assume 0 == ~E_2~0;~E_2~0 := 1; {99155#false} is VALID [2022-02-21 04:23:36,949 INFO L290 TraceCheckUtils]: 36: Hoare triple {99155#false} assume !(0 == ~E_3~0); {99155#false} is VALID [2022-02-21 04:23:36,949 INFO L290 TraceCheckUtils]: 37: Hoare triple {99155#false} assume !(0 == ~E_4~0); {99155#false} is VALID [2022-02-21 04:23:36,949 INFO L290 TraceCheckUtils]: 38: Hoare triple {99155#false} assume !(0 == ~E_5~0); {99155#false} is VALID [2022-02-21 04:23:36,949 INFO L290 TraceCheckUtils]: 39: Hoare triple {99155#false} assume !(0 == ~E_6~0); {99155#false} is VALID [2022-02-21 04:23:36,949 INFO L290 TraceCheckUtils]: 40: Hoare triple {99155#false} assume !(0 == ~E_7~0); {99155#false} is VALID [2022-02-21 04:23:36,949 INFO L290 TraceCheckUtils]: 41: Hoare triple {99155#false} assume !(0 == ~E_8~0); {99155#false} is VALID [2022-02-21 04:23:36,950 INFO L290 TraceCheckUtils]: 42: Hoare triple {99155#false} assume !(0 == ~E_9~0); {99155#false} is VALID [2022-02-21 04:23:36,950 INFO L290 TraceCheckUtils]: 43: Hoare triple {99155#false} assume 0 == ~E_10~0;~E_10~0 := 1; {99155#false} is VALID [2022-02-21 04:23:36,950 INFO L290 TraceCheckUtils]: 44: Hoare triple {99155#false} assume !(0 == ~E_11~0); {99155#false} is VALID [2022-02-21 04:23:36,950 INFO L290 TraceCheckUtils]: 45: Hoare triple {99155#false} assume !(0 == ~E_12~0); {99155#false} is VALID [2022-02-21 04:23:36,950 INFO L290 TraceCheckUtils]: 46: Hoare triple {99155#false} assume !(0 == ~E_13~0); {99155#false} is VALID [2022-02-21 04:23:36,950 INFO L290 TraceCheckUtils]: 47: Hoare triple {99155#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {99155#false} is VALID [2022-02-21 04:23:36,950 INFO L290 TraceCheckUtils]: 48: Hoare triple {99155#false} assume !(1 == ~m_pc~0); {99155#false} is VALID [2022-02-21 04:23:36,950 INFO L290 TraceCheckUtils]: 49: Hoare triple {99155#false} is_master_triggered_~__retres1~0#1 := 0; {99155#false} is VALID [2022-02-21 04:23:36,951 INFO L290 TraceCheckUtils]: 50: Hoare triple {99155#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {99155#false} is VALID [2022-02-21 04:23:36,951 INFO L290 TraceCheckUtils]: 51: Hoare triple {99155#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {99155#false} is VALID [2022-02-21 04:23:36,951 INFO L290 TraceCheckUtils]: 52: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp~1#1); {99155#false} is VALID [2022-02-21 04:23:36,951 INFO L290 TraceCheckUtils]: 53: Hoare triple {99155#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {99155#false} is VALID [2022-02-21 04:23:36,951 INFO L290 TraceCheckUtils]: 54: Hoare triple {99155#false} assume 1 == ~t1_pc~0; {99155#false} is VALID [2022-02-21 04:23:36,951 INFO L290 TraceCheckUtils]: 55: Hoare triple {99155#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {99155#false} is VALID [2022-02-21 04:23:36,951 INFO L290 TraceCheckUtils]: 56: Hoare triple {99155#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {99155#false} is VALID [2022-02-21 04:23:36,952 INFO L290 TraceCheckUtils]: 57: Hoare triple {99155#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {99155#false} is VALID [2022-02-21 04:23:36,952 INFO L290 TraceCheckUtils]: 58: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___0~0#1); {99155#false} is VALID [2022-02-21 04:23:36,952 INFO L290 TraceCheckUtils]: 59: Hoare triple {99155#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {99155#false} is VALID [2022-02-21 04:23:36,952 INFO L290 TraceCheckUtils]: 60: Hoare triple {99155#false} assume 1 == ~t2_pc~0; {99155#false} is VALID [2022-02-21 04:23:36,952 INFO L290 TraceCheckUtils]: 61: Hoare triple {99155#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {99155#false} is VALID [2022-02-21 04:23:36,952 INFO L290 TraceCheckUtils]: 62: Hoare triple {99155#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {99155#false} is VALID [2022-02-21 04:23:36,952 INFO L290 TraceCheckUtils]: 63: Hoare triple {99155#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {99155#false} is VALID [2022-02-21 04:23:36,952 INFO L290 TraceCheckUtils]: 64: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___1~0#1); {99155#false} is VALID [2022-02-21 04:23:36,953 INFO L290 TraceCheckUtils]: 65: Hoare triple {99155#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {99155#false} is VALID [2022-02-21 04:23:36,953 INFO L290 TraceCheckUtils]: 66: Hoare triple {99155#false} assume !(1 == ~t3_pc~0); {99155#false} is VALID [2022-02-21 04:23:36,953 INFO L290 TraceCheckUtils]: 67: Hoare triple {99155#false} is_transmit3_triggered_~__retres1~3#1 := 0; {99155#false} is VALID [2022-02-21 04:23:36,953 INFO L290 TraceCheckUtils]: 68: Hoare triple {99155#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {99155#false} is VALID [2022-02-21 04:23:36,953 INFO L290 TraceCheckUtils]: 69: Hoare triple {99155#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {99155#false} is VALID [2022-02-21 04:23:36,953 INFO L290 TraceCheckUtils]: 70: Hoare triple {99155#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {99155#false} is VALID [2022-02-21 04:23:36,953 INFO L290 TraceCheckUtils]: 71: Hoare triple {99155#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {99155#false} is VALID [2022-02-21 04:23:36,953 INFO L290 TraceCheckUtils]: 72: Hoare triple {99155#false} assume 1 == ~t4_pc~0; {99155#false} is VALID [2022-02-21 04:23:36,954 INFO L290 TraceCheckUtils]: 73: Hoare triple {99155#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {99155#false} is VALID [2022-02-21 04:23:36,954 INFO L290 TraceCheckUtils]: 74: Hoare triple {99155#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {99155#false} is VALID [2022-02-21 04:23:36,954 INFO L290 TraceCheckUtils]: 75: Hoare triple {99155#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {99155#false} is VALID [2022-02-21 04:23:36,954 INFO L290 TraceCheckUtils]: 76: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___3~0#1); {99155#false} is VALID [2022-02-21 04:23:36,954 INFO L290 TraceCheckUtils]: 77: Hoare triple {99155#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {99155#false} is VALID [2022-02-21 04:23:36,954 INFO L290 TraceCheckUtils]: 78: Hoare triple {99155#false} assume !(1 == ~t5_pc~0); {99155#false} is VALID [2022-02-21 04:23:36,954 INFO L290 TraceCheckUtils]: 79: Hoare triple {99155#false} is_transmit5_triggered_~__retres1~5#1 := 0; {99155#false} is VALID [2022-02-21 04:23:36,954 INFO L290 TraceCheckUtils]: 80: Hoare triple {99155#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {99155#false} is VALID [2022-02-21 04:23:36,955 INFO L290 TraceCheckUtils]: 81: Hoare triple {99155#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {99155#false} is VALID [2022-02-21 04:23:36,955 INFO L290 TraceCheckUtils]: 82: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___4~0#1); {99155#false} is VALID [2022-02-21 04:23:36,955 INFO L290 TraceCheckUtils]: 83: Hoare triple {99155#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {99155#false} is VALID [2022-02-21 04:23:36,955 INFO L290 TraceCheckUtils]: 84: Hoare triple {99155#false} assume 1 == ~t6_pc~0; {99155#false} is VALID [2022-02-21 04:23:36,955 INFO L290 TraceCheckUtils]: 85: Hoare triple {99155#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {99155#false} is VALID [2022-02-21 04:23:36,955 INFO L290 TraceCheckUtils]: 86: Hoare triple {99155#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {99155#false} is VALID [2022-02-21 04:23:36,955 INFO L290 TraceCheckUtils]: 87: Hoare triple {99155#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {99155#false} is VALID [2022-02-21 04:23:36,955 INFO L290 TraceCheckUtils]: 88: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___5~0#1); {99155#false} is VALID [2022-02-21 04:23:36,956 INFO L290 TraceCheckUtils]: 89: Hoare triple {99155#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {99155#false} is VALID [2022-02-21 04:23:36,956 INFO L290 TraceCheckUtils]: 90: Hoare triple {99155#false} assume !(1 == ~t7_pc~0); {99155#false} is VALID [2022-02-21 04:23:36,956 INFO L290 TraceCheckUtils]: 91: Hoare triple {99155#false} is_transmit7_triggered_~__retres1~7#1 := 0; {99155#false} is VALID [2022-02-21 04:23:36,956 INFO L290 TraceCheckUtils]: 92: Hoare triple {99155#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {99155#false} is VALID [2022-02-21 04:23:36,956 INFO L290 TraceCheckUtils]: 93: Hoare triple {99155#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {99155#false} is VALID [2022-02-21 04:23:36,956 INFO L290 TraceCheckUtils]: 94: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___6~0#1); {99155#false} is VALID [2022-02-21 04:23:36,956 INFO L290 TraceCheckUtils]: 95: Hoare triple {99155#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {99155#false} is VALID [2022-02-21 04:23:36,956 INFO L290 TraceCheckUtils]: 96: Hoare triple {99155#false} assume 1 == ~t8_pc~0; {99155#false} is VALID [2022-02-21 04:23:36,957 INFO L290 TraceCheckUtils]: 97: Hoare triple {99155#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {99155#false} is VALID [2022-02-21 04:23:36,957 INFO L290 TraceCheckUtils]: 98: Hoare triple {99155#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {99155#false} is VALID [2022-02-21 04:23:36,957 INFO L290 TraceCheckUtils]: 99: Hoare triple {99155#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {99155#false} is VALID [2022-02-21 04:23:36,957 INFO L290 TraceCheckUtils]: 100: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___7~0#1); {99155#false} is VALID [2022-02-21 04:23:36,957 INFO L290 TraceCheckUtils]: 101: Hoare triple {99155#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {99155#false} is VALID [2022-02-21 04:23:36,957 INFO L290 TraceCheckUtils]: 102: Hoare triple {99155#false} assume 1 == ~t9_pc~0; {99155#false} is VALID [2022-02-21 04:23:36,957 INFO L290 TraceCheckUtils]: 103: Hoare triple {99155#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {99155#false} is VALID [2022-02-21 04:23:36,957 INFO L290 TraceCheckUtils]: 104: Hoare triple {99155#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {99155#false} is VALID [2022-02-21 04:23:36,958 INFO L290 TraceCheckUtils]: 105: Hoare triple {99155#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {99155#false} is VALID [2022-02-21 04:23:36,958 INFO L290 TraceCheckUtils]: 106: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___8~0#1); {99155#false} is VALID [2022-02-21 04:23:36,958 INFO L290 TraceCheckUtils]: 107: Hoare triple {99155#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {99155#false} is VALID [2022-02-21 04:23:36,958 INFO L290 TraceCheckUtils]: 108: Hoare triple {99155#false} assume !(1 == ~t10_pc~0); {99155#false} is VALID [2022-02-21 04:23:36,958 INFO L290 TraceCheckUtils]: 109: Hoare triple {99155#false} is_transmit10_triggered_~__retres1~10#1 := 0; {99155#false} is VALID [2022-02-21 04:23:36,958 INFO L290 TraceCheckUtils]: 110: Hoare triple {99155#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {99155#false} is VALID [2022-02-21 04:23:36,958 INFO L290 TraceCheckUtils]: 111: Hoare triple {99155#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {99155#false} is VALID [2022-02-21 04:23:36,958 INFO L290 TraceCheckUtils]: 112: Hoare triple {99155#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {99155#false} is VALID [2022-02-21 04:23:36,959 INFO L290 TraceCheckUtils]: 113: Hoare triple {99155#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {99155#false} is VALID [2022-02-21 04:23:36,959 INFO L290 TraceCheckUtils]: 114: Hoare triple {99155#false} assume 1 == ~t11_pc~0; {99155#false} is VALID [2022-02-21 04:23:36,959 INFO L290 TraceCheckUtils]: 115: Hoare triple {99155#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {99155#false} is VALID [2022-02-21 04:23:36,959 INFO L290 TraceCheckUtils]: 116: Hoare triple {99155#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {99155#false} is VALID [2022-02-21 04:23:36,959 INFO L290 TraceCheckUtils]: 117: Hoare triple {99155#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {99155#false} is VALID [2022-02-21 04:23:36,959 INFO L290 TraceCheckUtils]: 118: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___10~0#1); {99155#false} is VALID [2022-02-21 04:23:36,959 INFO L290 TraceCheckUtils]: 119: Hoare triple {99155#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {99155#false} is VALID [2022-02-21 04:23:36,959 INFO L290 TraceCheckUtils]: 120: Hoare triple {99155#false} assume !(1 == ~t12_pc~0); {99155#false} is VALID [2022-02-21 04:23:36,960 INFO L290 TraceCheckUtils]: 121: Hoare triple {99155#false} is_transmit12_triggered_~__retres1~12#1 := 0; {99155#false} is VALID [2022-02-21 04:23:36,960 INFO L290 TraceCheckUtils]: 122: Hoare triple {99155#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {99155#false} is VALID [2022-02-21 04:23:36,960 INFO L290 TraceCheckUtils]: 123: Hoare triple {99155#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {99155#false} is VALID [2022-02-21 04:23:36,960 INFO L290 TraceCheckUtils]: 124: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___11~0#1); {99155#false} is VALID [2022-02-21 04:23:36,960 INFO L290 TraceCheckUtils]: 125: Hoare triple {99155#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {99155#false} is VALID [2022-02-21 04:23:36,960 INFO L290 TraceCheckUtils]: 126: Hoare triple {99155#false} assume 1 == ~t13_pc~0; {99155#false} is VALID [2022-02-21 04:23:36,960 INFO L290 TraceCheckUtils]: 127: Hoare triple {99155#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {99155#false} is VALID [2022-02-21 04:23:36,961 INFO L290 TraceCheckUtils]: 128: Hoare triple {99155#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {99155#false} is VALID [2022-02-21 04:23:36,961 INFO L290 TraceCheckUtils]: 129: Hoare triple {99155#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {99155#false} is VALID [2022-02-21 04:23:36,961 INFO L290 TraceCheckUtils]: 130: Hoare triple {99155#false} assume !(0 != activate_threads_~tmp___12~0#1); {99155#false} is VALID [2022-02-21 04:23:36,961 INFO L290 TraceCheckUtils]: 131: Hoare triple {99155#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {99155#false} is VALID [2022-02-21 04:23:36,961 INFO L290 TraceCheckUtils]: 132: Hoare triple {99155#false} assume !(1 == ~M_E~0); {99155#false} is VALID [2022-02-21 04:23:36,961 INFO L290 TraceCheckUtils]: 133: Hoare triple {99155#false} assume !(1 == ~T1_E~0); {99155#false} is VALID [2022-02-21 04:23:36,961 INFO L290 TraceCheckUtils]: 134: Hoare triple {99155#false} assume !(1 == ~T2_E~0); {99155#false} is VALID [2022-02-21 04:23:36,961 INFO L290 TraceCheckUtils]: 135: Hoare triple {99155#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {99155#false} is VALID [2022-02-21 04:23:36,962 INFO L290 TraceCheckUtils]: 136: Hoare triple {99155#false} assume !(1 == ~T4_E~0); {99155#false} is VALID [2022-02-21 04:23:36,962 INFO L290 TraceCheckUtils]: 137: Hoare triple {99155#false} assume !(1 == ~T5_E~0); {99155#false} is VALID [2022-02-21 04:23:36,962 INFO L290 TraceCheckUtils]: 138: Hoare triple {99155#false} assume !(1 == ~T6_E~0); {99155#false} is VALID [2022-02-21 04:23:36,962 INFO L290 TraceCheckUtils]: 139: Hoare triple {99155#false} assume !(1 == ~T7_E~0); {99155#false} is VALID [2022-02-21 04:23:36,962 INFO L290 TraceCheckUtils]: 140: Hoare triple {99155#false} assume !(1 == ~T8_E~0); {99155#false} is VALID [2022-02-21 04:23:36,962 INFO L290 TraceCheckUtils]: 141: Hoare triple {99155#false} assume !(1 == ~T9_E~0); {99155#false} is VALID [2022-02-21 04:23:36,962 INFO L290 TraceCheckUtils]: 142: Hoare triple {99155#false} assume !(1 == ~T10_E~0); {99155#false} is VALID [2022-02-21 04:23:36,962 INFO L290 TraceCheckUtils]: 143: Hoare triple {99155#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {99155#false} is VALID [2022-02-21 04:23:36,963 INFO L290 TraceCheckUtils]: 144: Hoare triple {99155#false} assume !(1 == ~T12_E~0); {99155#false} is VALID [2022-02-21 04:23:36,963 INFO L290 TraceCheckUtils]: 145: Hoare triple {99155#false} assume !(1 == ~T13_E~0); {99155#false} is VALID [2022-02-21 04:23:36,963 INFO L290 TraceCheckUtils]: 146: Hoare triple {99155#false} assume !(1 == ~E_M~0); {99155#false} is VALID [2022-02-21 04:23:36,963 INFO L290 TraceCheckUtils]: 147: Hoare triple {99155#false} assume !(1 == ~E_1~0); {99155#false} is VALID [2022-02-21 04:23:36,963 INFO L290 TraceCheckUtils]: 148: Hoare triple {99155#false} assume !(1 == ~E_2~0); {99155#false} is VALID [2022-02-21 04:23:36,963 INFO L290 TraceCheckUtils]: 149: Hoare triple {99155#false} assume !(1 == ~E_3~0); {99155#false} is VALID [2022-02-21 04:23:36,963 INFO L290 TraceCheckUtils]: 150: Hoare triple {99155#false} assume !(1 == ~E_4~0); {99155#false} is VALID [2022-02-21 04:23:36,963 INFO L290 TraceCheckUtils]: 151: Hoare triple {99155#false} assume 1 == ~E_5~0;~E_5~0 := 2; {99155#false} is VALID [2022-02-21 04:23:36,964 INFO L290 TraceCheckUtils]: 152: Hoare triple {99155#false} assume !(1 == ~E_6~0); {99155#false} is VALID [2022-02-21 04:23:36,964 INFO L290 TraceCheckUtils]: 153: Hoare triple {99155#false} assume !(1 == ~E_7~0); {99155#false} is VALID [2022-02-21 04:23:36,964 INFO L290 TraceCheckUtils]: 154: Hoare triple {99155#false} assume !(1 == ~E_8~0); {99155#false} is VALID [2022-02-21 04:23:36,964 INFO L290 TraceCheckUtils]: 155: Hoare triple {99155#false} assume !(1 == ~E_9~0); {99155#false} is VALID [2022-02-21 04:23:36,964 INFO L290 TraceCheckUtils]: 156: Hoare triple {99155#false} assume !(1 == ~E_10~0); {99155#false} is VALID [2022-02-21 04:23:36,964 INFO L290 TraceCheckUtils]: 157: Hoare triple {99155#false} assume !(1 == ~E_11~0); {99155#false} is VALID [2022-02-21 04:23:36,964 INFO L290 TraceCheckUtils]: 158: Hoare triple {99155#false} assume !(1 == ~E_12~0); {99155#false} is VALID [2022-02-21 04:23:36,964 INFO L290 TraceCheckUtils]: 159: Hoare triple {99155#false} assume 1 == ~E_13~0;~E_13~0 := 2; {99155#false} is VALID [2022-02-21 04:23:36,965 INFO L290 TraceCheckUtils]: 160: Hoare triple {99155#false} assume { :end_inline_reset_delta_events } true; {99155#false} is VALID [2022-02-21 04:23:36,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:36,965 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:36,965 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1382754918] [2022-02-21 04:23:36,965 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1382754918] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:36,965 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:36,966 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:36,966 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [400714153] [2022-02-21 04:23:36,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:36,967 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:36,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:36,967 INFO L85 PathProgramCache]: Analyzing trace with hash -258359003, now seen corresponding path program 1 times [2022-02-21 04:23:36,967 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:36,967 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120297922] [2022-02-21 04:23:36,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:36,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:36,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:37,021 INFO L290 TraceCheckUtils]: 0: Hoare triple {99157#true} assume !false; {99157#true} is VALID [2022-02-21 04:23:37,021 INFO L290 TraceCheckUtils]: 1: Hoare triple {99157#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {99157#true} is VALID [2022-02-21 04:23:37,021 INFO L290 TraceCheckUtils]: 2: Hoare triple {99157#true} assume !false; {99157#true} is VALID [2022-02-21 04:23:37,021 INFO L290 TraceCheckUtils]: 3: Hoare triple {99157#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {99157#true} is VALID [2022-02-21 04:23:37,022 INFO L290 TraceCheckUtils]: 4: Hoare triple {99157#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {99157#true} is VALID [2022-02-21 04:23:37,022 INFO L290 TraceCheckUtils]: 5: Hoare triple {99157#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {99157#true} is VALID [2022-02-21 04:23:37,022 INFO L290 TraceCheckUtils]: 6: Hoare triple {99157#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {99157#true} is VALID [2022-02-21 04:23:37,022 INFO L290 TraceCheckUtils]: 7: Hoare triple {99157#true} assume !(0 != eval_~tmp~0#1); {99157#true} is VALID [2022-02-21 04:23:37,022 INFO L290 TraceCheckUtils]: 8: Hoare triple {99157#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {99157#true} is VALID [2022-02-21 04:23:37,022 INFO L290 TraceCheckUtils]: 9: Hoare triple {99157#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {99157#true} is VALID [2022-02-21 04:23:37,022 INFO L290 TraceCheckUtils]: 10: Hoare triple {99157#true} assume 0 == ~M_E~0;~M_E~0 := 1; {99157#true} is VALID [2022-02-21 04:23:37,023 INFO L290 TraceCheckUtils]: 11: Hoare triple {99157#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {99157#true} is VALID [2022-02-21 04:23:37,023 INFO L290 TraceCheckUtils]: 12: Hoare triple {99157#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {99157#true} is VALID [2022-02-21 04:23:37,023 INFO L290 TraceCheckUtils]: 13: Hoare triple {99157#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {99157#true} is VALID [2022-02-21 04:23:37,023 INFO L290 TraceCheckUtils]: 14: Hoare triple {99157#true} assume !(0 == ~T4_E~0); {99157#true} is VALID [2022-02-21 04:23:37,023 INFO L290 TraceCheckUtils]: 15: Hoare triple {99157#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {99157#true} is VALID [2022-02-21 04:23:37,023 INFO L290 TraceCheckUtils]: 16: Hoare triple {99157#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {99157#true} is VALID [2022-02-21 04:23:37,023 INFO L290 TraceCheckUtils]: 17: Hoare triple {99157#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,024 INFO L290 TraceCheckUtils]: 18: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,024 INFO L290 TraceCheckUtils]: 19: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,024 INFO L290 TraceCheckUtils]: 20: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,025 INFO L290 TraceCheckUtils]: 21: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,025 INFO L290 TraceCheckUtils]: 22: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,025 INFO L290 TraceCheckUtils]: 23: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,025 INFO L290 TraceCheckUtils]: 24: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,026 INFO L290 TraceCheckUtils]: 25: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,026 INFO L290 TraceCheckUtils]: 26: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,026 INFO L290 TraceCheckUtils]: 27: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,026 INFO L290 TraceCheckUtils]: 28: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,027 INFO L290 TraceCheckUtils]: 29: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,027 INFO L290 TraceCheckUtils]: 30: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,027 INFO L290 TraceCheckUtils]: 31: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,027 INFO L290 TraceCheckUtils]: 32: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,028 INFO L290 TraceCheckUtils]: 33: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,028 INFO L290 TraceCheckUtils]: 34: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,028 INFO L290 TraceCheckUtils]: 35: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,028 INFO L290 TraceCheckUtils]: 36: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,029 INFO L290 TraceCheckUtils]: 37: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,029 INFO L290 TraceCheckUtils]: 38: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,029 INFO L290 TraceCheckUtils]: 39: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~m_pc~0); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,029 INFO L290 TraceCheckUtils]: 40: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,030 INFO L290 TraceCheckUtils]: 41: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,030 INFO L290 TraceCheckUtils]: 42: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,030 INFO L290 TraceCheckUtils]: 43: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,031 INFO L290 TraceCheckUtils]: 44: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,031 INFO L290 TraceCheckUtils]: 45: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t1_pc~0); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,031 INFO L290 TraceCheckUtils]: 46: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,031 INFO L290 TraceCheckUtils]: 47: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,032 INFO L290 TraceCheckUtils]: 48: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,032 INFO L290 TraceCheckUtils]: 49: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,032 INFO L290 TraceCheckUtils]: 50: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,032 INFO L290 TraceCheckUtils]: 51: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t2_pc~0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,033 INFO L290 TraceCheckUtils]: 52: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,033 INFO L290 TraceCheckUtils]: 53: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,033 INFO L290 TraceCheckUtils]: 54: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,033 INFO L290 TraceCheckUtils]: 55: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,034 INFO L290 TraceCheckUtils]: 56: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,034 INFO L290 TraceCheckUtils]: 57: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,034 INFO L290 TraceCheckUtils]: 58: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,034 INFO L290 TraceCheckUtils]: 59: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,035 INFO L290 TraceCheckUtils]: 60: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,035 INFO L290 TraceCheckUtils]: 61: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,035 INFO L290 TraceCheckUtils]: 62: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,035 INFO L290 TraceCheckUtils]: 63: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,036 INFO L290 TraceCheckUtils]: 64: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,036 INFO L290 TraceCheckUtils]: 65: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,036 INFO L290 TraceCheckUtils]: 66: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,036 INFO L290 TraceCheckUtils]: 67: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,037 INFO L290 TraceCheckUtils]: 68: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,037 INFO L290 TraceCheckUtils]: 69: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,037 INFO L290 TraceCheckUtils]: 70: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,038 INFO L290 TraceCheckUtils]: 71: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,038 INFO L290 TraceCheckUtils]: 72: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,038 INFO L290 TraceCheckUtils]: 73: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,038 INFO L290 TraceCheckUtils]: 74: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,039 INFO L290 TraceCheckUtils]: 75: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,039 INFO L290 TraceCheckUtils]: 76: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,039 INFO L290 TraceCheckUtils]: 77: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,039 INFO L290 TraceCheckUtils]: 78: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,040 INFO L290 TraceCheckUtils]: 79: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,040 INFO L290 TraceCheckUtils]: 80: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,040 INFO L290 TraceCheckUtils]: 81: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,040 INFO L290 TraceCheckUtils]: 82: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,041 INFO L290 TraceCheckUtils]: 83: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,041 INFO L290 TraceCheckUtils]: 84: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,041 INFO L290 TraceCheckUtils]: 85: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,041 INFO L290 TraceCheckUtils]: 86: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,042 INFO L290 TraceCheckUtils]: 87: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t8_pc~0); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,042 INFO L290 TraceCheckUtils]: 88: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,042 INFO L290 TraceCheckUtils]: 89: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,043 INFO L290 TraceCheckUtils]: 90: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,043 INFO L290 TraceCheckUtils]: 91: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,043 INFO L290 TraceCheckUtils]: 92: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,043 INFO L290 TraceCheckUtils]: 93: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,044 INFO L290 TraceCheckUtils]: 94: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,044 INFO L290 TraceCheckUtils]: 95: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,044 INFO L290 TraceCheckUtils]: 96: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,044 INFO L290 TraceCheckUtils]: 97: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,045 INFO L290 TraceCheckUtils]: 98: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,045 INFO L290 TraceCheckUtils]: 99: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t10_pc~0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,045 INFO L290 TraceCheckUtils]: 100: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,045 INFO L290 TraceCheckUtils]: 101: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,046 INFO L290 TraceCheckUtils]: 102: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,046 INFO L290 TraceCheckUtils]: 103: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,046 INFO L290 TraceCheckUtils]: 104: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,046 INFO L290 TraceCheckUtils]: 105: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t11_pc~0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,047 INFO L290 TraceCheckUtils]: 106: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,047 INFO L290 TraceCheckUtils]: 107: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,047 INFO L290 TraceCheckUtils]: 108: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,047 INFO L290 TraceCheckUtils]: 109: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,048 INFO L290 TraceCheckUtils]: 110: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,048 INFO L290 TraceCheckUtils]: 111: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t12_pc~0); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,048 INFO L290 TraceCheckUtils]: 112: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,049 INFO L290 TraceCheckUtils]: 113: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,049 INFO L290 TraceCheckUtils]: 114: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,049 INFO L290 TraceCheckUtils]: 115: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,049 INFO L290 TraceCheckUtils]: 116: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,050 INFO L290 TraceCheckUtils]: 117: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t13_pc~0); {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,050 INFO L290 TraceCheckUtils]: 118: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,050 INFO L290 TraceCheckUtils]: 119: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,050 INFO L290 TraceCheckUtils]: 120: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,051 INFO L290 TraceCheckUtils]: 121: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,051 INFO L290 TraceCheckUtils]: 122: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,051 INFO L290 TraceCheckUtils]: 123: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,051 INFO L290 TraceCheckUtils]: 124: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,052 INFO L290 TraceCheckUtils]: 125: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,052 INFO L290 TraceCheckUtils]: 126: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,052 INFO L290 TraceCheckUtils]: 127: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,052 INFO L290 TraceCheckUtils]: 128: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,053 INFO L290 TraceCheckUtils]: 129: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {99159#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:37,053 INFO L290 TraceCheckUtils]: 130: Hoare triple {99159#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {99158#false} is VALID [2022-02-21 04:23:37,053 INFO L290 TraceCheckUtils]: 131: Hoare triple {99158#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,053 INFO L290 TraceCheckUtils]: 132: Hoare triple {99158#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,053 INFO L290 TraceCheckUtils]: 133: Hoare triple {99158#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,054 INFO L290 TraceCheckUtils]: 134: Hoare triple {99158#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,054 INFO L290 TraceCheckUtils]: 135: Hoare triple {99158#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,054 INFO L290 TraceCheckUtils]: 136: Hoare triple {99158#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,054 INFO L290 TraceCheckUtils]: 137: Hoare triple {99158#false} assume 1 == ~E_M~0;~E_M~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,054 INFO L290 TraceCheckUtils]: 138: Hoare triple {99158#false} assume !(1 == ~E_1~0); {99158#false} is VALID [2022-02-21 04:23:37,054 INFO L290 TraceCheckUtils]: 139: Hoare triple {99158#false} assume 1 == ~E_2~0;~E_2~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,054 INFO L290 TraceCheckUtils]: 140: Hoare triple {99158#false} assume 1 == ~E_3~0;~E_3~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,054 INFO L290 TraceCheckUtils]: 141: Hoare triple {99158#false} assume 1 == ~E_4~0;~E_4~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,055 INFO L290 TraceCheckUtils]: 142: Hoare triple {99158#false} assume 1 == ~E_5~0;~E_5~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,055 INFO L290 TraceCheckUtils]: 143: Hoare triple {99158#false} assume 1 == ~E_6~0;~E_6~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,055 INFO L290 TraceCheckUtils]: 144: Hoare triple {99158#false} assume 1 == ~E_7~0;~E_7~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,055 INFO L290 TraceCheckUtils]: 145: Hoare triple {99158#false} assume 1 == ~E_8~0;~E_8~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,055 INFO L290 TraceCheckUtils]: 146: Hoare triple {99158#false} assume !(1 == ~E_9~0); {99158#false} is VALID [2022-02-21 04:23:37,055 INFO L290 TraceCheckUtils]: 147: Hoare triple {99158#false} assume 1 == ~E_10~0;~E_10~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,055 INFO L290 TraceCheckUtils]: 148: Hoare triple {99158#false} assume 1 == ~E_11~0;~E_11~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,055 INFO L290 TraceCheckUtils]: 149: Hoare triple {99158#false} assume 1 == ~E_12~0;~E_12~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,056 INFO L290 TraceCheckUtils]: 150: Hoare triple {99158#false} assume 1 == ~E_13~0;~E_13~0 := 2; {99158#false} is VALID [2022-02-21 04:23:37,056 INFO L290 TraceCheckUtils]: 151: Hoare triple {99158#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {99158#false} is VALID [2022-02-21 04:23:37,056 INFO L290 TraceCheckUtils]: 152: Hoare triple {99158#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {99158#false} is VALID [2022-02-21 04:23:37,056 INFO L290 TraceCheckUtils]: 153: Hoare triple {99158#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {99158#false} is VALID [2022-02-21 04:23:37,056 INFO L290 TraceCheckUtils]: 154: Hoare triple {99158#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {99158#false} is VALID [2022-02-21 04:23:37,056 INFO L290 TraceCheckUtils]: 155: Hoare triple {99158#false} assume !(0 == start_simulation_~tmp~3#1); {99158#false} is VALID [2022-02-21 04:23:37,056 INFO L290 TraceCheckUtils]: 156: Hoare triple {99158#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {99158#false} is VALID [2022-02-21 04:23:37,056 INFO L290 TraceCheckUtils]: 157: Hoare triple {99158#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {99158#false} is VALID [2022-02-21 04:23:37,057 INFO L290 TraceCheckUtils]: 158: Hoare triple {99158#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {99158#false} is VALID [2022-02-21 04:23:37,057 INFO L290 TraceCheckUtils]: 159: Hoare triple {99158#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {99158#false} is VALID [2022-02-21 04:23:37,057 INFO L290 TraceCheckUtils]: 160: Hoare triple {99158#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {99158#false} is VALID [2022-02-21 04:23:37,057 INFO L290 TraceCheckUtils]: 161: Hoare triple {99158#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {99158#false} is VALID [2022-02-21 04:23:37,057 INFO L290 TraceCheckUtils]: 162: Hoare triple {99158#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {99158#false} is VALID [2022-02-21 04:23:37,057 INFO L290 TraceCheckUtils]: 163: Hoare triple {99158#false} assume !(0 != start_simulation_~tmp___0~1#1); {99158#false} is VALID [2022-02-21 04:23:37,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:37,058 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:37,058 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120297922] [2022-02-21 04:23:37,058 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1120297922] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:37,058 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:37,058 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:37,058 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004622762] [2022-02-21 04:23:37,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:37,059 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:37,059 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:37,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:37,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:37,060 INFO L87 Difference]: Start difference. First operand 2021 states and 2981 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:38,345 INFO L93 Difference]: Finished difference Result 2021 states and 2980 transitions. [2022-02-21 04:23:38,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:38,345 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,435 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:38,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2980 transitions. [2022-02-21 04:23:38,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:38,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2980 transitions. [2022-02-21 04:23:38,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-02-21 04:23:38,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-02-21 04:23:38,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2980 transitions. [2022-02-21 04:23:38,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:38,631 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2022-02-21 04:23:38,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2980 transitions. [2022-02-21 04:23:38,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-02-21 04:23:38,645 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:38,647 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2021 states and 2980 transitions. Second operand has 2021 states, 2021 states have (on average 1.4745175655616032) internal successors, (2980), 2020 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,648 INFO L74 IsIncluded]: Start isIncluded. First operand 2021 states and 2980 transitions. Second operand has 2021 states, 2021 states have (on average 1.4745175655616032) internal successors, (2980), 2020 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,649 INFO L87 Difference]: Start difference. First operand 2021 states and 2980 transitions. Second operand has 2021 states, 2021 states have (on average 1.4745175655616032) internal successors, (2980), 2020 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:38,730 INFO L93 Difference]: Finished difference Result 2021 states and 2980 transitions. [2022-02-21 04:23:38,731 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2980 transitions. [2022-02-21 04:23:38,732 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:38,732 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:38,734 INFO L74 IsIncluded]: Start isIncluded. First operand has 2021 states, 2021 states have (on average 1.4745175655616032) internal successors, (2980), 2020 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2980 transitions. [2022-02-21 04:23:38,735 INFO L87 Difference]: Start difference. First operand has 2021 states, 2021 states have (on average 1.4745175655616032) internal successors, (2980), 2020 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2021 states and 2980 transitions. [2022-02-21 04:23:38,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:38,818 INFO L93 Difference]: Finished difference Result 2021 states and 2980 transitions. [2022-02-21 04:23:38,818 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2980 transitions. [2022-02-21 04:23:38,819 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:38,819 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:38,819 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:38,819 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:38,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4745175655616032) internal successors, (2980), 2020 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2980 transitions. [2022-02-21 04:23:38,902 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2022-02-21 04:23:38,902 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2022-02-21 04:23:38,902 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:23:38,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2980 transitions. [2022-02-21 04:23:38,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-02-21 04:23:38,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:38,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:38,913 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:38,914 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:38,914 INFO L791 eck$LassoCheckResult]: Stem: 102057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 102058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 101789#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101790#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103180#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 103181#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 101976#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 101977#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102011#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102848#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 102849#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 102961#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 102962#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 101795#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 101796#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 102998#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 102320#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 102321#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 102902#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 103168#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 103058#L1286-2 assume !(0 == ~T1_E~0); 101704#L1291-1 assume !(0 == ~T2_E~0); 101705#L1296-1 assume !(0 == ~T3_E~0); 102410#L1301-1 assume !(0 == ~T4_E~0); 102411#L1306-1 assume !(0 == ~T5_E~0); 102911#L1311-1 assume !(0 == ~T6_E~0); 101664#L1316-1 assume !(0 == ~T7_E~0); 101665#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 102430#L1326-1 assume !(0 == ~T9_E~0); 101479#L1331-1 assume !(0 == ~T10_E~0); 101185#L1336-1 assume !(0 == ~T11_E~0); 101186#L1341-1 assume !(0 == ~T12_E~0); 101237#L1346-1 assume !(0 == ~T13_E~0); 101238#L1351-1 assume !(0 == ~E_M~0); 101611#L1356-1 assume !(0 == ~E_1~0); 101612#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 103131#L1366-1 assume !(0 == ~E_3~0); 101657#L1371-1 assume !(0 == ~E_4~0); 101658#L1376-1 assume !(0 == ~E_5~0); 102471#L1381-1 assume !(0 == ~E_6~0); 102472#L1386-1 assume !(0 == ~E_7~0); 103159#L1391-1 assume !(0 == ~E_8~0); 103172#L1396-1 assume !(0 == ~E_9~0); 102354#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 102355#L1406-1 assume !(0 == ~E_11~0); 102657#L1411-1 assume !(0 == ~E_12~0); 102658#L1416-1 assume !(0 == ~E_13~0); 102278#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102116#L635 assume !(1 == ~m_pc~0); 101255#L635-2 is_master_triggered_~__retres1~0#1 := 0; 101256#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101606#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102242#L1598 assume !(0 != activate_threads_~tmp~1#1); 101434#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101435#L654 assume 1 == ~t1_pc~0; 102140#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 102141#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103156#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102222#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 102223#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101482#L673 assume 1 == ~t2_pc~0; 101483#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 102627#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102628#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103186#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 103193#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102301#L692 assume !(1 == ~t3_pc~0); 102118#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102119#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101978#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 101946#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 101947#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101507#L711 assume 1 == ~t4_pc~0; 101508#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 101991#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102448#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 101210#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 101211#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103179#L730 assume !(1 == ~t5_pc~0); 102561#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 101389#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101390#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 101517#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 101518#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101860#L749 assume 1 == ~t6_pc~0; 101634#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 101394#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101826#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 101827#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 102049#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101190#L768 assume !(1 == ~t7_pc~0); 101191#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 102495#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101427#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 101428#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 102514#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 101666#L787 assume 1 == ~t8_pc~0; 101667#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 102862#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 103026#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 103027#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 101235#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 101236#L806 assume 1 == ~t9_pc~0; 102873#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 101270#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 101271#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 101519#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 101520#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 102856#L825 assume !(1 == ~t10_pc~0); 102857#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 102462#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 102463#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 101607#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101608#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 102191#L844 assume 1 == ~t11_pc~0; 101881#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 101882#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 102248#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 102249#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 102844#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 102845#L863 assume !(1 == ~t12_pc~0); 101370#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 101369#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 101597#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 102936#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 102937#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 102315#L882 assume 1 == ~t13_pc~0; 102316#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 102600#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 103101#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 102904#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 102587#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102588#L1434 assume !(1 == ~M_E~0); 103109#L1434-2 assume !(1 == ~T1_E~0); 103185#L1439-1 assume !(1 == ~T2_E~0); 101500#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101501#L1449-1 assume !(1 == ~T4_E~0); 101943#L1454-1 assume !(1 == ~T5_E~0); 101944#L1459-1 assume !(1 == ~T6_E~0); 102515#L1464-1 assume !(1 == ~T7_E~0); 102516#L1469-1 assume !(1 == ~T8_E~0); 102601#L1474-1 assume !(1 == ~T9_E~0); 102279#L1479-1 assume !(1 == ~T10_E~0); 102280#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 102523#L1489-1 assume !(1 == ~T12_E~0); 102157#L1494-1 assume !(1 == ~T13_E~0); 102158#L1499-1 assume !(1 == ~E_M~0); 102339#L1504-1 assume !(1 == ~E_1~0); 102340#L1509-1 assume !(1 == ~E_2~0); 102953#L1514-1 assume !(1 == ~E_3~0); 102638#L1519-1 assume !(1 == ~E_4~0); 102639#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 103143#L1529-1 assume !(1 == ~E_6~0); 103144#L1534-1 assume !(1 == ~E_7~0); 101290#L1539-1 assume !(1 == ~E_8~0); 101291#L1544-1 assume !(1 == ~E_9~0); 101721#L1549-1 assume !(1 == ~E_10~0); 103121#L1554-1 assume !(1 == ~E_11~0); 103119#L1559-1 assume !(1 == ~E_12~0); 102981#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 102982#L1569-1 assume { :end_inline_reset_delta_events } true; 103137#L1935-2 [2022-02-21 04:23:38,914 INFO L793 eck$LassoCheckResult]: Loop: 103137#L1935-2 assume !false; 101299#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 101300#L1261 assume !false; 102527#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 102528#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101430#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 101600#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 101601#L1074 assume !(0 != eval_~tmp~0#1); 101958#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 102556#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 102957#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103013#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 102732#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 102733#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103169#L1301-3 assume !(0 == ~T4_E~0); 103127#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 102235#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 101534#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 101535#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 101640#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 102376#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 102641#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 102642#L1341-3 assume !(0 == ~T12_E~0); 101936#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 101927#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 101871#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 101872#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 102452#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 101225#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 101226#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102968#L1381-3 assume !(0 == ~E_6~0); 102817#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 102818#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 102999#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 103000#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 101605#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 101436#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 101437#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 102064#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101314#L635-45 assume 1 == ~m_pc~0; 101315#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 102109#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102589#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102843#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 101623#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101624#L654-45 assume !(1 == ~t1_pc~0); 102445#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 102792#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101277#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101278#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 101303#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102130#L673-45 assume !(1 == ~t2_pc~0); 102131#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 102455#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102456#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103081#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 102901#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101748#L692-45 assume !(1 == ~t3_pc~0); 101474#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 101475#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102519#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 101802#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 101803#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102115#L711-45 assume !(1 == ~t4_pc~0); 102241#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 102240#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102092#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 102093#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 102496#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101647#L730-45 assume 1 == ~t5_pc~0; 101485#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 101486#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101895#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 101896#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 102647#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101458#L749-45 assume !(1 == ~t6_pc~0); 101459#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 102859#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102622#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 102623#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 102774#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101774#L768-45 assume !(1 == ~t7_pc~0); 101776#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 101914#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102718#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 102719#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 102758#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102759#L787-45 assume !(1 == ~t8_pc~0); 102928#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 101920#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101921#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 102337#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102338#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102646#L806-45 assume 1 == ~t9_pc~0; 103122#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 101334#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 102159#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 101987#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 101899#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 101900#L825-45 assume !(1 == ~t10_pc~0); 102423#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 102424#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 102529#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 102530#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 102682#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 101542#L844-45 assume !(1 == ~t11_pc~0); 101543#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 102065#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 102066#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 102082#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 102493#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 101582#L863-45 assume !(1 == ~t12_pc~0); 101584#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 101183#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 101184#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 101699#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 101700#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 102499#L882-45 assume 1 == ~t13_pc~0; 102853#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 101202#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 101203#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 101811#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 102990#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102606#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 102607#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 102791#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 101496#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101497#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101659#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 102596#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 102597#L1464-3 assume !(1 == ~T7_E~0); 103043#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 102970#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 102971#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 103045#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 102237#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 102238#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 102898#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 102533#L1504-3 assume !(1 == ~E_1~0); 102534#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 102979#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 103019#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 102160#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 102161#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 103066#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 102461#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101915#L1544-3 assume !(1 == ~E_9~0); 101916#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 102431#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 101547#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 101548#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 102697#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 102698#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101432#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 101997#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 102668#L1954 assume !(0 == start_simulation_~tmp~3#1); 102670#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 102920#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101715#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 102756#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 102886#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 102887#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102977#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 103039#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 103137#L1935-2 [2022-02-21 04:23:38,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:38,915 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2022-02-21 04:23:38,915 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:38,915 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782199166] [2022-02-21 04:23:38,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:38,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:38,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:38,940 INFO L290 TraceCheckUtils]: 0: Hoare triple {107247#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,941 INFO L290 TraceCheckUtils]: 1: Hoare triple {107249#(<= 2 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,941 INFO L290 TraceCheckUtils]: 2: Hoare triple {107249#(<= 2 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,941 INFO L290 TraceCheckUtils]: 3: Hoare triple {107249#(<= 2 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,941 INFO L290 TraceCheckUtils]: 4: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,942 INFO L290 TraceCheckUtils]: 5: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,942 INFO L290 TraceCheckUtils]: 6: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,942 INFO L290 TraceCheckUtils]: 7: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,943 INFO L290 TraceCheckUtils]: 8: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,943 INFO L290 TraceCheckUtils]: 9: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,943 INFO L290 TraceCheckUtils]: 10: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,944 INFO L290 TraceCheckUtils]: 11: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,944 INFO L290 TraceCheckUtils]: 12: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,944 INFO L290 TraceCheckUtils]: 13: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,944 INFO L290 TraceCheckUtils]: 14: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,945 INFO L290 TraceCheckUtils]: 15: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,945 INFO L290 TraceCheckUtils]: 16: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,945 INFO L290 TraceCheckUtils]: 17: Hoare triple {107249#(<= 2 ~M_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,946 INFO L290 TraceCheckUtils]: 18: Hoare triple {107249#(<= 2 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {107249#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:23:38,946 INFO L290 TraceCheckUtils]: 19: Hoare triple {107249#(<= 2 ~M_E~0)} assume 0 == ~M_E~0;~M_E~0 := 1; {107248#false} is VALID [2022-02-21 04:23:38,946 INFO L290 TraceCheckUtils]: 20: Hoare triple {107248#false} assume !(0 == ~T1_E~0); {107248#false} is VALID [2022-02-21 04:23:38,946 INFO L290 TraceCheckUtils]: 21: Hoare triple {107248#false} assume !(0 == ~T2_E~0); {107248#false} is VALID [2022-02-21 04:23:38,946 INFO L290 TraceCheckUtils]: 22: Hoare triple {107248#false} assume !(0 == ~T3_E~0); {107248#false} is VALID [2022-02-21 04:23:38,946 INFO L290 TraceCheckUtils]: 23: Hoare triple {107248#false} assume !(0 == ~T4_E~0); {107248#false} is VALID [2022-02-21 04:23:38,946 INFO L290 TraceCheckUtils]: 24: Hoare triple {107248#false} assume !(0 == ~T5_E~0); {107248#false} is VALID [2022-02-21 04:23:38,946 INFO L290 TraceCheckUtils]: 25: Hoare triple {107248#false} assume !(0 == ~T6_E~0); {107248#false} is VALID [2022-02-21 04:23:38,946 INFO L290 TraceCheckUtils]: 26: Hoare triple {107248#false} assume !(0 == ~T7_E~0); {107248#false} is VALID [2022-02-21 04:23:38,947 INFO L290 TraceCheckUtils]: 27: Hoare triple {107248#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {107248#false} is VALID [2022-02-21 04:23:38,947 INFO L290 TraceCheckUtils]: 28: Hoare triple {107248#false} assume !(0 == ~T9_E~0); {107248#false} is VALID [2022-02-21 04:23:38,947 INFO L290 TraceCheckUtils]: 29: Hoare triple {107248#false} assume !(0 == ~T10_E~0); {107248#false} is VALID [2022-02-21 04:23:38,947 INFO L290 TraceCheckUtils]: 30: Hoare triple {107248#false} assume !(0 == ~T11_E~0); {107248#false} is VALID [2022-02-21 04:23:38,947 INFO L290 TraceCheckUtils]: 31: Hoare triple {107248#false} assume !(0 == ~T12_E~0); {107248#false} is VALID [2022-02-21 04:23:38,947 INFO L290 TraceCheckUtils]: 32: Hoare triple {107248#false} assume !(0 == ~T13_E~0); {107248#false} is VALID [2022-02-21 04:23:38,947 INFO L290 TraceCheckUtils]: 33: Hoare triple {107248#false} assume !(0 == ~E_M~0); {107248#false} is VALID [2022-02-21 04:23:38,947 INFO L290 TraceCheckUtils]: 34: Hoare triple {107248#false} assume !(0 == ~E_1~0); {107248#false} is VALID [2022-02-21 04:23:38,947 INFO L290 TraceCheckUtils]: 35: Hoare triple {107248#false} assume 0 == ~E_2~0;~E_2~0 := 1; {107248#false} is VALID [2022-02-21 04:23:38,947 INFO L290 TraceCheckUtils]: 36: Hoare triple {107248#false} assume !(0 == ~E_3~0); {107248#false} is VALID [2022-02-21 04:23:38,948 INFO L290 TraceCheckUtils]: 37: Hoare triple {107248#false} assume !(0 == ~E_4~0); {107248#false} is VALID [2022-02-21 04:23:38,948 INFO L290 TraceCheckUtils]: 38: Hoare triple {107248#false} assume !(0 == ~E_5~0); {107248#false} is VALID [2022-02-21 04:23:38,948 INFO L290 TraceCheckUtils]: 39: Hoare triple {107248#false} assume !(0 == ~E_6~0); {107248#false} is VALID [2022-02-21 04:23:38,948 INFO L290 TraceCheckUtils]: 40: Hoare triple {107248#false} assume !(0 == ~E_7~0); {107248#false} is VALID [2022-02-21 04:23:38,948 INFO L290 TraceCheckUtils]: 41: Hoare triple {107248#false} assume !(0 == ~E_8~0); {107248#false} is VALID [2022-02-21 04:23:38,948 INFO L290 TraceCheckUtils]: 42: Hoare triple {107248#false} assume !(0 == ~E_9~0); {107248#false} is VALID [2022-02-21 04:23:38,948 INFO L290 TraceCheckUtils]: 43: Hoare triple {107248#false} assume 0 == ~E_10~0;~E_10~0 := 1; {107248#false} is VALID [2022-02-21 04:23:38,948 INFO L290 TraceCheckUtils]: 44: Hoare triple {107248#false} assume !(0 == ~E_11~0); {107248#false} is VALID [2022-02-21 04:23:38,949 INFO L290 TraceCheckUtils]: 45: Hoare triple {107248#false} assume !(0 == ~E_12~0); {107248#false} is VALID [2022-02-21 04:23:38,949 INFO L290 TraceCheckUtils]: 46: Hoare triple {107248#false} assume !(0 == ~E_13~0); {107248#false} is VALID [2022-02-21 04:23:38,949 INFO L290 TraceCheckUtils]: 47: Hoare triple {107248#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {107248#false} is VALID [2022-02-21 04:23:38,949 INFO L290 TraceCheckUtils]: 48: Hoare triple {107248#false} assume !(1 == ~m_pc~0); {107248#false} is VALID [2022-02-21 04:23:38,949 INFO L290 TraceCheckUtils]: 49: Hoare triple {107248#false} is_master_triggered_~__retres1~0#1 := 0; {107248#false} is VALID [2022-02-21 04:23:38,949 INFO L290 TraceCheckUtils]: 50: Hoare triple {107248#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {107248#false} is VALID [2022-02-21 04:23:38,949 INFO L290 TraceCheckUtils]: 51: Hoare triple {107248#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {107248#false} is VALID [2022-02-21 04:23:38,950 INFO L290 TraceCheckUtils]: 52: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp~1#1); {107248#false} is VALID [2022-02-21 04:23:38,950 INFO L290 TraceCheckUtils]: 53: Hoare triple {107248#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {107248#false} is VALID [2022-02-21 04:23:38,950 INFO L290 TraceCheckUtils]: 54: Hoare triple {107248#false} assume 1 == ~t1_pc~0; {107248#false} is VALID [2022-02-21 04:23:38,950 INFO L290 TraceCheckUtils]: 55: Hoare triple {107248#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {107248#false} is VALID [2022-02-21 04:23:38,950 INFO L290 TraceCheckUtils]: 56: Hoare triple {107248#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {107248#false} is VALID [2022-02-21 04:23:38,950 INFO L290 TraceCheckUtils]: 57: Hoare triple {107248#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {107248#false} is VALID [2022-02-21 04:23:38,950 INFO L290 TraceCheckUtils]: 58: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___0~0#1); {107248#false} is VALID [2022-02-21 04:23:38,951 INFO L290 TraceCheckUtils]: 59: Hoare triple {107248#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {107248#false} is VALID [2022-02-21 04:23:38,951 INFO L290 TraceCheckUtils]: 60: Hoare triple {107248#false} assume 1 == ~t2_pc~0; {107248#false} is VALID [2022-02-21 04:23:38,951 INFO L290 TraceCheckUtils]: 61: Hoare triple {107248#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {107248#false} is VALID [2022-02-21 04:23:38,951 INFO L290 TraceCheckUtils]: 62: Hoare triple {107248#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {107248#false} is VALID [2022-02-21 04:23:38,951 INFO L290 TraceCheckUtils]: 63: Hoare triple {107248#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {107248#false} is VALID [2022-02-21 04:23:38,951 INFO L290 TraceCheckUtils]: 64: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___1~0#1); {107248#false} is VALID [2022-02-21 04:23:38,951 INFO L290 TraceCheckUtils]: 65: Hoare triple {107248#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {107248#false} is VALID [2022-02-21 04:23:38,952 INFO L290 TraceCheckUtils]: 66: Hoare triple {107248#false} assume !(1 == ~t3_pc~0); {107248#false} is VALID [2022-02-21 04:23:38,952 INFO L290 TraceCheckUtils]: 67: Hoare triple {107248#false} is_transmit3_triggered_~__retres1~3#1 := 0; {107248#false} is VALID [2022-02-21 04:23:38,952 INFO L290 TraceCheckUtils]: 68: Hoare triple {107248#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {107248#false} is VALID [2022-02-21 04:23:38,952 INFO L290 TraceCheckUtils]: 69: Hoare triple {107248#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {107248#false} is VALID [2022-02-21 04:23:38,952 INFO L290 TraceCheckUtils]: 70: Hoare triple {107248#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {107248#false} is VALID [2022-02-21 04:23:38,952 INFO L290 TraceCheckUtils]: 71: Hoare triple {107248#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {107248#false} is VALID [2022-02-21 04:23:38,952 INFO L290 TraceCheckUtils]: 72: Hoare triple {107248#false} assume 1 == ~t4_pc~0; {107248#false} is VALID [2022-02-21 04:23:38,953 INFO L290 TraceCheckUtils]: 73: Hoare triple {107248#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {107248#false} is VALID [2022-02-21 04:23:38,953 INFO L290 TraceCheckUtils]: 74: Hoare triple {107248#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {107248#false} is VALID [2022-02-21 04:23:38,953 INFO L290 TraceCheckUtils]: 75: Hoare triple {107248#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {107248#false} is VALID [2022-02-21 04:23:38,953 INFO L290 TraceCheckUtils]: 76: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___3~0#1); {107248#false} is VALID [2022-02-21 04:23:38,953 INFO L290 TraceCheckUtils]: 77: Hoare triple {107248#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {107248#false} is VALID [2022-02-21 04:23:38,953 INFO L290 TraceCheckUtils]: 78: Hoare triple {107248#false} assume !(1 == ~t5_pc~0); {107248#false} is VALID [2022-02-21 04:23:38,953 INFO L290 TraceCheckUtils]: 79: Hoare triple {107248#false} is_transmit5_triggered_~__retres1~5#1 := 0; {107248#false} is VALID [2022-02-21 04:23:38,954 INFO L290 TraceCheckUtils]: 80: Hoare triple {107248#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {107248#false} is VALID [2022-02-21 04:23:38,954 INFO L290 TraceCheckUtils]: 81: Hoare triple {107248#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {107248#false} is VALID [2022-02-21 04:23:38,954 INFO L290 TraceCheckUtils]: 82: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___4~0#1); {107248#false} is VALID [2022-02-21 04:23:38,954 INFO L290 TraceCheckUtils]: 83: Hoare triple {107248#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {107248#false} is VALID [2022-02-21 04:23:38,954 INFO L290 TraceCheckUtils]: 84: Hoare triple {107248#false} assume 1 == ~t6_pc~0; {107248#false} is VALID [2022-02-21 04:23:38,954 INFO L290 TraceCheckUtils]: 85: Hoare triple {107248#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {107248#false} is VALID [2022-02-21 04:23:38,954 INFO L290 TraceCheckUtils]: 86: Hoare triple {107248#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {107248#false} is VALID [2022-02-21 04:23:38,955 INFO L290 TraceCheckUtils]: 87: Hoare triple {107248#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {107248#false} is VALID [2022-02-21 04:23:38,955 INFO L290 TraceCheckUtils]: 88: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___5~0#1); {107248#false} is VALID [2022-02-21 04:23:38,955 INFO L290 TraceCheckUtils]: 89: Hoare triple {107248#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {107248#false} is VALID [2022-02-21 04:23:38,955 INFO L290 TraceCheckUtils]: 90: Hoare triple {107248#false} assume !(1 == ~t7_pc~0); {107248#false} is VALID [2022-02-21 04:23:38,955 INFO L290 TraceCheckUtils]: 91: Hoare triple {107248#false} is_transmit7_triggered_~__retres1~7#1 := 0; {107248#false} is VALID [2022-02-21 04:23:38,955 INFO L290 TraceCheckUtils]: 92: Hoare triple {107248#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {107248#false} is VALID [2022-02-21 04:23:38,955 INFO L290 TraceCheckUtils]: 93: Hoare triple {107248#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {107248#false} is VALID [2022-02-21 04:23:38,956 INFO L290 TraceCheckUtils]: 94: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___6~0#1); {107248#false} is VALID [2022-02-21 04:23:38,956 INFO L290 TraceCheckUtils]: 95: Hoare triple {107248#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {107248#false} is VALID [2022-02-21 04:23:38,956 INFO L290 TraceCheckUtils]: 96: Hoare triple {107248#false} assume 1 == ~t8_pc~0; {107248#false} is VALID [2022-02-21 04:23:38,956 INFO L290 TraceCheckUtils]: 97: Hoare triple {107248#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {107248#false} is VALID [2022-02-21 04:23:38,956 INFO L290 TraceCheckUtils]: 98: Hoare triple {107248#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {107248#false} is VALID [2022-02-21 04:23:38,956 INFO L290 TraceCheckUtils]: 99: Hoare triple {107248#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {107248#false} is VALID [2022-02-21 04:23:38,956 INFO L290 TraceCheckUtils]: 100: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___7~0#1); {107248#false} is VALID [2022-02-21 04:23:38,957 INFO L290 TraceCheckUtils]: 101: Hoare triple {107248#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {107248#false} is VALID [2022-02-21 04:23:38,957 INFO L290 TraceCheckUtils]: 102: Hoare triple {107248#false} assume 1 == ~t9_pc~0; {107248#false} is VALID [2022-02-21 04:23:38,957 INFO L290 TraceCheckUtils]: 103: Hoare triple {107248#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {107248#false} is VALID [2022-02-21 04:23:38,957 INFO L290 TraceCheckUtils]: 104: Hoare triple {107248#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {107248#false} is VALID [2022-02-21 04:23:38,957 INFO L290 TraceCheckUtils]: 105: Hoare triple {107248#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {107248#false} is VALID [2022-02-21 04:23:38,957 INFO L290 TraceCheckUtils]: 106: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___8~0#1); {107248#false} is VALID [2022-02-21 04:23:38,957 INFO L290 TraceCheckUtils]: 107: Hoare triple {107248#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {107248#false} is VALID [2022-02-21 04:23:38,958 INFO L290 TraceCheckUtils]: 108: Hoare triple {107248#false} assume !(1 == ~t10_pc~0); {107248#false} is VALID [2022-02-21 04:23:38,958 INFO L290 TraceCheckUtils]: 109: Hoare triple {107248#false} is_transmit10_triggered_~__retres1~10#1 := 0; {107248#false} is VALID [2022-02-21 04:23:38,958 INFO L290 TraceCheckUtils]: 110: Hoare triple {107248#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {107248#false} is VALID [2022-02-21 04:23:38,958 INFO L290 TraceCheckUtils]: 111: Hoare triple {107248#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {107248#false} is VALID [2022-02-21 04:23:38,958 INFO L290 TraceCheckUtils]: 112: Hoare triple {107248#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {107248#false} is VALID [2022-02-21 04:23:38,958 INFO L290 TraceCheckUtils]: 113: Hoare triple {107248#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {107248#false} is VALID [2022-02-21 04:23:38,958 INFO L290 TraceCheckUtils]: 114: Hoare triple {107248#false} assume 1 == ~t11_pc~0; {107248#false} is VALID [2022-02-21 04:23:38,959 INFO L290 TraceCheckUtils]: 115: Hoare triple {107248#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {107248#false} is VALID [2022-02-21 04:23:38,959 INFO L290 TraceCheckUtils]: 116: Hoare triple {107248#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {107248#false} is VALID [2022-02-21 04:23:38,959 INFO L290 TraceCheckUtils]: 117: Hoare triple {107248#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {107248#false} is VALID [2022-02-21 04:23:38,959 INFO L290 TraceCheckUtils]: 118: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___10~0#1); {107248#false} is VALID [2022-02-21 04:23:38,959 INFO L290 TraceCheckUtils]: 119: Hoare triple {107248#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {107248#false} is VALID [2022-02-21 04:23:38,959 INFO L290 TraceCheckUtils]: 120: Hoare triple {107248#false} assume !(1 == ~t12_pc~0); {107248#false} is VALID [2022-02-21 04:23:38,959 INFO L290 TraceCheckUtils]: 121: Hoare triple {107248#false} is_transmit12_triggered_~__retres1~12#1 := 0; {107248#false} is VALID [2022-02-21 04:23:38,960 INFO L290 TraceCheckUtils]: 122: Hoare triple {107248#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {107248#false} is VALID [2022-02-21 04:23:38,960 INFO L290 TraceCheckUtils]: 123: Hoare triple {107248#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {107248#false} is VALID [2022-02-21 04:23:38,960 INFO L290 TraceCheckUtils]: 124: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___11~0#1); {107248#false} is VALID [2022-02-21 04:23:38,960 INFO L290 TraceCheckUtils]: 125: Hoare triple {107248#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {107248#false} is VALID [2022-02-21 04:23:38,960 INFO L290 TraceCheckUtils]: 126: Hoare triple {107248#false} assume 1 == ~t13_pc~0; {107248#false} is VALID [2022-02-21 04:23:38,960 INFO L290 TraceCheckUtils]: 127: Hoare triple {107248#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {107248#false} is VALID [2022-02-21 04:23:38,960 INFO L290 TraceCheckUtils]: 128: Hoare triple {107248#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {107248#false} is VALID [2022-02-21 04:23:38,961 INFO L290 TraceCheckUtils]: 129: Hoare triple {107248#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {107248#false} is VALID [2022-02-21 04:23:38,961 INFO L290 TraceCheckUtils]: 130: Hoare triple {107248#false} assume !(0 != activate_threads_~tmp___12~0#1); {107248#false} is VALID [2022-02-21 04:23:38,961 INFO L290 TraceCheckUtils]: 131: Hoare triple {107248#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {107248#false} is VALID [2022-02-21 04:23:38,961 INFO L290 TraceCheckUtils]: 132: Hoare triple {107248#false} assume !(1 == ~M_E~0); {107248#false} is VALID [2022-02-21 04:23:38,961 INFO L290 TraceCheckUtils]: 133: Hoare triple {107248#false} assume !(1 == ~T1_E~0); {107248#false} is VALID [2022-02-21 04:23:38,961 INFO L290 TraceCheckUtils]: 134: Hoare triple {107248#false} assume !(1 == ~T2_E~0); {107248#false} is VALID [2022-02-21 04:23:38,961 INFO L290 TraceCheckUtils]: 135: Hoare triple {107248#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {107248#false} is VALID [2022-02-21 04:23:38,962 INFO L290 TraceCheckUtils]: 136: Hoare triple {107248#false} assume !(1 == ~T4_E~0); {107248#false} is VALID [2022-02-21 04:23:38,962 INFO L290 TraceCheckUtils]: 137: Hoare triple {107248#false} assume !(1 == ~T5_E~0); {107248#false} is VALID [2022-02-21 04:23:38,962 INFO L290 TraceCheckUtils]: 138: Hoare triple {107248#false} assume !(1 == ~T6_E~0); {107248#false} is VALID [2022-02-21 04:23:38,962 INFO L290 TraceCheckUtils]: 139: Hoare triple {107248#false} assume !(1 == ~T7_E~0); {107248#false} is VALID [2022-02-21 04:23:38,962 INFO L290 TraceCheckUtils]: 140: Hoare triple {107248#false} assume !(1 == ~T8_E~0); {107248#false} is VALID [2022-02-21 04:23:38,962 INFO L290 TraceCheckUtils]: 141: Hoare triple {107248#false} assume !(1 == ~T9_E~0); {107248#false} is VALID [2022-02-21 04:23:38,962 INFO L290 TraceCheckUtils]: 142: Hoare triple {107248#false} assume !(1 == ~T10_E~0); {107248#false} is VALID [2022-02-21 04:23:38,963 INFO L290 TraceCheckUtils]: 143: Hoare triple {107248#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {107248#false} is VALID [2022-02-21 04:23:38,963 INFO L290 TraceCheckUtils]: 144: Hoare triple {107248#false} assume !(1 == ~T12_E~0); {107248#false} is VALID [2022-02-21 04:23:38,963 INFO L290 TraceCheckUtils]: 145: Hoare triple {107248#false} assume !(1 == ~T13_E~0); {107248#false} is VALID [2022-02-21 04:23:38,963 INFO L290 TraceCheckUtils]: 146: Hoare triple {107248#false} assume !(1 == ~E_M~0); {107248#false} is VALID [2022-02-21 04:23:38,963 INFO L290 TraceCheckUtils]: 147: Hoare triple {107248#false} assume !(1 == ~E_1~0); {107248#false} is VALID [2022-02-21 04:23:38,963 INFO L290 TraceCheckUtils]: 148: Hoare triple {107248#false} assume !(1 == ~E_2~0); {107248#false} is VALID [2022-02-21 04:23:38,963 INFO L290 TraceCheckUtils]: 149: Hoare triple {107248#false} assume !(1 == ~E_3~0); {107248#false} is VALID [2022-02-21 04:23:38,964 INFO L290 TraceCheckUtils]: 150: Hoare triple {107248#false} assume !(1 == ~E_4~0); {107248#false} is VALID [2022-02-21 04:23:38,964 INFO L290 TraceCheckUtils]: 151: Hoare triple {107248#false} assume 1 == ~E_5~0;~E_5~0 := 2; {107248#false} is VALID [2022-02-21 04:23:38,964 INFO L290 TraceCheckUtils]: 152: Hoare triple {107248#false} assume !(1 == ~E_6~0); {107248#false} is VALID [2022-02-21 04:23:38,964 INFO L290 TraceCheckUtils]: 153: Hoare triple {107248#false} assume !(1 == ~E_7~0); {107248#false} is VALID [2022-02-21 04:23:38,964 INFO L290 TraceCheckUtils]: 154: Hoare triple {107248#false} assume !(1 == ~E_8~0); {107248#false} is VALID [2022-02-21 04:23:38,964 INFO L290 TraceCheckUtils]: 155: Hoare triple {107248#false} assume !(1 == ~E_9~0); {107248#false} is VALID [2022-02-21 04:23:38,964 INFO L290 TraceCheckUtils]: 156: Hoare triple {107248#false} assume !(1 == ~E_10~0); {107248#false} is VALID [2022-02-21 04:23:38,964 INFO L290 TraceCheckUtils]: 157: Hoare triple {107248#false} assume !(1 == ~E_11~0); {107248#false} is VALID [2022-02-21 04:23:38,965 INFO L290 TraceCheckUtils]: 158: Hoare triple {107248#false} assume !(1 == ~E_12~0); {107248#false} is VALID [2022-02-21 04:23:38,965 INFO L290 TraceCheckUtils]: 159: Hoare triple {107248#false} assume 1 == ~E_13~0;~E_13~0 := 2; {107248#false} is VALID [2022-02-21 04:23:38,965 INFO L290 TraceCheckUtils]: 160: Hoare triple {107248#false} assume { :end_inline_reset_delta_events } true; {107248#false} is VALID [2022-02-21 04:23:38,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:38,966 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:38,966 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782199166] [2022-02-21 04:23:38,966 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1782199166] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:38,966 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:38,966 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:38,966 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031799575] [2022-02-21 04:23:38,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:38,968 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:38,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:38,968 INFO L85 PathProgramCache]: Analyzing trace with hash 1360805736, now seen corresponding path program 1 times [2022-02-21 04:23:38,968 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:38,969 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646560885] [2022-02-21 04:23:38,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:38,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:38,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:38,996 INFO L290 TraceCheckUtils]: 0: Hoare triple {107250#true} assume !false; {107250#true} is VALID [2022-02-21 04:23:38,996 INFO L290 TraceCheckUtils]: 1: Hoare triple {107250#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {107250#true} is VALID [2022-02-21 04:23:38,997 INFO L290 TraceCheckUtils]: 2: Hoare triple {107250#true} assume !false; {107250#true} is VALID [2022-02-21 04:23:38,997 INFO L290 TraceCheckUtils]: 3: Hoare triple {107250#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {107250#true} is VALID [2022-02-21 04:23:38,997 INFO L290 TraceCheckUtils]: 4: Hoare triple {107250#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {107250#true} is VALID [2022-02-21 04:23:38,997 INFO L290 TraceCheckUtils]: 5: Hoare triple {107250#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {107250#true} is VALID [2022-02-21 04:23:38,997 INFO L290 TraceCheckUtils]: 6: Hoare triple {107250#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {107250#true} is VALID [2022-02-21 04:23:38,997 INFO L290 TraceCheckUtils]: 7: Hoare triple {107250#true} assume !(0 != eval_~tmp~0#1); {107250#true} is VALID [2022-02-21 04:23:38,997 INFO L290 TraceCheckUtils]: 8: Hoare triple {107250#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {107250#true} is VALID [2022-02-21 04:23:38,998 INFO L290 TraceCheckUtils]: 9: Hoare triple {107250#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {107250#true} is VALID [2022-02-21 04:23:38,998 INFO L290 TraceCheckUtils]: 10: Hoare triple {107250#true} assume 0 == ~M_E~0;~M_E~0 := 1; {107250#true} is VALID [2022-02-21 04:23:38,998 INFO L290 TraceCheckUtils]: 11: Hoare triple {107250#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {107250#true} is VALID [2022-02-21 04:23:38,998 INFO L290 TraceCheckUtils]: 12: Hoare triple {107250#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {107250#true} is VALID [2022-02-21 04:23:38,998 INFO L290 TraceCheckUtils]: 13: Hoare triple {107250#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {107250#true} is VALID [2022-02-21 04:23:38,998 INFO L290 TraceCheckUtils]: 14: Hoare triple {107250#true} assume !(0 == ~T4_E~0); {107250#true} is VALID [2022-02-21 04:23:38,998 INFO L290 TraceCheckUtils]: 15: Hoare triple {107250#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {107250#true} is VALID [2022-02-21 04:23:38,999 INFO L290 TraceCheckUtils]: 16: Hoare triple {107250#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {107250#true} is VALID [2022-02-21 04:23:38,999 INFO L290 TraceCheckUtils]: 17: Hoare triple {107250#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:38,999 INFO L290 TraceCheckUtils]: 18: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,000 INFO L290 TraceCheckUtils]: 19: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,000 INFO L290 TraceCheckUtils]: 20: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,000 INFO L290 TraceCheckUtils]: 21: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,001 INFO L290 TraceCheckUtils]: 22: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,001 INFO L290 TraceCheckUtils]: 23: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,001 INFO L290 TraceCheckUtils]: 24: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,001 INFO L290 TraceCheckUtils]: 25: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,002 INFO L290 TraceCheckUtils]: 26: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,002 INFO L290 TraceCheckUtils]: 27: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,002 INFO L290 TraceCheckUtils]: 28: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,003 INFO L290 TraceCheckUtils]: 29: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,003 INFO L290 TraceCheckUtils]: 30: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,003 INFO L290 TraceCheckUtils]: 31: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,004 INFO L290 TraceCheckUtils]: 32: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,004 INFO L290 TraceCheckUtils]: 33: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,004 INFO L290 TraceCheckUtils]: 34: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,004 INFO L290 TraceCheckUtils]: 35: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,005 INFO L290 TraceCheckUtils]: 36: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,005 INFO L290 TraceCheckUtils]: 37: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,005 INFO L290 TraceCheckUtils]: 38: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,006 INFO L290 TraceCheckUtils]: 39: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,006 INFO L290 TraceCheckUtils]: 40: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,006 INFO L290 TraceCheckUtils]: 41: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,006 INFO L290 TraceCheckUtils]: 42: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,007 INFO L290 TraceCheckUtils]: 43: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,007 INFO L290 TraceCheckUtils]: 44: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,007 INFO L290 TraceCheckUtils]: 45: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t1_pc~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,008 INFO L290 TraceCheckUtils]: 46: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,008 INFO L290 TraceCheckUtils]: 47: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,008 INFO L290 TraceCheckUtils]: 48: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,009 INFO L290 TraceCheckUtils]: 49: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,009 INFO L290 TraceCheckUtils]: 50: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,009 INFO L290 TraceCheckUtils]: 51: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,009 INFO L290 TraceCheckUtils]: 52: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,010 INFO L290 TraceCheckUtils]: 53: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,010 INFO L290 TraceCheckUtils]: 54: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,010 INFO L290 TraceCheckUtils]: 55: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,011 INFO L290 TraceCheckUtils]: 56: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,011 INFO L290 TraceCheckUtils]: 57: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,011 INFO L290 TraceCheckUtils]: 58: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,011 INFO L290 TraceCheckUtils]: 59: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,012 INFO L290 TraceCheckUtils]: 60: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,012 INFO L290 TraceCheckUtils]: 61: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,012 INFO L290 TraceCheckUtils]: 62: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,013 INFO L290 TraceCheckUtils]: 63: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t4_pc~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,013 INFO L290 TraceCheckUtils]: 64: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,013 INFO L290 TraceCheckUtils]: 65: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,014 INFO L290 TraceCheckUtils]: 66: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,014 INFO L290 TraceCheckUtils]: 67: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,014 INFO L290 TraceCheckUtils]: 68: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,014 INFO L290 TraceCheckUtils]: 69: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,015 INFO L290 TraceCheckUtils]: 70: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,015 INFO L290 TraceCheckUtils]: 71: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,015 INFO L290 TraceCheckUtils]: 72: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,016 INFO L290 TraceCheckUtils]: 73: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,016 INFO L290 TraceCheckUtils]: 74: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,016 INFO L290 TraceCheckUtils]: 75: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,016 INFO L290 TraceCheckUtils]: 76: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,017 INFO L290 TraceCheckUtils]: 77: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,017 INFO L290 TraceCheckUtils]: 78: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,017 INFO L290 TraceCheckUtils]: 79: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,018 INFO L290 TraceCheckUtils]: 80: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,018 INFO L290 TraceCheckUtils]: 81: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,018 INFO L290 TraceCheckUtils]: 82: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,019 INFO L290 TraceCheckUtils]: 83: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,019 INFO L290 TraceCheckUtils]: 84: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,019 INFO L290 TraceCheckUtils]: 85: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,019 INFO L290 TraceCheckUtils]: 86: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,020 INFO L290 TraceCheckUtils]: 87: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t8_pc~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,020 INFO L290 TraceCheckUtils]: 88: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,020 INFO L290 TraceCheckUtils]: 89: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,021 INFO L290 TraceCheckUtils]: 90: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,021 INFO L290 TraceCheckUtils]: 91: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,021 INFO L290 TraceCheckUtils]: 92: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,022 INFO L290 TraceCheckUtils]: 93: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,022 INFO L290 TraceCheckUtils]: 94: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,022 INFO L290 TraceCheckUtils]: 95: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,022 INFO L290 TraceCheckUtils]: 96: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,023 INFO L290 TraceCheckUtils]: 97: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,023 INFO L290 TraceCheckUtils]: 98: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,023 INFO L290 TraceCheckUtils]: 99: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t10_pc~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,024 INFO L290 TraceCheckUtils]: 100: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,024 INFO L290 TraceCheckUtils]: 101: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,024 INFO L290 TraceCheckUtils]: 102: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,024 INFO L290 TraceCheckUtils]: 103: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,025 INFO L290 TraceCheckUtils]: 104: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,025 INFO L290 TraceCheckUtils]: 105: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,025 INFO L290 TraceCheckUtils]: 106: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,026 INFO L290 TraceCheckUtils]: 107: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,026 INFO L290 TraceCheckUtils]: 108: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,026 INFO L290 TraceCheckUtils]: 109: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,026 INFO L290 TraceCheckUtils]: 110: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,027 INFO L290 TraceCheckUtils]: 111: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t12_pc~0); {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,027 INFO L290 TraceCheckUtils]: 112: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,027 INFO L290 TraceCheckUtils]: 113: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,028 INFO L290 TraceCheckUtils]: 114: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,028 INFO L290 TraceCheckUtils]: 115: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,028 INFO L290 TraceCheckUtils]: 116: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,029 INFO L290 TraceCheckUtils]: 117: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t13_pc~0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,029 INFO L290 TraceCheckUtils]: 118: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,029 INFO L290 TraceCheckUtils]: 119: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,029 INFO L290 TraceCheckUtils]: 120: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,030 INFO L290 TraceCheckUtils]: 121: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,030 INFO L290 TraceCheckUtils]: 122: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,030 INFO L290 TraceCheckUtils]: 123: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,031 INFO L290 TraceCheckUtils]: 124: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,031 INFO L290 TraceCheckUtils]: 125: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,031 INFO L290 TraceCheckUtils]: 126: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,031 INFO L290 TraceCheckUtils]: 127: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,032 INFO L290 TraceCheckUtils]: 128: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,032 INFO L290 TraceCheckUtils]: 129: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {107252#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:39,032 INFO L290 TraceCheckUtils]: 130: Hoare triple {107252#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {107251#false} is VALID [2022-02-21 04:23:39,032 INFO L290 TraceCheckUtils]: 131: Hoare triple {107251#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,033 INFO L290 TraceCheckUtils]: 132: Hoare triple {107251#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,033 INFO L290 TraceCheckUtils]: 133: Hoare triple {107251#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,033 INFO L290 TraceCheckUtils]: 134: Hoare triple {107251#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,033 INFO L290 TraceCheckUtils]: 135: Hoare triple {107251#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,033 INFO L290 TraceCheckUtils]: 136: Hoare triple {107251#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,033 INFO L290 TraceCheckUtils]: 137: Hoare triple {107251#false} assume 1 == ~E_M~0;~E_M~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,033 INFO L290 TraceCheckUtils]: 138: Hoare triple {107251#false} assume !(1 == ~E_1~0); {107251#false} is VALID [2022-02-21 04:23:39,034 INFO L290 TraceCheckUtils]: 139: Hoare triple {107251#false} assume 1 == ~E_2~0;~E_2~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,034 INFO L290 TraceCheckUtils]: 140: Hoare triple {107251#false} assume 1 == ~E_3~0;~E_3~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,034 INFO L290 TraceCheckUtils]: 141: Hoare triple {107251#false} assume 1 == ~E_4~0;~E_4~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,034 INFO L290 TraceCheckUtils]: 142: Hoare triple {107251#false} assume 1 == ~E_5~0;~E_5~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,034 INFO L290 TraceCheckUtils]: 143: Hoare triple {107251#false} assume 1 == ~E_6~0;~E_6~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,034 INFO L290 TraceCheckUtils]: 144: Hoare triple {107251#false} assume 1 == ~E_7~0;~E_7~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,034 INFO L290 TraceCheckUtils]: 145: Hoare triple {107251#false} assume 1 == ~E_8~0;~E_8~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,035 INFO L290 TraceCheckUtils]: 146: Hoare triple {107251#false} assume !(1 == ~E_9~0); {107251#false} is VALID [2022-02-21 04:23:39,035 INFO L290 TraceCheckUtils]: 147: Hoare triple {107251#false} assume 1 == ~E_10~0;~E_10~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,035 INFO L290 TraceCheckUtils]: 148: Hoare triple {107251#false} assume 1 == ~E_11~0;~E_11~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,035 INFO L290 TraceCheckUtils]: 149: Hoare triple {107251#false} assume 1 == ~E_12~0;~E_12~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,035 INFO L290 TraceCheckUtils]: 150: Hoare triple {107251#false} assume 1 == ~E_13~0;~E_13~0 := 2; {107251#false} is VALID [2022-02-21 04:23:39,035 INFO L290 TraceCheckUtils]: 151: Hoare triple {107251#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {107251#false} is VALID [2022-02-21 04:23:39,035 INFO L290 TraceCheckUtils]: 152: Hoare triple {107251#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {107251#false} is VALID [2022-02-21 04:23:39,036 INFO L290 TraceCheckUtils]: 153: Hoare triple {107251#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {107251#false} is VALID [2022-02-21 04:23:39,036 INFO L290 TraceCheckUtils]: 154: Hoare triple {107251#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {107251#false} is VALID [2022-02-21 04:23:39,036 INFO L290 TraceCheckUtils]: 155: Hoare triple {107251#false} assume !(0 == start_simulation_~tmp~3#1); {107251#false} is VALID [2022-02-21 04:23:39,036 INFO L290 TraceCheckUtils]: 156: Hoare triple {107251#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {107251#false} is VALID [2022-02-21 04:23:39,036 INFO L290 TraceCheckUtils]: 157: Hoare triple {107251#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {107251#false} is VALID [2022-02-21 04:23:39,036 INFO L290 TraceCheckUtils]: 158: Hoare triple {107251#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {107251#false} is VALID [2022-02-21 04:23:39,037 INFO L290 TraceCheckUtils]: 159: Hoare triple {107251#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {107251#false} is VALID [2022-02-21 04:23:39,037 INFO L290 TraceCheckUtils]: 160: Hoare triple {107251#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {107251#false} is VALID [2022-02-21 04:23:39,037 INFO L290 TraceCheckUtils]: 161: Hoare triple {107251#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {107251#false} is VALID [2022-02-21 04:23:39,037 INFO L290 TraceCheckUtils]: 162: Hoare triple {107251#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {107251#false} is VALID [2022-02-21 04:23:39,037 INFO L290 TraceCheckUtils]: 163: Hoare triple {107251#false} assume !(0 != start_simulation_~tmp___0~1#1); {107251#false} is VALID [2022-02-21 04:23:39,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:39,038 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:39,038 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646560885] [2022-02-21 04:23:39,038 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646560885] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:39,038 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:39,038 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:39,039 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799265315] [2022-02-21 04:23:39,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:39,039 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:39,039 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:39,039 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:39,040 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:39,040 INFO L87 Difference]: Start difference. First operand 2021 states and 2980 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:41,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:41,421 INFO L93 Difference]: Finished difference Result 3767 states and 5538 transitions. [2022-02-21 04:23:41,421 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:41,421 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:41,516 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:41,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3767 states and 5538 transitions. [2022-02-21 04:23:41,830 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2022-02-21 04:23:42,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3767 states to 3767 states and 5538 transitions. [2022-02-21 04:23:42,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3767 [2022-02-21 04:23:42,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3767 [2022-02-21 04:23:42,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3767 states and 5538 transitions. [2022-02-21 04:23:42,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:42,146 INFO L681 BuchiCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2022-02-21 04:23:42,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3767 states and 5538 transitions. [2022-02-21 04:23:42,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3767 to 3767. [2022-02-21 04:23:42,186 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:42,189 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3767 states and 5538 transitions. Second operand has 3767 states, 3767 states have (on average 1.4701353862490045) internal successors, (5538), 3766 states have internal predecessors, (5538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:42,192 INFO L74 IsIncluded]: Start isIncluded. First operand 3767 states and 5538 transitions. Second operand has 3767 states, 3767 states have (on average 1.4701353862490045) internal successors, (5538), 3766 states have internal predecessors, (5538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:42,194 INFO L87 Difference]: Start difference. First operand 3767 states and 5538 transitions. Second operand has 3767 states, 3767 states have (on average 1.4701353862490045) internal successors, (5538), 3766 states have internal predecessors, (5538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:42,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:42,509 INFO L93 Difference]: Finished difference Result 3767 states and 5538 transitions. [2022-02-21 04:23:42,509 INFO L276 IsEmpty]: Start isEmpty. Operand 3767 states and 5538 transitions. [2022-02-21 04:23:42,512 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:42,512 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:42,516 INFO L74 IsIncluded]: Start isIncluded. First operand has 3767 states, 3767 states have (on average 1.4701353862490045) internal successors, (5538), 3766 states have internal predecessors, (5538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3767 states and 5538 transitions. [2022-02-21 04:23:42,518 INFO L87 Difference]: Start difference. First operand has 3767 states, 3767 states have (on average 1.4701353862490045) internal successors, (5538), 3766 states have internal predecessors, (5538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3767 states and 5538 transitions. [2022-02-21 04:23:42,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:42,804 INFO L93 Difference]: Finished difference Result 3767 states and 5538 transitions. [2022-02-21 04:23:42,804 INFO L276 IsEmpty]: Start isEmpty. Operand 3767 states and 5538 transitions. [2022-02-21 04:23:42,808 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:42,808 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:42,808 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:42,808 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:42,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3767 states, 3767 states have (on average 1.4701353862490045) internal successors, (5538), 3766 states have internal predecessors, (5538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:43,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3767 states to 3767 states and 5538 transitions. [2022-02-21 04:23:43,114 INFO L704 BuchiCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2022-02-21 04:23:43,114 INFO L587 BuchiCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2022-02-21 04:23:43,114 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:23:43,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3767 states and 5538 transitions. [2022-02-21 04:23:43,119 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2022-02-21 04:23:43,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:43,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:43,121 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:43,121 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:43,121 INFO L791 eck$LassoCheckResult]: Stem: 111898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 111899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 111630#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111631#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 113098#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 113099#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111817#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111818#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111852#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112698#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112699#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 112818#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 112819#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 111636#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 111637#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 112858#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 112162#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 112163#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 112754#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 113083#L1286 assume !(0 == ~M_E~0); 112924#L1286-2 assume !(0 == ~T1_E~0); 111543#L1291-1 assume !(0 == ~T2_E~0); 111544#L1296-1 assume !(0 == ~T3_E~0); 112253#L1301-1 assume !(0 == ~T4_E~0); 112254#L1306-1 assume !(0 == ~T5_E~0); 112765#L1311-1 assume !(0 == ~T6_E~0); 111503#L1316-1 assume !(0 == ~T7_E~0); 111504#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 112273#L1326-1 assume !(0 == ~T9_E~0); 111318#L1331-1 assume !(0 == ~T10_E~0); 111024#L1336-1 assume !(0 == ~T11_E~0); 111025#L1341-1 assume !(0 == ~T12_E~0); 111076#L1346-1 assume !(0 == ~T13_E~0); 111077#L1351-1 assume !(0 == ~E_M~0); 111450#L1356-1 assume !(0 == ~E_1~0); 111451#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 113027#L1366-1 assume !(0 == ~E_3~0); 111496#L1371-1 assume !(0 == ~E_4~0); 111497#L1376-1 assume !(0 == ~E_5~0); 112315#L1381-1 assume !(0 == ~E_6~0); 112316#L1386-1 assume !(0 == ~E_7~0); 113071#L1391-1 assume !(0 == ~E_8~0); 113089#L1396-1 assume !(0 == ~E_9~0); 112196#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 112197#L1406-1 assume !(0 == ~E_11~0); 112504#L1411-1 assume !(0 == ~E_12~0); 112505#L1416-1 assume !(0 == ~E_13~0); 112120#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111957#L635 assume !(1 == ~m_pc~0); 111094#L635-2 is_master_triggered_~__retres1~0#1 := 0; 111095#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111445#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112083#L1598 assume !(0 != activate_threads_~tmp~1#1); 111273#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111274#L654 assume 1 == ~t1_pc~0; 111981#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 111982#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 113064#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112063#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 112064#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111321#L673 assume 1 == ~t2_pc~0; 111322#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 112472#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112473#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 113105#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 113115#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112143#L692 assume !(1 == ~t3_pc~0); 111959#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 111960#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111819#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 111787#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 111788#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111346#L711 assume 1 == ~t4_pc~0; 111347#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 111832#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112292#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 111049#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 111050#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 113097#L730 assume !(1 == ~t5_pc~0); 112406#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 111228#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111229#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 111356#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 111357#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 111701#L749 assume 1 == ~t6_pc~0; 111473#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111233#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111667#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111668#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 111890#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 111029#L768 assume !(1 == ~t7_pc~0); 111030#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 112339#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 111266#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 111267#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 112358#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 111505#L787 assume 1 == ~t8_pc~0; 111506#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 112713#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112889#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 112890#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 111074#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 111075#L806 assume 1 == ~t9_pc~0; 112724#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 111109#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111110#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111358#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 111359#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 112707#L825 assume !(1 == ~t10_pc~0); 112708#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 112306#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112307#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111446#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111447#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112032#L844 assume 1 == ~t11_pc~0; 111722#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 111723#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112089#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 112090#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 112694#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 112695#L863 assume !(1 == ~t12_pc~0); 111209#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 111208#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 111436#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 112791#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 112792#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 112157#L882 assume 1 == ~t13_pc~0; 112158#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 112445#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 112978#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 112756#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 112432#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112433#L1434 assume !(1 == ~M_E~0); 112991#L1434-2 assume !(1 == ~T1_E~0); 113104#L1439-1 assume !(1 == ~T2_E~0); 111339#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111340#L1449-1 assume !(1 == ~T4_E~0); 111784#L1454-1 assume !(1 == ~T5_E~0); 111785#L1459-1 assume !(1 == ~T6_E~0); 112359#L1464-1 assume !(1 == ~T7_E~0); 112360#L1469-1 assume !(1 == ~T8_E~0); 112446#L1474-1 assume !(1 == ~T9_E~0); 112121#L1479-1 assume !(1 == ~T10_E~0); 112122#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 112367#L1489-1 assume !(1 == ~T12_E~0); 111998#L1494-1 assume !(1 == ~T13_E~0); 111999#L1499-1 assume !(1 == ~E_M~0); 112181#L1504-1 assume !(1 == ~E_1~0); 112182#L1509-1 assume !(1 == ~E_2~0); 112810#L1514-1 assume !(1 == ~E_3~0); 112483#L1519-1 assume !(1 == ~E_4~0); 112484#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 113044#L1529-1 assume !(1 == ~E_6~0); 113045#L1534-1 assume !(1 == ~E_7~0); 111129#L1539-1 assume !(1 == ~E_8~0); 111130#L1544-1 assume !(1 == ~E_9~0); 111562#L1549-1 assume !(1 == ~E_10~0); 113006#L1554-1 assume !(1 == ~E_11~0); 113004#L1559-1 assume !(1 == ~E_12~0); 112840#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 112841#L1569-1 assume { :end_inline_reset_delta_events } true; 113035#L1935-2 [2022-02-21 04:23:43,122 INFO L793 eck$LassoCheckResult]: Loop: 113035#L1935-2 assume !false; 111138#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 111139#L1261 assume !false; 112372#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 112373#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 111269#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 111439#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 111440#L1074 assume !(0 != eval_~tmp~0#1); 111799#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112401#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 112814#L1286-3 assume !(0 == ~M_E~0); 112875#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 114658#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 114657#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 114656#L1301-3 assume !(0 == ~T4_E~0); 114655#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 114654#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 114653#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 114652#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 114651#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 114650#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 114649#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 114648#L1341-3 assume !(0 == ~T12_E~0); 114647#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 114646#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 114645#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 114644#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 114643#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 114642#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 114641#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 114640#L1381-3 assume !(0 == ~E_6~0); 114639#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 114638#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 114637#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 114636#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 114635#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 114634#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 114633#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 114632#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114631#L635-45 assume 1 == ~m_pc~0; 114629#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 114628#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114627#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 114626#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 114625#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114624#L654-45 assume 1 == ~t1_pc~0; 114623#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 114621#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114620#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 114619#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 114618#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114617#L673-45 assume 1 == ~t2_pc~0; 114615#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 114614#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114613#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 114612#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 114611#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114610#L692-45 assume !(1 == ~t3_pc~0); 114609#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 114607#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114606#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 114605#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 114604#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114603#L711-45 assume 1 == ~t4_pc~0; 114601#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 114600#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114599#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114598#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 114597#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114596#L730-45 assume !(1 == ~t5_pc~0); 114595#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 114593#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114592#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 114591#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 114590#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114589#L749-45 assume !(1 == ~t6_pc~0); 114587#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 114586#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 114585#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 114371#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 114309#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 114308#L768-45 assume !(1 == ~t7_pc~0); 114307#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 114305#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 114304#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 114303#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 114302#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 114301#L787-45 assume !(1 == ~t8_pc~0); 114299#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 114298#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 114297#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 114296#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 114295#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 114294#L806-45 assume !(1 == ~t9_pc~0); 114293#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 114291#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 114290#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 114289#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 114288#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 114287#L825-45 assume !(1 == ~t10_pc~0); 114285#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 114284#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 114283#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 114282#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 114281#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 114280#L844-45 assume !(1 == ~t11_pc~0); 114279#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 114277#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 114276#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 114275#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 114274#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 114273#L863-45 assume !(1 == ~t12_pc~0); 114272#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 114270#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 112912#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 111538#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 111539#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 112343#L882-45 assume 1 == ~t13_pc~0; 112703#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 111041#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 111042#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 111652#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 112850#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112451#L1434-3 assume !(1 == ~M_E~0); 112452#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 112638#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 111335#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111336#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 111498#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 112441#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 112442#L1464-3 assume !(1 == ~T7_E~0); 112907#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 112828#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 112829#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 112909#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 112078#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 112079#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 112750#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 112378#L1504-3 assume !(1 == ~E_1~0); 112379#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 112838#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112881#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 112001#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 112002#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 112932#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 112305#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 111756#L1544-3 assume !(1 == ~E_9~0); 111757#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 112274#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 111386#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 111387#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 112544#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 112545#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 111271#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 111838#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 112515#L1954 assume !(0 == start_simulation_~tmp~3#1); 112517#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 112774#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 111556#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 112603#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 112737#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 112738#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112835#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 112902#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 113035#L1935-2 [2022-02-21 04:23:43,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:43,122 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2022-02-21 04:23:43,122 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:43,123 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212219061] [2022-02-21 04:23:43,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:43,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:43,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:43,148 INFO L290 TraceCheckUtils]: 0: Hoare triple {122324#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,149 INFO L290 TraceCheckUtils]: 1: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,149 INFO L290 TraceCheckUtils]: 2: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,149 INFO L290 TraceCheckUtils]: 3: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,150 INFO L290 TraceCheckUtils]: 4: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,150 INFO L290 TraceCheckUtils]: 5: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,150 INFO L290 TraceCheckUtils]: 6: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,150 INFO L290 TraceCheckUtils]: 7: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,151 INFO L290 TraceCheckUtils]: 8: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,151 INFO L290 TraceCheckUtils]: 9: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,151 INFO L290 TraceCheckUtils]: 10: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,152 INFO L290 TraceCheckUtils]: 11: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,152 INFO L290 TraceCheckUtils]: 12: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,152 INFO L290 TraceCheckUtils]: 13: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,152 INFO L290 TraceCheckUtils]: 14: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,153 INFO L290 TraceCheckUtils]: 15: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,153 INFO L290 TraceCheckUtils]: 16: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,153 INFO L290 TraceCheckUtils]: 17: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,154 INFO L290 TraceCheckUtils]: 18: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,154 INFO L290 TraceCheckUtils]: 19: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume !(0 == ~M_E~0); {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,154 INFO L290 TraceCheckUtils]: 20: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume !(0 == ~T1_E~0); {122326#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:23:43,154 INFO L290 TraceCheckUtils]: 21: Hoare triple {122326#(= ~T2_E~0 ~T8_E~0)} assume !(0 == ~T2_E~0); {122327#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,155 INFO L290 TraceCheckUtils]: 22: Hoare triple {122327#(not (= ~T8_E~0 0))} assume !(0 == ~T3_E~0); {122327#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,155 INFO L290 TraceCheckUtils]: 23: Hoare triple {122327#(not (= ~T8_E~0 0))} assume !(0 == ~T4_E~0); {122327#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,155 INFO L290 TraceCheckUtils]: 24: Hoare triple {122327#(not (= ~T8_E~0 0))} assume !(0 == ~T5_E~0); {122327#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,156 INFO L290 TraceCheckUtils]: 25: Hoare triple {122327#(not (= ~T8_E~0 0))} assume !(0 == ~T6_E~0); {122327#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,156 INFO L290 TraceCheckUtils]: 26: Hoare triple {122327#(not (= ~T8_E~0 0))} assume !(0 == ~T7_E~0); {122327#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:23:43,156 INFO L290 TraceCheckUtils]: 27: Hoare triple {122327#(not (= ~T8_E~0 0))} assume 0 == ~T8_E~0;~T8_E~0 := 1; {122325#false} is VALID [2022-02-21 04:23:43,156 INFO L290 TraceCheckUtils]: 28: Hoare triple {122325#false} assume !(0 == ~T9_E~0); {122325#false} is VALID [2022-02-21 04:23:43,156 INFO L290 TraceCheckUtils]: 29: Hoare triple {122325#false} assume !(0 == ~T10_E~0); {122325#false} is VALID [2022-02-21 04:23:43,157 INFO L290 TraceCheckUtils]: 30: Hoare triple {122325#false} assume !(0 == ~T11_E~0); {122325#false} is VALID [2022-02-21 04:23:43,157 INFO L290 TraceCheckUtils]: 31: Hoare triple {122325#false} assume !(0 == ~T12_E~0); {122325#false} is VALID [2022-02-21 04:23:43,157 INFO L290 TraceCheckUtils]: 32: Hoare triple {122325#false} assume !(0 == ~T13_E~0); {122325#false} is VALID [2022-02-21 04:23:43,157 INFO L290 TraceCheckUtils]: 33: Hoare triple {122325#false} assume !(0 == ~E_M~0); {122325#false} is VALID [2022-02-21 04:23:43,157 INFO L290 TraceCheckUtils]: 34: Hoare triple {122325#false} assume !(0 == ~E_1~0); {122325#false} is VALID [2022-02-21 04:23:43,157 INFO L290 TraceCheckUtils]: 35: Hoare triple {122325#false} assume 0 == ~E_2~0;~E_2~0 := 1; {122325#false} is VALID [2022-02-21 04:23:43,157 INFO L290 TraceCheckUtils]: 36: Hoare triple {122325#false} assume !(0 == ~E_3~0); {122325#false} is VALID [2022-02-21 04:23:43,157 INFO L290 TraceCheckUtils]: 37: Hoare triple {122325#false} assume !(0 == ~E_4~0); {122325#false} is VALID [2022-02-21 04:23:43,158 INFO L290 TraceCheckUtils]: 38: Hoare triple {122325#false} assume !(0 == ~E_5~0); {122325#false} is VALID [2022-02-21 04:23:43,158 INFO L290 TraceCheckUtils]: 39: Hoare triple {122325#false} assume !(0 == ~E_6~0); {122325#false} is VALID [2022-02-21 04:23:43,158 INFO L290 TraceCheckUtils]: 40: Hoare triple {122325#false} assume !(0 == ~E_7~0); {122325#false} is VALID [2022-02-21 04:23:43,158 INFO L290 TraceCheckUtils]: 41: Hoare triple {122325#false} assume !(0 == ~E_8~0); {122325#false} is VALID [2022-02-21 04:23:43,158 INFO L290 TraceCheckUtils]: 42: Hoare triple {122325#false} assume !(0 == ~E_9~0); {122325#false} is VALID [2022-02-21 04:23:43,158 INFO L290 TraceCheckUtils]: 43: Hoare triple {122325#false} assume 0 == ~E_10~0;~E_10~0 := 1; {122325#false} is VALID [2022-02-21 04:23:43,158 INFO L290 TraceCheckUtils]: 44: Hoare triple {122325#false} assume !(0 == ~E_11~0); {122325#false} is VALID [2022-02-21 04:23:43,158 INFO L290 TraceCheckUtils]: 45: Hoare triple {122325#false} assume !(0 == ~E_12~0); {122325#false} is VALID [2022-02-21 04:23:43,159 INFO L290 TraceCheckUtils]: 46: Hoare triple {122325#false} assume !(0 == ~E_13~0); {122325#false} is VALID [2022-02-21 04:23:43,159 INFO L290 TraceCheckUtils]: 47: Hoare triple {122325#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {122325#false} is VALID [2022-02-21 04:23:43,159 INFO L290 TraceCheckUtils]: 48: Hoare triple {122325#false} assume !(1 == ~m_pc~0); {122325#false} is VALID [2022-02-21 04:23:43,159 INFO L290 TraceCheckUtils]: 49: Hoare triple {122325#false} is_master_triggered_~__retres1~0#1 := 0; {122325#false} is VALID [2022-02-21 04:23:43,159 INFO L290 TraceCheckUtils]: 50: Hoare triple {122325#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {122325#false} is VALID [2022-02-21 04:23:43,159 INFO L290 TraceCheckUtils]: 51: Hoare triple {122325#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {122325#false} is VALID [2022-02-21 04:23:43,159 INFO L290 TraceCheckUtils]: 52: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp~1#1); {122325#false} is VALID [2022-02-21 04:23:43,159 INFO L290 TraceCheckUtils]: 53: Hoare triple {122325#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {122325#false} is VALID [2022-02-21 04:23:43,160 INFO L290 TraceCheckUtils]: 54: Hoare triple {122325#false} assume 1 == ~t1_pc~0; {122325#false} is VALID [2022-02-21 04:23:43,160 INFO L290 TraceCheckUtils]: 55: Hoare triple {122325#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {122325#false} is VALID [2022-02-21 04:23:43,160 INFO L290 TraceCheckUtils]: 56: Hoare triple {122325#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {122325#false} is VALID [2022-02-21 04:23:43,160 INFO L290 TraceCheckUtils]: 57: Hoare triple {122325#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {122325#false} is VALID [2022-02-21 04:23:43,160 INFO L290 TraceCheckUtils]: 58: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___0~0#1); {122325#false} is VALID [2022-02-21 04:23:43,160 INFO L290 TraceCheckUtils]: 59: Hoare triple {122325#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {122325#false} is VALID [2022-02-21 04:23:43,160 INFO L290 TraceCheckUtils]: 60: Hoare triple {122325#false} assume 1 == ~t2_pc~0; {122325#false} is VALID [2022-02-21 04:23:43,160 INFO L290 TraceCheckUtils]: 61: Hoare triple {122325#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {122325#false} is VALID [2022-02-21 04:23:43,161 INFO L290 TraceCheckUtils]: 62: Hoare triple {122325#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {122325#false} is VALID [2022-02-21 04:23:43,161 INFO L290 TraceCheckUtils]: 63: Hoare triple {122325#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {122325#false} is VALID [2022-02-21 04:23:43,161 INFO L290 TraceCheckUtils]: 64: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___1~0#1); {122325#false} is VALID [2022-02-21 04:23:43,161 INFO L290 TraceCheckUtils]: 65: Hoare triple {122325#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {122325#false} is VALID [2022-02-21 04:23:43,161 INFO L290 TraceCheckUtils]: 66: Hoare triple {122325#false} assume !(1 == ~t3_pc~0); {122325#false} is VALID [2022-02-21 04:23:43,161 INFO L290 TraceCheckUtils]: 67: Hoare triple {122325#false} is_transmit3_triggered_~__retres1~3#1 := 0; {122325#false} is VALID [2022-02-21 04:23:43,161 INFO L290 TraceCheckUtils]: 68: Hoare triple {122325#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {122325#false} is VALID [2022-02-21 04:23:43,161 INFO L290 TraceCheckUtils]: 69: Hoare triple {122325#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {122325#false} is VALID [2022-02-21 04:23:43,162 INFO L290 TraceCheckUtils]: 70: Hoare triple {122325#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {122325#false} is VALID [2022-02-21 04:23:43,162 INFO L290 TraceCheckUtils]: 71: Hoare triple {122325#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {122325#false} is VALID [2022-02-21 04:23:43,162 INFO L290 TraceCheckUtils]: 72: Hoare triple {122325#false} assume 1 == ~t4_pc~0; {122325#false} is VALID [2022-02-21 04:23:43,162 INFO L290 TraceCheckUtils]: 73: Hoare triple {122325#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {122325#false} is VALID [2022-02-21 04:23:43,162 INFO L290 TraceCheckUtils]: 74: Hoare triple {122325#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {122325#false} is VALID [2022-02-21 04:23:43,162 INFO L290 TraceCheckUtils]: 75: Hoare triple {122325#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {122325#false} is VALID [2022-02-21 04:23:43,162 INFO L290 TraceCheckUtils]: 76: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___3~0#1); {122325#false} is VALID [2022-02-21 04:23:43,162 INFO L290 TraceCheckUtils]: 77: Hoare triple {122325#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {122325#false} is VALID [2022-02-21 04:23:43,163 INFO L290 TraceCheckUtils]: 78: Hoare triple {122325#false} assume !(1 == ~t5_pc~0); {122325#false} is VALID [2022-02-21 04:23:43,163 INFO L290 TraceCheckUtils]: 79: Hoare triple {122325#false} is_transmit5_triggered_~__retres1~5#1 := 0; {122325#false} is VALID [2022-02-21 04:23:43,163 INFO L290 TraceCheckUtils]: 80: Hoare triple {122325#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {122325#false} is VALID [2022-02-21 04:23:43,163 INFO L290 TraceCheckUtils]: 81: Hoare triple {122325#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {122325#false} is VALID [2022-02-21 04:23:43,163 INFO L290 TraceCheckUtils]: 82: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___4~0#1); {122325#false} is VALID [2022-02-21 04:23:43,163 INFO L290 TraceCheckUtils]: 83: Hoare triple {122325#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {122325#false} is VALID [2022-02-21 04:23:43,163 INFO L290 TraceCheckUtils]: 84: Hoare triple {122325#false} assume 1 == ~t6_pc~0; {122325#false} is VALID [2022-02-21 04:23:43,163 INFO L290 TraceCheckUtils]: 85: Hoare triple {122325#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {122325#false} is VALID [2022-02-21 04:23:43,164 INFO L290 TraceCheckUtils]: 86: Hoare triple {122325#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {122325#false} is VALID [2022-02-21 04:23:43,164 INFO L290 TraceCheckUtils]: 87: Hoare triple {122325#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {122325#false} is VALID [2022-02-21 04:23:43,164 INFO L290 TraceCheckUtils]: 88: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___5~0#1); {122325#false} is VALID [2022-02-21 04:23:43,164 INFO L290 TraceCheckUtils]: 89: Hoare triple {122325#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {122325#false} is VALID [2022-02-21 04:23:43,164 INFO L290 TraceCheckUtils]: 90: Hoare triple {122325#false} assume !(1 == ~t7_pc~0); {122325#false} is VALID [2022-02-21 04:23:43,164 INFO L290 TraceCheckUtils]: 91: Hoare triple {122325#false} is_transmit7_triggered_~__retres1~7#1 := 0; {122325#false} is VALID [2022-02-21 04:23:43,164 INFO L290 TraceCheckUtils]: 92: Hoare triple {122325#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {122325#false} is VALID [2022-02-21 04:23:43,164 INFO L290 TraceCheckUtils]: 93: Hoare triple {122325#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {122325#false} is VALID [2022-02-21 04:23:43,165 INFO L290 TraceCheckUtils]: 94: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___6~0#1); {122325#false} is VALID [2022-02-21 04:23:43,165 INFO L290 TraceCheckUtils]: 95: Hoare triple {122325#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {122325#false} is VALID [2022-02-21 04:23:43,165 INFO L290 TraceCheckUtils]: 96: Hoare triple {122325#false} assume 1 == ~t8_pc~0; {122325#false} is VALID [2022-02-21 04:23:43,165 INFO L290 TraceCheckUtils]: 97: Hoare triple {122325#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {122325#false} is VALID [2022-02-21 04:23:43,165 INFO L290 TraceCheckUtils]: 98: Hoare triple {122325#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {122325#false} is VALID [2022-02-21 04:23:43,165 INFO L290 TraceCheckUtils]: 99: Hoare triple {122325#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {122325#false} is VALID [2022-02-21 04:23:43,165 INFO L290 TraceCheckUtils]: 100: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___7~0#1); {122325#false} is VALID [2022-02-21 04:23:43,165 INFO L290 TraceCheckUtils]: 101: Hoare triple {122325#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {122325#false} is VALID [2022-02-21 04:23:43,166 INFO L290 TraceCheckUtils]: 102: Hoare triple {122325#false} assume 1 == ~t9_pc~0; {122325#false} is VALID [2022-02-21 04:23:43,166 INFO L290 TraceCheckUtils]: 103: Hoare triple {122325#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {122325#false} is VALID [2022-02-21 04:23:43,166 INFO L290 TraceCheckUtils]: 104: Hoare triple {122325#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {122325#false} is VALID [2022-02-21 04:23:43,166 INFO L290 TraceCheckUtils]: 105: Hoare triple {122325#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {122325#false} is VALID [2022-02-21 04:23:43,166 INFO L290 TraceCheckUtils]: 106: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___8~0#1); {122325#false} is VALID [2022-02-21 04:23:43,166 INFO L290 TraceCheckUtils]: 107: Hoare triple {122325#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {122325#false} is VALID [2022-02-21 04:23:43,166 INFO L290 TraceCheckUtils]: 108: Hoare triple {122325#false} assume !(1 == ~t10_pc~0); {122325#false} is VALID [2022-02-21 04:23:43,166 INFO L290 TraceCheckUtils]: 109: Hoare triple {122325#false} is_transmit10_triggered_~__retres1~10#1 := 0; {122325#false} is VALID [2022-02-21 04:23:43,167 INFO L290 TraceCheckUtils]: 110: Hoare triple {122325#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {122325#false} is VALID [2022-02-21 04:23:43,167 INFO L290 TraceCheckUtils]: 111: Hoare triple {122325#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {122325#false} is VALID [2022-02-21 04:23:43,167 INFO L290 TraceCheckUtils]: 112: Hoare triple {122325#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {122325#false} is VALID [2022-02-21 04:23:43,167 INFO L290 TraceCheckUtils]: 113: Hoare triple {122325#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {122325#false} is VALID [2022-02-21 04:23:43,167 INFO L290 TraceCheckUtils]: 114: Hoare triple {122325#false} assume 1 == ~t11_pc~0; {122325#false} is VALID [2022-02-21 04:23:43,167 INFO L290 TraceCheckUtils]: 115: Hoare triple {122325#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {122325#false} is VALID [2022-02-21 04:23:43,167 INFO L290 TraceCheckUtils]: 116: Hoare triple {122325#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {122325#false} is VALID [2022-02-21 04:23:43,168 INFO L290 TraceCheckUtils]: 117: Hoare triple {122325#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {122325#false} is VALID [2022-02-21 04:23:43,168 INFO L290 TraceCheckUtils]: 118: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___10~0#1); {122325#false} is VALID [2022-02-21 04:23:43,168 INFO L290 TraceCheckUtils]: 119: Hoare triple {122325#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {122325#false} is VALID [2022-02-21 04:23:43,168 INFO L290 TraceCheckUtils]: 120: Hoare triple {122325#false} assume !(1 == ~t12_pc~0); {122325#false} is VALID [2022-02-21 04:23:43,168 INFO L290 TraceCheckUtils]: 121: Hoare triple {122325#false} is_transmit12_triggered_~__retres1~12#1 := 0; {122325#false} is VALID [2022-02-21 04:23:43,168 INFO L290 TraceCheckUtils]: 122: Hoare triple {122325#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {122325#false} is VALID [2022-02-21 04:23:43,168 INFO L290 TraceCheckUtils]: 123: Hoare triple {122325#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {122325#false} is VALID [2022-02-21 04:23:43,168 INFO L290 TraceCheckUtils]: 124: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___11~0#1); {122325#false} is VALID [2022-02-21 04:23:43,169 INFO L290 TraceCheckUtils]: 125: Hoare triple {122325#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {122325#false} is VALID [2022-02-21 04:23:43,169 INFO L290 TraceCheckUtils]: 126: Hoare triple {122325#false} assume 1 == ~t13_pc~0; {122325#false} is VALID [2022-02-21 04:23:43,169 INFO L290 TraceCheckUtils]: 127: Hoare triple {122325#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {122325#false} is VALID [2022-02-21 04:23:43,169 INFO L290 TraceCheckUtils]: 128: Hoare triple {122325#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {122325#false} is VALID [2022-02-21 04:23:43,169 INFO L290 TraceCheckUtils]: 129: Hoare triple {122325#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {122325#false} is VALID [2022-02-21 04:23:43,169 INFO L290 TraceCheckUtils]: 130: Hoare triple {122325#false} assume !(0 != activate_threads_~tmp___12~0#1); {122325#false} is VALID [2022-02-21 04:23:43,169 INFO L290 TraceCheckUtils]: 131: Hoare triple {122325#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {122325#false} is VALID [2022-02-21 04:23:43,169 INFO L290 TraceCheckUtils]: 132: Hoare triple {122325#false} assume !(1 == ~M_E~0); {122325#false} is VALID [2022-02-21 04:23:43,170 INFO L290 TraceCheckUtils]: 133: Hoare triple {122325#false} assume !(1 == ~T1_E~0); {122325#false} is VALID [2022-02-21 04:23:43,170 INFO L290 TraceCheckUtils]: 134: Hoare triple {122325#false} assume !(1 == ~T2_E~0); {122325#false} is VALID [2022-02-21 04:23:43,170 INFO L290 TraceCheckUtils]: 135: Hoare triple {122325#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {122325#false} is VALID [2022-02-21 04:23:43,170 INFO L290 TraceCheckUtils]: 136: Hoare triple {122325#false} assume !(1 == ~T4_E~0); {122325#false} is VALID [2022-02-21 04:23:43,170 INFO L290 TraceCheckUtils]: 137: Hoare triple {122325#false} assume !(1 == ~T5_E~0); {122325#false} is VALID [2022-02-21 04:23:43,170 INFO L290 TraceCheckUtils]: 138: Hoare triple {122325#false} assume !(1 == ~T6_E~0); {122325#false} is VALID [2022-02-21 04:23:43,170 INFO L290 TraceCheckUtils]: 139: Hoare triple {122325#false} assume !(1 == ~T7_E~0); {122325#false} is VALID [2022-02-21 04:23:43,170 INFO L290 TraceCheckUtils]: 140: Hoare triple {122325#false} assume !(1 == ~T8_E~0); {122325#false} is VALID [2022-02-21 04:23:43,171 INFO L290 TraceCheckUtils]: 141: Hoare triple {122325#false} assume !(1 == ~T9_E~0); {122325#false} is VALID [2022-02-21 04:23:43,171 INFO L290 TraceCheckUtils]: 142: Hoare triple {122325#false} assume !(1 == ~T10_E~0); {122325#false} is VALID [2022-02-21 04:23:43,171 INFO L290 TraceCheckUtils]: 143: Hoare triple {122325#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {122325#false} is VALID [2022-02-21 04:23:43,171 INFO L290 TraceCheckUtils]: 144: Hoare triple {122325#false} assume !(1 == ~T12_E~0); {122325#false} is VALID [2022-02-21 04:23:43,171 INFO L290 TraceCheckUtils]: 145: Hoare triple {122325#false} assume !(1 == ~T13_E~0); {122325#false} is VALID [2022-02-21 04:23:43,171 INFO L290 TraceCheckUtils]: 146: Hoare triple {122325#false} assume !(1 == ~E_M~0); {122325#false} is VALID [2022-02-21 04:23:43,171 INFO L290 TraceCheckUtils]: 147: Hoare triple {122325#false} assume !(1 == ~E_1~0); {122325#false} is VALID [2022-02-21 04:23:43,171 INFO L290 TraceCheckUtils]: 148: Hoare triple {122325#false} assume !(1 == ~E_2~0); {122325#false} is VALID [2022-02-21 04:23:43,171 INFO L290 TraceCheckUtils]: 149: Hoare triple {122325#false} assume !(1 == ~E_3~0); {122325#false} is VALID [2022-02-21 04:23:43,172 INFO L290 TraceCheckUtils]: 150: Hoare triple {122325#false} assume !(1 == ~E_4~0); {122325#false} is VALID [2022-02-21 04:23:43,172 INFO L290 TraceCheckUtils]: 151: Hoare triple {122325#false} assume 1 == ~E_5~0;~E_5~0 := 2; {122325#false} is VALID [2022-02-21 04:23:43,172 INFO L290 TraceCheckUtils]: 152: Hoare triple {122325#false} assume !(1 == ~E_6~0); {122325#false} is VALID [2022-02-21 04:23:43,172 INFO L290 TraceCheckUtils]: 153: Hoare triple {122325#false} assume !(1 == ~E_7~0); {122325#false} is VALID [2022-02-21 04:23:43,172 INFO L290 TraceCheckUtils]: 154: Hoare triple {122325#false} assume !(1 == ~E_8~0); {122325#false} is VALID [2022-02-21 04:23:43,172 INFO L290 TraceCheckUtils]: 155: Hoare triple {122325#false} assume !(1 == ~E_9~0); {122325#false} is VALID [2022-02-21 04:23:43,172 INFO L290 TraceCheckUtils]: 156: Hoare triple {122325#false} assume !(1 == ~E_10~0); {122325#false} is VALID [2022-02-21 04:23:43,172 INFO L290 TraceCheckUtils]: 157: Hoare triple {122325#false} assume !(1 == ~E_11~0); {122325#false} is VALID [2022-02-21 04:23:43,173 INFO L290 TraceCheckUtils]: 158: Hoare triple {122325#false} assume !(1 == ~E_12~0); {122325#false} is VALID [2022-02-21 04:23:43,173 INFO L290 TraceCheckUtils]: 159: Hoare triple {122325#false} assume 1 == ~E_13~0;~E_13~0 := 2; {122325#false} is VALID [2022-02-21 04:23:43,173 INFO L290 TraceCheckUtils]: 160: Hoare triple {122325#false} assume { :end_inline_reset_delta_events } true; {122325#false} is VALID [2022-02-21 04:23:43,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:43,173 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:43,173 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212219061] [2022-02-21 04:23:43,174 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212219061] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:43,174 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:43,174 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:43,174 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23626971] [2022-02-21 04:23:43,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:43,174 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:43,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:43,175 INFO L85 PathProgramCache]: Analyzing trace with hash 529247527, now seen corresponding path program 1 times [2022-02-21 04:23:43,175 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:43,175 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872058912] [2022-02-21 04:23:43,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:43,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:43,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:43,198 INFO L290 TraceCheckUtils]: 0: Hoare triple {122328#true} assume !false; {122328#true} is VALID [2022-02-21 04:23:43,198 INFO L290 TraceCheckUtils]: 1: Hoare triple {122328#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {122328#true} is VALID [2022-02-21 04:23:43,198 INFO L290 TraceCheckUtils]: 2: Hoare triple {122328#true} assume !false; {122328#true} is VALID [2022-02-21 04:23:43,198 INFO L290 TraceCheckUtils]: 3: Hoare triple {122328#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {122328#true} is VALID [2022-02-21 04:23:43,198 INFO L290 TraceCheckUtils]: 4: Hoare triple {122328#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {122328#true} is VALID [2022-02-21 04:23:43,199 INFO L290 TraceCheckUtils]: 5: Hoare triple {122328#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {122328#true} is VALID [2022-02-21 04:23:43,199 INFO L290 TraceCheckUtils]: 6: Hoare triple {122328#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {122328#true} is VALID [2022-02-21 04:23:43,199 INFO L290 TraceCheckUtils]: 7: Hoare triple {122328#true} assume !(0 != eval_~tmp~0#1); {122328#true} is VALID [2022-02-21 04:23:43,199 INFO L290 TraceCheckUtils]: 8: Hoare triple {122328#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {122328#true} is VALID [2022-02-21 04:23:43,199 INFO L290 TraceCheckUtils]: 9: Hoare triple {122328#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {122328#true} is VALID [2022-02-21 04:23:43,199 INFO L290 TraceCheckUtils]: 10: Hoare triple {122328#true} assume !(0 == ~M_E~0); {122328#true} is VALID [2022-02-21 04:23:43,199 INFO L290 TraceCheckUtils]: 11: Hoare triple {122328#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {122328#true} is VALID [2022-02-21 04:23:43,200 INFO L290 TraceCheckUtils]: 12: Hoare triple {122328#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {122328#true} is VALID [2022-02-21 04:23:43,200 INFO L290 TraceCheckUtils]: 13: Hoare triple {122328#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {122328#true} is VALID [2022-02-21 04:23:43,200 INFO L290 TraceCheckUtils]: 14: Hoare triple {122328#true} assume !(0 == ~T4_E~0); {122328#true} is VALID [2022-02-21 04:23:43,200 INFO L290 TraceCheckUtils]: 15: Hoare triple {122328#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {122328#true} is VALID [2022-02-21 04:23:43,200 INFO L290 TraceCheckUtils]: 16: Hoare triple {122328#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {122328#true} is VALID [2022-02-21 04:23:43,200 INFO L290 TraceCheckUtils]: 17: Hoare triple {122328#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,201 INFO L290 TraceCheckUtils]: 18: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,201 INFO L290 TraceCheckUtils]: 19: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,201 INFO L290 TraceCheckUtils]: 20: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,201 INFO L290 TraceCheckUtils]: 21: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,202 INFO L290 TraceCheckUtils]: 22: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,202 INFO L290 TraceCheckUtils]: 23: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,202 INFO L290 TraceCheckUtils]: 24: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,203 INFO L290 TraceCheckUtils]: 25: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,203 INFO L290 TraceCheckUtils]: 26: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,203 INFO L290 TraceCheckUtils]: 27: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,203 INFO L290 TraceCheckUtils]: 28: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,204 INFO L290 TraceCheckUtils]: 29: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,204 INFO L290 TraceCheckUtils]: 30: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,204 INFO L290 TraceCheckUtils]: 31: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,205 INFO L290 TraceCheckUtils]: 32: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,205 INFO L290 TraceCheckUtils]: 33: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,205 INFO L290 TraceCheckUtils]: 34: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,205 INFO L290 TraceCheckUtils]: 35: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,206 INFO L290 TraceCheckUtils]: 36: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,206 INFO L290 TraceCheckUtils]: 37: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,206 INFO L290 TraceCheckUtils]: 38: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,207 INFO L290 TraceCheckUtils]: 39: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,207 INFO L290 TraceCheckUtils]: 40: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,207 INFO L290 TraceCheckUtils]: 41: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,207 INFO L290 TraceCheckUtils]: 42: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,208 INFO L290 TraceCheckUtils]: 43: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,208 INFO L290 TraceCheckUtils]: 44: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,208 INFO L290 TraceCheckUtils]: 45: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,209 INFO L290 TraceCheckUtils]: 46: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,209 INFO L290 TraceCheckUtils]: 47: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,209 INFO L290 TraceCheckUtils]: 48: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,209 INFO L290 TraceCheckUtils]: 49: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,210 INFO L290 TraceCheckUtils]: 50: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,210 INFO L290 TraceCheckUtils]: 51: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t2_pc~0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,210 INFO L290 TraceCheckUtils]: 52: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,211 INFO L290 TraceCheckUtils]: 53: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,211 INFO L290 TraceCheckUtils]: 54: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,211 INFO L290 TraceCheckUtils]: 55: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,211 INFO L290 TraceCheckUtils]: 56: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,212 INFO L290 TraceCheckUtils]: 57: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,212 INFO L290 TraceCheckUtils]: 58: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,212 INFO L290 TraceCheckUtils]: 59: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,213 INFO L290 TraceCheckUtils]: 60: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,213 INFO L290 TraceCheckUtils]: 61: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,213 INFO L290 TraceCheckUtils]: 62: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,213 INFO L290 TraceCheckUtils]: 63: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,214 INFO L290 TraceCheckUtils]: 64: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,214 INFO L290 TraceCheckUtils]: 65: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,214 INFO L290 TraceCheckUtils]: 66: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,214 INFO L290 TraceCheckUtils]: 67: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,215 INFO L290 TraceCheckUtils]: 68: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,215 INFO L290 TraceCheckUtils]: 69: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t5_pc~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,215 INFO L290 TraceCheckUtils]: 70: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,216 INFO L290 TraceCheckUtils]: 71: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,216 INFO L290 TraceCheckUtils]: 72: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,216 INFO L290 TraceCheckUtils]: 73: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,216 INFO L290 TraceCheckUtils]: 74: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,217 INFO L290 TraceCheckUtils]: 75: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,217 INFO L290 TraceCheckUtils]: 76: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,217 INFO L290 TraceCheckUtils]: 77: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,218 INFO L290 TraceCheckUtils]: 78: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,218 INFO L290 TraceCheckUtils]: 79: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,218 INFO L290 TraceCheckUtils]: 80: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,218 INFO L290 TraceCheckUtils]: 81: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,219 INFO L290 TraceCheckUtils]: 82: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,219 INFO L290 TraceCheckUtils]: 83: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,219 INFO L290 TraceCheckUtils]: 84: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,220 INFO L290 TraceCheckUtils]: 85: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,220 INFO L290 TraceCheckUtils]: 86: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,220 INFO L290 TraceCheckUtils]: 87: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t8_pc~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,220 INFO L290 TraceCheckUtils]: 88: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,221 INFO L290 TraceCheckUtils]: 89: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,221 INFO L290 TraceCheckUtils]: 90: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,221 INFO L290 TraceCheckUtils]: 91: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,222 INFO L290 TraceCheckUtils]: 92: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,222 INFO L290 TraceCheckUtils]: 93: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t9_pc~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,222 INFO L290 TraceCheckUtils]: 94: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,222 INFO L290 TraceCheckUtils]: 95: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,223 INFO L290 TraceCheckUtils]: 96: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,223 INFO L290 TraceCheckUtils]: 97: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,223 INFO L290 TraceCheckUtils]: 98: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,224 INFO L290 TraceCheckUtils]: 99: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t10_pc~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,224 INFO L290 TraceCheckUtils]: 100: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,224 INFO L290 TraceCheckUtils]: 101: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,224 INFO L290 TraceCheckUtils]: 102: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,225 INFO L290 TraceCheckUtils]: 103: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,225 INFO L290 TraceCheckUtils]: 104: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,225 INFO L290 TraceCheckUtils]: 105: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,226 INFO L290 TraceCheckUtils]: 106: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,226 INFO L290 TraceCheckUtils]: 107: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,226 INFO L290 TraceCheckUtils]: 108: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,226 INFO L290 TraceCheckUtils]: 109: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,227 INFO L290 TraceCheckUtils]: 110: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,227 INFO L290 TraceCheckUtils]: 111: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t12_pc~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,227 INFO L290 TraceCheckUtils]: 112: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,228 INFO L290 TraceCheckUtils]: 113: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,228 INFO L290 TraceCheckUtils]: 114: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,228 INFO L290 TraceCheckUtils]: 115: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,228 INFO L290 TraceCheckUtils]: 116: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,229 INFO L290 TraceCheckUtils]: 117: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t13_pc~0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,229 INFO L290 TraceCheckUtils]: 118: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,229 INFO L290 TraceCheckUtils]: 119: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,230 INFO L290 TraceCheckUtils]: 120: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,230 INFO L290 TraceCheckUtils]: 121: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,230 INFO L290 TraceCheckUtils]: 122: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,230 INFO L290 TraceCheckUtils]: 123: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~M_E~0); {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,231 INFO L290 TraceCheckUtils]: 124: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,231 INFO L290 TraceCheckUtils]: 125: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,231 INFO L290 TraceCheckUtils]: 126: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,231 INFO L290 TraceCheckUtils]: 127: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,232 INFO L290 TraceCheckUtils]: 128: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,232 INFO L290 TraceCheckUtils]: 129: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {122330#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:43,232 INFO L290 TraceCheckUtils]: 130: Hoare triple {122330#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {122329#false} is VALID [2022-02-21 04:23:43,232 INFO L290 TraceCheckUtils]: 131: Hoare triple {122329#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,233 INFO L290 TraceCheckUtils]: 132: Hoare triple {122329#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,233 INFO L290 TraceCheckUtils]: 133: Hoare triple {122329#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,233 INFO L290 TraceCheckUtils]: 134: Hoare triple {122329#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,233 INFO L290 TraceCheckUtils]: 135: Hoare triple {122329#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,233 INFO L290 TraceCheckUtils]: 136: Hoare triple {122329#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,233 INFO L290 TraceCheckUtils]: 137: Hoare triple {122329#false} assume 1 == ~E_M~0;~E_M~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,233 INFO L290 TraceCheckUtils]: 138: Hoare triple {122329#false} assume !(1 == ~E_1~0); {122329#false} is VALID [2022-02-21 04:23:43,234 INFO L290 TraceCheckUtils]: 139: Hoare triple {122329#false} assume 1 == ~E_2~0;~E_2~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,234 INFO L290 TraceCheckUtils]: 140: Hoare triple {122329#false} assume 1 == ~E_3~0;~E_3~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,234 INFO L290 TraceCheckUtils]: 141: Hoare triple {122329#false} assume 1 == ~E_4~0;~E_4~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,234 INFO L290 TraceCheckUtils]: 142: Hoare triple {122329#false} assume 1 == ~E_5~0;~E_5~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,234 INFO L290 TraceCheckUtils]: 143: Hoare triple {122329#false} assume 1 == ~E_6~0;~E_6~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,234 INFO L290 TraceCheckUtils]: 144: Hoare triple {122329#false} assume 1 == ~E_7~0;~E_7~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,234 INFO L290 TraceCheckUtils]: 145: Hoare triple {122329#false} assume 1 == ~E_8~0;~E_8~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,234 INFO L290 TraceCheckUtils]: 146: Hoare triple {122329#false} assume !(1 == ~E_9~0); {122329#false} is VALID [2022-02-21 04:23:43,234 INFO L290 TraceCheckUtils]: 147: Hoare triple {122329#false} assume 1 == ~E_10~0;~E_10~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,235 INFO L290 TraceCheckUtils]: 148: Hoare triple {122329#false} assume 1 == ~E_11~0;~E_11~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,235 INFO L290 TraceCheckUtils]: 149: Hoare triple {122329#false} assume 1 == ~E_12~0;~E_12~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,235 INFO L290 TraceCheckUtils]: 150: Hoare triple {122329#false} assume 1 == ~E_13~0;~E_13~0 := 2; {122329#false} is VALID [2022-02-21 04:23:43,235 INFO L290 TraceCheckUtils]: 151: Hoare triple {122329#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {122329#false} is VALID [2022-02-21 04:23:43,235 INFO L290 TraceCheckUtils]: 152: Hoare triple {122329#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {122329#false} is VALID [2022-02-21 04:23:43,235 INFO L290 TraceCheckUtils]: 153: Hoare triple {122329#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {122329#false} is VALID [2022-02-21 04:23:43,235 INFO L290 TraceCheckUtils]: 154: Hoare triple {122329#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {122329#false} is VALID [2022-02-21 04:23:43,236 INFO L290 TraceCheckUtils]: 155: Hoare triple {122329#false} assume !(0 == start_simulation_~tmp~3#1); {122329#false} is VALID [2022-02-21 04:23:43,236 INFO L290 TraceCheckUtils]: 156: Hoare triple {122329#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {122329#false} is VALID [2022-02-21 04:23:43,236 INFO L290 TraceCheckUtils]: 157: Hoare triple {122329#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {122329#false} is VALID [2022-02-21 04:23:43,236 INFO L290 TraceCheckUtils]: 158: Hoare triple {122329#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {122329#false} is VALID [2022-02-21 04:23:43,236 INFO L290 TraceCheckUtils]: 159: Hoare triple {122329#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {122329#false} is VALID [2022-02-21 04:23:43,236 INFO L290 TraceCheckUtils]: 160: Hoare triple {122329#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {122329#false} is VALID [2022-02-21 04:23:43,236 INFO L290 TraceCheckUtils]: 161: Hoare triple {122329#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {122329#false} is VALID [2022-02-21 04:23:43,236 INFO L290 TraceCheckUtils]: 162: Hoare triple {122329#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {122329#false} is VALID [2022-02-21 04:23:43,237 INFO L290 TraceCheckUtils]: 163: Hoare triple {122329#false} assume !(0 != start_simulation_~tmp___0~1#1); {122329#false} is VALID [2022-02-21 04:23:43,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:43,237 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:43,237 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872058912] [2022-02-21 04:23:43,237 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872058912] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:43,237 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:43,238 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:43,238 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1295992067] [2022-02-21 04:23:43,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:43,238 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:43,238 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:43,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:43,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:43,239 INFO L87 Difference]: Start difference. First operand 3767 states and 5538 transitions. cyclomatic complexity: 1772 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:47,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:47,647 INFO L93 Difference]: Finished difference Result 7385 states and 10846 transitions. [2022-02-21 04:23:47,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:47,648 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:47,735 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:47,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7385 states and 10846 transitions. [2022-02-21 04:23:48,904 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2022-02-21 04:23:50,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7385 states to 7385 states and 10846 transitions. [2022-02-21 04:23:50,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7385 [2022-02-21 04:23:50,107 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7385 [2022-02-21 04:23:50,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7385 states and 10846 transitions. [2022-02-21 04:23:50,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:50,112 INFO L681 BuchiCegarLoop]: Abstraction has 7385 states and 10846 transitions. [2022-02-21 04:23:50,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7385 states and 10846 transitions. [2022-02-21 04:23:50,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7385 to 7385. [2022-02-21 04:23:50,177 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:50,183 INFO L82 GeneralOperation]: Start isEquivalent. First operand 7385 states and 10846 transitions. Second operand has 7385 states, 7385 states have (on average 1.4686526743398782) internal successors, (10846), 7384 states have internal predecessors, (10846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:50,189 INFO L74 IsIncluded]: Start isIncluded. First operand 7385 states and 10846 transitions. Second operand has 7385 states, 7385 states have (on average 1.4686526743398782) internal successors, (10846), 7384 states have internal predecessors, (10846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:50,196 INFO L87 Difference]: Start difference. First operand 7385 states and 10846 transitions. Second operand has 7385 states, 7385 states have (on average 1.4686526743398782) internal successors, (10846), 7384 states have internal predecessors, (10846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:51,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:51,446 INFO L93 Difference]: Finished difference Result 7385 states and 10846 transitions. [2022-02-21 04:23:51,446 INFO L276 IsEmpty]: Start isEmpty. Operand 7385 states and 10846 transitions. [2022-02-21 04:23:51,452 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:51,452 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:51,459 INFO L74 IsIncluded]: Start isIncluded. First operand has 7385 states, 7385 states have (on average 1.4686526743398782) internal successors, (10846), 7384 states have internal predecessors, (10846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7385 states and 10846 transitions. [2022-02-21 04:23:51,463 INFO L87 Difference]: Start difference. First operand has 7385 states, 7385 states have (on average 1.4686526743398782) internal successors, (10846), 7384 states have internal predecessors, (10846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7385 states and 10846 transitions. [2022-02-21 04:23:52,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:52,680 INFO L93 Difference]: Finished difference Result 7385 states and 10846 transitions. [2022-02-21 04:23:52,680 INFO L276 IsEmpty]: Start isEmpty. Operand 7385 states and 10846 transitions. [2022-02-21 04:23:52,685 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:52,685 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:52,686 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:52,686 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:52,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7385 states, 7385 states have (on average 1.4686526743398782) internal successors, (10846), 7384 states have internal predecessors, (10846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:53,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7385 states to 7385 states and 10846 transitions. [2022-02-21 04:23:53,990 INFO L704 BuchiCegarLoop]: Abstraction has 7385 states and 10846 transitions. [2022-02-21 04:23:53,990 INFO L587 BuchiCegarLoop]: Abstraction has 7385 states and 10846 transitions. [2022-02-21 04:23:53,990 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:23:53,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7385 states and 10846 transitions. [2022-02-21 04:23:54,000 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2022-02-21 04:23:54,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:54,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:54,023 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:54,023 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:54,024 INFO L791 eck$LassoCheckResult]: Stem: 130597#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 130598#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 130328#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 130329#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131852#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 131853#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130516#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 130517#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 130551#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131413#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131414#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131544#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 131545#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 130334#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 130335#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 131586#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 130863#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 130864#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 131474#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131831#L1286 assume !(0 == ~M_E~0); 131661#L1286-2 assume !(0 == ~T1_E~0); 130242#L1291-1 assume !(0 == ~T2_E~0); 130243#L1296-1 assume !(0 == ~T3_E~0); 130954#L1301-1 assume !(0 == ~T4_E~0); 130955#L1306-1 assume !(0 == ~T5_E~0); 131485#L1311-1 assume !(0 == ~T6_E~0); 130202#L1316-1 assume !(0 == ~T7_E~0); 130203#L1321-1 assume !(0 == ~T8_E~0); 130975#L1326-1 assume !(0 == ~T9_E~0); 130017#L1331-1 assume !(0 == ~T10_E~0); 129722#L1336-1 assume !(0 == ~T11_E~0); 129723#L1341-1 assume !(0 == ~T12_E~0); 129774#L1346-1 assume !(0 == ~T13_E~0); 129775#L1351-1 assume !(0 == ~E_M~0); 130149#L1356-1 assume !(0 == ~E_1~0); 130150#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 131768#L1366-1 assume !(0 == ~E_3~0); 130195#L1371-1 assume !(0 == ~E_4~0); 130196#L1376-1 assume !(0 == ~E_5~0); 131016#L1381-1 assume !(0 == ~E_6~0); 131017#L1386-1 assume !(0 == ~E_7~0); 131818#L1391-1 assume !(0 == ~E_8~0); 131840#L1396-1 assume !(0 == ~E_9~0); 130897#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 130898#L1406-1 assume !(0 == ~E_11~0); 131211#L1411-1 assume !(0 == ~E_12~0); 131212#L1416-1 assume !(0 == ~E_13~0); 130821#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 130659#L635 assume !(1 == ~m_pc~0); 129792#L635-2 is_master_triggered_~__retres1~0#1 := 0; 129793#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130144#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 130785#L1598 assume !(0 != activate_threads_~tmp~1#1); 129972#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129973#L654 assume 1 == ~t1_pc~0; 130683#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 130684#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131811#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 130765#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 130766#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130020#L673 assume 1 == ~t2_pc~0; 130021#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 131179#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131180#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131860#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 131867#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130844#L692 assume !(1 == ~t3_pc~0); 130661#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 130662#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130518#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 130486#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 130487#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130045#L711 assume 1 == ~t4_pc~0; 130046#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 130531#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130993#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 129747#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 129748#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131851#L730 assume !(1 == ~t5_pc~0); 131109#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 129927#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 129928#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 130055#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 130056#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 130399#L749 assume 1 == ~t6_pc~0; 130172#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 129932#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 130365#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 130366#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 130589#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 129727#L768 assume !(1 == ~t7_pc~0); 129728#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 131040#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 129965#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 129966#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 131059#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 130204#L787 assume 1 == ~t8_pc~0; 130205#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 131432#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131621#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 131622#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 129772#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 129773#L806 assume 1 == ~t9_pc~0; 131443#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 129807#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 129808#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 130057#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 130058#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 131422#L825 assume !(1 == ~t10_pc~0); 131423#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 131007#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 131008#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 130145#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 130146#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 130734#L844 assume 1 == ~t11_pc~0; 130420#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 130421#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 130791#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 130792#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 131408#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 131409#L863 assume !(1 == ~t12_pc~0); 129908#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 129907#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 130135#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 131514#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 131515#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 130858#L882 assume 1 == ~t13_pc~0; 130859#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 131148#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 131718#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 131478#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 131135#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131136#L1434 assume !(1 == ~M_E~0); 131732#L1434-2 assume !(1 == ~T1_E~0); 131858#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 131859#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 133390#L1449-1 assume !(1 == ~T4_E~0); 133389#L1454-1 assume !(1 == ~T5_E~0); 133388#L1459-1 assume !(1 == ~T6_E~0); 133387#L1464-1 assume !(1 == ~T7_E~0); 133386#L1469-1 assume !(1 == ~T8_E~0); 131149#L1474-1 assume !(1 == ~T9_E~0); 133385#L1479-1 assume !(1 == ~T10_E~0); 133384#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 133383#L1489-1 assume !(1 == ~T12_E~0); 133382#L1494-1 assume !(1 == ~T13_E~0); 133381#L1499-1 assume !(1 == ~E_M~0); 133380#L1504-1 assume !(1 == ~E_1~0); 133379#L1509-1 assume !(1 == ~E_2~0); 133378#L1514-1 assume !(1 == ~E_3~0); 133377#L1519-1 assume !(1 == ~E_4~0); 133376#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 133375#L1529-1 assume !(1 == ~E_6~0); 133374#L1534-1 assume !(1 == ~E_7~0); 133373#L1539-1 assume !(1 == ~E_8~0); 133372#L1544-1 assume !(1 == ~E_9~0); 133371#L1549-1 assume !(1 == ~E_10~0); 133370#L1554-1 assume !(1 == ~E_11~0); 133369#L1559-1 assume !(1 == ~E_12~0); 131567#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 131568#L1569-1 assume { :end_inline_reset_delta_events } true; 133340#L1935-2 [2022-02-21 04:23:54,024 INFO L793 eck$LassoCheckResult]: Loop: 133340#L1935-2 assume !false; 129836#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129837#L1261 assume !false; 131073#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 131074#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 131412#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 130138#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 130139#L1074 assume !(0 != eval_~tmp~0#1); 130498#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 131538#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 131539#L1286-3 assume !(0 == ~M_E~0); 133319#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 133316#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 133317#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 136472#L1301-3 assume !(0 == ~T4_E~0); 136471#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 136470#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 136469#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 136468#L1321-3 assume !(0 == ~T8_E~0); 136467#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 136466#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 136465#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 136464#L1341-3 assume !(0 == ~T12_E~0); 136463#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 136462#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 136461#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 136460#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 136459#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 136458#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 136457#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 136456#L1381-3 assume !(0 == ~E_6~0); 136455#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 136454#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 136453#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 136452#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 136451#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 136450#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 136449#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 136448#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136447#L635-45 assume !(1 == ~m_pc~0); 136446#L635-47 is_master_triggered_~__retres1~0#1 := 0; 136444#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136443#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 136442#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 136441#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133227#L654-45 assume 1 == ~t1_pc~0; 133228#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 133220#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133221#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 129840#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 129841#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130673#L673-45 assume 1 == ~t2_pc~0; 130675#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 136440#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131729#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131691#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 131692#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130286#L692-45 assume !(1 == ~t3_pc~0); 130288#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 131500#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131064#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 130341#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 130342#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131884#L711-45 assume 1 == ~t4_pc~0; 131886#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 136436#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130633#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 130634#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 136435#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136434#L730-45 assume 1 == ~t5_pc~0; 136432#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 131889#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130434#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 130435#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 131200#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 136429#L749-45 assume 1 == ~t6_pc~0; 131426#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 131428#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 136428#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 131644#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 131645#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 130313#L768-45 assume !(1 == ~t7_pc~0); 130315#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 130453#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131274#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 131275#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 131317#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 131318#L787-45 assume !(1 == ~t8_pc~0); 131504#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 130460#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130461#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 136419#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 131198#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 131199#L806-45 assume 1 == ~t9_pc~0; 131751#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 129872#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 130702#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 136417#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 136416#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 136415#L825-45 assume 1 == ~t10_pc~0; 136414#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 136412#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 136411#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 131237#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 131238#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 130080#L844-45 assume !(1 == ~t11_pc~0); 130081#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 130606#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 130607#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 130623#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 131038#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 130120#L863-45 assume 1 == ~t12_pc~0; 130121#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 129720#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 129721#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 130237#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 130238#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 131044#L882-45 assume !(1 == ~t13_pc~0); 130569#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 129739#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 129740#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 130350#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 131577#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131157#L1434-3 assume !(1 == ~M_E~0); 131158#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 133018#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 133017#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 133016#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133015#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 133014#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 133013#L1464-3 assume !(1 == ~T7_E~0); 133012#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 133010#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 131763#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 131646#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 130780#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 130781#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 131469#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 131079#L1504-3 assume !(1 == ~E_1~0); 131080#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 131565#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 131612#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 130703#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 130704#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 131673#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 133627#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 133625#L1544-3 assume !(1 == ~E_9~0); 131649#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 130976#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 130085#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 130086#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 131253#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 131254#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 133592#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 133591#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 133590#L1954 assume !(0 == start_simulation_~tmp~3#1); 131780#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 131781#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 133348#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 133347#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 133346#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 133345#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 133344#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 133342#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 133340#L1935-2 [2022-02-21 04:23:54,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:54,025 INFO L85 PathProgramCache]: Analyzing trace with hash -113531325, now seen corresponding path program 1 times [2022-02-21 04:23:54,025 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:54,025 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280976502] [2022-02-21 04:23:54,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:54,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:54,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:54,052 INFO L290 TraceCheckUtils]: 0: Hoare triple {151876#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,052 INFO L290 TraceCheckUtils]: 1: Hoare triple {151878#(<= 2 ~E_2~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,053 INFO L290 TraceCheckUtils]: 2: Hoare triple {151878#(<= 2 ~E_2~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,053 INFO L290 TraceCheckUtils]: 3: Hoare triple {151878#(<= 2 ~E_2~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,053 INFO L290 TraceCheckUtils]: 4: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,053 INFO L290 TraceCheckUtils]: 5: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,054 INFO L290 TraceCheckUtils]: 6: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,054 INFO L290 TraceCheckUtils]: 7: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,054 INFO L290 TraceCheckUtils]: 8: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,054 INFO L290 TraceCheckUtils]: 9: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,055 INFO L290 TraceCheckUtils]: 10: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,055 INFO L290 TraceCheckUtils]: 11: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,055 INFO L290 TraceCheckUtils]: 12: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,056 INFO L290 TraceCheckUtils]: 13: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,056 INFO L290 TraceCheckUtils]: 14: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,056 INFO L290 TraceCheckUtils]: 15: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,056 INFO L290 TraceCheckUtils]: 16: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,057 INFO L290 TraceCheckUtils]: 17: Hoare triple {151878#(<= 2 ~E_2~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,057 INFO L290 TraceCheckUtils]: 18: Hoare triple {151878#(<= 2 ~E_2~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,057 INFO L290 TraceCheckUtils]: 19: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~M_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,057 INFO L290 TraceCheckUtils]: 20: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T1_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,058 INFO L290 TraceCheckUtils]: 21: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T2_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,058 INFO L290 TraceCheckUtils]: 22: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T3_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,058 INFO L290 TraceCheckUtils]: 23: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T4_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,058 INFO L290 TraceCheckUtils]: 24: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T5_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,059 INFO L290 TraceCheckUtils]: 25: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T6_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,059 INFO L290 TraceCheckUtils]: 26: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T7_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,059 INFO L290 TraceCheckUtils]: 27: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T8_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,060 INFO L290 TraceCheckUtils]: 28: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T9_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,060 INFO L290 TraceCheckUtils]: 29: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T10_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,060 INFO L290 TraceCheckUtils]: 30: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T11_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,060 INFO L290 TraceCheckUtils]: 31: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T12_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,061 INFO L290 TraceCheckUtils]: 32: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~T13_E~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,061 INFO L290 TraceCheckUtils]: 33: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~E_M~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,061 INFO L290 TraceCheckUtils]: 34: Hoare triple {151878#(<= 2 ~E_2~0)} assume !(0 == ~E_1~0); {151878#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:54,061 INFO L290 TraceCheckUtils]: 35: Hoare triple {151878#(<= 2 ~E_2~0)} assume 0 == ~E_2~0;~E_2~0 := 1; {151877#false} is VALID [2022-02-21 04:23:54,061 INFO L290 TraceCheckUtils]: 36: Hoare triple {151877#false} assume !(0 == ~E_3~0); {151877#false} is VALID [2022-02-21 04:23:54,062 INFO L290 TraceCheckUtils]: 37: Hoare triple {151877#false} assume !(0 == ~E_4~0); {151877#false} is VALID [2022-02-21 04:23:54,062 INFO L290 TraceCheckUtils]: 38: Hoare triple {151877#false} assume !(0 == ~E_5~0); {151877#false} is VALID [2022-02-21 04:23:54,062 INFO L290 TraceCheckUtils]: 39: Hoare triple {151877#false} assume !(0 == ~E_6~0); {151877#false} is VALID [2022-02-21 04:23:54,062 INFO L290 TraceCheckUtils]: 40: Hoare triple {151877#false} assume !(0 == ~E_7~0); {151877#false} is VALID [2022-02-21 04:23:54,062 INFO L290 TraceCheckUtils]: 41: Hoare triple {151877#false} assume !(0 == ~E_8~0); {151877#false} is VALID [2022-02-21 04:23:54,062 INFO L290 TraceCheckUtils]: 42: Hoare triple {151877#false} assume !(0 == ~E_9~0); {151877#false} is VALID [2022-02-21 04:23:54,062 INFO L290 TraceCheckUtils]: 43: Hoare triple {151877#false} assume 0 == ~E_10~0;~E_10~0 := 1; {151877#false} is VALID [2022-02-21 04:23:54,062 INFO L290 TraceCheckUtils]: 44: Hoare triple {151877#false} assume !(0 == ~E_11~0); {151877#false} is VALID [2022-02-21 04:23:54,063 INFO L290 TraceCheckUtils]: 45: Hoare triple {151877#false} assume !(0 == ~E_12~0); {151877#false} is VALID [2022-02-21 04:23:54,063 INFO L290 TraceCheckUtils]: 46: Hoare triple {151877#false} assume !(0 == ~E_13~0); {151877#false} is VALID [2022-02-21 04:23:54,063 INFO L290 TraceCheckUtils]: 47: Hoare triple {151877#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {151877#false} is VALID [2022-02-21 04:23:54,063 INFO L290 TraceCheckUtils]: 48: Hoare triple {151877#false} assume !(1 == ~m_pc~0); {151877#false} is VALID [2022-02-21 04:23:54,063 INFO L290 TraceCheckUtils]: 49: Hoare triple {151877#false} is_master_triggered_~__retres1~0#1 := 0; {151877#false} is VALID [2022-02-21 04:23:54,063 INFO L290 TraceCheckUtils]: 50: Hoare triple {151877#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {151877#false} is VALID [2022-02-21 04:23:54,063 INFO L290 TraceCheckUtils]: 51: Hoare triple {151877#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {151877#false} is VALID [2022-02-21 04:23:54,064 INFO L290 TraceCheckUtils]: 52: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp~1#1); {151877#false} is VALID [2022-02-21 04:23:54,064 INFO L290 TraceCheckUtils]: 53: Hoare triple {151877#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {151877#false} is VALID [2022-02-21 04:23:54,064 INFO L290 TraceCheckUtils]: 54: Hoare triple {151877#false} assume 1 == ~t1_pc~0; {151877#false} is VALID [2022-02-21 04:23:54,064 INFO L290 TraceCheckUtils]: 55: Hoare triple {151877#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {151877#false} is VALID [2022-02-21 04:23:54,064 INFO L290 TraceCheckUtils]: 56: Hoare triple {151877#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {151877#false} is VALID [2022-02-21 04:23:54,064 INFO L290 TraceCheckUtils]: 57: Hoare triple {151877#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {151877#false} is VALID [2022-02-21 04:23:54,064 INFO L290 TraceCheckUtils]: 58: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___0~0#1); {151877#false} is VALID [2022-02-21 04:23:54,064 INFO L290 TraceCheckUtils]: 59: Hoare triple {151877#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {151877#false} is VALID [2022-02-21 04:23:54,065 INFO L290 TraceCheckUtils]: 60: Hoare triple {151877#false} assume 1 == ~t2_pc~0; {151877#false} is VALID [2022-02-21 04:23:54,065 INFO L290 TraceCheckUtils]: 61: Hoare triple {151877#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {151877#false} is VALID [2022-02-21 04:23:54,065 INFO L290 TraceCheckUtils]: 62: Hoare triple {151877#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {151877#false} is VALID [2022-02-21 04:23:54,065 INFO L290 TraceCheckUtils]: 63: Hoare triple {151877#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {151877#false} is VALID [2022-02-21 04:23:54,065 INFO L290 TraceCheckUtils]: 64: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___1~0#1); {151877#false} is VALID [2022-02-21 04:23:54,065 INFO L290 TraceCheckUtils]: 65: Hoare triple {151877#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {151877#false} is VALID [2022-02-21 04:23:54,065 INFO L290 TraceCheckUtils]: 66: Hoare triple {151877#false} assume !(1 == ~t3_pc~0); {151877#false} is VALID [2022-02-21 04:23:54,065 INFO L290 TraceCheckUtils]: 67: Hoare triple {151877#false} is_transmit3_triggered_~__retres1~3#1 := 0; {151877#false} is VALID [2022-02-21 04:23:54,066 INFO L290 TraceCheckUtils]: 68: Hoare triple {151877#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {151877#false} is VALID [2022-02-21 04:23:54,066 INFO L290 TraceCheckUtils]: 69: Hoare triple {151877#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {151877#false} is VALID [2022-02-21 04:23:54,066 INFO L290 TraceCheckUtils]: 70: Hoare triple {151877#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {151877#false} is VALID [2022-02-21 04:23:54,066 INFO L290 TraceCheckUtils]: 71: Hoare triple {151877#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {151877#false} is VALID [2022-02-21 04:23:54,066 INFO L290 TraceCheckUtils]: 72: Hoare triple {151877#false} assume 1 == ~t4_pc~0; {151877#false} is VALID [2022-02-21 04:23:54,066 INFO L290 TraceCheckUtils]: 73: Hoare triple {151877#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {151877#false} is VALID [2022-02-21 04:23:54,066 INFO L290 TraceCheckUtils]: 74: Hoare triple {151877#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {151877#false} is VALID [2022-02-21 04:23:54,066 INFO L290 TraceCheckUtils]: 75: Hoare triple {151877#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {151877#false} is VALID [2022-02-21 04:23:54,067 INFO L290 TraceCheckUtils]: 76: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___3~0#1); {151877#false} is VALID [2022-02-21 04:23:54,067 INFO L290 TraceCheckUtils]: 77: Hoare triple {151877#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {151877#false} is VALID [2022-02-21 04:23:54,067 INFO L290 TraceCheckUtils]: 78: Hoare triple {151877#false} assume !(1 == ~t5_pc~0); {151877#false} is VALID [2022-02-21 04:23:54,067 INFO L290 TraceCheckUtils]: 79: Hoare triple {151877#false} is_transmit5_triggered_~__retres1~5#1 := 0; {151877#false} is VALID [2022-02-21 04:23:54,067 INFO L290 TraceCheckUtils]: 80: Hoare triple {151877#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {151877#false} is VALID [2022-02-21 04:23:54,067 INFO L290 TraceCheckUtils]: 81: Hoare triple {151877#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {151877#false} is VALID [2022-02-21 04:23:54,067 INFO L290 TraceCheckUtils]: 82: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___4~0#1); {151877#false} is VALID [2022-02-21 04:23:54,067 INFO L290 TraceCheckUtils]: 83: Hoare triple {151877#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {151877#false} is VALID [2022-02-21 04:23:54,068 INFO L290 TraceCheckUtils]: 84: Hoare triple {151877#false} assume 1 == ~t6_pc~0; {151877#false} is VALID [2022-02-21 04:23:54,068 INFO L290 TraceCheckUtils]: 85: Hoare triple {151877#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {151877#false} is VALID [2022-02-21 04:23:54,068 INFO L290 TraceCheckUtils]: 86: Hoare triple {151877#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {151877#false} is VALID [2022-02-21 04:23:54,068 INFO L290 TraceCheckUtils]: 87: Hoare triple {151877#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {151877#false} is VALID [2022-02-21 04:23:54,068 INFO L290 TraceCheckUtils]: 88: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___5~0#1); {151877#false} is VALID [2022-02-21 04:23:54,068 INFO L290 TraceCheckUtils]: 89: Hoare triple {151877#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {151877#false} is VALID [2022-02-21 04:23:54,068 INFO L290 TraceCheckUtils]: 90: Hoare triple {151877#false} assume !(1 == ~t7_pc~0); {151877#false} is VALID [2022-02-21 04:23:54,068 INFO L290 TraceCheckUtils]: 91: Hoare triple {151877#false} is_transmit7_triggered_~__retres1~7#1 := 0; {151877#false} is VALID [2022-02-21 04:23:54,069 INFO L290 TraceCheckUtils]: 92: Hoare triple {151877#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {151877#false} is VALID [2022-02-21 04:23:54,069 INFO L290 TraceCheckUtils]: 93: Hoare triple {151877#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {151877#false} is VALID [2022-02-21 04:23:54,069 INFO L290 TraceCheckUtils]: 94: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___6~0#1); {151877#false} is VALID [2022-02-21 04:23:54,069 INFO L290 TraceCheckUtils]: 95: Hoare triple {151877#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {151877#false} is VALID [2022-02-21 04:23:54,069 INFO L290 TraceCheckUtils]: 96: Hoare triple {151877#false} assume 1 == ~t8_pc~0; {151877#false} is VALID [2022-02-21 04:23:54,069 INFO L290 TraceCheckUtils]: 97: Hoare triple {151877#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {151877#false} is VALID [2022-02-21 04:23:54,069 INFO L290 TraceCheckUtils]: 98: Hoare triple {151877#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {151877#false} is VALID [2022-02-21 04:23:54,069 INFO L290 TraceCheckUtils]: 99: Hoare triple {151877#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {151877#false} is VALID [2022-02-21 04:23:54,070 INFO L290 TraceCheckUtils]: 100: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___7~0#1); {151877#false} is VALID [2022-02-21 04:23:54,070 INFO L290 TraceCheckUtils]: 101: Hoare triple {151877#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {151877#false} is VALID [2022-02-21 04:23:54,070 INFO L290 TraceCheckUtils]: 102: Hoare triple {151877#false} assume 1 == ~t9_pc~0; {151877#false} is VALID [2022-02-21 04:23:54,070 INFO L290 TraceCheckUtils]: 103: Hoare triple {151877#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {151877#false} is VALID [2022-02-21 04:23:54,070 INFO L290 TraceCheckUtils]: 104: Hoare triple {151877#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {151877#false} is VALID [2022-02-21 04:23:54,070 INFO L290 TraceCheckUtils]: 105: Hoare triple {151877#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {151877#false} is VALID [2022-02-21 04:23:54,070 INFO L290 TraceCheckUtils]: 106: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___8~0#1); {151877#false} is VALID [2022-02-21 04:23:54,070 INFO L290 TraceCheckUtils]: 107: Hoare triple {151877#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {151877#false} is VALID [2022-02-21 04:23:54,071 INFO L290 TraceCheckUtils]: 108: Hoare triple {151877#false} assume !(1 == ~t10_pc~0); {151877#false} is VALID [2022-02-21 04:23:54,071 INFO L290 TraceCheckUtils]: 109: Hoare triple {151877#false} is_transmit10_triggered_~__retres1~10#1 := 0; {151877#false} is VALID [2022-02-21 04:23:54,071 INFO L290 TraceCheckUtils]: 110: Hoare triple {151877#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {151877#false} is VALID [2022-02-21 04:23:54,071 INFO L290 TraceCheckUtils]: 111: Hoare triple {151877#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {151877#false} is VALID [2022-02-21 04:23:54,071 INFO L290 TraceCheckUtils]: 112: Hoare triple {151877#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {151877#false} is VALID [2022-02-21 04:23:54,071 INFO L290 TraceCheckUtils]: 113: Hoare triple {151877#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {151877#false} is VALID [2022-02-21 04:23:54,071 INFO L290 TraceCheckUtils]: 114: Hoare triple {151877#false} assume 1 == ~t11_pc~0; {151877#false} is VALID [2022-02-21 04:23:54,071 INFO L290 TraceCheckUtils]: 115: Hoare triple {151877#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {151877#false} is VALID [2022-02-21 04:23:54,072 INFO L290 TraceCheckUtils]: 116: Hoare triple {151877#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {151877#false} is VALID [2022-02-21 04:23:54,072 INFO L290 TraceCheckUtils]: 117: Hoare triple {151877#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {151877#false} is VALID [2022-02-21 04:23:54,072 INFO L290 TraceCheckUtils]: 118: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___10~0#1); {151877#false} is VALID [2022-02-21 04:23:54,072 INFO L290 TraceCheckUtils]: 119: Hoare triple {151877#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {151877#false} is VALID [2022-02-21 04:23:54,072 INFO L290 TraceCheckUtils]: 120: Hoare triple {151877#false} assume !(1 == ~t12_pc~0); {151877#false} is VALID [2022-02-21 04:23:54,072 INFO L290 TraceCheckUtils]: 121: Hoare triple {151877#false} is_transmit12_triggered_~__retres1~12#1 := 0; {151877#false} is VALID [2022-02-21 04:23:54,072 INFO L290 TraceCheckUtils]: 122: Hoare triple {151877#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {151877#false} is VALID [2022-02-21 04:23:54,073 INFO L290 TraceCheckUtils]: 123: Hoare triple {151877#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {151877#false} is VALID [2022-02-21 04:23:54,073 INFO L290 TraceCheckUtils]: 124: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___11~0#1); {151877#false} is VALID [2022-02-21 04:23:54,073 INFO L290 TraceCheckUtils]: 125: Hoare triple {151877#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {151877#false} is VALID [2022-02-21 04:23:54,073 INFO L290 TraceCheckUtils]: 126: Hoare triple {151877#false} assume 1 == ~t13_pc~0; {151877#false} is VALID [2022-02-21 04:23:54,073 INFO L290 TraceCheckUtils]: 127: Hoare triple {151877#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {151877#false} is VALID [2022-02-21 04:23:54,073 INFO L290 TraceCheckUtils]: 128: Hoare triple {151877#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {151877#false} is VALID [2022-02-21 04:23:54,073 INFO L290 TraceCheckUtils]: 129: Hoare triple {151877#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {151877#false} is VALID [2022-02-21 04:23:54,073 INFO L290 TraceCheckUtils]: 130: Hoare triple {151877#false} assume !(0 != activate_threads_~tmp___12~0#1); {151877#false} is VALID [2022-02-21 04:23:54,073 INFO L290 TraceCheckUtils]: 131: Hoare triple {151877#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {151877#false} is VALID [2022-02-21 04:23:54,074 INFO L290 TraceCheckUtils]: 132: Hoare triple {151877#false} assume !(1 == ~M_E~0); {151877#false} is VALID [2022-02-21 04:23:54,074 INFO L290 TraceCheckUtils]: 133: Hoare triple {151877#false} assume !(1 == ~T1_E~0); {151877#false} is VALID [2022-02-21 04:23:54,074 INFO L290 TraceCheckUtils]: 134: Hoare triple {151877#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {151877#false} is VALID [2022-02-21 04:23:54,074 INFO L290 TraceCheckUtils]: 135: Hoare triple {151877#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {151877#false} is VALID [2022-02-21 04:23:54,074 INFO L290 TraceCheckUtils]: 136: Hoare triple {151877#false} assume !(1 == ~T4_E~0); {151877#false} is VALID [2022-02-21 04:23:54,074 INFO L290 TraceCheckUtils]: 137: Hoare triple {151877#false} assume !(1 == ~T5_E~0); {151877#false} is VALID [2022-02-21 04:23:54,074 INFO L290 TraceCheckUtils]: 138: Hoare triple {151877#false} assume !(1 == ~T6_E~0); {151877#false} is VALID [2022-02-21 04:23:54,074 INFO L290 TraceCheckUtils]: 139: Hoare triple {151877#false} assume !(1 == ~T7_E~0); {151877#false} is VALID [2022-02-21 04:23:54,075 INFO L290 TraceCheckUtils]: 140: Hoare triple {151877#false} assume !(1 == ~T8_E~0); {151877#false} is VALID [2022-02-21 04:23:54,075 INFO L290 TraceCheckUtils]: 141: Hoare triple {151877#false} assume !(1 == ~T9_E~0); {151877#false} is VALID [2022-02-21 04:23:54,075 INFO L290 TraceCheckUtils]: 142: Hoare triple {151877#false} assume !(1 == ~T10_E~0); {151877#false} is VALID [2022-02-21 04:23:54,075 INFO L290 TraceCheckUtils]: 143: Hoare triple {151877#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {151877#false} is VALID [2022-02-21 04:23:54,075 INFO L290 TraceCheckUtils]: 144: Hoare triple {151877#false} assume !(1 == ~T12_E~0); {151877#false} is VALID [2022-02-21 04:23:54,075 INFO L290 TraceCheckUtils]: 145: Hoare triple {151877#false} assume !(1 == ~T13_E~0); {151877#false} is VALID [2022-02-21 04:23:54,075 INFO L290 TraceCheckUtils]: 146: Hoare triple {151877#false} assume !(1 == ~E_M~0); {151877#false} is VALID [2022-02-21 04:23:54,076 INFO L290 TraceCheckUtils]: 147: Hoare triple {151877#false} assume !(1 == ~E_1~0); {151877#false} is VALID [2022-02-21 04:23:54,076 INFO L290 TraceCheckUtils]: 148: Hoare triple {151877#false} assume !(1 == ~E_2~0); {151877#false} is VALID [2022-02-21 04:23:54,076 INFO L290 TraceCheckUtils]: 149: Hoare triple {151877#false} assume !(1 == ~E_3~0); {151877#false} is VALID [2022-02-21 04:23:54,076 INFO L290 TraceCheckUtils]: 150: Hoare triple {151877#false} assume !(1 == ~E_4~0); {151877#false} is VALID [2022-02-21 04:23:54,076 INFO L290 TraceCheckUtils]: 151: Hoare triple {151877#false} assume 1 == ~E_5~0;~E_5~0 := 2; {151877#false} is VALID [2022-02-21 04:23:54,076 INFO L290 TraceCheckUtils]: 152: Hoare triple {151877#false} assume !(1 == ~E_6~0); {151877#false} is VALID [2022-02-21 04:23:54,076 INFO L290 TraceCheckUtils]: 153: Hoare triple {151877#false} assume !(1 == ~E_7~0); {151877#false} is VALID [2022-02-21 04:23:54,076 INFO L290 TraceCheckUtils]: 154: Hoare triple {151877#false} assume !(1 == ~E_8~0); {151877#false} is VALID [2022-02-21 04:23:54,077 INFO L290 TraceCheckUtils]: 155: Hoare triple {151877#false} assume !(1 == ~E_9~0); {151877#false} is VALID [2022-02-21 04:23:54,077 INFO L290 TraceCheckUtils]: 156: Hoare triple {151877#false} assume !(1 == ~E_10~0); {151877#false} is VALID [2022-02-21 04:23:54,077 INFO L290 TraceCheckUtils]: 157: Hoare triple {151877#false} assume !(1 == ~E_11~0); {151877#false} is VALID [2022-02-21 04:23:54,077 INFO L290 TraceCheckUtils]: 158: Hoare triple {151877#false} assume !(1 == ~E_12~0); {151877#false} is VALID [2022-02-21 04:23:54,077 INFO L290 TraceCheckUtils]: 159: Hoare triple {151877#false} assume 1 == ~E_13~0;~E_13~0 := 2; {151877#false} is VALID [2022-02-21 04:23:54,077 INFO L290 TraceCheckUtils]: 160: Hoare triple {151877#false} assume { :end_inline_reset_delta_events } true; {151877#false} is VALID [2022-02-21 04:23:54,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:54,078 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:54,078 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280976502] [2022-02-21 04:23:54,078 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280976502] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:54,078 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:54,078 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:54,078 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1866915472] [2022-02-21 04:23:54,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:54,079 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:54,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:54,079 INFO L85 PathProgramCache]: Analyzing trace with hash -1101617054, now seen corresponding path program 1 times [2022-02-21 04:23:54,079 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:54,079 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119981228] [2022-02-21 04:23:54,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:54,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:54,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:54,104 INFO L290 TraceCheckUtils]: 0: Hoare triple {151879#true} assume !false; {151879#true} is VALID [2022-02-21 04:23:54,105 INFO L290 TraceCheckUtils]: 1: Hoare triple {151879#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {151879#true} is VALID [2022-02-21 04:23:54,105 INFO L290 TraceCheckUtils]: 2: Hoare triple {151879#true} assume !false; {151879#true} is VALID [2022-02-21 04:23:54,105 INFO L290 TraceCheckUtils]: 3: Hoare triple {151879#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {151879#true} is VALID [2022-02-21 04:23:54,105 INFO L290 TraceCheckUtils]: 4: Hoare triple {151879#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {151879#true} is VALID [2022-02-21 04:23:54,105 INFO L290 TraceCheckUtils]: 5: Hoare triple {151879#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {151879#true} is VALID [2022-02-21 04:23:54,105 INFO L290 TraceCheckUtils]: 6: Hoare triple {151879#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {151879#true} is VALID [2022-02-21 04:23:54,105 INFO L290 TraceCheckUtils]: 7: Hoare triple {151879#true} assume !(0 != eval_~tmp~0#1); {151879#true} is VALID [2022-02-21 04:23:54,106 INFO L290 TraceCheckUtils]: 8: Hoare triple {151879#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {151879#true} is VALID [2022-02-21 04:23:54,106 INFO L290 TraceCheckUtils]: 9: Hoare triple {151879#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {151879#true} is VALID [2022-02-21 04:23:54,106 INFO L290 TraceCheckUtils]: 10: Hoare triple {151879#true} assume !(0 == ~M_E~0); {151879#true} is VALID [2022-02-21 04:23:54,106 INFO L290 TraceCheckUtils]: 11: Hoare triple {151879#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {151879#true} is VALID [2022-02-21 04:23:54,106 INFO L290 TraceCheckUtils]: 12: Hoare triple {151879#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {151879#true} is VALID [2022-02-21 04:23:54,106 INFO L290 TraceCheckUtils]: 13: Hoare triple {151879#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {151879#true} is VALID [2022-02-21 04:23:54,106 INFO L290 TraceCheckUtils]: 14: Hoare triple {151879#true} assume !(0 == ~T4_E~0); {151879#true} is VALID [2022-02-21 04:23:54,106 INFO L290 TraceCheckUtils]: 15: Hoare triple {151879#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {151879#true} is VALID [2022-02-21 04:23:54,107 INFO L290 TraceCheckUtils]: 16: Hoare triple {151879#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {151879#true} is VALID [2022-02-21 04:23:54,107 INFO L290 TraceCheckUtils]: 17: Hoare triple {151879#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,107 INFO L290 TraceCheckUtils]: 18: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T8_E~0); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,107 INFO L290 TraceCheckUtils]: 19: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,108 INFO L290 TraceCheckUtils]: 20: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,108 INFO L290 TraceCheckUtils]: 21: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,108 INFO L290 TraceCheckUtils]: 22: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,109 INFO L290 TraceCheckUtils]: 23: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,109 INFO L290 TraceCheckUtils]: 24: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,109 INFO L290 TraceCheckUtils]: 25: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,109 INFO L290 TraceCheckUtils]: 26: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,110 INFO L290 TraceCheckUtils]: 27: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,110 INFO L290 TraceCheckUtils]: 28: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,110 INFO L290 TraceCheckUtils]: 29: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,110 INFO L290 TraceCheckUtils]: 30: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,111 INFO L290 TraceCheckUtils]: 31: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,111 INFO L290 TraceCheckUtils]: 32: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,111 INFO L290 TraceCheckUtils]: 33: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,111 INFO L290 TraceCheckUtils]: 34: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,112 INFO L290 TraceCheckUtils]: 35: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,112 INFO L290 TraceCheckUtils]: 36: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,112 INFO L290 TraceCheckUtils]: 37: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,112 INFO L290 TraceCheckUtils]: 38: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,113 INFO L290 TraceCheckUtils]: 39: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~m_pc~0); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,113 INFO L290 TraceCheckUtils]: 40: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,113 INFO L290 TraceCheckUtils]: 41: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,113 INFO L290 TraceCheckUtils]: 42: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,114 INFO L290 TraceCheckUtils]: 43: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,114 INFO L290 TraceCheckUtils]: 44: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,114 INFO L290 TraceCheckUtils]: 45: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,114 INFO L290 TraceCheckUtils]: 46: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,115 INFO L290 TraceCheckUtils]: 47: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,115 INFO L290 TraceCheckUtils]: 48: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,115 INFO L290 TraceCheckUtils]: 49: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,116 INFO L290 TraceCheckUtils]: 50: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,116 INFO L290 TraceCheckUtils]: 51: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t2_pc~0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,116 INFO L290 TraceCheckUtils]: 52: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,116 INFO L290 TraceCheckUtils]: 53: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,117 INFO L290 TraceCheckUtils]: 54: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,117 INFO L290 TraceCheckUtils]: 55: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,117 INFO L290 TraceCheckUtils]: 56: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,117 INFO L290 TraceCheckUtils]: 57: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,118 INFO L290 TraceCheckUtils]: 58: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,118 INFO L290 TraceCheckUtils]: 59: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,118 INFO L290 TraceCheckUtils]: 60: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,118 INFO L290 TraceCheckUtils]: 61: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,119 INFO L290 TraceCheckUtils]: 62: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,119 INFO L290 TraceCheckUtils]: 63: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,119 INFO L290 TraceCheckUtils]: 64: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,119 INFO L290 TraceCheckUtils]: 65: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,120 INFO L290 TraceCheckUtils]: 66: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,120 INFO L290 TraceCheckUtils]: 67: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,120 INFO L290 TraceCheckUtils]: 68: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,120 INFO L290 TraceCheckUtils]: 69: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,121 INFO L290 TraceCheckUtils]: 70: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,121 INFO L290 TraceCheckUtils]: 71: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,121 INFO L290 TraceCheckUtils]: 72: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,122 INFO L290 TraceCheckUtils]: 73: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,122 INFO L290 TraceCheckUtils]: 74: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,123 INFO L290 TraceCheckUtils]: 75: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,124 INFO L290 TraceCheckUtils]: 76: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,124 INFO L290 TraceCheckUtils]: 77: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,124 INFO L290 TraceCheckUtils]: 78: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,125 INFO L290 TraceCheckUtils]: 79: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,125 INFO L290 TraceCheckUtils]: 80: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,125 INFO L290 TraceCheckUtils]: 81: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,126 INFO L290 TraceCheckUtils]: 82: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,126 INFO L290 TraceCheckUtils]: 83: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,126 INFO L290 TraceCheckUtils]: 84: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,126 INFO L290 TraceCheckUtils]: 85: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,127 INFO L290 TraceCheckUtils]: 86: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,127 INFO L290 TraceCheckUtils]: 87: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t8_pc~0); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,127 INFO L290 TraceCheckUtils]: 88: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,127 INFO L290 TraceCheckUtils]: 89: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,128 INFO L290 TraceCheckUtils]: 90: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,128 INFO L290 TraceCheckUtils]: 91: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,128 INFO L290 TraceCheckUtils]: 92: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,129 INFO L290 TraceCheckUtils]: 93: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,129 INFO L290 TraceCheckUtils]: 94: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,129 INFO L290 TraceCheckUtils]: 95: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,129 INFO L290 TraceCheckUtils]: 96: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,130 INFO L290 TraceCheckUtils]: 97: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,130 INFO L290 TraceCheckUtils]: 98: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,130 INFO L290 TraceCheckUtils]: 99: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t10_pc~0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,130 INFO L290 TraceCheckUtils]: 100: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,131 INFO L290 TraceCheckUtils]: 101: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,131 INFO L290 TraceCheckUtils]: 102: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,131 INFO L290 TraceCheckUtils]: 103: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,131 INFO L290 TraceCheckUtils]: 104: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,132 INFO L290 TraceCheckUtils]: 105: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,132 INFO L290 TraceCheckUtils]: 106: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,132 INFO L290 TraceCheckUtils]: 107: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,132 INFO L290 TraceCheckUtils]: 108: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,133 INFO L290 TraceCheckUtils]: 109: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,133 INFO L290 TraceCheckUtils]: 110: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,133 INFO L290 TraceCheckUtils]: 111: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,134 INFO L290 TraceCheckUtils]: 112: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,134 INFO L290 TraceCheckUtils]: 113: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,134 INFO L290 TraceCheckUtils]: 114: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,134 INFO L290 TraceCheckUtils]: 115: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,135 INFO L290 TraceCheckUtils]: 116: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,135 INFO L290 TraceCheckUtils]: 117: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t13_pc~0); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,135 INFO L290 TraceCheckUtils]: 118: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,135 INFO L290 TraceCheckUtils]: 119: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,136 INFO L290 TraceCheckUtils]: 120: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,136 INFO L290 TraceCheckUtils]: 121: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,136 INFO L290 TraceCheckUtils]: 122: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,137 INFO L290 TraceCheckUtils]: 123: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~M_E~0); {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,137 INFO L290 TraceCheckUtils]: 124: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,137 INFO L290 TraceCheckUtils]: 125: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,137 INFO L290 TraceCheckUtils]: 126: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,138 INFO L290 TraceCheckUtils]: 127: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,138 INFO L290 TraceCheckUtils]: 128: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,138 INFO L290 TraceCheckUtils]: 129: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {151881#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:23:54,139 INFO L290 TraceCheckUtils]: 130: Hoare triple {151881#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {151880#false} is VALID [2022-02-21 04:23:54,139 INFO L290 TraceCheckUtils]: 131: Hoare triple {151880#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,139 INFO L290 TraceCheckUtils]: 132: Hoare triple {151880#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,139 INFO L290 TraceCheckUtils]: 133: Hoare triple {151880#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,139 INFO L290 TraceCheckUtils]: 134: Hoare triple {151880#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,139 INFO L290 TraceCheckUtils]: 135: Hoare triple {151880#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,139 INFO L290 TraceCheckUtils]: 136: Hoare triple {151880#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,139 INFO L290 TraceCheckUtils]: 137: Hoare triple {151880#false} assume 1 == ~E_M~0;~E_M~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,140 INFO L290 TraceCheckUtils]: 138: Hoare triple {151880#false} assume !(1 == ~E_1~0); {151880#false} is VALID [2022-02-21 04:23:54,140 INFO L290 TraceCheckUtils]: 139: Hoare triple {151880#false} assume 1 == ~E_2~0;~E_2~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,140 INFO L290 TraceCheckUtils]: 140: Hoare triple {151880#false} assume 1 == ~E_3~0;~E_3~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,140 INFO L290 TraceCheckUtils]: 141: Hoare triple {151880#false} assume 1 == ~E_4~0;~E_4~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,140 INFO L290 TraceCheckUtils]: 142: Hoare triple {151880#false} assume 1 == ~E_5~0;~E_5~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,140 INFO L290 TraceCheckUtils]: 143: Hoare triple {151880#false} assume 1 == ~E_6~0;~E_6~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,140 INFO L290 TraceCheckUtils]: 144: Hoare triple {151880#false} assume 1 == ~E_7~0;~E_7~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,140 INFO L290 TraceCheckUtils]: 145: Hoare triple {151880#false} assume 1 == ~E_8~0;~E_8~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,141 INFO L290 TraceCheckUtils]: 146: Hoare triple {151880#false} assume !(1 == ~E_9~0); {151880#false} is VALID [2022-02-21 04:23:54,141 INFO L290 TraceCheckUtils]: 147: Hoare triple {151880#false} assume 1 == ~E_10~0;~E_10~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,141 INFO L290 TraceCheckUtils]: 148: Hoare triple {151880#false} assume 1 == ~E_11~0;~E_11~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,141 INFO L290 TraceCheckUtils]: 149: Hoare triple {151880#false} assume 1 == ~E_12~0;~E_12~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,141 INFO L290 TraceCheckUtils]: 150: Hoare triple {151880#false} assume 1 == ~E_13~0;~E_13~0 := 2; {151880#false} is VALID [2022-02-21 04:23:54,141 INFO L290 TraceCheckUtils]: 151: Hoare triple {151880#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {151880#false} is VALID [2022-02-21 04:23:54,141 INFO L290 TraceCheckUtils]: 152: Hoare triple {151880#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {151880#false} is VALID [2022-02-21 04:23:54,141 INFO L290 TraceCheckUtils]: 153: Hoare triple {151880#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {151880#false} is VALID [2022-02-21 04:23:54,142 INFO L290 TraceCheckUtils]: 154: Hoare triple {151880#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {151880#false} is VALID [2022-02-21 04:23:54,142 INFO L290 TraceCheckUtils]: 155: Hoare triple {151880#false} assume !(0 == start_simulation_~tmp~3#1); {151880#false} is VALID [2022-02-21 04:23:54,142 INFO L290 TraceCheckUtils]: 156: Hoare triple {151880#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {151880#false} is VALID [2022-02-21 04:23:54,142 INFO L290 TraceCheckUtils]: 157: Hoare triple {151880#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {151880#false} is VALID [2022-02-21 04:23:54,142 INFO L290 TraceCheckUtils]: 158: Hoare triple {151880#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {151880#false} is VALID [2022-02-21 04:23:54,142 INFO L290 TraceCheckUtils]: 159: Hoare triple {151880#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {151880#false} is VALID [2022-02-21 04:23:54,142 INFO L290 TraceCheckUtils]: 160: Hoare triple {151880#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {151880#false} is VALID [2022-02-21 04:23:54,142 INFO L290 TraceCheckUtils]: 161: Hoare triple {151880#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {151880#false} is VALID [2022-02-21 04:23:54,143 INFO L290 TraceCheckUtils]: 162: Hoare triple {151880#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {151880#false} is VALID [2022-02-21 04:23:54,143 INFO L290 TraceCheckUtils]: 163: Hoare triple {151880#false} assume !(0 != start_simulation_~tmp___0~1#1); {151880#false} is VALID [2022-02-21 04:23:54,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:54,143 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:54,143 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119981228] [2022-02-21 04:23:54,143 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119981228] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:54,144 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:54,144 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:54,144 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854502928] [2022-02-21 04:23:54,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:54,144 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:54,144 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:54,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:54,145 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:54,145 INFO L87 Difference]: Start difference. First operand 7385 states and 10846 transitions. cyclomatic complexity: 3463 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:56,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:56,638 INFO L93 Difference]: Finished difference Result 7385 states and 10772 transitions. [2022-02-21 04:23:56,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:56,638 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:56,723 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:56,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7385 states and 10772 transitions. [2022-02-21 04:23:58,063 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2022-02-21 04:23:59,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7385 states to 7385 states and 10772 transitions. [2022-02-21 04:23:59,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7385 [2022-02-21 04:23:59,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7385 [2022-02-21 04:23:59,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7385 states and 10772 transitions. [2022-02-21 04:23:59,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:59,247 INFO L681 BuchiCegarLoop]: Abstraction has 7385 states and 10772 transitions. [2022-02-21 04:23:59,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7385 states and 10772 transitions. [2022-02-21 04:23:59,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7385 to 7385. [2022-02-21 04:23:59,305 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:59,312 INFO L82 GeneralOperation]: Start isEquivalent. First operand 7385 states and 10772 transitions. Second operand has 7385 states, 7385 states have (on average 1.4586323628977658) internal successors, (10772), 7384 states have internal predecessors, (10772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:59,318 INFO L74 IsIncluded]: Start isIncluded. First operand 7385 states and 10772 transitions. Second operand has 7385 states, 7385 states have (on average 1.4586323628977658) internal successors, (10772), 7384 states have internal predecessors, (10772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:59,324 INFO L87 Difference]: Start difference. First operand 7385 states and 10772 transitions. Second operand has 7385 states, 7385 states have (on average 1.4586323628977658) internal successors, (10772), 7384 states have internal predecessors, (10772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:00,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:00,421 INFO L93 Difference]: Finished difference Result 7385 states and 10772 transitions. [2022-02-21 04:24:00,421 INFO L276 IsEmpty]: Start isEmpty. Operand 7385 states and 10772 transitions. [2022-02-21 04:24:00,426 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:00,426 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:00,432 INFO L74 IsIncluded]: Start isIncluded. First operand has 7385 states, 7385 states have (on average 1.4586323628977658) internal successors, (10772), 7384 states have internal predecessors, (10772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7385 states and 10772 transitions. [2022-02-21 04:24:00,437 INFO L87 Difference]: Start difference. First operand has 7385 states, 7385 states have (on average 1.4586323628977658) internal successors, (10772), 7384 states have internal predecessors, (10772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7385 states and 10772 transitions. [2022-02-21 04:24:01,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:01,575 INFO L93 Difference]: Finished difference Result 7385 states and 10772 transitions. [2022-02-21 04:24:01,575 INFO L276 IsEmpty]: Start isEmpty. Operand 7385 states and 10772 transitions. [2022-02-21 04:24:01,580 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:01,580 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:01,580 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:01,580 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:01,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7385 states, 7385 states have (on average 1.4586323628977658) internal successors, (10772), 7384 states have internal predecessors, (10772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7385 states to 7385 states and 10772 transitions. [2022-02-21 04:24:02,848 INFO L704 BuchiCegarLoop]: Abstraction has 7385 states and 10772 transitions. [2022-02-21 04:24:02,848 INFO L587 BuchiCegarLoop]: Abstraction has 7385 states and 10772 transitions. [2022-02-21 04:24:02,849 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2022-02-21 04:24:02,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7385 states and 10772 transitions. [2022-02-21 04:24:02,860 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2022-02-21 04:24:02,860 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:02,860 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:02,862 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,866 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,866 INFO L791 eck$LassoCheckResult]: Stem: 160148#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 160149#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 159876#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 159877#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 161470#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 161471#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 160067#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 160068#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 160102#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 160994#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 160995#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 161131#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 161132#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 159882#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 159883#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 161180#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 160422#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 160423#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 161061#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 161443#L1286 assume !(0 == ~M_E~0); 161263#L1286-2 assume !(0 == ~T1_E~0); 159791#L1291-1 assume !(0 == ~T2_E~0); 159792#L1296-1 assume !(0 == ~T3_E~0); 160514#L1301-1 assume !(0 == ~T4_E~0); 160515#L1306-1 assume !(0 == ~T5_E~0); 161070#L1311-1 assume !(0 == ~T6_E~0); 159750#L1316-1 assume !(0 == ~T7_E~0); 159751#L1321-1 assume !(0 == ~T8_E~0); 160537#L1326-1 assume !(0 == ~T9_E~0); 159565#L1331-1 assume !(0 == ~T10_E~0); 159271#L1336-1 assume !(0 == ~T11_E~0); 159272#L1341-1 assume !(0 == ~T12_E~0); 159323#L1346-1 assume !(0 == ~T13_E~0); 159324#L1351-1 assume !(0 == ~E_M~0); 159696#L1356-1 assume !(0 == ~E_1~0); 159697#L1361-1 assume !(0 == ~E_2~0); 161381#L1366-1 assume !(0 == ~E_3~0); 159743#L1371-1 assume !(0 == ~E_4~0); 159744#L1376-1 assume !(0 == ~E_5~0); 160579#L1381-1 assume !(0 == ~E_6~0); 160580#L1386-1 assume !(0 == ~E_7~0); 161430#L1391-1 assume !(0 == ~E_8~0); 161454#L1396-1 assume !(0 == ~E_9~0); 160458#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 160459#L1406-1 assume !(0 == ~E_11~0); 160782#L1411-1 assume !(0 == ~E_12~0); 160783#L1416-1 assume !(0 == ~E_13~0); 160379#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 160211#L635 assume !(1 == ~m_pc~0); 159341#L635-2 is_master_triggered_~__retres1~0#1 := 0; 159342#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159691#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 160341#L1598 assume !(0 != activate_threads_~tmp~1#1); 159520#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159521#L654 assume 1 == ~t1_pc~0; 160234#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 160235#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 161420#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 160318#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 160319#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159568#L673 assume !(1 == ~t2_pc~0); 159570#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 160745#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160746#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 161481#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 161492#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 160403#L692 assume !(1 == ~t3_pc~0); 160213#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 160214#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160069#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 160036#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 160037#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159593#L711 assume 1 == ~t4_pc~0; 159594#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 160082#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 160556#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 159296#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 159297#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 161469#L730 assume !(1 == ~t5_pc~0); 160675#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 159475#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159476#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 159603#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 159604#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159946#L749 assume 1 == ~t6_pc~0; 159720#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 159480#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 159912#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 159913#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 160140#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 159276#L768 assume !(1 == ~t7_pc~0); 159277#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 160604#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 159513#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 159514#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 160626#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 159752#L787 assume 1 == ~t8_pc~0; 159753#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 161017#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 161215#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 161216#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 159321#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 159322#L806 assume 1 == ~t9_pc~0; 161029#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 159356#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 159357#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 159605#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 159606#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 161007#L825 assume !(1 == ~t10_pc~0); 161008#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 160570#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 160571#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 159692#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 159693#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 160287#L844 assume 1 == ~t11_pc~0; 159968#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 159969#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 160347#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 160348#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 160988#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 160989#L863 assume !(1 == ~t12_pc~0); 159456#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 159455#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 159682#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 161103#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 161104#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 160417#L882 assume 1 == ~t13_pc~0; 160418#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 160716#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 161326#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 161063#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 160703#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160704#L1434 assume !(1 == ~M_E~0); 161340#L1434-2 assume !(1 == ~T1_E~0); 161479#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 161480#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 165662#L1449-1 assume !(1 == ~T4_E~0); 165661#L1454-1 assume !(1 == ~T5_E~0); 165660#L1459-1 assume !(1 == ~T6_E~0); 165659#L1464-1 assume !(1 == ~T7_E~0); 165658#L1469-1 assume !(1 == ~T8_E~0); 160717#L1474-1 assume !(1 == ~T9_E~0); 165657#L1479-1 assume !(1 == ~T10_E~0); 165656#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 165655#L1489-1 assume !(1 == ~T12_E~0); 165654#L1494-1 assume !(1 == ~T13_E~0); 165653#L1499-1 assume !(1 == ~E_M~0); 165652#L1504-1 assume !(1 == ~E_1~0); 165651#L1509-1 assume !(1 == ~E_2~0); 165650#L1514-1 assume !(1 == ~E_3~0); 165649#L1519-1 assume !(1 == ~E_4~0); 165648#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 165647#L1529-1 assume !(1 == ~E_6~0); 165646#L1534-1 assume !(1 == ~E_7~0); 165645#L1539-1 assume !(1 == ~E_8~0); 165644#L1544-1 assume !(1 == ~E_9~0); 165643#L1549-1 assume !(1 == ~E_10~0); 165642#L1554-1 assume !(1 == ~E_11~0); 165641#L1559-1 assume !(1 == ~E_12~0); 165640#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 164391#L1569-1 assume { :end_inline_reset_delta_events } true; 164386#L1935-2 [2022-02-21 04:24:02,867 INFO L793 eck$LassoCheckResult]: Loop: 164386#L1935-2 assume !false; 159385#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 159386#L1261 assume !false; 160641#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 160642#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 159516#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 159685#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 159686#L1074 assume !(0 != eval_~tmp~0#1); 160048#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 160670#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 161127#L1286-3 assume !(0 == ~M_E~0); 161199#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 160862#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 160863#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 161447#L1301-3 assume !(0 == ~T4_E~0); 161372#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 160334#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 159620#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 159621#L1321-3 assume !(0 == ~T8_E~0); 159726#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 160480#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 160760#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 160761#L1341-3 assume !(0 == ~T12_E~0); 160024#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 160015#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 159958#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 159959#L1361-3 assume !(0 == ~E_2~0); 160560#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 159311#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 159312#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 161138#L1381-3 assume !(0 == ~E_6~0); 160960#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 160961#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 161182#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 161183#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 159690#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 159522#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 159523#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 160156#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159400#L635-45 assume !(1 == ~m_pc~0); 159402#L635-47 is_master_triggered_~__retres1~0#1 := 0; 160203#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160705#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 160987#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 159708#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159709#L654-45 assume 1 == ~t1_pc~0; 160552#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 160933#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159363#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 159364#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 159389#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160224#L673-45 assume !(1 == ~t2_pc~0); 160225#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 160563#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160564#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 161295#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 161060#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159835#L692-45 assume !(1 == ~t3_pc~0); 159560#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 159561#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160632#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 159889#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 159890#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 160210#L711-45 assume 1 == ~t4_pc~0; 160338#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 160339#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 160185#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 160186#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 160605#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159733#L730-45 assume 1 == ~t5_pc~0; 159571#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 159572#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159982#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 159983#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 160770#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159544#L749-45 assume 1 == ~t6_pc~0; 159546#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 161011#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 160740#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 160741#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 160913#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 159861#L768-45 assume 1 == ~t7_pc~0; 159862#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 160001#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 160848#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 160849#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 160892#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 160893#L787-45 assume !(1 == ~t8_pc~0); 161090#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 160008#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 160009#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 162978#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 160768#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 160769#L806-45 assume 1 == ~t9_pc~0; 161444#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 163946#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 161033#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 160078#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 159986#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 159987#L825-45 assume 1 == ~t10_pc~0; 161459#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 163935#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 163933#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 162768#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 162769#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 162761#L844-45 assume !(1 == ~t11_pc~0); 162762#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 162754#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 162755#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 162750#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 162751#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 162745#L863-45 assume 1 == ~t12_pc~0; 162746#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 162740#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 162741#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 162736#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 162737#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 162731#L882-45 assume !(1 == ~t13_pc~0); 162732#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 162726#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 162727#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 162722#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 162723#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160723#L1434-3 assume !(1 == ~M_E~0); 160724#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 160932#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 159582#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 159583#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 159745#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 160712#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 160713#L1464-3 assume !(1 == ~T7_E~0); 161240#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 161140#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 161141#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 161376#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 165695#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 165693#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 165691#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 165689#L1504-3 assume !(1 == ~E_1~0); 165687#L1509-3 assume !(1 == ~E_2~0); 165685#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 161494#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 160254#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 160255#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 161399#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 160569#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 160002#L1544-3 assume !(1 == ~E_9~0); 160003#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 163902#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 163901#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 163900#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 163899#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 162696#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 162688#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 160991#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 160992#L1954 assume !(0 == start_simulation_~tmp~3#1); 163789#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 161082#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 159802#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 160890#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 161044#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 161045#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 161151#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 164392#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 164386#L1935-2 [2022-02-21 04:24:02,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,867 INFO L85 PathProgramCache]: Analyzing trace with hash -1573181374, now seen corresponding path program 1 times [2022-02-21 04:24:02,867 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,868 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967821640] [2022-02-21 04:24:02,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:02,912 INFO L290 TraceCheckUtils]: 0: Hoare triple {181425#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,913 INFO L290 TraceCheckUtils]: 1: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,913 INFO L290 TraceCheckUtils]: 2: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,913 INFO L290 TraceCheckUtils]: 3: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,914 INFO L290 TraceCheckUtils]: 4: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,914 INFO L290 TraceCheckUtils]: 5: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,914 INFO L290 TraceCheckUtils]: 6: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,915 INFO L290 TraceCheckUtils]: 7: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,915 INFO L290 TraceCheckUtils]: 8: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,915 INFO L290 TraceCheckUtils]: 9: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,916 INFO L290 TraceCheckUtils]: 10: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,916 INFO L290 TraceCheckUtils]: 11: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,916 INFO L290 TraceCheckUtils]: 12: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,917 INFO L290 TraceCheckUtils]: 13: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,917 INFO L290 TraceCheckUtils]: 14: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,917 INFO L290 TraceCheckUtils]: 15: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,917 INFO L290 TraceCheckUtils]: 16: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,918 INFO L290 TraceCheckUtils]: 17: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,918 INFO L290 TraceCheckUtils]: 18: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,918 INFO L290 TraceCheckUtils]: 19: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume !(0 == ~M_E~0); {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,919 INFO L290 TraceCheckUtils]: 20: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume !(0 == ~T1_E~0); {181427#(= ~E_10~0 ~T2_E~0)} is VALID [2022-02-21 04:24:02,919 INFO L290 TraceCheckUtils]: 21: Hoare triple {181427#(= ~E_10~0 ~T2_E~0)} assume !(0 == ~T2_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,919 INFO L290 TraceCheckUtils]: 22: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T3_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,919 INFO L290 TraceCheckUtils]: 23: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T4_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,920 INFO L290 TraceCheckUtils]: 24: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T5_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,920 INFO L290 TraceCheckUtils]: 25: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T6_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,920 INFO L290 TraceCheckUtils]: 26: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T7_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,921 INFO L290 TraceCheckUtils]: 27: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T8_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,921 INFO L290 TraceCheckUtils]: 28: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T9_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,921 INFO L290 TraceCheckUtils]: 29: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T10_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,921 INFO L290 TraceCheckUtils]: 30: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T11_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,922 INFO L290 TraceCheckUtils]: 31: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T12_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,922 INFO L290 TraceCheckUtils]: 32: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~T13_E~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,922 INFO L290 TraceCheckUtils]: 33: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~E_M~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,922 INFO L290 TraceCheckUtils]: 34: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~E_1~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,923 INFO L290 TraceCheckUtils]: 35: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~E_2~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,923 INFO L290 TraceCheckUtils]: 36: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~E_3~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,923 INFO L290 TraceCheckUtils]: 37: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~E_4~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,923 INFO L290 TraceCheckUtils]: 38: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~E_5~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,924 INFO L290 TraceCheckUtils]: 39: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~E_6~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,924 INFO L290 TraceCheckUtils]: 40: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~E_7~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,924 INFO L290 TraceCheckUtils]: 41: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~E_8~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 42: Hoare triple {181428#(not (= ~E_10~0 0))} assume !(0 == ~E_9~0); {181428#(not (= ~E_10~0 0))} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 43: Hoare triple {181428#(not (= ~E_10~0 0))} assume 0 == ~E_10~0;~E_10~0 := 1; {181426#false} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 44: Hoare triple {181426#false} assume !(0 == ~E_11~0); {181426#false} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 45: Hoare triple {181426#false} assume !(0 == ~E_12~0); {181426#false} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 46: Hoare triple {181426#false} assume !(0 == ~E_13~0); {181426#false} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 47: Hoare triple {181426#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {181426#false} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 48: Hoare triple {181426#false} assume !(1 == ~m_pc~0); {181426#false} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 49: Hoare triple {181426#false} is_master_triggered_~__retres1~0#1 := 0; {181426#false} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 50: Hoare triple {181426#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {181426#false} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 51: Hoare triple {181426#false} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {181426#false} is VALID [2022-02-21 04:24:02,925 INFO L290 TraceCheckUtils]: 52: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp~1#1); {181426#false} is VALID [2022-02-21 04:24:02,926 INFO L290 TraceCheckUtils]: 53: Hoare triple {181426#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {181426#false} is VALID [2022-02-21 04:24:02,926 INFO L290 TraceCheckUtils]: 54: Hoare triple {181426#false} assume 1 == ~t1_pc~0; {181426#false} is VALID [2022-02-21 04:24:02,926 INFO L290 TraceCheckUtils]: 55: Hoare triple {181426#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {181426#false} is VALID [2022-02-21 04:24:02,926 INFO L290 TraceCheckUtils]: 56: Hoare triple {181426#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {181426#false} is VALID [2022-02-21 04:24:02,926 INFO L290 TraceCheckUtils]: 57: Hoare triple {181426#false} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {181426#false} is VALID [2022-02-21 04:24:02,926 INFO L290 TraceCheckUtils]: 58: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___0~0#1); {181426#false} is VALID [2022-02-21 04:24:02,926 INFO L290 TraceCheckUtils]: 59: Hoare triple {181426#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {181426#false} is VALID [2022-02-21 04:24:02,926 INFO L290 TraceCheckUtils]: 60: Hoare triple {181426#false} assume !(1 == ~t2_pc~0); {181426#false} is VALID [2022-02-21 04:24:02,926 INFO L290 TraceCheckUtils]: 61: Hoare triple {181426#false} is_transmit2_triggered_~__retres1~2#1 := 0; {181426#false} is VALID [2022-02-21 04:24:02,926 INFO L290 TraceCheckUtils]: 62: Hoare triple {181426#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 63: Hoare triple {181426#false} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 64: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___1~0#1); {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 65: Hoare triple {181426#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 66: Hoare triple {181426#false} assume !(1 == ~t3_pc~0); {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 67: Hoare triple {181426#false} is_transmit3_triggered_~__retres1~3#1 := 0; {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 68: Hoare triple {181426#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 69: Hoare triple {181426#false} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 70: Hoare triple {181426#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 71: Hoare triple {181426#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 72: Hoare triple {181426#false} assume 1 == ~t4_pc~0; {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 73: Hoare triple {181426#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {181426#false} is VALID [2022-02-21 04:24:02,927 INFO L290 TraceCheckUtils]: 74: Hoare triple {181426#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 75: Hoare triple {181426#false} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 76: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___3~0#1); {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 77: Hoare triple {181426#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 78: Hoare triple {181426#false} assume !(1 == ~t5_pc~0); {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 79: Hoare triple {181426#false} is_transmit5_triggered_~__retres1~5#1 := 0; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 80: Hoare triple {181426#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 81: Hoare triple {181426#false} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 82: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___4~0#1); {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 83: Hoare triple {181426#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 84: Hoare triple {181426#false} assume 1 == ~t6_pc~0; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 85: Hoare triple {181426#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 86: Hoare triple {181426#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 87: Hoare triple {181426#false} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {181426#false} is VALID [2022-02-21 04:24:02,928 INFO L290 TraceCheckUtils]: 88: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___5~0#1); {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 89: Hoare triple {181426#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 90: Hoare triple {181426#false} assume !(1 == ~t7_pc~0); {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 91: Hoare triple {181426#false} is_transmit7_triggered_~__retres1~7#1 := 0; {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 92: Hoare triple {181426#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 93: Hoare triple {181426#false} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 94: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___6~0#1); {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 95: Hoare triple {181426#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 96: Hoare triple {181426#false} assume 1 == ~t8_pc~0; {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 97: Hoare triple {181426#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 98: Hoare triple {181426#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 99: Hoare triple {181426#false} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 100: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___7~0#1); {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 101: Hoare triple {181426#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {181426#false} is VALID [2022-02-21 04:24:02,929 INFO L290 TraceCheckUtils]: 102: Hoare triple {181426#false} assume 1 == ~t9_pc~0; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 103: Hoare triple {181426#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 104: Hoare triple {181426#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 105: Hoare triple {181426#false} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 106: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___8~0#1); {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 107: Hoare triple {181426#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 108: Hoare triple {181426#false} assume !(1 == ~t10_pc~0); {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 109: Hoare triple {181426#false} is_transmit10_triggered_~__retres1~10#1 := 0; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 110: Hoare triple {181426#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 111: Hoare triple {181426#false} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 112: Hoare triple {181426#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 113: Hoare triple {181426#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 114: Hoare triple {181426#false} assume 1 == ~t11_pc~0; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 115: Hoare triple {181426#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {181426#false} is VALID [2022-02-21 04:24:02,930 INFO L290 TraceCheckUtils]: 116: Hoare triple {181426#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 117: Hoare triple {181426#false} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 118: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___10~0#1); {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 119: Hoare triple {181426#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 120: Hoare triple {181426#false} assume !(1 == ~t12_pc~0); {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 121: Hoare triple {181426#false} is_transmit12_triggered_~__retres1~12#1 := 0; {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 122: Hoare triple {181426#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 123: Hoare triple {181426#false} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 124: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___11~0#1); {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 125: Hoare triple {181426#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 126: Hoare triple {181426#false} assume 1 == ~t13_pc~0; {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 127: Hoare triple {181426#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 128: Hoare triple {181426#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {181426#false} is VALID [2022-02-21 04:24:02,931 INFO L290 TraceCheckUtils]: 129: Hoare triple {181426#false} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 130: Hoare triple {181426#false} assume !(0 != activate_threads_~tmp___12~0#1); {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 131: Hoare triple {181426#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 132: Hoare triple {181426#false} assume !(1 == ~M_E~0); {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 133: Hoare triple {181426#false} assume !(1 == ~T1_E~0); {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 134: Hoare triple {181426#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 135: Hoare triple {181426#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 136: Hoare triple {181426#false} assume !(1 == ~T4_E~0); {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 137: Hoare triple {181426#false} assume !(1 == ~T5_E~0); {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 138: Hoare triple {181426#false} assume !(1 == ~T6_E~0); {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 139: Hoare triple {181426#false} assume !(1 == ~T7_E~0); {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 140: Hoare triple {181426#false} assume !(1 == ~T8_E~0); {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 141: Hoare triple {181426#false} assume !(1 == ~T9_E~0); {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 142: Hoare triple {181426#false} assume !(1 == ~T10_E~0); {181426#false} is VALID [2022-02-21 04:24:02,932 INFO L290 TraceCheckUtils]: 143: Hoare triple {181426#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 144: Hoare triple {181426#false} assume !(1 == ~T12_E~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 145: Hoare triple {181426#false} assume !(1 == ~T13_E~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 146: Hoare triple {181426#false} assume !(1 == ~E_M~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 147: Hoare triple {181426#false} assume !(1 == ~E_1~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 148: Hoare triple {181426#false} assume !(1 == ~E_2~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 149: Hoare triple {181426#false} assume !(1 == ~E_3~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 150: Hoare triple {181426#false} assume !(1 == ~E_4~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 151: Hoare triple {181426#false} assume 1 == ~E_5~0;~E_5~0 := 2; {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 152: Hoare triple {181426#false} assume !(1 == ~E_6~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 153: Hoare triple {181426#false} assume !(1 == ~E_7~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 154: Hoare triple {181426#false} assume !(1 == ~E_8~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 155: Hoare triple {181426#false} assume !(1 == ~E_9~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 156: Hoare triple {181426#false} assume !(1 == ~E_10~0); {181426#false} is VALID [2022-02-21 04:24:02,933 INFO L290 TraceCheckUtils]: 157: Hoare triple {181426#false} assume !(1 == ~E_11~0); {181426#false} is VALID [2022-02-21 04:24:02,934 INFO L290 TraceCheckUtils]: 158: Hoare triple {181426#false} assume !(1 == ~E_12~0); {181426#false} is VALID [2022-02-21 04:24:02,934 INFO L290 TraceCheckUtils]: 159: Hoare triple {181426#false} assume 1 == ~E_13~0;~E_13~0 := 2; {181426#false} is VALID [2022-02-21 04:24:02,934 INFO L290 TraceCheckUtils]: 160: Hoare triple {181426#false} assume { :end_inline_reset_delta_events } true; {181426#false} is VALID [2022-02-21 04:24:02,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:02,934 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:02,934 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967821640] [2022-02-21 04:24:02,934 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967821640] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:02,935 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:02,935 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:02,935 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982654439] [2022-02-21 04:24:02,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:02,935 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:02,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,936 INFO L85 PathProgramCache]: Analyzing trace with hash -680178462, now seen corresponding path program 1 times [2022-02-21 04:24:02,936 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,936 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534449345] [2022-02-21 04:24:02,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:02,959 INFO L290 TraceCheckUtils]: 0: Hoare triple {181429#true} assume !false; {181429#true} is VALID [2022-02-21 04:24:02,959 INFO L290 TraceCheckUtils]: 1: Hoare triple {181429#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {181429#true} is VALID [2022-02-21 04:24:02,959 INFO L290 TraceCheckUtils]: 2: Hoare triple {181429#true} assume !false; {181429#true} is VALID [2022-02-21 04:24:02,959 INFO L290 TraceCheckUtils]: 3: Hoare triple {181429#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {181429#true} is VALID [2022-02-21 04:24:02,960 INFO L290 TraceCheckUtils]: 4: Hoare triple {181429#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {181429#true} is VALID [2022-02-21 04:24:02,960 INFO L290 TraceCheckUtils]: 5: Hoare triple {181429#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {181429#true} is VALID [2022-02-21 04:24:02,960 INFO L290 TraceCheckUtils]: 6: Hoare triple {181429#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {181429#true} is VALID [2022-02-21 04:24:02,960 INFO L290 TraceCheckUtils]: 7: Hoare triple {181429#true} assume !(0 != eval_~tmp~0#1); {181429#true} is VALID [2022-02-21 04:24:02,960 INFO L290 TraceCheckUtils]: 8: Hoare triple {181429#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {181429#true} is VALID [2022-02-21 04:24:02,960 INFO L290 TraceCheckUtils]: 9: Hoare triple {181429#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {181429#true} is VALID [2022-02-21 04:24:02,960 INFO L290 TraceCheckUtils]: 10: Hoare triple {181429#true} assume !(0 == ~M_E~0); {181429#true} is VALID [2022-02-21 04:24:02,960 INFO L290 TraceCheckUtils]: 11: Hoare triple {181429#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {181429#true} is VALID [2022-02-21 04:24:02,961 INFO L290 TraceCheckUtils]: 12: Hoare triple {181429#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {181429#true} is VALID [2022-02-21 04:24:02,961 INFO L290 TraceCheckUtils]: 13: Hoare triple {181429#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {181429#true} is VALID [2022-02-21 04:24:02,961 INFO L290 TraceCheckUtils]: 14: Hoare triple {181429#true} assume !(0 == ~T4_E~0); {181429#true} is VALID [2022-02-21 04:24:02,961 INFO L290 TraceCheckUtils]: 15: Hoare triple {181429#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {181429#true} is VALID [2022-02-21 04:24:02,961 INFO L290 TraceCheckUtils]: 16: Hoare triple {181429#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {181429#true} is VALID [2022-02-21 04:24:02,961 INFO L290 TraceCheckUtils]: 17: Hoare triple {181429#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,962 INFO L290 TraceCheckUtils]: 18: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T8_E~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,962 INFO L290 TraceCheckUtils]: 19: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,962 INFO L290 TraceCheckUtils]: 20: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,963 INFO L290 TraceCheckUtils]: 21: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,963 INFO L290 TraceCheckUtils]: 22: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~T12_E~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,963 INFO L290 TraceCheckUtils]: 23: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,963 INFO L290 TraceCheckUtils]: 24: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,964 INFO L290 TraceCheckUtils]: 25: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,964 INFO L290 TraceCheckUtils]: 26: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_2~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,964 INFO L290 TraceCheckUtils]: 27: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,965 INFO L290 TraceCheckUtils]: 28: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,965 INFO L290 TraceCheckUtils]: 29: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,965 INFO L290 TraceCheckUtils]: 30: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,965 INFO L290 TraceCheckUtils]: 31: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,966 INFO L290 TraceCheckUtils]: 32: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,966 INFO L290 TraceCheckUtils]: 33: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,966 INFO L290 TraceCheckUtils]: 34: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,966 INFO L290 TraceCheckUtils]: 35: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,967 INFO L290 TraceCheckUtils]: 36: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,967 INFO L290 TraceCheckUtils]: 37: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,967 INFO L290 TraceCheckUtils]: 38: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,968 INFO L290 TraceCheckUtils]: 39: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~m_pc~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,968 INFO L290 TraceCheckUtils]: 40: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,968 INFO L290 TraceCheckUtils]: 41: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,968 INFO L290 TraceCheckUtils]: 42: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,969 INFO L290 TraceCheckUtils]: 43: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,969 INFO L290 TraceCheckUtils]: 44: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,969 INFO L290 TraceCheckUtils]: 45: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,970 INFO L290 TraceCheckUtils]: 46: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,970 INFO L290 TraceCheckUtils]: 47: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,970 INFO L290 TraceCheckUtils]: 48: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,970 INFO L290 TraceCheckUtils]: 49: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,971 INFO L290 TraceCheckUtils]: 50: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,971 INFO L290 TraceCheckUtils]: 51: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,971 INFO L290 TraceCheckUtils]: 52: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,972 INFO L290 TraceCheckUtils]: 53: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,972 INFO L290 TraceCheckUtils]: 54: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,972 INFO L290 TraceCheckUtils]: 55: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,972 INFO L290 TraceCheckUtils]: 56: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,973 INFO L290 TraceCheckUtils]: 57: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t3_pc~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,973 INFO L290 TraceCheckUtils]: 58: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,973 INFO L290 TraceCheckUtils]: 59: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,974 INFO L290 TraceCheckUtils]: 60: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,974 INFO L290 TraceCheckUtils]: 61: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,974 INFO L290 TraceCheckUtils]: 62: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,974 INFO L290 TraceCheckUtils]: 63: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,975 INFO L290 TraceCheckUtils]: 64: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,975 INFO L290 TraceCheckUtils]: 65: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,975 INFO L290 TraceCheckUtils]: 66: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,975 INFO L290 TraceCheckUtils]: 67: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,976 INFO L290 TraceCheckUtils]: 68: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,976 INFO L290 TraceCheckUtils]: 69: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,976 INFO L290 TraceCheckUtils]: 70: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,977 INFO L290 TraceCheckUtils]: 71: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,977 INFO L290 TraceCheckUtils]: 72: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,977 INFO L290 TraceCheckUtils]: 73: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,977 INFO L290 TraceCheckUtils]: 74: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,978 INFO L290 TraceCheckUtils]: 75: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,978 INFO L290 TraceCheckUtils]: 76: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,978 INFO L290 TraceCheckUtils]: 77: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,979 INFO L290 TraceCheckUtils]: 78: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,979 INFO L290 TraceCheckUtils]: 79: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,979 INFO L290 TraceCheckUtils]: 80: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,979 INFO L290 TraceCheckUtils]: 81: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t7_pc~0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,980 INFO L290 TraceCheckUtils]: 82: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,980 INFO L290 TraceCheckUtils]: 83: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,980 INFO L290 TraceCheckUtils]: 84: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,980 INFO L290 TraceCheckUtils]: 85: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,981 INFO L290 TraceCheckUtils]: 86: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,981 INFO L290 TraceCheckUtils]: 87: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t8_pc~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,981 INFO L290 TraceCheckUtils]: 88: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,982 INFO L290 TraceCheckUtils]: 89: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,982 INFO L290 TraceCheckUtils]: 90: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,982 INFO L290 TraceCheckUtils]: 91: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,982 INFO L290 TraceCheckUtils]: 92: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,983 INFO L290 TraceCheckUtils]: 93: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t9_pc~0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,983 INFO L290 TraceCheckUtils]: 94: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,983 INFO L290 TraceCheckUtils]: 95: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,984 INFO L290 TraceCheckUtils]: 96: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,984 INFO L290 TraceCheckUtils]: 97: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,984 INFO L290 TraceCheckUtils]: 98: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,984 INFO L290 TraceCheckUtils]: 99: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t10_pc~0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,985 INFO L290 TraceCheckUtils]: 100: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,985 INFO L290 TraceCheckUtils]: 101: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,985 INFO L290 TraceCheckUtils]: 102: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,986 INFO L290 TraceCheckUtils]: 103: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,986 INFO L290 TraceCheckUtils]: 104: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,986 INFO L290 TraceCheckUtils]: 105: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t11_pc~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,986 INFO L290 TraceCheckUtils]: 106: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,987 INFO L290 TraceCheckUtils]: 107: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,987 INFO L290 TraceCheckUtils]: 108: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,987 INFO L290 TraceCheckUtils]: 109: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___10~0#1); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,987 INFO L290 TraceCheckUtils]: 110: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,988 INFO L290 TraceCheckUtils]: 111: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t12_pc~0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,988 INFO L290 TraceCheckUtils]: 112: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,988 INFO L290 TraceCheckUtils]: 113: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,989 INFO L290 TraceCheckUtils]: 114: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,989 INFO L290 TraceCheckUtils]: 115: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,989 INFO L290 TraceCheckUtils]: 116: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,989 INFO L290 TraceCheckUtils]: 117: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t13_pc~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,990 INFO L290 TraceCheckUtils]: 118: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,990 INFO L290 TraceCheckUtils]: 119: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,990 INFO L290 TraceCheckUtils]: 120: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,991 INFO L290 TraceCheckUtils]: 121: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,991 INFO L290 TraceCheckUtils]: 122: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,991 INFO L290 TraceCheckUtils]: 123: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~M_E~0); {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,991 INFO L290 TraceCheckUtils]: 124: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,992 INFO L290 TraceCheckUtils]: 125: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,992 INFO L290 TraceCheckUtils]: 126: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,992 INFO L290 TraceCheckUtils]: 127: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,993 INFO L290 TraceCheckUtils]: 128: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,993 INFO L290 TraceCheckUtils]: 129: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {181431#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:24:02,993 INFO L290 TraceCheckUtils]: 130: Hoare triple {181431#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {181430#false} is VALID [2022-02-21 04:24:02,993 INFO L290 TraceCheckUtils]: 131: Hoare triple {181430#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,993 INFO L290 TraceCheckUtils]: 132: Hoare triple {181430#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,994 INFO L290 TraceCheckUtils]: 133: Hoare triple {181430#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,994 INFO L290 TraceCheckUtils]: 134: Hoare triple {181430#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,994 INFO L290 TraceCheckUtils]: 135: Hoare triple {181430#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,994 INFO L290 TraceCheckUtils]: 136: Hoare triple {181430#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,994 INFO L290 TraceCheckUtils]: 137: Hoare triple {181430#false} assume 1 == ~E_M~0;~E_M~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,994 INFO L290 TraceCheckUtils]: 138: Hoare triple {181430#false} assume !(1 == ~E_1~0); {181430#false} is VALID [2022-02-21 04:24:02,994 INFO L290 TraceCheckUtils]: 139: Hoare triple {181430#false} assume !(1 == ~E_2~0); {181430#false} is VALID [2022-02-21 04:24:02,994 INFO L290 TraceCheckUtils]: 140: Hoare triple {181430#false} assume 1 == ~E_3~0;~E_3~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,995 INFO L290 TraceCheckUtils]: 141: Hoare triple {181430#false} assume 1 == ~E_4~0;~E_4~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,995 INFO L290 TraceCheckUtils]: 142: Hoare triple {181430#false} assume 1 == ~E_5~0;~E_5~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,995 INFO L290 TraceCheckUtils]: 143: Hoare triple {181430#false} assume 1 == ~E_6~0;~E_6~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,995 INFO L290 TraceCheckUtils]: 144: Hoare triple {181430#false} assume 1 == ~E_7~0;~E_7~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,995 INFO L290 TraceCheckUtils]: 145: Hoare triple {181430#false} assume 1 == ~E_8~0;~E_8~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,995 INFO L290 TraceCheckUtils]: 146: Hoare triple {181430#false} assume !(1 == ~E_9~0); {181430#false} is VALID [2022-02-21 04:24:02,995 INFO L290 TraceCheckUtils]: 147: Hoare triple {181430#false} assume 1 == ~E_10~0;~E_10~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,995 INFO L290 TraceCheckUtils]: 148: Hoare triple {181430#false} assume 1 == ~E_11~0;~E_11~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,996 INFO L290 TraceCheckUtils]: 149: Hoare triple {181430#false} assume 1 == ~E_12~0;~E_12~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,996 INFO L290 TraceCheckUtils]: 150: Hoare triple {181430#false} assume 1 == ~E_13~0;~E_13~0 := 2; {181430#false} is VALID [2022-02-21 04:24:02,996 INFO L290 TraceCheckUtils]: 151: Hoare triple {181430#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {181430#false} is VALID [2022-02-21 04:24:02,996 INFO L290 TraceCheckUtils]: 152: Hoare triple {181430#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {181430#false} is VALID [2022-02-21 04:24:02,996 INFO L290 TraceCheckUtils]: 153: Hoare triple {181430#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {181430#false} is VALID [2022-02-21 04:24:02,996 INFO L290 TraceCheckUtils]: 154: Hoare triple {181430#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {181430#false} is VALID [2022-02-21 04:24:02,996 INFO L290 TraceCheckUtils]: 155: Hoare triple {181430#false} assume !(0 == start_simulation_~tmp~3#1); {181430#false} is VALID [2022-02-21 04:24:02,996 INFO L290 TraceCheckUtils]: 156: Hoare triple {181430#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {181430#false} is VALID [2022-02-21 04:24:02,997 INFO L290 TraceCheckUtils]: 157: Hoare triple {181430#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {181430#false} is VALID [2022-02-21 04:24:02,997 INFO L290 TraceCheckUtils]: 158: Hoare triple {181430#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {181430#false} is VALID [2022-02-21 04:24:02,997 INFO L290 TraceCheckUtils]: 159: Hoare triple {181430#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {181430#false} is VALID [2022-02-21 04:24:02,997 INFO L290 TraceCheckUtils]: 160: Hoare triple {181430#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {181430#false} is VALID [2022-02-21 04:24:02,997 INFO L290 TraceCheckUtils]: 161: Hoare triple {181430#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {181430#false} is VALID [2022-02-21 04:24:02,997 INFO L290 TraceCheckUtils]: 162: Hoare triple {181430#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {181430#false} is VALID [2022-02-21 04:24:02,997 INFO L290 TraceCheckUtils]: 163: Hoare triple {181430#false} assume !(0 != start_simulation_~tmp___0~1#1); {181430#false} is VALID [2022-02-21 04:24:02,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:02,998 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:02,998 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534449345] [2022-02-21 04:24:02,998 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534449345] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:02,998 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:02,998 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:02,999 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174530040] [2022-02-21 04:24:02,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:02,999 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:02,999 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:02,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:03,000 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:03,001 INFO L87 Difference]: Start difference. First operand 7385 states and 10772 transitions. cyclomatic complexity: 3389 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:10,616 INFO L93 Difference]: Finished difference Result 14197 states and 20700 transitions. [2022-02-21 04:24:10,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:10,616 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,699 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 161 edges. 161 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:10,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14197 states and 20700 transitions.