./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:23:57,353 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:23:57,354 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:23:57,386 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:23:57,387 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:23:57,390 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:23:57,391 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:23:57,396 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:23:57,397 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:23:57,405 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:23:57,406 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:23:57,407 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:23:57,407 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:23:57,410 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:23:57,410 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:23:57,413 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:23:57,414 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:23:57,415 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:23:57,417 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:23:57,422 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:23:57,423 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:23:57,424 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:23:57,425 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:23:57,426 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:23:57,431 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:23:57,431 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:23:57,432 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:23:57,433 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:23:57,433 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:23:57,434 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:23:57,434 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:23:57,435 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:23:57,437 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:23:57,438 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:23:57,439 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:23:57,439 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:23:57,440 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:23:57,440 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:23:57,440 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:23:57,441 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:23:57,441 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:23:57,442 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:23:57,475 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:23:57,476 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:23:57,476 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:23:57,476 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:23:57,477 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:23:57,478 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:23:57,478 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:23:57,478 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:23:57,478 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:23:57,478 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:23:57,479 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:23:57,479 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:23:57,480 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:23:57,480 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:23:57,480 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:23:57,480 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:23:57,480 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:23:57,481 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:23:57,481 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:23:57,481 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:23:57,481 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:23:57,481 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:23:57,482 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:23:57,482 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:23:57,482 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:23:57,482 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:23:57,482 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:23:57,483 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:23:57,483 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:23:57,483 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:23:57,483 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:23:57,484 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:23:57,484 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2022-02-21 04:23:57,707 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:23:57,726 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:23:57,728 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:23:57,729 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:23:57,730 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:23:57,731 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.01.cil.c [2022-02-21 04:23:57,783 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/193952662/49776da3c6944a6cafb65e9cb9dfef45/FLAGedc9e39d9 [2022-02-21 04:23:58,134 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:23:58,135 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c [2022-02-21 04:23:58,147 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/193952662/49776da3c6944a6cafb65e9cb9dfef45/FLAGedc9e39d9 [2022-02-21 04:23:58,159 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/193952662/49776da3c6944a6cafb65e9cb9dfef45 [2022-02-21 04:23:58,161 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:23:58,162 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:23:58,163 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:58,164 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:23:58,166 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:23:58,167 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,168 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@41674eb8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58, skipping insertion in model container [2022-02-21 04:23:58,168 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,179 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:23:58,213 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:23:58,320 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c[706,719] [2022-02-21 04:23:58,364 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:58,373 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:23:58,384 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c[706,719] [2022-02-21 04:23:58,401 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:58,415 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:23:58,415 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58 WrapperNode [2022-02-21 04:23:58,415 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:58,416 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:58,416 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:23:58,416 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:23:58,423 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,428 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,465 INFO L137 Inliner]: procedures = 30, calls = 33, calls flagged for inlining = 28, calls inlined = 34, statements flattened = 357 [2022-02-21 04:23:58,466 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:58,466 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:23:58,467 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:23:58,467 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:23:58,477 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,477 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,480 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,481 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,487 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,500 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,501 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,504 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:23:58,505 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:23:58,505 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:23:58,505 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:23:58,506 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (1/1) ... [2022-02-21 04:23:58,523 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:23:58,535 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:23:58,553 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:23:58,590 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:23:58,605 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:23:58,605 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:23:58,605 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:23:58,606 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:23:58,681 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:23:58,682 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:23:59,009 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:23:59,023 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:23:59,025 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2022-02-21 04:23:59,027 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:59 BoogieIcfgContainer [2022-02-21 04:23:59,027 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:23:59,028 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:23:59,028 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:23:59,031 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:23:59,032 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:59,032 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:23:58" (1/3) ... [2022-02-21 04:23:59,033 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@48a39cdd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:59, skipping insertion in model container [2022-02-21 04:23:59,033 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:59,033 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:58" (2/3) ... [2022-02-21 04:23:59,033 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@48a39cdd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:59, skipping insertion in model container [2022-02-21 04:23:59,033 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:59,033 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:59" (3/3) ... [2022-02-21 04:23:59,034 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2022-02-21 04:23:59,067 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:23:59,067 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:23:59,067 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:23:59,067 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:23:59,067 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:23:59,067 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:23:59,067 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:23:59,068 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:23:59,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:59,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2022-02-21 04:23:59,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:59,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:59,138 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:59,138 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:59,138 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:23:59,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:59,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2022-02-21 04:23:59,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:59,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:59,169 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:59,169 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:59,175 INFO L791 eck$LassoCheckResult]: Stem: 117#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 46#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 15#L367true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 92#L154true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12#L161true assume !(1 == ~m_i~0);~m_st~0 := 2; 7#L161-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 78#L166-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L250true assume !(0 == ~M_E~0); 105#L250-2true assume !(0 == ~T1_E~0); 38#L255-1true assume !(0 == ~E_1~0); 79#L260-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52#L115true assume !(1 == ~m_pc~0); 56#L115-2true is_master_triggered_~__retres1~0#1 := 0; 67#L126true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121#L127true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 63#L300true assume !(0 != activate_threads_~tmp~1#1); 104#L300-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119#L134true assume 1 == ~t1_pc~0; 106#L135true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54#L145true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85#L146true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11#L308true assume !(0 != activate_threads_~tmp___0~0#1); 59#L308-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57#L273true assume !(1 == ~M_E~0); 109#L273-2true assume !(1 == ~T1_E~0); 99#L278-1true assume !(1 == ~E_1~0); 69#L283-1true assume { :end_inline_reset_delta_events } true; 55#L404-2true [2022-02-21 04:23:59,176 INFO L793 eck$LassoCheckResult]: Loop: 55#L404-2true assume !false; 80#L405true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43#L225true assume !true; 25#L240true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 114#L154-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 118#L250-3true assume 0 == ~M_E~0;~M_E~0 := 1; 96#L250-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 101#L255-3true assume 0 == ~E_1~0;~E_1~0 := 1; 8#L260-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48#L115-6true assume 1 == ~m_pc~0; 113#L116-2true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 133#L126-2true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58#L127-2true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 72#L300-6true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 115#L300-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131#L134-6true assume !(1 == ~t1_pc~0); 33#L134-8true is_transmit1_triggered_~__retres1~1#1 := 0; 51#L145-2true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112#L146-2true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 49#L308-6true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9#L308-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127#L273-3true assume 1 == ~M_E~0;~M_E~0 := 2; 44#L273-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 35#L278-3true assume 1 == ~E_1~0;~E_1~0 := 2; 93#L283-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 75#L179-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 110#L191-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 132#L192-1true start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 19#L423true assume !(0 == start_simulation_~tmp~3#1); 18#L423-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 22#L179-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 70#L191-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 94#L192-2true stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 14#L378true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16#L385true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76#L386true start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 42#L436true assume !(0 != start_simulation_~tmp___0~1#1); 55#L404-2true [2022-02-21 04:23:59,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:59,181 INFO L85 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2022-02-21 04:23:59,188 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:59,189 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326263040] [2022-02-21 04:23:59,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:59,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:59,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:59,328 INFO L290 TraceCheckUtils]: 0: Hoare triple {137#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; {137#true} is VALID [2022-02-21 04:23:59,329 INFO L290 TraceCheckUtils]: 1: Hoare triple {137#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; {139#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:59,330 INFO L290 TraceCheckUtils]: 2: Hoare triple {139#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {139#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:59,331 INFO L290 TraceCheckUtils]: 3: Hoare triple {139#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {139#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:59,331 INFO L290 TraceCheckUtils]: 4: Hoare triple {139#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {138#false} is VALID [2022-02-21 04:23:59,332 INFO L290 TraceCheckUtils]: 5: Hoare triple {138#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {138#false} is VALID [2022-02-21 04:23:59,332 INFO L290 TraceCheckUtils]: 6: Hoare triple {138#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {138#false} is VALID [2022-02-21 04:23:59,332 INFO L290 TraceCheckUtils]: 7: Hoare triple {138#false} assume !(0 == ~M_E~0); {138#false} is VALID [2022-02-21 04:23:59,332 INFO L290 TraceCheckUtils]: 8: Hoare triple {138#false} assume !(0 == ~T1_E~0); {138#false} is VALID [2022-02-21 04:23:59,333 INFO L290 TraceCheckUtils]: 9: Hoare triple {138#false} assume !(0 == ~E_1~0); {138#false} is VALID [2022-02-21 04:23:59,333 INFO L290 TraceCheckUtils]: 10: Hoare triple {138#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {138#false} is VALID [2022-02-21 04:23:59,333 INFO L290 TraceCheckUtils]: 11: Hoare triple {138#false} assume !(1 == ~m_pc~0); {138#false} is VALID [2022-02-21 04:23:59,333 INFO L290 TraceCheckUtils]: 12: Hoare triple {138#false} is_master_triggered_~__retres1~0#1 := 0; {138#false} is VALID [2022-02-21 04:23:59,334 INFO L290 TraceCheckUtils]: 13: Hoare triple {138#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {138#false} is VALID [2022-02-21 04:23:59,334 INFO L290 TraceCheckUtils]: 14: Hoare triple {138#false} activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {138#false} is VALID [2022-02-21 04:23:59,334 INFO L290 TraceCheckUtils]: 15: Hoare triple {138#false} assume !(0 != activate_threads_~tmp~1#1); {138#false} is VALID [2022-02-21 04:23:59,334 INFO L290 TraceCheckUtils]: 16: Hoare triple {138#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {138#false} is VALID [2022-02-21 04:23:59,334 INFO L290 TraceCheckUtils]: 17: Hoare triple {138#false} assume 1 == ~t1_pc~0; {138#false} is VALID [2022-02-21 04:23:59,335 INFO L290 TraceCheckUtils]: 18: Hoare triple {138#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {138#false} is VALID [2022-02-21 04:23:59,335 INFO L290 TraceCheckUtils]: 19: Hoare triple {138#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {138#false} is VALID [2022-02-21 04:23:59,335 INFO L290 TraceCheckUtils]: 20: Hoare triple {138#false} activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {138#false} is VALID [2022-02-21 04:23:59,335 INFO L290 TraceCheckUtils]: 21: Hoare triple {138#false} assume !(0 != activate_threads_~tmp___0~0#1); {138#false} is VALID [2022-02-21 04:23:59,335 INFO L290 TraceCheckUtils]: 22: Hoare triple {138#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {138#false} is VALID [2022-02-21 04:23:59,336 INFO L290 TraceCheckUtils]: 23: Hoare triple {138#false} assume !(1 == ~M_E~0); {138#false} is VALID [2022-02-21 04:23:59,336 INFO L290 TraceCheckUtils]: 24: Hoare triple {138#false} assume !(1 == ~T1_E~0); {138#false} is VALID [2022-02-21 04:23:59,336 INFO L290 TraceCheckUtils]: 25: Hoare triple {138#false} assume !(1 == ~E_1~0); {138#false} is VALID [2022-02-21 04:23:59,336 INFO L290 TraceCheckUtils]: 26: Hoare triple {138#false} assume { :end_inline_reset_delta_events } true; {138#false} is VALID [2022-02-21 04:23:59,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:59,338 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:59,338 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326263040] [2022-02-21 04:23:59,338 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [326263040] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:59,339 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:59,339 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:59,340 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366229781] [2022-02-21 04:23:59,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:59,343 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:59,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:59,344 INFO L85 PathProgramCache]: Analyzing trace with hash 478113713, now seen corresponding path program 1 times [2022-02-21 04:23:59,345 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:59,345 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859725989] [2022-02-21 04:23:59,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:59,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:59,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:59,364 INFO L290 TraceCheckUtils]: 0: Hoare triple {140#true} assume !false; {140#true} is VALID [2022-02-21 04:23:59,365 INFO L290 TraceCheckUtils]: 1: Hoare triple {140#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {140#true} is VALID [2022-02-21 04:23:59,365 INFO L290 TraceCheckUtils]: 2: Hoare triple {140#true} assume !true; {141#false} is VALID [2022-02-21 04:23:59,366 INFO L290 TraceCheckUtils]: 3: Hoare triple {141#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {141#false} is VALID [2022-02-21 04:23:59,366 INFO L290 TraceCheckUtils]: 4: Hoare triple {141#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {141#false} is VALID [2022-02-21 04:23:59,366 INFO L290 TraceCheckUtils]: 5: Hoare triple {141#false} assume 0 == ~M_E~0;~M_E~0 := 1; {141#false} is VALID [2022-02-21 04:23:59,366 INFO L290 TraceCheckUtils]: 6: Hoare triple {141#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {141#false} is VALID [2022-02-21 04:23:59,367 INFO L290 TraceCheckUtils]: 7: Hoare triple {141#false} assume 0 == ~E_1~0;~E_1~0 := 1; {141#false} is VALID [2022-02-21 04:23:59,367 INFO L290 TraceCheckUtils]: 8: Hoare triple {141#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {141#false} is VALID [2022-02-21 04:23:59,367 INFO L290 TraceCheckUtils]: 9: Hoare triple {141#false} assume 1 == ~m_pc~0; {141#false} is VALID [2022-02-21 04:23:59,367 INFO L290 TraceCheckUtils]: 10: Hoare triple {141#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {141#false} is VALID [2022-02-21 04:23:59,368 INFO L290 TraceCheckUtils]: 11: Hoare triple {141#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {141#false} is VALID [2022-02-21 04:23:59,368 INFO L290 TraceCheckUtils]: 12: Hoare triple {141#false} activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {141#false} is VALID [2022-02-21 04:23:59,368 INFO L290 TraceCheckUtils]: 13: Hoare triple {141#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {141#false} is VALID [2022-02-21 04:23:59,368 INFO L290 TraceCheckUtils]: 14: Hoare triple {141#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {141#false} is VALID [2022-02-21 04:23:59,368 INFO L290 TraceCheckUtils]: 15: Hoare triple {141#false} assume !(1 == ~t1_pc~0); {141#false} is VALID [2022-02-21 04:23:59,369 INFO L290 TraceCheckUtils]: 16: Hoare triple {141#false} is_transmit1_triggered_~__retres1~1#1 := 0; {141#false} is VALID [2022-02-21 04:23:59,369 INFO L290 TraceCheckUtils]: 17: Hoare triple {141#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {141#false} is VALID [2022-02-21 04:23:59,369 INFO L290 TraceCheckUtils]: 18: Hoare triple {141#false} activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {141#false} is VALID [2022-02-21 04:23:59,369 INFO L290 TraceCheckUtils]: 19: Hoare triple {141#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {141#false} is VALID [2022-02-21 04:23:59,370 INFO L290 TraceCheckUtils]: 20: Hoare triple {141#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {141#false} is VALID [2022-02-21 04:23:59,370 INFO L290 TraceCheckUtils]: 21: Hoare triple {141#false} assume 1 == ~M_E~0;~M_E~0 := 2; {141#false} is VALID [2022-02-21 04:23:59,370 INFO L290 TraceCheckUtils]: 22: Hoare triple {141#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {141#false} is VALID [2022-02-21 04:23:59,370 INFO L290 TraceCheckUtils]: 23: Hoare triple {141#false} assume 1 == ~E_1~0;~E_1~0 := 2; {141#false} is VALID [2022-02-21 04:23:59,371 INFO L290 TraceCheckUtils]: 24: Hoare triple {141#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {141#false} is VALID [2022-02-21 04:23:59,371 INFO L290 TraceCheckUtils]: 25: Hoare triple {141#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {141#false} is VALID [2022-02-21 04:23:59,371 INFO L290 TraceCheckUtils]: 26: Hoare triple {141#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {141#false} is VALID [2022-02-21 04:23:59,371 INFO L290 TraceCheckUtils]: 27: Hoare triple {141#false} start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; {141#false} is VALID [2022-02-21 04:23:59,371 INFO L290 TraceCheckUtils]: 28: Hoare triple {141#false} assume !(0 == start_simulation_~tmp~3#1); {141#false} is VALID [2022-02-21 04:23:59,372 INFO L290 TraceCheckUtils]: 29: Hoare triple {141#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {141#false} is VALID [2022-02-21 04:23:59,372 INFO L290 TraceCheckUtils]: 30: Hoare triple {141#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {141#false} is VALID [2022-02-21 04:23:59,372 INFO L290 TraceCheckUtils]: 31: Hoare triple {141#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {141#false} is VALID [2022-02-21 04:23:59,372 INFO L290 TraceCheckUtils]: 32: Hoare triple {141#false} stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; {141#false} is VALID [2022-02-21 04:23:59,373 INFO L290 TraceCheckUtils]: 33: Hoare triple {141#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {141#false} is VALID [2022-02-21 04:23:59,373 INFO L290 TraceCheckUtils]: 34: Hoare triple {141#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {141#false} is VALID [2022-02-21 04:23:59,373 INFO L290 TraceCheckUtils]: 35: Hoare triple {141#false} start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {141#false} is VALID [2022-02-21 04:23:59,373 INFO L290 TraceCheckUtils]: 36: Hoare triple {141#false} assume !(0 != start_simulation_~tmp___0~1#1); {141#false} is VALID [2022-02-21 04:23:59,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:59,374 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:59,374 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859725989] [2022-02-21 04:23:59,374 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859725989] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:59,375 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:59,375 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:59,375 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2001545633] [2022-02-21 04:23:59,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:59,376 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:59,377 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:59,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:59,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:59,409 INFO L87 Difference]: Start difference. First operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:59,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:59,610 INFO L93 Difference]: Finished difference Result 132 states and 188 transitions. [2022-02-21 04:23:59,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:59,612 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:59,638 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:59,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132 states and 188 transitions. [2022-02-21 04:23:59,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2022-02-21 04:23:59,672 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132 states to 126 states and 182 transitions. [2022-02-21 04:23:59,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126 [2022-02-21 04:23:59,673 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126 [2022-02-21 04:23:59,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126 states and 182 transitions. [2022-02-21 04:23:59,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:59,675 INFO L681 BuchiCegarLoop]: Abstraction has 126 states and 182 transitions. [2022-02-21 04:23:59,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states and 182 transitions. [2022-02-21 04:23:59,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 126. [2022-02-21 04:23:59,715 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:59,730 INFO L82 GeneralOperation]: Start isEquivalent. First operand 126 states and 182 transitions. Second operand has 126 states, 126 states have (on average 1.4444444444444444) internal successors, (182), 125 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:59,732 INFO L74 IsIncluded]: Start isIncluded. First operand 126 states and 182 transitions. Second operand has 126 states, 126 states have (on average 1.4444444444444444) internal successors, (182), 125 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:59,733 INFO L87 Difference]: Start difference. First operand 126 states and 182 transitions. Second operand has 126 states, 126 states have (on average 1.4444444444444444) internal successors, (182), 125 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:59,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:59,741 INFO L93 Difference]: Finished difference Result 126 states and 182 transitions. [2022-02-21 04:23:59,742 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 182 transitions. [2022-02-21 04:23:59,743 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:59,743 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:59,744 INFO L74 IsIncluded]: Start isIncluded. First operand has 126 states, 126 states have (on average 1.4444444444444444) internal successors, (182), 125 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 126 states and 182 transitions. [2022-02-21 04:23:59,744 INFO L87 Difference]: Start difference. First operand has 126 states, 126 states have (on average 1.4444444444444444) internal successors, (182), 125 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 126 states and 182 transitions. [2022-02-21 04:23:59,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:59,749 INFO L93 Difference]: Finished difference Result 126 states and 182 transitions. [2022-02-21 04:23:59,749 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 182 transitions. [2022-02-21 04:23:59,750 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:59,750 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:59,750 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:59,750 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:59,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 126 states, 126 states have (on average 1.4444444444444444) internal successors, (182), 125 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:59,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 182 transitions. [2022-02-21 04:23:59,755 INFO L704 BuchiCegarLoop]: Abstraction has 126 states and 182 transitions. [2022-02-21 04:23:59,756 INFO L587 BuchiCegarLoop]: Abstraction has 126 states and 182 transitions. [2022-02-21 04:23:59,756 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:23:59,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 126 states and 182 transitions. [2022-02-21 04:23:59,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2022-02-21 04:23:59,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:59,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:59,758 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:59,759 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:59,759 INFO L791 eck$LassoCheckResult]: Stem: 398#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 341#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 293#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 294#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 287#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 278#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 279#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 375#L250 assume !(0 == ~M_E~0); 382#L250-2 assume !(0 == ~T1_E~0); 331#L255-1 assume !(0 == ~E_1~0); 332#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 347#L115 assume !(1 == ~m_pc~0); 318#L115-2 is_master_triggered_~__retres1~0#1 := 0; 319#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 362#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 359#L300 assume !(0 != activate_threads_~tmp~1#1); 360#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 391#L134 assume 1 == ~t1_pc~0; 392#L135 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 349#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 350#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 285#L308 assume !(0 != activate_threads_~tmp___0~0#1); 286#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 352#L273 assume !(1 == ~M_E~0); 353#L273-2 assume !(1 == ~T1_E~0); 389#L278-1 assume !(1 == ~E_1~0); 365#L283-1 assume { :end_inline_reset_delta_events } true; 337#L404-2 [2022-02-21 04:23:59,759 INFO L793 eck$LassoCheckResult]: Loop: 337#L404-2 assume !false; 351#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 301#L225 assume !false; 338#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 379#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 321#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 374#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 329#L206 assume !(0 != eval_~tmp~0#1); 310#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 311#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 396#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 387#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 388#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 280#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281#L115-6 assume 1 == ~m_pc~0; 342#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 395#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 354#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 355#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 368#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 397#L134-6 assume !(1 == ~t1_pc~0); 322#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 323#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 346#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 344#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 282#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 283#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 339#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 325#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 326#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 371#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 372#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 393#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 298#L423 assume !(0 == start_simulation_~tmp~3#1); 296#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 297#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 304#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 366#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 291#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 292#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 295#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 336#L436 assume !(0 != start_simulation_~tmp___0~1#1); 337#L404-2 [2022-02-21 04:23:59,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:59,760 INFO L85 PathProgramCache]: Analyzing trace with hash -1569234711, now seen corresponding path program 1 times [2022-02-21 04:23:59,761 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:59,761 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27693537] [2022-02-21 04:23:59,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:59,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:59,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:59,808 INFO L290 TraceCheckUtils]: 0: Hoare triple {655#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,809 INFO L290 TraceCheckUtils]: 1: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,810 INFO L290 TraceCheckUtils]: 2: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,810 INFO L290 TraceCheckUtils]: 3: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,811 INFO L290 TraceCheckUtils]: 4: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,811 INFO L290 TraceCheckUtils]: 5: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,811 INFO L290 TraceCheckUtils]: 6: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,812 INFO L290 TraceCheckUtils]: 7: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,813 INFO L290 TraceCheckUtils]: 8: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,813 INFO L290 TraceCheckUtils]: 9: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,813 INFO L290 TraceCheckUtils]: 10: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {657#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:59,814 INFO L290 TraceCheckUtils]: 11: Hoare triple {657#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {658#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:59,814 INFO L290 TraceCheckUtils]: 12: Hoare triple {658#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {658#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:59,815 INFO L290 TraceCheckUtils]: 13: Hoare triple {658#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {658#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:59,815 INFO L290 TraceCheckUtils]: 14: Hoare triple {658#(not (= ~t1_pc~0 1))} activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {658#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:59,816 INFO L290 TraceCheckUtils]: 15: Hoare triple {658#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {658#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:59,816 INFO L290 TraceCheckUtils]: 16: Hoare triple {658#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {658#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:59,817 INFO L290 TraceCheckUtils]: 17: Hoare triple {658#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {656#false} is VALID [2022-02-21 04:23:59,817 INFO L290 TraceCheckUtils]: 18: Hoare triple {656#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {656#false} is VALID [2022-02-21 04:23:59,817 INFO L290 TraceCheckUtils]: 19: Hoare triple {656#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {656#false} is VALID [2022-02-21 04:23:59,817 INFO L290 TraceCheckUtils]: 20: Hoare triple {656#false} activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {656#false} is VALID [2022-02-21 04:23:59,818 INFO L290 TraceCheckUtils]: 21: Hoare triple {656#false} assume !(0 != activate_threads_~tmp___0~0#1); {656#false} is VALID [2022-02-21 04:23:59,818 INFO L290 TraceCheckUtils]: 22: Hoare triple {656#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {656#false} is VALID [2022-02-21 04:23:59,818 INFO L290 TraceCheckUtils]: 23: Hoare triple {656#false} assume !(1 == ~M_E~0); {656#false} is VALID [2022-02-21 04:23:59,818 INFO L290 TraceCheckUtils]: 24: Hoare triple {656#false} assume !(1 == ~T1_E~0); {656#false} is VALID [2022-02-21 04:23:59,818 INFO L290 TraceCheckUtils]: 25: Hoare triple {656#false} assume !(1 == ~E_1~0); {656#false} is VALID [2022-02-21 04:23:59,819 INFO L290 TraceCheckUtils]: 26: Hoare triple {656#false} assume { :end_inline_reset_delta_events } true; {656#false} is VALID [2022-02-21 04:23:59,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:59,819 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:59,819 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [27693537] [2022-02-21 04:23:59,820 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [27693537] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:59,820 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:59,820 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:59,820 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [426071810] [2022-02-21 04:23:59,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:59,821 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:59,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:59,821 INFO L85 PathProgramCache]: Analyzing trace with hash -445215682, now seen corresponding path program 1 times [2022-02-21 04:23:59,821 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:59,822 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083355531] [2022-02-21 04:23:59,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:59,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:59,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:59,896 INFO L290 TraceCheckUtils]: 0: Hoare triple {659#true} assume !false; {659#true} is VALID [2022-02-21 04:23:59,897 INFO L290 TraceCheckUtils]: 1: Hoare triple {659#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {659#true} is VALID [2022-02-21 04:23:59,897 INFO L290 TraceCheckUtils]: 2: Hoare triple {659#true} assume !false; {659#true} is VALID [2022-02-21 04:23:59,898 INFO L290 TraceCheckUtils]: 3: Hoare triple {659#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {659#true} is VALID [2022-02-21 04:23:59,901 INFO L290 TraceCheckUtils]: 4: Hoare triple {659#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {661#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:23:59,901 INFO L290 TraceCheckUtils]: 5: Hoare triple {661#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {662#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:23:59,902 INFO L290 TraceCheckUtils]: 6: Hoare triple {662#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {663#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:23:59,902 INFO L290 TraceCheckUtils]: 7: Hoare triple {663#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {660#false} is VALID [2022-02-21 04:23:59,903 INFO L290 TraceCheckUtils]: 8: Hoare triple {660#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {660#false} is VALID [2022-02-21 04:23:59,903 INFO L290 TraceCheckUtils]: 9: Hoare triple {660#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {660#false} is VALID [2022-02-21 04:23:59,903 INFO L290 TraceCheckUtils]: 10: Hoare triple {660#false} assume 0 == ~M_E~0;~M_E~0 := 1; {660#false} is VALID [2022-02-21 04:23:59,904 INFO L290 TraceCheckUtils]: 11: Hoare triple {660#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {660#false} is VALID [2022-02-21 04:23:59,904 INFO L290 TraceCheckUtils]: 12: Hoare triple {660#false} assume 0 == ~E_1~0;~E_1~0 := 1; {660#false} is VALID [2022-02-21 04:23:59,907 INFO L290 TraceCheckUtils]: 13: Hoare triple {660#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {660#false} is VALID [2022-02-21 04:23:59,908 INFO L290 TraceCheckUtils]: 14: Hoare triple {660#false} assume 1 == ~m_pc~0; {660#false} is VALID [2022-02-21 04:23:59,908 INFO L290 TraceCheckUtils]: 15: Hoare triple {660#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {660#false} is VALID [2022-02-21 04:23:59,908 INFO L290 TraceCheckUtils]: 16: Hoare triple {660#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {660#false} is VALID [2022-02-21 04:23:59,908 INFO L290 TraceCheckUtils]: 17: Hoare triple {660#false} activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {660#false} is VALID [2022-02-21 04:23:59,908 INFO L290 TraceCheckUtils]: 18: Hoare triple {660#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {660#false} is VALID [2022-02-21 04:23:59,910 INFO L290 TraceCheckUtils]: 19: Hoare triple {660#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {660#false} is VALID [2022-02-21 04:23:59,910 INFO L290 TraceCheckUtils]: 20: Hoare triple {660#false} assume !(1 == ~t1_pc~0); {660#false} is VALID [2022-02-21 04:23:59,910 INFO L290 TraceCheckUtils]: 21: Hoare triple {660#false} is_transmit1_triggered_~__retres1~1#1 := 0; {660#false} is VALID [2022-02-21 04:23:59,910 INFO L290 TraceCheckUtils]: 22: Hoare triple {660#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {660#false} is VALID [2022-02-21 04:23:59,911 INFO L290 TraceCheckUtils]: 23: Hoare triple {660#false} activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {660#false} is VALID [2022-02-21 04:23:59,911 INFO L290 TraceCheckUtils]: 24: Hoare triple {660#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {660#false} is VALID [2022-02-21 04:23:59,911 INFO L290 TraceCheckUtils]: 25: Hoare triple {660#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {660#false} is VALID [2022-02-21 04:23:59,913 INFO L290 TraceCheckUtils]: 26: Hoare triple {660#false} assume 1 == ~M_E~0;~M_E~0 := 2; {660#false} is VALID [2022-02-21 04:23:59,913 INFO L290 TraceCheckUtils]: 27: Hoare triple {660#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {660#false} is VALID [2022-02-21 04:23:59,913 INFO L290 TraceCheckUtils]: 28: Hoare triple {660#false} assume 1 == ~E_1~0;~E_1~0 := 2; {660#false} is VALID [2022-02-21 04:23:59,914 INFO L290 TraceCheckUtils]: 29: Hoare triple {660#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {660#false} is VALID [2022-02-21 04:23:59,914 INFO L290 TraceCheckUtils]: 30: Hoare triple {660#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {660#false} is VALID [2022-02-21 04:23:59,914 INFO L290 TraceCheckUtils]: 31: Hoare triple {660#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {660#false} is VALID [2022-02-21 04:23:59,914 INFO L290 TraceCheckUtils]: 32: Hoare triple {660#false} start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; {660#false} is VALID [2022-02-21 04:23:59,914 INFO L290 TraceCheckUtils]: 33: Hoare triple {660#false} assume !(0 == start_simulation_~tmp~3#1); {660#false} is VALID [2022-02-21 04:23:59,915 INFO L290 TraceCheckUtils]: 34: Hoare triple {660#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {660#false} is VALID [2022-02-21 04:23:59,915 INFO L290 TraceCheckUtils]: 35: Hoare triple {660#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {660#false} is VALID [2022-02-21 04:23:59,915 INFO L290 TraceCheckUtils]: 36: Hoare triple {660#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {660#false} is VALID [2022-02-21 04:23:59,925 INFO L290 TraceCheckUtils]: 37: Hoare triple {660#false} stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; {660#false} is VALID [2022-02-21 04:23:59,926 INFO L290 TraceCheckUtils]: 38: Hoare triple {660#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {660#false} is VALID [2022-02-21 04:23:59,926 INFO L290 TraceCheckUtils]: 39: Hoare triple {660#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {660#false} is VALID [2022-02-21 04:23:59,926 INFO L290 TraceCheckUtils]: 40: Hoare triple {660#false} start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {660#false} is VALID [2022-02-21 04:23:59,926 INFO L290 TraceCheckUtils]: 41: Hoare triple {660#false} assume !(0 != start_simulation_~tmp___0~1#1); {660#false} is VALID [2022-02-21 04:23:59,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:59,927 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:59,927 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083355531] [2022-02-21 04:23:59,927 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083355531] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:59,927 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:59,928 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:23:59,928 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615514594] [2022-02-21 04:23:59,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:59,928 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:59,929 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:59,929 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:59,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:59,929 INFO L87 Difference]: Start difference. First operand 126 states and 182 transitions. cyclomatic complexity: 57 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:00,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:00,333 INFO L93 Difference]: Finished difference Result 304 states and 423 transitions. [2022-02-21 04:24:00,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:00,334 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:00,356 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:00,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 304 states and 423 transitions. [2022-02-21 04:24:00,376 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 254 [2022-02-21 04:24:00,389 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 304 states to 304 states and 423 transitions. [2022-02-21 04:24:00,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 304 [2022-02-21 04:24:00,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 304 [2022-02-21 04:24:00,391 INFO L73 IsDeterministic]: Start isDeterministic. Operand 304 states and 423 transitions. [2022-02-21 04:24:00,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:00,394 INFO L681 BuchiCegarLoop]: Abstraction has 304 states and 423 transitions. [2022-02-21 04:24:00,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states and 423 transitions. [2022-02-21 04:24:00,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 284. [2022-02-21 04:24:00,414 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:00,419 INFO L82 GeneralOperation]: Start isEquivalent. First operand 304 states and 423 transitions. Second operand has 284 states, 284 states have (on average 1.4049295774647887) internal successors, (399), 283 states have internal predecessors, (399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:00,420 INFO L74 IsIncluded]: Start isIncluded. First operand 304 states and 423 transitions. Second operand has 284 states, 284 states have (on average 1.4049295774647887) internal successors, (399), 283 states have internal predecessors, (399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:00,421 INFO L87 Difference]: Start difference. First operand 304 states and 423 transitions. Second operand has 284 states, 284 states have (on average 1.4049295774647887) internal successors, (399), 283 states have internal predecessors, (399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:00,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:00,438 INFO L93 Difference]: Finished difference Result 304 states and 423 transitions. [2022-02-21 04:24:00,438 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 423 transitions. [2022-02-21 04:24:00,443 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:00,444 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:00,445 INFO L74 IsIncluded]: Start isIncluded. First operand has 284 states, 284 states have (on average 1.4049295774647887) internal successors, (399), 283 states have internal predecessors, (399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 304 states and 423 transitions. [2022-02-21 04:24:00,445 INFO L87 Difference]: Start difference. First operand has 284 states, 284 states have (on average 1.4049295774647887) internal successors, (399), 283 states have internal predecessors, (399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 304 states and 423 transitions. [2022-02-21 04:24:00,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:00,455 INFO L93 Difference]: Finished difference Result 304 states and 423 transitions. [2022-02-21 04:24:00,455 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 423 transitions. [2022-02-21 04:24:00,456 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:00,456 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:00,456 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:00,456 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:00,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4049295774647887) internal successors, (399), 283 states have internal predecessors, (399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:00,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 399 transitions. [2022-02-21 04:24:00,465 INFO L704 BuchiCegarLoop]: Abstraction has 284 states and 399 transitions. [2022-02-21 04:24:00,465 INFO L587 BuchiCegarLoop]: Abstraction has 284 states and 399 transitions. [2022-02-21 04:24:00,465 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:00,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 399 transitions. [2022-02-21 04:24:00,468 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 252 [2022-02-21 04:24:00,468 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:00,468 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:00,473 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:00,473 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:00,474 INFO L791 eck$LassoCheckResult]: Stem: 1104#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1037#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 989#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 990#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 983#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 974#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 975#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1074#L250 assume !(0 == ~M_E~0); 1083#L250-2 assume !(0 == ~T1_E~0); 1025#L255-1 assume !(0 == ~E_1~0); 1026#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1042#L115 assume !(1 == ~m_pc~0); 1043#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1047#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1060#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1056#L300 assume !(0 != activate_threads_~tmp~1#1); 1057#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1095#L134 assume !(1 == ~t1_pc~0); 1052#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1044#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1045#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 981#L308 assume !(0 != activate_threads_~tmp___0~0#1); 982#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1048#L273 assume !(1 == ~M_E~0); 1049#L273-2 assume !(1 == ~T1_E~0); 1092#L278-1 assume !(1 == ~E_1~0); 1063#L283-1 assume { :end_inline_reset_delta_events } true; 1064#L404-2 [2022-02-21 04:24:00,474 INFO L793 eck$LassoCheckResult]: Loop: 1064#L404-2 assume !false; 1075#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1031#L225 assume !false; 1032#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1078#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1014#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1073#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1023#L206 assume !(0 != eval_~tmp~0#1); 1006#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1007#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1102#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1089#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1090#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 976#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 977#L115-6 assume !(1 == ~m_pc~0); 1038#L115-8 is_master_triggered_~__retres1~0#1 := 0; 1106#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1050#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1051#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1067#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1103#L134-6 assume !(1 == ~t1_pc~0); 1016#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1017#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1041#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1039#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 978#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 979#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1033#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1019#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1020#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1070#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1071#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1097#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 994#L423 assume !(0 == start_simulation_~tmp~3#1); 992#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 993#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1000#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1065#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1241#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1240#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1239#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1238#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1064#L404-2 [2022-02-21 04:24:00,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:00,478 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2022-02-21 04:24:00,478 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:00,479 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [141042642] [2022-02-21 04:24:00,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:00,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:00,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:00,511 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:00,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:00,548 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:00,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:00,548 INFO L85 PathProgramCache]: Analyzing trace with hash -753654691, now seen corresponding path program 1 times [2022-02-21 04:24:00,549 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:00,549 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83854384] [2022-02-21 04:24:00,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:00,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:00,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:00,598 INFO L290 TraceCheckUtils]: 0: Hoare triple {1867#true} assume !false; {1867#true} is VALID [2022-02-21 04:24:00,598 INFO L290 TraceCheckUtils]: 1: Hoare triple {1867#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1867#true} is VALID [2022-02-21 04:24:00,598 INFO L290 TraceCheckUtils]: 2: Hoare triple {1867#true} assume !false; {1867#true} is VALID [2022-02-21 04:24:00,599 INFO L290 TraceCheckUtils]: 3: Hoare triple {1867#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {1867#true} is VALID [2022-02-21 04:24:00,599 INFO L290 TraceCheckUtils]: 4: Hoare triple {1867#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {1869#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:24:00,600 INFO L290 TraceCheckUtils]: 5: Hoare triple {1869#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {1870#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:00,600 INFO L290 TraceCheckUtils]: 6: Hoare triple {1870#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {1871#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:00,600 INFO L290 TraceCheckUtils]: 7: Hoare triple {1871#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {1868#false} is VALID [2022-02-21 04:24:00,601 INFO L290 TraceCheckUtils]: 8: Hoare triple {1868#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1868#false} is VALID [2022-02-21 04:24:00,601 INFO L290 TraceCheckUtils]: 9: Hoare triple {1868#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1868#false} is VALID [2022-02-21 04:24:00,601 INFO L290 TraceCheckUtils]: 10: Hoare triple {1868#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1868#false} is VALID [2022-02-21 04:24:00,601 INFO L290 TraceCheckUtils]: 11: Hoare triple {1868#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1868#false} is VALID [2022-02-21 04:24:00,601 INFO L290 TraceCheckUtils]: 12: Hoare triple {1868#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1868#false} is VALID [2022-02-21 04:24:00,602 INFO L290 TraceCheckUtils]: 13: Hoare triple {1868#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1868#false} is VALID [2022-02-21 04:24:00,602 INFO L290 TraceCheckUtils]: 14: Hoare triple {1868#false} assume !(1 == ~m_pc~0); {1868#false} is VALID [2022-02-21 04:24:00,602 INFO L290 TraceCheckUtils]: 15: Hoare triple {1868#false} is_master_triggered_~__retres1~0#1 := 0; {1868#false} is VALID [2022-02-21 04:24:00,602 INFO L290 TraceCheckUtils]: 16: Hoare triple {1868#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1868#false} is VALID [2022-02-21 04:24:00,602 INFO L290 TraceCheckUtils]: 17: Hoare triple {1868#false} activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {1868#false} is VALID [2022-02-21 04:24:00,603 INFO L290 TraceCheckUtils]: 18: Hoare triple {1868#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1868#false} is VALID [2022-02-21 04:24:00,603 INFO L290 TraceCheckUtils]: 19: Hoare triple {1868#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1868#false} is VALID [2022-02-21 04:24:00,603 INFO L290 TraceCheckUtils]: 20: Hoare triple {1868#false} assume !(1 == ~t1_pc~0); {1868#false} is VALID [2022-02-21 04:24:00,603 INFO L290 TraceCheckUtils]: 21: Hoare triple {1868#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1868#false} is VALID [2022-02-21 04:24:00,603 INFO L290 TraceCheckUtils]: 22: Hoare triple {1868#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1868#false} is VALID [2022-02-21 04:24:00,603 INFO L290 TraceCheckUtils]: 23: Hoare triple {1868#false} activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {1868#false} is VALID [2022-02-21 04:24:00,604 INFO L290 TraceCheckUtils]: 24: Hoare triple {1868#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1868#false} is VALID [2022-02-21 04:24:00,604 INFO L290 TraceCheckUtils]: 25: Hoare triple {1868#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1868#false} is VALID [2022-02-21 04:24:00,604 INFO L290 TraceCheckUtils]: 26: Hoare triple {1868#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1868#false} is VALID [2022-02-21 04:24:00,604 INFO L290 TraceCheckUtils]: 27: Hoare triple {1868#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1868#false} is VALID [2022-02-21 04:24:00,604 INFO L290 TraceCheckUtils]: 28: Hoare triple {1868#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1868#false} is VALID [2022-02-21 04:24:00,604 INFO L290 TraceCheckUtils]: 29: Hoare triple {1868#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {1868#false} is VALID [2022-02-21 04:24:00,605 INFO L290 TraceCheckUtils]: 30: Hoare triple {1868#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {1868#false} is VALID [2022-02-21 04:24:00,605 INFO L290 TraceCheckUtils]: 31: Hoare triple {1868#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {1868#false} is VALID [2022-02-21 04:24:00,605 INFO L290 TraceCheckUtils]: 32: Hoare triple {1868#false} start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; {1868#false} is VALID [2022-02-21 04:24:00,605 INFO L290 TraceCheckUtils]: 33: Hoare triple {1868#false} assume !(0 == start_simulation_~tmp~3#1); {1868#false} is VALID [2022-02-21 04:24:00,605 INFO L290 TraceCheckUtils]: 34: Hoare triple {1868#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {1868#false} is VALID [2022-02-21 04:24:00,606 INFO L290 TraceCheckUtils]: 35: Hoare triple {1868#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {1868#false} is VALID [2022-02-21 04:24:00,606 INFO L290 TraceCheckUtils]: 36: Hoare triple {1868#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {1868#false} is VALID [2022-02-21 04:24:00,606 INFO L290 TraceCheckUtils]: 37: Hoare triple {1868#false} stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; {1868#false} is VALID [2022-02-21 04:24:00,606 INFO L290 TraceCheckUtils]: 38: Hoare triple {1868#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1868#false} is VALID [2022-02-21 04:24:00,606 INFO L290 TraceCheckUtils]: 39: Hoare triple {1868#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1868#false} is VALID [2022-02-21 04:24:00,606 INFO L290 TraceCheckUtils]: 40: Hoare triple {1868#false} start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {1868#false} is VALID [2022-02-21 04:24:00,607 INFO L290 TraceCheckUtils]: 41: Hoare triple {1868#false} assume !(0 != start_simulation_~tmp___0~1#1); {1868#false} is VALID [2022-02-21 04:24:00,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:00,607 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:00,607 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [83854384] [2022-02-21 04:24:00,608 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [83854384] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:00,608 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:00,608 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:00,608 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [399335878] [2022-02-21 04:24:00,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:00,609 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:00,609 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:00,609 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:00,609 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:00,610 INFO L87 Difference]: Start difference. First operand 284 states and 399 transitions. cyclomatic complexity: 117 Second operand has 5 states, 5 states have (on average 8.4) internal successors, (42), 5 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:01,006 INFO L93 Difference]: Finished difference Result 478 states and 654 transitions. [2022-02-21 04:24:01,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-02-21 04:24:01,007 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 8.4) internal successors, (42), 5 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,041 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 42 edges. 42 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:01,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 654 transitions. [2022-02-21 04:24:01,060 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 441 [2022-02-21 04:24:01,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 478 states and 654 transitions. [2022-02-21 04:24:01,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 478 [2022-02-21 04:24:01,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 478 [2022-02-21 04:24:01,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 478 states and 654 transitions. [2022-02-21 04:24:01,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:01,090 INFO L681 BuchiCegarLoop]: Abstraction has 478 states and 654 transitions. [2022-02-21 04:24:01,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states and 654 transitions. [2022-02-21 04:24:01,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 293. [2022-02-21 04:24:01,098 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:01,099 INFO L82 GeneralOperation]: Start isEquivalent. First operand 478 states and 654 transitions. Second operand has 293 states, 293 states have (on average 1.3924914675767919) internal successors, (408), 292 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,100 INFO L74 IsIncluded]: Start isIncluded. First operand 478 states and 654 transitions. Second operand has 293 states, 293 states have (on average 1.3924914675767919) internal successors, (408), 292 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,101 INFO L87 Difference]: Start difference. First operand 478 states and 654 transitions. Second operand has 293 states, 293 states have (on average 1.3924914675767919) internal successors, (408), 292 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:01,115 INFO L93 Difference]: Finished difference Result 478 states and 654 transitions. [2022-02-21 04:24:01,115 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 654 transitions. [2022-02-21 04:24:01,116 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:01,116 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:01,117 INFO L74 IsIncluded]: Start isIncluded. First operand has 293 states, 293 states have (on average 1.3924914675767919) internal successors, (408), 292 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 478 states and 654 transitions. [2022-02-21 04:24:01,117 INFO L87 Difference]: Start difference. First operand has 293 states, 293 states have (on average 1.3924914675767919) internal successors, (408), 292 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 478 states and 654 transitions. [2022-02-21 04:24:01,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:01,132 INFO L93 Difference]: Finished difference Result 478 states and 654 transitions. [2022-02-21 04:24:01,132 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 654 transitions. [2022-02-21 04:24:01,133 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:01,133 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:01,133 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:01,134 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:01,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 293 states, 293 states have (on average 1.3924914675767919) internal successors, (408), 292 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 293 states to 293 states and 408 transitions. [2022-02-21 04:24:01,142 INFO L704 BuchiCegarLoop]: Abstraction has 293 states and 408 transitions. [2022-02-21 04:24:01,142 INFO L587 BuchiCegarLoop]: Abstraction has 293 states and 408 transitions. [2022-02-21 04:24:01,142 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:01,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 293 states and 408 transitions. [2022-02-21 04:24:01,144 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 261 [2022-02-21 04:24:01,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:01,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:01,145 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:01,145 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:01,145 INFO L791 eck$LassoCheckResult]: Stem: 2502#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2377#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2378#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2371#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2362#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2363#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2469#L250 assume !(0 == ~M_E~0); 2483#L250-2 assume !(0 == ~T1_E~0); 2416#L255-1 assume !(0 == ~E_1~0); 2417#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2436#L115 assume !(1 == ~m_pc~0); 2437#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2441#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2454#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2450#L300 assume !(0 != activate_threads_~tmp~1#1); 2451#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2491#L134 assume !(1 == ~t1_pc~0); 2448#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2438#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2439#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2369#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2370#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2442#L273 assume !(1 == ~M_E~0); 2443#L273-2 assume !(1 == ~T1_E~0); 2487#L278-1 assume !(1 == ~E_1~0); 2458#L283-1 assume { :end_inline_reset_delta_events } true; 2459#L404-2 [2022-02-21 04:24:01,146 INFO L793 eck$LassoCheckResult]: Loop: 2459#L404-2 assume !false; 2576#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2571#L225 assume !false; 2558#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2557#L179 assume !(0 == ~m_st~0); 2554#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2551#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2546#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2544#L206 assume !(0 != eval_~tmp~0#1); 2395#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2396#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2499#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2503#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2526#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2527#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2429#L115-6 assume !(1 == ~m_pc~0); 2430#L115-8 is_master_triggered_~__retres1~0#1 := 0; 2505#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2444#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2445#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2500#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2501#L134-6 assume !(1 == ~t1_pc~0); 2622#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2433#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2434#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2495#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2620#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2619#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2422#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2410#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2411#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2465#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2466#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2493#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2382#L423 assume !(0 == start_simulation_~tmp~3#1); 2384#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2592#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2589#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2587#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2585#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2583#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2581#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2579#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2459#L404-2 [2022-02-21 04:24:01,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:01,146 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2022-02-21 04:24:01,146 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:01,147 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643723163] [2022-02-21 04:24:01,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:01,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:01,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:01,157 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:01,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:01,167 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:01,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:01,168 INFO L85 PathProgramCache]: Analyzing trace with hash -682345966, now seen corresponding path program 1 times [2022-02-21 04:24:01,168 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:01,168 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565010437] [2022-02-21 04:24:01,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:01,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:01,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:01,265 INFO L290 TraceCheckUtils]: 0: Hoare triple {3612#true} assume !false; {3612#true} is VALID [2022-02-21 04:24:01,266 INFO L290 TraceCheckUtils]: 1: Hoare triple {3612#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {3612#true} is VALID [2022-02-21 04:24:01,266 INFO L290 TraceCheckUtils]: 2: Hoare triple {3612#true} assume !false; {3612#true} is VALID [2022-02-21 04:24:01,266 INFO L290 TraceCheckUtils]: 3: Hoare triple {3612#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {3612#true} is VALID [2022-02-21 04:24:01,266 INFO L290 TraceCheckUtils]: 4: Hoare triple {3612#true} assume !(0 == ~m_st~0); {3612#true} is VALID [2022-02-21 04:24:01,267 INFO L290 TraceCheckUtils]: 5: Hoare triple {3612#true} assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {3612#true} is VALID [2022-02-21 04:24:01,267 INFO L290 TraceCheckUtils]: 6: Hoare triple {3612#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {3612#true} is VALID [2022-02-21 04:24:01,267 INFO L290 TraceCheckUtils]: 7: Hoare triple {3612#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {3612#true} is VALID [2022-02-21 04:24:01,267 INFO L290 TraceCheckUtils]: 8: Hoare triple {3612#true} assume !(0 != eval_~tmp~0#1); {3612#true} is VALID [2022-02-21 04:24:01,267 INFO L290 TraceCheckUtils]: 9: Hoare triple {3612#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {3612#true} is VALID [2022-02-21 04:24:01,267 INFO L290 TraceCheckUtils]: 10: Hoare triple {3612#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {3612#true} is VALID [2022-02-21 04:24:01,268 INFO L290 TraceCheckUtils]: 11: Hoare triple {3612#true} assume 0 == ~M_E~0;~M_E~0 := 1; {3612#true} is VALID [2022-02-21 04:24:01,268 INFO L290 TraceCheckUtils]: 12: Hoare triple {3612#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {3612#true} is VALID [2022-02-21 04:24:01,268 INFO L290 TraceCheckUtils]: 13: Hoare triple {3612#true} assume 0 == ~E_1~0;~E_1~0 := 1; {3612#true} is VALID [2022-02-21 04:24:01,268 INFO L290 TraceCheckUtils]: 14: Hoare triple {3612#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3612#true} is VALID [2022-02-21 04:24:01,268 INFO L290 TraceCheckUtils]: 15: Hoare triple {3612#true} assume !(1 == ~m_pc~0); {3612#true} is VALID [2022-02-21 04:24:01,269 INFO L290 TraceCheckUtils]: 16: Hoare triple {3612#true} is_master_triggered_~__retres1~0#1 := 0; {3614#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is VALID [2022-02-21 04:24:01,269 INFO L290 TraceCheckUtils]: 17: Hoare triple {3614#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3615#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} is VALID [2022-02-21 04:24:01,270 INFO L290 TraceCheckUtils]: 18: Hoare triple {3615#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {3616#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} is VALID [2022-02-21 04:24:01,270 INFO L290 TraceCheckUtils]: 19: Hoare triple {3616#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {3613#false} is VALID [2022-02-21 04:24:01,270 INFO L290 TraceCheckUtils]: 20: Hoare triple {3613#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3613#false} is VALID [2022-02-21 04:24:01,270 INFO L290 TraceCheckUtils]: 21: Hoare triple {3613#false} assume !(1 == ~t1_pc~0); {3613#false} is VALID [2022-02-21 04:24:01,271 INFO L290 TraceCheckUtils]: 22: Hoare triple {3613#false} is_transmit1_triggered_~__retres1~1#1 := 0; {3613#false} is VALID [2022-02-21 04:24:01,271 INFO L290 TraceCheckUtils]: 23: Hoare triple {3613#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3613#false} is VALID [2022-02-21 04:24:01,271 INFO L290 TraceCheckUtils]: 24: Hoare triple {3613#false} activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {3613#false} is VALID [2022-02-21 04:24:01,271 INFO L290 TraceCheckUtils]: 25: Hoare triple {3613#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3613#false} is VALID [2022-02-21 04:24:01,271 INFO L290 TraceCheckUtils]: 26: Hoare triple {3613#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3613#false} is VALID [2022-02-21 04:24:01,271 INFO L290 TraceCheckUtils]: 27: Hoare triple {3613#false} assume 1 == ~M_E~0;~M_E~0 := 2; {3613#false} is VALID [2022-02-21 04:24:01,272 INFO L290 TraceCheckUtils]: 28: Hoare triple {3613#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {3613#false} is VALID [2022-02-21 04:24:01,272 INFO L290 TraceCheckUtils]: 29: Hoare triple {3613#false} assume 1 == ~E_1~0;~E_1~0 := 2; {3613#false} is VALID [2022-02-21 04:24:01,272 INFO L290 TraceCheckUtils]: 30: Hoare triple {3613#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {3613#false} is VALID [2022-02-21 04:24:01,272 INFO L290 TraceCheckUtils]: 31: Hoare triple {3613#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {3613#false} is VALID [2022-02-21 04:24:01,272 INFO L290 TraceCheckUtils]: 32: Hoare triple {3613#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {3613#false} is VALID [2022-02-21 04:24:01,273 INFO L290 TraceCheckUtils]: 33: Hoare triple {3613#false} start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; {3613#false} is VALID [2022-02-21 04:24:01,273 INFO L290 TraceCheckUtils]: 34: Hoare triple {3613#false} assume !(0 == start_simulation_~tmp~3#1); {3613#false} is VALID [2022-02-21 04:24:01,273 INFO L290 TraceCheckUtils]: 35: Hoare triple {3613#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {3613#false} is VALID [2022-02-21 04:24:01,273 INFO L290 TraceCheckUtils]: 36: Hoare triple {3613#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {3613#false} is VALID [2022-02-21 04:24:01,273 INFO L290 TraceCheckUtils]: 37: Hoare triple {3613#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {3613#false} is VALID [2022-02-21 04:24:01,273 INFO L290 TraceCheckUtils]: 38: Hoare triple {3613#false} stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; {3613#false} is VALID [2022-02-21 04:24:01,273 INFO L290 TraceCheckUtils]: 39: Hoare triple {3613#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {3613#false} is VALID [2022-02-21 04:24:01,274 INFO L290 TraceCheckUtils]: 40: Hoare triple {3613#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {3613#false} is VALID [2022-02-21 04:24:01,274 INFO L290 TraceCheckUtils]: 41: Hoare triple {3613#false} start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {3613#false} is VALID [2022-02-21 04:24:01,274 INFO L290 TraceCheckUtils]: 42: Hoare triple {3613#false} assume !(0 != start_simulation_~tmp___0~1#1); {3613#false} is VALID [2022-02-21 04:24:01,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:01,275 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:01,275 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565010437] [2022-02-21 04:24:01,275 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565010437] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:01,275 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:01,275 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:01,275 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [216089905] [2022-02-21 04:24:01,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:01,276 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:01,276 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:01,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:01,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:01,277 INFO L87 Difference]: Start difference. First operand 293 states and 408 transitions. cyclomatic complexity: 117 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:01,950 INFO L93 Difference]: Finished difference Result 623 states and 857 transitions. [2022-02-21 04:24:01,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:24:01,951 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,987 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:01,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 623 states and 857 transitions. [2022-02-21 04:24:02,008 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 591 [2022-02-21 04:24:02,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 623 states to 623 states and 857 transitions. [2022-02-21 04:24:02,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 623 [2022-02-21 04:24:02,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 623 [2022-02-21 04:24:02,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 623 states and 857 transitions. [2022-02-21 04:24:02,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:02,028 INFO L681 BuchiCegarLoop]: Abstraction has 623 states and 857 transitions. [2022-02-21 04:24:02,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 623 states and 857 transitions. [2022-02-21 04:24:02,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 623 to 311. [2022-02-21 04:24:02,032 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:02,033 INFO L82 GeneralOperation]: Start isEquivalent. First operand 623 states and 857 transitions. Second operand has 311 states, 311 states have (on average 1.360128617363344) internal successors, (423), 310 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,034 INFO L74 IsIncluded]: Start isIncluded. First operand 623 states and 857 transitions. Second operand has 311 states, 311 states have (on average 1.360128617363344) internal successors, (423), 310 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,035 INFO L87 Difference]: Start difference. First operand 623 states and 857 transitions. Second operand has 311 states, 311 states have (on average 1.360128617363344) internal successors, (423), 310 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,052 INFO L93 Difference]: Finished difference Result 623 states and 857 transitions. [2022-02-21 04:24:02,052 INFO L276 IsEmpty]: Start isEmpty. Operand 623 states and 857 transitions. [2022-02-21 04:24:02,053 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:02,053 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:02,054 INFO L74 IsIncluded]: Start isIncluded. First operand has 311 states, 311 states have (on average 1.360128617363344) internal successors, (423), 310 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 623 states and 857 transitions. [2022-02-21 04:24:02,055 INFO L87 Difference]: Start difference. First operand has 311 states, 311 states have (on average 1.360128617363344) internal successors, (423), 310 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 623 states and 857 transitions. [2022-02-21 04:24:02,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,072 INFO L93 Difference]: Finished difference Result 623 states and 857 transitions. [2022-02-21 04:24:02,072 INFO L276 IsEmpty]: Start isEmpty. Operand 623 states and 857 transitions. [2022-02-21 04:24:02,073 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:02,074 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:02,074 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:02,074 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:02,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 311 states, 311 states have (on average 1.360128617363344) internal successors, (423), 310 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 423 transitions. [2022-02-21 04:24:02,080 INFO L704 BuchiCegarLoop]: Abstraction has 311 states and 423 transitions. [2022-02-21 04:24:02,080 INFO L587 BuchiCegarLoop]: Abstraction has 311 states and 423 transitions. [2022-02-21 04:24:02,080 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:02,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 311 states and 423 transitions. [2022-02-21 04:24:02,082 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 279 [2022-02-21 04:24:02,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:02,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:02,084 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,084 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,084 INFO L791 eck$LassoCheckResult]: Stem: 4380#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 4313#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 4264#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4265#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4258#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 4249#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4250#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4353#L250 assume !(0 == ~M_E~0); 4361#L250-2 assume !(0 == ~T1_E~0); 4304#L255-1 assume !(0 == ~E_1~0); 4305#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4320#L115 assume !(1 == ~m_pc~0); 4321#L115-2 is_master_triggered_~__retres1~0#1 := 0; 4326#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4338#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4335#L300 assume !(0 != activate_threads_~tmp~1#1); 4336#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4371#L134 assume !(1 == ~t1_pc~0); 4333#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4323#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4324#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4256#L308 assume !(0 != activate_threads_~tmp___0~0#1); 4257#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4327#L273 assume !(1 == ~M_E~0); 4328#L273-2 assume !(1 == ~T1_E~0); 4368#L278-1 assume !(1 == ~E_1~0); 4341#L283-1 assume { :end_inline_reset_delta_events } true; 4342#L404-2 [2022-02-21 04:24:02,086 INFO L793 eck$LassoCheckResult]: Loop: 4342#L404-2 assume !false; 4423#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4421#L225 assume !false; 4420#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4418#L179 assume !(0 == ~m_st~0); 4419#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 4417#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4415#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4413#L206 assume !(0 != eval_~tmp~0#1); 4411#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4409#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4406#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4403#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4401#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4398#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4314#L115-6 assume !(1 == ~m_pc~0); 4315#L115-8 is_master_triggered_~__retres1~0#1 := 0; 4466#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4465#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4464#L300-6 assume !(0 != activate_threads_~tmp~1#1); 4463#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4462#L134-6 assume !(1 == ~t1_pc~0); 4460#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 4458#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4456#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4454#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4452#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4450#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4448#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4446#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4444#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4441#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4439#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4437#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 4434#L423 assume !(0 == start_simulation_~tmp~3#1); 4432#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4430#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4429#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4428#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 4427#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4426#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4425#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 4424#L436 assume !(0 != start_simulation_~tmp___0~1#1); 4342#L404-2 [2022-02-21 04:24:02,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,086 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2022-02-21 04:24:02,086 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,087 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166609549] [2022-02-21 04:24:02,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:02,112 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:02,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:02,121 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:02,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,122 INFO L85 PathProgramCache]: Analyzing trace with hash -816359472, now seen corresponding path program 1 times [2022-02-21 04:24:02,122 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,122 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613951618] [2022-02-21 04:24:02,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:02,152 INFO L290 TraceCheckUtils]: 0: Hoare triple {5807#true} assume !false; {5807#true} is VALID [2022-02-21 04:24:02,152 INFO L290 TraceCheckUtils]: 1: Hoare triple {5807#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {5807#true} is VALID [2022-02-21 04:24:02,152 INFO L290 TraceCheckUtils]: 2: Hoare triple {5807#true} assume !false; {5807#true} is VALID [2022-02-21 04:24:02,152 INFO L290 TraceCheckUtils]: 3: Hoare triple {5807#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {5807#true} is VALID [2022-02-21 04:24:02,153 INFO L290 TraceCheckUtils]: 4: Hoare triple {5807#true} assume !(0 == ~m_st~0); {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,153 INFO L290 TraceCheckUtils]: 5: Hoare triple {5809#(not (= ~m_st~0 0))} assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,153 INFO L290 TraceCheckUtils]: 6: Hoare triple {5809#(not (= ~m_st~0 0))} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,154 INFO L290 TraceCheckUtils]: 7: Hoare triple {5809#(not (= ~m_st~0 0))} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,154 INFO L290 TraceCheckUtils]: 8: Hoare triple {5809#(not (= ~m_st~0 0))} assume !(0 != eval_~tmp~0#1); {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,154 INFO L290 TraceCheckUtils]: 9: Hoare triple {5809#(not (= ~m_st~0 0))} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,154 INFO L290 TraceCheckUtils]: 10: Hoare triple {5809#(not (= ~m_st~0 0))} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,155 INFO L290 TraceCheckUtils]: 11: Hoare triple {5809#(not (= ~m_st~0 0))} assume 0 == ~M_E~0;~M_E~0 := 1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,155 INFO L290 TraceCheckUtils]: 12: Hoare triple {5809#(not (= ~m_st~0 0))} assume 0 == ~T1_E~0;~T1_E~0 := 1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,155 INFO L290 TraceCheckUtils]: 13: Hoare triple {5809#(not (= ~m_st~0 0))} assume 0 == ~E_1~0;~E_1~0 := 1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,156 INFO L290 TraceCheckUtils]: 14: Hoare triple {5809#(not (= ~m_st~0 0))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,156 INFO L290 TraceCheckUtils]: 15: Hoare triple {5809#(not (= ~m_st~0 0))} assume !(1 == ~m_pc~0); {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,156 INFO L290 TraceCheckUtils]: 16: Hoare triple {5809#(not (= ~m_st~0 0))} is_master_triggered_~__retres1~0#1 := 0; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,156 INFO L290 TraceCheckUtils]: 17: Hoare triple {5809#(not (= ~m_st~0 0))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,157 INFO L290 TraceCheckUtils]: 18: Hoare triple {5809#(not (= ~m_st~0 0))} activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,157 INFO L290 TraceCheckUtils]: 19: Hoare triple {5809#(not (= ~m_st~0 0))} assume !(0 != activate_threads_~tmp~1#1); {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,157 INFO L290 TraceCheckUtils]: 20: Hoare triple {5809#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,158 INFO L290 TraceCheckUtils]: 21: Hoare triple {5809#(not (= ~m_st~0 0))} assume !(1 == ~t1_pc~0); {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,158 INFO L290 TraceCheckUtils]: 22: Hoare triple {5809#(not (= ~m_st~0 0))} is_transmit1_triggered_~__retres1~1#1 := 0; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,158 INFO L290 TraceCheckUtils]: 23: Hoare triple {5809#(not (= ~m_st~0 0))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,158 INFO L290 TraceCheckUtils]: 24: Hoare triple {5809#(not (= ~m_st~0 0))} activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,159 INFO L290 TraceCheckUtils]: 25: Hoare triple {5809#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,159 INFO L290 TraceCheckUtils]: 26: Hoare triple {5809#(not (= ~m_st~0 0))} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,159 INFO L290 TraceCheckUtils]: 27: Hoare triple {5809#(not (= ~m_st~0 0))} assume 1 == ~M_E~0;~M_E~0 := 2; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,160 INFO L290 TraceCheckUtils]: 28: Hoare triple {5809#(not (= ~m_st~0 0))} assume 1 == ~T1_E~0;~T1_E~0 := 2; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,160 INFO L290 TraceCheckUtils]: 29: Hoare triple {5809#(not (= ~m_st~0 0))} assume 1 == ~E_1~0;~E_1~0 := 2; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,160 INFO L290 TraceCheckUtils]: 30: Hoare triple {5809#(not (= ~m_st~0 0))} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {5809#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:02,161 INFO L290 TraceCheckUtils]: 31: Hoare triple {5809#(not (= ~m_st~0 0))} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {5808#false} is VALID [2022-02-21 04:24:02,161 INFO L290 TraceCheckUtils]: 32: Hoare triple {5808#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {5808#false} is VALID [2022-02-21 04:24:02,161 INFO L290 TraceCheckUtils]: 33: Hoare triple {5808#false} start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; {5808#false} is VALID [2022-02-21 04:24:02,161 INFO L290 TraceCheckUtils]: 34: Hoare triple {5808#false} assume !(0 == start_simulation_~tmp~3#1); {5808#false} is VALID [2022-02-21 04:24:02,161 INFO L290 TraceCheckUtils]: 35: Hoare triple {5808#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {5808#false} is VALID [2022-02-21 04:24:02,162 INFO L290 TraceCheckUtils]: 36: Hoare triple {5808#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {5808#false} is VALID [2022-02-21 04:24:02,162 INFO L290 TraceCheckUtils]: 37: Hoare triple {5808#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {5808#false} is VALID [2022-02-21 04:24:02,162 INFO L290 TraceCheckUtils]: 38: Hoare triple {5808#false} stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; {5808#false} is VALID [2022-02-21 04:24:02,162 INFO L290 TraceCheckUtils]: 39: Hoare triple {5808#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {5808#false} is VALID [2022-02-21 04:24:02,162 INFO L290 TraceCheckUtils]: 40: Hoare triple {5808#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {5808#false} is VALID [2022-02-21 04:24:02,162 INFO L290 TraceCheckUtils]: 41: Hoare triple {5808#false} start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {5808#false} is VALID [2022-02-21 04:24:02,162 INFO L290 TraceCheckUtils]: 42: Hoare triple {5808#false} assume !(0 != start_simulation_~tmp___0~1#1); {5808#false} is VALID [2022-02-21 04:24:02,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:02,163 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:02,163 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613951618] [2022-02-21 04:24:02,163 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613951618] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:02,163 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:02,164 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:02,164 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145443945] [2022-02-21 04:24:02,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:02,164 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:02,164 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:02,165 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:02,165 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:02,165 INFO L87 Difference]: Start difference. First operand 311 states and 423 transitions. cyclomatic complexity: 114 Second operand has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,317 INFO L93 Difference]: Finished difference Result 460 states and 611 transitions. [2022-02-21 04:24:02,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:02,317 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,363 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:02,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 460 states and 611 transitions. [2022-02-21 04:24:02,376 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 426 [2022-02-21 04:24:02,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 460 states to 460 states and 611 transitions. [2022-02-21 04:24:02,387 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 460 [2022-02-21 04:24:02,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 460 [2022-02-21 04:24:02,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 460 states and 611 transitions. [2022-02-21 04:24:02,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:02,388 INFO L681 BuchiCegarLoop]: Abstraction has 460 states and 611 transitions. [2022-02-21 04:24:02,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states and 611 transitions. [2022-02-21 04:24:02,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 439. [2022-02-21 04:24:02,393 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:02,394 INFO L82 GeneralOperation]: Start isEquivalent. First operand 460 states and 611 transitions. Second operand has 439 states, 439 states have (on average 1.3348519362186788) internal successors, (586), 438 states have internal predecessors, (586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,395 INFO L74 IsIncluded]: Start isIncluded. First operand 460 states and 611 transitions. Second operand has 439 states, 439 states have (on average 1.3348519362186788) internal successors, (586), 438 states have internal predecessors, (586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,396 INFO L87 Difference]: Start difference. First operand 460 states and 611 transitions. Second operand has 439 states, 439 states have (on average 1.3348519362186788) internal successors, (586), 438 states have internal predecessors, (586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,406 INFO L93 Difference]: Finished difference Result 460 states and 611 transitions. [2022-02-21 04:24:02,406 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 611 transitions. [2022-02-21 04:24:02,407 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:02,407 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:02,408 INFO L74 IsIncluded]: Start isIncluded. First operand has 439 states, 439 states have (on average 1.3348519362186788) internal successors, (586), 438 states have internal predecessors, (586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 460 states and 611 transitions. [2022-02-21 04:24:02,409 INFO L87 Difference]: Start difference. First operand has 439 states, 439 states have (on average 1.3348519362186788) internal successors, (586), 438 states have internal predecessors, (586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 460 states and 611 transitions. [2022-02-21 04:24:02,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,420 INFO L93 Difference]: Finished difference Result 460 states and 611 transitions. [2022-02-21 04:24:02,420 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 611 transitions. [2022-02-21 04:24:02,421 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:02,421 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:02,421 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:02,421 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:02,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 439 states, 439 states have (on average 1.3348519362186788) internal successors, (586), 438 states have internal predecessors, (586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 439 states to 439 states and 586 transitions. [2022-02-21 04:24:02,432 INFO L704 BuchiCegarLoop]: Abstraction has 439 states and 586 transitions. [2022-02-21 04:24:02,432 INFO L587 BuchiCegarLoop]: Abstraction has 439 states and 586 transitions. [2022-02-21 04:24:02,432 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:02,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 439 states and 586 transitions. [2022-02-21 04:24:02,434 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 405 [2022-02-21 04:24:02,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:02,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:02,435 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,435 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,435 INFO L791 eck$LassoCheckResult]: Stem: 6407#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 6338#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 6289#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6290#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6283#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 6274#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6275#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6374#L250 assume !(0 == ~M_E~0); 6384#L250-2 assume !(0 == ~T1_E~0); 6326#L255-1 assume !(0 == ~E_1~0); 6327#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6343#L115 assume !(1 == ~m_pc~0); 6344#L115-2 is_master_triggered_~__retres1~0#1 := 0; 6348#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6360#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6356#L300 assume !(0 != activate_threads_~tmp~1#1); 6357#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6397#L134 assume !(1 == ~t1_pc~0); 6355#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6345#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6346#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6281#L308 assume !(0 != activate_threads_~tmp___0~0#1); 6282#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6349#L273 assume !(1 == ~M_E~0); 6350#L273-2 assume !(1 == ~T1_E~0); 6392#L278-1 assume !(1 == ~E_1~0); 6364#L283-1 assume { :end_inline_reset_delta_events } true; 6365#L404-2 assume !false; 6611#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6609#L225 [2022-02-21 04:24:02,435 INFO L793 eck$LassoCheckResult]: Loop: 6609#L225 assume !false; 6608#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6606#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6604#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6602#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6600#L206 assume 0 != eval_~tmp~0#1; 6598#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 6595#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 6596#L211 assume !(0 == ~t1_st~0); 6609#L225 [2022-02-21 04:24:02,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,436 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 1 times [2022-02-21 04:24:02,436 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,436 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286477024] [2022-02-21 04:24:02,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:02,458 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:02,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:02,474 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:02,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,474 INFO L85 PathProgramCache]: Analyzing trace with hash 438949112, now seen corresponding path program 1 times [2022-02-21 04:24:02,474 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,475 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1032194142] [2022-02-21 04:24:02,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:02,478 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:02,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:02,489 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:02,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,489 INFO L85 PathProgramCache]: Analyzing trace with hash -1724815409, now seen corresponding path program 1 times [2022-02-21 04:24:02,490 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,490 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71487078] [2022-02-21 04:24:02,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:02,512 INFO L290 TraceCheckUtils]: 0: Hoare triple {7636#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; {7636#true} is VALID [2022-02-21 04:24:02,512 INFO L290 TraceCheckUtils]: 1: Hoare triple {7636#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; {7636#true} is VALID [2022-02-21 04:24:02,512 INFO L290 TraceCheckUtils]: 2: Hoare triple {7636#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {7636#true} is VALID [2022-02-21 04:24:02,512 INFO L290 TraceCheckUtils]: 3: Hoare triple {7636#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {7636#true} is VALID [2022-02-21 04:24:02,512 INFO L290 TraceCheckUtils]: 4: Hoare triple {7636#true} assume 1 == ~m_i~0;~m_st~0 := 0; {7636#true} is VALID [2022-02-21 04:24:02,514 INFO L290 TraceCheckUtils]: 5: Hoare triple {7636#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,515 INFO L290 TraceCheckUtils]: 6: Hoare triple {7638#(= ~t1_st~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,515 INFO L290 TraceCheckUtils]: 7: Hoare triple {7638#(= ~t1_st~0 0)} assume !(0 == ~M_E~0); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,515 INFO L290 TraceCheckUtils]: 8: Hoare triple {7638#(= ~t1_st~0 0)} assume !(0 == ~T1_E~0); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,516 INFO L290 TraceCheckUtils]: 9: Hoare triple {7638#(= ~t1_st~0 0)} assume !(0 == ~E_1~0); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,516 INFO L290 TraceCheckUtils]: 10: Hoare triple {7638#(= ~t1_st~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,516 INFO L290 TraceCheckUtils]: 11: Hoare triple {7638#(= ~t1_st~0 0)} assume !(1 == ~m_pc~0); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,517 INFO L290 TraceCheckUtils]: 12: Hoare triple {7638#(= ~t1_st~0 0)} is_master_triggered_~__retres1~0#1 := 0; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,517 INFO L290 TraceCheckUtils]: 13: Hoare triple {7638#(= ~t1_st~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,517 INFO L290 TraceCheckUtils]: 14: Hoare triple {7638#(= ~t1_st~0 0)} activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,518 INFO L290 TraceCheckUtils]: 15: Hoare triple {7638#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp~1#1); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,519 INFO L290 TraceCheckUtils]: 16: Hoare triple {7638#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,519 INFO L290 TraceCheckUtils]: 17: Hoare triple {7638#(= ~t1_st~0 0)} assume !(1 == ~t1_pc~0); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,520 INFO L290 TraceCheckUtils]: 18: Hoare triple {7638#(= ~t1_st~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,520 INFO L290 TraceCheckUtils]: 19: Hoare triple {7638#(= ~t1_st~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,520 INFO L290 TraceCheckUtils]: 20: Hoare triple {7638#(= ~t1_st~0 0)} activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,521 INFO L290 TraceCheckUtils]: 21: Hoare triple {7638#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,522 INFO L290 TraceCheckUtils]: 22: Hoare triple {7638#(= ~t1_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,522 INFO L290 TraceCheckUtils]: 23: Hoare triple {7638#(= ~t1_st~0 0)} assume !(1 == ~M_E~0); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,522 INFO L290 TraceCheckUtils]: 24: Hoare triple {7638#(= ~t1_st~0 0)} assume !(1 == ~T1_E~0); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,523 INFO L290 TraceCheckUtils]: 25: Hoare triple {7638#(= ~t1_st~0 0)} assume !(1 == ~E_1~0); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,523 INFO L290 TraceCheckUtils]: 26: Hoare triple {7638#(= ~t1_st~0 0)} assume { :end_inline_reset_delta_events } true; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,523 INFO L290 TraceCheckUtils]: 27: Hoare triple {7638#(= ~t1_st~0 0)} assume !false; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,524 INFO L290 TraceCheckUtils]: 28: Hoare triple {7638#(= ~t1_st~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,524 INFO L290 TraceCheckUtils]: 29: Hoare triple {7638#(= ~t1_st~0 0)} assume !false; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,524 INFO L290 TraceCheckUtils]: 30: Hoare triple {7638#(= ~t1_st~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,525 INFO L290 TraceCheckUtils]: 31: Hoare triple {7638#(= ~t1_st~0 0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,525 INFO L290 TraceCheckUtils]: 32: Hoare triple {7638#(= ~t1_st~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,525 INFO L290 TraceCheckUtils]: 33: Hoare triple {7638#(= ~t1_st~0 0)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,526 INFO L290 TraceCheckUtils]: 34: Hoare triple {7638#(= ~t1_st~0 0)} assume 0 != eval_~tmp~0#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,526 INFO L290 TraceCheckUtils]: 35: Hoare triple {7638#(= ~t1_st~0 0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,526 INFO L290 TraceCheckUtils]: 36: Hoare triple {7638#(= ~t1_st~0 0)} assume !(0 != eval_~tmp_ndt_1~0#1); {7638#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:02,527 INFO L290 TraceCheckUtils]: 37: Hoare triple {7638#(= ~t1_st~0 0)} assume !(0 == ~t1_st~0); {7637#false} is VALID [2022-02-21 04:24:02,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:02,527 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:02,527 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [71487078] [2022-02-21 04:24:02,527 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [71487078] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:02,527 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:02,527 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:02,528 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674583911] [2022-02-21 04:24:02,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:02,595 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:02,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:02,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:02,596 INFO L87 Difference]: Start difference. First operand 439 states and 586 transitions. cyclomatic complexity: 150 Second operand has 3 states, 2 states have (on average 19.0) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,859 INFO L93 Difference]: Finished difference Result 765 states and 1008 transitions. [2022-02-21 04:24:02,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:02,860 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 2 states have (on average 19.0) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,886 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:02,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 765 states and 1008 transitions. [2022-02-21 04:24:02,914 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 665 [2022-02-21 04:24:02,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 765 states to 765 states and 1008 transitions. [2022-02-21 04:24:02,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 765 [2022-02-21 04:24:02,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 765 [2022-02-21 04:24:02,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 765 states and 1008 transitions. [2022-02-21 04:24:02,941 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:02,941 INFO L681 BuchiCegarLoop]: Abstraction has 765 states and 1008 transitions. [2022-02-21 04:24:02,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 765 states and 1008 transitions. [2022-02-21 04:24:02,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 765 to 690. [2022-02-21 04:24:02,948 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:02,950 INFO L82 GeneralOperation]: Start isEquivalent. First operand 765 states and 1008 transitions. Second operand has 690 states, 690 states have (on average 1.3333333333333333) internal successors, (920), 689 states have internal predecessors, (920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,951 INFO L74 IsIncluded]: Start isIncluded. First operand 765 states and 1008 transitions. Second operand has 690 states, 690 states have (on average 1.3333333333333333) internal successors, (920), 689 states have internal predecessors, (920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,952 INFO L87 Difference]: Start difference. First operand 765 states and 1008 transitions. Second operand has 690 states, 690 states have (on average 1.3333333333333333) internal successors, (920), 689 states have internal predecessors, (920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,976 INFO L93 Difference]: Finished difference Result 765 states and 1008 transitions. [2022-02-21 04:24:02,977 INFO L276 IsEmpty]: Start isEmpty. Operand 765 states and 1008 transitions. [2022-02-21 04:24:02,978 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:02,978 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:02,979 INFO L74 IsIncluded]: Start isIncluded. First operand has 690 states, 690 states have (on average 1.3333333333333333) internal successors, (920), 689 states have internal predecessors, (920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 765 states and 1008 transitions. [2022-02-21 04:24:02,981 INFO L87 Difference]: Start difference. First operand has 690 states, 690 states have (on average 1.3333333333333333) internal successors, (920), 689 states have internal predecessors, (920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 765 states and 1008 transitions. [2022-02-21 04:24:03,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:03,005 INFO L93 Difference]: Finished difference Result 765 states and 1008 transitions. [2022-02-21 04:24:03,005 INFO L276 IsEmpty]: Start isEmpty. Operand 765 states and 1008 transitions. [2022-02-21 04:24:03,007 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:03,007 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:03,007 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:03,007 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:03,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 690 states, 690 states have (on average 1.3333333333333333) internal successors, (920), 689 states have internal predecessors, (920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 920 transitions. [2022-02-21 04:24:03,049 INFO L704 BuchiCegarLoop]: Abstraction has 690 states and 920 transitions. [2022-02-21 04:24:03,049 INFO L587 BuchiCegarLoop]: Abstraction has 690 states and 920 transitions. [2022-02-21 04:24:03,049 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:03,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 920 transitions. [2022-02-21 04:24:03,052 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 616 [2022-02-21 04:24:03,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:03,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:03,053 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:03,053 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:03,053 INFO L791 eck$LassoCheckResult]: Stem: 8542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 8472#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 8424#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8425#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8418#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 8408#L161-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 8409#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9032#L250 assume !(0 == ~M_E~0); 9031#L250-2 assume !(0 == ~T1_E~0); 9030#L255-1 assume !(0 == ~E_1~0); 9029#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9028#L115 assume !(1 == ~m_pc~0); 9027#L115-2 is_master_triggered_~__retres1~0#1 := 0; 9026#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9025#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9024#L300 assume !(0 != activate_threads_~tmp~1#1); 9023#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9022#L134 assume !(1 == ~t1_pc~0); 9021#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9020#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9019#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9018#L308 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8417#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8487#L273 assume !(1 == ~M_E~0); 8488#L273-2 assume !(1 == ~T1_E~0); 8527#L278-1 assume !(1 == ~E_1~0); 8501#L283-1 assume { :end_inline_reset_delta_events } true; 8502#L404-2 assume !false; 9093#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8517#L225 [2022-02-21 04:24:03,054 INFO L793 eck$LassoCheckResult]: Loop: 8517#L225 assume !false; 9092#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9091#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9090#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9089#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9088#L206 assume 0 != eval_~tmp~0#1; 9087#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 8547#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 8548#L211 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 8515#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 8517#L225 [2022-02-21 04:24:03,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:03,054 INFO L85 PathProgramCache]: Analyzing trace with hash -1113894070, now seen corresponding path program 1 times [2022-02-21 04:24:03,055 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:03,056 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154553209] [2022-02-21 04:24:03,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:03,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:03,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:03,072 INFO L290 TraceCheckUtils]: 0: Hoare triple {10627#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; {10627#true} is VALID [2022-02-21 04:24:03,073 INFO L290 TraceCheckUtils]: 1: Hoare triple {10627#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; {10629#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:03,073 INFO L290 TraceCheckUtils]: 2: Hoare triple {10629#(= ~t1_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10629#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:03,074 INFO L290 TraceCheckUtils]: 3: Hoare triple {10629#(= ~t1_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10629#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:03,074 INFO L290 TraceCheckUtils]: 4: Hoare triple {10629#(= ~t1_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {10629#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:03,074 INFO L290 TraceCheckUtils]: 5: Hoare triple {10629#(= ~t1_i~0 1)} assume !(1 == ~t1_i~0);~t1_st~0 := 2; {10628#false} is VALID [2022-02-21 04:24:03,074 INFO L290 TraceCheckUtils]: 6: Hoare triple {10628#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10628#false} is VALID [2022-02-21 04:24:03,075 INFO L290 TraceCheckUtils]: 7: Hoare triple {10628#false} assume !(0 == ~M_E~0); {10628#false} is VALID [2022-02-21 04:24:03,075 INFO L290 TraceCheckUtils]: 8: Hoare triple {10628#false} assume !(0 == ~T1_E~0); {10628#false} is VALID [2022-02-21 04:24:03,075 INFO L290 TraceCheckUtils]: 9: Hoare triple {10628#false} assume !(0 == ~E_1~0); {10628#false} is VALID [2022-02-21 04:24:03,075 INFO L290 TraceCheckUtils]: 10: Hoare triple {10628#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10628#false} is VALID [2022-02-21 04:24:03,075 INFO L290 TraceCheckUtils]: 11: Hoare triple {10628#false} assume !(1 == ~m_pc~0); {10628#false} is VALID [2022-02-21 04:24:03,075 INFO L290 TraceCheckUtils]: 12: Hoare triple {10628#false} is_master_triggered_~__retres1~0#1 := 0; {10628#false} is VALID [2022-02-21 04:24:03,076 INFO L290 TraceCheckUtils]: 13: Hoare triple {10628#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10628#false} is VALID [2022-02-21 04:24:03,076 INFO L290 TraceCheckUtils]: 14: Hoare triple {10628#false} activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {10628#false} is VALID [2022-02-21 04:24:03,076 INFO L290 TraceCheckUtils]: 15: Hoare triple {10628#false} assume !(0 != activate_threads_~tmp~1#1); {10628#false} is VALID [2022-02-21 04:24:03,076 INFO L290 TraceCheckUtils]: 16: Hoare triple {10628#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10628#false} is VALID [2022-02-21 04:24:03,076 INFO L290 TraceCheckUtils]: 17: Hoare triple {10628#false} assume !(1 == ~t1_pc~0); {10628#false} is VALID [2022-02-21 04:24:03,076 INFO L290 TraceCheckUtils]: 18: Hoare triple {10628#false} is_transmit1_triggered_~__retres1~1#1 := 0; {10628#false} is VALID [2022-02-21 04:24:03,077 INFO L290 TraceCheckUtils]: 19: Hoare triple {10628#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10628#false} is VALID [2022-02-21 04:24:03,077 INFO L290 TraceCheckUtils]: 20: Hoare triple {10628#false} activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {10628#false} is VALID [2022-02-21 04:24:03,077 INFO L290 TraceCheckUtils]: 21: Hoare triple {10628#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10628#false} is VALID [2022-02-21 04:24:03,077 INFO L290 TraceCheckUtils]: 22: Hoare triple {10628#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10628#false} is VALID [2022-02-21 04:24:03,077 INFO L290 TraceCheckUtils]: 23: Hoare triple {10628#false} assume !(1 == ~M_E~0); {10628#false} is VALID [2022-02-21 04:24:03,077 INFO L290 TraceCheckUtils]: 24: Hoare triple {10628#false} assume !(1 == ~T1_E~0); {10628#false} is VALID [2022-02-21 04:24:03,077 INFO L290 TraceCheckUtils]: 25: Hoare triple {10628#false} assume !(1 == ~E_1~0); {10628#false} is VALID [2022-02-21 04:24:03,078 INFO L290 TraceCheckUtils]: 26: Hoare triple {10628#false} assume { :end_inline_reset_delta_events } true; {10628#false} is VALID [2022-02-21 04:24:03,078 INFO L290 TraceCheckUtils]: 27: Hoare triple {10628#false} assume !false; {10628#false} is VALID [2022-02-21 04:24:03,078 INFO L290 TraceCheckUtils]: 28: Hoare triple {10628#false} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10628#false} is VALID [2022-02-21 04:24:03,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:03,078 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:03,079 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [154553209] [2022-02-21 04:24:03,079 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [154553209] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:03,079 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:03,079 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:03,079 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674672712] [2022-02-21 04:24:03,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:03,080 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:03,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:03,080 INFO L85 PathProgramCache]: Analyzing trace with hash 722519635, now seen corresponding path program 1 times [2022-02-21 04:24:03,080 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:03,080 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995040254] [2022-02-21 04:24:03,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:03,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:03,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:03,085 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:03,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:03,088 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:03,150 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:03,150 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:03,151 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:03,151 INFO L87 Difference]: Start difference. First operand 690 states and 920 transitions. cyclomatic complexity: 234 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:03,291 INFO L93 Difference]: Finished difference Result 577 states and 772 transitions. [2022-02-21 04:24:03,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:03,292 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,312 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 29 edges. 29 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:03,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 577 states and 772 transitions. [2022-02-21 04:24:03,329 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 543 [2022-02-21 04:24:03,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 577 states to 577 states and 772 transitions. [2022-02-21 04:24:03,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 577 [2022-02-21 04:24:03,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 577 [2022-02-21 04:24:03,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 577 states and 772 transitions. [2022-02-21 04:24:03,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:03,346 INFO L681 BuchiCegarLoop]: Abstraction has 577 states and 772 transitions. [2022-02-21 04:24:03,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 577 states and 772 transitions. [2022-02-21 04:24:03,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 577 to 577. [2022-02-21 04:24:03,353 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:03,354 INFO L82 GeneralOperation]: Start isEquivalent. First operand 577 states and 772 transitions. Second operand has 577 states, 577 states have (on average 1.3379549393414212) internal successors, (772), 576 states have internal predecessors, (772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,355 INFO L74 IsIncluded]: Start isIncluded. First operand 577 states and 772 transitions. Second operand has 577 states, 577 states have (on average 1.3379549393414212) internal successors, (772), 576 states have internal predecessors, (772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,356 INFO L87 Difference]: Start difference. First operand 577 states and 772 transitions. Second operand has 577 states, 577 states have (on average 1.3379549393414212) internal successors, (772), 576 states have internal predecessors, (772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:03,371 INFO L93 Difference]: Finished difference Result 577 states and 772 transitions. [2022-02-21 04:24:03,371 INFO L276 IsEmpty]: Start isEmpty. Operand 577 states and 772 transitions. [2022-02-21 04:24:03,372 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:03,372 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:03,373 INFO L74 IsIncluded]: Start isIncluded. First operand has 577 states, 577 states have (on average 1.3379549393414212) internal successors, (772), 576 states have internal predecessors, (772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 577 states and 772 transitions. [2022-02-21 04:24:03,374 INFO L87 Difference]: Start difference. First operand has 577 states, 577 states have (on average 1.3379549393414212) internal successors, (772), 576 states have internal predecessors, (772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 577 states and 772 transitions. [2022-02-21 04:24:03,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:03,390 INFO L93 Difference]: Finished difference Result 577 states and 772 transitions. [2022-02-21 04:24:03,390 INFO L276 IsEmpty]: Start isEmpty. Operand 577 states and 772 transitions. [2022-02-21 04:24:03,391 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:03,391 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:03,391 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:03,391 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:03,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 577 states, 577 states have (on average 1.3379549393414212) internal successors, (772), 576 states have internal predecessors, (772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 577 states to 577 states and 772 transitions. [2022-02-21 04:24:03,407 INFO L704 BuchiCegarLoop]: Abstraction has 577 states and 772 transitions. [2022-02-21 04:24:03,407 INFO L587 BuchiCegarLoop]: Abstraction has 577 states and 772 transitions. [2022-02-21 04:24:03,407 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:03,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 577 states and 772 transitions. [2022-02-21 04:24:03,409 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 543 [2022-02-21 04:24:03,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:03,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:03,410 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:03,410 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:03,410 INFO L791 eck$LassoCheckResult]: Stem: 11351#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 11276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 11229#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11230#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11223#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 11213#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11214#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11318#L250 assume !(0 == ~M_E~0); 11328#L250-2 assume !(0 == ~T1_E~0); 11263#L255-1 assume !(0 == ~E_1~0); 11264#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11285#L115 assume !(1 == ~m_pc~0); 11286#L115-2 is_master_triggered_~__retres1~0#1 := 0; 11290#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11302#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11298#L300 assume !(0 != activate_threads_~tmp~1#1); 11299#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11343#L134 assume !(1 == ~t1_pc~0); 11295#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11287#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11288#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11221#L308 assume !(0 != activate_threads_~tmp___0~0#1); 11222#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11291#L273 assume !(1 == ~M_E~0); 11292#L273-2 assume !(1 == ~T1_E~0); 11337#L278-1 assume !(1 == ~E_1~0); 11305#L283-1 assume { :end_inline_reset_delta_events } true; 11306#L404-2 assume !false; 11650#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11648#L225 [2022-02-21 04:24:03,411 INFO L793 eck$LassoCheckResult]: Loop: 11648#L225 assume !false; 11644#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11642#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11643#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11334#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11261#L206 assume 0 != eval_~tmp~0#1; 11262#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 11357#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 11358#L211 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 11649#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 11648#L225 [2022-02-21 04:24:03,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:03,411 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 2 times [2022-02-21 04:24:03,411 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:03,412 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2048850163] [2022-02-21 04:24:03,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:03,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:03,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:03,418 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:03,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:03,434 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:03,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:03,440 INFO L85 PathProgramCache]: Analyzing trace with hash 722519635, now seen corresponding path program 2 times [2022-02-21 04:24:03,440 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:03,440 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082275161] [2022-02-21 04:24:03,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:03,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:03,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:03,446 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:03,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:03,451 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:03,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:03,454 INFO L85 PathProgramCache]: Analyzing trace with hash -1929671076, now seen corresponding path program 1 times [2022-02-21 04:24:03,454 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:03,454 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351096639] [2022-02-21 04:24:03,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:03,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:03,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:03,462 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:03,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:03,476 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:03,995 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.02 04:24:03 BoogieIcfgContainer [2022-02-21 04:24:03,995 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-02-21 04:24:03,996 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-02-21 04:24:03,996 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-02-21 04:24:03,996 INFO L275 PluginConnector]: Witness Printer initialized [2022-02-21 04:24:03,996 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:59" (3/4) ... [2022-02-21 04:24:04,000 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-02-21 04:24:04,041 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-02-21 04:24:04,041 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-02-21 04:24:04,042 INFO L158 Benchmark]: Toolchain (without parser) took 5880.01ms. Allocated memory was 86.0MB in the beginning and 130.0MB in the end (delta: 44.0MB). Free memory was 45.6MB in the beginning and 77.7MB in the end (delta: -32.1MB). Peak memory consumption was 14.8MB. Max. memory is 16.1GB. [2022-02-21 04:24:04,042 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 86.0MB. Free memory is still 62.0MB. There was no memory consumed. Max. memory is 16.1GB. [2022-02-21 04:24:04,043 INFO L158 Benchmark]: CACSL2BoogieTranslator took 252.15ms. Allocated memory is still 86.0MB. Free memory was 45.4MB in the beginning and 58.6MB in the end (delta: -13.3MB). Peak memory consumption was 9.2MB. Max. memory is 16.1GB. [2022-02-21 04:24:04,043 INFO L158 Benchmark]: Boogie Procedure Inliner took 49.68ms. Allocated memory is still 86.0MB. Free memory was 58.6MB in the beginning and 55.8MB in the end (delta: 2.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:24:04,043 INFO L158 Benchmark]: Boogie Preprocessor took 37.85ms. Allocated memory is still 86.0MB. Free memory was 55.8MB in the beginning and 54.2MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:24:04,044 INFO L158 Benchmark]: RCFGBuilder took 522.59ms. Allocated memory was 86.0MB in the beginning and 104.9MB in the end (delta: 18.9MB). Free memory was 53.7MB in the beginning and 68.2MB in the end (delta: -14.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-02-21 04:24:04,044 INFO L158 Benchmark]: BuchiAutomizer took 4966.91ms. Allocated memory was 104.9MB in the beginning and 130.0MB in the end (delta: 25.2MB). Free memory was 68.2MB in the beginning and 79.8MB in the end (delta: -11.6MB). Peak memory consumption was 62.8MB. Max. memory is 16.1GB. [2022-02-21 04:24:04,044 INFO L158 Benchmark]: Witness Printer took 45.62ms. Allocated memory is still 130.0MB. Free memory was 79.8MB in the beginning and 77.7MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:24:04,046 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - AssertionsEnabledResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 86.0MB. Free memory is still 62.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 252.15ms. Allocated memory is still 86.0MB. Free memory was 45.4MB in the beginning and 58.6MB in the end (delta: -13.3MB). Peak memory consumption was 9.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 49.68ms. Allocated memory is still 86.0MB. Free memory was 58.6MB in the beginning and 55.8MB in the end (delta: 2.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 37.85ms. Allocated memory is still 86.0MB. Free memory was 55.8MB in the beginning and 54.2MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 522.59ms. Allocated memory was 86.0MB in the beginning and 104.9MB in the end (delta: 18.9MB). Free memory was 53.7MB in the beginning and 68.2MB in the end (delta: -14.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 4966.91ms. Allocated memory was 104.9MB in the beginning and 130.0MB in the end (delta: 25.2MB). Free memory was 68.2MB in the beginning and 79.8MB in the end (delta: -11.6MB). Peak memory consumption was 62.8MB. Max. memory is 16.1GB. * Witness Printer took 45.62ms. Allocated memory is still 130.0MB. Free memory was 79.8MB in the beginning and 77.7MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 7 terminating modules (7 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.7 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 577 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.9s and 8 iterations. TraceHistogramMax:1. Analysis of lassos took 1.5s. Construction of modules took 0.1s. Büchi inclusion checks took 2.3s. Highest rank in rank-based complementation 0. Minimization of det autom 7. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 7 MinimizatonAttempts, 613 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had 690 states and ocurred in iteration 6. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1700 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1700 mSDsluCounter, 3003 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1724 mSDsCounter, 62 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 173 IncrementalHoareTripleChecker+Invalid, 235 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 62 mSolverCounterUnsat, 1279 mSDtfsCounter, 173 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN1 SILU0 SILI2 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 201]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@637bc276=0, NULL=1, \result=0, tmp=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3406b662=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@737c4718=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@17a53c54=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@329c7a0a=0, t1_pc=0, tmp_ndt_2=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@ff01ced=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@235b6741=0, E_1=2, __retres1=0, M_E=2, tmp_ndt_1=0, __retres1=1, tmp=1, \result=0, m_i=1, t1_st=0, __retres1=0, m_st=0, NULL=0, kernel_st=1, tmp___0=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 201]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) [L255] COND FALSE !(T1_E == 0) [L260] COND FALSE !(E_1 == 0) [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; [L115] COND FALSE !(m_pc == 1) [L125] __retres1 = 0 [L127] return (__retres1); [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; [L134] COND FALSE !(t1_pc == 1) [L144] __retres1 = 0 [L146] return (__retres1); [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) [L278] COND FALSE !(T1_E == 1) [L283] COND FALSE !(E_1 == 1) [L401] RET reset_delta_events() [L404] COND TRUE 1 [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-02-21 04:24:04,088 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)