./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:23:59,230 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:23:59,232 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:23:59,273 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:23:59,274 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:23:59,285 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:23:59,286 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:23:59,289 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:23:59,291 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:23:59,295 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:23:59,296 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:23:59,298 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:23:59,298 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:23:59,300 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:23:59,302 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:23:59,305 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:23:59,306 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:23:59,306 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:23:59,308 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:23:59,314 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:23:59,315 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:23:59,320 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:23:59,321 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:23:59,322 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:23:59,328 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:23:59,328 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:23:59,329 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:23:59,330 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:23:59,331 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:23:59,332 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:23:59,332 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:23:59,333 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:23:59,334 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:23:59,335 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:23:59,336 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:23:59,336 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:23:59,337 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:23:59,337 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:23:59,337 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:23:59,338 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:23:59,339 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:23:59,339 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:23:59,369 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:23:59,370 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:23:59,370 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:23:59,371 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:23:59,372 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:23:59,372 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:23:59,372 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:23:59,372 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:23:59,373 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:23:59,373 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:23:59,374 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:23:59,374 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:23:59,374 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:23:59,374 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:23:59,374 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:23:59,375 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:23:59,375 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:23:59,375 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:23:59,375 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:23:59,375 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:23:59,376 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:23:59,376 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:23:59,376 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:23:59,376 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:23:59,376 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:23:59,377 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:23:59,377 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:23:59,377 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:23:59,377 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:23:59,377 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:23:59,378 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:23:59,379 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:23:59,379 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2022-02-21 04:23:59,611 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:23:59,635 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:23:59,637 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:23:59,638 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:23:59,639 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:23:59,640 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.02.cil.c [2022-02-21 04:23:59,700 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3b0e46e31/59bd764b418845dcaee87e133d87a8d3/FLAG24a6a5e68 [2022-02-21 04:24:00,081 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:00,082 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c [2022-02-21 04:24:00,088 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3b0e46e31/59bd764b418845dcaee87e133d87a8d3/FLAG24a6a5e68 [2022-02-21 04:24:00,486 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3b0e46e31/59bd764b418845dcaee87e133d87a8d3 [2022-02-21 04:24:00,488 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:00,490 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:00,490 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:00,491 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:00,493 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:00,494 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,495 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7c2d3e5d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00, skipping insertion in model container [2022-02-21 04:24:00,495 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,506 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:00,543 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:00,628 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c[706,719] [2022-02-21 04:24:00,672 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:00,681 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:00,690 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c[706,719] [2022-02-21 04:24:00,717 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:00,730 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:00,730 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00 WrapperNode [2022-02-21 04:24:00,730 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:00,731 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:00,731 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:00,732 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:00,737 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,743 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,780 INFO L137 Inliner]: procedures = 32, calls = 36, calls flagged for inlining = 31, calls inlined = 44, statements flattened = 530 [2022-02-21 04:24:00,780 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:00,781 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:00,781 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:00,781 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:00,788 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,788 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,791 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,792 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,800 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,816 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,818 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,822 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:00,823 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:00,823 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:00,823 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:00,824 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (1/1) ... [2022-02-21 04:24:00,836 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:00,849 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:00,867 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:00,879 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:00,924 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:00,925 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:00,925 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:00,925 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:00,979 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:00,981 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:01,507 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:01,519 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:01,519 INFO L299 CfgBuilder]: Removed 6 assume(true) statements. [2022-02-21 04:24:01,521 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:01 BoogieIcfgContainer [2022-02-21 04:24:01,522 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:01,523 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:01,523 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:01,526 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:01,526 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:01,527 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:00" (1/3) ... [2022-02-21 04:24:01,528 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@12801b29 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:01, skipping insertion in model container [2022-02-21 04:24:01,528 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:01,528 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:00" (2/3) ... [2022-02-21 04:24:01,528 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@12801b29 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:01, skipping insertion in model container [2022-02-21 04:24:01,529 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:01,529 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:01" (3/3) ... [2022-02-21 04:24:01,530 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2022-02-21 04:24:01,567 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:01,568 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:01,568 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:01,568 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:01,568 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:01,568 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:01,568 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:01,568 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:01,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,642 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2022-02-21 04:24:01,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:01,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:01,649 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:01,649 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:01,649 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:01,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:01,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2022-02-21 04:24:01,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:01,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:01,690 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:01,691 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:01,697 INFO L791 eck$LassoCheckResult]: Stem: 197#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 144#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4#L491true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200#L214true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 176#L221true assume !(1 == ~m_i~0);~m_st~0 := 2; 55#L221-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 38#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 149#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31#L334true assume !(0 == ~M_E~0); 156#L334-2true assume !(0 == ~T1_E~0); 99#L339-1true assume !(0 == ~T2_E~0); 94#L344-1true assume 0 == ~E_1~0;~E_1~0 := 1; 131#L349-1true assume !(0 == ~E_2~0); 37#L354-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105#L156true assume !(1 == ~m_pc~0); 142#L156-2true is_master_triggered_~__retres1~0#1 := 0; 125#L167true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115#L168true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 71#L405true assume !(0 != activate_threads_~tmp~1#1); 58#L405-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113#L175true assume 1 == ~t1_pc~0; 148#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59#L186true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101#L187true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 102#L413true assume !(0 != activate_threads_~tmp___0~0#1); 179#L413-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 182#L194true assume !(1 == ~t2_pc~0); 201#L194-2true is_transmit2_triggered_~__retres1~2#1 := 0; 65#L205true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32#L206true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25#L421true assume !(0 != activate_threads_~tmp___1~0#1); 76#L421-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12#L367true assume !(1 == ~M_E~0); 181#L367-2true assume !(1 == ~T1_E~0); 119#L372-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 122#L377-1true assume !(1 == ~E_1~0); 22#L382-1true assume !(1 == ~E_2~0); 73#L387-1true assume { :end_inline_reset_delta_events } true; 93#L528-2true [2022-02-21 04:24:01,706 INFO L793 eck$LassoCheckResult]: Loop: 93#L528-2true assume !false; 77#L529true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 175#L309true assume false; 13#L324true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72#L214-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 204#L334-3true assume 0 == ~M_E~0;~M_E~0 := 1; 145#L334-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 103#L339-3true assume !(0 == ~T2_E~0); 177#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 69#L349-3true assume 0 == ~E_2~0;~E_2~0 := 1; 30#L354-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88#L156-9true assume !(1 == ~m_pc~0); 6#L156-11true is_master_triggered_~__retres1~0#1 := 0; 53#L167-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 167#L168-3true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 106#L405-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19#L405-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189#L175-9true assume !(1 == ~t1_pc~0); 129#L175-11true is_transmit1_triggered_~__retres1~1#1 := 0; 14#L186-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100#L187-3true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 141#L413-9true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 135#L413-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186#L194-9true assume !(1 == ~t2_pc~0); 26#L194-11true is_transmit2_triggered_~__retres1~2#1 := 0; 193#L205-3true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75#L206-3true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 97#L421-9true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 132#L421-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51#L367-3true assume 1 == ~M_E~0;~M_E~0 := 2; 8#L367-5true assume !(1 == ~T1_E~0); 33#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 17#L377-3true assume 1 == ~E_1~0;~E_1~0 := 2; 28#L382-3true assume 1 == ~E_2~0;~E_2~0 := 2; 98#L387-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 133#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 169#L261-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 23#L262-1true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 140#L547true assume !(0 == start_simulation_~tmp~3#1); 152#L547-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 137#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 49#L261-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 166#L262-2true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 36#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46#L509true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 174#L510true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 18#L560true assume !(0 != start_simulation_~tmp___0~1#1); 93#L528-2true [2022-02-21 04:24:01,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:01,713 INFO L85 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2022-02-21 04:24:01,720 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:01,721 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167767688] [2022-02-21 04:24:01,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:01,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:01,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:01,916 INFO L290 TraceCheckUtils]: 0: Hoare triple {209#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; {209#true} is VALID [2022-02-21 04:24:01,917 INFO L290 TraceCheckUtils]: 1: Hoare triple {209#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {211#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:01,918 INFO L290 TraceCheckUtils]: 2: Hoare triple {211#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {211#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:01,920 INFO L290 TraceCheckUtils]: 3: Hoare triple {211#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {211#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:01,922 INFO L290 TraceCheckUtils]: 4: Hoare triple {211#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {210#false} is VALID [2022-02-21 04:24:01,923 INFO L290 TraceCheckUtils]: 5: Hoare triple {210#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {210#false} is VALID [2022-02-21 04:24:01,923 INFO L290 TraceCheckUtils]: 6: Hoare triple {210#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {210#false} is VALID [2022-02-21 04:24:01,924 INFO L290 TraceCheckUtils]: 7: Hoare triple {210#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {210#false} is VALID [2022-02-21 04:24:01,924 INFO L290 TraceCheckUtils]: 8: Hoare triple {210#false} assume !(0 == ~M_E~0); {210#false} is VALID [2022-02-21 04:24:01,924 INFO L290 TraceCheckUtils]: 9: Hoare triple {210#false} assume !(0 == ~T1_E~0); {210#false} is VALID [2022-02-21 04:24:01,925 INFO L290 TraceCheckUtils]: 10: Hoare triple {210#false} assume !(0 == ~T2_E~0); {210#false} is VALID [2022-02-21 04:24:01,925 INFO L290 TraceCheckUtils]: 11: Hoare triple {210#false} assume 0 == ~E_1~0;~E_1~0 := 1; {210#false} is VALID [2022-02-21 04:24:01,925 INFO L290 TraceCheckUtils]: 12: Hoare triple {210#false} assume !(0 == ~E_2~0); {210#false} is VALID [2022-02-21 04:24:01,925 INFO L290 TraceCheckUtils]: 13: Hoare triple {210#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {210#false} is VALID [2022-02-21 04:24:01,926 INFO L290 TraceCheckUtils]: 14: Hoare triple {210#false} assume !(1 == ~m_pc~0); {210#false} is VALID [2022-02-21 04:24:01,926 INFO L290 TraceCheckUtils]: 15: Hoare triple {210#false} is_master_triggered_~__retres1~0#1 := 0; {210#false} is VALID [2022-02-21 04:24:01,926 INFO L290 TraceCheckUtils]: 16: Hoare triple {210#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {210#false} is VALID [2022-02-21 04:24:01,926 INFO L290 TraceCheckUtils]: 17: Hoare triple {210#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {210#false} is VALID [2022-02-21 04:24:01,927 INFO L290 TraceCheckUtils]: 18: Hoare triple {210#false} assume !(0 != activate_threads_~tmp~1#1); {210#false} is VALID [2022-02-21 04:24:01,927 INFO L290 TraceCheckUtils]: 19: Hoare triple {210#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {210#false} is VALID [2022-02-21 04:24:01,927 INFO L290 TraceCheckUtils]: 20: Hoare triple {210#false} assume 1 == ~t1_pc~0; {210#false} is VALID [2022-02-21 04:24:01,927 INFO L290 TraceCheckUtils]: 21: Hoare triple {210#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {210#false} is VALID [2022-02-21 04:24:01,928 INFO L290 TraceCheckUtils]: 22: Hoare triple {210#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {210#false} is VALID [2022-02-21 04:24:01,928 INFO L290 TraceCheckUtils]: 23: Hoare triple {210#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {210#false} is VALID [2022-02-21 04:24:01,928 INFO L290 TraceCheckUtils]: 24: Hoare triple {210#false} assume !(0 != activate_threads_~tmp___0~0#1); {210#false} is VALID [2022-02-21 04:24:01,928 INFO L290 TraceCheckUtils]: 25: Hoare triple {210#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {210#false} is VALID [2022-02-21 04:24:01,929 INFO L290 TraceCheckUtils]: 26: Hoare triple {210#false} assume !(1 == ~t2_pc~0); {210#false} is VALID [2022-02-21 04:24:01,930 INFO L290 TraceCheckUtils]: 27: Hoare triple {210#false} is_transmit2_triggered_~__retres1~2#1 := 0; {210#false} is VALID [2022-02-21 04:24:01,931 INFO L290 TraceCheckUtils]: 28: Hoare triple {210#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {210#false} is VALID [2022-02-21 04:24:01,931 INFO L290 TraceCheckUtils]: 29: Hoare triple {210#false} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {210#false} is VALID [2022-02-21 04:24:01,931 INFO L290 TraceCheckUtils]: 30: Hoare triple {210#false} assume !(0 != activate_threads_~tmp___1~0#1); {210#false} is VALID [2022-02-21 04:24:01,932 INFO L290 TraceCheckUtils]: 31: Hoare triple {210#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {210#false} is VALID [2022-02-21 04:24:01,932 INFO L290 TraceCheckUtils]: 32: Hoare triple {210#false} assume !(1 == ~M_E~0); {210#false} is VALID [2022-02-21 04:24:01,932 INFO L290 TraceCheckUtils]: 33: Hoare triple {210#false} assume !(1 == ~T1_E~0); {210#false} is VALID [2022-02-21 04:24:01,933 INFO L290 TraceCheckUtils]: 34: Hoare triple {210#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {210#false} is VALID [2022-02-21 04:24:01,933 INFO L290 TraceCheckUtils]: 35: Hoare triple {210#false} assume !(1 == ~E_1~0); {210#false} is VALID [2022-02-21 04:24:01,933 INFO L290 TraceCheckUtils]: 36: Hoare triple {210#false} assume !(1 == ~E_2~0); {210#false} is VALID [2022-02-21 04:24:01,933 INFO L290 TraceCheckUtils]: 37: Hoare triple {210#false} assume { :end_inline_reset_delta_events } true; {210#false} is VALID [2022-02-21 04:24:01,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:01,935 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:01,936 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1167767688] [2022-02-21 04:24:01,937 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1167767688] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:01,937 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:01,937 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:01,940 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [287283683] [2022-02-21 04:24:01,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:01,944 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:01,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:01,947 INFO L85 PathProgramCache]: Analyzing trace with hash 707442261, now seen corresponding path program 1 times [2022-02-21 04:24:01,947 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:01,947 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163277383] [2022-02-21 04:24:01,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:01,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:01,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:02,000 INFO L290 TraceCheckUtils]: 0: Hoare triple {212#true} assume !false; {212#true} is VALID [2022-02-21 04:24:02,000 INFO L290 TraceCheckUtils]: 1: Hoare triple {212#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {212#true} is VALID [2022-02-21 04:24:02,001 INFO L290 TraceCheckUtils]: 2: Hoare triple {212#true} assume false; {213#false} is VALID [2022-02-21 04:24:02,001 INFO L290 TraceCheckUtils]: 3: Hoare triple {213#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {213#false} is VALID [2022-02-21 04:24:02,001 INFO L290 TraceCheckUtils]: 4: Hoare triple {213#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {213#false} is VALID [2022-02-21 04:24:02,002 INFO L290 TraceCheckUtils]: 5: Hoare triple {213#false} assume 0 == ~M_E~0;~M_E~0 := 1; {213#false} is VALID [2022-02-21 04:24:02,002 INFO L290 TraceCheckUtils]: 6: Hoare triple {213#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {213#false} is VALID [2022-02-21 04:24:02,002 INFO L290 TraceCheckUtils]: 7: Hoare triple {213#false} assume !(0 == ~T2_E~0); {213#false} is VALID [2022-02-21 04:24:02,002 INFO L290 TraceCheckUtils]: 8: Hoare triple {213#false} assume 0 == ~E_1~0;~E_1~0 := 1; {213#false} is VALID [2022-02-21 04:24:02,003 INFO L290 TraceCheckUtils]: 9: Hoare triple {213#false} assume 0 == ~E_2~0;~E_2~0 := 1; {213#false} is VALID [2022-02-21 04:24:02,003 INFO L290 TraceCheckUtils]: 10: Hoare triple {213#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {213#false} is VALID [2022-02-21 04:24:02,004 INFO L290 TraceCheckUtils]: 11: Hoare triple {213#false} assume !(1 == ~m_pc~0); {213#false} is VALID [2022-02-21 04:24:02,005 INFO L290 TraceCheckUtils]: 12: Hoare triple {213#false} is_master_triggered_~__retres1~0#1 := 0; {213#false} is VALID [2022-02-21 04:24:02,008 INFO L290 TraceCheckUtils]: 13: Hoare triple {213#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {213#false} is VALID [2022-02-21 04:24:02,008 INFO L290 TraceCheckUtils]: 14: Hoare triple {213#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {213#false} is VALID [2022-02-21 04:24:02,008 INFO L290 TraceCheckUtils]: 15: Hoare triple {213#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {213#false} is VALID [2022-02-21 04:24:02,009 INFO L290 TraceCheckUtils]: 16: Hoare triple {213#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {213#false} is VALID [2022-02-21 04:24:02,009 INFO L290 TraceCheckUtils]: 17: Hoare triple {213#false} assume !(1 == ~t1_pc~0); {213#false} is VALID [2022-02-21 04:24:02,009 INFO L290 TraceCheckUtils]: 18: Hoare triple {213#false} is_transmit1_triggered_~__retres1~1#1 := 0; {213#false} is VALID [2022-02-21 04:24:02,010 INFO L290 TraceCheckUtils]: 19: Hoare triple {213#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {213#false} is VALID [2022-02-21 04:24:02,010 INFO L290 TraceCheckUtils]: 20: Hoare triple {213#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {213#false} is VALID [2022-02-21 04:24:02,012 INFO L290 TraceCheckUtils]: 21: Hoare triple {213#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {213#false} is VALID [2022-02-21 04:24:02,012 INFO L290 TraceCheckUtils]: 22: Hoare triple {213#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {213#false} is VALID [2022-02-21 04:24:02,012 INFO L290 TraceCheckUtils]: 23: Hoare triple {213#false} assume !(1 == ~t2_pc~0); {213#false} is VALID [2022-02-21 04:24:02,012 INFO L290 TraceCheckUtils]: 24: Hoare triple {213#false} is_transmit2_triggered_~__retres1~2#1 := 0; {213#false} is VALID [2022-02-21 04:24:02,013 INFO L290 TraceCheckUtils]: 25: Hoare triple {213#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {213#false} is VALID [2022-02-21 04:24:02,013 INFO L290 TraceCheckUtils]: 26: Hoare triple {213#false} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {213#false} is VALID [2022-02-21 04:24:02,014 INFO L290 TraceCheckUtils]: 27: Hoare triple {213#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {213#false} is VALID [2022-02-21 04:24:02,014 INFO L290 TraceCheckUtils]: 28: Hoare triple {213#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {213#false} is VALID [2022-02-21 04:24:02,014 INFO L290 TraceCheckUtils]: 29: Hoare triple {213#false} assume 1 == ~M_E~0;~M_E~0 := 2; {213#false} is VALID [2022-02-21 04:24:02,014 INFO L290 TraceCheckUtils]: 30: Hoare triple {213#false} assume !(1 == ~T1_E~0); {213#false} is VALID [2022-02-21 04:24:02,014 INFO L290 TraceCheckUtils]: 31: Hoare triple {213#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {213#false} is VALID [2022-02-21 04:24:02,015 INFO L290 TraceCheckUtils]: 32: Hoare triple {213#false} assume 1 == ~E_1~0;~E_1~0 := 2; {213#false} is VALID [2022-02-21 04:24:02,019 INFO L290 TraceCheckUtils]: 33: Hoare triple {213#false} assume 1 == ~E_2~0;~E_2~0 := 2; {213#false} is VALID [2022-02-21 04:24:02,019 INFO L290 TraceCheckUtils]: 34: Hoare triple {213#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {213#false} is VALID [2022-02-21 04:24:02,019 INFO L290 TraceCheckUtils]: 35: Hoare triple {213#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {213#false} is VALID [2022-02-21 04:24:02,020 INFO L290 TraceCheckUtils]: 36: Hoare triple {213#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {213#false} is VALID [2022-02-21 04:24:02,020 INFO L290 TraceCheckUtils]: 37: Hoare triple {213#false} start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {213#false} is VALID [2022-02-21 04:24:02,020 INFO L290 TraceCheckUtils]: 38: Hoare triple {213#false} assume !(0 == start_simulation_~tmp~3#1); {213#false} is VALID [2022-02-21 04:24:02,020 INFO L290 TraceCheckUtils]: 39: Hoare triple {213#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {213#false} is VALID [2022-02-21 04:24:02,021 INFO L290 TraceCheckUtils]: 40: Hoare triple {213#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {213#false} is VALID [2022-02-21 04:24:02,021 INFO L290 TraceCheckUtils]: 41: Hoare triple {213#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {213#false} is VALID [2022-02-21 04:24:02,021 INFO L290 TraceCheckUtils]: 42: Hoare triple {213#false} stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; {213#false} is VALID [2022-02-21 04:24:02,021 INFO L290 TraceCheckUtils]: 43: Hoare triple {213#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {213#false} is VALID [2022-02-21 04:24:02,021 INFO L290 TraceCheckUtils]: 44: Hoare triple {213#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {213#false} is VALID [2022-02-21 04:24:02,022 INFO L290 TraceCheckUtils]: 45: Hoare triple {213#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {213#false} is VALID [2022-02-21 04:24:02,022 INFO L290 TraceCheckUtils]: 46: Hoare triple {213#false} assume !(0 != start_simulation_~tmp___0~1#1); {213#false} is VALID [2022-02-21 04:24:02,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:02,023 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:02,023 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163277383] [2022-02-21 04:24:02,024 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163277383] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:02,024 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:02,024 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:02,024 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090569326] [2022-02-21 04:24:02,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:02,026 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:02,028 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:02,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:02,056 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:02,058 INFO L87 Difference]: Start difference. First operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,338 INFO L93 Difference]: Finished difference Result 204 states and 299 transitions. [2022-02-21 04:24:02,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:02,340 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,379 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:02,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 299 transitions. [2022-02-21 04:24:02,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2022-02-21 04:24:02,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 198 states and 293 transitions. [2022-02-21 04:24:02,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 198 [2022-02-21 04:24:02,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2022-02-21 04:24:02,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 293 transitions. [2022-02-21 04:24:02,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:02,411 INFO L681 BuchiCegarLoop]: Abstraction has 198 states and 293 transitions. [2022-02-21 04:24:02,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 293 transitions. [2022-02-21 04:24:02,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2022-02-21 04:24:02,444 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:02,449 INFO L82 GeneralOperation]: Start isEquivalent. First operand 198 states and 293 transitions. Second operand has 198 states, 198 states have (on average 1.47979797979798) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,450 INFO L74 IsIncluded]: Start isIncluded. First operand 198 states and 293 transitions. Second operand has 198 states, 198 states have (on average 1.47979797979798) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,451 INFO L87 Difference]: Start difference. First operand 198 states and 293 transitions. Second operand has 198 states, 198 states have (on average 1.47979797979798) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,461 INFO L93 Difference]: Finished difference Result 198 states and 293 transitions. [2022-02-21 04:24:02,462 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 293 transitions. [2022-02-21 04:24:02,464 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:02,464 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:02,464 INFO L74 IsIncluded]: Start isIncluded. First operand has 198 states, 198 states have (on average 1.47979797979798) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 198 states and 293 transitions. [2022-02-21 04:24:02,465 INFO L87 Difference]: Start difference. First operand has 198 states, 198 states have (on average 1.47979797979798) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 198 states and 293 transitions. [2022-02-21 04:24:02,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,472 INFO L93 Difference]: Finished difference Result 198 states and 293 transitions. [2022-02-21 04:24:02,472 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 293 transitions. [2022-02-21 04:24:02,473 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:02,473 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:02,473 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:02,473 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:02,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198 states, 198 states have (on average 1.47979797979798) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 293 transitions. [2022-02-21 04:24:02,481 INFO L704 BuchiCegarLoop]: Abstraction has 198 states and 293 transitions. [2022-02-21 04:24:02,482 INFO L587 BuchiCegarLoop]: Abstraction has 198 states and 293 transitions. [2022-02-21 04:24:02,482 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:02,482 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 293 transitions. [2022-02-21 04:24:02,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2022-02-21 04:24:02,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:02,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:02,485 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,485 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,485 INFO L791 eck$LassoCheckResult]: Stem: 615#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 421#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 422#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 609#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 514#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 488#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 489#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 476#L334 assume !(0 == ~M_E~0); 477#L334-2 assume !(0 == ~T1_E~0); 565#L339-1 assume !(0 == ~T2_E~0); 559#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 560#L349-1 assume !(0 == ~E_2~0); 486#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 487#L156 assume !(1 == ~m_pc~0); 429#L156-2 is_master_triggered_~__retres1~0#1 := 0; 428#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 581#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 534#L405 assume !(0 != activate_threads_~tmp~1#1); 518#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 519#L175 assume 1 == ~t1_pc~0; 578#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 520#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 521#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 567#L413 assume !(0 != activate_threads_~tmp___0~0#1); 568#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 611#L194 assume !(1 == ~t2_pc~0); 558#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 530#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 478#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 465#L421 assume !(0 != activate_threads_~tmp___1~0#1); 466#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 440#L367 assume !(1 == ~M_E~0); 441#L367-2 assume !(1 == ~T1_E~0); 585#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 586#L377-1 assume !(1 == ~E_1~0); 460#L382-1 assume !(1 == ~E_2~0); 461#L387-1 assume { :end_inline_reset_delta_events } true; 452#L528-2 [2022-02-21 04:24:02,485 INFO L793 eck$LassoCheckResult]: Loop: 452#L528-2 assume !false; 539#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 513#L309 assume !false; 492#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 432#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 433#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 577#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 418#L276 assume !(0 != eval_~tmp~0#1); 420#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 442#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 535#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 602#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 569#L339-3 assume !(0 == ~T2_E~0); 570#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 533#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 474#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475#L156-9 assume !(1 == ~m_pc~0); 425#L156-11 is_master_triggered_~__retres1~0#1 := 0; 426#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 511#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 572#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 453#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 454#L175-9 assume 1 == ~t1_pc~0; 496#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 443#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 444#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 566#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 596#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 597#L194-9 assume !(1 == ~t2_pc~0); 467#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 468#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 537#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 538#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 563#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 430#L367-5 assume !(1 == ~T1_E~0); 431#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 449#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 450#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 471#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 564#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 480#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 462#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 463#L547 assume !(0 == start_simulation_~tmp~3#1); 587#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 598#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 505#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 506#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 484#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 485#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 501#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 451#L560 assume !(0 != start_simulation_~tmp___0~1#1); 452#L528-2 [2022-02-21 04:24:02,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,486 INFO L85 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2022-02-21 04:24:02,487 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,487 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095626232] [2022-02-21 04:24:02,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:02,536 INFO L290 TraceCheckUtils]: 0: Hoare triple {1015#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; {1015#true} is VALID [2022-02-21 04:24:02,537 INFO L290 TraceCheckUtils]: 1: Hoare triple {1015#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {1017#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:02,537 INFO L290 TraceCheckUtils]: 2: Hoare triple {1017#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1017#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:02,538 INFO L290 TraceCheckUtils]: 3: Hoare triple {1017#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1017#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:02,538 INFO L290 TraceCheckUtils]: 4: Hoare triple {1017#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {1017#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:02,539 INFO L290 TraceCheckUtils]: 5: Hoare triple {1017#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1017#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:02,539 INFO L290 TraceCheckUtils]: 6: Hoare triple {1017#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1016#false} is VALID [2022-02-21 04:24:02,539 INFO L290 TraceCheckUtils]: 7: Hoare triple {1016#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1016#false} is VALID [2022-02-21 04:24:02,540 INFO L290 TraceCheckUtils]: 8: Hoare triple {1016#false} assume !(0 == ~M_E~0); {1016#false} is VALID [2022-02-21 04:24:02,540 INFO L290 TraceCheckUtils]: 9: Hoare triple {1016#false} assume !(0 == ~T1_E~0); {1016#false} is VALID [2022-02-21 04:24:02,540 INFO L290 TraceCheckUtils]: 10: Hoare triple {1016#false} assume !(0 == ~T2_E~0); {1016#false} is VALID [2022-02-21 04:24:02,540 INFO L290 TraceCheckUtils]: 11: Hoare triple {1016#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1016#false} is VALID [2022-02-21 04:24:02,540 INFO L290 TraceCheckUtils]: 12: Hoare triple {1016#false} assume !(0 == ~E_2~0); {1016#false} is VALID [2022-02-21 04:24:02,541 INFO L290 TraceCheckUtils]: 13: Hoare triple {1016#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1016#false} is VALID [2022-02-21 04:24:02,541 INFO L290 TraceCheckUtils]: 14: Hoare triple {1016#false} assume !(1 == ~m_pc~0); {1016#false} is VALID [2022-02-21 04:24:02,541 INFO L290 TraceCheckUtils]: 15: Hoare triple {1016#false} is_master_triggered_~__retres1~0#1 := 0; {1016#false} is VALID [2022-02-21 04:24:02,541 INFO L290 TraceCheckUtils]: 16: Hoare triple {1016#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1016#false} is VALID [2022-02-21 04:24:02,541 INFO L290 TraceCheckUtils]: 17: Hoare triple {1016#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {1016#false} is VALID [2022-02-21 04:24:02,542 INFO L290 TraceCheckUtils]: 18: Hoare triple {1016#false} assume !(0 != activate_threads_~tmp~1#1); {1016#false} is VALID [2022-02-21 04:24:02,542 INFO L290 TraceCheckUtils]: 19: Hoare triple {1016#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1016#false} is VALID [2022-02-21 04:24:02,542 INFO L290 TraceCheckUtils]: 20: Hoare triple {1016#false} assume 1 == ~t1_pc~0; {1016#false} is VALID [2022-02-21 04:24:02,544 INFO L290 TraceCheckUtils]: 21: Hoare triple {1016#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1016#false} is VALID [2022-02-21 04:24:02,544 INFO L290 TraceCheckUtils]: 22: Hoare triple {1016#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1016#false} is VALID [2022-02-21 04:24:02,545 INFO L290 TraceCheckUtils]: 23: Hoare triple {1016#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {1016#false} is VALID [2022-02-21 04:24:02,545 INFO L290 TraceCheckUtils]: 24: Hoare triple {1016#false} assume !(0 != activate_threads_~tmp___0~0#1); {1016#false} is VALID [2022-02-21 04:24:02,545 INFO L290 TraceCheckUtils]: 25: Hoare triple {1016#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1016#false} is VALID [2022-02-21 04:24:02,548 INFO L290 TraceCheckUtils]: 26: Hoare triple {1016#false} assume !(1 == ~t2_pc~0); {1016#false} is VALID [2022-02-21 04:24:02,548 INFO L290 TraceCheckUtils]: 27: Hoare triple {1016#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1016#false} is VALID [2022-02-21 04:24:02,548 INFO L290 TraceCheckUtils]: 28: Hoare triple {1016#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1016#false} is VALID [2022-02-21 04:24:02,548 INFO L290 TraceCheckUtils]: 29: Hoare triple {1016#false} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {1016#false} is VALID [2022-02-21 04:24:02,549 INFO L290 TraceCheckUtils]: 30: Hoare triple {1016#false} assume !(0 != activate_threads_~tmp___1~0#1); {1016#false} is VALID [2022-02-21 04:24:02,549 INFO L290 TraceCheckUtils]: 31: Hoare triple {1016#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1016#false} is VALID [2022-02-21 04:24:02,550 INFO L290 TraceCheckUtils]: 32: Hoare triple {1016#false} assume !(1 == ~M_E~0); {1016#false} is VALID [2022-02-21 04:24:02,550 INFO L290 TraceCheckUtils]: 33: Hoare triple {1016#false} assume !(1 == ~T1_E~0); {1016#false} is VALID [2022-02-21 04:24:02,551 INFO L290 TraceCheckUtils]: 34: Hoare triple {1016#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1016#false} is VALID [2022-02-21 04:24:02,557 INFO L290 TraceCheckUtils]: 35: Hoare triple {1016#false} assume !(1 == ~E_1~0); {1016#false} is VALID [2022-02-21 04:24:02,557 INFO L290 TraceCheckUtils]: 36: Hoare triple {1016#false} assume !(1 == ~E_2~0); {1016#false} is VALID [2022-02-21 04:24:02,558 INFO L290 TraceCheckUtils]: 37: Hoare triple {1016#false} assume { :end_inline_reset_delta_events } true; {1016#false} is VALID [2022-02-21 04:24:02,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:02,563 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:02,563 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095626232] [2022-02-21 04:24:02,564 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095626232] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:02,564 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:02,564 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:02,572 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010122314] [2022-02-21 04:24:02,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:02,572 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:02,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,573 INFO L85 PathProgramCache]: Analyzing trace with hash -1486806721, now seen corresponding path program 1 times [2022-02-21 04:24:02,573 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,574 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55735830] [2022-02-21 04:24:02,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:02,631 INFO L290 TraceCheckUtils]: 0: Hoare triple {1018#true} assume !false; {1018#true} is VALID [2022-02-21 04:24:02,631 INFO L290 TraceCheckUtils]: 1: Hoare triple {1018#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1018#true} is VALID [2022-02-21 04:24:02,631 INFO L290 TraceCheckUtils]: 2: Hoare triple {1018#true} assume !false; {1018#true} is VALID [2022-02-21 04:24:02,631 INFO L290 TraceCheckUtils]: 3: Hoare triple {1018#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {1018#true} is VALID [2022-02-21 04:24:02,632 INFO L290 TraceCheckUtils]: 4: Hoare triple {1018#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {1018#true} is VALID [2022-02-21 04:24:02,632 INFO L290 TraceCheckUtils]: 5: Hoare triple {1018#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {1018#true} is VALID [2022-02-21 04:24:02,632 INFO L290 TraceCheckUtils]: 6: Hoare triple {1018#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {1018#true} is VALID [2022-02-21 04:24:02,632 INFO L290 TraceCheckUtils]: 7: Hoare triple {1018#true} assume !(0 != eval_~tmp~0#1); {1018#true} is VALID [2022-02-21 04:24:02,632 INFO L290 TraceCheckUtils]: 8: Hoare triple {1018#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1018#true} is VALID [2022-02-21 04:24:02,632 INFO L290 TraceCheckUtils]: 9: Hoare triple {1018#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1018#true} is VALID [2022-02-21 04:24:02,633 INFO L290 TraceCheckUtils]: 10: Hoare triple {1018#true} assume 0 == ~M_E~0;~M_E~0 := 1; {1018#true} is VALID [2022-02-21 04:24:02,633 INFO L290 TraceCheckUtils]: 11: Hoare triple {1018#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,634 INFO L290 TraceCheckUtils]: 12: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume !(0 == ~T2_E~0); {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,634 INFO L290 TraceCheckUtils]: 13: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,634 INFO L290 TraceCheckUtils]: 14: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,635 INFO L290 TraceCheckUtils]: 15: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,635 INFO L290 TraceCheckUtils]: 16: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~m_pc~0); {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,636 INFO L290 TraceCheckUtils]: 17: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,636 INFO L290 TraceCheckUtils]: 18: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,636 INFO L290 TraceCheckUtils]: 19: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,637 INFO L290 TraceCheckUtils]: 20: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,637 INFO L290 TraceCheckUtils]: 21: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,638 INFO L290 TraceCheckUtils]: 22: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~t1_pc~0; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,638 INFO L290 TraceCheckUtils]: 23: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,639 INFO L290 TraceCheckUtils]: 24: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,639 INFO L290 TraceCheckUtils]: 25: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,640 INFO L290 TraceCheckUtils]: 26: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,640 INFO L290 TraceCheckUtils]: 27: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,640 INFO L290 TraceCheckUtils]: 28: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~t2_pc~0); {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,641 INFO L290 TraceCheckUtils]: 29: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,641 INFO L290 TraceCheckUtils]: 30: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,642 INFO L290 TraceCheckUtils]: 31: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,642 INFO L290 TraceCheckUtils]: 32: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,643 INFO L290 TraceCheckUtils]: 33: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,643 INFO L290 TraceCheckUtils]: 34: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {1020#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:02,643 INFO L290 TraceCheckUtils]: 35: Hoare triple {1020#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~T1_E~0); {1019#false} is VALID [2022-02-21 04:24:02,644 INFO L290 TraceCheckUtils]: 36: Hoare triple {1019#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1019#false} is VALID [2022-02-21 04:24:02,644 INFO L290 TraceCheckUtils]: 37: Hoare triple {1019#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1019#false} is VALID [2022-02-21 04:24:02,644 INFO L290 TraceCheckUtils]: 38: Hoare triple {1019#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1019#false} is VALID [2022-02-21 04:24:02,644 INFO L290 TraceCheckUtils]: 39: Hoare triple {1019#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {1019#false} is VALID [2022-02-21 04:24:02,644 INFO L290 TraceCheckUtils]: 40: Hoare triple {1019#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {1019#false} is VALID [2022-02-21 04:24:02,644 INFO L290 TraceCheckUtils]: 41: Hoare triple {1019#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {1019#false} is VALID [2022-02-21 04:24:02,645 INFO L290 TraceCheckUtils]: 42: Hoare triple {1019#false} start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {1019#false} is VALID [2022-02-21 04:24:02,645 INFO L290 TraceCheckUtils]: 43: Hoare triple {1019#false} assume !(0 == start_simulation_~tmp~3#1); {1019#false} is VALID [2022-02-21 04:24:02,645 INFO L290 TraceCheckUtils]: 44: Hoare triple {1019#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {1019#false} is VALID [2022-02-21 04:24:02,645 INFO L290 TraceCheckUtils]: 45: Hoare triple {1019#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {1019#false} is VALID [2022-02-21 04:24:02,645 INFO L290 TraceCheckUtils]: 46: Hoare triple {1019#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {1019#false} is VALID [2022-02-21 04:24:02,646 INFO L290 TraceCheckUtils]: 47: Hoare triple {1019#false} stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; {1019#false} is VALID [2022-02-21 04:24:02,646 INFO L290 TraceCheckUtils]: 48: Hoare triple {1019#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1019#false} is VALID [2022-02-21 04:24:02,646 INFO L290 TraceCheckUtils]: 49: Hoare triple {1019#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1019#false} is VALID [2022-02-21 04:24:02,646 INFO L290 TraceCheckUtils]: 50: Hoare triple {1019#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {1019#false} is VALID [2022-02-21 04:24:02,646 INFO L290 TraceCheckUtils]: 51: Hoare triple {1019#false} assume !(0 != start_simulation_~tmp___0~1#1); {1019#false} is VALID [2022-02-21 04:24:02,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:02,647 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:02,647 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55735830] [2022-02-21 04:24:02,647 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55735830] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:02,648 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:02,648 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:02,648 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607673283] [2022-02-21 04:24:02,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:02,648 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:02,649 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:02,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:02,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:02,650 INFO L87 Difference]: Start difference. First operand 198 states and 293 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,860 INFO L93 Difference]: Finished difference Result 198 states and 292 transitions. [2022-02-21 04:24:02,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:02,861 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,908 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:02,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 198 states and 292 transitions. [2022-02-21 04:24:02,915 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2022-02-21 04:24:02,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 198 states to 198 states and 292 transitions. [2022-02-21 04:24:02,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 198 [2022-02-21 04:24:02,921 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2022-02-21 04:24:02,921 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 292 transitions. [2022-02-21 04:24:02,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:02,926 INFO L681 BuchiCegarLoop]: Abstraction has 198 states and 292 transitions. [2022-02-21 04:24:02,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 292 transitions. [2022-02-21 04:24:02,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2022-02-21 04:24:02,939 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:02,940 INFO L82 GeneralOperation]: Start isEquivalent. First operand 198 states and 292 transitions. Second operand has 198 states, 198 states have (on average 1.4747474747474747) internal successors, (292), 197 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,940 INFO L74 IsIncluded]: Start isIncluded. First operand 198 states and 292 transitions. Second operand has 198 states, 198 states have (on average 1.4747474747474747) internal successors, (292), 197 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,941 INFO L87 Difference]: Start difference. First operand 198 states and 292 transitions. Second operand has 198 states, 198 states have (on average 1.4747474747474747) internal successors, (292), 197 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,945 INFO L93 Difference]: Finished difference Result 198 states and 292 transitions. [2022-02-21 04:24:02,945 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 292 transitions. [2022-02-21 04:24:02,946 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:02,946 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:02,947 INFO L74 IsIncluded]: Start isIncluded. First operand has 198 states, 198 states have (on average 1.4747474747474747) internal successors, (292), 197 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 198 states and 292 transitions. [2022-02-21 04:24:02,947 INFO L87 Difference]: Start difference. First operand has 198 states, 198 states have (on average 1.4747474747474747) internal successors, (292), 197 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 198 states and 292 transitions. [2022-02-21 04:24:02,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:02,952 INFO L93 Difference]: Finished difference Result 198 states and 292 transitions. [2022-02-21 04:24:02,952 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 292 transitions. [2022-02-21 04:24:02,953 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:02,953 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:02,953 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:02,954 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:02,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198 states, 198 states have (on average 1.4747474747474747) internal successors, (292), 197 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:02,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 292 transitions. [2022-02-21 04:24:02,959 INFO L704 BuchiCegarLoop]: Abstraction has 198 states and 292 transitions. [2022-02-21 04:24:02,959 INFO L587 BuchiCegarLoop]: Abstraction has 198 states and 292 transitions. [2022-02-21 04:24:02,959 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:02,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 292 transitions. [2022-02-21 04:24:02,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2022-02-21 04:24:02,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:02,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:02,962 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,962 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:02,963 INFO L791 eck$LassoCheckResult]: Stem: 1416#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1222#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1223#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1410#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1315#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1289#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1290#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1277#L334 assume !(0 == ~M_E~0); 1278#L334-2 assume !(0 == ~T1_E~0); 1366#L339-1 assume !(0 == ~T2_E~0); 1360#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1361#L349-1 assume !(0 == ~E_2~0); 1287#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1288#L156 assume !(1 == ~m_pc~0); 1230#L156-2 is_master_triggered_~__retres1~0#1 := 0; 1229#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1382#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1335#L405 assume !(0 != activate_threads_~tmp~1#1); 1319#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1320#L175 assume 1 == ~t1_pc~0; 1379#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1321#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1322#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1368#L413 assume !(0 != activate_threads_~tmp___0~0#1); 1369#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1412#L194 assume !(1 == ~t2_pc~0); 1359#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1331#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1279#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1266#L421 assume !(0 != activate_threads_~tmp___1~0#1); 1267#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1241#L367 assume !(1 == ~M_E~0); 1242#L367-2 assume !(1 == ~T1_E~0); 1386#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1387#L377-1 assume !(1 == ~E_1~0); 1261#L382-1 assume !(1 == ~E_2~0); 1262#L387-1 assume { :end_inline_reset_delta_events } true; 1253#L528-2 [2022-02-21 04:24:02,963 INFO L793 eck$LassoCheckResult]: Loop: 1253#L528-2 assume !false; 1340#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1314#L309 assume !false; 1293#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1233#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1234#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1378#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1219#L276 assume !(0 != eval_~tmp~0#1); 1221#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1243#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1336#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1403#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1370#L339-3 assume !(0 == ~T2_E~0); 1371#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1334#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1275#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1276#L156-9 assume !(1 == ~m_pc~0); 1226#L156-11 is_master_triggered_~__retres1~0#1 := 0; 1227#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1312#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1373#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1254#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1255#L175-9 assume 1 == ~t1_pc~0; 1297#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1244#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1245#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1367#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1397#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1398#L194-9 assume !(1 == ~t2_pc~0); 1268#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 1269#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1338#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1339#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1364#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1309#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1231#L367-5 assume !(1 == ~T1_E~0); 1232#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1250#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1251#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1272#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1365#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1281#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1263#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1264#L547 assume !(0 == start_simulation_~tmp~3#1); 1388#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1399#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1306#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1307#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1285#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1286#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1302#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1252#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1253#L528-2 [2022-02-21 04:24:02,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:02,964 INFO L85 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2022-02-21 04:24:02,964 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:02,964 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556118288] [2022-02-21 04:24:02,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:02,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:02,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:03,009 INFO L290 TraceCheckUtils]: 0: Hoare triple {1816#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; {1818#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:03,010 INFO L290 TraceCheckUtils]: 1: Hoare triple {1818#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {1818#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:03,011 INFO L290 TraceCheckUtils]: 2: Hoare triple {1818#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1818#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:03,011 INFO L290 TraceCheckUtils]: 3: Hoare triple {1818#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1818#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:03,012 INFO L290 TraceCheckUtils]: 4: Hoare triple {1818#(= ~T2_E~0 ~E_1~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {1818#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:03,012 INFO L290 TraceCheckUtils]: 5: Hoare triple {1818#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1818#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:03,013 INFO L290 TraceCheckUtils]: 6: Hoare triple {1818#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {1818#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:03,013 INFO L290 TraceCheckUtils]: 7: Hoare triple {1818#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1818#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:03,014 INFO L290 TraceCheckUtils]: 8: Hoare triple {1818#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~M_E~0); {1818#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:03,014 INFO L290 TraceCheckUtils]: 9: Hoare triple {1818#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~T1_E~0); {1818#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:03,015 INFO L290 TraceCheckUtils]: 10: Hoare triple {1818#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~T2_E~0); {1819#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:03,015 INFO L290 TraceCheckUtils]: 11: Hoare triple {1819#(not (= ~E_1~0 0))} assume 0 == ~E_1~0;~E_1~0 := 1; {1817#false} is VALID [2022-02-21 04:24:03,016 INFO L290 TraceCheckUtils]: 12: Hoare triple {1817#false} assume !(0 == ~E_2~0); {1817#false} is VALID [2022-02-21 04:24:03,016 INFO L290 TraceCheckUtils]: 13: Hoare triple {1817#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1817#false} is VALID [2022-02-21 04:24:03,017 INFO L290 TraceCheckUtils]: 14: Hoare triple {1817#false} assume !(1 == ~m_pc~0); {1817#false} is VALID [2022-02-21 04:24:03,017 INFO L290 TraceCheckUtils]: 15: Hoare triple {1817#false} is_master_triggered_~__retres1~0#1 := 0; {1817#false} is VALID [2022-02-21 04:24:03,017 INFO L290 TraceCheckUtils]: 16: Hoare triple {1817#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1817#false} is VALID [2022-02-21 04:24:03,018 INFO L290 TraceCheckUtils]: 17: Hoare triple {1817#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {1817#false} is VALID [2022-02-21 04:24:03,018 INFO L290 TraceCheckUtils]: 18: Hoare triple {1817#false} assume !(0 != activate_threads_~tmp~1#1); {1817#false} is VALID [2022-02-21 04:24:03,018 INFO L290 TraceCheckUtils]: 19: Hoare triple {1817#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1817#false} is VALID [2022-02-21 04:24:03,028 INFO L290 TraceCheckUtils]: 20: Hoare triple {1817#false} assume 1 == ~t1_pc~0; {1817#false} is VALID [2022-02-21 04:24:03,028 INFO L290 TraceCheckUtils]: 21: Hoare triple {1817#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1817#false} is VALID [2022-02-21 04:24:03,029 INFO L290 TraceCheckUtils]: 22: Hoare triple {1817#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1817#false} is VALID [2022-02-21 04:24:03,029 INFO L290 TraceCheckUtils]: 23: Hoare triple {1817#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {1817#false} is VALID [2022-02-21 04:24:03,029 INFO L290 TraceCheckUtils]: 24: Hoare triple {1817#false} assume !(0 != activate_threads_~tmp___0~0#1); {1817#false} is VALID [2022-02-21 04:24:03,029 INFO L290 TraceCheckUtils]: 25: Hoare triple {1817#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1817#false} is VALID [2022-02-21 04:24:03,029 INFO L290 TraceCheckUtils]: 26: Hoare triple {1817#false} assume !(1 == ~t2_pc~0); {1817#false} is VALID [2022-02-21 04:24:03,029 INFO L290 TraceCheckUtils]: 27: Hoare triple {1817#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1817#false} is VALID [2022-02-21 04:24:03,029 INFO L290 TraceCheckUtils]: 28: Hoare triple {1817#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1817#false} is VALID [2022-02-21 04:24:03,029 INFO L290 TraceCheckUtils]: 29: Hoare triple {1817#false} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {1817#false} is VALID [2022-02-21 04:24:03,029 INFO L290 TraceCheckUtils]: 30: Hoare triple {1817#false} assume !(0 != activate_threads_~tmp___1~0#1); {1817#false} is VALID [2022-02-21 04:24:03,029 INFO L290 TraceCheckUtils]: 31: Hoare triple {1817#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1817#false} is VALID [2022-02-21 04:24:03,030 INFO L290 TraceCheckUtils]: 32: Hoare triple {1817#false} assume !(1 == ~M_E~0); {1817#false} is VALID [2022-02-21 04:24:03,030 INFO L290 TraceCheckUtils]: 33: Hoare triple {1817#false} assume !(1 == ~T1_E~0); {1817#false} is VALID [2022-02-21 04:24:03,030 INFO L290 TraceCheckUtils]: 34: Hoare triple {1817#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1817#false} is VALID [2022-02-21 04:24:03,030 INFO L290 TraceCheckUtils]: 35: Hoare triple {1817#false} assume !(1 == ~E_1~0); {1817#false} is VALID [2022-02-21 04:24:03,030 INFO L290 TraceCheckUtils]: 36: Hoare triple {1817#false} assume !(1 == ~E_2~0); {1817#false} is VALID [2022-02-21 04:24:03,030 INFO L290 TraceCheckUtils]: 37: Hoare triple {1817#false} assume { :end_inline_reset_delta_events } true; {1817#false} is VALID [2022-02-21 04:24:03,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:03,031 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:03,031 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556118288] [2022-02-21 04:24:03,031 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1556118288] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:03,031 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:03,031 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:03,032 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669306732] [2022-02-21 04:24:03,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:03,032 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:03,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:03,033 INFO L85 PathProgramCache]: Analyzing trace with hash -1486806721, now seen corresponding path program 2 times [2022-02-21 04:24:03,033 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:03,033 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217107671] [2022-02-21 04:24:03,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:03,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:03,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:03,100 INFO L290 TraceCheckUtils]: 0: Hoare triple {1820#true} assume !false; {1820#true} is VALID [2022-02-21 04:24:03,101 INFO L290 TraceCheckUtils]: 1: Hoare triple {1820#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1820#true} is VALID [2022-02-21 04:24:03,101 INFO L290 TraceCheckUtils]: 2: Hoare triple {1820#true} assume !false; {1820#true} is VALID [2022-02-21 04:24:03,101 INFO L290 TraceCheckUtils]: 3: Hoare triple {1820#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {1820#true} is VALID [2022-02-21 04:24:03,101 INFO L290 TraceCheckUtils]: 4: Hoare triple {1820#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {1820#true} is VALID [2022-02-21 04:24:03,101 INFO L290 TraceCheckUtils]: 5: Hoare triple {1820#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {1820#true} is VALID [2022-02-21 04:24:03,101 INFO L290 TraceCheckUtils]: 6: Hoare triple {1820#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {1820#true} is VALID [2022-02-21 04:24:03,101 INFO L290 TraceCheckUtils]: 7: Hoare triple {1820#true} assume !(0 != eval_~tmp~0#1); {1820#true} is VALID [2022-02-21 04:24:03,101 INFO L290 TraceCheckUtils]: 8: Hoare triple {1820#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1820#true} is VALID [2022-02-21 04:24:03,102 INFO L290 TraceCheckUtils]: 9: Hoare triple {1820#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1820#true} is VALID [2022-02-21 04:24:03,102 INFO L290 TraceCheckUtils]: 10: Hoare triple {1820#true} assume 0 == ~M_E~0;~M_E~0 := 1; {1820#true} is VALID [2022-02-21 04:24:03,103 INFO L290 TraceCheckUtils]: 11: Hoare triple {1820#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,103 INFO L290 TraceCheckUtils]: 12: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume !(0 == ~T2_E~0); {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,104 INFO L290 TraceCheckUtils]: 13: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,104 INFO L290 TraceCheckUtils]: 14: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,104 INFO L290 TraceCheckUtils]: 15: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,105 INFO L290 TraceCheckUtils]: 16: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~m_pc~0); {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,105 INFO L290 TraceCheckUtils]: 17: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,106 INFO L290 TraceCheckUtils]: 18: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,106 INFO L290 TraceCheckUtils]: 19: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,106 INFO L290 TraceCheckUtils]: 20: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,107 INFO L290 TraceCheckUtils]: 21: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,107 INFO L290 TraceCheckUtils]: 22: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~t1_pc~0; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,108 INFO L290 TraceCheckUtils]: 23: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,108 INFO L290 TraceCheckUtils]: 24: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,108 INFO L290 TraceCheckUtils]: 25: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,109 INFO L290 TraceCheckUtils]: 26: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,109 INFO L290 TraceCheckUtils]: 27: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,110 INFO L290 TraceCheckUtils]: 28: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~t2_pc~0); {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,110 INFO L290 TraceCheckUtils]: 29: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,110 INFO L290 TraceCheckUtils]: 30: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,111 INFO L290 TraceCheckUtils]: 31: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,111 INFO L290 TraceCheckUtils]: 32: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,114 INFO L290 TraceCheckUtils]: 33: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,115 INFO L290 TraceCheckUtils]: 34: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {1822#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,115 INFO L290 TraceCheckUtils]: 35: Hoare triple {1822#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~T1_E~0); {1821#false} is VALID [2022-02-21 04:24:03,115 INFO L290 TraceCheckUtils]: 36: Hoare triple {1821#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1821#false} is VALID [2022-02-21 04:24:03,116 INFO L290 TraceCheckUtils]: 37: Hoare triple {1821#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1821#false} is VALID [2022-02-21 04:24:03,116 INFO L290 TraceCheckUtils]: 38: Hoare triple {1821#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1821#false} is VALID [2022-02-21 04:24:03,116 INFO L290 TraceCheckUtils]: 39: Hoare triple {1821#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {1821#false} is VALID [2022-02-21 04:24:03,116 INFO L290 TraceCheckUtils]: 40: Hoare triple {1821#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {1821#false} is VALID [2022-02-21 04:24:03,116 INFO L290 TraceCheckUtils]: 41: Hoare triple {1821#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {1821#false} is VALID [2022-02-21 04:24:03,116 INFO L290 TraceCheckUtils]: 42: Hoare triple {1821#false} start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {1821#false} is VALID [2022-02-21 04:24:03,116 INFO L290 TraceCheckUtils]: 43: Hoare triple {1821#false} assume !(0 == start_simulation_~tmp~3#1); {1821#false} is VALID [2022-02-21 04:24:03,116 INFO L290 TraceCheckUtils]: 44: Hoare triple {1821#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {1821#false} is VALID [2022-02-21 04:24:03,117 INFO L290 TraceCheckUtils]: 45: Hoare triple {1821#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {1821#false} is VALID [2022-02-21 04:24:03,117 INFO L290 TraceCheckUtils]: 46: Hoare triple {1821#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {1821#false} is VALID [2022-02-21 04:24:03,118 INFO L290 TraceCheckUtils]: 47: Hoare triple {1821#false} stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; {1821#false} is VALID [2022-02-21 04:24:03,118 INFO L290 TraceCheckUtils]: 48: Hoare triple {1821#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1821#false} is VALID [2022-02-21 04:24:03,118 INFO L290 TraceCheckUtils]: 49: Hoare triple {1821#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1821#false} is VALID [2022-02-21 04:24:03,118 INFO L290 TraceCheckUtils]: 50: Hoare triple {1821#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {1821#false} is VALID [2022-02-21 04:24:03,118 INFO L290 TraceCheckUtils]: 51: Hoare triple {1821#false} assume !(0 != start_simulation_~tmp___0~1#1); {1821#false} is VALID [2022-02-21 04:24:03,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:03,120 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:03,120 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217107671] [2022-02-21 04:24:03,121 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217107671] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:03,121 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:03,121 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:03,121 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550896383] [2022-02-21 04:24:03,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:03,121 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:03,121 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:03,122 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:03,122 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:03,122 INFO L87 Difference]: Start difference. First operand 198 states and 292 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:03,613 INFO L93 Difference]: Finished difference Result 336 states and 492 transitions. [2022-02-21 04:24:03,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:03,614 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,643 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:03,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 336 states and 492 transitions. [2022-02-21 04:24:03,655 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 290 [2022-02-21 04:24:03,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 336 states to 336 states and 492 transitions. [2022-02-21 04:24:03,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 336 [2022-02-21 04:24:03,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 336 [2022-02-21 04:24:03,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 336 states and 492 transitions. [2022-02-21 04:24:03,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:03,666 INFO L681 BuchiCegarLoop]: Abstraction has 336 states and 492 transitions. [2022-02-21 04:24:03,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 336 states and 492 transitions. [2022-02-21 04:24:03,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 336 to 334. [2022-02-21 04:24:03,672 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:03,673 INFO L82 GeneralOperation]: Start isEquivalent. First operand 336 states and 492 transitions. Second operand has 334 states, 334 states have (on average 1.467065868263473) internal successors, (490), 333 states have internal predecessors, (490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,674 INFO L74 IsIncluded]: Start isIncluded. First operand 336 states and 492 transitions. Second operand has 334 states, 334 states have (on average 1.467065868263473) internal successors, (490), 333 states have internal predecessors, (490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,674 INFO L87 Difference]: Start difference. First operand 336 states and 492 transitions. Second operand has 334 states, 334 states have (on average 1.467065868263473) internal successors, (490), 333 states have internal predecessors, (490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:03,683 INFO L93 Difference]: Finished difference Result 336 states and 492 transitions. [2022-02-21 04:24:03,683 INFO L276 IsEmpty]: Start isEmpty. Operand 336 states and 492 transitions. [2022-02-21 04:24:03,684 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:03,684 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:03,685 INFO L74 IsIncluded]: Start isIncluded. First operand has 334 states, 334 states have (on average 1.467065868263473) internal successors, (490), 333 states have internal predecessors, (490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 336 states and 492 transitions. [2022-02-21 04:24:03,686 INFO L87 Difference]: Start difference. First operand has 334 states, 334 states have (on average 1.467065868263473) internal successors, (490), 333 states have internal predecessors, (490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 336 states and 492 transitions. [2022-02-21 04:24:03,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:03,696 INFO L93 Difference]: Finished difference Result 336 states and 492 transitions. [2022-02-21 04:24:03,696 INFO L276 IsEmpty]: Start isEmpty. Operand 336 states and 492 transitions. [2022-02-21 04:24:03,699 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:03,699 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:03,699 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:03,699 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:03,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 334 states, 334 states have (on average 1.467065868263473) internal successors, (490), 333 states have internal predecessors, (490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 334 states to 334 states and 490 transitions. [2022-02-21 04:24:03,708 INFO L704 BuchiCegarLoop]: Abstraction has 334 states and 490 transitions. [2022-02-21 04:24:03,709 INFO L587 BuchiCegarLoop]: Abstraction has 334 states and 490 transitions. [2022-02-21 04:24:03,709 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:03,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 334 states and 490 transitions. [2022-02-21 04:24:03,710 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 290 [2022-02-21 04:24:03,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:03,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:03,711 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:03,711 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:03,712 INFO L791 eck$LassoCheckResult]: Stem: 2395#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2367#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2164#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2165#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2381#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2264#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2236#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2237#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2222#L334 assume !(0 == ~M_E~0); 2223#L334-2 assume !(0 == ~T1_E~0); 2321#L339-1 assume !(0 == ~T2_E~0); 2313#L344-1 assume !(0 == ~E_1~0); 2314#L349-1 assume !(0 == ~E_2~0); 2234#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2235#L156 assume !(1 == ~m_pc~0); 2174#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2173#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2339#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2285#L405 assume !(0 != activate_threads_~tmp~1#1); 2270#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2271#L175 assume 1 == ~t1_pc~0; 2336#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2272#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2273#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2324#L413 assume !(0 != activate_threads_~tmp___0~0#1); 2325#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2385#L194 assume !(1 == ~t2_pc~0); 2311#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2283#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2228#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2211#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2212#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2183#L367 assume !(1 == ~M_E~0); 2184#L367-2 assume !(1 == ~T1_E~0); 2343#L372-1 assume !(1 == ~T2_E~0); 2344#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2206#L382-1 assume !(1 == ~E_2~0); 2207#L387-1 assume { :end_inline_reset_delta_events } true; 2198#L528-2 [2022-02-21 04:24:03,716 INFO L793 eck$LassoCheckResult]: Loop: 2198#L528-2 assume !false; 2312#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2379#L309 assume !false; 2380#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2175#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2176#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2399#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2398#L276 assume !(0 != eval_~tmp~0#1); 2185#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2186#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2397#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2368#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2369#L339-3 assume !(0 == ~T2_E~0); 2382#L344-3 assume !(0 == ~E_1~0); 2284#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2220#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2221#L156-9 assume 1 == ~m_pc~0; 2306#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2169#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2261#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2329#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2199#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2200#L175-9 assume 1 == ~t1_pc~0; 2245#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2246#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2322#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2323#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2445#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2440#L194-9 assume 1 == ~t2_pc~0; 2437#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2390#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2391#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2317#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2318#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2433#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2431#L367-5 assume !(1 == ~T1_E~0); 2224#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2225#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2195#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2217#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2357#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2227#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2208#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2209#L547 assume !(0 == start_simulation_~tmp~3#1); 2346#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2362#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2253#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2254#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 2232#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2233#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2251#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2197#L560 assume !(0 != start_simulation_~tmp___0~1#1); 2198#L528-2 [2022-02-21 04:24:03,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:03,717 INFO L85 PathProgramCache]: Analyzing trace with hash -1288865440, now seen corresponding path program 1 times [2022-02-21 04:24:03,718 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:03,718 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611171892] [2022-02-21 04:24:03,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:03,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:03,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:03,769 INFO L290 TraceCheckUtils]: 0: Hoare triple {3170#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,769 INFO L290 TraceCheckUtils]: 1: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,770 INFO L290 TraceCheckUtils]: 2: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,770 INFO L290 TraceCheckUtils]: 3: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,771 INFO L290 TraceCheckUtils]: 4: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,771 INFO L290 TraceCheckUtils]: 5: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,771 INFO L290 TraceCheckUtils]: 6: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,772 INFO L290 TraceCheckUtils]: 7: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,772 INFO L290 TraceCheckUtils]: 8: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,773 INFO L290 TraceCheckUtils]: 9: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,773 INFO L290 TraceCheckUtils]: 10: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,773 INFO L290 TraceCheckUtils]: 11: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,774 INFO L290 TraceCheckUtils]: 12: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,774 INFO L290 TraceCheckUtils]: 13: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3172#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:03,774 INFO L290 TraceCheckUtils]: 14: Hoare triple {3172#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {3173#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:03,775 INFO L290 TraceCheckUtils]: 15: Hoare triple {3173#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {3173#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:03,775 INFO L290 TraceCheckUtils]: 16: Hoare triple {3173#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3173#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:03,775 INFO L290 TraceCheckUtils]: 17: Hoare triple {3173#(not (= ~t1_pc~0 1))} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {3173#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:03,776 INFO L290 TraceCheckUtils]: 18: Hoare triple {3173#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {3173#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:03,777 INFO L290 TraceCheckUtils]: 19: Hoare triple {3173#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3173#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:03,777 INFO L290 TraceCheckUtils]: 20: Hoare triple {3173#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {3171#false} is VALID [2022-02-21 04:24:03,777 INFO L290 TraceCheckUtils]: 21: Hoare triple {3171#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {3171#false} is VALID [2022-02-21 04:24:03,777 INFO L290 TraceCheckUtils]: 22: Hoare triple {3171#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3171#false} is VALID [2022-02-21 04:24:03,778 INFO L290 TraceCheckUtils]: 23: Hoare triple {3171#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {3171#false} is VALID [2022-02-21 04:24:03,778 INFO L290 TraceCheckUtils]: 24: Hoare triple {3171#false} assume !(0 != activate_threads_~tmp___0~0#1); {3171#false} is VALID [2022-02-21 04:24:03,778 INFO L290 TraceCheckUtils]: 25: Hoare triple {3171#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3171#false} is VALID [2022-02-21 04:24:03,778 INFO L290 TraceCheckUtils]: 26: Hoare triple {3171#false} assume !(1 == ~t2_pc~0); {3171#false} is VALID [2022-02-21 04:24:03,778 INFO L290 TraceCheckUtils]: 27: Hoare triple {3171#false} is_transmit2_triggered_~__retres1~2#1 := 0; {3171#false} is VALID [2022-02-21 04:24:03,778 INFO L290 TraceCheckUtils]: 28: Hoare triple {3171#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3171#false} is VALID [2022-02-21 04:24:03,778 INFO L290 TraceCheckUtils]: 29: Hoare triple {3171#false} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {3171#false} is VALID [2022-02-21 04:24:03,778 INFO L290 TraceCheckUtils]: 30: Hoare triple {3171#false} assume !(0 != activate_threads_~tmp___1~0#1); {3171#false} is VALID [2022-02-21 04:24:03,779 INFO L290 TraceCheckUtils]: 31: Hoare triple {3171#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3171#false} is VALID [2022-02-21 04:24:03,779 INFO L290 TraceCheckUtils]: 32: Hoare triple {3171#false} assume !(1 == ~M_E~0); {3171#false} is VALID [2022-02-21 04:24:03,779 INFO L290 TraceCheckUtils]: 33: Hoare triple {3171#false} assume !(1 == ~T1_E~0); {3171#false} is VALID [2022-02-21 04:24:03,779 INFO L290 TraceCheckUtils]: 34: Hoare triple {3171#false} assume !(1 == ~T2_E~0); {3171#false} is VALID [2022-02-21 04:24:03,779 INFO L290 TraceCheckUtils]: 35: Hoare triple {3171#false} assume 1 == ~E_1~0;~E_1~0 := 2; {3171#false} is VALID [2022-02-21 04:24:03,779 INFO L290 TraceCheckUtils]: 36: Hoare triple {3171#false} assume !(1 == ~E_2~0); {3171#false} is VALID [2022-02-21 04:24:03,779 INFO L290 TraceCheckUtils]: 37: Hoare triple {3171#false} assume { :end_inline_reset_delta_events } true; {3171#false} is VALID [2022-02-21 04:24:03,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:03,780 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:03,780 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1611171892] [2022-02-21 04:24:03,780 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1611171892] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:03,781 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:03,781 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:03,781 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950949146] [2022-02-21 04:24:03,781 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:03,781 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:03,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:03,782 INFO L85 PathProgramCache]: Analyzing trace with hash 23037699, now seen corresponding path program 1 times [2022-02-21 04:24:03,782 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:03,782 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578855914] [2022-02-21 04:24:03,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:03,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:03,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:03,810 INFO L290 TraceCheckUtils]: 0: Hoare triple {3174#true} assume !false; {3174#true} is VALID [2022-02-21 04:24:03,810 INFO L290 TraceCheckUtils]: 1: Hoare triple {3174#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {3174#true} is VALID [2022-02-21 04:24:03,811 INFO L290 TraceCheckUtils]: 2: Hoare triple {3174#true} assume !false; {3174#true} is VALID [2022-02-21 04:24:03,811 INFO L290 TraceCheckUtils]: 3: Hoare triple {3174#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {3174#true} is VALID [2022-02-21 04:24:03,811 INFO L290 TraceCheckUtils]: 4: Hoare triple {3174#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {3174#true} is VALID [2022-02-21 04:24:03,811 INFO L290 TraceCheckUtils]: 5: Hoare triple {3174#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {3174#true} is VALID [2022-02-21 04:24:03,811 INFO L290 TraceCheckUtils]: 6: Hoare triple {3174#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {3174#true} is VALID [2022-02-21 04:24:03,811 INFO L290 TraceCheckUtils]: 7: Hoare triple {3174#true} assume !(0 != eval_~tmp~0#1); {3174#true} is VALID [2022-02-21 04:24:03,812 INFO L290 TraceCheckUtils]: 8: Hoare triple {3174#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {3174#true} is VALID [2022-02-21 04:24:03,812 INFO L290 TraceCheckUtils]: 9: Hoare triple {3174#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {3174#true} is VALID [2022-02-21 04:24:03,812 INFO L290 TraceCheckUtils]: 10: Hoare triple {3174#true} assume 0 == ~M_E~0;~M_E~0 := 1; {3174#true} is VALID [2022-02-21 04:24:03,812 INFO L290 TraceCheckUtils]: 11: Hoare triple {3174#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,813 INFO L290 TraceCheckUtils]: 12: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume !(0 == ~T2_E~0); {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,813 INFO L290 TraceCheckUtils]: 13: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume !(0 == ~E_1~0); {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,814 INFO L290 TraceCheckUtils]: 14: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,814 INFO L290 TraceCheckUtils]: 15: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,814 INFO L290 TraceCheckUtils]: 16: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~m_pc~0; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,815 INFO L290 TraceCheckUtils]: 17: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,815 INFO L290 TraceCheckUtils]: 18: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,816 INFO L290 TraceCheckUtils]: 19: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,816 INFO L290 TraceCheckUtils]: 20: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,816 INFO L290 TraceCheckUtils]: 21: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,817 INFO L290 TraceCheckUtils]: 22: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~t1_pc~0; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,817 INFO L290 TraceCheckUtils]: 23: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,817 INFO L290 TraceCheckUtils]: 24: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,818 INFO L290 TraceCheckUtils]: 25: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,818 INFO L290 TraceCheckUtils]: 26: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,819 INFO L290 TraceCheckUtils]: 27: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,819 INFO L290 TraceCheckUtils]: 28: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~t2_pc~0; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,819 INFO L290 TraceCheckUtils]: 29: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,820 INFO L290 TraceCheckUtils]: 30: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,820 INFO L290 TraceCheckUtils]: 31: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,820 INFO L290 TraceCheckUtils]: 32: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,821 INFO L290 TraceCheckUtils]: 33: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,821 INFO L290 TraceCheckUtils]: 34: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {3176#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:03,822 INFO L290 TraceCheckUtils]: 35: Hoare triple {3176#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~T1_E~0); {3175#false} is VALID [2022-02-21 04:24:03,822 INFO L290 TraceCheckUtils]: 36: Hoare triple {3175#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {3175#false} is VALID [2022-02-21 04:24:03,822 INFO L290 TraceCheckUtils]: 37: Hoare triple {3175#false} assume 1 == ~E_1~0;~E_1~0 := 2; {3175#false} is VALID [2022-02-21 04:24:03,822 INFO L290 TraceCheckUtils]: 38: Hoare triple {3175#false} assume 1 == ~E_2~0;~E_2~0 := 2; {3175#false} is VALID [2022-02-21 04:24:03,822 INFO L290 TraceCheckUtils]: 39: Hoare triple {3175#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {3175#false} is VALID [2022-02-21 04:24:03,822 INFO L290 TraceCheckUtils]: 40: Hoare triple {3175#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {3175#false} is VALID [2022-02-21 04:24:03,822 INFO L290 TraceCheckUtils]: 41: Hoare triple {3175#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {3175#false} is VALID [2022-02-21 04:24:03,822 INFO L290 TraceCheckUtils]: 42: Hoare triple {3175#false} start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {3175#false} is VALID [2022-02-21 04:24:03,822 INFO L290 TraceCheckUtils]: 43: Hoare triple {3175#false} assume !(0 == start_simulation_~tmp~3#1); {3175#false} is VALID [2022-02-21 04:24:03,823 INFO L290 TraceCheckUtils]: 44: Hoare triple {3175#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {3175#false} is VALID [2022-02-21 04:24:03,823 INFO L290 TraceCheckUtils]: 45: Hoare triple {3175#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {3175#false} is VALID [2022-02-21 04:24:03,823 INFO L290 TraceCheckUtils]: 46: Hoare triple {3175#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {3175#false} is VALID [2022-02-21 04:24:03,823 INFO L290 TraceCheckUtils]: 47: Hoare triple {3175#false} stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; {3175#false} is VALID [2022-02-21 04:24:03,823 INFO L290 TraceCheckUtils]: 48: Hoare triple {3175#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {3175#false} is VALID [2022-02-21 04:24:03,823 INFO L290 TraceCheckUtils]: 49: Hoare triple {3175#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {3175#false} is VALID [2022-02-21 04:24:03,823 INFO L290 TraceCheckUtils]: 50: Hoare triple {3175#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {3175#false} is VALID [2022-02-21 04:24:03,823 INFO L290 TraceCheckUtils]: 51: Hoare triple {3175#false} assume !(0 != start_simulation_~tmp___0~1#1); {3175#false} is VALID [2022-02-21 04:24:03,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:03,824 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:03,824 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1578855914] [2022-02-21 04:24:03,824 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1578855914] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:03,824 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:03,824 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:03,824 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154660584] [2022-02-21 04:24:03,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:03,825 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:03,825 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:03,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:03,826 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:03,826 INFO L87 Difference]: Start difference. First operand 334 states and 490 transitions. cyclomatic complexity: 158 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:04,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:04,422 INFO L93 Difference]: Finished difference Result 823 states and 1183 transitions. [2022-02-21 04:24:04,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:04,422 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:04,446 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:04,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 823 states and 1183 transitions. [2022-02-21 04:24:04,491 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 745 [2022-02-21 04:24:04,520 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 823 states to 823 states and 1183 transitions. [2022-02-21 04:24:04,520 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 823 [2022-02-21 04:24:04,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 823 [2022-02-21 04:24:04,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 823 states and 1183 transitions. [2022-02-21 04:24:04,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:04,521 INFO L681 BuchiCegarLoop]: Abstraction has 823 states and 1183 transitions. [2022-02-21 04:24:04,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 823 states and 1183 transitions. [2022-02-21 04:24:04,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 823 to 762. [2022-02-21 04:24:04,532 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:04,534 INFO L82 GeneralOperation]: Start isEquivalent. First operand 823 states and 1183 transitions. Second operand has 762 states, 762 states have (on average 1.4514435695538057) internal successors, (1106), 761 states have internal predecessors, (1106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:04,535 INFO L74 IsIncluded]: Start isIncluded. First operand 823 states and 1183 transitions. Second operand has 762 states, 762 states have (on average 1.4514435695538057) internal successors, (1106), 761 states have internal predecessors, (1106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:04,537 INFO L87 Difference]: Start difference. First operand 823 states and 1183 transitions. Second operand has 762 states, 762 states have (on average 1.4514435695538057) internal successors, (1106), 761 states have internal predecessors, (1106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:04,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:04,566 INFO L93 Difference]: Finished difference Result 823 states and 1183 transitions. [2022-02-21 04:24:04,566 INFO L276 IsEmpty]: Start isEmpty. Operand 823 states and 1183 transitions. [2022-02-21 04:24:04,567 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:04,567 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:04,569 INFO L74 IsIncluded]: Start isIncluded. First operand has 762 states, 762 states have (on average 1.4514435695538057) internal successors, (1106), 761 states have internal predecessors, (1106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 823 states and 1183 transitions. [2022-02-21 04:24:04,570 INFO L87 Difference]: Start difference. First operand has 762 states, 762 states have (on average 1.4514435695538057) internal successors, (1106), 761 states have internal predecessors, (1106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 823 states and 1183 transitions. [2022-02-21 04:24:04,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:04,598 INFO L93 Difference]: Finished difference Result 823 states and 1183 transitions. [2022-02-21 04:24:04,598 INFO L276 IsEmpty]: Start isEmpty. Operand 823 states and 1183 transitions. [2022-02-21 04:24:04,599 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:04,599 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:04,599 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:04,599 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:04,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 762 states, 762 states have (on average 1.4514435695538057) internal successors, (1106), 761 states have internal predecessors, (1106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:04,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 762 states to 762 states and 1106 transitions. [2022-02-21 04:24:04,624 INFO L704 BuchiCegarLoop]: Abstraction has 762 states and 1106 transitions. [2022-02-21 04:24:04,624 INFO L587 BuchiCegarLoop]: Abstraction has 762 states and 1106 transitions. [2022-02-21 04:24:04,624 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:04,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 762 states and 1106 transitions. [2022-02-21 04:24:04,627 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 715 [2022-02-21 04:24:04,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:04,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:04,627 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:04,627 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:04,628 INFO L791 eck$LassoCheckResult]: Stem: 4247#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4210#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4005#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4006#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4227#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 4100#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4072#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4073#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4059#L334 assume !(0 == ~M_E~0); 4060#L334-2 assume !(0 == ~T1_E~0); 4155#L339-1 assume !(0 == ~T2_E~0); 4148#L344-1 assume !(0 == ~E_1~0); 4149#L349-1 assume !(0 == ~E_2~0); 4070#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4071#L156 assume !(1 == ~m_pc~0); 4162#L156-2 is_master_triggered_~__retres1~0#1 := 0; 4186#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4171#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4120#L405 assume !(0 != activate_threads_~tmp~1#1); 4104#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4105#L175 assume !(1 == ~t1_pc~0); 4112#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4106#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4107#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4157#L413 assume !(0 != activate_threads_~tmp___0~0#1); 4158#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4232#L194 assume !(1 == ~t2_pc~0); 4147#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4116#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4061#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4048#L421 assume !(0 != activate_threads_~tmp___1~0#1); 4049#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4020#L367 assume !(1 == ~M_E~0); 4021#L367-2 assume !(1 == ~T1_E~0); 4175#L372-1 assume !(1 == ~T2_E~0); 4176#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4182#L382-1 assume !(1 == ~E_2~0); 4596#L387-1 assume { :end_inline_reset_delta_events } true; 4595#L528-2 [2022-02-21 04:24:04,628 INFO L793 eck$LassoCheckResult]: Loop: 4595#L528-2 assume !false; 4594#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4592#L309 assume !false; 4591#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4589#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4587#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4586#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4584#L276 assume !(0 != eval_~tmp~0#1); 4585#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4683#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4681#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4679#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4677#L339-3 assume !(0 == ~T2_E~0); 4675#L344-3 assume !(0 == ~E_1~0); 4673#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4671#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4669#L156-9 assume !(1 == ~m_pc~0); 4667#L156-11 is_master_triggered_~__retres1~0#1 := 0; 4665#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4663#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4658#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4656#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4654#L175-9 assume !(1 == ~t1_pc~0); 4653#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4652#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4651#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4650#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4649#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4648#L194-9 assume 1 == ~t2_pc~0; 4646#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4645#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4644#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4643#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4642#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4641#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4640#L367-5 assume !(1 == ~T1_E~0); 4639#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4062#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4032#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4054#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4154#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4632#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4045#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4046#L547 assume !(0 == start_simulation_~tmp~3#1); 4213#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4201#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4202#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4601#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 4600#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4599#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4598#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4597#L560 assume !(0 != start_simulation_~tmp___0~1#1); 4595#L528-2 [2022-02-21 04:24:04,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:04,628 INFO L85 PathProgramCache]: Analyzing trace with hash -148513729, now seen corresponding path program 1 times [2022-02-21 04:24:04,629 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:04,629 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010912659] [2022-02-21 04:24:04,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:04,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:04,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:04,658 INFO L290 TraceCheckUtils]: 0: Hoare triple {6413#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,659 INFO L290 TraceCheckUtils]: 1: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,659 INFO L290 TraceCheckUtils]: 2: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,659 INFO L290 TraceCheckUtils]: 3: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,660 INFO L290 TraceCheckUtils]: 4: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,660 INFO L290 TraceCheckUtils]: 5: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,660 INFO L290 TraceCheckUtils]: 6: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,661 INFO L290 TraceCheckUtils]: 7: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,661 INFO L290 TraceCheckUtils]: 8: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~M_E~0); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,661 INFO L290 TraceCheckUtils]: 9: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~T1_E~0); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,662 INFO L290 TraceCheckUtils]: 10: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~T2_E~0); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,662 INFO L290 TraceCheckUtils]: 11: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~E_1~0); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,662 INFO L290 TraceCheckUtils]: 12: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~E_2~0); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,663 INFO L290 TraceCheckUtils]: 13: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,663 INFO L290 TraceCheckUtils]: 14: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(1 == ~m_pc~0); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,664 INFO L290 TraceCheckUtils]: 15: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} is_master_triggered_~__retres1~0#1 := 0; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,664 INFO L290 TraceCheckUtils]: 16: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,664 INFO L290 TraceCheckUtils]: 17: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,671 INFO L290 TraceCheckUtils]: 18: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(0 != activate_threads_~tmp~1#1); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,671 INFO L290 TraceCheckUtils]: 19: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,672 INFO L290 TraceCheckUtils]: 20: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(1 == ~t1_pc~0); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,672 INFO L290 TraceCheckUtils]: 21: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,672 INFO L290 TraceCheckUtils]: 22: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,673 INFO L290 TraceCheckUtils]: 23: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,673 INFO L290 TraceCheckUtils]: 24: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(0 != activate_threads_~tmp___0~0#1); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,673 INFO L290 TraceCheckUtils]: 25: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,674 INFO L290 TraceCheckUtils]: 26: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(1 == ~t2_pc~0); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,674 INFO L290 TraceCheckUtils]: 27: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,675 INFO L290 TraceCheckUtils]: 28: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,675 INFO L290 TraceCheckUtils]: 29: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,675 INFO L290 TraceCheckUtils]: 30: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(0 != activate_threads_~tmp___1~0#1); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,676 INFO L290 TraceCheckUtils]: 31: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,676 INFO L290 TraceCheckUtils]: 32: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(1 == ~M_E~0); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,676 INFO L290 TraceCheckUtils]: 33: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(1 == ~T1_E~0); {6415#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:04,677 INFO L290 TraceCheckUtils]: 34: Hoare triple {6415#(= ~T2_E~0 ~E_1~0)} assume !(1 == ~T2_E~0); {6416#(not (= ~E_1~0 1))} is VALID [2022-02-21 04:24:04,677 INFO L290 TraceCheckUtils]: 35: Hoare triple {6416#(not (= ~E_1~0 1))} assume 1 == ~E_1~0;~E_1~0 := 2; {6414#false} is VALID [2022-02-21 04:24:04,677 INFO L290 TraceCheckUtils]: 36: Hoare triple {6414#false} assume !(1 == ~E_2~0); {6414#false} is VALID [2022-02-21 04:24:04,677 INFO L290 TraceCheckUtils]: 37: Hoare triple {6414#false} assume { :end_inline_reset_delta_events } true; {6414#false} is VALID [2022-02-21 04:24:04,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:04,678 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:04,678 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1010912659] [2022-02-21 04:24:04,678 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1010912659] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:04,678 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:04,678 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:04,678 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [163961984] [2022-02-21 04:24:04,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:04,679 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:04,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:04,679 INFO L85 PathProgramCache]: Analyzing trace with hash -1798923135, now seen corresponding path program 1 times [2022-02-21 04:24:04,679 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:04,679 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931964416] [2022-02-21 04:24:04,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:04,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:04,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:04,702 INFO L290 TraceCheckUtils]: 0: Hoare triple {6417#true} assume !false; {6417#true} is VALID [2022-02-21 04:24:04,703 INFO L290 TraceCheckUtils]: 1: Hoare triple {6417#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {6417#true} is VALID [2022-02-21 04:24:04,703 INFO L290 TraceCheckUtils]: 2: Hoare triple {6417#true} assume !false; {6417#true} is VALID [2022-02-21 04:24:04,703 INFO L290 TraceCheckUtils]: 3: Hoare triple {6417#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {6417#true} is VALID [2022-02-21 04:24:04,703 INFO L290 TraceCheckUtils]: 4: Hoare triple {6417#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {6417#true} is VALID [2022-02-21 04:24:04,703 INFO L290 TraceCheckUtils]: 5: Hoare triple {6417#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {6417#true} is VALID [2022-02-21 04:24:04,703 INFO L290 TraceCheckUtils]: 6: Hoare triple {6417#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {6417#true} is VALID [2022-02-21 04:24:04,703 INFO L290 TraceCheckUtils]: 7: Hoare triple {6417#true} assume !(0 != eval_~tmp~0#1); {6417#true} is VALID [2022-02-21 04:24:04,703 INFO L290 TraceCheckUtils]: 8: Hoare triple {6417#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {6417#true} is VALID [2022-02-21 04:24:04,704 INFO L290 TraceCheckUtils]: 9: Hoare triple {6417#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {6417#true} is VALID [2022-02-21 04:24:04,704 INFO L290 TraceCheckUtils]: 10: Hoare triple {6417#true} assume 0 == ~M_E~0;~M_E~0 := 1; {6417#true} is VALID [2022-02-21 04:24:04,704 INFO L290 TraceCheckUtils]: 11: Hoare triple {6417#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,704 INFO L290 TraceCheckUtils]: 12: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume !(0 == ~T2_E~0); {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,705 INFO L290 TraceCheckUtils]: 13: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume !(0 == ~E_1~0); {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,705 INFO L290 TraceCheckUtils]: 14: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,705 INFO L290 TraceCheckUtils]: 15: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,706 INFO L290 TraceCheckUtils]: 16: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~m_pc~0); {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,706 INFO L290 TraceCheckUtils]: 17: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,706 INFO L290 TraceCheckUtils]: 18: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,707 INFO L290 TraceCheckUtils]: 19: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,707 INFO L290 TraceCheckUtils]: 20: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,707 INFO L290 TraceCheckUtils]: 21: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,707 INFO L290 TraceCheckUtils]: 22: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~t1_pc~0); {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,708 INFO L290 TraceCheckUtils]: 23: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,708 INFO L290 TraceCheckUtils]: 24: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,708 INFO L290 TraceCheckUtils]: 25: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,709 INFO L290 TraceCheckUtils]: 26: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,709 INFO L290 TraceCheckUtils]: 27: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,709 INFO L290 TraceCheckUtils]: 28: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~t2_pc~0; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,710 INFO L290 TraceCheckUtils]: 29: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,710 INFO L290 TraceCheckUtils]: 30: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,710 INFO L290 TraceCheckUtils]: 31: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,711 INFO L290 TraceCheckUtils]: 32: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,711 INFO L290 TraceCheckUtils]: 33: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,711 INFO L290 TraceCheckUtils]: 34: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {6419#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:04,712 INFO L290 TraceCheckUtils]: 35: Hoare triple {6419#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~T1_E~0); {6418#false} is VALID [2022-02-21 04:24:04,712 INFO L290 TraceCheckUtils]: 36: Hoare triple {6418#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {6418#false} is VALID [2022-02-21 04:24:04,712 INFO L290 TraceCheckUtils]: 37: Hoare triple {6418#false} assume 1 == ~E_1~0;~E_1~0 := 2; {6418#false} is VALID [2022-02-21 04:24:04,712 INFO L290 TraceCheckUtils]: 38: Hoare triple {6418#false} assume 1 == ~E_2~0;~E_2~0 := 2; {6418#false} is VALID [2022-02-21 04:24:04,712 INFO L290 TraceCheckUtils]: 39: Hoare triple {6418#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {6418#false} is VALID [2022-02-21 04:24:04,712 INFO L290 TraceCheckUtils]: 40: Hoare triple {6418#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {6418#false} is VALID [2022-02-21 04:24:04,712 INFO L290 TraceCheckUtils]: 41: Hoare triple {6418#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {6418#false} is VALID [2022-02-21 04:24:04,712 INFO L290 TraceCheckUtils]: 42: Hoare triple {6418#false} start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {6418#false} is VALID [2022-02-21 04:24:04,713 INFO L290 TraceCheckUtils]: 43: Hoare triple {6418#false} assume !(0 == start_simulation_~tmp~3#1); {6418#false} is VALID [2022-02-21 04:24:04,713 INFO L290 TraceCheckUtils]: 44: Hoare triple {6418#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {6418#false} is VALID [2022-02-21 04:24:04,713 INFO L290 TraceCheckUtils]: 45: Hoare triple {6418#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {6418#false} is VALID [2022-02-21 04:24:04,713 INFO L290 TraceCheckUtils]: 46: Hoare triple {6418#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {6418#false} is VALID [2022-02-21 04:24:04,713 INFO L290 TraceCheckUtils]: 47: Hoare triple {6418#false} stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; {6418#false} is VALID [2022-02-21 04:24:04,713 INFO L290 TraceCheckUtils]: 48: Hoare triple {6418#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {6418#false} is VALID [2022-02-21 04:24:04,713 INFO L290 TraceCheckUtils]: 49: Hoare triple {6418#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {6418#false} is VALID [2022-02-21 04:24:04,713 INFO L290 TraceCheckUtils]: 50: Hoare triple {6418#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {6418#false} is VALID [2022-02-21 04:24:04,713 INFO L290 TraceCheckUtils]: 51: Hoare triple {6418#false} assume !(0 != start_simulation_~tmp___0~1#1); {6418#false} is VALID [2022-02-21 04:24:04,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:04,714 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:04,714 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [931964416] [2022-02-21 04:24:04,714 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [931964416] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:04,714 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:04,714 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:04,714 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348436904] [2022-02-21 04:24:04,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:04,715 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:04,715 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:04,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:04,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:04,716 INFO L87 Difference]: Start difference. First operand 762 states and 1106 transitions. cyclomatic complexity: 348 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:05,183 INFO L93 Difference]: Finished difference Result 679 states and 958 transitions. [2022-02-21 04:24:05,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:05,184 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,216 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:05,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 679 states and 958 transitions. [2022-02-21 04:24:05,238 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 631 [2022-02-21 04:24:05,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 679 states to 679 states and 958 transitions. [2022-02-21 04:24:05,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 679 [2022-02-21 04:24:05,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 679 [2022-02-21 04:24:05,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 679 states and 958 transitions. [2022-02-21 04:24:05,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:05,259 INFO L681 BuchiCegarLoop]: Abstraction has 679 states and 958 transitions. [2022-02-21 04:24:05,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 679 states and 958 transitions. [2022-02-21 04:24:05,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 679 to 663. [2022-02-21 04:24:05,267 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:05,269 INFO L82 GeneralOperation]: Start isEquivalent. First operand 679 states and 958 transitions. Second operand has 663 states, 663 states have (on average 1.4147812971342384) internal successors, (938), 662 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,270 INFO L74 IsIncluded]: Start isIncluded. First operand 679 states and 958 transitions. Second operand has 663 states, 663 states have (on average 1.4147812971342384) internal successors, (938), 662 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,271 INFO L87 Difference]: Start difference. First operand 679 states and 958 transitions. Second operand has 663 states, 663 states have (on average 1.4147812971342384) internal successors, (938), 662 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:05,291 INFO L93 Difference]: Finished difference Result 679 states and 958 transitions. [2022-02-21 04:24:05,291 INFO L276 IsEmpty]: Start isEmpty. Operand 679 states and 958 transitions. [2022-02-21 04:24:05,292 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:05,292 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:05,293 INFO L74 IsIncluded]: Start isIncluded. First operand has 663 states, 663 states have (on average 1.4147812971342384) internal successors, (938), 662 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 679 states and 958 transitions. [2022-02-21 04:24:05,294 INFO L87 Difference]: Start difference. First operand has 663 states, 663 states have (on average 1.4147812971342384) internal successors, (938), 662 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 679 states and 958 transitions. [2022-02-21 04:24:05,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:05,325 INFO L93 Difference]: Finished difference Result 679 states and 958 transitions. [2022-02-21 04:24:05,325 INFO L276 IsEmpty]: Start isEmpty. Operand 679 states and 958 transitions. [2022-02-21 04:24:05,326 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:05,326 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:05,326 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:05,326 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:05,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 663 states, 663 states have (on average 1.4147812971342384) internal successors, (938), 662 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 663 states to 663 states and 938 transitions. [2022-02-21 04:24:05,345 INFO L704 BuchiCegarLoop]: Abstraction has 663 states and 938 transitions. [2022-02-21 04:24:05,345 INFO L587 BuchiCegarLoop]: Abstraction has 663 states and 938 transitions. [2022-02-21 04:24:05,345 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:05,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 663 states and 938 transitions. [2022-02-21 04:24:05,348 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 619 [2022-02-21 04:24:05,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:05,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:05,349 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:05,349 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:05,349 INFO L791 eck$LassoCheckResult]: Stem: 7318#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 7290#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7104#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7105#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7309#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 7195#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7169#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7170#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7156#L334 assume !(0 == ~M_E~0); 7157#L334-2 assume !(0 == ~T1_E~0); 7249#L339-1 assume !(0 == ~T2_E~0); 7242#L344-1 assume !(0 == ~E_1~0); 7243#L349-1 assume !(0 == ~E_2~0); 7167#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7168#L156 assume !(1 == ~m_pc~0); 7256#L156-2 is_master_triggered_~__retres1~0#1 := 0; 7276#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7265#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7215#L405 assume !(0 != activate_threads_~tmp~1#1); 7199#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7200#L175 assume !(1 == ~t1_pc~0); 7207#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7201#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7202#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7251#L413 assume !(0 != activate_threads_~tmp___0~0#1); 7252#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7311#L194 assume !(1 == ~t2_pc~0); 7241#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7211#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7158#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7145#L421 assume !(0 != activate_threads_~tmp___1~0#1); 7146#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7119#L367 assume !(1 == ~M_E~0); 7120#L367-2 assume !(1 == ~T1_E~0); 7269#L372-1 assume !(1 == ~T2_E~0); 7270#L377-1 assume !(1 == ~E_1~0); 7140#L382-1 assume !(1 == ~E_2~0); 7141#L387-1 assume { :end_inline_reset_delta_events } true; 7217#L528-2 [2022-02-21 04:24:05,351 INFO L793 eck$LassoCheckResult]: Loop: 7217#L528-2 assume !false; 7371#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7366#L309 assume !false; 7365#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7363#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7361#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7360#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7355#L276 assume !(0 != eval_~tmp~0#1); 7356#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7450#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7449#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7448#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7447#L339-3 assume !(0 == ~T2_E~0); 7446#L344-3 assume !(0 == ~E_1~0); 7445#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7444#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7443#L156-9 assume !(1 == ~m_pc~0); 7442#L156-11 is_master_triggered_~__retres1~0#1 := 0; 7441#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7440#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7439#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7437#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7435#L175-9 assume !(1 == ~t1_pc~0); 7433#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 7431#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7429#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7427#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7425#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7423#L194-9 assume 1 == ~t2_pc~0; 7420#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7418#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7416#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7414#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7412#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7409#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7407#L367-5 assume !(1 == ~T1_E~0); 7405#L372-3 assume !(1 == ~T2_E~0); 7403#L377-3 assume !(1 == ~E_1~0); 7401#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7399#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7396#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7393#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7391#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 7388#L547 assume !(0 == start_simulation_~tmp~3#1); 7386#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7384#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7382#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7381#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 7380#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7379#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7378#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7376#L560 assume !(0 != start_simulation_~tmp___0~1#1); 7217#L528-2 [2022-02-21 04:24:05,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:05,352 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2022-02-21 04:24:05,352 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:05,352 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079837734] [2022-02-21 04:24:05,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:05,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:05,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:05,359 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:05,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:05,385 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:05,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:05,386 INFO L85 PathProgramCache]: Analyzing trace with hash 195112129, now seen corresponding path program 1 times [2022-02-21 04:24:05,386 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:05,386 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [883894513] [2022-02-21 04:24:05,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:05,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:05,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:05,409 INFO L290 TraceCheckUtils]: 0: Hoare triple {9127#true} assume !false; {9127#true} is VALID [2022-02-21 04:24:05,409 INFO L290 TraceCheckUtils]: 1: Hoare triple {9127#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {9127#true} is VALID [2022-02-21 04:24:05,410 INFO L290 TraceCheckUtils]: 2: Hoare triple {9127#true} assume !false; {9127#true} is VALID [2022-02-21 04:24:05,410 INFO L290 TraceCheckUtils]: 3: Hoare triple {9127#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {9127#true} is VALID [2022-02-21 04:24:05,410 INFO L290 TraceCheckUtils]: 4: Hoare triple {9127#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {9127#true} is VALID [2022-02-21 04:24:05,410 INFO L290 TraceCheckUtils]: 5: Hoare triple {9127#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {9127#true} is VALID [2022-02-21 04:24:05,410 INFO L290 TraceCheckUtils]: 6: Hoare triple {9127#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {9127#true} is VALID [2022-02-21 04:24:05,410 INFO L290 TraceCheckUtils]: 7: Hoare triple {9127#true} assume !(0 != eval_~tmp~0#1); {9127#true} is VALID [2022-02-21 04:24:05,410 INFO L290 TraceCheckUtils]: 8: Hoare triple {9127#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {9127#true} is VALID [2022-02-21 04:24:05,410 INFO L290 TraceCheckUtils]: 9: Hoare triple {9127#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {9127#true} is VALID [2022-02-21 04:24:05,410 INFO L290 TraceCheckUtils]: 10: Hoare triple {9127#true} assume 0 == ~M_E~0;~M_E~0 := 1; {9127#true} is VALID [2022-02-21 04:24:05,411 INFO L290 TraceCheckUtils]: 11: Hoare triple {9127#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,413 INFO L290 TraceCheckUtils]: 12: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume !(0 == ~T2_E~0); {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,413 INFO L290 TraceCheckUtils]: 13: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume !(0 == ~E_1~0); {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,413 INFO L290 TraceCheckUtils]: 14: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,414 INFO L290 TraceCheckUtils]: 15: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,414 INFO L290 TraceCheckUtils]: 16: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~m_pc~0); {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,415 INFO L290 TraceCheckUtils]: 17: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,415 INFO L290 TraceCheckUtils]: 18: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,415 INFO L290 TraceCheckUtils]: 19: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,416 INFO L290 TraceCheckUtils]: 20: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,416 INFO L290 TraceCheckUtils]: 21: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,419 INFO L290 TraceCheckUtils]: 22: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~t1_pc~0); {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,419 INFO L290 TraceCheckUtils]: 23: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,420 INFO L290 TraceCheckUtils]: 24: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,420 INFO L290 TraceCheckUtils]: 25: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,420 INFO L290 TraceCheckUtils]: 26: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,421 INFO L290 TraceCheckUtils]: 27: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,421 INFO L290 TraceCheckUtils]: 28: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~t2_pc~0; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,421 INFO L290 TraceCheckUtils]: 29: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,422 INFO L290 TraceCheckUtils]: 30: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,422 INFO L290 TraceCheckUtils]: 31: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,422 INFO L290 TraceCheckUtils]: 32: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,423 INFO L290 TraceCheckUtils]: 33: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,423 INFO L290 TraceCheckUtils]: 34: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {9129#(= (+ (- 1) ~T1_E~0) 0)} is VALID [2022-02-21 04:24:05,423 INFO L290 TraceCheckUtils]: 35: Hoare triple {9129#(= (+ (- 1) ~T1_E~0) 0)} assume !(1 == ~T1_E~0); {9128#false} is VALID [2022-02-21 04:24:05,424 INFO L290 TraceCheckUtils]: 36: Hoare triple {9128#false} assume !(1 == ~T2_E~0); {9128#false} is VALID [2022-02-21 04:24:05,424 INFO L290 TraceCheckUtils]: 37: Hoare triple {9128#false} assume !(1 == ~E_1~0); {9128#false} is VALID [2022-02-21 04:24:05,424 INFO L290 TraceCheckUtils]: 38: Hoare triple {9128#false} assume 1 == ~E_2~0;~E_2~0 := 2; {9128#false} is VALID [2022-02-21 04:24:05,424 INFO L290 TraceCheckUtils]: 39: Hoare triple {9128#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {9128#false} is VALID [2022-02-21 04:24:05,424 INFO L290 TraceCheckUtils]: 40: Hoare triple {9128#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {9128#false} is VALID [2022-02-21 04:24:05,424 INFO L290 TraceCheckUtils]: 41: Hoare triple {9128#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {9128#false} is VALID [2022-02-21 04:24:05,425 INFO L290 TraceCheckUtils]: 42: Hoare triple {9128#false} start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {9128#false} is VALID [2022-02-21 04:24:05,425 INFO L290 TraceCheckUtils]: 43: Hoare triple {9128#false} assume !(0 == start_simulation_~tmp~3#1); {9128#false} is VALID [2022-02-21 04:24:05,425 INFO L290 TraceCheckUtils]: 44: Hoare triple {9128#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {9128#false} is VALID [2022-02-21 04:24:05,425 INFO L290 TraceCheckUtils]: 45: Hoare triple {9128#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {9128#false} is VALID [2022-02-21 04:24:05,425 INFO L290 TraceCheckUtils]: 46: Hoare triple {9128#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {9128#false} is VALID [2022-02-21 04:24:05,425 INFO L290 TraceCheckUtils]: 47: Hoare triple {9128#false} stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; {9128#false} is VALID [2022-02-21 04:24:05,425 INFO L290 TraceCheckUtils]: 48: Hoare triple {9128#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {9128#false} is VALID [2022-02-21 04:24:05,426 INFO L290 TraceCheckUtils]: 49: Hoare triple {9128#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {9128#false} is VALID [2022-02-21 04:24:05,426 INFO L290 TraceCheckUtils]: 50: Hoare triple {9128#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {9128#false} is VALID [2022-02-21 04:24:05,426 INFO L290 TraceCheckUtils]: 51: Hoare triple {9128#false} assume !(0 != start_simulation_~tmp___0~1#1); {9128#false} is VALID [2022-02-21 04:24:05,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:05,427 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:05,427 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [883894513] [2022-02-21 04:24:05,427 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [883894513] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:05,429 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:05,429 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:05,430 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1746540306] [2022-02-21 04:24:05,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:05,430 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:05,431 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:05,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:05,431 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:05,431 INFO L87 Difference]: Start difference. First operand 663 states and 938 transitions. cyclomatic complexity: 278 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:05,665 INFO L93 Difference]: Finished difference Result 819 states and 1148 transitions. [2022-02-21 04:24:05,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:05,666 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,699 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 52 edges. 52 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:05,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 819 states and 1148 transitions. [2022-02-21 04:24:05,729 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 750 [2022-02-21 04:24:05,759 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 819 states to 819 states and 1148 transitions. [2022-02-21 04:24:05,759 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 819 [2022-02-21 04:24:05,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 819 [2022-02-21 04:24:05,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 819 states and 1148 transitions. [2022-02-21 04:24:05,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:05,760 INFO L681 BuchiCegarLoop]: Abstraction has 819 states and 1148 transitions. [2022-02-21 04:24:05,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 819 states and 1148 transitions. [2022-02-21 04:24:05,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 819 to 819. [2022-02-21 04:24:05,769 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:05,770 INFO L82 GeneralOperation]: Start isEquivalent. First operand 819 states and 1148 transitions. Second operand has 819 states, 819 states have (on average 1.4017094017094016) internal successors, (1148), 818 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,772 INFO L74 IsIncluded]: Start isIncluded. First operand 819 states and 1148 transitions. Second operand has 819 states, 819 states have (on average 1.4017094017094016) internal successors, (1148), 818 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,773 INFO L87 Difference]: Start difference. First operand 819 states and 1148 transitions. Second operand has 819 states, 819 states have (on average 1.4017094017094016) internal successors, (1148), 818 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:05,801 INFO L93 Difference]: Finished difference Result 819 states and 1148 transitions. [2022-02-21 04:24:05,801 INFO L276 IsEmpty]: Start isEmpty. Operand 819 states and 1148 transitions. [2022-02-21 04:24:05,802 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:05,802 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:05,804 INFO L74 IsIncluded]: Start isIncluded. First operand has 819 states, 819 states have (on average 1.4017094017094016) internal successors, (1148), 818 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 819 states and 1148 transitions. [2022-02-21 04:24:05,805 INFO L87 Difference]: Start difference. First operand has 819 states, 819 states have (on average 1.4017094017094016) internal successors, (1148), 818 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 819 states and 1148 transitions. [2022-02-21 04:24:05,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:05,833 INFO L93 Difference]: Finished difference Result 819 states and 1148 transitions. [2022-02-21 04:24:05,833 INFO L276 IsEmpty]: Start isEmpty. Operand 819 states and 1148 transitions. [2022-02-21 04:24:05,834 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:05,834 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:05,834 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:05,834 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:05,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 819 states, 819 states have (on average 1.4017094017094016) internal successors, (1148), 818 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 819 states to 819 states and 1148 transitions. [2022-02-21 04:24:05,882 INFO L704 BuchiCegarLoop]: Abstraction has 819 states and 1148 transitions. [2022-02-21 04:24:05,883 INFO L587 BuchiCegarLoop]: Abstraction has 819 states and 1148 transitions. [2022-02-21 04:24:05,883 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:05,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 819 states and 1148 transitions. [2022-02-21 04:24:05,886 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 750 [2022-02-21 04:24:05,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:05,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:05,886 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:05,886 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:05,887 INFO L791 eck$LassoCheckResult]: Stem: 10199#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 10152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9952#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9953#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10179#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 10046#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10016#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10017#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10004#L334 assume !(0 == ~M_E~0); 10005#L334-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10103#L339-1 assume !(0 == ~T2_E~0); 10104#L344-1 assume !(0 == ~E_1~0); 10356#L349-1 assume !(0 == ~E_2~0); 10014#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10015#L156 assume !(1 == ~m_pc~0); 10112#L156-2 is_master_triggered_~__retres1~0#1 := 0; 10354#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10353#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10067#L405 assume !(0 != activate_threads_~tmp~1#1); 10051#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10052#L175 assume !(1 == ~t1_pc~0); 10059#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10053#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10054#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10107#L413 assume !(0 != activate_threads_~tmp___0~0#1); 10108#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10182#L194 assume !(1 == ~t2_pc~0); 10096#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10063#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10006#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9993#L421 assume !(0 != activate_threads_~tmp___1~0#1); 9994#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9967#L367 assume !(1 == ~M_E~0); 9968#L367-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10127#L372-1 assume !(1 == ~T2_E~0); 10128#L377-1 assume !(1 == ~E_1~0); 9988#L382-1 assume !(1 == ~E_2~0); 9989#L387-1 assume { :end_inline_reset_delta_events } true; 10070#L528-2 [2022-02-21 04:24:05,887 INFO L793 eck$LassoCheckResult]: Loop: 10070#L528-2 assume !false; 10236#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10231#L309 assume !false; 10230#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10228#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10226#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10225#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10223#L276 assume !(0 != eval_~tmp~0#1); 10224#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10325#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10323#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10320#L334-5 assume !(0 == ~T1_E~0); 10321#L339-3 assume !(0 == ~T2_E~0); 10339#L344-3 assume !(0 == ~E_1~0); 10338#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10337#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10336#L156-9 assume !(1 == ~m_pc~0); 10335#L156-11 is_master_triggered_~__retres1~0#1 := 0; 10334#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10333#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10332#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10331#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10330#L175-9 assume !(1 == ~t1_pc~0); 10329#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 10328#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10327#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10326#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10324#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10322#L194-9 assume 1 == ~t2_pc~0; 10318#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10316#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10314#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10312#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10310#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10308#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10272#L367-5 assume !(1 == ~T1_E~0); 10270#L372-3 assume !(1 == ~T2_E~0); 10268#L377-3 assume !(1 == ~E_1~0); 10266#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10264#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10260#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10257#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10255#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 10252#L547 assume !(0 == start_simulation_~tmp~3#1); 10250#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10248#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10246#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10245#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 10243#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10242#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10241#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10239#L560 assume !(0 != start_simulation_~tmp___0~1#1); 10070#L528-2 [2022-02-21 04:24:05,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:05,887 INFO L85 PathProgramCache]: Analyzing trace with hash -1536562243, now seen corresponding path program 1 times [2022-02-21 04:24:05,888 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:05,888 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373308916] [2022-02-21 04:24:05,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:05,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:05,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:05,930 INFO L290 TraceCheckUtils]: 0: Hoare triple {12409#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; {12411#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:05,930 INFO L290 TraceCheckUtils]: 1: Hoare triple {12411#(<= 2 ~T1_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {12411#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:05,931 INFO L290 TraceCheckUtils]: 2: Hoare triple {12411#(<= 2 ~T1_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {12411#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:05,931 INFO L290 TraceCheckUtils]: 3: Hoare triple {12411#(<= 2 ~T1_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {12411#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:05,931 INFO L290 TraceCheckUtils]: 4: Hoare triple {12411#(<= 2 ~T1_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {12411#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:05,932 INFO L290 TraceCheckUtils]: 5: Hoare triple {12411#(<= 2 ~T1_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {12411#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:05,932 INFO L290 TraceCheckUtils]: 6: Hoare triple {12411#(<= 2 ~T1_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {12411#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:05,932 INFO L290 TraceCheckUtils]: 7: Hoare triple {12411#(<= 2 ~T1_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {12411#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:05,933 INFO L290 TraceCheckUtils]: 8: Hoare triple {12411#(<= 2 ~T1_E~0)} assume !(0 == ~M_E~0); {12411#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:05,935 INFO L290 TraceCheckUtils]: 9: Hoare triple {12411#(<= 2 ~T1_E~0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {12410#false} is VALID [2022-02-21 04:24:05,935 INFO L290 TraceCheckUtils]: 10: Hoare triple {12410#false} assume !(0 == ~T2_E~0); {12410#false} is VALID [2022-02-21 04:24:05,936 INFO L290 TraceCheckUtils]: 11: Hoare triple {12410#false} assume !(0 == ~E_1~0); {12410#false} is VALID [2022-02-21 04:24:05,936 INFO L290 TraceCheckUtils]: 12: Hoare triple {12410#false} assume !(0 == ~E_2~0); {12410#false} is VALID [2022-02-21 04:24:05,936 INFO L290 TraceCheckUtils]: 13: Hoare triple {12410#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12410#false} is VALID [2022-02-21 04:24:05,936 INFO L290 TraceCheckUtils]: 14: Hoare triple {12410#false} assume !(1 == ~m_pc~0); {12410#false} is VALID [2022-02-21 04:24:05,936 INFO L290 TraceCheckUtils]: 15: Hoare triple {12410#false} is_master_triggered_~__retres1~0#1 := 0; {12410#false} is VALID [2022-02-21 04:24:05,936 INFO L290 TraceCheckUtils]: 16: Hoare triple {12410#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12410#false} is VALID [2022-02-21 04:24:05,936 INFO L290 TraceCheckUtils]: 17: Hoare triple {12410#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {12410#false} is VALID [2022-02-21 04:24:05,936 INFO L290 TraceCheckUtils]: 18: Hoare triple {12410#false} assume !(0 != activate_threads_~tmp~1#1); {12410#false} is VALID [2022-02-21 04:24:05,936 INFO L290 TraceCheckUtils]: 19: Hoare triple {12410#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12410#false} is VALID [2022-02-21 04:24:05,937 INFO L290 TraceCheckUtils]: 20: Hoare triple {12410#false} assume !(1 == ~t1_pc~0); {12410#false} is VALID [2022-02-21 04:24:05,937 INFO L290 TraceCheckUtils]: 21: Hoare triple {12410#false} is_transmit1_triggered_~__retres1~1#1 := 0; {12410#false} is VALID [2022-02-21 04:24:05,937 INFO L290 TraceCheckUtils]: 22: Hoare triple {12410#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12410#false} is VALID [2022-02-21 04:24:05,937 INFO L290 TraceCheckUtils]: 23: Hoare triple {12410#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {12410#false} is VALID [2022-02-21 04:24:05,937 INFO L290 TraceCheckUtils]: 24: Hoare triple {12410#false} assume !(0 != activate_threads_~tmp___0~0#1); {12410#false} is VALID [2022-02-21 04:24:05,937 INFO L290 TraceCheckUtils]: 25: Hoare triple {12410#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {12410#false} is VALID [2022-02-21 04:24:05,937 INFO L290 TraceCheckUtils]: 26: Hoare triple {12410#false} assume !(1 == ~t2_pc~0); {12410#false} is VALID [2022-02-21 04:24:05,937 INFO L290 TraceCheckUtils]: 27: Hoare triple {12410#false} is_transmit2_triggered_~__retres1~2#1 := 0; {12410#false} is VALID [2022-02-21 04:24:05,937 INFO L290 TraceCheckUtils]: 28: Hoare triple {12410#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {12410#false} is VALID [2022-02-21 04:24:05,937 INFO L290 TraceCheckUtils]: 29: Hoare triple {12410#false} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {12410#false} is VALID [2022-02-21 04:24:05,938 INFO L290 TraceCheckUtils]: 30: Hoare triple {12410#false} assume !(0 != activate_threads_~tmp___1~0#1); {12410#false} is VALID [2022-02-21 04:24:05,938 INFO L290 TraceCheckUtils]: 31: Hoare triple {12410#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12410#false} is VALID [2022-02-21 04:24:05,938 INFO L290 TraceCheckUtils]: 32: Hoare triple {12410#false} assume !(1 == ~M_E~0); {12410#false} is VALID [2022-02-21 04:24:05,938 INFO L290 TraceCheckUtils]: 33: Hoare triple {12410#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {12410#false} is VALID [2022-02-21 04:24:05,938 INFO L290 TraceCheckUtils]: 34: Hoare triple {12410#false} assume !(1 == ~T2_E~0); {12410#false} is VALID [2022-02-21 04:24:05,938 INFO L290 TraceCheckUtils]: 35: Hoare triple {12410#false} assume !(1 == ~E_1~0); {12410#false} is VALID [2022-02-21 04:24:05,938 INFO L290 TraceCheckUtils]: 36: Hoare triple {12410#false} assume !(1 == ~E_2~0); {12410#false} is VALID [2022-02-21 04:24:05,938 INFO L290 TraceCheckUtils]: 37: Hoare triple {12410#false} assume { :end_inline_reset_delta_events } true; {12410#false} is VALID [2022-02-21 04:24:05,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:05,939 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:05,939 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373308916] [2022-02-21 04:24:05,939 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373308916] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:05,939 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:05,939 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:05,939 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2056287172] [2022-02-21 04:24:05,939 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:05,940 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:05,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:05,940 INFO L85 PathProgramCache]: Analyzing trace with hash 618758851, now seen corresponding path program 1 times [2022-02-21 04:24:05,940 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:05,940 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217905418] [2022-02-21 04:24:05,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:05,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:05,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:05,981 INFO L290 TraceCheckUtils]: 0: Hoare triple {12412#true} assume !false; {12412#true} is VALID [2022-02-21 04:24:05,982 INFO L290 TraceCheckUtils]: 1: Hoare triple {12412#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {12412#true} is VALID [2022-02-21 04:24:05,982 INFO L290 TraceCheckUtils]: 2: Hoare triple {12412#true} assume !false; {12412#true} is VALID [2022-02-21 04:24:05,982 INFO L290 TraceCheckUtils]: 3: Hoare triple {12412#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {12412#true} is VALID [2022-02-21 04:24:05,982 INFO L290 TraceCheckUtils]: 4: Hoare triple {12412#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {12414#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} is VALID [2022-02-21 04:24:05,983 INFO L290 TraceCheckUtils]: 5: Hoare triple {12414#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {12415#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:05,983 INFO L290 TraceCheckUtils]: 6: Hoare triple {12415#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {12416#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 7: Hoare triple {12416#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {12413#false} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 8: Hoare triple {12413#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {12413#false} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 9: Hoare triple {12413#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {12413#false} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 10: Hoare triple {12413#false} assume 0 == ~M_E~0;~M_E~0 := 1; {12413#false} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 11: Hoare triple {12413#false} assume !(0 == ~T1_E~0); {12413#false} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 12: Hoare triple {12413#false} assume !(0 == ~T2_E~0); {12413#false} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 13: Hoare triple {12413#false} assume !(0 == ~E_1~0); {12413#false} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 14: Hoare triple {12413#false} assume 0 == ~E_2~0;~E_2~0 := 1; {12413#false} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 15: Hoare triple {12413#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12413#false} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 16: Hoare triple {12413#false} assume !(1 == ~m_pc~0); {12413#false} is VALID [2022-02-21 04:24:05,984 INFO L290 TraceCheckUtils]: 17: Hoare triple {12413#false} is_master_triggered_~__retres1~0#1 := 0; {12413#false} is VALID [2022-02-21 04:24:05,985 INFO L290 TraceCheckUtils]: 18: Hoare triple {12413#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12413#false} is VALID [2022-02-21 04:24:05,985 INFO L290 TraceCheckUtils]: 19: Hoare triple {12413#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {12413#false} is VALID [2022-02-21 04:24:05,985 INFO L290 TraceCheckUtils]: 20: Hoare triple {12413#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {12413#false} is VALID [2022-02-21 04:24:05,985 INFO L290 TraceCheckUtils]: 21: Hoare triple {12413#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12413#false} is VALID [2022-02-21 04:24:05,985 INFO L290 TraceCheckUtils]: 22: Hoare triple {12413#false} assume !(1 == ~t1_pc~0); {12413#false} is VALID [2022-02-21 04:24:05,985 INFO L290 TraceCheckUtils]: 23: Hoare triple {12413#false} is_transmit1_triggered_~__retres1~1#1 := 0; {12413#false} is VALID [2022-02-21 04:24:05,985 INFO L290 TraceCheckUtils]: 24: Hoare triple {12413#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12413#false} is VALID [2022-02-21 04:24:05,985 INFO L290 TraceCheckUtils]: 25: Hoare triple {12413#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {12413#false} is VALID [2022-02-21 04:24:05,986 INFO L290 TraceCheckUtils]: 26: Hoare triple {12413#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {12413#false} is VALID [2022-02-21 04:24:05,986 INFO L290 TraceCheckUtils]: 27: Hoare triple {12413#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {12413#false} is VALID [2022-02-21 04:24:05,987 INFO L290 TraceCheckUtils]: 28: Hoare triple {12413#false} assume 1 == ~t2_pc~0; {12413#false} is VALID [2022-02-21 04:24:05,987 INFO L290 TraceCheckUtils]: 29: Hoare triple {12413#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {12413#false} is VALID [2022-02-21 04:24:05,987 INFO L290 TraceCheckUtils]: 30: Hoare triple {12413#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {12413#false} is VALID [2022-02-21 04:24:05,987 INFO L290 TraceCheckUtils]: 31: Hoare triple {12413#false} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {12413#false} is VALID [2022-02-21 04:24:05,987 INFO L290 TraceCheckUtils]: 32: Hoare triple {12413#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {12413#false} is VALID [2022-02-21 04:24:05,987 INFO L290 TraceCheckUtils]: 33: Hoare triple {12413#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12413#false} is VALID [2022-02-21 04:24:05,987 INFO L290 TraceCheckUtils]: 34: Hoare triple {12413#false} assume 1 == ~M_E~0;~M_E~0 := 2; {12413#false} is VALID [2022-02-21 04:24:05,987 INFO L290 TraceCheckUtils]: 35: Hoare triple {12413#false} assume !(1 == ~T1_E~0); {12413#false} is VALID [2022-02-21 04:24:05,988 INFO L290 TraceCheckUtils]: 36: Hoare triple {12413#false} assume !(1 == ~T2_E~0); {12413#false} is VALID [2022-02-21 04:24:05,988 INFO L290 TraceCheckUtils]: 37: Hoare triple {12413#false} assume !(1 == ~E_1~0); {12413#false} is VALID [2022-02-21 04:24:05,988 INFO L290 TraceCheckUtils]: 38: Hoare triple {12413#false} assume 1 == ~E_2~0;~E_2~0 := 2; {12413#false} is VALID [2022-02-21 04:24:05,988 INFO L290 TraceCheckUtils]: 39: Hoare triple {12413#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {12413#false} is VALID [2022-02-21 04:24:05,988 INFO L290 TraceCheckUtils]: 40: Hoare triple {12413#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {12413#false} is VALID [2022-02-21 04:24:05,988 INFO L290 TraceCheckUtils]: 41: Hoare triple {12413#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {12413#false} is VALID [2022-02-21 04:24:05,988 INFO L290 TraceCheckUtils]: 42: Hoare triple {12413#false} start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {12413#false} is VALID [2022-02-21 04:24:05,988 INFO L290 TraceCheckUtils]: 43: Hoare triple {12413#false} assume !(0 == start_simulation_~tmp~3#1); {12413#false} is VALID [2022-02-21 04:24:05,988 INFO L290 TraceCheckUtils]: 44: Hoare triple {12413#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {12413#false} is VALID [2022-02-21 04:24:05,988 INFO L290 TraceCheckUtils]: 45: Hoare triple {12413#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {12413#false} is VALID [2022-02-21 04:24:05,989 INFO L290 TraceCheckUtils]: 46: Hoare triple {12413#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {12413#false} is VALID [2022-02-21 04:24:05,989 INFO L290 TraceCheckUtils]: 47: Hoare triple {12413#false} stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; {12413#false} is VALID [2022-02-21 04:24:05,989 INFO L290 TraceCheckUtils]: 48: Hoare triple {12413#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {12413#false} is VALID [2022-02-21 04:24:05,989 INFO L290 TraceCheckUtils]: 49: Hoare triple {12413#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {12413#false} is VALID [2022-02-21 04:24:05,989 INFO L290 TraceCheckUtils]: 50: Hoare triple {12413#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {12413#false} is VALID [2022-02-21 04:24:05,989 INFO L290 TraceCheckUtils]: 51: Hoare triple {12413#false} assume !(0 != start_simulation_~tmp___0~1#1); {12413#false} is VALID [2022-02-21 04:24:05,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:05,989 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:05,989 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217905418] [2022-02-21 04:24:05,990 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1217905418] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:05,990 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:05,990 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:05,990 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1692552031] [2022-02-21 04:24:05,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:05,990 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:05,990 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:05,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:05,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:05,992 INFO L87 Difference]: Start difference. First operand 819 states and 1148 transitions. cyclomatic complexity: 332 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:06,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:06,175 INFO L93 Difference]: Finished difference Result 663 states and 921 transitions. [2022-02-21 04:24:06,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:06,175 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:06,204 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:06,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 663 states and 921 transitions. [2022-02-21 04:24:06,228 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 619 [2022-02-21 04:24:06,247 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 663 states to 663 states and 921 transitions. [2022-02-21 04:24:06,248 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 663 [2022-02-21 04:24:06,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 663 [2022-02-21 04:24:06,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 663 states and 921 transitions. [2022-02-21 04:24:06,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:06,249 INFO L681 BuchiCegarLoop]: Abstraction has 663 states and 921 transitions. [2022-02-21 04:24:06,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 663 states and 921 transitions. [2022-02-21 04:24:06,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 663 to 663. [2022-02-21 04:24:06,255 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:06,257 INFO L82 GeneralOperation]: Start isEquivalent. First operand 663 states and 921 transitions. Second operand has 663 states, 663 states have (on average 1.3891402714932126) internal successors, (921), 662 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:06,258 INFO L74 IsIncluded]: Start isIncluded. First operand 663 states and 921 transitions. Second operand has 663 states, 663 states have (on average 1.3891402714932126) internal successors, (921), 662 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:06,259 INFO L87 Difference]: Start difference. First operand 663 states and 921 transitions. Second operand has 663 states, 663 states have (on average 1.3891402714932126) internal successors, (921), 662 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:06,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:06,278 INFO L93 Difference]: Finished difference Result 663 states and 921 transitions. [2022-02-21 04:24:06,278 INFO L276 IsEmpty]: Start isEmpty. Operand 663 states and 921 transitions. [2022-02-21 04:24:06,279 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:06,279 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:06,281 INFO L74 IsIncluded]: Start isIncluded. First operand has 663 states, 663 states have (on average 1.3891402714932126) internal successors, (921), 662 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 663 states and 921 transitions. [2022-02-21 04:24:06,282 INFO L87 Difference]: Start difference. First operand has 663 states, 663 states have (on average 1.3891402714932126) internal successors, (921), 662 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 663 states and 921 transitions. [2022-02-21 04:24:06,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:06,301 INFO L93 Difference]: Finished difference Result 663 states and 921 transitions. [2022-02-21 04:24:06,301 INFO L276 IsEmpty]: Start isEmpty. Operand 663 states and 921 transitions. [2022-02-21 04:24:06,302 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:06,302 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:06,302 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:06,302 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:06,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 663 states, 663 states have (on average 1.3891402714932126) internal successors, (921), 662 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:06,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 663 states to 663 states and 921 transitions. [2022-02-21 04:24:06,322 INFO L704 BuchiCegarLoop]: Abstraction has 663 states and 921 transitions. [2022-02-21 04:24:06,322 INFO L587 BuchiCegarLoop]: Abstraction has 663 states and 921 transitions. [2022-02-21 04:24:06,322 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:06,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 663 states and 921 transitions. [2022-02-21 04:24:06,324 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 619 [2022-02-21 04:24:06,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:06,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:06,327 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:06,327 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:06,327 INFO L791 eck$LassoCheckResult]: Stem: 13311#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 13274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13083#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13084#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13299#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 13177#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13147#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13148#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13135#L334 assume !(0 == ~M_E~0); 13136#L334-2 assume !(0 == ~T1_E~0); 13233#L339-1 assume !(0 == ~T2_E~0); 13227#L344-1 assume !(0 == ~E_1~0); 13228#L349-1 assume !(0 == ~E_2~0); 13145#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13146#L156 assume !(1 == ~m_pc~0); 13240#L156-2 is_master_triggered_~__retres1~0#1 := 0; 13261#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13249#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13198#L405 assume !(0 != activate_threads_~tmp~1#1); 13182#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13183#L175 assume !(1 == ~t1_pc~0); 13190#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13184#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13185#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13235#L413 assume !(0 != activate_threads_~tmp___0~0#1); 13236#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13301#L194 assume !(1 == ~t2_pc~0); 13226#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13194#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13137#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13124#L421 assume !(0 != activate_threads_~tmp___1~0#1); 13125#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13098#L367 assume !(1 == ~M_E~0); 13099#L367-2 assume !(1 == ~T1_E~0); 13253#L372-1 assume !(1 == ~T2_E~0); 13254#L377-1 assume !(1 == ~E_1~0); 13119#L382-1 assume !(1 == ~E_2~0); 13120#L387-1 assume { :end_inline_reset_delta_events } true; 13200#L528-2 [2022-02-21 04:24:06,331 INFO L793 eck$LassoCheckResult]: Loop: 13200#L528-2 assume !false; 13372#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13367#L309 assume !false; 13366#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13091#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13092#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13246#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13080#L276 assume !(0 != eval_~tmp~0#1); 13082#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13451#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13450#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13449#L334-5 assume !(0 == ~T1_E~0); 13448#L339-3 assume !(0 == ~T2_E~0); 13447#L344-3 assume !(0 == ~E_1~0); 13446#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13445#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13444#L156-9 assume !(1 == ~m_pc~0); 13443#L156-11 is_master_triggered_~__retres1~0#1 := 0; 13442#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13441#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13440#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13438#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13436#L175-9 assume !(1 == ~t1_pc~0); 13434#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 13432#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13430#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13428#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13426#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13424#L194-9 assume 1 == ~t2_pc~0; 13421#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13419#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13417#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13415#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13413#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13410#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13408#L367-5 assume !(1 == ~T1_E~0); 13406#L372-3 assume !(1 == ~T2_E~0); 13404#L377-3 assume !(1 == ~E_1~0); 13402#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13400#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13397#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13394#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13392#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 13389#L547 assume !(0 == start_simulation_~tmp~3#1); 13387#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13385#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13383#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13382#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 13381#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13380#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13379#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 13377#L560 assume !(0 != start_simulation_~tmp___0~1#1); 13200#L528-2 [2022-02-21 04:24:06,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:06,332 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2022-02-21 04:24:06,332 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:06,332 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2026979488] [2022-02-21 04:24:06,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:06,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:06,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:06,339 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:06,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:06,348 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:06,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:06,348 INFO L85 PathProgramCache]: Analyzing trace with hash 618758851, now seen corresponding path program 2 times [2022-02-21 04:24:06,349 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:06,349 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590783625] [2022-02-21 04:24:06,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:06,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:06,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:06,401 INFO L290 TraceCheckUtils]: 0: Hoare triple {15074#true} assume !false; {15074#true} is VALID [2022-02-21 04:24:06,402 INFO L290 TraceCheckUtils]: 1: Hoare triple {15074#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {15074#true} is VALID [2022-02-21 04:24:06,402 INFO L290 TraceCheckUtils]: 2: Hoare triple {15074#true} assume !false; {15074#true} is VALID [2022-02-21 04:24:06,402 INFO L290 TraceCheckUtils]: 3: Hoare triple {15074#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {15074#true} is VALID [2022-02-21 04:24:06,402 INFO L290 TraceCheckUtils]: 4: Hoare triple {15074#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {15076#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} is VALID [2022-02-21 04:24:06,403 INFO L290 TraceCheckUtils]: 5: Hoare triple {15076#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {15077#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:06,403 INFO L290 TraceCheckUtils]: 6: Hoare triple {15077#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {15078#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:06,404 INFO L290 TraceCheckUtils]: 7: Hoare triple {15078#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {15075#false} is VALID [2022-02-21 04:24:06,404 INFO L290 TraceCheckUtils]: 8: Hoare triple {15075#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {15075#false} is VALID [2022-02-21 04:24:06,404 INFO L290 TraceCheckUtils]: 9: Hoare triple {15075#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {15075#false} is VALID [2022-02-21 04:24:06,404 INFO L290 TraceCheckUtils]: 10: Hoare triple {15075#false} assume 0 == ~M_E~0;~M_E~0 := 1; {15075#false} is VALID [2022-02-21 04:24:06,404 INFO L290 TraceCheckUtils]: 11: Hoare triple {15075#false} assume !(0 == ~T1_E~0); {15075#false} is VALID [2022-02-21 04:24:06,405 INFO L290 TraceCheckUtils]: 12: Hoare triple {15075#false} assume !(0 == ~T2_E~0); {15075#false} is VALID [2022-02-21 04:24:06,405 INFO L290 TraceCheckUtils]: 13: Hoare triple {15075#false} assume !(0 == ~E_1~0); {15075#false} is VALID [2022-02-21 04:24:06,405 INFO L290 TraceCheckUtils]: 14: Hoare triple {15075#false} assume 0 == ~E_2~0;~E_2~0 := 1; {15075#false} is VALID [2022-02-21 04:24:06,405 INFO L290 TraceCheckUtils]: 15: Hoare triple {15075#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {15075#false} is VALID [2022-02-21 04:24:06,405 INFO L290 TraceCheckUtils]: 16: Hoare triple {15075#false} assume !(1 == ~m_pc~0); {15075#false} is VALID [2022-02-21 04:24:06,405 INFO L290 TraceCheckUtils]: 17: Hoare triple {15075#false} is_master_triggered_~__retres1~0#1 := 0; {15075#false} is VALID [2022-02-21 04:24:06,406 INFO L290 TraceCheckUtils]: 18: Hoare triple {15075#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {15075#false} is VALID [2022-02-21 04:24:06,406 INFO L290 TraceCheckUtils]: 19: Hoare triple {15075#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {15075#false} is VALID [2022-02-21 04:24:06,406 INFO L290 TraceCheckUtils]: 20: Hoare triple {15075#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {15075#false} is VALID [2022-02-21 04:24:06,406 INFO L290 TraceCheckUtils]: 21: Hoare triple {15075#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {15075#false} is VALID [2022-02-21 04:24:06,406 INFO L290 TraceCheckUtils]: 22: Hoare triple {15075#false} assume !(1 == ~t1_pc~0); {15075#false} is VALID [2022-02-21 04:24:06,406 INFO L290 TraceCheckUtils]: 23: Hoare triple {15075#false} is_transmit1_triggered_~__retres1~1#1 := 0; {15075#false} is VALID [2022-02-21 04:24:06,407 INFO L290 TraceCheckUtils]: 24: Hoare triple {15075#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {15075#false} is VALID [2022-02-21 04:24:06,407 INFO L290 TraceCheckUtils]: 25: Hoare triple {15075#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {15075#false} is VALID [2022-02-21 04:24:06,407 INFO L290 TraceCheckUtils]: 26: Hoare triple {15075#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {15075#false} is VALID [2022-02-21 04:24:06,407 INFO L290 TraceCheckUtils]: 27: Hoare triple {15075#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {15075#false} is VALID [2022-02-21 04:24:06,407 INFO L290 TraceCheckUtils]: 28: Hoare triple {15075#false} assume 1 == ~t2_pc~0; {15075#false} is VALID [2022-02-21 04:24:06,407 INFO L290 TraceCheckUtils]: 29: Hoare triple {15075#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {15075#false} is VALID [2022-02-21 04:24:06,408 INFO L290 TraceCheckUtils]: 30: Hoare triple {15075#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {15075#false} is VALID [2022-02-21 04:24:06,408 INFO L290 TraceCheckUtils]: 31: Hoare triple {15075#false} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {15075#false} is VALID [2022-02-21 04:24:06,408 INFO L290 TraceCheckUtils]: 32: Hoare triple {15075#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {15075#false} is VALID [2022-02-21 04:24:06,408 INFO L290 TraceCheckUtils]: 33: Hoare triple {15075#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {15075#false} is VALID [2022-02-21 04:24:06,408 INFO L290 TraceCheckUtils]: 34: Hoare triple {15075#false} assume 1 == ~M_E~0;~M_E~0 := 2; {15075#false} is VALID [2022-02-21 04:24:06,408 INFO L290 TraceCheckUtils]: 35: Hoare triple {15075#false} assume !(1 == ~T1_E~0); {15075#false} is VALID [2022-02-21 04:24:06,409 INFO L290 TraceCheckUtils]: 36: Hoare triple {15075#false} assume !(1 == ~T2_E~0); {15075#false} is VALID [2022-02-21 04:24:06,409 INFO L290 TraceCheckUtils]: 37: Hoare triple {15075#false} assume !(1 == ~E_1~0); {15075#false} is VALID [2022-02-21 04:24:06,409 INFO L290 TraceCheckUtils]: 38: Hoare triple {15075#false} assume 1 == ~E_2~0;~E_2~0 := 2; {15075#false} is VALID [2022-02-21 04:24:06,409 INFO L290 TraceCheckUtils]: 39: Hoare triple {15075#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {15075#false} is VALID [2022-02-21 04:24:06,409 INFO L290 TraceCheckUtils]: 40: Hoare triple {15075#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {15075#false} is VALID [2022-02-21 04:24:06,409 INFO L290 TraceCheckUtils]: 41: Hoare triple {15075#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {15075#false} is VALID [2022-02-21 04:24:06,410 INFO L290 TraceCheckUtils]: 42: Hoare triple {15075#false} start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {15075#false} is VALID [2022-02-21 04:24:06,410 INFO L290 TraceCheckUtils]: 43: Hoare triple {15075#false} assume !(0 == start_simulation_~tmp~3#1); {15075#false} is VALID [2022-02-21 04:24:06,410 INFO L290 TraceCheckUtils]: 44: Hoare triple {15075#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {15075#false} is VALID [2022-02-21 04:24:06,410 INFO L290 TraceCheckUtils]: 45: Hoare triple {15075#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {15075#false} is VALID [2022-02-21 04:24:06,410 INFO L290 TraceCheckUtils]: 46: Hoare triple {15075#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {15075#false} is VALID [2022-02-21 04:24:06,410 INFO L290 TraceCheckUtils]: 47: Hoare triple {15075#false} stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; {15075#false} is VALID [2022-02-21 04:24:06,411 INFO L290 TraceCheckUtils]: 48: Hoare triple {15075#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {15075#false} is VALID [2022-02-21 04:24:06,411 INFO L290 TraceCheckUtils]: 49: Hoare triple {15075#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {15075#false} is VALID [2022-02-21 04:24:06,411 INFO L290 TraceCheckUtils]: 50: Hoare triple {15075#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {15075#false} is VALID [2022-02-21 04:24:06,411 INFO L290 TraceCheckUtils]: 51: Hoare triple {15075#false} assume !(0 != start_simulation_~tmp___0~1#1); {15075#false} is VALID [2022-02-21 04:24:06,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:06,412 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:06,412 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590783625] [2022-02-21 04:24:06,412 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590783625] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:06,412 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:06,412 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:06,414 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067565779] [2022-02-21 04:24:06,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:06,414 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:06,415 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:06,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:06,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:06,417 INFO L87 Difference]: Start difference. First operand 663 states and 921 transitions. cyclomatic complexity: 261 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:07,021 INFO L93 Difference]: Finished difference Result 1116 states and 1528 transitions. [2022-02-21 04:24:07,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-02-21 04:24:07,021 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,052 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 52 edges. 52 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:07,053 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1116 states and 1528 transitions. [2022-02-21 04:24:07,100 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1067 [2022-02-21 04:24:07,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1116 states to 1116 states and 1528 transitions. [2022-02-21 04:24:07,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1116 [2022-02-21 04:24:07,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1116 [2022-02-21 04:24:07,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1116 states and 1528 transitions. [2022-02-21 04:24:07,149 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:07,149 INFO L681 BuchiCegarLoop]: Abstraction has 1116 states and 1528 transitions. [2022-02-21 04:24:07,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1116 states and 1528 transitions. [2022-02-21 04:24:07,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1116 to 678. [2022-02-21 04:24:07,158 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:07,159 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1116 states and 1528 transitions. Second operand has 678 states, 678 states have (on average 1.3805309734513274) internal successors, (936), 677 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,160 INFO L74 IsIncluded]: Start isIncluded. First operand 1116 states and 1528 transitions. Second operand has 678 states, 678 states have (on average 1.3805309734513274) internal successors, (936), 677 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,162 INFO L87 Difference]: Start difference. First operand 1116 states and 1528 transitions. Second operand has 678 states, 678 states have (on average 1.3805309734513274) internal successors, (936), 677 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:07,205 INFO L93 Difference]: Finished difference Result 1116 states and 1528 transitions. [2022-02-21 04:24:07,205 INFO L276 IsEmpty]: Start isEmpty. Operand 1116 states and 1528 transitions. [2022-02-21 04:24:07,206 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:07,206 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:07,208 INFO L74 IsIncluded]: Start isIncluded. First operand has 678 states, 678 states have (on average 1.3805309734513274) internal successors, (936), 677 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1116 states and 1528 transitions. [2022-02-21 04:24:07,209 INFO L87 Difference]: Start difference. First operand has 678 states, 678 states have (on average 1.3805309734513274) internal successors, (936), 677 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1116 states and 1528 transitions. [2022-02-21 04:24:07,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:07,269 INFO L93 Difference]: Finished difference Result 1116 states and 1528 transitions. [2022-02-21 04:24:07,269 INFO L276 IsEmpty]: Start isEmpty. Operand 1116 states and 1528 transitions. [2022-02-21 04:24:07,271 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:07,271 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:07,271 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:07,271 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:07,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 678 states, 678 states have (on average 1.3805309734513274) internal successors, (936), 677 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678 states to 678 states and 936 transitions. [2022-02-21 04:24:07,291 INFO L704 BuchiCegarLoop]: Abstraction has 678 states and 936 transitions. [2022-02-21 04:24:07,291 INFO L587 BuchiCegarLoop]: Abstraction has 678 states and 936 transitions. [2022-02-21 04:24:07,291 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:07,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 678 states and 936 transitions. [2022-02-21 04:24:07,294 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 634 [2022-02-21 04:24:07,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:07,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:07,295 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:07,295 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:07,295 INFO L791 eck$LassoCheckResult]: Stem: 16449#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 16410#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 16205#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16206#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16430#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 16302#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16273#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16274#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16259#L334 assume !(0 == ~M_E~0); 16260#L334-2 assume !(0 == ~T1_E~0); 16358#L339-1 assume !(0 == ~T2_E~0); 16350#L344-1 assume !(0 == ~E_1~0); 16351#L349-1 assume !(0 == ~E_2~0); 16271#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16272#L156 assume !(1 == ~m_pc~0); 16366#L156-2 is_master_triggered_~__retres1~0#1 := 0; 16388#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16378#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16324#L405 assume !(0 != activate_threads_~tmp~1#1); 16307#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16308#L175 assume !(1 == ~t1_pc~0); 16315#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16309#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16310#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16361#L413 assume !(0 != activate_threads_~tmp___0~0#1); 16362#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16433#L194 assume !(1 == ~t2_pc~0); 16348#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16319#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16261#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16247#L421 assume !(0 != activate_threads_~tmp___1~0#1); 16248#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16220#L367 assume !(1 == ~M_E~0); 16221#L367-2 assume !(1 == ~T1_E~0); 16382#L372-1 assume !(1 == ~T2_E~0); 16383#L377-1 assume !(1 == ~E_1~0); 16242#L382-1 assume !(1 == ~E_2~0); 16243#L387-1 assume { :end_inline_reset_delta_events } true; 16234#L528-2 [2022-02-21 04:24:07,295 INFO L793 eck$LassoCheckResult]: Loop: 16234#L528-2 assume !false; 16349#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16791#L309 assume !false; 16689#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16687#L244 assume !(0 == ~m_st~0); 16688#L248 assume !(0 == ~t1_st~0); 16685#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 16686#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16644#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16645#L276 assume !(0 != eval_~tmp~0#1); 16682#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16681#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16680#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16679#L334-5 assume !(0 == ~T1_E~0); 16678#L339-3 assume !(0 == ~T2_E~0); 16677#L344-3 assume !(0 == ~E_1~0); 16675#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16257#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16258#L156-9 assume !(1 == ~m_pc~0); 16209#L156-11 is_master_triggered_~__retres1~0#1 := 0; 16210#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16425#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16426#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16235#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16236#L175-9 assume !(1 == ~t1_pc~0); 16391#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 16392#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16359#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16360#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16400#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16401#L194-9 assume 1 == ~t2_pc~0; 16327#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16250#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16328#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16329#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16395#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16396#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16211#L367-5 assume !(1 == ~T1_E~0); 16212#L372-3 assume !(1 == ~T2_E~0); 16231#L377-3 assume !(1 == ~E_1~0); 16232#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16356#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16357#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16841#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16838#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 16835#L547 assume !(0 == start_simulation_~tmp~3#1); 16832#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16404#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16291#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16292#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 16269#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16270#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16287#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 16233#L560 assume !(0 != start_simulation_~tmp___0~1#1); 16234#L528-2 [2022-02-21 04:24:07,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:07,296 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 3 times [2022-02-21 04:24:07,296 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:07,296 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966116945] [2022-02-21 04:24:07,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:07,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:07,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:07,303 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:07,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:07,311 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:07,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:07,312 INFO L85 PathProgramCache]: Analyzing trace with hash 2132958556, now seen corresponding path program 1 times [2022-02-21 04:24:07,312 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:07,312 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400044021] [2022-02-21 04:24:07,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:07,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:07,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:07,365 INFO L290 TraceCheckUtils]: 0: Hoare triple {19118#true} assume !false; {19118#true} is VALID [2022-02-21 04:24:07,365 INFO L290 TraceCheckUtils]: 1: Hoare triple {19118#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {19118#true} is VALID [2022-02-21 04:24:07,365 INFO L290 TraceCheckUtils]: 2: Hoare triple {19118#true} assume !false; {19118#true} is VALID [2022-02-21 04:24:07,366 INFO L290 TraceCheckUtils]: 3: Hoare triple {19118#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {19118#true} is VALID [2022-02-21 04:24:07,366 INFO L290 TraceCheckUtils]: 4: Hoare triple {19118#true} assume !(0 == ~m_st~0); {19118#true} is VALID [2022-02-21 04:24:07,366 INFO L290 TraceCheckUtils]: 5: Hoare triple {19118#true} assume !(0 == ~t1_st~0); {19118#true} is VALID [2022-02-21 04:24:07,366 INFO L290 TraceCheckUtils]: 6: Hoare triple {19118#true} assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; {19118#true} is VALID [2022-02-21 04:24:07,366 INFO L290 TraceCheckUtils]: 7: Hoare triple {19118#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {19118#true} is VALID [2022-02-21 04:24:07,366 INFO L290 TraceCheckUtils]: 8: Hoare triple {19118#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {19118#true} is VALID [2022-02-21 04:24:07,366 INFO L290 TraceCheckUtils]: 9: Hoare triple {19118#true} assume !(0 != eval_~tmp~0#1); {19118#true} is VALID [2022-02-21 04:24:07,367 INFO L290 TraceCheckUtils]: 10: Hoare triple {19118#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {19118#true} is VALID [2022-02-21 04:24:07,367 INFO L290 TraceCheckUtils]: 11: Hoare triple {19118#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {19118#true} is VALID [2022-02-21 04:24:07,367 INFO L290 TraceCheckUtils]: 12: Hoare triple {19118#true} assume 0 == ~M_E~0;~M_E~0 := 1; {19118#true} is VALID [2022-02-21 04:24:07,367 INFO L290 TraceCheckUtils]: 13: Hoare triple {19118#true} assume !(0 == ~T1_E~0); {19118#true} is VALID [2022-02-21 04:24:07,367 INFO L290 TraceCheckUtils]: 14: Hoare triple {19118#true} assume !(0 == ~T2_E~0); {19118#true} is VALID [2022-02-21 04:24:07,367 INFO L290 TraceCheckUtils]: 15: Hoare triple {19118#true} assume !(0 == ~E_1~0); {19118#true} is VALID [2022-02-21 04:24:07,367 INFO L290 TraceCheckUtils]: 16: Hoare triple {19118#true} assume 0 == ~E_2~0;~E_2~0 := 1; {19118#true} is VALID [2022-02-21 04:24:07,368 INFO L290 TraceCheckUtils]: 17: Hoare triple {19118#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {19118#true} is VALID [2022-02-21 04:24:07,368 INFO L290 TraceCheckUtils]: 18: Hoare triple {19118#true} assume !(1 == ~m_pc~0); {19118#true} is VALID [2022-02-21 04:24:07,368 INFO L290 TraceCheckUtils]: 19: Hoare triple {19118#true} is_master_triggered_~__retres1~0#1 := 0; {19120#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is VALID [2022-02-21 04:24:07,369 INFO L290 TraceCheckUtils]: 20: Hoare triple {19120#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {19121#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} is VALID [2022-02-21 04:24:07,369 INFO L290 TraceCheckUtils]: 21: Hoare triple {19121#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {19122#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} is VALID [2022-02-21 04:24:07,370 INFO L290 TraceCheckUtils]: 22: Hoare triple {19122#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {19119#false} is VALID [2022-02-21 04:24:07,370 INFO L290 TraceCheckUtils]: 23: Hoare triple {19119#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {19119#false} is VALID [2022-02-21 04:24:07,370 INFO L290 TraceCheckUtils]: 24: Hoare triple {19119#false} assume !(1 == ~t1_pc~0); {19119#false} is VALID [2022-02-21 04:24:07,370 INFO L290 TraceCheckUtils]: 25: Hoare triple {19119#false} is_transmit1_triggered_~__retres1~1#1 := 0; {19119#false} is VALID [2022-02-21 04:24:07,370 INFO L290 TraceCheckUtils]: 26: Hoare triple {19119#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {19119#false} is VALID [2022-02-21 04:24:07,370 INFO L290 TraceCheckUtils]: 27: Hoare triple {19119#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {19119#false} is VALID [2022-02-21 04:24:07,370 INFO L290 TraceCheckUtils]: 28: Hoare triple {19119#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {19119#false} is VALID [2022-02-21 04:24:07,371 INFO L290 TraceCheckUtils]: 29: Hoare triple {19119#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {19119#false} is VALID [2022-02-21 04:24:07,371 INFO L290 TraceCheckUtils]: 30: Hoare triple {19119#false} assume 1 == ~t2_pc~0; {19119#false} is VALID [2022-02-21 04:24:07,371 INFO L290 TraceCheckUtils]: 31: Hoare triple {19119#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {19119#false} is VALID [2022-02-21 04:24:07,371 INFO L290 TraceCheckUtils]: 32: Hoare triple {19119#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {19119#false} is VALID [2022-02-21 04:24:07,371 INFO L290 TraceCheckUtils]: 33: Hoare triple {19119#false} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {19119#false} is VALID [2022-02-21 04:24:07,371 INFO L290 TraceCheckUtils]: 34: Hoare triple {19119#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {19119#false} is VALID [2022-02-21 04:24:07,371 INFO L290 TraceCheckUtils]: 35: Hoare triple {19119#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {19119#false} is VALID [2022-02-21 04:24:07,372 INFO L290 TraceCheckUtils]: 36: Hoare triple {19119#false} assume 1 == ~M_E~0;~M_E~0 := 2; {19119#false} is VALID [2022-02-21 04:24:07,372 INFO L290 TraceCheckUtils]: 37: Hoare triple {19119#false} assume !(1 == ~T1_E~0); {19119#false} is VALID [2022-02-21 04:24:07,372 INFO L290 TraceCheckUtils]: 38: Hoare triple {19119#false} assume !(1 == ~T2_E~0); {19119#false} is VALID [2022-02-21 04:24:07,372 INFO L290 TraceCheckUtils]: 39: Hoare triple {19119#false} assume !(1 == ~E_1~0); {19119#false} is VALID [2022-02-21 04:24:07,372 INFO L290 TraceCheckUtils]: 40: Hoare triple {19119#false} assume 1 == ~E_2~0;~E_2~0 := 2; {19119#false} is VALID [2022-02-21 04:24:07,372 INFO L290 TraceCheckUtils]: 41: Hoare triple {19119#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {19119#false} is VALID [2022-02-21 04:24:07,372 INFO L290 TraceCheckUtils]: 42: Hoare triple {19119#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {19119#false} is VALID [2022-02-21 04:24:07,373 INFO L290 TraceCheckUtils]: 43: Hoare triple {19119#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {19119#false} is VALID [2022-02-21 04:24:07,373 INFO L290 TraceCheckUtils]: 44: Hoare triple {19119#false} start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {19119#false} is VALID [2022-02-21 04:24:07,373 INFO L290 TraceCheckUtils]: 45: Hoare triple {19119#false} assume !(0 == start_simulation_~tmp~3#1); {19119#false} is VALID [2022-02-21 04:24:07,373 INFO L290 TraceCheckUtils]: 46: Hoare triple {19119#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {19119#false} is VALID [2022-02-21 04:24:07,373 INFO L290 TraceCheckUtils]: 47: Hoare triple {19119#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {19119#false} is VALID [2022-02-21 04:24:07,373 INFO L290 TraceCheckUtils]: 48: Hoare triple {19119#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {19119#false} is VALID [2022-02-21 04:24:07,373 INFO L290 TraceCheckUtils]: 49: Hoare triple {19119#false} stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; {19119#false} is VALID [2022-02-21 04:24:07,374 INFO L290 TraceCheckUtils]: 50: Hoare triple {19119#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {19119#false} is VALID [2022-02-21 04:24:07,374 INFO L290 TraceCheckUtils]: 51: Hoare triple {19119#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {19119#false} is VALID [2022-02-21 04:24:07,374 INFO L290 TraceCheckUtils]: 52: Hoare triple {19119#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {19119#false} is VALID [2022-02-21 04:24:07,374 INFO L290 TraceCheckUtils]: 53: Hoare triple {19119#false} assume !(0 != start_simulation_~tmp___0~1#1); {19119#false} is VALID [2022-02-21 04:24:07,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:07,374 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:07,375 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400044021] [2022-02-21 04:24:07,375 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400044021] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:07,375 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:07,375 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:07,375 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536319056] [2022-02-21 04:24:07,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:07,376 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:07,376 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:07,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:07,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:07,377 INFO L87 Difference]: Start difference. First operand 678 states and 936 transitions. cyclomatic complexity: 261 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:08,408 INFO L93 Difference]: Finished difference Result 1640 states and 2247 transitions. [2022-02-21 04:24:08,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:24:08,409 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,442 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:08,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1640 states and 2247 transitions. [2022-02-21 04:24:08,507 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1596 [2022-02-21 04:24:08,591 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1640 states to 1640 states and 2247 transitions. [2022-02-21 04:24:08,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1640 [2022-02-21 04:24:08,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1640 [2022-02-21 04:24:08,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1640 states and 2247 transitions. [2022-02-21 04:24:08,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:08,593 INFO L681 BuchiCegarLoop]: Abstraction has 1640 states and 2247 transitions. [2022-02-21 04:24:08,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1640 states and 2247 transitions. [2022-02-21 04:24:08,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1640 to 714. [2022-02-21 04:24:08,604 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:08,606 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1640 states and 2247 transitions. Second operand has 714 states, 714 states have (on average 1.3571428571428572) internal successors, (969), 713 states have internal predecessors, (969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,607 INFO L74 IsIncluded]: Start isIncluded. First operand 1640 states and 2247 transitions. Second operand has 714 states, 714 states have (on average 1.3571428571428572) internal successors, (969), 713 states have internal predecessors, (969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,608 INFO L87 Difference]: Start difference. First operand 1640 states and 2247 transitions. Second operand has 714 states, 714 states have (on average 1.3571428571428572) internal successors, (969), 713 states have internal predecessors, (969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:08,686 INFO L93 Difference]: Finished difference Result 1640 states and 2247 transitions. [2022-02-21 04:24:08,686 INFO L276 IsEmpty]: Start isEmpty. Operand 1640 states and 2247 transitions. [2022-02-21 04:24:08,688 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:08,688 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:08,690 INFO L74 IsIncluded]: Start isIncluded. First operand has 714 states, 714 states have (on average 1.3571428571428572) internal successors, (969), 713 states have internal predecessors, (969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1640 states and 2247 transitions. [2022-02-21 04:24:08,691 INFO L87 Difference]: Start difference. First operand has 714 states, 714 states have (on average 1.3571428571428572) internal successors, (969), 713 states have internal predecessors, (969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1640 states and 2247 transitions. [2022-02-21 04:24:08,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:08,779 INFO L93 Difference]: Finished difference Result 1640 states and 2247 transitions. [2022-02-21 04:24:08,779 INFO L276 IsEmpty]: Start isEmpty. Operand 1640 states and 2247 transitions. [2022-02-21 04:24:08,781 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:08,781 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:08,781 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:08,781 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:08,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 714 states, 714 states have (on average 1.3571428571428572) internal successors, (969), 713 states have internal predecessors, (969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 714 states to 714 states and 969 transitions. [2022-02-21 04:24:08,801 INFO L704 BuchiCegarLoop]: Abstraction has 714 states and 969 transitions. [2022-02-21 04:24:08,801 INFO L587 BuchiCegarLoop]: Abstraction has 714 states and 969 transitions. [2022-02-21 04:24:08,801 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:08,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 714 states and 969 transitions. [2022-02-21 04:24:08,804 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 670 [2022-02-21 04:24:08,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:08,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:08,808 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:08,808 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:08,808 INFO L791 eck$LassoCheckResult]: Stem: 21028#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 20979#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 20770#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20771#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21008#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 20864#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20835#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20836#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20823#L334 assume !(0 == ~M_E~0); 20824#L334-2 assume !(0 == ~T1_E~0); 20930#L339-1 assume !(0 == ~T2_E~0); 20924#L344-1 assume !(0 == ~E_1~0); 20925#L349-1 assume !(0 == ~E_2~0); 20833#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20834#L156 assume !(1 == ~m_pc~0); 20938#L156-2 is_master_triggered_~__retres1~0#1 := 0; 20962#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20949#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 20889#L405 assume !(0 != activate_threads_~tmp~1#1); 20869#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20870#L175 assume !(1 == ~t1_pc~0); 20879#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20871#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20872#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20932#L413 assume !(0 != activate_threads_~tmp___0~0#1); 20935#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21011#L194 assume !(1 == ~t2_pc~0); 20922#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20886#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20827#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20812#L421 assume !(0 != activate_threads_~tmp___1~0#1); 20813#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20785#L367 assume !(1 == ~M_E~0); 20786#L367-2 assume !(1 == ~T1_E~0); 20954#L372-1 assume !(1 == ~T2_E~0); 20955#L377-1 assume !(1 == ~E_1~0); 20806#L382-1 assume !(1 == ~E_2~0); 20807#L387-1 assume { :end_inline_reset_delta_events } true; 20891#L528-2 [2022-02-21 04:24:08,808 INFO L793 eck$LassoCheckResult]: Loop: 20891#L528-2 assume !false; 21058#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21053#L309 assume !false; 21052#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21050#L244 assume !(0 == ~m_st~0); 21051#L248 assume !(0 == ~t1_st~0); 21048#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 21049#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21044#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21045#L276 assume !(0 != eval_~tmp~0#1); 21137#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21136#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21135#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21134#L334-5 assume !(0 == ~T1_E~0); 21133#L339-3 assume !(0 == ~T2_E~0); 21132#L344-3 assume !(0 == ~E_1~0); 21131#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21130#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21129#L156-9 assume !(1 == ~m_pc~0); 21128#L156-11 is_master_triggered_~__retres1~0#1 := 0; 21127#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21126#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21125#L405-9 assume !(0 != activate_threads_~tmp~1#1); 21123#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21121#L175-9 assume !(1 == ~t1_pc~0); 21119#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 21117#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21115#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21113#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21111#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21109#L194-9 assume 1 == ~t2_pc~0; 21106#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21104#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21102#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21100#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21098#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21095#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21093#L367-5 assume !(1 == ~T1_E~0); 21091#L372-3 assume !(1 == ~T2_E~0); 21089#L377-3 assume !(1 == ~E_1~0); 21087#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21085#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21082#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 21079#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21077#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 21074#L547 assume !(0 == start_simulation_~tmp~3#1); 21072#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21070#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 21068#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21067#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 21066#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21065#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21064#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 21062#L560 assume !(0 != start_simulation_~tmp___0~1#1); 20891#L528-2 [2022-02-21 04:24:08,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:08,809 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 4 times [2022-02-21 04:24:08,809 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:08,810 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045960301] [2022-02-21 04:24:08,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:08,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:08,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:08,820 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:08,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:08,828 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:08,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:08,829 INFO L85 PathProgramCache]: Analyzing trace with hash -1887249126, now seen corresponding path program 1 times [2022-02-21 04:24:08,829 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:08,829 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539698807] [2022-02-21 04:24:08,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:08,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:08,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:08,846 INFO L290 TraceCheckUtils]: 0: Hoare triple {24767#true} assume !false; {24767#true} is VALID [2022-02-21 04:24:08,846 INFO L290 TraceCheckUtils]: 1: Hoare triple {24767#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {24767#true} is VALID [2022-02-21 04:24:08,846 INFO L290 TraceCheckUtils]: 2: Hoare triple {24767#true} assume !false; {24767#true} is VALID [2022-02-21 04:24:08,847 INFO L290 TraceCheckUtils]: 3: Hoare triple {24767#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {24767#true} is VALID [2022-02-21 04:24:08,847 INFO L290 TraceCheckUtils]: 4: Hoare triple {24767#true} assume !(0 == ~m_st~0); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,847 INFO L290 TraceCheckUtils]: 5: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(0 == ~t1_st~0); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,848 INFO L290 TraceCheckUtils]: 6: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,848 INFO L290 TraceCheckUtils]: 7: Hoare triple {24769#(not (= ~m_st~0 0))} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,848 INFO L290 TraceCheckUtils]: 8: Hoare triple {24769#(not (= ~m_st~0 0))} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,849 INFO L290 TraceCheckUtils]: 9: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(0 != eval_~tmp~0#1); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,849 INFO L290 TraceCheckUtils]: 10: Hoare triple {24769#(not (= ~m_st~0 0))} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,849 INFO L290 TraceCheckUtils]: 11: Hoare triple {24769#(not (= ~m_st~0 0))} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,850 INFO L290 TraceCheckUtils]: 12: Hoare triple {24769#(not (= ~m_st~0 0))} assume 0 == ~M_E~0;~M_E~0 := 1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,850 INFO L290 TraceCheckUtils]: 13: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(0 == ~T1_E~0); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,850 INFO L290 TraceCheckUtils]: 14: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(0 == ~T2_E~0); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,851 INFO L290 TraceCheckUtils]: 15: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(0 == ~E_1~0); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,851 INFO L290 TraceCheckUtils]: 16: Hoare triple {24769#(not (= ~m_st~0 0))} assume 0 == ~E_2~0;~E_2~0 := 1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,851 INFO L290 TraceCheckUtils]: 17: Hoare triple {24769#(not (= ~m_st~0 0))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,852 INFO L290 TraceCheckUtils]: 18: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(1 == ~m_pc~0); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,852 INFO L290 TraceCheckUtils]: 19: Hoare triple {24769#(not (= ~m_st~0 0))} is_master_triggered_~__retres1~0#1 := 0; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,852 INFO L290 TraceCheckUtils]: 20: Hoare triple {24769#(not (= ~m_st~0 0))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,853 INFO L290 TraceCheckUtils]: 21: Hoare triple {24769#(not (= ~m_st~0 0))} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,853 INFO L290 TraceCheckUtils]: 22: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(0 != activate_threads_~tmp~1#1); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,853 INFO L290 TraceCheckUtils]: 23: Hoare triple {24769#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,854 INFO L290 TraceCheckUtils]: 24: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(1 == ~t1_pc~0); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,854 INFO L290 TraceCheckUtils]: 25: Hoare triple {24769#(not (= ~m_st~0 0))} is_transmit1_triggered_~__retres1~1#1 := 0; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,854 INFO L290 TraceCheckUtils]: 26: Hoare triple {24769#(not (= ~m_st~0 0))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,855 INFO L290 TraceCheckUtils]: 27: Hoare triple {24769#(not (= ~m_st~0 0))} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,855 INFO L290 TraceCheckUtils]: 28: Hoare triple {24769#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,855 INFO L290 TraceCheckUtils]: 29: Hoare triple {24769#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,856 INFO L290 TraceCheckUtils]: 30: Hoare triple {24769#(not (= ~m_st~0 0))} assume 1 == ~t2_pc~0; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,856 INFO L290 TraceCheckUtils]: 31: Hoare triple {24769#(not (= ~m_st~0 0))} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,856 INFO L290 TraceCheckUtils]: 32: Hoare triple {24769#(not (= ~m_st~0 0))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,857 INFO L290 TraceCheckUtils]: 33: Hoare triple {24769#(not (= ~m_st~0 0))} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,857 INFO L290 TraceCheckUtils]: 34: Hoare triple {24769#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,857 INFO L290 TraceCheckUtils]: 35: Hoare triple {24769#(not (= ~m_st~0 0))} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,858 INFO L290 TraceCheckUtils]: 36: Hoare triple {24769#(not (= ~m_st~0 0))} assume 1 == ~M_E~0;~M_E~0 := 2; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,858 INFO L290 TraceCheckUtils]: 37: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(1 == ~T1_E~0); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,858 INFO L290 TraceCheckUtils]: 38: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(1 == ~T2_E~0); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,859 INFO L290 TraceCheckUtils]: 39: Hoare triple {24769#(not (= ~m_st~0 0))} assume !(1 == ~E_1~0); {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,859 INFO L290 TraceCheckUtils]: 40: Hoare triple {24769#(not (= ~m_st~0 0))} assume 1 == ~E_2~0;~E_2~0 := 2; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,859 INFO L290 TraceCheckUtils]: 41: Hoare triple {24769#(not (= ~m_st~0 0))} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {24769#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:08,860 INFO L290 TraceCheckUtils]: 42: Hoare triple {24769#(not (= ~m_st~0 0))} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {24768#false} is VALID [2022-02-21 04:24:08,860 INFO L290 TraceCheckUtils]: 43: Hoare triple {24768#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {24768#false} is VALID [2022-02-21 04:24:08,860 INFO L290 TraceCheckUtils]: 44: Hoare triple {24768#false} start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {24768#false} is VALID [2022-02-21 04:24:08,860 INFO L290 TraceCheckUtils]: 45: Hoare triple {24768#false} assume !(0 == start_simulation_~tmp~3#1); {24768#false} is VALID [2022-02-21 04:24:08,860 INFO L290 TraceCheckUtils]: 46: Hoare triple {24768#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {24768#false} is VALID [2022-02-21 04:24:08,860 INFO L290 TraceCheckUtils]: 47: Hoare triple {24768#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {24768#false} is VALID [2022-02-21 04:24:08,860 INFO L290 TraceCheckUtils]: 48: Hoare triple {24768#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {24768#false} is VALID [2022-02-21 04:24:08,861 INFO L290 TraceCheckUtils]: 49: Hoare triple {24768#false} stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; {24768#false} is VALID [2022-02-21 04:24:08,861 INFO L290 TraceCheckUtils]: 50: Hoare triple {24768#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {24768#false} is VALID [2022-02-21 04:24:08,861 INFO L290 TraceCheckUtils]: 51: Hoare triple {24768#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {24768#false} is VALID [2022-02-21 04:24:08,861 INFO L290 TraceCheckUtils]: 52: Hoare triple {24768#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {24768#false} is VALID [2022-02-21 04:24:08,861 INFO L290 TraceCheckUtils]: 53: Hoare triple {24768#false} assume !(0 != start_simulation_~tmp___0~1#1); {24768#false} is VALID [2022-02-21 04:24:08,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:08,862 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:08,862 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539698807] [2022-02-21 04:24:08,862 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539698807] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:08,862 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:08,862 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:08,862 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765488675] [2022-02-21 04:24:08,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:08,863 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:08,863 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:08,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:08,864 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:08,864 INFO L87 Difference]: Start difference. First operand 714 states and 969 transitions. cyclomatic complexity: 258 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:09,157 INFO L93 Difference]: Finished difference Result 1157 states and 1543 transitions. [2022-02-21 04:24:09,157 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:09,157 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,200 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:09,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1157 states and 1543 transitions. [2022-02-21 04:24:09,250 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1111 [2022-02-21 04:24:09,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1157 states to 1157 states and 1543 transitions. [2022-02-21 04:24:09,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1157 [2022-02-21 04:24:09,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1157 [2022-02-21 04:24:09,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1157 states and 1543 transitions. [2022-02-21 04:24:09,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:09,282 INFO L681 BuchiCegarLoop]: Abstraction has 1157 states and 1543 transitions. [2022-02-21 04:24:09,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1157 states and 1543 transitions. [2022-02-21 04:24:09,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1157 to 1122. [2022-02-21 04:24:09,294 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:09,296 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1157 states and 1543 transitions. Second operand has 1122 states, 1122 states have (on average 1.3351158645276293) internal successors, (1498), 1121 states have internal predecessors, (1498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,297 INFO L74 IsIncluded]: Start isIncluded. First operand 1157 states and 1543 transitions. Second operand has 1122 states, 1122 states have (on average 1.3351158645276293) internal successors, (1498), 1121 states have internal predecessors, (1498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,298 INFO L87 Difference]: Start difference. First operand 1157 states and 1543 transitions. Second operand has 1122 states, 1122 states have (on average 1.3351158645276293) internal successors, (1498), 1121 states have internal predecessors, (1498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:09,338 INFO L93 Difference]: Finished difference Result 1157 states and 1543 transitions. [2022-02-21 04:24:09,338 INFO L276 IsEmpty]: Start isEmpty. Operand 1157 states and 1543 transitions. [2022-02-21 04:24:09,339 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:09,340 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:09,341 INFO L74 IsIncluded]: Start isIncluded. First operand has 1122 states, 1122 states have (on average 1.3351158645276293) internal successors, (1498), 1121 states have internal predecessors, (1498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1157 states and 1543 transitions. [2022-02-21 04:24:09,342 INFO L87 Difference]: Start difference. First operand has 1122 states, 1122 states have (on average 1.3351158645276293) internal successors, (1498), 1121 states have internal predecessors, (1498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1157 states and 1543 transitions. [2022-02-21 04:24:09,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:09,376 INFO L93 Difference]: Finished difference Result 1157 states and 1543 transitions. [2022-02-21 04:24:09,376 INFO L276 IsEmpty]: Start isEmpty. Operand 1157 states and 1543 transitions. [2022-02-21 04:24:09,378 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:09,378 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:09,378 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:09,378 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:09,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1122 states, 1122 states have (on average 1.3351158645276293) internal successors, (1498), 1121 states have internal predecessors, (1498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1122 states to 1122 states and 1498 transitions. [2022-02-21 04:24:09,408 INFO L704 BuchiCegarLoop]: Abstraction has 1122 states and 1498 transitions. [2022-02-21 04:24:09,408 INFO L587 BuchiCegarLoop]: Abstraction has 1122 states and 1498 transitions. [2022-02-21 04:24:09,408 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:24:09,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1122 states and 1498 transitions. [2022-02-21 04:24:09,411 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1076 [2022-02-21 04:24:09,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:09,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:09,412 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:09,412 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:09,412 INFO L791 eck$LassoCheckResult]: Stem: 26165#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 26132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 25929#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25930#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26152#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 26021#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25992#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25993#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25980#L334 assume !(0 == ~M_E~0); 25981#L334-2 assume !(0 == ~T1_E~0); 26079#L339-1 assume !(0 == ~T2_E~0); 26073#L344-1 assume !(0 == ~E_1~0); 26074#L349-1 assume !(0 == ~E_2~0); 25990#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25991#L156 assume !(1 == ~m_pc~0); 26088#L156-2 is_master_triggered_~__retres1~0#1 := 0; 26114#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26102#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 26044#L405 assume !(0 != activate_threads_~tmp~1#1); 26026#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26027#L175 assume !(1 == ~t1_pc~0); 26034#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26028#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26029#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26082#L413 assume !(0 != activate_threads_~tmp___0~0#1); 26083#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26156#L194 assume !(1 == ~t2_pc~0); 26072#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26038#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25982#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25969#L421 assume !(0 != activate_threads_~tmp___1~0#1); 25970#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25943#L367 assume !(1 == ~M_E~0); 25944#L367-2 assume !(1 == ~T1_E~0); 26107#L372-1 assume !(1 == ~T2_E~0); 26108#L377-1 assume !(1 == ~E_1~0); 25964#L382-1 assume !(1 == ~E_2~0); 25965#L387-1 assume { :end_inline_reset_delta_events } true; 26046#L528-2 assume !false; 26192#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26187#L309 [2022-02-21 04:24:09,412 INFO L793 eck$LassoCheckResult]: Loop: 26187#L309 assume !false; 26186#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 26184#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 26183#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 26182#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26181#L276 assume 0 != eval_~tmp~0#1; 26179#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 26177#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 26178#L281 assume !(0 == ~t1_st~0); 26191#L295 assume !(0 == ~t2_st~0); 26187#L309 [2022-02-21 04:24:09,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:09,413 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 1 times [2022-02-21 04:24:09,413 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:09,413 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857886169] [2022-02-21 04:24:09,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:09,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:09,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:09,420 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:09,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:09,428 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:09,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:09,429 INFO L85 PathProgramCache]: Analyzing trace with hash 1417539670, now seen corresponding path program 1 times [2022-02-21 04:24:09,429 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:09,429 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909640559] [2022-02-21 04:24:09,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:09,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:09,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:09,432 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:09,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:09,435 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:09,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:09,435 INFO L85 PathProgramCache]: Analyzing trace with hash -1345054088, now seen corresponding path program 1 times [2022-02-21 04:24:09,436 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:09,436 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297099080] [2022-02-21 04:24:09,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:09,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:09,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:09,456 INFO L290 TraceCheckUtils]: 0: Hoare triple {29370#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; {29370#true} is VALID [2022-02-21 04:24:09,456 INFO L290 TraceCheckUtils]: 1: Hoare triple {29370#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {29370#true} is VALID [2022-02-21 04:24:09,456 INFO L290 TraceCheckUtils]: 2: Hoare triple {29370#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {29370#true} is VALID [2022-02-21 04:24:09,456 INFO L290 TraceCheckUtils]: 3: Hoare triple {29370#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {29370#true} is VALID [2022-02-21 04:24:09,456 INFO L290 TraceCheckUtils]: 4: Hoare triple {29370#true} assume 1 == ~m_i~0;~m_st~0 := 0; {29370#true} is VALID [2022-02-21 04:24:09,456 INFO L290 TraceCheckUtils]: 5: Hoare triple {29370#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,457 INFO L290 TraceCheckUtils]: 6: Hoare triple {29372#(= ~t1_st~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,457 INFO L290 TraceCheckUtils]: 7: Hoare triple {29372#(= ~t1_st~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,457 INFO L290 TraceCheckUtils]: 8: Hoare triple {29372#(= ~t1_st~0 0)} assume !(0 == ~M_E~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,458 INFO L290 TraceCheckUtils]: 9: Hoare triple {29372#(= ~t1_st~0 0)} assume !(0 == ~T1_E~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,458 INFO L290 TraceCheckUtils]: 10: Hoare triple {29372#(= ~t1_st~0 0)} assume !(0 == ~T2_E~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,458 INFO L290 TraceCheckUtils]: 11: Hoare triple {29372#(= ~t1_st~0 0)} assume !(0 == ~E_1~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,459 INFO L290 TraceCheckUtils]: 12: Hoare triple {29372#(= ~t1_st~0 0)} assume !(0 == ~E_2~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,459 INFO L290 TraceCheckUtils]: 13: Hoare triple {29372#(= ~t1_st~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,459 INFO L290 TraceCheckUtils]: 14: Hoare triple {29372#(= ~t1_st~0 0)} assume !(1 == ~m_pc~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,460 INFO L290 TraceCheckUtils]: 15: Hoare triple {29372#(= ~t1_st~0 0)} is_master_triggered_~__retres1~0#1 := 0; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,460 INFO L290 TraceCheckUtils]: 16: Hoare triple {29372#(= ~t1_st~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,460 INFO L290 TraceCheckUtils]: 17: Hoare triple {29372#(= ~t1_st~0 0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,460 INFO L290 TraceCheckUtils]: 18: Hoare triple {29372#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp~1#1); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,461 INFO L290 TraceCheckUtils]: 19: Hoare triple {29372#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,461 INFO L290 TraceCheckUtils]: 20: Hoare triple {29372#(= ~t1_st~0 0)} assume !(1 == ~t1_pc~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,461 INFO L290 TraceCheckUtils]: 21: Hoare triple {29372#(= ~t1_st~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,462 INFO L290 TraceCheckUtils]: 22: Hoare triple {29372#(= ~t1_st~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,462 INFO L290 TraceCheckUtils]: 23: Hoare triple {29372#(= ~t1_st~0 0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,462 INFO L290 TraceCheckUtils]: 24: Hoare triple {29372#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,463 INFO L290 TraceCheckUtils]: 25: Hoare triple {29372#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,463 INFO L290 TraceCheckUtils]: 26: Hoare triple {29372#(= ~t1_st~0 0)} assume !(1 == ~t2_pc~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,463 INFO L290 TraceCheckUtils]: 27: Hoare triple {29372#(= ~t1_st~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,464 INFO L290 TraceCheckUtils]: 28: Hoare triple {29372#(= ~t1_st~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,464 INFO L290 TraceCheckUtils]: 29: Hoare triple {29372#(= ~t1_st~0 0)} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,464 INFO L290 TraceCheckUtils]: 30: Hoare triple {29372#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,465 INFO L290 TraceCheckUtils]: 31: Hoare triple {29372#(= ~t1_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,465 INFO L290 TraceCheckUtils]: 32: Hoare triple {29372#(= ~t1_st~0 0)} assume !(1 == ~M_E~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,465 INFO L290 TraceCheckUtils]: 33: Hoare triple {29372#(= ~t1_st~0 0)} assume !(1 == ~T1_E~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,465 INFO L290 TraceCheckUtils]: 34: Hoare triple {29372#(= ~t1_st~0 0)} assume !(1 == ~T2_E~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,466 INFO L290 TraceCheckUtils]: 35: Hoare triple {29372#(= ~t1_st~0 0)} assume !(1 == ~E_1~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,466 INFO L290 TraceCheckUtils]: 36: Hoare triple {29372#(= ~t1_st~0 0)} assume !(1 == ~E_2~0); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,466 INFO L290 TraceCheckUtils]: 37: Hoare triple {29372#(= ~t1_st~0 0)} assume { :end_inline_reset_delta_events } true; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,467 INFO L290 TraceCheckUtils]: 38: Hoare triple {29372#(= ~t1_st~0 0)} assume !false; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,467 INFO L290 TraceCheckUtils]: 39: Hoare triple {29372#(= ~t1_st~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,467 INFO L290 TraceCheckUtils]: 40: Hoare triple {29372#(= ~t1_st~0 0)} assume !false; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,468 INFO L290 TraceCheckUtils]: 41: Hoare triple {29372#(= ~t1_st~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,468 INFO L290 TraceCheckUtils]: 42: Hoare triple {29372#(= ~t1_st~0 0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,468 INFO L290 TraceCheckUtils]: 43: Hoare triple {29372#(= ~t1_st~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,468 INFO L290 TraceCheckUtils]: 44: Hoare triple {29372#(= ~t1_st~0 0)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,469 INFO L290 TraceCheckUtils]: 45: Hoare triple {29372#(= ~t1_st~0 0)} assume 0 != eval_~tmp~0#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,469 INFO L290 TraceCheckUtils]: 46: Hoare triple {29372#(= ~t1_st~0 0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,469 INFO L290 TraceCheckUtils]: 47: Hoare triple {29372#(= ~t1_st~0 0)} assume !(0 != eval_~tmp_ndt_1~0#1); {29372#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:09,470 INFO L290 TraceCheckUtils]: 48: Hoare triple {29372#(= ~t1_st~0 0)} assume !(0 == ~t1_st~0); {29371#false} is VALID [2022-02-21 04:24:09,470 INFO L290 TraceCheckUtils]: 49: Hoare triple {29371#false} assume !(0 == ~t2_st~0); {29371#false} is VALID [2022-02-21 04:24:09,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:09,470 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:09,470 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [297099080] [2022-02-21 04:24:09,470 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [297099080] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:09,471 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:09,471 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:09,471 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602969606] [2022-02-21 04:24:09,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:09,541 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:09,542 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:09,542 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:09,542 INFO L87 Difference]: Start difference. First operand 1122 states and 1498 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 16.666666666666668) internal successors, (50), 3 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:10,069 INFO L93 Difference]: Finished difference Result 1971 states and 2598 transitions. [2022-02-21 04:24:10,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:10,069 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 16.666666666666668) internal successors, (50), 3 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,104 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:10,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1971 states and 2598 transitions. [2022-02-21 04:24:10,243 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1829 [2022-02-21 04:24:10,382 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1971 states to 1971 states and 2598 transitions. [2022-02-21 04:24:10,382 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1971 [2022-02-21 04:24:10,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1971 [2022-02-21 04:24:10,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1971 states and 2598 transitions. [2022-02-21 04:24:10,386 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:10,387 INFO L681 BuchiCegarLoop]: Abstraction has 1971 states and 2598 transitions. [2022-02-21 04:24:10,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1971 states and 2598 transitions. [2022-02-21 04:24:10,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1971 to 1875. [2022-02-21 04:24:10,409 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:10,412 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1971 states and 2598 transitions. Second operand has 1875 states, 1875 states have (on average 1.3221333333333334) internal successors, (2479), 1874 states have internal predecessors, (2479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,413 INFO L74 IsIncluded]: Start isIncluded. First operand 1971 states and 2598 transitions. Second operand has 1875 states, 1875 states have (on average 1.3221333333333334) internal successors, (2479), 1874 states have internal predecessors, (2479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,415 INFO L87 Difference]: Start difference. First operand 1971 states and 2598 transitions. Second operand has 1875 states, 1875 states have (on average 1.3221333333333334) internal successors, (2479), 1874 states have internal predecessors, (2479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:10,542 INFO L93 Difference]: Finished difference Result 1971 states and 2598 transitions. [2022-02-21 04:24:10,542 INFO L276 IsEmpty]: Start isEmpty. Operand 1971 states and 2598 transitions. [2022-02-21 04:24:10,544 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:10,544 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:10,547 INFO L74 IsIncluded]: Start isIncluded. First operand has 1875 states, 1875 states have (on average 1.3221333333333334) internal successors, (2479), 1874 states have internal predecessors, (2479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1971 states and 2598 transitions. [2022-02-21 04:24:10,549 INFO L87 Difference]: Start difference. First operand has 1875 states, 1875 states have (on average 1.3221333333333334) internal successors, (2479), 1874 states have internal predecessors, (2479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1971 states and 2598 transitions. [2022-02-21 04:24:10,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:10,649 INFO L93 Difference]: Finished difference Result 1971 states and 2598 transitions. [2022-02-21 04:24:10,649 INFO L276 IsEmpty]: Start isEmpty. Operand 1971 states and 2598 transitions. [2022-02-21 04:24:10,651 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:10,652 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:10,652 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:10,652 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:10,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1875 states, 1875 states have (on average 1.3221333333333334) internal successors, (2479), 1874 states have internal predecessors, (2479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1875 states to 1875 states and 2479 transitions. [2022-02-21 04:24:10,774 INFO L704 BuchiCegarLoop]: Abstraction has 1875 states and 2479 transitions. [2022-02-21 04:24:10,774 INFO L587 BuchiCegarLoop]: Abstraction has 1875 states and 2479 transitions. [2022-02-21 04:24:10,775 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:24:10,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1875 states and 2479 transitions. [2022-02-21 04:24:10,782 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1768 [2022-02-21 04:24:10,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:10,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:10,782 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,782 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,783 INFO L791 eck$LassoCheckResult]: Stem: 31612#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 31568#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 31346#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31347#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31593#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 31440#L221-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 31411#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31412#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31398#L334 assume !(0 == ~M_E~0); 31399#L334-2 assume !(0 == ~T1_E~0); 31504#L339-1 assume !(0 == ~T2_E~0); 31505#L344-1 assume !(0 == ~E_1~0); 31553#L349-1 assume !(0 == ~E_2~0); 31554#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31515#L156 assume !(1 == ~m_pc~0); 31516#L156-2 is_master_triggered_~__retres1~0#1 := 0; 31546#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31547#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 31463#L405 assume !(0 != activate_threads_~tmp~1#1); 31464#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31528#L175 assume !(1 == ~t1_pc~0); 31529#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31447#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31448#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 31509#L413 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31510#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31596#L194 assume !(1 == ~t2_pc~0); 31495#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31496#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31400#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31401#L421 assume !(0 != activate_threads_~tmp___1~0#1); 31472#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31473#L367 assume !(1 == ~M_E~0); 31598#L367-2 assume !(1 == ~T1_E~0); 31538#L372-1 assume !(1 == ~T2_E~0); 31539#L377-1 assume !(1 == ~E_1~0); 31543#L382-1 assume !(1 == ~E_2~0); 31467#L387-1 assume { :end_inline_reset_delta_events } true; 31468#L528-2 assume !false; 33175#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33170#L309 [2022-02-21 04:24:10,783 INFO L793 eck$LassoCheckResult]: Loop: 33170#L309 assume !false; 33167#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 33162#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 33158#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 33155#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33149#L276 assume 0 != eval_~tmp~0#1; 33147#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 31442#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 31443#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 31738#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 32523#L295 assume !(0 == ~t2_st~0); 33170#L309 [2022-02-21 04:24:10,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:10,783 INFO L85 PathProgramCache]: Analyzing trace with hash -808857497, now seen corresponding path program 1 times [2022-02-21 04:24:10,783 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:10,784 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036485578] [2022-02-21 04:24:10,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:10,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:10,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:10,797 INFO L290 TraceCheckUtils]: 0: Hoare triple {37164#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; {37164#true} is VALID [2022-02-21 04:24:10,797 INFO L290 TraceCheckUtils]: 1: Hoare triple {37164#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {37166#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:10,798 INFO L290 TraceCheckUtils]: 2: Hoare triple {37166#(= ~t1_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {37166#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:10,798 INFO L290 TraceCheckUtils]: 3: Hoare triple {37166#(= ~t1_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {37166#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:10,798 INFO L290 TraceCheckUtils]: 4: Hoare triple {37166#(= ~t1_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {37166#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:10,799 INFO L290 TraceCheckUtils]: 5: Hoare triple {37166#(= ~t1_i~0 1)} assume !(1 == ~t1_i~0);~t1_st~0 := 2; {37165#false} is VALID [2022-02-21 04:24:10,799 INFO L290 TraceCheckUtils]: 6: Hoare triple {37165#false} assume 1 == ~t2_i~0;~t2_st~0 := 0; {37165#false} is VALID [2022-02-21 04:24:10,799 INFO L290 TraceCheckUtils]: 7: Hoare triple {37165#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {37165#false} is VALID [2022-02-21 04:24:10,799 INFO L290 TraceCheckUtils]: 8: Hoare triple {37165#false} assume !(0 == ~M_E~0); {37165#false} is VALID [2022-02-21 04:24:10,799 INFO L290 TraceCheckUtils]: 9: Hoare triple {37165#false} assume !(0 == ~T1_E~0); {37165#false} is VALID [2022-02-21 04:24:10,799 INFO L290 TraceCheckUtils]: 10: Hoare triple {37165#false} assume !(0 == ~T2_E~0); {37165#false} is VALID [2022-02-21 04:24:10,799 INFO L290 TraceCheckUtils]: 11: Hoare triple {37165#false} assume !(0 == ~E_1~0); {37165#false} is VALID [2022-02-21 04:24:10,800 INFO L290 TraceCheckUtils]: 12: Hoare triple {37165#false} assume !(0 == ~E_2~0); {37165#false} is VALID [2022-02-21 04:24:10,800 INFO L290 TraceCheckUtils]: 13: Hoare triple {37165#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37165#false} is VALID [2022-02-21 04:24:10,800 INFO L290 TraceCheckUtils]: 14: Hoare triple {37165#false} assume !(1 == ~m_pc~0); {37165#false} is VALID [2022-02-21 04:24:10,800 INFO L290 TraceCheckUtils]: 15: Hoare triple {37165#false} is_master_triggered_~__retres1~0#1 := 0; {37165#false} is VALID [2022-02-21 04:24:10,800 INFO L290 TraceCheckUtils]: 16: Hoare triple {37165#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37165#false} is VALID [2022-02-21 04:24:10,800 INFO L290 TraceCheckUtils]: 17: Hoare triple {37165#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {37165#false} is VALID [2022-02-21 04:24:10,800 INFO L290 TraceCheckUtils]: 18: Hoare triple {37165#false} assume !(0 != activate_threads_~tmp~1#1); {37165#false} is VALID [2022-02-21 04:24:10,801 INFO L290 TraceCheckUtils]: 19: Hoare triple {37165#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37165#false} is VALID [2022-02-21 04:24:10,801 INFO L290 TraceCheckUtils]: 20: Hoare triple {37165#false} assume !(1 == ~t1_pc~0); {37165#false} is VALID [2022-02-21 04:24:10,801 INFO L290 TraceCheckUtils]: 21: Hoare triple {37165#false} is_transmit1_triggered_~__retres1~1#1 := 0; {37165#false} is VALID [2022-02-21 04:24:10,801 INFO L290 TraceCheckUtils]: 22: Hoare triple {37165#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37165#false} is VALID [2022-02-21 04:24:10,801 INFO L290 TraceCheckUtils]: 23: Hoare triple {37165#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {37165#false} is VALID [2022-02-21 04:24:10,801 INFO L290 TraceCheckUtils]: 24: Hoare triple {37165#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {37165#false} is VALID [2022-02-21 04:24:10,801 INFO L290 TraceCheckUtils]: 25: Hoare triple {37165#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37165#false} is VALID [2022-02-21 04:24:10,801 INFO L290 TraceCheckUtils]: 26: Hoare triple {37165#false} assume !(1 == ~t2_pc~0); {37165#false} is VALID [2022-02-21 04:24:10,802 INFO L290 TraceCheckUtils]: 27: Hoare triple {37165#false} is_transmit2_triggered_~__retres1~2#1 := 0; {37165#false} is VALID [2022-02-21 04:24:10,802 INFO L290 TraceCheckUtils]: 28: Hoare triple {37165#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37165#false} is VALID [2022-02-21 04:24:10,802 INFO L290 TraceCheckUtils]: 29: Hoare triple {37165#false} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {37165#false} is VALID [2022-02-21 04:24:10,802 INFO L290 TraceCheckUtils]: 30: Hoare triple {37165#false} assume !(0 != activate_threads_~tmp___1~0#1); {37165#false} is VALID [2022-02-21 04:24:10,802 INFO L290 TraceCheckUtils]: 31: Hoare triple {37165#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37165#false} is VALID [2022-02-21 04:24:10,802 INFO L290 TraceCheckUtils]: 32: Hoare triple {37165#false} assume !(1 == ~M_E~0); {37165#false} is VALID [2022-02-21 04:24:10,802 INFO L290 TraceCheckUtils]: 33: Hoare triple {37165#false} assume !(1 == ~T1_E~0); {37165#false} is VALID [2022-02-21 04:24:10,803 INFO L290 TraceCheckUtils]: 34: Hoare triple {37165#false} assume !(1 == ~T2_E~0); {37165#false} is VALID [2022-02-21 04:24:10,803 INFO L290 TraceCheckUtils]: 35: Hoare triple {37165#false} assume !(1 == ~E_1~0); {37165#false} is VALID [2022-02-21 04:24:10,803 INFO L290 TraceCheckUtils]: 36: Hoare triple {37165#false} assume !(1 == ~E_2~0); {37165#false} is VALID [2022-02-21 04:24:10,803 INFO L290 TraceCheckUtils]: 37: Hoare triple {37165#false} assume { :end_inline_reset_delta_events } true; {37165#false} is VALID [2022-02-21 04:24:10,803 INFO L290 TraceCheckUtils]: 38: Hoare triple {37165#false} assume !false; {37165#false} is VALID [2022-02-21 04:24:10,803 INFO L290 TraceCheckUtils]: 39: Hoare triple {37165#false} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {37165#false} is VALID [2022-02-21 04:24:10,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:10,804 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:10,804 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036485578] [2022-02-21 04:24:10,804 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036485578] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:10,804 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:10,804 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:10,804 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350971565] [2022-02-21 04:24:10,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:10,805 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:10,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:10,805 INFO L85 PathProgramCache]: Analyzing trace with hash 993952052, now seen corresponding path program 1 times [2022-02-21 04:24:10,805 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:10,805 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004801737] [2022-02-21 04:24:10,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:10,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:10,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:10,808 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:10,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:10,811 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:10,892 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:10,893 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:10,893 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:10,893 INFO L87 Difference]: Start difference. First operand 1875 states and 2479 transitions. cyclomatic complexity: 609 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,148 INFO L93 Difference]: Finished difference Result 1701 states and 2255 transitions. [2022-02-21 04:24:11,148 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:11,148 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,173 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:11,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2255 transitions. [2022-02-21 04:24:11,285 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1655 [2022-02-21 04:24:11,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2255 transitions. [2022-02-21 04:24:11,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2022-02-21 04:24:11,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2022-02-21 04:24:11,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2255 transitions. [2022-02-21 04:24:11,387 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:11,387 INFO L681 BuchiCegarLoop]: Abstraction has 1701 states and 2255 transitions. [2022-02-21 04:24:11,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2255 transitions. [2022-02-21 04:24:11,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2022-02-21 04:24:11,406 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:11,409 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1701 states and 2255 transitions. Second operand has 1701 states, 1701 states have (on average 1.3256907701352145) internal successors, (2255), 1700 states have internal predecessors, (2255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,410 INFO L74 IsIncluded]: Start isIncluded. First operand 1701 states and 2255 transitions. Second operand has 1701 states, 1701 states have (on average 1.3256907701352145) internal successors, (2255), 1700 states have internal predecessors, (2255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,412 INFO L87 Difference]: Start difference. First operand 1701 states and 2255 transitions. Second operand has 1701 states, 1701 states have (on average 1.3256907701352145) internal successors, (2255), 1700 states have internal predecessors, (2255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,506 INFO L93 Difference]: Finished difference Result 1701 states and 2255 transitions. [2022-02-21 04:24:11,506 INFO L276 IsEmpty]: Start isEmpty. Operand 1701 states and 2255 transitions. [2022-02-21 04:24:11,508 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:11,508 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:11,511 INFO L74 IsIncluded]: Start isIncluded. First operand has 1701 states, 1701 states have (on average 1.3256907701352145) internal successors, (2255), 1700 states have internal predecessors, (2255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1701 states and 2255 transitions. [2022-02-21 04:24:11,512 INFO L87 Difference]: Start difference. First operand has 1701 states, 1701 states have (on average 1.3256907701352145) internal successors, (2255), 1700 states have internal predecessors, (2255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1701 states and 2255 transitions. [2022-02-21 04:24:11,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,575 INFO L93 Difference]: Finished difference Result 1701 states and 2255 transitions. [2022-02-21 04:24:11,575 INFO L276 IsEmpty]: Start isEmpty. Operand 1701 states and 2255 transitions. [2022-02-21 04:24:11,576 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:11,577 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:11,577 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:11,577 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:11,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.3256907701352145) internal successors, (2255), 1700 states have internal predecessors, (2255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2255 transitions. [2022-02-21 04:24:11,679 INFO L704 BuchiCegarLoop]: Abstraction has 1701 states and 2255 transitions. [2022-02-21 04:24:11,680 INFO L587 BuchiCegarLoop]: Abstraction has 1701 states and 2255 transitions. [2022-02-21 04:24:11,680 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:24:11,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2255 transitions. [2022-02-21 04:24:11,685 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1655 [2022-02-21 04:24:11,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:11,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:11,686 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:11,686 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:11,686 INFO L791 eck$LassoCheckResult]: Stem: 39110#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 39070#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 38872#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38873#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39095#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 38963#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38935#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38936#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38923#L334 assume !(0 == ~M_E~0); 38924#L334-2 assume !(0 == ~T1_E~0); 39019#L339-1 assume !(0 == ~T2_E~0); 39013#L344-1 assume !(0 == ~E_1~0); 39014#L349-1 assume !(0 == ~E_2~0); 38933#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38934#L156 assume !(1 == ~m_pc~0); 39027#L156-2 is_master_triggered_~__retres1~0#1 := 0; 39050#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39039#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 38985#L405 assume !(0 != activate_threads_~tmp~1#1); 38968#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38969#L175 assume !(1 == ~t1_pc~0); 38976#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38970#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38971#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 39022#L413 assume !(0 != activate_threads_~tmp___0~0#1); 39023#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39098#L194 assume !(1 == ~t2_pc~0); 39012#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38980#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38925#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38912#L421 assume !(0 != activate_threads_~tmp___1~0#1); 38913#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38886#L367 assume !(1 == ~M_E~0); 38887#L367-2 assume !(1 == ~T1_E~0); 39043#L372-1 assume !(1 == ~T2_E~0); 39044#L377-1 assume !(1 == ~E_1~0); 38907#L382-1 assume !(1 == ~E_2~0); 38908#L387-1 assume { :end_inline_reset_delta_events } true; 38987#L528-2 assume !false; 40501#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40496#L309 [2022-02-21 04:24:11,686 INFO L793 eck$LassoCheckResult]: Loop: 40496#L309 assume !false; 40495#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 40494#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 40493#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 40491#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40489#L276 assume 0 != eval_~tmp~0#1; 40488#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 38964#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 38965#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 39046#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 39063#L295 assume !(0 == ~t2_st~0); 40496#L309 [2022-02-21 04:24:11,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:11,687 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 2 times [2022-02-21 04:24:11,687 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:11,687 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747012586] [2022-02-21 04:24:11,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:11,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:11,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:11,693 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:11,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:11,703 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:11,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:11,704 INFO L85 PathProgramCache]: Analyzing trace with hash 993952052, now seen corresponding path program 2 times [2022-02-21 04:24:11,704 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:11,704 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487029700] [2022-02-21 04:24:11,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:11,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:11,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:11,707 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:11,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:11,720 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:11,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:11,722 INFO L85 PathProgramCache]: Analyzing trace with hash 1252891474, now seen corresponding path program 1 times [2022-02-21 04:24:11,722 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:11,722 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575575318] [2022-02-21 04:24:11,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:11,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:11,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:11,741 INFO L290 TraceCheckUtils]: 0: Hoare triple {43980#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; {43980#true} is VALID [2022-02-21 04:24:11,741 INFO L290 TraceCheckUtils]: 1: Hoare triple {43980#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {43980#true} is VALID [2022-02-21 04:24:11,742 INFO L290 TraceCheckUtils]: 2: Hoare triple {43980#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {43980#true} is VALID [2022-02-21 04:24:11,742 INFO L290 TraceCheckUtils]: 3: Hoare triple {43980#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {43980#true} is VALID [2022-02-21 04:24:11,742 INFO L290 TraceCheckUtils]: 4: Hoare triple {43980#true} assume 1 == ~m_i~0;~m_st~0 := 0; {43980#true} is VALID [2022-02-21 04:24:11,742 INFO L290 TraceCheckUtils]: 5: Hoare triple {43980#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {43980#true} is VALID [2022-02-21 04:24:11,742 INFO L290 TraceCheckUtils]: 6: Hoare triple {43980#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,743 INFO L290 TraceCheckUtils]: 7: Hoare triple {43982#(= 0 ~t2_st~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,743 INFO L290 TraceCheckUtils]: 8: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 == ~M_E~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,743 INFO L290 TraceCheckUtils]: 9: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 == ~T1_E~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,744 INFO L290 TraceCheckUtils]: 10: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 == ~T2_E~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,744 INFO L290 TraceCheckUtils]: 11: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 == ~E_1~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,745 INFO L290 TraceCheckUtils]: 12: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 == ~E_2~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,745 INFO L290 TraceCheckUtils]: 13: Hoare triple {43982#(= 0 ~t2_st~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,745 INFO L290 TraceCheckUtils]: 14: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(1 == ~m_pc~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,746 INFO L290 TraceCheckUtils]: 15: Hoare triple {43982#(= 0 ~t2_st~0)} is_master_triggered_~__retres1~0#1 := 0; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,746 INFO L290 TraceCheckUtils]: 16: Hoare triple {43982#(= 0 ~t2_st~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,746 INFO L290 TraceCheckUtils]: 17: Hoare triple {43982#(= 0 ~t2_st~0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,747 INFO L290 TraceCheckUtils]: 18: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp~1#1); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,747 INFO L290 TraceCheckUtils]: 19: Hoare triple {43982#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,747 INFO L290 TraceCheckUtils]: 20: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(1 == ~t1_pc~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,748 INFO L290 TraceCheckUtils]: 21: Hoare triple {43982#(= 0 ~t2_st~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,748 INFO L290 TraceCheckUtils]: 22: Hoare triple {43982#(= 0 ~t2_st~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,749 INFO L290 TraceCheckUtils]: 23: Hoare triple {43982#(= 0 ~t2_st~0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,749 INFO L290 TraceCheckUtils]: 24: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___0~0#1); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,749 INFO L290 TraceCheckUtils]: 25: Hoare triple {43982#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,750 INFO L290 TraceCheckUtils]: 26: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(1 == ~t2_pc~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,750 INFO L290 TraceCheckUtils]: 27: Hoare triple {43982#(= 0 ~t2_st~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,750 INFO L290 TraceCheckUtils]: 28: Hoare triple {43982#(= 0 ~t2_st~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,751 INFO L290 TraceCheckUtils]: 29: Hoare triple {43982#(= 0 ~t2_st~0)} activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,751 INFO L290 TraceCheckUtils]: 30: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___1~0#1); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,751 INFO L290 TraceCheckUtils]: 31: Hoare triple {43982#(= 0 ~t2_st~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,752 INFO L290 TraceCheckUtils]: 32: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(1 == ~M_E~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,752 INFO L290 TraceCheckUtils]: 33: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(1 == ~T1_E~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,753 INFO L290 TraceCheckUtils]: 34: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(1 == ~T2_E~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,753 INFO L290 TraceCheckUtils]: 35: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(1 == ~E_1~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,753 INFO L290 TraceCheckUtils]: 36: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(1 == ~E_2~0); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,754 INFO L290 TraceCheckUtils]: 37: Hoare triple {43982#(= 0 ~t2_st~0)} assume { :end_inline_reset_delta_events } true; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,754 INFO L290 TraceCheckUtils]: 38: Hoare triple {43982#(= 0 ~t2_st~0)} assume !false; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,755 INFO L290 TraceCheckUtils]: 39: Hoare triple {43982#(= 0 ~t2_st~0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,755 INFO L290 TraceCheckUtils]: 40: Hoare triple {43982#(= 0 ~t2_st~0)} assume !false; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,755 INFO L290 TraceCheckUtils]: 41: Hoare triple {43982#(= 0 ~t2_st~0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,756 INFO L290 TraceCheckUtils]: 42: Hoare triple {43982#(= 0 ~t2_st~0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,756 INFO L290 TraceCheckUtils]: 43: Hoare triple {43982#(= 0 ~t2_st~0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,757 INFO L290 TraceCheckUtils]: 44: Hoare triple {43982#(= 0 ~t2_st~0)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,757 INFO L290 TraceCheckUtils]: 45: Hoare triple {43982#(= 0 ~t2_st~0)} assume 0 != eval_~tmp~0#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,758 INFO L290 TraceCheckUtils]: 46: Hoare triple {43982#(= 0 ~t2_st~0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,758 INFO L290 TraceCheckUtils]: 47: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 != eval_~tmp_ndt_1~0#1); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,758 INFO L290 TraceCheckUtils]: 48: Hoare triple {43982#(= 0 ~t2_st~0)} assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,759 INFO L290 TraceCheckUtils]: 49: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 != eval_~tmp_ndt_2~0#1); {43982#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:11,759 INFO L290 TraceCheckUtils]: 50: Hoare triple {43982#(= 0 ~t2_st~0)} assume !(0 == ~t2_st~0); {43981#false} is VALID [2022-02-21 04:24:11,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:11,759 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:11,760 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1575575318] [2022-02-21 04:24:11,760 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1575575318] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:11,760 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:11,760 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:11,760 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181193295] [2022-02-21 04:24:11,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:11,822 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:11,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:11,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:11,823 INFO L87 Difference]: Start difference. First operand 1701 states and 2255 transitions. cyclomatic complexity: 557 Second operand has 3 states, 2 states have (on average 25.5) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:12,219 INFO L93 Difference]: Finished difference Result 3003 states and 3954 transitions. [2022-02-21 04:24:12,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:12,219 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 2 states have (on average 25.5) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,253 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:12,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3003 states and 3954 transitions. [2022-02-21 04:24:12,465 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2952 [2022-02-21 04:24:12,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3003 states to 3003 states and 3954 transitions. [2022-02-21 04:24:12,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3003 [2022-02-21 04:24:12,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3003 [2022-02-21 04:24:12,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3003 states and 3954 transitions. [2022-02-21 04:24:12,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:12,684 INFO L681 BuchiCegarLoop]: Abstraction has 3003 states and 3954 transitions. [2022-02-21 04:24:12,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3003 states and 3954 transitions. [2022-02-21 04:24:12,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3003 to 3003. [2022-02-21 04:24:12,713 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:12,717 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3003 states and 3954 transitions. Second operand has 3003 states, 3003 states have (on average 1.3166833166833167) internal successors, (3954), 3002 states have internal predecessors, (3954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,721 INFO L74 IsIncluded]: Start isIncluded. First operand 3003 states and 3954 transitions. Second operand has 3003 states, 3003 states have (on average 1.3166833166833167) internal successors, (3954), 3002 states have internal predecessors, (3954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,724 INFO L87 Difference]: Start difference. First operand 3003 states and 3954 transitions. Second operand has 3003 states, 3003 states have (on average 1.3166833166833167) internal successors, (3954), 3002 states have internal predecessors, (3954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:12,949 INFO L93 Difference]: Finished difference Result 3003 states and 3954 transitions. [2022-02-21 04:24:12,949 INFO L276 IsEmpty]: Start isEmpty. Operand 3003 states and 3954 transitions. [2022-02-21 04:24:12,952 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:12,952 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:12,956 INFO L74 IsIncluded]: Start isIncluded. First operand has 3003 states, 3003 states have (on average 1.3166833166833167) internal successors, (3954), 3002 states have internal predecessors, (3954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3003 states and 3954 transitions. [2022-02-21 04:24:12,960 INFO L87 Difference]: Start difference. First operand has 3003 states, 3003 states have (on average 1.3166833166833167) internal successors, (3954), 3002 states have internal predecessors, (3954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3003 states and 3954 transitions. [2022-02-21 04:24:13,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,238 INFO L93 Difference]: Finished difference Result 3003 states and 3954 transitions. [2022-02-21 04:24:13,239 INFO L276 IsEmpty]: Start isEmpty. Operand 3003 states and 3954 transitions. [2022-02-21 04:24:13,241 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:13,241 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:13,241 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:13,241 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:13,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3003 states, 3003 states have (on average 1.3166833166833167) internal successors, (3954), 3002 states have internal predecessors, (3954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3003 states to 3003 states and 3954 transitions. [2022-02-21 04:24:13,444 INFO L704 BuchiCegarLoop]: Abstraction has 3003 states and 3954 transitions. [2022-02-21 04:24:13,444 INFO L587 BuchiCegarLoop]: Abstraction has 3003 states and 3954 transitions. [2022-02-21 04:24:13,444 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:24:13,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3003 states and 3954 transitions. [2022-02-21 04:24:13,452 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2952 [2022-02-21 04:24:13,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:13,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:13,453 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:13,453 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:13,453 INFO L791 eck$LassoCheckResult]: Stem: 47222#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 47190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 46988#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46989#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47208#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 47079#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47051#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47052#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47039#L334 assume !(0 == ~M_E~0); 47040#L334-2 assume !(0 == ~T1_E~0); 47141#L339-1 assume !(0 == ~T2_E~0); 47134#L344-1 assume !(0 == ~E_1~0); 47135#L349-1 assume !(0 == ~E_2~0); 47049#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47050#L156 assume !(1 == ~m_pc~0); 47148#L156-2 is_master_triggered_~__retres1~0#1 := 0; 47170#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47158#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 47105#L405 assume !(0 != activate_threads_~tmp~1#1); 47085#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47086#L175 assume !(1 == ~t1_pc~0); 47092#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47087#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47088#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 47143#L413 assume !(0 != activate_threads_~tmp___0~0#1); 47146#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47213#L194 assume !(1 == ~t2_pc~0); 47132#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47099#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47043#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 47028#L421 assume !(0 != activate_threads_~tmp___1~0#1); 47029#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47002#L367 assume !(1 == ~M_E~0); 47003#L367-2 assume !(1 == ~T1_E~0); 47162#L372-1 assume !(1 == ~T2_E~0); 47163#L377-1 assume !(1 == ~E_1~0); 47023#L382-1 assume !(1 == ~E_2~0); 47024#L387-1 assume { :end_inline_reset_delta_events } true; 47106#L528-2 assume !false; 47133#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49693#L309 [2022-02-21 04:24:13,454 INFO L793 eck$LassoCheckResult]: Loop: 49693#L309 assume !false; 49870#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 49869#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 49867#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 49864#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49863#L276 assume 0 != eval_~tmp~0#1; 49862#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 47080#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 47081#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 48242#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 48243#L295 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 49687#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 49693#L309 [2022-02-21 04:24:13,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:13,454 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 3 times [2022-02-21 04:24:13,454 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:13,454 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415165349] [2022-02-21 04:24:13,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:13,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:13,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:13,460 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:13,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:13,466 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:13,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:13,467 INFO L85 PathProgramCache]: Analyzing trace with hash 747741784, now seen corresponding path program 1 times [2022-02-21 04:24:13,467 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:13,467 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [653509812] [2022-02-21 04:24:13,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:13,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:13,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:13,470 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:13,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:13,473 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:13,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:13,473 INFO L85 PathProgramCache]: Analyzing trace with hash 184929274, now seen corresponding path program 1 times [2022-02-21 04:24:13,473 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:13,473 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957803874] [2022-02-21 04:24:13,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:13,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:13,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:13,479 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:13,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:13,487 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:14,169 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.02 04:24:14 BoogieIcfgContainer [2022-02-21 04:24:14,169 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-02-21 04:24:14,169 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-02-21 04:24:14,170 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-02-21 04:24:14,170 INFO L275 PluginConnector]: Witness Printer initialized [2022-02-21 04:24:14,170 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:01" (3/4) ... [2022-02-21 04:24:14,174 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-02-21 04:24:14,221 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-02-21 04:24:14,221 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-02-21 04:24:14,223 INFO L158 Benchmark]: Toolchain (without parser) took 13732.92ms. Allocated memory was 79.7MB in the beginning and 174.1MB in the end (delta: 94.4MB). Free memory was 58.7MB in the beginning and 86.4MB in the end (delta: -27.7MB). Peak memory consumption was 65.9MB. Max. memory is 16.1GB. [2022-02-21 04:24:14,223 INFO L158 Benchmark]: CDTParser took 0.21ms. Allocated memory is still 79.7MB. Free memory was 53.9MB in the beginning and 53.8MB in the end (delta: 45.7kB). There was no memory consumed. Max. memory is 16.1GB. [2022-02-21 04:24:14,224 INFO L158 Benchmark]: CACSL2BoogieTranslator took 240.23ms. Allocated memory is still 79.7MB. Free memory was 58.4MB in the beginning and 44.7MB in the end (delta: 13.8MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-02-21 04:24:14,226 INFO L158 Benchmark]: Boogie Procedure Inliner took 49.28ms. Allocated memory is still 79.7MB. Free memory was 44.7MB in the beginning and 41.1MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-02-21 04:24:14,227 INFO L158 Benchmark]: Boogie Preprocessor took 40.97ms. Allocated memory is still 79.7MB. Free memory was 41.1MB in the beginning and 38.7MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:24:14,227 INFO L158 Benchmark]: RCFGBuilder took 699.18ms. Allocated memory was 79.7MB in the beginning and 98.6MB in the end (delta: 18.9MB). Free memory was 38.7MB in the beginning and 55.3MB in the end (delta: -16.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-02-21 04:24:14,227 INFO L158 Benchmark]: BuchiAutomizer took 12646.29ms. Allocated memory was 98.6MB in the beginning and 174.1MB in the end (delta: 75.5MB). Free memory was 54.8MB in the beginning and 89.6MB in the end (delta: -34.8MB). Peak memory consumption was 89.0MB. Max. memory is 16.1GB. [2022-02-21 04:24:14,228 INFO L158 Benchmark]: Witness Printer took 52.09ms. Allocated memory is still 174.1MB. Free memory was 89.6MB in the beginning and 86.4MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-02-21 04:24:14,232 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - AssertionsEnabledResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21ms. Allocated memory is still 79.7MB. Free memory was 53.9MB in the beginning and 53.8MB in the end (delta: 45.7kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 240.23ms. Allocated memory is still 79.7MB. Free memory was 58.4MB in the beginning and 44.7MB in the end (delta: 13.8MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 49.28ms. Allocated memory is still 79.7MB. Free memory was 44.7MB in the beginning and 41.1MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 40.97ms. Allocated memory is still 79.7MB. Free memory was 41.1MB in the beginning and 38.7MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 699.18ms. Allocated memory was 79.7MB in the beginning and 98.6MB in the end (delta: 18.9MB). Free memory was 38.7MB in the beginning and 55.3MB in the end (delta: -16.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 12646.29ms. Allocated memory was 98.6MB in the beginning and 174.1MB in the end (delta: 75.5MB). Free memory was 54.8MB in the beginning and 89.6MB in the end (delta: -34.8MB). Peak memory consumption was 89.0MB. Max. memory is 16.1GB. * Witness Printer took 52.09ms. Allocated memory is still 174.1MB. Free memory was 89.6MB in the beginning and 86.4MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 3003 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 12.5s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 2.3s. Construction of modules took 0.3s. Büchi inclusion checks took 5.7s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 2.4s AutomataMinimizationTime, 13 MinimizatonAttempts, 1574 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 1.5s Buchi closure took 0.0s. Biggest automaton had 3003 states and ocurred in iteration 13. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4699 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 4699 mSDsluCounter, 7557 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3730 mSDsCounter, 123 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 321 IncrementalHoareTripleChecker+Invalid, 444 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 123 mSolverCounterUnsat, 3827 mSDtfsCounter, 321 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1b4b10b5=0, NULL=1, \result=0, tmp=0, \result=0, __retres1=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@203ad147=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@32c7450f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6fe2b7f7=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@29be91a7=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2fc2846d=0, t1_pc=0, tmp_ndt_2=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22ac9714=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@68028c50=0, E_1=2, __retres1=0, M_E=2, __retres1=1, tmp_ndt_1=0, t2_i=1, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@44517918=0, \result=0, m_i=1, t1_st=0, __retres1=0, t2_pc=0, m_st=0, NULL=0, kernel_st=1, __retres1=0, tmp___0=0, t1_i=1, m_pc=0, \result=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) [L339] COND FALSE !(T1_E == 0) [L344] COND FALSE !(T2_E == 0) [L349] COND FALSE !(E_1 == 0) [L354] COND FALSE !(E_2 == 0) [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; [L156] COND FALSE !(m_pc == 1) [L166] __retres1 = 0 [L168] return (__retres1); [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; [L175] COND FALSE !(t1_pc == 1) [L185] __retres1 = 0 [L187] return (__retres1); [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; [L194] COND FALSE !(t2_pc == 1) [L204] __retres1 = 0 [L206] return (__retres1); [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) [L372] COND FALSE !(T1_E == 1) [L377] COND FALSE !(T2_E == 1) [L382] COND FALSE !(E_1 == 1) [L387] COND FALSE !(E_2 == 1) [L525] RET reset_delta_events() [L528] COND TRUE 1 [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-02-21 04:24:14,292 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)