./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:03,530 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:03,532 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:03,571 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:03,572 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:03,575 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:03,576 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:03,579 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:03,580 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:03,584 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:03,585 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:03,586 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:03,587 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:03,589 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:03,590 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:03,593 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:03,594 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:03,594 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:03,596 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:03,601 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:03,602 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:03,603 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:03,605 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:03,605 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:03,611 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:03,612 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:03,612 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:03,613 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:03,613 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:03,614 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:03,614 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:03,615 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:03,616 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:03,617 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:03,618 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:03,619 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:03,620 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:03,620 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:03,621 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:03,621 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:03,622 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:03,623 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:03,649 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:03,649 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:03,650 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:03,650 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:03,651 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:03,651 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:03,652 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:03,652 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:03,652 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:03,652 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:03,653 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:03,653 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:03,653 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:03,654 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:03,654 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:03,654 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:03,654 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:03,654 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:03,654 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:03,655 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:03,655 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:03,655 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:03,655 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:03,655 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:03,657 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:03,657 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:03,657 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:03,657 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:03,657 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:03,658 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:03,658 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:03,659 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:03,659 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa [2022-02-21 04:24:03,859 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:03,879 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:03,881 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:03,882 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:03,883 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:03,884 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.04.cil.c [2022-02-21 04:24:03,942 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/893401477/2c8f1856b2ad42ed829434a7e07d0ee7/FLAG2c67eafa2 [2022-02-21 04:24:04,309 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:04,310 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c [2022-02-21 04:24:04,320 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/893401477/2c8f1856b2ad42ed829434a7e07d0ee7/FLAG2c67eafa2 [2022-02-21 04:24:04,334 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/893401477/2c8f1856b2ad42ed829434a7e07d0ee7 [2022-02-21 04:24:04,336 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:04,337 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:04,339 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:04,339 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:04,341 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:04,342 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,343 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6bcb6ad6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04, skipping insertion in model container [2022-02-21 04:24:04,343 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,349 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:04,392 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:04,515 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c[706,719] [2022-02-21 04:24:04,574 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:04,583 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:04,591 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c[706,719] [2022-02-21 04:24:04,624 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:04,640 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:04,640 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04 WrapperNode [2022-02-21 04:24:04,640 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:04,641 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:04,641 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:04,641 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:04,659 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,667 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,737 INFO L137 Inliner]: procedures = 36, calls = 42, calls flagged for inlining = 37, calls inlined = 70, statements flattened = 966 [2022-02-21 04:24:04,737 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:04,738 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:04,738 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:04,738 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:04,744 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,745 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,751 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,751 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,767 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,779 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,782 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,788 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:04,789 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:04,789 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:04,790 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:04,791 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (1/1) ... [2022-02-21 04:24:04,803 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:04,813 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:04,828 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:04,834 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:04,855 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:04,855 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:04,855 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:04,856 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:04,926 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:04,928 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:05,773 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:05,793 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:05,794 INFO L299 CfgBuilder]: Removed 8 assume(true) statements. [2022-02-21 04:24:05,797 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:05 BoogieIcfgContainer [2022-02-21 04:24:05,798 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:05,801 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:05,801 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:05,804 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:05,804 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:05,805 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:04" (1/3) ... [2022-02-21 04:24:05,805 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@820461e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:05, skipping insertion in model container [2022-02-21 04:24:05,806 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:05,806 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:04" (2/3) ... [2022-02-21 04:24:05,806 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@820461e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:05, skipping insertion in model container [2022-02-21 04:24:05,806 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:05,806 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:05" (3/3) ... [2022-02-21 04:24:05,807 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2022-02-21 04:24:05,847 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:05,847 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:05,847 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:05,847 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:05,847 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:05,848 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:05,848 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:05,848 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:05,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:05,976 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 322 [2022-02-21 04:24:05,976 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:05,976 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:05,986 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:05,987 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:05,987 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:05,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:06,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 322 [2022-02-21 04:24:06,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:06,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:06,044 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:06,044 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:06,052 INFO L791 eck$LassoCheckResult]: Stem: 381#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 327#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 191#L739true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29#L334true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55#L341true assume !(1 == ~m_i~0);~m_st~0 := 2; 364#L341-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 212#L346-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 117#L351-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 24#L356-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 108#L361-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L502true assume !(0 == ~M_E~0); 83#L502-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 18#L507-1true assume !(0 == ~T2_E~0); 56#L512-1true assume !(0 == ~T3_E~0); 314#L517-1true assume !(0 == ~T4_E~0); 12#L522-1true assume !(0 == ~E_1~0); 277#L527-1true assume !(0 == ~E_2~0); 121#L532-1true assume !(0 == ~E_3~0); 358#L537-1true assume !(0 == ~E_4~0); 136#L542-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115#L238true assume 1 == ~m_pc~0; 320#L239true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 195#L249true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159#L250true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 101#L615true assume !(0 != activate_threads_~tmp~1#1); 200#L615-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89#L257true assume 1 == ~t1_pc~0; 323#L258true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 112#L268true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44#L269true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 193#L623true assume !(0 != activate_threads_~tmp___0~0#1); 25#L623-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 192#L276true assume !(1 == ~t2_pc~0); 279#L276-2true is_transmit2_triggered_~__retres1~2#1 := 0; 337#L287true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214#L288true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 340#L631true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 356#L631-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99#L295true assume 1 == ~t3_pc~0; 38#L296true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 92#L306true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149#L307true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 325#L639true assume !(0 != activate_threads_~tmp___2~0#1); 318#L639-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372#L314true assume !(1 == ~t4_pc~0); 345#L314-2true is_transmit4_triggered_~__retres1~4#1 := 0; 142#L325true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 321#L326true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88#L647true assume !(0 != activate_threads_~tmp___3~0#1); 273#L647-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 386#L555true assume !(1 == ~M_E~0); 40#L555-2true assume !(1 == ~T1_E~0); 366#L560-1true assume !(1 == ~T2_E~0); 13#L565-1true assume !(1 == ~T3_E~0); 94#L570-1true assume !(1 == ~T4_E~0); 222#L575-1true assume !(1 == ~E_1~0); 292#L580-1true assume !(1 == ~E_2~0); 130#L585-1true assume 1 == ~E_3~0;~E_3~0 := 2; 31#L590-1true assume !(1 == ~E_4~0); 28#L595-1true assume { :end_inline_reset_delta_events } true; 179#L776-2true [2022-02-21 04:24:06,059 INFO L793 eck$LassoCheckResult]: Loop: 179#L776-2true assume !false; 20#L777true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118#L477true assume !true; 379#L492true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 124#L334-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75#L502-3true assume !(0 == ~M_E~0); 300#L502-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 312#L507-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 53#L512-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 392#L517-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 50#L522-3true assume 0 == ~E_1~0;~E_1~0 := 1; 90#L527-3true assume 0 == ~E_2~0;~E_2~0 := 1; 140#L532-3true assume 0 == ~E_3~0;~E_3~0 := 1; 264#L537-3true assume !(0 == ~E_4~0); 59#L542-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84#L238-15true assume !(1 == ~m_pc~0); 113#L238-17true is_master_triggered_~__retres1~0#1 := 0; 309#L249-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163#L250-5true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 230#L615-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 157#L615-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 210#L257-15true assume !(1 == ~t1_pc~0); 72#L257-17true is_transmit1_triggered_~__retres1~1#1 := 0; 334#L268-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 362#L269-5true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 305#L623-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 313#L623-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 367#L276-15true assume 1 == ~t2_pc~0; 253#L277-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 246#L287-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 188#L288-5true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 184#L631-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 288#L631-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26#L295-15true assume 1 == ~t3_pc~0; 304#L296-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 331#L306-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155#L307-5true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 165#L639-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 123#L639-17true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164#L314-15true assume 1 == ~t4_pc~0; 282#L315-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 186#L325-5true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252#L326-5true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 317#L647-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119#L647-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82#L555-3true assume 1 == ~M_E~0;~M_E~0 := 2; 196#L555-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 43#L560-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 306#L565-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 346#L570-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 289#L575-3true assume 1 == ~E_1~0;~E_1~0 := 2; 194#L580-3true assume !(1 == ~E_2~0); 390#L585-3true assume 1 == ~E_3~0;~E_3~0 := 2; 236#L590-3true assume 1 == ~E_4~0;~E_4~0 := 2; 271#L595-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 166#L374-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 71#L401-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 100#L402-1true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 98#L795true assume !(0 == start_simulation_~tmp~3#1); 319#L795-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 110#L374-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 266#L401-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 248#L402-2true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 171#L750true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41#L757true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 272#L758true start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 276#L808true assume !(0 != start_simulation_~tmp___0~1#1); 179#L776-2true [2022-02-21 04:24:06,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:06,064 INFO L85 PathProgramCache]: Analyzing trace with hash 1110077256, now seen corresponding path program 1 times [2022-02-21 04:24:06,071 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:06,071 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1258457540] [2022-02-21 04:24:06,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:06,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:06,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:06,280 INFO L290 TraceCheckUtils]: 0: Hoare triple {395#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {395#true} is VALID [2022-02-21 04:24:06,281 INFO L290 TraceCheckUtils]: 1: Hoare triple {395#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {397#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:06,281 INFO L290 TraceCheckUtils]: 2: Hoare triple {397#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {397#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:06,282 INFO L290 TraceCheckUtils]: 3: Hoare triple {397#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {397#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:06,283 INFO L290 TraceCheckUtils]: 4: Hoare triple {397#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {396#false} is VALID [2022-02-21 04:24:06,283 INFO L290 TraceCheckUtils]: 5: Hoare triple {396#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {396#false} is VALID [2022-02-21 04:24:06,284 INFO L290 TraceCheckUtils]: 6: Hoare triple {396#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {396#false} is VALID [2022-02-21 04:24:06,284 INFO L290 TraceCheckUtils]: 7: Hoare triple {396#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {396#false} is VALID [2022-02-21 04:24:06,285 INFO L290 TraceCheckUtils]: 8: Hoare triple {396#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {396#false} is VALID [2022-02-21 04:24:06,285 INFO L290 TraceCheckUtils]: 9: Hoare triple {396#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {396#false} is VALID [2022-02-21 04:24:06,285 INFO L290 TraceCheckUtils]: 10: Hoare triple {396#false} assume !(0 == ~M_E~0); {396#false} is VALID [2022-02-21 04:24:06,286 INFO L290 TraceCheckUtils]: 11: Hoare triple {396#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {396#false} is VALID [2022-02-21 04:24:06,286 INFO L290 TraceCheckUtils]: 12: Hoare triple {396#false} assume !(0 == ~T2_E~0); {396#false} is VALID [2022-02-21 04:24:06,286 INFO L290 TraceCheckUtils]: 13: Hoare triple {396#false} assume !(0 == ~T3_E~0); {396#false} is VALID [2022-02-21 04:24:06,287 INFO L290 TraceCheckUtils]: 14: Hoare triple {396#false} assume !(0 == ~T4_E~0); {396#false} is VALID [2022-02-21 04:24:06,287 INFO L290 TraceCheckUtils]: 15: Hoare triple {396#false} assume !(0 == ~E_1~0); {396#false} is VALID [2022-02-21 04:24:06,287 INFO L290 TraceCheckUtils]: 16: Hoare triple {396#false} assume !(0 == ~E_2~0); {396#false} is VALID [2022-02-21 04:24:06,287 INFO L290 TraceCheckUtils]: 17: Hoare triple {396#false} assume !(0 == ~E_3~0); {396#false} is VALID [2022-02-21 04:24:06,288 INFO L290 TraceCheckUtils]: 18: Hoare triple {396#false} assume !(0 == ~E_4~0); {396#false} is VALID [2022-02-21 04:24:06,288 INFO L290 TraceCheckUtils]: 19: Hoare triple {396#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {396#false} is VALID [2022-02-21 04:24:06,288 INFO L290 TraceCheckUtils]: 20: Hoare triple {396#false} assume 1 == ~m_pc~0; {396#false} is VALID [2022-02-21 04:24:06,289 INFO L290 TraceCheckUtils]: 21: Hoare triple {396#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {396#false} is VALID [2022-02-21 04:24:06,289 INFO L290 TraceCheckUtils]: 22: Hoare triple {396#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {396#false} is VALID [2022-02-21 04:24:06,290 INFO L290 TraceCheckUtils]: 23: Hoare triple {396#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {396#false} is VALID [2022-02-21 04:24:06,290 INFO L290 TraceCheckUtils]: 24: Hoare triple {396#false} assume !(0 != activate_threads_~tmp~1#1); {396#false} is VALID [2022-02-21 04:24:06,290 INFO L290 TraceCheckUtils]: 25: Hoare triple {396#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {396#false} is VALID [2022-02-21 04:24:06,290 INFO L290 TraceCheckUtils]: 26: Hoare triple {396#false} assume 1 == ~t1_pc~0; {396#false} is VALID [2022-02-21 04:24:06,290 INFO L290 TraceCheckUtils]: 27: Hoare triple {396#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {396#false} is VALID [2022-02-21 04:24:06,291 INFO L290 TraceCheckUtils]: 28: Hoare triple {396#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {396#false} is VALID [2022-02-21 04:24:06,291 INFO L290 TraceCheckUtils]: 29: Hoare triple {396#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {396#false} is VALID [2022-02-21 04:24:06,291 INFO L290 TraceCheckUtils]: 30: Hoare triple {396#false} assume !(0 != activate_threads_~tmp___0~0#1); {396#false} is VALID [2022-02-21 04:24:06,292 INFO L290 TraceCheckUtils]: 31: Hoare triple {396#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {396#false} is VALID [2022-02-21 04:24:06,292 INFO L290 TraceCheckUtils]: 32: Hoare triple {396#false} assume !(1 == ~t2_pc~0); {396#false} is VALID [2022-02-21 04:24:06,292 INFO L290 TraceCheckUtils]: 33: Hoare triple {396#false} is_transmit2_triggered_~__retres1~2#1 := 0; {396#false} is VALID [2022-02-21 04:24:06,292 INFO L290 TraceCheckUtils]: 34: Hoare triple {396#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {396#false} is VALID [2022-02-21 04:24:06,293 INFO L290 TraceCheckUtils]: 35: Hoare triple {396#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {396#false} is VALID [2022-02-21 04:24:06,293 INFO L290 TraceCheckUtils]: 36: Hoare triple {396#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {396#false} is VALID [2022-02-21 04:24:06,293 INFO L290 TraceCheckUtils]: 37: Hoare triple {396#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {396#false} is VALID [2022-02-21 04:24:06,293 INFO L290 TraceCheckUtils]: 38: Hoare triple {396#false} assume 1 == ~t3_pc~0; {396#false} is VALID [2022-02-21 04:24:06,294 INFO L290 TraceCheckUtils]: 39: Hoare triple {396#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {396#false} is VALID [2022-02-21 04:24:06,294 INFO L290 TraceCheckUtils]: 40: Hoare triple {396#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {396#false} is VALID [2022-02-21 04:24:06,294 INFO L290 TraceCheckUtils]: 41: Hoare triple {396#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {396#false} is VALID [2022-02-21 04:24:06,294 INFO L290 TraceCheckUtils]: 42: Hoare triple {396#false} assume !(0 != activate_threads_~tmp___2~0#1); {396#false} is VALID [2022-02-21 04:24:06,295 INFO L290 TraceCheckUtils]: 43: Hoare triple {396#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {396#false} is VALID [2022-02-21 04:24:06,296 INFO L290 TraceCheckUtils]: 44: Hoare triple {396#false} assume !(1 == ~t4_pc~0); {396#false} is VALID [2022-02-21 04:24:06,296 INFO L290 TraceCheckUtils]: 45: Hoare triple {396#false} is_transmit4_triggered_~__retres1~4#1 := 0; {396#false} is VALID [2022-02-21 04:24:06,296 INFO L290 TraceCheckUtils]: 46: Hoare triple {396#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {396#false} is VALID [2022-02-21 04:24:06,296 INFO L290 TraceCheckUtils]: 47: Hoare triple {396#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {396#false} is VALID [2022-02-21 04:24:06,296 INFO L290 TraceCheckUtils]: 48: Hoare triple {396#false} assume !(0 != activate_threads_~tmp___3~0#1); {396#false} is VALID [2022-02-21 04:24:06,299 INFO L290 TraceCheckUtils]: 49: Hoare triple {396#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {396#false} is VALID [2022-02-21 04:24:06,300 INFO L290 TraceCheckUtils]: 50: Hoare triple {396#false} assume !(1 == ~M_E~0); {396#false} is VALID [2022-02-21 04:24:06,300 INFO L290 TraceCheckUtils]: 51: Hoare triple {396#false} assume !(1 == ~T1_E~0); {396#false} is VALID [2022-02-21 04:24:06,302 INFO L290 TraceCheckUtils]: 52: Hoare triple {396#false} assume !(1 == ~T2_E~0); {396#false} is VALID [2022-02-21 04:24:06,302 INFO L290 TraceCheckUtils]: 53: Hoare triple {396#false} assume !(1 == ~T3_E~0); {396#false} is VALID [2022-02-21 04:24:06,303 INFO L290 TraceCheckUtils]: 54: Hoare triple {396#false} assume !(1 == ~T4_E~0); {396#false} is VALID [2022-02-21 04:24:06,303 INFO L290 TraceCheckUtils]: 55: Hoare triple {396#false} assume !(1 == ~E_1~0); {396#false} is VALID [2022-02-21 04:24:06,303 INFO L290 TraceCheckUtils]: 56: Hoare triple {396#false} assume !(1 == ~E_2~0); {396#false} is VALID [2022-02-21 04:24:06,303 INFO L290 TraceCheckUtils]: 57: Hoare triple {396#false} assume 1 == ~E_3~0;~E_3~0 := 2; {396#false} is VALID [2022-02-21 04:24:06,304 INFO L290 TraceCheckUtils]: 58: Hoare triple {396#false} assume !(1 == ~E_4~0); {396#false} is VALID [2022-02-21 04:24:06,304 INFO L290 TraceCheckUtils]: 59: Hoare triple {396#false} assume { :end_inline_reset_delta_events } true; {396#false} is VALID [2022-02-21 04:24:06,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:06,306 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:06,306 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1258457540] [2022-02-21 04:24:06,308 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1258457540] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:06,309 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:06,311 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:06,314 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1361617178] [2022-02-21 04:24:06,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:06,322 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:06,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:06,325 INFO L85 PathProgramCache]: Analyzing trace with hash 1190976846, now seen corresponding path program 1 times [2022-02-21 04:24:06,325 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:06,325 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523816611] [2022-02-21 04:24:06,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:06,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:06,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:06,368 INFO L290 TraceCheckUtils]: 0: Hoare triple {398#true} assume !false; {398#true} is VALID [2022-02-21 04:24:06,369 INFO L290 TraceCheckUtils]: 1: Hoare triple {398#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {398#true} is VALID [2022-02-21 04:24:06,369 INFO L290 TraceCheckUtils]: 2: Hoare triple {398#true} assume !true; {399#false} is VALID [2022-02-21 04:24:06,370 INFO L290 TraceCheckUtils]: 3: Hoare triple {399#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {399#false} is VALID [2022-02-21 04:24:06,370 INFO L290 TraceCheckUtils]: 4: Hoare triple {399#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {399#false} is VALID [2022-02-21 04:24:06,370 INFO L290 TraceCheckUtils]: 5: Hoare triple {399#false} assume !(0 == ~M_E~0); {399#false} is VALID [2022-02-21 04:24:06,370 INFO L290 TraceCheckUtils]: 6: Hoare triple {399#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {399#false} is VALID [2022-02-21 04:24:06,371 INFO L290 TraceCheckUtils]: 7: Hoare triple {399#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {399#false} is VALID [2022-02-21 04:24:06,371 INFO L290 TraceCheckUtils]: 8: Hoare triple {399#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {399#false} is VALID [2022-02-21 04:24:06,372 INFO L290 TraceCheckUtils]: 9: Hoare triple {399#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {399#false} is VALID [2022-02-21 04:24:06,372 INFO L290 TraceCheckUtils]: 10: Hoare triple {399#false} assume 0 == ~E_1~0;~E_1~0 := 1; {399#false} is VALID [2022-02-21 04:24:06,372 INFO L290 TraceCheckUtils]: 11: Hoare triple {399#false} assume 0 == ~E_2~0;~E_2~0 := 1; {399#false} is VALID [2022-02-21 04:24:06,372 INFO L290 TraceCheckUtils]: 12: Hoare triple {399#false} assume 0 == ~E_3~0;~E_3~0 := 1; {399#false} is VALID [2022-02-21 04:24:06,372 INFO L290 TraceCheckUtils]: 13: Hoare triple {399#false} assume !(0 == ~E_4~0); {399#false} is VALID [2022-02-21 04:24:06,373 INFO L290 TraceCheckUtils]: 14: Hoare triple {399#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {399#false} is VALID [2022-02-21 04:24:06,373 INFO L290 TraceCheckUtils]: 15: Hoare triple {399#false} assume !(1 == ~m_pc~0); {399#false} is VALID [2022-02-21 04:24:06,373 INFO L290 TraceCheckUtils]: 16: Hoare triple {399#false} is_master_triggered_~__retres1~0#1 := 0; {399#false} is VALID [2022-02-21 04:24:06,373 INFO L290 TraceCheckUtils]: 17: Hoare triple {399#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {399#false} is VALID [2022-02-21 04:24:06,373 INFO L290 TraceCheckUtils]: 18: Hoare triple {399#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {399#false} is VALID [2022-02-21 04:24:06,374 INFO L290 TraceCheckUtils]: 19: Hoare triple {399#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {399#false} is VALID [2022-02-21 04:24:06,374 INFO L290 TraceCheckUtils]: 20: Hoare triple {399#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {399#false} is VALID [2022-02-21 04:24:06,374 INFO L290 TraceCheckUtils]: 21: Hoare triple {399#false} assume !(1 == ~t1_pc~0); {399#false} is VALID [2022-02-21 04:24:06,374 INFO L290 TraceCheckUtils]: 22: Hoare triple {399#false} is_transmit1_triggered_~__retres1~1#1 := 0; {399#false} is VALID [2022-02-21 04:24:06,374 INFO L290 TraceCheckUtils]: 23: Hoare triple {399#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {399#false} is VALID [2022-02-21 04:24:06,375 INFO L290 TraceCheckUtils]: 24: Hoare triple {399#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {399#false} is VALID [2022-02-21 04:24:06,375 INFO L290 TraceCheckUtils]: 25: Hoare triple {399#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {399#false} is VALID [2022-02-21 04:24:06,375 INFO L290 TraceCheckUtils]: 26: Hoare triple {399#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {399#false} is VALID [2022-02-21 04:24:06,375 INFO L290 TraceCheckUtils]: 27: Hoare triple {399#false} assume 1 == ~t2_pc~0; {399#false} is VALID [2022-02-21 04:24:06,375 INFO L290 TraceCheckUtils]: 28: Hoare triple {399#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {399#false} is VALID [2022-02-21 04:24:06,376 INFO L290 TraceCheckUtils]: 29: Hoare triple {399#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {399#false} is VALID [2022-02-21 04:24:06,376 INFO L290 TraceCheckUtils]: 30: Hoare triple {399#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {399#false} is VALID [2022-02-21 04:24:06,376 INFO L290 TraceCheckUtils]: 31: Hoare triple {399#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {399#false} is VALID [2022-02-21 04:24:06,376 INFO L290 TraceCheckUtils]: 32: Hoare triple {399#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {399#false} is VALID [2022-02-21 04:24:06,376 INFO L290 TraceCheckUtils]: 33: Hoare triple {399#false} assume 1 == ~t3_pc~0; {399#false} is VALID [2022-02-21 04:24:06,377 INFO L290 TraceCheckUtils]: 34: Hoare triple {399#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {399#false} is VALID [2022-02-21 04:24:06,377 INFO L290 TraceCheckUtils]: 35: Hoare triple {399#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {399#false} is VALID [2022-02-21 04:24:06,377 INFO L290 TraceCheckUtils]: 36: Hoare triple {399#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {399#false} is VALID [2022-02-21 04:24:06,377 INFO L290 TraceCheckUtils]: 37: Hoare triple {399#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {399#false} is VALID [2022-02-21 04:24:06,378 INFO L290 TraceCheckUtils]: 38: Hoare triple {399#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {399#false} is VALID [2022-02-21 04:24:06,378 INFO L290 TraceCheckUtils]: 39: Hoare triple {399#false} assume 1 == ~t4_pc~0; {399#false} is VALID [2022-02-21 04:24:06,378 INFO L290 TraceCheckUtils]: 40: Hoare triple {399#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {399#false} is VALID [2022-02-21 04:24:06,378 INFO L290 TraceCheckUtils]: 41: Hoare triple {399#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {399#false} is VALID [2022-02-21 04:24:06,379 INFO L290 TraceCheckUtils]: 42: Hoare triple {399#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {399#false} is VALID [2022-02-21 04:24:06,379 INFO L290 TraceCheckUtils]: 43: Hoare triple {399#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {399#false} is VALID [2022-02-21 04:24:06,379 INFO L290 TraceCheckUtils]: 44: Hoare triple {399#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {399#false} is VALID [2022-02-21 04:24:06,381 INFO L290 TraceCheckUtils]: 45: Hoare triple {399#false} assume 1 == ~M_E~0;~M_E~0 := 2; {399#false} is VALID [2022-02-21 04:24:06,382 INFO L290 TraceCheckUtils]: 46: Hoare triple {399#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {399#false} is VALID [2022-02-21 04:24:06,382 INFO L290 TraceCheckUtils]: 47: Hoare triple {399#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {399#false} is VALID [2022-02-21 04:24:06,382 INFO L290 TraceCheckUtils]: 48: Hoare triple {399#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {399#false} is VALID [2022-02-21 04:24:06,382 INFO L290 TraceCheckUtils]: 49: Hoare triple {399#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {399#false} is VALID [2022-02-21 04:24:06,383 INFO L290 TraceCheckUtils]: 50: Hoare triple {399#false} assume 1 == ~E_1~0;~E_1~0 := 2; {399#false} is VALID [2022-02-21 04:24:06,384 INFO L290 TraceCheckUtils]: 51: Hoare triple {399#false} assume !(1 == ~E_2~0); {399#false} is VALID [2022-02-21 04:24:06,384 INFO L290 TraceCheckUtils]: 52: Hoare triple {399#false} assume 1 == ~E_3~0;~E_3~0 := 2; {399#false} is VALID [2022-02-21 04:24:06,384 INFO L290 TraceCheckUtils]: 53: Hoare triple {399#false} assume 1 == ~E_4~0;~E_4~0 := 2; {399#false} is VALID [2022-02-21 04:24:06,386 INFO L290 TraceCheckUtils]: 54: Hoare triple {399#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {399#false} is VALID [2022-02-21 04:24:06,386 INFO L290 TraceCheckUtils]: 55: Hoare triple {399#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {399#false} is VALID [2022-02-21 04:24:06,394 INFO L290 TraceCheckUtils]: 56: Hoare triple {399#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {399#false} is VALID [2022-02-21 04:24:06,395 INFO L290 TraceCheckUtils]: 57: Hoare triple {399#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {399#false} is VALID [2022-02-21 04:24:06,397 INFO L290 TraceCheckUtils]: 58: Hoare triple {399#false} assume !(0 == start_simulation_~tmp~3#1); {399#false} is VALID [2022-02-21 04:24:06,398 INFO L290 TraceCheckUtils]: 59: Hoare triple {399#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {399#false} is VALID [2022-02-21 04:24:06,398 INFO L290 TraceCheckUtils]: 60: Hoare triple {399#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {399#false} is VALID [2022-02-21 04:24:06,398 INFO L290 TraceCheckUtils]: 61: Hoare triple {399#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {399#false} is VALID [2022-02-21 04:24:06,399 INFO L290 TraceCheckUtils]: 62: Hoare triple {399#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {399#false} is VALID [2022-02-21 04:24:06,400 INFO L290 TraceCheckUtils]: 63: Hoare triple {399#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {399#false} is VALID [2022-02-21 04:24:06,400 INFO L290 TraceCheckUtils]: 64: Hoare triple {399#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {399#false} is VALID [2022-02-21 04:24:06,400 INFO L290 TraceCheckUtils]: 65: Hoare triple {399#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {399#false} is VALID [2022-02-21 04:24:06,400 INFO L290 TraceCheckUtils]: 66: Hoare triple {399#false} assume !(0 != start_simulation_~tmp___0~1#1); {399#false} is VALID [2022-02-21 04:24:06,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:06,402 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:06,402 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523816611] [2022-02-21 04:24:06,402 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523816611] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:06,403 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:06,403 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:06,403 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1895245860] [2022-02-21 04:24:06,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:06,404 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:06,405 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:06,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:06,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:06,435 INFO L87 Difference]: Start difference. First operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:06,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:06,910 INFO L93 Difference]: Finished difference Result 390 states and 581 transitions. [2022-02-21 04:24:06,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:06,911 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:06,969 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:06,974 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 390 states and 581 transitions. [2022-02-21 04:24:06,988 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-02-21 04:24:07,006 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 390 states to 384 states and 575 transitions. [2022-02-21 04:24:07,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-02-21 04:24:07,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-02-21 04:24:07,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 575 transitions. [2022-02-21 04:24:07,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:07,010 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2022-02-21 04:24:07,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 575 transitions. [2022-02-21 04:24:07,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-02-21 04:24:07,048 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:07,051 INFO L82 GeneralOperation]: Start isEquivalent. First operand 384 states and 575 transitions. Second operand has 384 states, 384 states have (on average 1.4973958333333333) internal successors, (575), 383 states have internal predecessors, (575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,053 INFO L74 IsIncluded]: Start isIncluded. First operand 384 states and 575 transitions. Second operand has 384 states, 384 states have (on average 1.4973958333333333) internal successors, (575), 383 states have internal predecessors, (575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,055 INFO L87 Difference]: Start difference. First operand 384 states and 575 transitions. Second operand has 384 states, 384 states have (on average 1.4973958333333333) internal successors, (575), 383 states have internal predecessors, (575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:07,068 INFO L93 Difference]: Finished difference Result 384 states and 575 transitions. [2022-02-21 04:24:07,069 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 575 transitions. [2022-02-21 04:24:07,071 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:07,072 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:07,073 INFO L74 IsIncluded]: Start isIncluded. First operand has 384 states, 384 states have (on average 1.4973958333333333) internal successors, (575), 383 states have internal predecessors, (575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 384 states and 575 transitions. [2022-02-21 04:24:07,074 INFO L87 Difference]: Start difference. First operand has 384 states, 384 states have (on average 1.4973958333333333) internal successors, (575), 383 states have internal predecessors, (575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 384 states and 575 transitions. [2022-02-21 04:24:07,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:07,086 INFO L93 Difference]: Finished difference Result 384 states and 575 transitions. [2022-02-21 04:24:07,086 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 575 transitions. [2022-02-21 04:24:07,087 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:07,087 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:07,087 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:07,088 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:07,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4973958333333333) internal successors, (575), 383 states have internal predecessors, (575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 575 transitions. [2022-02-21 04:24:07,101 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2022-02-21 04:24:07,101 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2022-02-21 04:24:07,101 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:07,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 575 transitions. [2022-02-21 04:24:07,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-02-21 04:24:07,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:07,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:07,105 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:07,105 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:07,105 INFO L791 eck$LassoCheckResult]: Stem: 1171#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 790#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 791#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 915#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1021#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 874#L346-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 875#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 887#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 888#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 933#L502 assume !(0 == ~M_E~0); 934#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 862#L507-1 assume !(0 == ~T2_E~0); 863#L512-1 assume !(0 == ~T3_E~0); 1023#L517-1 assume !(0 == ~T4_E~0); 844#L522-1 assume !(0 == ~E_1~0); 845#L527-1 assume !(0 == ~E_2~0); 1040#L532-1 assume !(0 == ~E_3~0); 1134#L537-1 assume !(0 == ~E_4~0); 1148#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1124#L238 assume 1 == ~m_pc~0; 1125#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 803#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 804#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1104#L615 assume !(0 != activate_threads_~tmp~1#1); 826#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 827#L257 assume 1 == ~t1_pc~0; 1082#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 977#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 797#L623 assume !(0 != activate_threads_~tmp___0~0#1); 798#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 792#L276 assume !(1 == ~t2_pc~0); 793#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1051#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 889#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 890#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1159#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1103#L295 assume 1 == ~t3_pc~0; 953#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 908#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1088#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1135#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1128#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1129#L314 assume !(1 == ~t4_pc~0); 945#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 944#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1130#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1080#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1034#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1035#L555 assume !(1 == ~M_E~0); 958#L555-2 assume !(1 == ~T1_E~0); 959#L560-1 assume !(1 == ~T2_E~0); 846#L565-1 assume !(1 == ~T3_E~0); 847#L570-1 assume !(1 == ~T4_E~0); 918#L575-1 assume !(1 == ~E_1~0); 919#L580-1 assume !(1 == ~E_2~0); 1081#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 920#L590-1 assume !(1 == ~E_4~0); 909#L595-1 assume { :end_inline_reset_delta_events } true; 910#L776-2 [2022-02-21 04:24:07,107 INFO L793 eck$LassoCheckResult]: Loop: 910#L776-2 assume !false; 878#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 879#L477 assume !false; 969#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 970#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 811#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 812#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 850#L416 assume !(0 != eval_~tmp~0#1); 852#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1138#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1065#L502-3 assume !(0 == ~M_E~0); 1066#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1092#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1014#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1015#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1000#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1001#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1083#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1017#L537-3 assume !(0 == ~E_4~0); 1018#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1027#L238-15 assume 1 == ~m_pc~0; 828#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 829#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1113#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 939#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 940#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 869#L257-15 assume !(1 == ~t1_pc~0); 870#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1061#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1152#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1105#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1106#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1119#L276-15 assume 1 == ~t2_pc~0; 997#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 984#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 985#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1173#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1074#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 904#L295-15 assume !(1 == ~t3_pc~0); 905#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1102#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1146#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1167#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1136#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1137#L314-15 assume 1 == ~t4_pc~0; 1056#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1057#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 995#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 996#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1123#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1073#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 805#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 806#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 974#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1108#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1075#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 799#L580-3 assume !(1 == ~E_2~0); 800#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 956#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 957#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1032#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 883#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1059#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1098#L795 assume !(0 == start_simulation_~tmp~3#1); 1100#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1120#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 841#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 986#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 987#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 965#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 966#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1033#L808 assume !(0 != start_simulation_~tmp___0~1#1); 910#L776-2 [2022-02-21 04:24:07,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:07,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1069402506, now seen corresponding path program 1 times [2022-02-21 04:24:07,108 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:07,108 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843239467] [2022-02-21 04:24:07,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:07,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:07,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:07,148 INFO L290 TraceCheckUtils]: 0: Hoare triple {1945#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {1945#true} is VALID [2022-02-21 04:24:07,149 INFO L290 TraceCheckUtils]: 1: Hoare triple {1945#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {1947#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:07,150 INFO L290 TraceCheckUtils]: 2: Hoare triple {1947#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1947#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:07,150 INFO L290 TraceCheckUtils]: 3: Hoare triple {1947#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1947#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:07,151 INFO L290 TraceCheckUtils]: 4: Hoare triple {1947#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {1947#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:07,151 INFO L290 TraceCheckUtils]: 5: Hoare triple {1947#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1947#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:07,151 INFO L290 TraceCheckUtils]: 6: Hoare triple {1947#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1946#false} is VALID [2022-02-21 04:24:07,152 INFO L290 TraceCheckUtils]: 7: Hoare triple {1946#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1946#false} is VALID [2022-02-21 04:24:07,152 INFO L290 TraceCheckUtils]: 8: Hoare triple {1946#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1946#false} is VALID [2022-02-21 04:24:07,152 INFO L290 TraceCheckUtils]: 9: Hoare triple {1946#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1946#false} is VALID [2022-02-21 04:24:07,152 INFO L290 TraceCheckUtils]: 10: Hoare triple {1946#false} assume !(0 == ~M_E~0); {1946#false} is VALID [2022-02-21 04:24:07,152 INFO L290 TraceCheckUtils]: 11: Hoare triple {1946#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1946#false} is VALID [2022-02-21 04:24:07,153 INFO L290 TraceCheckUtils]: 12: Hoare triple {1946#false} assume !(0 == ~T2_E~0); {1946#false} is VALID [2022-02-21 04:24:07,153 INFO L290 TraceCheckUtils]: 13: Hoare triple {1946#false} assume !(0 == ~T3_E~0); {1946#false} is VALID [2022-02-21 04:24:07,153 INFO L290 TraceCheckUtils]: 14: Hoare triple {1946#false} assume !(0 == ~T4_E~0); {1946#false} is VALID [2022-02-21 04:24:07,153 INFO L290 TraceCheckUtils]: 15: Hoare triple {1946#false} assume !(0 == ~E_1~0); {1946#false} is VALID [2022-02-21 04:24:07,153 INFO L290 TraceCheckUtils]: 16: Hoare triple {1946#false} assume !(0 == ~E_2~0); {1946#false} is VALID [2022-02-21 04:24:07,154 INFO L290 TraceCheckUtils]: 17: Hoare triple {1946#false} assume !(0 == ~E_3~0); {1946#false} is VALID [2022-02-21 04:24:07,154 INFO L290 TraceCheckUtils]: 18: Hoare triple {1946#false} assume !(0 == ~E_4~0); {1946#false} is VALID [2022-02-21 04:24:07,154 INFO L290 TraceCheckUtils]: 19: Hoare triple {1946#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1946#false} is VALID [2022-02-21 04:24:07,154 INFO L290 TraceCheckUtils]: 20: Hoare triple {1946#false} assume 1 == ~m_pc~0; {1946#false} is VALID [2022-02-21 04:24:07,154 INFO L290 TraceCheckUtils]: 21: Hoare triple {1946#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {1946#false} is VALID [2022-02-21 04:24:07,154 INFO L290 TraceCheckUtils]: 22: Hoare triple {1946#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1946#false} is VALID [2022-02-21 04:24:07,155 INFO L290 TraceCheckUtils]: 23: Hoare triple {1946#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {1946#false} is VALID [2022-02-21 04:24:07,155 INFO L290 TraceCheckUtils]: 24: Hoare triple {1946#false} assume !(0 != activate_threads_~tmp~1#1); {1946#false} is VALID [2022-02-21 04:24:07,155 INFO L290 TraceCheckUtils]: 25: Hoare triple {1946#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1946#false} is VALID [2022-02-21 04:24:07,155 INFO L290 TraceCheckUtils]: 26: Hoare triple {1946#false} assume 1 == ~t1_pc~0; {1946#false} is VALID [2022-02-21 04:24:07,155 INFO L290 TraceCheckUtils]: 27: Hoare triple {1946#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1946#false} is VALID [2022-02-21 04:24:07,156 INFO L290 TraceCheckUtils]: 28: Hoare triple {1946#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1946#false} is VALID [2022-02-21 04:24:07,156 INFO L290 TraceCheckUtils]: 29: Hoare triple {1946#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {1946#false} is VALID [2022-02-21 04:24:07,156 INFO L290 TraceCheckUtils]: 30: Hoare triple {1946#false} assume !(0 != activate_threads_~tmp___0~0#1); {1946#false} is VALID [2022-02-21 04:24:07,156 INFO L290 TraceCheckUtils]: 31: Hoare triple {1946#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1946#false} is VALID [2022-02-21 04:24:07,156 INFO L290 TraceCheckUtils]: 32: Hoare triple {1946#false} assume !(1 == ~t2_pc~0); {1946#false} is VALID [2022-02-21 04:24:07,157 INFO L290 TraceCheckUtils]: 33: Hoare triple {1946#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1946#false} is VALID [2022-02-21 04:24:07,157 INFO L290 TraceCheckUtils]: 34: Hoare triple {1946#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1946#false} is VALID [2022-02-21 04:24:07,157 INFO L290 TraceCheckUtils]: 35: Hoare triple {1946#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {1946#false} is VALID [2022-02-21 04:24:07,157 INFO L290 TraceCheckUtils]: 36: Hoare triple {1946#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1946#false} is VALID [2022-02-21 04:24:07,157 INFO L290 TraceCheckUtils]: 37: Hoare triple {1946#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1946#false} is VALID [2022-02-21 04:24:07,157 INFO L290 TraceCheckUtils]: 38: Hoare triple {1946#false} assume 1 == ~t3_pc~0; {1946#false} is VALID [2022-02-21 04:24:07,158 INFO L290 TraceCheckUtils]: 39: Hoare triple {1946#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1946#false} is VALID [2022-02-21 04:24:07,158 INFO L290 TraceCheckUtils]: 40: Hoare triple {1946#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1946#false} is VALID [2022-02-21 04:24:07,158 INFO L290 TraceCheckUtils]: 41: Hoare triple {1946#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {1946#false} is VALID [2022-02-21 04:24:07,158 INFO L290 TraceCheckUtils]: 42: Hoare triple {1946#false} assume !(0 != activate_threads_~tmp___2~0#1); {1946#false} is VALID [2022-02-21 04:24:07,158 INFO L290 TraceCheckUtils]: 43: Hoare triple {1946#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1946#false} is VALID [2022-02-21 04:24:07,159 INFO L290 TraceCheckUtils]: 44: Hoare triple {1946#false} assume !(1 == ~t4_pc~0); {1946#false} is VALID [2022-02-21 04:24:07,159 INFO L290 TraceCheckUtils]: 45: Hoare triple {1946#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1946#false} is VALID [2022-02-21 04:24:07,159 INFO L290 TraceCheckUtils]: 46: Hoare triple {1946#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1946#false} is VALID [2022-02-21 04:24:07,159 INFO L290 TraceCheckUtils]: 47: Hoare triple {1946#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {1946#false} is VALID [2022-02-21 04:24:07,159 INFO L290 TraceCheckUtils]: 48: Hoare triple {1946#false} assume !(0 != activate_threads_~tmp___3~0#1); {1946#false} is VALID [2022-02-21 04:24:07,159 INFO L290 TraceCheckUtils]: 49: Hoare triple {1946#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1946#false} is VALID [2022-02-21 04:24:07,160 INFO L290 TraceCheckUtils]: 50: Hoare triple {1946#false} assume !(1 == ~M_E~0); {1946#false} is VALID [2022-02-21 04:24:07,160 INFO L290 TraceCheckUtils]: 51: Hoare triple {1946#false} assume !(1 == ~T1_E~0); {1946#false} is VALID [2022-02-21 04:24:07,160 INFO L290 TraceCheckUtils]: 52: Hoare triple {1946#false} assume !(1 == ~T2_E~0); {1946#false} is VALID [2022-02-21 04:24:07,160 INFO L290 TraceCheckUtils]: 53: Hoare triple {1946#false} assume !(1 == ~T3_E~0); {1946#false} is VALID [2022-02-21 04:24:07,160 INFO L290 TraceCheckUtils]: 54: Hoare triple {1946#false} assume !(1 == ~T4_E~0); {1946#false} is VALID [2022-02-21 04:24:07,161 INFO L290 TraceCheckUtils]: 55: Hoare triple {1946#false} assume !(1 == ~E_1~0); {1946#false} is VALID [2022-02-21 04:24:07,161 INFO L290 TraceCheckUtils]: 56: Hoare triple {1946#false} assume !(1 == ~E_2~0); {1946#false} is VALID [2022-02-21 04:24:07,161 INFO L290 TraceCheckUtils]: 57: Hoare triple {1946#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1946#false} is VALID [2022-02-21 04:24:07,161 INFO L290 TraceCheckUtils]: 58: Hoare triple {1946#false} assume !(1 == ~E_4~0); {1946#false} is VALID [2022-02-21 04:24:07,161 INFO L290 TraceCheckUtils]: 59: Hoare triple {1946#false} assume { :end_inline_reset_delta_events } true; {1946#false} is VALID [2022-02-21 04:24:07,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:07,163 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:07,163 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843239467] [2022-02-21 04:24:07,164 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [843239467] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:07,164 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:07,164 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:07,164 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2140441214] [2022-02-21 04:24:07,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:07,165 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:07,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:07,165 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 1 times [2022-02-21 04:24:07,166 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:07,166 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028959164] [2022-02-21 04:24:07,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:07,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:07,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:07,239 INFO L290 TraceCheckUtils]: 0: Hoare triple {1948#true} assume !false; {1948#true} is VALID [2022-02-21 04:24:07,239 INFO L290 TraceCheckUtils]: 1: Hoare triple {1948#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1948#true} is VALID [2022-02-21 04:24:07,239 INFO L290 TraceCheckUtils]: 2: Hoare triple {1948#true} assume !false; {1948#true} is VALID [2022-02-21 04:24:07,240 INFO L290 TraceCheckUtils]: 3: Hoare triple {1948#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {1948#true} is VALID [2022-02-21 04:24:07,240 INFO L290 TraceCheckUtils]: 4: Hoare triple {1948#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {1948#true} is VALID [2022-02-21 04:24:07,240 INFO L290 TraceCheckUtils]: 5: Hoare triple {1948#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {1948#true} is VALID [2022-02-21 04:24:07,240 INFO L290 TraceCheckUtils]: 6: Hoare triple {1948#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {1948#true} is VALID [2022-02-21 04:24:07,240 INFO L290 TraceCheckUtils]: 7: Hoare triple {1948#true} assume !(0 != eval_~tmp~0#1); {1948#true} is VALID [2022-02-21 04:24:07,240 INFO L290 TraceCheckUtils]: 8: Hoare triple {1948#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1948#true} is VALID [2022-02-21 04:24:07,240 INFO L290 TraceCheckUtils]: 9: Hoare triple {1948#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1948#true} is VALID [2022-02-21 04:24:07,240 INFO L290 TraceCheckUtils]: 10: Hoare triple {1948#true} assume !(0 == ~M_E~0); {1948#true} is VALID [2022-02-21 04:24:07,241 INFO L290 TraceCheckUtils]: 11: Hoare triple {1948#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1948#true} is VALID [2022-02-21 04:24:07,241 INFO L290 TraceCheckUtils]: 12: Hoare triple {1948#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1948#true} is VALID [2022-02-21 04:24:07,241 INFO L290 TraceCheckUtils]: 13: Hoare triple {1948#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1948#true} is VALID [2022-02-21 04:24:07,241 INFO L290 TraceCheckUtils]: 14: Hoare triple {1948#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1948#true} is VALID [2022-02-21 04:24:07,241 INFO L290 TraceCheckUtils]: 15: Hoare triple {1948#true} assume 0 == ~E_1~0;~E_1~0 := 1; {1948#true} is VALID [2022-02-21 04:24:07,245 INFO L290 TraceCheckUtils]: 16: Hoare triple {1948#true} assume 0 == ~E_2~0;~E_2~0 := 1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,245 INFO L290 TraceCheckUtils]: 17: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,246 INFO L290 TraceCheckUtils]: 18: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,246 INFO L290 TraceCheckUtils]: 19: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,246 INFO L290 TraceCheckUtils]: 20: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~m_pc~0; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,247 INFO L290 TraceCheckUtils]: 21: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,247 INFO L290 TraceCheckUtils]: 22: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,248 INFO L290 TraceCheckUtils]: 23: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,248 INFO L290 TraceCheckUtils]: 24: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,248 INFO L290 TraceCheckUtils]: 25: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,249 INFO L290 TraceCheckUtils]: 26: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,249 INFO L290 TraceCheckUtils]: 27: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,250 INFO L290 TraceCheckUtils]: 28: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,250 INFO L290 TraceCheckUtils]: 29: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,250 INFO L290 TraceCheckUtils]: 30: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,251 INFO L290 TraceCheckUtils]: 31: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,251 INFO L290 TraceCheckUtils]: 32: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t2_pc~0; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,251 INFO L290 TraceCheckUtils]: 33: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,252 INFO L290 TraceCheckUtils]: 34: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,252 INFO L290 TraceCheckUtils]: 35: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,253 INFO L290 TraceCheckUtils]: 36: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,253 INFO L290 TraceCheckUtils]: 37: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,253 INFO L290 TraceCheckUtils]: 38: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,254 INFO L290 TraceCheckUtils]: 39: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,254 INFO L290 TraceCheckUtils]: 40: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,255 INFO L290 TraceCheckUtils]: 41: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,255 INFO L290 TraceCheckUtils]: 42: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,255 INFO L290 TraceCheckUtils]: 43: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,256 INFO L290 TraceCheckUtils]: 44: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,256 INFO L290 TraceCheckUtils]: 45: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,257 INFO L290 TraceCheckUtils]: 46: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,257 INFO L290 TraceCheckUtils]: 47: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,257 INFO L290 TraceCheckUtils]: 48: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,258 INFO L290 TraceCheckUtils]: 49: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,258 INFO L290 TraceCheckUtils]: 50: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,259 INFO L290 TraceCheckUtils]: 51: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,259 INFO L290 TraceCheckUtils]: 52: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,264 INFO L290 TraceCheckUtils]: 53: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,265 INFO L290 TraceCheckUtils]: 54: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,265 INFO L290 TraceCheckUtils]: 55: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {1950#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,265 INFO L290 TraceCheckUtils]: 56: Hoare triple {1950#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {1949#false} is VALID [2022-02-21 04:24:07,266 INFO L290 TraceCheckUtils]: 57: Hoare triple {1949#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1949#false} is VALID [2022-02-21 04:24:07,266 INFO L290 TraceCheckUtils]: 58: Hoare triple {1949#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1949#false} is VALID [2022-02-21 04:24:07,266 INFO L290 TraceCheckUtils]: 59: Hoare triple {1949#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {1949#false} is VALID [2022-02-21 04:24:07,266 INFO L290 TraceCheckUtils]: 60: Hoare triple {1949#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {1949#false} is VALID [2022-02-21 04:24:07,266 INFO L290 TraceCheckUtils]: 61: Hoare triple {1949#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {1949#false} is VALID [2022-02-21 04:24:07,267 INFO L290 TraceCheckUtils]: 62: Hoare triple {1949#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {1949#false} is VALID [2022-02-21 04:24:07,267 INFO L290 TraceCheckUtils]: 63: Hoare triple {1949#false} assume !(0 == start_simulation_~tmp~3#1); {1949#false} is VALID [2022-02-21 04:24:07,267 INFO L290 TraceCheckUtils]: 64: Hoare triple {1949#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {1949#false} is VALID [2022-02-21 04:24:07,267 INFO L290 TraceCheckUtils]: 65: Hoare triple {1949#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {1949#false} is VALID [2022-02-21 04:24:07,267 INFO L290 TraceCheckUtils]: 66: Hoare triple {1949#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {1949#false} is VALID [2022-02-21 04:24:07,267 INFO L290 TraceCheckUtils]: 67: Hoare triple {1949#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {1949#false} is VALID [2022-02-21 04:24:07,268 INFO L290 TraceCheckUtils]: 68: Hoare triple {1949#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1949#false} is VALID [2022-02-21 04:24:07,268 INFO L290 TraceCheckUtils]: 69: Hoare triple {1949#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1949#false} is VALID [2022-02-21 04:24:07,268 INFO L290 TraceCheckUtils]: 70: Hoare triple {1949#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {1949#false} is VALID [2022-02-21 04:24:07,268 INFO L290 TraceCheckUtils]: 71: Hoare triple {1949#false} assume !(0 != start_simulation_~tmp___0~1#1); {1949#false} is VALID [2022-02-21 04:24:07,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:07,269 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:07,269 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028959164] [2022-02-21 04:24:07,269 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1028959164] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:07,270 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:07,270 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:07,270 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740255762] [2022-02-21 04:24:07,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:07,271 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:07,271 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:07,271 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:07,271 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:07,272 INFO L87 Difference]: Start difference. First operand 384 states and 575 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:07,625 INFO L93 Difference]: Finished difference Result 384 states and 574 transitions. [2022-02-21 04:24:07,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:07,626 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,669 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:07,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 574 transitions. [2022-02-21 04:24:07,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-02-21 04:24:07,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 574 transitions. [2022-02-21 04:24:07,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-02-21 04:24:07,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-02-21 04:24:07,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 574 transitions. [2022-02-21 04:24:07,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:07,695 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2022-02-21 04:24:07,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 574 transitions. [2022-02-21 04:24:07,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-02-21 04:24:07,704 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:07,705 INFO L82 GeneralOperation]: Start isEquivalent. First operand 384 states and 574 transitions. Second operand has 384 states, 384 states have (on average 1.4947916666666667) internal successors, (574), 383 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,706 INFO L74 IsIncluded]: Start isIncluded. First operand 384 states and 574 transitions. Second operand has 384 states, 384 states have (on average 1.4947916666666667) internal successors, (574), 383 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,707 INFO L87 Difference]: Start difference. First operand 384 states and 574 transitions. Second operand has 384 states, 384 states have (on average 1.4947916666666667) internal successors, (574), 383 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:07,728 INFO L93 Difference]: Finished difference Result 384 states and 574 transitions. [2022-02-21 04:24:07,728 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 574 transitions. [2022-02-21 04:24:07,729 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:07,729 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:07,730 INFO L74 IsIncluded]: Start isIncluded. First operand has 384 states, 384 states have (on average 1.4947916666666667) internal successors, (574), 383 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 384 states and 574 transitions. [2022-02-21 04:24:07,731 INFO L87 Difference]: Start difference. First operand has 384 states, 384 states have (on average 1.4947916666666667) internal successors, (574), 383 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 384 states and 574 transitions. [2022-02-21 04:24:07,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:07,743 INFO L93 Difference]: Finished difference Result 384 states and 574 transitions. [2022-02-21 04:24:07,743 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 574 transitions. [2022-02-21 04:24:07,744 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:07,744 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:07,744 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:07,744 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:07,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4947916666666667) internal successors, (574), 383 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:07,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 574 transitions. [2022-02-21 04:24:07,756 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2022-02-21 04:24:07,756 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2022-02-21 04:24:07,756 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:07,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 574 transitions. [2022-02-21 04:24:07,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-02-21 04:24:07,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:07,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:07,759 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:07,760 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:07,760 INFO L791 eck$LassoCheckResult]: Stem: 2716#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2685#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2335#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2336#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2460#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 2566#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2419#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2420#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2432#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2433#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2478#L502 assume !(0 == ~M_E~0); 2479#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2410#L507-1 assume !(0 == ~T2_E~0); 2411#L512-1 assume !(0 == ~T3_E~0); 2568#L517-1 assume !(0 == ~T4_E~0); 2389#L522-1 assume !(0 == ~E_1~0); 2390#L527-1 assume !(0 == ~E_2~0); 2585#L532-1 assume !(0 == ~E_3~0); 2679#L537-1 assume !(0 == ~E_4~0); 2693#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2669#L238 assume 1 == ~m_pc~0; 2670#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2348#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2349#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2649#L615 assume !(0 != activate_threads_~tmp~1#1); 2371#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2372#L257 assume 1 == ~t1_pc~0; 2627#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2487#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2522#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2342#L623 assume !(0 != activate_threads_~tmp___0~0#1); 2343#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2337#L276 assume !(1 == ~t2_pc~0); 2338#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2598#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2434#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2435#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2704#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2648#L295 assume 1 == ~t3_pc~0; 2498#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2453#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2633#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2680#L639 assume !(0 != activate_threads_~tmp___2~0#1); 2673#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2674#L314 assume !(1 == ~t4_pc~0); 2490#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2489#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2675#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2625#L647 assume !(0 != activate_threads_~tmp___3~0#1); 2579#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2580#L555 assume !(1 == ~M_E~0); 2503#L555-2 assume !(1 == ~T1_E~0); 2504#L560-1 assume !(1 == ~T2_E~0); 2391#L565-1 assume !(1 == ~T3_E~0); 2392#L570-1 assume !(1 == ~T4_E~0); 2463#L575-1 assume !(1 == ~E_1~0); 2464#L580-1 assume !(1 == ~E_2~0); 2626#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2465#L590-1 assume !(1 == ~E_4~0); 2454#L595-1 assume { :end_inline_reset_delta_events } true; 2455#L776-2 [2022-02-21 04:24:07,760 INFO L793 eck$LassoCheckResult]: Loop: 2455#L776-2 assume !false; 2423#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2424#L477 assume !false; 2514#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2515#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2356#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2357#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2395#L416 assume !(0 != eval_~tmp~0#1); 2397#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2683#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2610#L502-3 assume !(0 == ~M_E~0); 2611#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2637#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2559#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2560#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2545#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2546#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2628#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2562#L537-3 assume !(0 == ~E_4~0); 2563#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2572#L238-15 assume 1 == ~m_pc~0; 2373#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2374#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2658#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2484#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2485#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2414#L257-15 assume 1 == ~t1_pc~0; 2416#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2606#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2697#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2650#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2651#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2664#L276-15 assume 1 == ~t2_pc~0; 2542#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2529#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2530#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2718#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2619#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2449#L295-15 assume !(1 == ~t3_pc~0); 2450#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2647#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2691#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2712#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2681#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2682#L314-15 assume 1 == ~t4_pc~0; 2601#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2602#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2540#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2541#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2668#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2618#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2350#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2351#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2519#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2653#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2620#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2344#L580-3 assume !(1 == ~E_2~0); 2345#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2501#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2502#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2577#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2428#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2604#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2643#L795 assume !(0 == start_simulation_~tmp~3#1); 2645#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2665#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2386#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2531#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2532#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2510#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2511#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2578#L808 assume !(0 != start_simulation_~tmp___0~1#1); 2455#L776-2 [2022-02-21 04:24:07,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:07,761 INFO L85 PathProgramCache]: Analyzing trace with hash 193383500, now seen corresponding path program 1 times [2022-02-21 04:24:07,761 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:07,761 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316648922] [2022-02-21 04:24:07,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:07,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:07,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:07,791 INFO L290 TraceCheckUtils]: 0: Hoare triple {3490#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {3490#true} is VALID [2022-02-21 04:24:07,792 INFO L290 TraceCheckUtils]: 1: Hoare triple {3490#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {3492#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:07,792 INFO L290 TraceCheckUtils]: 2: Hoare triple {3492#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {3492#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:07,793 INFO L290 TraceCheckUtils]: 3: Hoare triple {3492#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {3492#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:07,793 INFO L290 TraceCheckUtils]: 4: Hoare triple {3492#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {3492#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:07,794 INFO L290 TraceCheckUtils]: 5: Hoare triple {3492#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {3492#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:07,794 INFO L290 TraceCheckUtils]: 6: Hoare triple {3492#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {3492#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:07,794 INFO L290 TraceCheckUtils]: 7: Hoare triple {3492#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {3491#false} is VALID [2022-02-21 04:24:07,795 INFO L290 TraceCheckUtils]: 8: Hoare triple {3491#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {3491#false} is VALID [2022-02-21 04:24:07,795 INFO L290 TraceCheckUtils]: 9: Hoare triple {3491#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {3491#false} is VALID [2022-02-21 04:24:07,795 INFO L290 TraceCheckUtils]: 10: Hoare triple {3491#false} assume !(0 == ~M_E~0); {3491#false} is VALID [2022-02-21 04:24:07,795 INFO L290 TraceCheckUtils]: 11: Hoare triple {3491#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {3491#false} is VALID [2022-02-21 04:24:07,795 INFO L290 TraceCheckUtils]: 12: Hoare triple {3491#false} assume !(0 == ~T2_E~0); {3491#false} is VALID [2022-02-21 04:24:07,795 INFO L290 TraceCheckUtils]: 13: Hoare triple {3491#false} assume !(0 == ~T3_E~0); {3491#false} is VALID [2022-02-21 04:24:07,796 INFO L290 TraceCheckUtils]: 14: Hoare triple {3491#false} assume !(0 == ~T4_E~0); {3491#false} is VALID [2022-02-21 04:24:07,796 INFO L290 TraceCheckUtils]: 15: Hoare triple {3491#false} assume !(0 == ~E_1~0); {3491#false} is VALID [2022-02-21 04:24:07,796 INFO L290 TraceCheckUtils]: 16: Hoare triple {3491#false} assume !(0 == ~E_2~0); {3491#false} is VALID [2022-02-21 04:24:07,796 INFO L290 TraceCheckUtils]: 17: Hoare triple {3491#false} assume !(0 == ~E_3~0); {3491#false} is VALID [2022-02-21 04:24:07,796 INFO L290 TraceCheckUtils]: 18: Hoare triple {3491#false} assume !(0 == ~E_4~0); {3491#false} is VALID [2022-02-21 04:24:07,797 INFO L290 TraceCheckUtils]: 19: Hoare triple {3491#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3491#false} is VALID [2022-02-21 04:24:07,797 INFO L290 TraceCheckUtils]: 20: Hoare triple {3491#false} assume 1 == ~m_pc~0; {3491#false} is VALID [2022-02-21 04:24:07,797 INFO L290 TraceCheckUtils]: 21: Hoare triple {3491#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {3491#false} is VALID [2022-02-21 04:24:07,797 INFO L290 TraceCheckUtils]: 22: Hoare triple {3491#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3491#false} is VALID [2022-02-21 04:24:07,797 INFO L290 TraceCheckUtils]: 23: Hoare triple {3491#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {3491#false} is VALID [2022-02-21 04:24:07,797 INFO L290 TraceCheckUtils]: 24: Hoare triple {3491#false} assume !(0 != activate_threads_~tmp~1#1); {3491#false} is VALID [2022-02-21 04:24:07,798 INFO L290 TraceCheckUtils]: 25: Hoare triple {3491#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3491#false} is VALID [2022-02-21 04:24:07,798 INFO L290 TraceCheckUtils]: 26: Hoare triple {3491#false} assume 1 == ~t1_pc~0; {3491#false} is VALID [2022-02-21 04:24:07,798 INFO L290 TraceCheckUtils]: 27: Hoare triple {3491#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {3491#false} is VALID [2022-02-21 04:24:07,798 INFO L290 TraceCheckUtils]: 28: Hoare triple {3491#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3491#false} is VALID [2022-02-21 04:24:07,798 INFO L290 TraceCheckUtils]: 29: Hoare triple {3491#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {3491#false} is VALID [2022-02-21 04:24:07,799 INFO L290 TraceCheckUtils]: 30: Hoare triple {3491#false} assume !(0 != activate_threads_~tmp___0~0#1); {3491#false} is VALID [2022-02-21 04:24:07,799 INFO L290 TraceCheckUtils]: 31: Hoare triple {3491#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3491#false} is VALID [2022-02-21 04:24:07,799 INFO L290 TraceCheckUtils]: 32: Hoare triple {3491#false} assume !(1 == ~t2_pc~0); {3491#false} is VALID [2022-02-21 04:24:07,799 INFO L290 TraceCheckUtils]: 33: Hoare triple {3491#false} is_transmit2_triggered_~__retres1~2#1 := 0; {3491#false} is VALID [2022-02-21 04:24:07,799 INFO L290 TraceCheckUtils]: 34: Hoare triple {3491#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3491#false} is VALID [2022-02-21 04:24:07,799 INFO L290 TraceCheckUtils]: 35: Hoare triple {3491#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {3491#false} is VALID [2022-02-21 04:24:07,800 INFO L290 TraceCheckUtils]: 36: Hoare triple {3491#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {3491#false} is VALID [2022-02-21 04:24:07,800 INFO L290 TraceCheckUtils]: 37: Hoare triple {3491#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {3491#false} is VALID [2022-02-21 04:24:07,800 INFO L290 TraceCheckUtils]: 38: Hoare triple {3491#false} assume 1 == ~t3_pc~0; {3491#false} is VALID [2022-02-21 04:24:07,800 INFO L290 TraceCheckUtils]: 39: Hoare triple {3491#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {3491#false} is VALID [2022-02-21 04:24:07,800 INFO L290 TraceCheckUtils]: 40: Hoare triple {3491#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {3491#false} is VALID [2022-02-21 04:24:07,801 INFO L290 TraceCheckUtils]: 41: Hoare triple {3491#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {3491#false} is VALID [2022-02-21 04:24:07,801 INFO L290 TraceCheckUtils]: 42: Hoare triple {3491#false} assume !(0 != activate_threads_~tmp___2~0#1); {3491#false} is VALID [2022-02-21 04:24:07,801 INFO L290 TraceCheckUtils]: 43: Hoare triple {3491#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {3491#false} is VALID [2022-02-21 04:24:07,801 INFO L290 TraceCheckUtils]: 44: Hoare triple {3491#false} assume !(1 == ~t4_pc~0); {3491#false} is VALID [2022-02-21 04:24:07,801 INFO L290 TraceCheckUtils]: 45: Hoare triple {3491#false} is_transmit4_triggered_~__retres1~4#1 := 0; {3491#false} is VALID [2022-02-21 04:24:07,802 INFO L290 TraceCheckUtils]: 46: Hoare triple {3491#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {3491#false} is VALID [2022-02-21 04:24:07,802 INFO L290 TraceCheckUtils]: 47: Hoare triple {3491#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {3491#false} is VALID [2022-02-21 04:24:07,802 INFO L290 TraceCheckUtils]: 48: Hoare triple {3491#false} assume !(0 != activate_threads_~tmp___3~0#1); {3491#false} is VALID [2022-02-21 04:24:07,802 INFO L290 TraceCheckUtils]: 49: Hoare triple {3491#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3491#false} is VALID [2022-02-21 04:24:07,802 INFO L290 TraceCheckUtils]: 50: Hoare triple {3491#false} assume !(1 == ~M_E~0); {3491#false} is VALID [2022-02-21 04:24:07,802 INFO L290 TraceCheckUtils]: 51: Hoare triple {3491#false} assume !(1 == ~T1_E~0); {3491#false} is VALID [2022-02-21 04:24:07,803 INFO L290 TraceCheckUtils]: 52: Hoare triple {3491#false} assume !(1 == ~T2_E~0); {3491#false} is VALID [2022-02-21 04:24:07,803 INFO L290 TraceCheckUtils]: 53: Hoare triple {3491#false} assume !(1 == ~T3_E~0); {3491#false} is VALID [2022-02-21 04:24:07,803 INFO L290 TraceCheckUtils]: 54: Hoare triple {3491#false} assume !(1 == ~T4_E~0); {3491#false} is VALID [2022-02-21 04:24:07,803 INFO L290 TraceCheckUtils]: 55: Hoare triple {3491#false} assume !(1 == ~E_1~0); {3491#false} is VALID [2022-02-21 04:24:07,803 INFO L290 TraceCheckUtils]: 56: Hoare triple {3491#false} assume !(1 == ~E_2~0); {3491#false} is VALID [2022-02-21 04:24:07,804 INFO L290 TraceCheckUtils]: 57: Hoare triple {3491#false} assume 1 == ~E_3~0;~E_3~0 := 2; {3491#false} is VALID [2022-02-21 04:24:07,804 INFO L290 TraceCheckUtils]: 58: Hoare triple {3491#false} assume !(1 == ~E_4~0); {3491#false} is VALID [2022-02-21 04:24:07,804 INFO L290 TraceCheckUtils]: 59: Hoare triple {3491#false} assume { :end_inline_reset_delta_events } true; {3491#false} is VALID [2022-02-21 04:24:07,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:07,805 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:07,805 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316648922] [2022-02-21 04:24:07,805 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316648922] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:07,805 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:07,805 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:07,806 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [178444943] [2022-02-21 04:24:07,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:07,806 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:07,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:07,807 INFO L85 PathProgramCache]: Analyzing trace with hash -396103874, now seen corresponding path program 1 times [2022-02-21 04:24:07,807 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:07,808 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203392641] [2022-02-21 04:24:07,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:07,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:07,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:07,879 INFO L290 TraceCheckUtils]: 0: Hoare triple {3493#true} assume !false; {3493#true} is VALID [2022-02-21 04:24:07,879 INFO L290 TraceCheckUtils]: 1: Hoare triple {3493#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {3493#true} is VALID [2022-02-21 04:24:07,879 INFO L290 TraceCheckUtils]: 2: Hoare triple {3493#true} assume !false; {3493#true} is VALID [2022-02-21 04:24:07,879 INFO L290 TraceCheckUtils]: 3: Hoare triple {3493#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {3493#true} is VALID [2022-02-21 04:24:07,880 INFO L290 TraceCheckUtils]: 4: Hoare triple {3493#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {3493#true} is VALID [2022-02-21 04:24:07,880 INFO L290 TraceCheckUtils]: 5: Hoare triple {3493#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {3493#true} is VALID [2022-02-21 04:24:07,880 INFO L290 TraceCheckUtils]: 6: Hoare triple {3493#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {3493#true} is VALID [2022-02-21 04:24:07,880 INFO L290 TraceCheckUtils]: 7: Hoare triple {3493#true} assume !(0 != eval_~tmp~0#1); {3493#true} is VALID [2022-02-21 04:24:07,880 INFO L290 TraceCheckUtils]: 8: Hoare triple {3493#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {3493#true} is VALID [2022-02-21 04:24:07,881 INFO L290 TraceCheckUtils]: 9: Hoare triple {3493#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {3493#true} is VALID [2022-02-21 04:24:07,881 INFO L290 TraceCheckUtils]: 10: Hoare triple {3493#true} assume !(0 == ~M_E~0); {3493#true} is VALID [2022-02-21 04:24:07,881 INFO L290 TraceCheckUtils]: 11: Hoare triple {3493#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {3493#true} is VALID [2022-02-21 04:24:07,881 INFO L290 TraceCheckUtils]: 12: Hoare triple {3493#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {3493#true} is VALID [2022-02-21 04:24:07,881 INFO L290 TraceCheckUtils]: 13: Hoare triple {3493#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {3493#true} is VALID [2022-02-21 04:24:07,881 INFO L290 TraceCheckUtils]: 14: Hoare triple {3493#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {3493#true} is VALID [2022-02-21 04:24:07,882 INFO L290 TraceCheckUtils]: 15: Hoare triple {3493#true} assume 0 == ~E_1~0;~E_1~0 := 1; {3493#true} is VALID [2022-02-21 04:24:07,882 INFO L290 TraceCheckUtils]: 16: Hoare triple {3493#true} assume 0 == ~E_2~0;~E_2~0 := 1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,883 INFO L290 TraceCheckUtils]: 17: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,883 INFO L290 TraceCheckUtils]: 18: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,883 INFO L290 TraceCheckUtils]: 19: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,884 INFO L290 TraceCheckUtils]: 20: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~m_pc~0; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,884 INFO L290 TraceCheckUtils]: 21: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,884 INFO L290 TraceCheckUtils]: 22: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,885 INFO L290 TraceCheckUtils]: 23: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,885 INFO L290 TraceCheckUtils]: 24: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,885 INFO L290 TraceCheckUtils]: 25: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,886 INFO L290 TraceCheckUtils]: 26: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t1_pc~0; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,886 INFO L290 TraceCheckUtils]: 27: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,887 INFO L290 TraceCheckUtils]: 28: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,887 INFO L290 TraceCheckUtils]: 29: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,887 INFO L290 TraceCheckUtils]: 30: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,888 INFO L290 TraceCheckUtils]: 31: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,888 INFO L290 TraceCheckUtils]: 32: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t2_pc~0; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,888 INFO L290 TraceCheckUtils]: 33: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,889 INFO L290 TraceCheckUtils]: 34: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,889 INFO L290 TraceCheckUtils]: 35: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,889 INFO L290 TraceCheckUtils]: 36: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,890 INFO L290 TraceCheckUtils]: 37: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,890 INFO L290 TraceCheckUtils]: 38: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,891 INFO L290 TraceCheckUtils]: 39: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,891 INFO L290 TraceCheckUtils]: 40: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,891 INFO L290 TraceCheckUtils]: 41: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,892 INFO L290 TraceCheckUtils]: 42: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,892 INFO L290 TraceCheckUtils]: 43: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,892 INFO L290 TraceCheckUtils]: 44: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,893 INFO L290 TraceCheckUtils]: 45: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,893 INFO L290 TraceCheckUtils]: 46: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,893 INFO L290 TraceCheckUtils]: 47: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,894 INFO L290 TraceCheckUtils]: 48: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,895 INFO L290 TraceCheckUtils]: 49: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,895 INFO L290 TraceCheckUtils]: 50: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,895 INFO L290 TraceCheckUtils]: 51: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,896 INFO L290 TraceCheckUtils]: 52: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,899 INFO L290 TraceCheckUtils]: 53: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,900 INFO L290 TraceCheckUtils]: 54: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,900 INFO L290 TraceCheckUtils]: 55: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {3495#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:07,900 INFO L290 TraceCheckUtils]: 56: Hoare triple {3495#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {3494#false} is VALID [2022-02-21 04:24:07,900 INFO L290 TraceCheckUtils]: 57: Hoare triple {3494#false} assume 1 == ~E_3~0;~E_3~0 := 2; {3494#false} is VALID [2022-02-21 04:24:07,901 INFO L290 TraceCheckUtils]: 58: Hoare triple {3494#false} assume 1 == ~E_4~0;~E_4~0 := 2; {3494#false} is VALID [2022-02-21 04:24:07,901 INFO L290 TraceCheckUtils]: 59: Hoare triple {3494#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {3494#false} is VALID [2022-02-21 04:24:07,901 INFO L290 TraceCheckUtils]: 60: Hoare triple {3494#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {3494#false} is VALID [2022-02-21 04:24:07,901 INFO L290 TraceCheckUtils]: 61: Hoare triple {3494#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {3494#false} is VALID [2022-02-21 04:24:07,901 INFO L290 TraceCheckUtils]: 62: Hoare triple {3494#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {3494#false} is VALID [2022-02-21 04:24:07,901 INFO L290 TraceCheckUtils]: 63: Hoare triple {3494#false} assume !(0 == start_simulation_~tmp~3#1); {3494#false} is VALID [2022-02-21 04:24:07,901 INFO L290 TraceCheckUtils]: 64: Hoare triple {3494#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {3494#false} is VALID [2022-02-21 04:24:07,902 INFO L290 TraceCheckUtils]: 65: Hoare triple {3494#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {3494#false} is VALID [2022-02-21 04:24:07,902 INFO L290 TraceCheckUtils]: 66: Hoare triple {3494#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {3494#false} is VALID [2022-02-21 04:24:07,902 INFO L290 TraceCheckUtils]: 67: Hoare triple {3494#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {3494#false} is VALID [2022-02-21 04:24:07,902 INFO L290 TraceCheckUtils]: 68: Hoare triple {3494#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {3494#false} is VALID [2022-02-21 04:24:07,902 INFO L290 TraceCheckUtils]: 69: Hoare triple {3494#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {3494#false} is VALID [2022-02-21 04:24:07,902 INFO L290 TraceCheckUtils]: 70: Hoare triple {3494#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {3494#false} is VALID [2022-02-21 04:24:07,902 INFO L290 TraceCheckUtils]: 71: Hoare triple {3494#false} assume !(0 != start_simulation_~tmp___0~1#1); {3494#false} is VALID [2022-02-21 04:24:07,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:07,903 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:07,903 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203392641] [2022-02-21 04:24:07,903 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203392641] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:07,904 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:07,904 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:07,904 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525149703] [2022-02-21 04:24:07,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:07,904 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:07,904 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:07,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:07,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:07,905 INFO L87 Difference]: Start difference. First operand 384 states and 574 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:08,237 INFO L93 Difference]: Finished difference Result 384 states and 573 transitions. [2022-02-21 04:24:08,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:08,237 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,277 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:08,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 573 transitions. [2022-02-21 04:24:08,287 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-02-21 04:24:08,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 573 transitions. [2022-02-21 04:24:08,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-02-21 04:24:08,295 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-02-21 04:24:08,296 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 573 transitions. [2022-02-21 04:24:08,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:08,296 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2022-02-21 04:24:08,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 573 transitions. [2022-02-21 04:24:08,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-02-21 04:24:08,301 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:08,302 INFO L82 GeneralOperation]: Start isEquivalent. First operand 384 states and 573 transitions. Second operand has 384 states, 384 states have (on average 1.4921875) internal successors, (573), 383 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,302 INFO L74 IsIncluded]: Start isIncluded. First operand 384 states and 573 transitions. Second operand has 384 states, 384 states have (on average 1.4921875) internal successors, (573), 383 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,303 INFO L87 Difference]: Start difference. First operand 384 states and 573 transitions. Second operand has 384 states, 384 states have (on average 1.4921875) internal successors, (573), 383 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:08,311 INFO L93 Difference]: Finished difference Result 384 states and 573 transitions. [2022-02-21 04:24:08,311 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 573 transitions. [2022-02-21 04:24:08,312 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:08,312 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:08,313 INFO L74 IsIncluded]: Start isIncluded. First operand has 384 states, 384 states have (on average 1.4921875) internal successors, (573), 383 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 384 states and 573 transitions. [2022-02-21 04:24:08,314 INFO L87 Difference]: Start difference. First operand has 384 states, 384 states have (on average 1.4921875) internal successors, (573), 383 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 384 states and 573 transitions. [2022-02-21 04:24:08,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:08,322 INFO L93 Difference]: Finished difference Result 384 states and 573 transitions. [2022-02-21 04:24:08,322 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 573 transitions. [2022-02-21 04:24:08,323 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:08,323 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:08,323 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:08,323 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:08,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4921875) internal successors, (573), 383 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 573 transitions. [2022-02-21 04:24:08,331 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2022-02-21 04:24:08,331 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2022-02-21 04:24:08,332 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:08,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 573 transitions. [2022-02-21 04:24:08,333 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-02-21 04:24:08,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:08,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:08,335 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:08,335 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:08,335 INFO L791 eck$LassoCheckResult]: Stem: 4261#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4230#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3880#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3881#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4005#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 4111#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3964#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3965#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3977#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3978#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4023#L502 assume !(0 == ~M_E~0); 4024#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3955#L507-1 assume !(0 == ~T2_E~0); 3956#L512-1 assume !(0 == ~T3_E~0); 4113#L517-1 assume !(0 == ~T4_E~0); 3934#L522-1 assume !(0 == ~E_1~0); 3935#L527-1 assume !(0 == ~E_2~0); 4130#L532-1 assume !(0 == ~E_3~0); 4224#L537-1 assume !(0 == ~E_4~0); 4238#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4214#L238 assume 1 == ~m_pc~0; 4215#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3893#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3894#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4194#L615 assume !(0 != activate_threads_~tmp~1#1); 3916#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3917#L257 assume 1 == ~t1_pc~0; 4172#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4032#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4067#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3887#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3888#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3882#L276 assume !(1 == ~t2_pc~0); 3883#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4143#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3979#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3980#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4249#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4193#L295 assume 1 == ~t3_pc~0; 4043#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3998#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4178#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4225#L639 assume !(0 != activate_threads_~tmp___2~0#1); 4218#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4219#L314 assume !(1 == ~t4_pc~0); 4035#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4034#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4220#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4170#L647 assume !(0 != activate_threads_~tmp___3~0#1); 4124#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4125#L555 assume !(1 == ~M_E~0); 4048#L555-2 assume !(1 == ~T1_E~0); 4049#L560-1 assume !(1 == ~T2_E~0); 3936#L565-1 assume !(1 == ~T3_E~0); 3937#L570-1 assume !(1 == ~T4_E~0); 4008#L575-1 assume !(1 == ~E_1~0); 4009#L580-1 assume !(1 == ~E_2~0); 4171#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4010#L590-1 assume !(1 == ~E_4~0); 3999#L595-1 assume { :end_inline_reset_delta_events } true; 4000#L776-2 [2022-02-21 04:24:08,335 INFO L793 eck$LassoCheckResult]: Loop: 4000#L776-2 assume !false; 3968#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3969#L477 assume !false; 4059#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4060#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3901#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3902#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3940#L416 assume !(0 != eval_~tmp~0#1); 3942#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4228#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4155#L502-3 assume !(0 == ~M_E~0); 4156#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4181#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4104#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4105#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4090#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4091#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4173#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4107#L537-3 assume !(0 == ~E_4~0); 4108#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4117#L238-15 assume !(1 == ~m_pc~0); 3920#L238-17 is_master_triggered_~__retres1~0#1 := 0; 3919#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4203#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4029#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4030#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3959#L257-15 assume !(1 == ~t1_pc~0); 3960#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 4151#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4242#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4195#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4196#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4209#L276-15 assume 1 == ~t2_pc~0; 4087#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4074#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4075#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4263#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4164#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3994#L295-15 assume !(1 == ~t3_pc~0); 3995#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 4192#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4236#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4257#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4226#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4227#L314-15 assume 1 == ~t4_pc~0; 4146#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4147#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4085#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4086#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4213#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4163#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3895#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3896#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4064#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4198#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4165#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3889#L580-3 assume !(1 == ~E_2~0); 3890#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4046#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4047#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4122#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3973#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4149#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4188#L795 assume !(0 == start_simulation_~tmp~3#1); 4190#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4210#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3931#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4076#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4077#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4055#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4056#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4123#L808 assume !(0 != start_simulation_~tmp___0~1#1); 4000#L776-2 [2022-02-21 04:24:08,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:08,336 INFO L85 PathProgramCache]: Analyzing trace with hash -250517174, now seen corresponding path program 1 times [2022-02-21 04:24:08,336 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:08,336 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146733819] [2022-02-21 04:24:08,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:08,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:08,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:08,375 INFO L290 TraceCheckUtils]: 0: Hoare triple {5035#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {5035#true} is VALID [2022-02-21 04:24:08,376 INFO L290 TraceCheckUtils]: 1: Hoare triple {5035#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {5037#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:08,376 INFO L290 TraceCheckUtils]: 2: Hoare triple {5037#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {5037#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:08,377 INFO L290 TraceCheckUtils]: 3: Hoare triple {5037#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {5037#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:08,377 INFO L290 TraceCheckUtils]: 4: Hoare triple {5037#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {5037#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:08,377 INFO L290 TraceCheckUtils]: 5: Hoare triple {5037#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {5037#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:08,378 INFO L290 TraceCheckUtils]: 6: Hoare triple {5037#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {5037#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:08,378 INFO L290 TraceCheckUtils]: 7: Hoare triple {5037#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {5037#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:08,378 INFO L290 TraceCheckUtils]: 8: Hoare triple {5037#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {5036#false} is VALID [2022-02-21 04:24:08,378 INFO L290 TraceCheckUtils]: 9: Hoare triple {5036#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {5036#false} is VALID [2022-02-21 04:24:08,379 INFO L290 TraceCheckUtils]: 10: Hoare triple {5036#false} assume !(0 == ~M_E~0); {5036#false} is VALID [2022-02-21 04:24:08,379 INFO L290 TraceCheckUtils]: 11: Hoare triple {5036#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {5036#false} is VALID [2022-02-21 04:24:08,379 INFO L290 TraceCheckUtils]: 12: Hoare triple {5036#false} assume !(0 == ~T2_E~0); {5036#false} is VALID [2022-02-21 04:24:08,379 INFO L290 TraceCheckUtils]: 13: Hoare triple {5036#false} assume !(0 == ~T3_E~0); {5036#false} is VALID [2022-02-21 04:24:08,380 INFO L290 TraceCheckUtils]: 14: Hoare triple {5036#false} assume !(0 == ~T4_E~0); {5036#false} is VALID [2022-02-21 04:24:08,380 INFO L290 TraceCheckUtils]: 15: Hoare triple {5036#false} assume !(0 == ~E_1~0); {5036#false} is VALID [2022-02-21 04:24:08,380 INFO L290 TraceCheckUtils]: 16: Hoare triple {5036#false} assume !(0 == ~E_2~0); {5036#false} is VALID [2022-02-21 04:24:08,380 INFO L290 TraceCheckUtils]: 17: Hoare triple {5036#false} assume !(0 == ~E_3~0); {5036#false} is VALID [2022-02-21 04:24:08,380 INFO L290 TraceCheckUtils]: 18: Hoare triple {5036#false} assume !(0 == ~E_4~0); {5036#false} is VALID [2022-02-21 04:24:08,381 INFO L290 TraceCheckUtils]: 19: Hoare triple {5036#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5036#false} is VALID [2022-02-21 04:24:08,381 INFO L290 TraceCheckUtils]: 20: Hoare triple {5036#false} assume 1 == ~m_pc~0; {5036#false} is VALID [2022-02-21 04:24:08,381 INFO L290 TraceCheckUtils]: 21: Hoare triple {5036#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {5036#false} is VALID [2022-02-21 04:24:08,381 INFO L290 TraceCheckUtils]: 22: Hoare triple {5036#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5036#false} is VALID [2022-02-21 04:24:08,381 INFO L290 TraceCheckUtils]: 23: Hoare triple {5036#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {5036#false} is VALID [2022-02-21 04:24:08,381 INFO L290 TraceCheckUtils]: 24: Hoare triple {5036#false} assume !(0 != activate_threads_~tmp~1#1); {5036#false} is VALID [2022-02-21 04:24:08,381 INFO L290 TraceCheckUtils]: 25: Hoare triple {5036#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5036#false} is VALID [2022-02-21 04:24:08,381 INFO L290 TraceCheckUtils]: 26: Hoare triple {5036#false} assume 1 == ~t1_pc~0; {5036#false} is VALID [2022-02-21 04:24:08,381 INFO L290 TraceCheckUtils]: 27: Hoare triple {5036#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {5036#false} is VALID [2022-02-21 04:24:08,382 INFO L290 TraceCheckUtils]: 28: Hoare triple {5036#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5036#false} is VALID [2022-02-21 04:24:08,382 INFO L290 TraceCheckUtils]: 29: Hoare triple {5036#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {5036#false} is VALID [2022-02-21 04:24:08,382 INFO L290 TraceCheckUtils]: 30: Hoare triple {5036#false} assume !(0 != activate_threads_~tmp___0~0#1); {5036#false} is VALID [2022-02-21 04:24:08,382 INFO L290 TraceCheckUtils]: 31: Hoare triple {5036#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5036#false} is VALID [2022-02-21 04:24:08,382 INFO L290 TraceCheckUtils]: 32: Hoare triple {5036#false} assume !(1 == ~t2_pc~0); {5036#false} is VALID [2022-02-21 04:24:08,382 INFO L290 TraceCheckUtils]: 33: Hoare triple {5036#false} is_transmit2_triggered_~__retres1~2#1 := 0; {5036#false} is VALID [2022-02-21 04:24:08,382 INFO L290 TraceCheckUtils]: 34: Hoare triple {5036#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5036#false} is VALID [2022-02-21 04:24:08,382 INFO L290 TraceCheckUtils]: 35: Hoare triple {5036#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {5036#false} is VALID [2022-02-21 04:24:08,382 INFO L290 TraceCheckUtils]: 36: Hoare triple {5036#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {5036#false} is VALID [2022-02-21 04:24:08,382 INFO L290 TraceCheckUtils]: 37: Hoare triple {5036#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5036#false} is VALID [2022-02-21 04:24:08,383 INFO L290 TraceCheckUtils]: 38: Hoare triple {5036#false} assume 1 == ~t3_pc~0; {5036#false} is VALID [2022-02-21 04:24:08,383 INFO L290 TraceCheckUtils]: 39: Hoare triple {5036#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {5036#false} is VALID [2022-02-21 04:24:08,383 INFO L290 TraceCheckUtils]: 40: Hoare triple {5036#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5036#false} is VALID [2022-02-21 04:24:08,383 INFO L290 TraceCheckUtils]: 41: Hoare triple {5036#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {5036#false} is VALID [2022-02-21 04:24:08,383 INFO L290 TraceCheckUtils]: 42: Hoare triple {5036#false} assume !(0 != activate_threads_~tmp___2~0#1); {5036#false} is VALID [2022-02-21 04:24:08,383 INFO L290 TraceCheckUtils]: 43: Hoare triple {5036#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5036#false} is VALID [2022-02-21 04:24:08,383 INFO L290 TraceCheckUtils]: 44: Hoare triple {5036#false} assume !(1 == ~t4_pc~0); {5036#false} is VALID [2022-02-21 04:24:08,383 INFO L290 TraceCheckUtils]: 45: Hoare triple {5036#false} is_transmit4_triggered_~__retres1~4#1 := 0; {5036#false} is VALID [2022-02-21 04:24:08,383 INFO L290 TraceCheckUtils]: 46: Hoare triple {5036#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5036#false} is VALID [2022-02-21 04:24:08,384 INFO L290 TraceCheckUtils]: 47: Hoare triple {5036#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {5036#false} is VALID [2022-02-21 04:24:08,384 INFO L290 TraceCheckUtils]: 48: Hoare triple {5036#false} assume !(0 != activate_threads_~tmp___3~0#1); {5036#false} is VALID [2022-02-21 04:24:08,384 INFO L290 TraceCheckUtils]: 49: Hoare triple {5036#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5036#false} is VALID [2022-02-21 04:24:08,384 INFO L290 TraceCheckUtils]: 50: Hoare triple {5036#false} assume !(1 == ~M_E~0); {5036#false} is VALID [2022-02-21 04:24:08,384 INFO L290 TraceCheckUtils]: 51: Hoare triple {5036#false} assume !(1 == ~T1_E~0); {5036#false} is VALID [2022-02-21 04:24:08,384 INFO L290 TraceCheckUtils]: 52: Hoare triple {5036#false} assume !(1 == ~T2_E~0); {5036#false} is VALID [2022-02-21 04:24:08,384 INFO L290 TraceCheckUtils]: 53: Hoare triple {5036#false} assume !(1 == ~T3_E~0); {5036#false} is VALID [2022-02-21 04:24:08,384 INFO L290 TraceCheckUtils]: 54: Hoare triple {5036#false} assume !(1 == ~T4_E~0); {5036#false} is VALID [2022-02-21 04:24:08,384 INFO L290 TraceCheckUtils]: 55: Hoare triple {5036#false} assume !(1 == ~E_1~0); {5036#false} is VALID [2022-02-21 04:24:08,385 INFO L290 TraceCheckUtils]: 56: Hoare triple {5036#false} assume !(1 == ~E_2~0); {5036#false} is VALID [2022-02-21 04:24:08,385 INFO L290 TraceCheckUtils]: 57: Hoare triple {5036#false} assume 1 == ~E_3~0;~E_3~0 := 2; {5036#false} is VALID [2022-02-21 04:24:08,385 INFO L290 TraceCheckUtils]: 58: Hoare triple {5036#false} assume !(1 == ~E_4~0); {5036#false} is VALID [2022-02-21 04:24:08,385 INFO L290 TraceCheckUtils]: 59: Hoare triple {5036#false} assume { :end_inline_reset_delta_events } true; {5036#false} is VALID [2022-02-21 04:24:08,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:08,385 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:08,385 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2146733819] [2022-02-21 04:24:08,386 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2146733819] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:08,386 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:08,386 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:08,386 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933303530] [2022-02-21 04:24:08,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:08,386 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:08,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:08,387 INFO L85 PathProgramCache]: Analyzing trace with hash 1889290428, now seen corresponding path program 1 times [2022-02-21 04:24:08,387 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:08,387 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176591168] [2022-02-21 04:24:08,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:08,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:08,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:08,437 INFO L290 TraceCheckUtils]: 0: Hoare triple {5038#true} assume !false; {5038#true} is VALID [2022-02-21 04:24:08,437 INFO L290 TraceCheckUtils]: 1: Hoare triple {5038#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {5038#true} is VALID [2022-02-21 04:24:08,438 INFO L290 TraceCheckUtils]: 2: Hoare triple {5038#true} assume !false; {5038#true} is VALID [2022-02-21 04:24:08,438 INFO L290 TraceCheckUtils]: 3: Hoare triple {5038#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {5038#true} is VALID [2022-02-21 04:24:08,438 INFO L290 TraceCheckUtils]: 4: Hoare triple {5038#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {5038#true} is VALID [2022-02-21 04:24:08,438 INFO L290 TraceCheckUtils]: 5: Hoare triple {5038#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {5038#true} is VALID [2022-02-21 04:24:08,438 INFO L290 TraceCheckUtils]: 6: Hoare triple {5038#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {5038#true} is VALID [2022-02-21 04:24:08,438 INFO L290 TraceCheckUtils]: 7: Hoare triple {5038#true} assume !(0 != eval_~tmp~0#1); {5038#true} is VALID [2022-02-21 04:24:08,438 INFO L290 TraceCheckUtils]: 8: Hoare triple {5038#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {5038#true} is VALID [2022-02-21 04:24:08,439 INFO L290 TraceCheckUtils]: 9: Hoare triple {5038#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {5038#true} is VALID [2022-02-21 04:24:08,439 INFO L290 TraceCheckUtils]: 10: Hoare triple {5038#true} assume !(0 == ~M_E~0); {5038#true} is VALID [2022-02-21 04:24:08,439 INFO L290 TraceCheckUtils]: 11: Hoare triple {5038#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {5038#true} is VALID [2022-02-21 04:24:08,439 INFO L290 TraceCheckUtils]: 12: Hoare triple {5038#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {5038#true} is VALID [2022-02-21 04:24:08,439 INFO L290 TraceCheckUtils]: 13: Hoare triple {5038#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {5038#true} is VALID [2022-02-21 04:24:08,439 INFO L290 TraceCheckUtils]: 14: Hoare triple {5038#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {5038#true} is VALID [2022-02-21 04:24:08,439 INFO L290 TraceCheckUtils]: 15: Hoare triple {5038#true} assume 0 == ~E_1~0;~E_1~0 := 1; {5038#true} is VALID [2022-02-21 04:24:08,440 INFO L290 TraceCheckUtils]: 16: Hoare triple {5038#true} assume 0 == ~E_2~0;~E_2~0 := 1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,440 INFO L290 TraceCheckUtils]: 17: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,441 INFO L290 TraceCheckUtils]: 18: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,441 INFO L290 TraceCheckUtils]: 19: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,441 INFO L290 TraceCheckUtils]: 20: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~m_pc~0); {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,442 INFO L290 TraceCheckUtils]: 21: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,442 INFO L290 TraceCheckUtils]: 22: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,442 INFO L290 TraceCheckUtils]: 23: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,443 INFO L290 TraceCheckUtils]: 24: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,443 INFO L290 TraceCheckUtils]: 25: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,444 INFO L290 TraceCheckUtils]: 26: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,444 INFO L290 TraceCheckUtils]: 27: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,444 INFO L290 TraceCheckUtils]: 28: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,445 INFO L290 TraceCheckUtils]: 29: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,445 INFO L290 TraceCheckUtils]: 30: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,445 INFO L290 TraceCheckUtils]: 31: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,446 INFO L290 TraceCheckUtils]: 32: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t2_pc~0; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,446 INFO L290 TraceCheckUtils]: 33: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,446 INFO L290 TraceCheckUtils]: 34: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,447 INFO L290 TraceCheckUtils]: 35: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,447 INFO L290 TraceCheckUtils]: 36: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,448 INFO L290 TraceCheckUtils]: 37: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,448 INFO L290 TraceCheckUtils]: 38: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,448 INFO L290 TraceCheckUtils]: 39: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,449 INFO L290 TraceCheckUtils]: 40: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,449 INFO L290 TraceCheckUtils]: 41: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,449 INFO L290 TraceCheckUtils]: 42: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,450 INFO L290 TraceCheckUtils]: 43: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,450 INFO L290 TraceCheckUtils]: 44: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,450 INFO L290 TraceCheckUtils]: 45: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,451 INFO L290 TraceCheckUtils]: 46: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,451 INFO L290 TraceCheckUtils]: 47: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,453 INFO L290 TraceCheckUtils]: 48: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,453 INFO L290 TraceCheckUtils]: 49: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,454 INFO L290 TraceCheckUtils]: 50: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,454 INFO L290 TraceCheckUtils]: 51: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,454 INFO L290 TraceCheckUtils]: 52: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,455 INFO L290 TraceCheckUtils]: 53: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,455 INFO L290 TraceCheckUtils]: 54: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,456 INFO L290 TraceCheckUtils]: 55: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {5040#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,456 INFO L290 TraceCheckUtils]: 56: Hoare triple {5040#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {5039#false} is VALID [2022-02-21 04:24:08,456 INFO L290 TraceCheckUtils]: 57: Hoare triple {5039#false} assume 1 == ~E_3~0;~E_3~0 := 2; {5039#false} is VALID [2022-02-21 04:24:08,456 INFO L290 TraceCheckUtils]: 58: Hoare triple {5039#false} assume 1 == ~E_4~0;~E_4~0 := 2; {5039#false} is VALID [2022-02-21 04:24:08,456 INFO L290 TraceCheckUtils]: 59: Hoare triple {5039#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {5039#false} is VALID [2022-02-21 04:24:08,457 INFO L290 TraceCheckUtils]: 60: Hoare triple {5039#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {5039#false} is VALID [2022-02-21 04:24:08,457 INFO L290 TraceCheckUtils]: 61: Hoare triple {5039#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {5039#false} is VALID [2022-02-21 04:24:08,457 INFO L290 TraceCheckUtils]: 62: Hoare triple {5039#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {5039#false} is VALID [2022-02-21 04:24:08,457 INFO L290 TraceCheckUtils]: 63: Hoare triple {5039#false} assume !(0 == start_simulation_~tmp~3#1); {5039#false} is VALID [2022-02-21 04:24:08,457 INFO L290 TraceCheckUtils]: 64: Hoare triple {5039#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {5039#false} is VALID [2022-02-21 04:24:08,457 INFO L290 TraceCheckUtils]: 65: Hoare triple {5039#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {5039#false} is VALID [2022-02-21 04:24:08,457 INFO L290 TraceCheckUtils]: 66: Hoare triple {5039#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {5039#false} is VALID [2022-02-21 04:24:08,458 INFO L290 TraceCheckUtils]: 67: Hoare triple {5039#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {5039#false} is VALID [2022-02-21 04:24:08,458 INFO L290 TraceCheckUtils]: 68: Hoare triple {5039#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {5039#false} is VALID [2022-02-21 04:24:08,458 INFO L290 TraceCheckUtils]: 69: Hoare triple {5039#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {5039#false} is VALID [2022-02-21 04:24:08,458 INFO L290 TraceCheckUtils]: 70: Hoare triple {5039#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {5039#false} is VALID [2022-02-21 04:24:08,458 INFO L290 TraceCheckUtils]: 71: Hoare triple {5039#false} assume !(0 != start_simulation_~tmp___0~1#1); {5039#false} is VALID [2022-02-21 04:24:08,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:08,459 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:08,459 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [176591168] [2022-02-21 04:24:08,460 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [176591168] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:08,460 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:08,460 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:08,460 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262294675] [2022-02-21 04:24:08,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:08,461 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:08,461 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:08,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:08,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:08,462 INFO L87 Difference]: Start difference. First operand 384 states and 573 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:08,804 INFO L93 Difference]: Finished difference Result 384 states and 572 transitions. [2022-02-21 04:24:08,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:08,804 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,848 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:08,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 572 transitions. [2022-02-21 04:24:08,858 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-02-21 04:24:08,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 572 transitions. [2022-02-21 04:24:08,866 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-02-21 04:24:08,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-02-21 04:24:08,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 572 transitions. [2022-02-21 04:24:08,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:08,867 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2022-02-21 04:24:08,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 572 transitions. [2022-02-21 04:24:08,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-02-21 04:24:08,888 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:08,889 INFO L82 GeneralOperation]: Start isEquivalent. First operand 384 states and 572 transitions. Second operand has 384 states, 384 states have (on average 1.4895833333333333) internal successors, (572), 383 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,890 INFO L74 IsIncluded]: Start isIncluded. First operand 384 states and 572 transitions. Second operand has 384 states, 384 states have (on average 1.4895833333333333) internal successors, (572), 383 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,891 INFO L87 Difference]: Start difference. First operand 384 states and 572 transitions. Second operand has 384 states, 384 states have (on average 1.4895833333333333) internal successors, (572), 383 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:08,899 INFO L93 Difference]: Finished difference Result 384 states and 572 transitions. [2022-02-21 04:24:08,899 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 572 transitions. [2022-02-21 04:24:08,899 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:08,899 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:08,900 INFO L74 IsIncluded]: Start isIncluded. First operand has 384 states, 384 states have (on average 1.4895833333333333) internal successors, (572), 383 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 384 states and 572 transitions. [2022-02-21 04:24:08,901 INFO L87 Difference]: Start difference. First operand has 384 states, 384 states have (on average 1.4895833333333333) internal successors, (572), 383 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 384 states and 572 transitions. [2022-02-21 04:24:08,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:08,909 INFO L93 Difference]: Finished difference Result 384 states and 572 transitions. [2022-02-21 04:24:08,909 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 572 transitions. [2022-02-21 04:24:08,909 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:08,910 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:08,910 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:08,910 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:08,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4895833333333333) internal successors, (572), 383 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:08,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 572 transitions. [2022-02-21 04:24:08,918 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2022-02-21 04:24:08,918 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2022-02-21 04:24:08,918 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:08,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 572 transitions. [2022-02-21 04:24:08,920 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-02-21 04:24:08,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:08,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:08,921 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:08,921 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:08,921 INFO L791 eck$LassoCheckResult]: Stem: 5806#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5425#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5426#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5550#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 5656#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5509#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5510#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5522#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5523#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5568#L502 assume !(0 == ~M_E~0); 5569#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5500#L507-1 assume !(0 == ~T2_E~0); 5501#L512-1 assume !(0 == ~T3_E~0); 5658#L517-1 assume !(0 == ~T4_E~0); 5479#L522-1 assume !(0 == ~E_1~0); 5480#L527-1 assume !(0 == ~E_2~0); 5675#L532-1 assume !(0 == ~E_3~0); 5769#L537-1 assume !(0 == ~E_4~0); 5783#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5759#L238 assume 1 == ~m_pc~0; 5760#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5438#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5439#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5739#L615 assume !(0 != activate_threads_~tmp~1#1); 5461#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5462#L257 assume 1 == ~t1_pc~0; 5717#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5577#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5612#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5432#L623 assume !(0 != activate_threads_~tmp___0~0#1); 5433#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5427#L276 assume !(1 == ~t2_pc~0); 5428#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5688#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5524#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5525#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5794#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5738#L295 assume 1 == ~t3_pc~0; 5588#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5543#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5723#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5770#L639 assume !(0 != activate_threads_~tmp___2~0#1); 5763#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5764#L314 assume !(1 == ~t4_pc~0); 5580#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5579#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5765#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5715#L647 assume !(0 != activate_threads_~tmp___3~0#1); 5669#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5670#L555 assume !(1 == ~M_E~0); 5593#L555-2 assume !(1 == ~T1_E~0); 5594#L560-1 assume !(1 == ~T2_E~0); 5481#L565-1 assume !(1 == ~T3_E~0); 5482#L570-1 assume !(1 == ~T4_E~0); 5553#L575-1 assume !(1 == ~E_1~0); 5554#L580-1 assume !(1 == ~E_2~0); 5716#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5555#L590-1 assume !(1 == ~E_4~0); 5544#L595-1 assume { :end_inline_reset_delta_events } true; 5545#L776-2 [2022-02-21 04:24:08,922 INFO L793 eck$LassoCheckResult]: Loop: 5545#L776-2 assume !false; 5513#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5514#L477 assume !false; 5604#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5605#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5446#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5447#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5485#L416 assume !(0 != eval_~tmp~0#1); 5487#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5773#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5700#L502-3 assume !(0 == ~M_E~0); 5701#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5726#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5649#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5650#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5635#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5636#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5718#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5652#L537-3 assume !(0 == ~E_4~0); 5653#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5662#L238-15 assume 1 == ~m_pc~0; 5463#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5464#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5748#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5574#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5575#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5504#L257-15 assume !(1 == ~t1_pc~0); 5505#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 5696#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5787#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5740#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5741#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5754#L276-15 assume 1 == ~t2_pc~0; 5632#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5619#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5620#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5808#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5709#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5539#L295-15 assume !(1 == ~t3_pc~0); 5540#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 5737#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5781#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5802#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5771#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5772#L314-15 assume 1 == ~t4_pc~0; 5691#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5692#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5630#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5631#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5758#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5708#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5440#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5441#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5609#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5743#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5710#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5434#L580-3 assume !(1 == ~E_2~0); 5435#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5591#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5592#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5667#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5518#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5694#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5733#L795 assume !(0 == start_simulation_~tmp~3#1); 5735#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5755#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5476#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5621#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5622#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5600#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5601#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5668#L808 assume !(0 != start_simulation_~tmp___0~1#1); 5545#L776-2 [2022-02-21 04:24:08,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:08,922 INFO L85 PathProgramCache]: Analyzing trace with hash -1788857204, now seen corresponding path program 1 times [2022-02-21 04:24:08,922 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:08,922 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204338618] [2022-02-21 04:24:08,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:08,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:08,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:08,948 INFO L290 TraceCheckUtils]: 0: Hoare triple {6580#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,949 INFO L290 TraceCheckUtils]: 1: Hoare triple {6582#(<= 2 ~T1_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,949 INFO L290 TraceCheckUtils]: 2: Hoare triple {6582#(<= 2 ~T1_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,949 INFO L290 TraceCheckUtils]: 3: Hoare triple {6582#(<= 2 ~T1_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,950 INFO L290 TraceCheckUtils]: 4: Hoare triple {6582#(<= 2 ~T1_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,950 INFO L290 TraceCheckUtils]: 5: Hoare triple {6582#(<= 2 ~T1_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,950 INFO L290 TraceCheckUtils]: 6: Hoare triple {6582#(<= 2 ~T1_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,951 INFO L290 TraceCheckUtils]: 7: Hoare triple {6582#(<= 2 ~T1_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,951 INFO L290 TraceCheckUtils]: 8: Hoare triple {6582#(<= 2 ~T1_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,951 INFO L290 TraceCheckUtils]: 9: Hoare triple {6582#(<= 2 ~T1_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,952 INFO L290 TraceCheckUtils]: 10: Hoare triple {6582#(<= 2 ~T1_E~0)} assume !(0 == ~M_E~0); {6582#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:08,952 INFO L290 TraceCheckUtils]: 11: Hoare triple {6582#(<= 2 ~T1_E~0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {6581#false} is VALID [2022-02-21 04:24:08,952 INFO L290 TraceCheckUtils]: 12: Hoare triple {6581#false} assume !(0 == ~T2_E~0); {6581#false} is VALID [2022-02-21 04:24:08,952 INFO L290 TraceCheckUtils]: 13: Hoare triple {6581#false} assume !(0 == ~T3_E~0); {6581#false} is VALID [2022-02-21 04:24:08,952 INFO L290 TraceCheckUtils]: 14: Hoare triple {6581#false} assume !(0 == ~T4_E~0); {6581#false} is VALID [2022-02-21 04:24:08,952 INFO L290 TraceCheckUtils]: 15: Hoare triple {6581#false} assume !(0 == ~E_1~0); {6581#false} is VALID [2022-02-21 04:24:08,952 INFO L290 TraceCheckUtils]: 16: Hoare triple {6581#false} assume !(0 == ~E_2~0); {6581#false} is VALID [2022-02-21 04:24:08,953 INFO L290 TraceCheckUtils]: 17: Hoare triple {6581#false} assume !(0 == ~E_3~0); {6581#false} is VALID [2022-02-21 04:24:08,953 INFO L290 TraceCheckUtils]: 18: Hoare triple {6581#false} assume !(0 == ~E_4~0); {6581#false} is VALID [2022-02-21 04:24:08,953 INFO L290 TraceCheckUtils]: 19: Hoare triple {6581#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6581#false} is VALID [2022-02-21 04:24:08,953 INFO L290 TraceCheckUtils]: 20: Hoare triple {6581#false} assume 1 == ~m_pc~0; {6581#false} is VALID [2022-02-21 04:24:08,953 INFO L290 TraceCheckUtils]: 21: Hoare triple {6581#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {6581#false} is VALID [2022-02-21 04:24:08,953 INFO L290 TraceCheckUtils]: 22: Hoare triple {6581#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6581#false} is VALID [2022-02-21 04:24:08,953 INFO L290 TraceCheckUtils]: 23: Hoare triple {6581#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {6581#false} is VALID [2022-02-21 04:24:08,953 INFO L290 TraceCheckUtils]: 24: Hoare triple {6581#false} assume !(0 != activate_threads_~tmp~1#1); {6581#false} is VALID [2022-02-21 04:24:08,953 INFO L290 TraceCheckUtils]: 25: Hoare triple {6581#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6581#false} is VALID [2022-02-21 04:24:08,954 INFO L290 TraceCheckUtils]: 26: Hoare triple {6581#false} assume 1 == ~t1_pc~0; {6581#false} is VALID [2022-02-21 04:24:08,954 INFO L290 TraceCheckUtils]: 27: Hoare triple {6581#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {6581#false} is VALID [2022-02-21 04:24:08,954 INFO L290 TraceCheckUtils]: 28: Hoare triple {6581#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6581#false} is VALID [2022-02-21 04:24:08,954 INFO L290 TraceCheckUtils]: 29: Hoare triple {6581#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {6581#false} is VALID [2022-02-21 04:24:08,954 INFO L290 TraceCheckUtils]: 30: Hoare triple {6581#false} assume !(0 != activate_threads_~tmp___0~0#1); {6581#false} is VALID [2022-02-21 04:24:08,954 INFO L290 TraceCheckUtils]: 31: Hoare triple {6581#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6581#false} is VALID [2022-02-21 04:24:08,954 INFO L290 TraceCheckUtils]: 32: Hoare triple {6581#false} assume !(1 == ~t2_pc~0); {6581#false} is VALID [2022-02-21 04:24:08,954 INFO L290 TraceCheckUtils]: 33: Hoare triple {6581#false} is_transmit2_triggered_~__retres1~2#1 := 0; {6581#false} is VALID [2022-02-21 04:24:08,954 INFO L290 TraceCheckUtils]: 34: Hoare triple {6581#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6581#false} is VALID [2022-02-21 04:24:08,954 INFO L290 TraceCheckUtils]: 35: Hoare triple {6581#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {6581#false} is VALID [2022-02-21 04:24:08,955 INFO L290 TraceCheckUtils]: 36: Hoare triple {6581#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {6581#false} is VALID [2022-02-21 04:24:08,955 INFO L290 TraceCheckUtils]: 37: Hoare triple {6581#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6581#false} is VALID [2022-02-21 04:24:08,955 INFO L290 TraceCheckUtils]: 38: Hoare triple {6581#false} assume 1 == ~t3_pc~0; {6581#false} is VALID [2022-02-21 04:24:08,955 INFO L290 TraceCheckUtils]: 39: Hoare triple {6581#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6581#false} is VALID [2022-02-21 04:24:08,955 INFO L290 TraceCheckUtils]: 40: Hoare triple {6581#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6581#false} is VALID [2022-02-21 04:24:08,955 INFO L290 TraceCheckUtils]: 41: Hoare triple {6581#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {6581#false} is VALID [2022-02-21 04:24:08,955 INFO L290 TraceCheckUtils]: 42: Hoare triple {6581#false} assume !(0 != activate_threads_~tmp___2~0#1); {6581#false} is VALID [2022-02-21 04:24:08,955 INFO L290 TraceCheckUtils]: 43: Hoare triple {6581#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6581#false} is VALID [2022-02-21 04:24:08,955 INFO L290 TraceCheckUtils]: 44: Hoare triple {6581#false} assume !(1 == ~t4_pc~0); {6581#false} is VALID [2022-02-21 04:24:08,955 INFO L290 TraceCheckUtils]: 45: Hoare triple {6581#false} is_transmit4_triggered_~__retres1~4#1 := 0; {6581#false} is VALID [2022-02-21 04:24:08,956 INFO L290 TraceCheckUtils]: 46: Hoare triple {6581#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6581#false} is VALID [2022-02-21 04:24:08,956 INFO L290 TraceCheckUtils]: 47: Hoare triple {6581#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {6581#false} is VALID [2022-02-21 04:24:08,956 INFO L290 TraceCheckUtils]: 48: Hoare triple {6581#false} assume !(0 != activate_threads_~tmp___3~0#1); {6581#false} is VALID [2022-02-21 04:24:08,956 INFO L290 TraceCheckUtils]: 49: Hoare triple {6581#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6581#false} is VALID [2022-02-21 04:24:08,956 INFO L290 TraceCheckUtils]: 50: Hoare triple {6581#false} assume !(1 == ~M_E~0); {6581#false} is VALID [2022-02-21 04:24:08,956 INFO L290 TraceCheckUtils]: 51: Hoare triple {6581#false} assume !(1 == ~T1_E~0); {6581#false} is VALID [2022-02-21 04:24:08,956 INFO L290 TraceCheckUtils]: 52: Hoare triple {6581#false} assume !(1 == ~T2_E~0); {6581#false} is VALID [2022-02-21 04:24:08,956 INFO L290 TraceCheckUtils]: 53: Hoare triple {6581#false} assume !(1 == ~T3_E~0); {6581#false} is VALID [2022-02-21 04:24:08,956 INFO L290 TraceCheckUtils]: 54: Hoare triple {6581#false} assume !(1 == ~T4_E~0); {6581#false} is VALID [2022-02-21 04:24:08,957 INFO L290 TraceCheckUtils]: 55: Hoare triple {6581#false} assume !(1 == ~E_1~0); {6581#false} is VALID [2022-02-21 04:24:08,957 INFO L290 TraceCheckUtils]: 56: Hoare triple {6581#false} assume !(1 == ~E_2~0); {6581#false} is VALID [2022-02-21 04:24:08,957 INFO L290 TraceCheckUtils]: 57: Hoare triple {6581#false} assume 1 == ~E_3~0;~E_3~0 := 2; {6581#false} is VALID [2022-02-21 04:24:08,957 INFO L290 TraceCheckUtils]: 58: Hoare triple {6581#false} assume !(1 == ~E_4~0); {6581#false} is VALID [2022-02-21 04:24:08,957 INFO L290 TraceCheckUtils]: 59: Hoare triple {6581#false} assume { :end_inline_reset_delta_events } true; {6581#false} is VALID [2022-02-21 04:24:08,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:08,957 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:08,957 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1204338618] [2022-02-21 04:24:08,958 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1204338618] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:08,958 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:08,958 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:08,958 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1611239837] [2022-02-21 04:24:08,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:08,958 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:08,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:08,959 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 2 times [2022-02-21 04:24:08,959 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:08,959 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718948126] [2022-02-21 04:24:08,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:08,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:08,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:08,993 INFO L290 TraceCheckUtils]: 0: Hoare triple {6583#true} assume !false; {6583#true} is VALID [2022-02-21 04:24:08,993 INFO L290 TraceCheckUtils]: 1: Hoare triple {6583#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {6583#true} is VALID [2022-02-21 04:24:08,993 INFO L290 TraceCheckUtils]: 2: Hoare triple {6583#true} assume !false; {6583#true} is VALID [2022-02-21 04:24:08,993 INFO L290 TraceCheckUtils]: 3: Hoare triple {6583#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {6583#true} is VALID [2022-02-21 04:24:08,993 INFO L290 TraceCheckUtils]: 4: Hoare triple {6583#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {6583#true} is VALID [2022-02-21 04:24:08,994 INFO L290 TraceCheckUtils]: 5: Hoare triple {6583#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {6583#true} is VALID [2022-02-21 04:24:08,994 INFO L290 TraceCheckUtils]: 6: Hoare triple {6583#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {6583#true} is VALID [2022-02-21 04:24:08,994 INFO L290 TraceCheckUtils]: 7: Hoare triple {6583#true} assume !(0 != eval_~tmp~0#1); {6583#true} is VALID [2022-02-21 04:24:08,994 INFO L290 TraceCheckUtils]: 8: Hoare triple {6583#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {6583#true} is VALID [2022-02-21 04:24:08,994 INFO L290 TraceCheckUtils]: 9: Hoare triple {6583#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {6583#true} is VALID [2022-02-21 04:24:08,994 INFO L290 TraceCheckUtils]: 10: Hoare triple {6583#true} assume !(0 == ~M_E~0); {6583#true} is VALID [2022-02-21 04:24:08,994 INFO L290 TraceCheckUtils]: 11: Hoare triple {6583#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {6583#true} is VALID [2022-02-21 04:24:08,995 INFO L290 TraceCheckUtils]: 12: Hoare triple {6583#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {6583#true} is VALID [2022-02-21 04:24:08,995 INFO L290 TraceCheckUtils]: 13: Hoare triple {6583#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6583#true} is VALID [2022-02-21 04:24:08,995 INFO L290 TraceCheckUtils]: 14: Hoare triple {6583#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {6583#true} is VALID [2022-02-21 04:24:08,995 INFO L290 TraceCheckUtils]: 15: Hoare triple {6583#true} assume 0 == ~E_1~0;~E_1~0 := 1; {6583#true} is VALID [2022-02-21 04:24:08,996 INFO L290 TraceCheckUtils]: 16: Hoare triple {6583#true} assume 0 == ~E_2~0;~E_2~0 := 1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,996 INFO L290 TraceCheckUtils]: 17: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,996 INFO L290 TraceCheckUtils]: 18: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,997 INFO L290 TraceCheckUtils]: 19: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,997 INFO L290 TraceCheckUtils]: 20: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~m_pc~0; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,997 INFO L290 TraceCheckUtils]: 21: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,998 INFO L290 TraceCheckUtils]: 22: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,998 INFO L290 TraceCheckUtils]: 23: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,998 INFO L290 TraceCheckUtils]: 24: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,999 INFO L290 TraceCheckUtils]: 25: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:08,999 INFO L290 TraceCheckUtils]: 26: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,000 INFO L290 TraceCheckUtils]: 27: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,000 INFO L290 TraceCheckUtils]: 28: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,000 INFO L290 TraceCheckUtils]: 29: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,001 INFO L290 TraceCheckUtils]: 30: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,001 INFO L290 TraceCheckUtils]: 31: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,001 INFO L290 TraceCheckUtils]: 32: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t2_pc~0; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,002 INFO L290 TraceCheckUtils]: 33: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,002 INFO L290 TraceCheckUtils]: 34: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,002 INFO L290 TraceCheckUtils]: 35: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,003 INFO L290 TraceCheckUtils]: 36: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,003 INFO L290 TraceCheckUtils]: 37: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,003 INFO L290 TraceCheckUtils]: 38: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,004 INFO L290 TraceCheckUtils]: 39: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,004 INFO L290 TraceCheckUtils]: 40: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,004 INFO L290 TraceCheckUtils]: 41: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,005 INFO L290 TraceCheckUtils]: 42: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,005 INFO L290 TraceCheckUtils]: 43: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,005 INFO L290 TraceCheckUtils]: 44: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,006 INFO L290 TraceCheckUtils]: 45: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,006 INFO L290 TraceCheckUtils]: 46: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,006 INFO L290 TraceCheckUtils]: 47: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,007 INFO L290 TraceCheckUtils]: 48: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,007 INFO L290 TraceCheckUtils]: 49: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,008 INFO L290 TraceCheckUtils]: 50: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,008 INFO L290 TraceCheckUtils]: 51: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,008 INFO L290 TraceCheckUtils]: 52: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,009 INFO L290 TraceCheckUtils]: 53: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,009 INFO L290 TraceCheckUtils]: 54: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,009 INFO L290 TraceCheckUtils]: 55: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {6585#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,010 INFO L290 TraceCheckUtils]: 56: Hoare triple {6585#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {6584#false} is VALID [2022-02-21 04:24:09,010 INFO L290 TraceCheckUtils]: 57: Hoare triple {6584#false} assume 1 == ~E_3~0;~E_3~0 := 2; {6584#false} is VALID [2022-02-21 04:24:09,010 INFO L290 TraceCheckUtils]: 58: Hoare triple {6584#false} assume 1 == ~E_4~0;~E_4~0 := 2; {6584#false} is VALID [2022-02-21 04:24:09,010 INFO L290 TraceCheckUtils]: 59: Hoare triple {6584#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {6584#false} is VALID [2022-02-21 04:24:09,010 INFO L290 TraceCheckUtils]: 60: Hoare triple {6584#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {6584#false} is VALID [2022-02-21 04:24:09,010 INFO L290 TraceCheckUtils]: 61: Hoare triple {6584#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {6584#false} is VALID [2022-02-21 04:24:09,010 INFO L290 TraceCheckUtils]: 62: Hoare triple {6584#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {6584#false} is VALID [2022-02-21 04:24:09,011 INFO L290 TraceCheckUtils]: 63: Hoare triple {6584#false} assume !(0 == start_simulation_~tmp~3#1); {6584#false} is VALID [2022-02-21 04:24:09,011 INFO L290 TraceCheckUtils]: 64: Hoare triple {6584#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {6584#false} is VALID [2022-02-21 04:24:09,011 INFO L290 TraceCheckUtils]: 65: Hoare triple {6584#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {6584#false} is VALID [2022-02-21 04:24:09,011 INFO L290 TraceCheckUtils]: 66: Hoare triple {6584#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {6584#false} is VALID [2022-02-21 04:24:09,011 INFO L290 TraceCheckUtils]: 67: Hoare triple {6584#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {6584#false} is VALID [2022-02-21 04:24:09,011 INFO L290 TraceCheckUtils]: 68: Hoare triple {6584#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {6584#false} is VALID [2022-02-21 04:24:09,012 INFO L290 TraceCheckUtils]: 69: Hoare triple {6584#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {6584#false} is VALID [2022-02-21 04:24:09,012 INFO L290 TraceCheckUtils]: 70: Hoare triple {6584#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {6584#false} is VALID [2022-02-21 04:24:09,012 INFO L290 TraceCheckUtils]: 71: Hoare triple {6584#false} assume !(0 != start_simulation_~tmp___0~1#1); {6584#false} is VALID [2022-02-21 04:24:09,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:09,012 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:09,013 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718948126] [2022-02-21 04:24:09,013 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1718948126] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:09,013 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:09,013 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:09,013 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881310479] [2022-02-21 04:24:09,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:09,014 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:09,014 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:09,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:09,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:09,015 INFO L87 Difference]: Start difference. First operand 384 states and 572 transitions. cyclomatic complexity: 189 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:09,358 INFO L93 Difference]: Finished difference Result 384 states and 567 transitions. [2022-02-21 04:24:09,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:09,358 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,402 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:09,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 567 transitions. [2022-02-21 04:24:09,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-02-21 04:24:09,418 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 567 transitions. [2022-02-21 04:24:09,418 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-02-21 04:24:09,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-02-21 04:24:09,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 567 transitions. [2022-02-21 04:24:09,418 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:09,419 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 567 transitions. [2022-02-21 04:24:09,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 567 transitions. [2022-02-21 04:24:09,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-02-21 04:24:09,422 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:09,423 INFO L82 GeneralOperation]: Start isEquivalent. First operand 384 states and 567 transitions. Second operand has 384 states, 384 states have (on average 1.4765625) internal successors, (567), 383 states have internal predecessors, (567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,424 INFO L74 IsIncluded]: Start isIncluded. First operand 384 states and 567 transitions. Second operand has 384 states, 384 states have (on average 1.4765625) internal successors, (567), 383 states have internal predecessors, (567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,425 INFO L87 Difference]: Start difference. First operand 384 states and 567 transitions. Second operand has 384 states, 384 states have (on average 1.4765625) internal successors, (567), 383 states have internal predecessors, (567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:09,432 INFO L93 Difference]: Finished difference Result 384 states and 567 transitions. [2022-02-21 04:24:09,432 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 567 transitions. [2022-02-21 04:24:09,433 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:09,433 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:09,433 INFO L74 IsIncluded]: Start isIncluded. First operand has 384 states, 384 states have (on average 1.4765625) internal successors, (567), 383 states have internal predecessors, (567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 384 states and 567 transitions. [2022-02-21 04:24:09,434 INFO L87 Difference]: Start difference. First operand has 384 states, 384 states have (on average 1.4765625) internal successors, (567), 383 states have internal predecessors, (567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 384 states and 567 transitions. [2022-02-21 04:24:09,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:09,442 INFO L93 Difference]: Finished difference Result 384 states and 567 transitions. [2022-02-21 04:24:09,442 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 567 transitions. [2022-02-21 04:24:09,442 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:09,442 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:09,442 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:09,442 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:09,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4765625) internal successors, (567), 383 states have internal predecessors, (567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 567 transitions. [2022-02-21 04:24:09,450 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 567 transitions. [2022-02-21 04:24:09,450 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 567 transitions. [2022-02-21 04:24:09,450 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:09,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 567 transitions. [2022-02-21 04:24:09,452 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-02-21 04:24:09,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:09,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:09,457 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:09,457 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:09,458 INFO L791 eck$LassoCheckResult]: Stem: 7351#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 7320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6970#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6971#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7095#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 7201#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7054#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7055#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7067#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7068#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7113#L502 assume !(0 == ~M_E~0); 7114#L502-2 assume !(0 == ~T1_E~0); 7045#L507-1 assume !(0 == ~T2_E~0); 7046#L512-1 assume !(0 == ~T3_E~0); 7203#L517-1 assume !(0 == ~T4_E~0); 7024#L522-1 assume !(0 == ~E_1~0); 7025#L527-1 assume !(0 == ~E_2~0); 7220#L532-1 assume !(0 == ~E_3~0); 7314#L537-1 assume !(0 == ~E_4~0); 7328#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7304#L238 assume 1 == ~m_pc~0; 7305#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6983#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6984#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7284#L615 assume !(0 != activate_threads_~tmp~1#1); 7006#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7007#L257 assume 1 == ~t1_pc~0; 7262#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7122#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7157#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6977#L623 assume !(0 != activate_threads_~tmp___0~0#1); 6978#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6972#L276 assume !(1 == ~t2_pc~0); 6973#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7233#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7069#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7070#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7339#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7283#L295 assume 1 == ~t3_pc~0; 7133#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7088#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7268#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7315#L639 assume !(0 != activate_threads_~tmp___2~0#1); 7308#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7309#L314 assume !(1 == ~t4_pc~0); 7125#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7124#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7310#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7260#L647 assume !(0 != activate_threads_~tmp___3~0#1); 7214#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7215#L555 assume !(1 == ~M_E~0); 7138#L555-2 assume !(1 == ~T1_E~0); 7139#L560-1 assume !(1 == ~T2_E~0); 7026#L565-1 assume !(1 == ~T3_E~0); 7027#L570-1 assume !(1 == ~T4_E~0); 7098#L575-1 assume !(1 == ~E_1~0); 7099#L580-1 assume !(1 == ~E_2~0); 7261#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 7100#L590-1 assume !(1 == ~E_4~0); 7089#L595-1 assume { :end_inline_reset_delta_events } true; 7090#L776-2 [2022-02-21 04:24:09,458 INFO L793 eck$LassoCheckResult]: Loop: 7090#L776-2 assume !false; 7058#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7059#L477 assume !false; 7149#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7150#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6989#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6990#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7030#L416 assume !(0 != eval_~tmp~0#1); 7032#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7318#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7245#L502-3 assume !(0 == ~M_E~0); 7246#L502-5 assume !(0 == ~T1_E~0); 7271#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7194#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7195#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7180#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7181#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7263#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7197#L537-3 assume !(0 == ~E_4~0); 7198#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7207#L238-15 assume 1 == ~m_pc~0; 7008#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7009#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7293#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7119#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7120#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7049#L257-15 assume !(1 == ~t1_pc~0); 7050#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 7241#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7332#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7285#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7286#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7299#L276-15 assume 1 == ~t2_pc~0; 7177#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7164#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7165#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7353#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7254#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7084#L295-15 assume !(1 == ~t3_pc~0); 7085#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 7282#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7326#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7347#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7316#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7317#L314-15 assume 1 == ~t4_pc~0; 7236#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7237#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7175#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7176#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7303#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7253#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6985#L555-5 assume !(1 == ~T1_E~0); 6986#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7154#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7288#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7255#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6979#L580-3 assume !(1 == ~E_2~0); 6980#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7136#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7137#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7212#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7063#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7239#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 7278#L795 assume !(0 == start_simulation_~tmp~3#1); 7280#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7300#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7021#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7166#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 7167#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7145#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7146#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7213#L808 assume !(0 != start_simulation_~tmp___0~1#1); 7090#L776-2 [2022-02-21 04:24:09,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:09,458 INFO L85 PathProgramCache]: Analyzing trace with hash -1804375922, now seen corresponding path program 1 times [2022-02-21 04:24:09,459 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:09,459 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018120565] [2022-02-21 04:24:09,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:09,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:09,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:09,482 INFO L290 TraceCheckUtils]: 0: Hoare triple {8125#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,483 INFO L290 TraceCheckUtils]: 1: Hoare triple {8127#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,483 INFO L290 TraceCheckUtils]: 2: Hoare triple {8127#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,483 INFO L290 TraceCheckUtils]: 3: Hoare triple {8127#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,484 INFO L290 TraceCheckUtils]: 4: Hoare triple {8127#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,484 INFO L290 TraceCheckUtils]: 5: Hoare triple {8127#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,484 INFO L290 TraceCheckUtils]: 6: Hoare triple {8127#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,485 INFO L290 TraceCheckUtils]: 7: Hoare triple {8127#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,485 INFO L290 TraceCheckUtils]: 8: Hoare triple {8127#(= ~m_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,485 INFO L290 TraceCheckUtils]: 9: Hoare triple {8127#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,486 INFO L290 TraceCheckUtils]: 10: Hoare triple {8127#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,486 INFO L290 TraceCheckUtils]: 11: Hoare triple {8127#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,486 INFO L290 TraceCheckUtils]: 12: Hoare triple {8127#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,487 INFO L290 TraceCheckUtils]: 13: Hoare triple {8127#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,487 INFO L290 TraceCheckUtils]: 14: Hoare triple {8127#(= ~m_pc~0 0)} assume !(0 == ~T4_E~0); {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,487 INFO L290 TraceCheckUtils]: 15: Hoare triple {8127#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,488 INFO L290 TraceCheckUtils]: 16: Hoare triple {8127#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,488 INFO L290 TraceCheckUtils]: 17: Hoare triple {8127#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,488 INFO L290 TraceCheckUtils]: 18: Hoare triple {8127#(= ~m_pc~0 0)} assume !(0 == ~E_4~0); {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,489 INFO L290 TraceCheckUtils]: 19: Hoare triple {8127#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8127#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:09,489 INFO L290 TraceCheckUtils]: 20: Hoare triple {8127#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {8126#false} is VALID [2022-02-21 04:24:09,489 INFO L290 TraceCheckUtils]: 21: Hoare triple {8126#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {8126#false} is VALID [2022-02-21 04:24:09,489 INFO L290 TraceCheckUtils]: 22: Hoare triple {8126#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8126#false} is VALID [2022-02-21 04:24:09,489 INFO L290 TraceCheckUtils]: 23: Hoare triple {8126#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {8126#false} is VALID [2022-02-21 04:24:09,489 INFO L290 TraceCheckUtils]: 24: Hoare triple {8126#false} assume !(0 != activate_threads_~tmp~1#1); {8126#false} is VALID [2022-02-21 04:24:09,490 INFO L290 TraceCheckUtils]: 25: Hoare triple {8126#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8126#false} is VALID [2022-02-21 04:24:09,492 INFO L290 TraceCheckUtils]: 26: Hoare triple {8126#false} assume 1 == ~t1_pc~0; {8126#false} is VALID [2022-02-21 04:24:09,492 INFO L290 TraceCheckUtils]: 27: Hoare triple {8126#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {8126#false} is VALID [2022-02-21 04:24:09,493 INFO L290 TraceCheckUtils]: 28: Hoare triple {8126#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8126#false} is VALID [2022-02-21 04:24:09,493 INFO L290 TraceCheckUtils]: 29: Hoare triple {8126#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {8126#false} is VALID [2022-02-21 04:24:09,493 INFO L290 TraceCheckUtils]: 30: Hoare triple {8126#false} assume !(0 != activate_threads_~tmp___0~0#1); {8126#false} is VALID [2022-02-21 04:24:09,493 INFO L290 TraceCheckUtils]: 31: Hoare triple {8126#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8126#false} is VALID [2022-02-21 04:24:09,493 INFO L290 TraceCheckUtils]: 32: Hoare triple {8126#false} assume !(1 == ~t2_pc~0); {8126#false} is VALID [2022-02-21 04:24:09,493 INFO L290 TraceCheckUtils]: 33: Hoare triple {8126#false} is_transmit2_triggered_~__retres1~2#1 := 0; {8126#false} is VALID [2022-02-21 04:24:09,493 INFO L290 TraceCheckUtils]: 34: Hoare triple {8126#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8126#false} is VALID [2022-02-21 04:24:09,494 INFO L290 TraceCheckUtils]: 35: Hoare triple {8126#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {8126#false} is VALID [2022-02-21 04:24:09,494 INFO L290 TraceCheckUtils]: 36: Hoare triple {8126#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8126#false} is VALID [2022-02-21 04:24:09,494 INFO L290 TraceCheckUtils]: 37: Hoare triple {8126#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8126#false} is VALID [2022-02-21 04:24:09,494 INFO L290 TraceCheckUtils]: 38: Hoare triple {8126#false} assume 1 == ~t3_pc~0; {8126#false} is VALID [2022-02-21 04:24:09,494 INFO L290 TraceCheckUtils]: 39: Hoare triple {8126#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8126#false} is VALID [2022-02-21 04:24:09,494 INFO L290 TraceCheckUtils]: 40: Hoare triple {8126#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8126#false} is VALID [2022-02-21 04:24:09,494 INFO L290 TraceCheckUtils]: 41: Hoare triple {8126#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {8126#false} is VALID [2022-02-21 04:24:09,495 INFO L290 TraceCheckUtils]: 42: Hoare triple {8126#false} assume !(0 != activate_threads_~tmp___2~0#1); {8126#false} is VALID [2022-02-21 04:24:09,495 INFO L290 TraceCheckUtils]: 43: Hoare triple {8126#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8126#false} is VALID [2022-02-21 04:24:09,495 INFO L290 TraceCheckUtils]: 44: Hoare triple {8126#false} assume !(1 == ~t4_pc~0); {8126#false} is VALID [2022-02-21 04:24:09,495 INFO L290 TraceCheckUtils]: 45: Hoare triple {8126#false} is_transmit4_triggered_~__retres1~4#1 := 0; {8126#false} is VALID [2022-02-21 04:24:09,495 INFO L290 TraceCheckUtils]: 46: Hoare triple {8126#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8126#false} is VALID [2022-02-21 04:24:09,510 INFO L290 TraceCheckUtils]: 47: Hoare triple {8126#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8126#false} is VALID [2022-02-21 04:24:09,510 INFO L290 TraceCheckUtils]: 48: Hoare triple {8126#false} assume !(0 != activate_threads_~tmp___3~0#1); {8126#false} is VALID [2022-02-21 04:24:09,510 INFO L290 TraceCheckUtils]: 49: Hoare triple {8126#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8126#false} is VALID [2022-02-21 04:24:09,510 INFO L290 TraceCheckUtils]: 50: Hoare triple {8126#false} assume !(1 == ~M_E~0); {8126#false} is VALID [2022-02-21 04:24:09,510 INFO L290 TraceCheckUtils]: 51: Hoare triple {8126#false} assume !(1 == ~T1_E~0); {8126#false} is VALID [2022-02-21 04:24:09,510 INFO L290 TraceCheckUtils]: 52: Hoare triple {8126#false} assume !(1 == ~T2_E~0); {8126#false} is VALID [2022-02-21 04:24:09,511 INFO L290 TraceCheckUtils]: 53: Hoare triple {8126#false} assume !(1 == ~T3_E~0); {8126#false} is VALID [2022-02-21 04:24:09,511 INFO L290 TraceCheckUtils]: 54: Hoare triple {8126#false} assume !(1 == ~T4_E~0); {8126#false} is VALID [2022-02-21 04:24:09,511 INFO L290 TraceCheckUtils]: 55: Hoare triple {8126#false} assume !(1 == ~E_1~0); {8126#false} is VALID [2022-02-21 04:24:09,511 INFO L290 TraceCheckUtils]: 56: Hoare triple {8126#false} assume !(1 == ~E_2~0); {8126#false} is VALID [2022-02-21 04:24:09,511 INFO L290 TraceCheckUtils]: 57: Hoare triple {8126#false} assume 1 == ~E_3~0;~E_3~0 := 2; {8126#false} is VALID [2022-02-21 04:24:09,511 INFO L290 TraceCheckUtils]: 58: Hoare triple {8126#false} assume !(1 == ~E_4~0); {8126#false} is VALID [2022-02-21 04:24:09,512 INFO L290 TraceCheckUtils]: 59: Hoare triple {8126#false} assume { :end_inline_reset_delta_events } true; {8126#false} is VALID [2022-02-21 04:24:09,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:09,512 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:09,512 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018120565] [2022-02-21 04:24:09,513 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018120565] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:09,513 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:09,513 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:09,513 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805549894] [2022-02-21 04:24:09,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:09,514 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:09,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:09,514 INFO L85 PathProgramCache]: Analyzing trace with hash 680167841, now seen corresponding path program 1 times [2022-02-21 04:24:09,514 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:09,514 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145434575] [2022-02-21 04:24:09,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:09,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:09,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:09,560 INFO L290 TraceCheckUtils]: 0: Hoare triple {8128#true} assume !false; {8128#true} is VALID [2022-02-21 04:24:09,560 INFO L290 TraceCheckUtils]: 1: Hoare triple {8128#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {8128#true} is VALID [2022-02-21 04:24:09,560 INFO L290 TraceCheckUtils]: 2: Hoare triple {8128#true} assume !false; {8128#true} is VALID [2022-02-21 04:24:09,560 INFO L290 TraceCheckUtils]: 3: Hoare triple {8128#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {8128#true} is VALID [2022-02-21 04:24:09,560 INFO L290 TraceCheckUtils]: 4: Hoare triple {8128#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 5: Hoare triple {8128#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 6: Hoare triple {8128#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 7: Hoare triple {8128#true} assume !(0 != eval_~tmp~0#1); {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 8: Hoare triple {8128#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 9: Hoare triple {8128#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 10: Hoare triple {8128#true} assume !(0 == ~M_E~0); {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 11: Hoare triple {8128#true} assume !(0 == ~T1_E~0); {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 12: Hoare triple {8128#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 13: Hoare triple {8128#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 14: Hoare triple {8128#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {8128#true} is VALID [2022-02-21 04:24:09,561 INFO L290 TraceCheckUtils]: 15: Hoare triple {8128#true} assume 0 == ~E_1~0;~E_1~0 := 1; {8128#true} is VALID [2022-02-21 04:24:09,562 INFO L290 TraceCheckUtils]: 16: Hoare triple {8128#true} assume 0 == ~E_2~0;~E_2~0 := 1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,562 INFO L290 TraceCheckUtils]: 17: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,563 INFO L290 TraceCheckUtils]: 18: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,563 INFO L290 TraceCheckUtils]: 19: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,563 INFO L290 TraceCheckUtils]: 20: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~m_pc~0; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,564 INFO L290 TraceCheckUtils]: 21: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,564 INFO L290 TraceCheckUtils]: 22: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,564 INFO L290 TraceCheckUtils]: 23: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,565 INFO L290 TraceCheckUtils]: 24: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,565 INFO L290 TraceCheckUtils]: 25: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,565 INFO L290 TraceCheckUtils]: 26: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,566 INFO L290 TraceCheckUtils]: 27: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,566 INFO L290 TraceCheckUtils]: 28: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,566 INFO L290 TraceCheckUtils]: 29: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,567 INFO L290 TraceCheckUtils]: 30: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,567 INFO L290 TraceCheckUtils]: 31: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,567 INFO L290 TraceCheckUtils]: 32: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t2_pc~0; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,568 INFO L290 TraceCheckUtils]: 33: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,568 INFO L290 TraceCheckUtils]: 34: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,568 INFO L290 TraceCheckUtils]: 35: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,569 INFO L290 TraceCheckUtils]: 36: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,569 INFO L290 TraceCheckUtils]: 37: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,569 INFO L290 TraceCheckUtils]: 38: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,570 INFO L290 TraceCheckUtils]: 39: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,570 INFO L290 TraceCheckUtils]: 40: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,570 INFO L290 TraceCheckUtils]: 41: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,571 INFO L290 TraceCheckUtils]: 42: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,571 INFO L290 TraceCheckUtils]: 43: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,571 INFO L290 TraceCheckUtils]: 44: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,572 INFO L290 TraceCheckUtils]: 45: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,572 INFO L290 TraceCheckUtils]: 46: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,572 INFO L290 TraceCheckUtils]: 47: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,573 INFO L290 TraceCheckUtils]: 48: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,573 INFO L290 TraceCheckUtils]: 49: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,573 INFO L290 TraceCheckUtils]: 50: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,574 INFO L290 TraceCheckUtils]: 51: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T1_E~0); {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,574 INFO L290 TraceCheckUtils]: 52: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,574 INFO L290 TraceCheckUtils]: 53: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,575 INFO L290 TraceCheckUtils]: 54: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,575 INFO L290 TraceCheckUtils]: 55: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {8130#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:09,575 INFO L290 TraceCheckUtils]: 56: Hoare triple {8130#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {8129#false} is VALID [2022-02-21 04:24:09,576 INFO L290 TraceCheckUtils]: 57: Hoare triple {8129#false} assume 1 == ~E_3~0;~E_3~0 := 2; {8129#false} is VALID [2022-02-21 04:24:09,576 INFO L290 TraceCheckUtils]: 58: Hoare triple {8129#false} assume 1 == ~E_4~0;~E_4~0 := 2; {8129#false} is VALID [2022-02-21 04:24:09,576 INFO L290 TraceCheckUtils]: 59: Hoare triple {8129#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {8129#false} is VALID [2022-02-21 04:24:09,576 INFO L290 TraceCheckUtils]: 60: Hoare triple {8129#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {8129#false} is VALID [2022-02-21 04:24:09,576 INFO L290 TraceCheckUtils]: 61: Hoare triple {8129#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {8129#false} is VALID [2022-02-21 04:24:09,576 INFO L290 TraceCheckUtils]: 62: Hoare triple {8129#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {8129#false} is VALID [2022-02-21 04:24:09,576 INFO L290 TraceCheckUtils]: 63: Hoare triple {8129#false} assume !(0 == start_simulation_~tmp~3#1); {8129#false} is VALID [2022-02-21 04:24:09,577 INFO L290 TraceCheckUtils]: 64: Hoare triple {8129#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {8129#false} is VALID [2022-02-21 04:24:09,577 INFO L290 TraceCheckUtils]: 65: Hoare triple {8129#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {8129#false} is VALID [2022-02-21 04:24:09,577 INFO L290 TraceCheckUtils]: 66: Hoare triple {8129#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {8129#false} is VALID [2022-02-21 04:24:09,577 INFO L290 TraceCheckUtils]: 67: Hoare triple {8129#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {8129#false} is VALID [2022-02-21 04:24:09,577 INFO L290 TraceCheckUtils]: 68: Hoare triple {8129#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {8129#false} is VALID [2022-02-21 04:24:09,577 INFO L290 TraceCheckUtils]: 69: Hoare triple {8129#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8129#false} is VALID [2022-02-21 04:24:09,578 INFO L290 TraceCheckUtils]: 70: Hoare triple {8129#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {8129#false} is VALID [2022-02-21 04:24:09,578 INFO L290 TraceCheckUtils]: 71: Hoare triple {8129#false} assume !(0 != start_simulation_~tmp___0~1#1); {8129#false} is VALID [2022-02-21 04:24:09,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:09,578 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:09,579 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145434575] [2022-02-21 04:24:09,579 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1145434575] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:09,579 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:09,579 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:09,579 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [659317357] [2022-02-21 04:24:09,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:09,580 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:09,580 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:09,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:09,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:09,581 INFO L87 Difference]: Start difference. First operand 384 states and 567 transitions. cyclomatic complexity: 184 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:10,095 INFO L93 Difference]: Finished difference Result 694 states and 1012 transitions. [2022-02-21 04:24:10,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:10,095 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,150 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:10,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 694 states and 1012 transitions. [2022-02-21 04:24:10,174 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 629 [2022-02-21 04:24:10,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 694 states to 694 states and 1012 transitions. [2022-02-21 04:24:10,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 694 [2022-02-21 04:24:10,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 694 [2022-02-21 04:24:10,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 694 states and 1012 transitions. [2022-02-21 04:24:10,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:10,198 INFO L681 BuchiCegarLoop]: Abstraction has 694 states and 1012 transitions. [2022-02-21 04:24:10,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states and 1012 transitions. [2022-02-21 04:24:10,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 658. [2022-02-21 04:24:10,205 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:10,206 INFO L82 GeneralOperation]: Start isEquivalent. First operand 694 states and 1012 transitions. Second operand has 658 states, 658 states have (on average 1.4635258358662615) internal successors, (963), 657 states have internal predecessors, (963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,208 INFO L74 IsIncluded]: Start isIncluded. First operand 694 states and 1012 transitions. Second operand has 658 states, 658 states have (on average 1.4635258358662615) internal successors, (963), 657 states have internal predecessors, (963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,220 INFO L87 Difference]: Start difference. First operand 694 states and 1012 transitions. Second operand has 658 states, 658 states have (on average 1.4635258358662615) internal successors, (963), 657 states have internal predecessors, (963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:10,240 INFO L93 Difference]: Finished difference Result 694 states and 1012 transitions. [2022-02-21 04:24:10,240 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 1012 transitions. [2022-02-21 04:24:10,241 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:10,241 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:10,242 INFO L74 IsIncluded]: Start isIncluded. First operand has 658 states, 658 states have (on average 1.4635258358662615) internal successors, (963), 657 states have internal predecessors, (963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 694 states and 1012 transitions. [2022-02-21 04:24:10,244 INFO L87 Difference]: Start difference. First operand has 658 states, 658 states have (on average 1.4635258358662615) internal successors, (963), 657 states have internal predecessors, (963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 694 states and 1012 transitions. [2022-02-21 04:24:10,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:10,265 INFO L93 Difference]: Finished difference Result 694 states and 1012 transitions. [2022-02-21 04:24:10,265 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 1012 transitions. [2022-02-21 04:24:10,266 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:10,266 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:10,266 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:10,266 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:10,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 658 states, 658 states have (on average 1.4635258358662615) internal successors, (963), 657 states have internal predecessors, (963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 963 transitions. [2022-02-21 04:24:10,285 INFO L704 BuchiCegarLoop]: Abstraction has 658 states and 963 transitions. [2022-02-21 04:24:10,285 INFO L587 BuchiCegarLoop]: Abstraction has 658 states and 963 transitions. [2022-02-21 04:24:10,285 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:10,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 658 states and 963 transitions. [2022-02-21 04:24:10,288 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 593 [2022-02-21 04:24:10,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:10,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:10,289 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,289 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,289 INFO L791 eck$LassoCheckResult]: Stem: 9221#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 9181#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8825#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8826#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8950#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 9056#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8909#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8910#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8922#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8923#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8968#L502 assume !(0 == ~M_E~0); 8969#L502-2 assume !(0 == ~T1_E~0); 8900#L507-1 assume !(0 == ~T2_E~0); 8901#L512-1 assume !(0 == ~T3_E~0); 9058#L517-1 assume !(0 == ~T4_E~0); 8879#L522-1 assume !(0 == ~E_1~0); 8880#L527-1 assume !(0 == ~E_2~0); 9075#L532-1 assume !(0 == ~E_3~0); 9173#L537-1 assume !(0 == ~E_4~0); 9192#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9164#L238 assume !(1 == ~m_pc~0); 9165#L238-2 is_master_triggered_~__retres1~0#1 := 0; 8838#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8839#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9143#L615 assume !(0 != activate_threads_~tmp~1#1); 8861#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8862#L257 assume 1 == ~t1_pc~0; 9119#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8977#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9012#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8832#L623 assume !(0 != activate_threads_~tmp___0~0#1); 8833#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8827#L276 assume !(1 == ~t2_pc~0); 8828#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9087#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8924#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8925#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9205#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9142#L295 assume 1 == ~t3_pc~0; 8988#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8943#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9128#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9174#L639 assume !(0 != activate_threads_~tmp___2~0#1); 9167#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9168#L314 assume !(1 == ~t4_pc~0); 8980#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8979#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9169#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9117#L647 assume !(0 != activate_threads_~tmp___3~0#1); 9069#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9070#L555 assume !(1 == ~M_E~0); 8993#L555-2 assume !(1 == ~T1_E~0); 8994#L560-1 assume !(1 == ~T2_E~0); 8881#L565-1 assume !(1 == ~T3_E~0); 8882#L570-1 assume !(1 == ~T4_E~0); 8954#L575-1 assume !(1 == ~E_1~0); 8955#L580-1 assume !(1 == ~E_2~0); 9118#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 8953#L590-1 assume !(1 == ~E_4~0); 8944#L595-1 assume { :end_inline_reset_delta_events } true; 8945#L776-2 [2022-02-21 04:24:10,293 INFO L793 eck$LassoCheckResult]: Loop: 8945#L776-2 assume !false; 8913#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8914#L477 assume !false; 9004#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9005#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8844#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8845#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8885#L416 assume !(0 != eval_~tmp~0#1); 8887#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9177#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9099#L502-3 assume !(0 == ~M_E~0); 9100#L502-5 assume !(0 == ~T1_E~0); 9131#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9049#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9050#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9036#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9037#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9120#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9052#L537-3 assume !(0 == ~E_4~0); 9053#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9062#L238-15 assume !(1 == ~m_pc~0); 9111#L238-17 is_master_triggered_~__retres1~0#1 := 0; 9152#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9153#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8974#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8975#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8904#L257-15 assume !(1 == ~t1_pc~0); 8905#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 9095#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9197#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9144#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9145#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9158#L276-15 assume 1 == ~t2_pc~0; 9033#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9020#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9021#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9223#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9108#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8939#L295-15 assume !(1 == ~t3_pc~0); 8940#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 9141#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9190#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9215#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9175#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9176#L314-15 assume 1 == ~t4_pc~0; 9090#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9091#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9031#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9032#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9163#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9107#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8840#L555-5 assume !(1 == ~T1_E~0); 8841#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9009#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9147#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9109#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8834#L580-3 assume !(1 == ~E_2~0); 8835#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8991#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8992#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9067#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8918#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 9093#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 9137#L795 assume !(0 == start_simulation_~tmp~3#1); 9139#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9159#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8876#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 9022#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 9023#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9000#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9001#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 9068#L808 assume !(0 != start_simulation_~tmp___0~1#1); 8945#L776-2 [2022-02-21 04:24:10,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:10,293 INFO L85 PathProgramCache]: Analyzing trace with hash -1404384723, now seen corresponding path program 1 times [2022-02-21 04:24:10,294 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:10,294 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439032887] [2022-02-21 04:24:10,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:10,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:10,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:10,322 INFO L290 TraceCheckUtils]: 0: Hoare triple {10874#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,322 INFO L290 TraceCheckUtils]: 1: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,322 INFO L290 TraceCheckUtils]: 2: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,323 INFO L290 TraceCheckUtils]: 3: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,323 INFO L290 TraceCheckUtils]: 4: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,323 INFO L290 TraceCheckUtils]: 5: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,324 INFO L290 TraceCheckUtils]: 6: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,324 INFO L290 TraceCheckUtils]: 7: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,325 INFO L290 TraceCheckUtils]: 8: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,325 INFO L290 TraceCheckUtils]: 9: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,325 INFO L290 TraceCheckUtils]: 10: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,326 INFO L290 TraceCheckUtils]: 11: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,326 INFO L290 TraceCheckUtils]: 12: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,326 INFO L290 TraceCheckUtils]: 13: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,327 INFO L290 TraceCheckUtils]: 14: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,327 INFO L290 TraceCheckUtils]: 15: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,327 INFO L290 TraceCheckUtils]: 16: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,328 INFO L290 TraceCheckUtils]: 17: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,328 INFO L290 TraceCheckUtils]: 18: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,328 INFO L290 TraceCheckUtils]: 19: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10876#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:10,329 INFO L290 TraceCheckUtils]: 20: Hoare triple {10876#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {10877#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:10,329 INFO L290 TraceCheckUtils]: 21: Hoare triple {10877#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {10877#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:10,329 INFO L290 TraceCheckUtils]: 22: Hoare triple {10877#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10877#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:10,330 INFO L290 TraceCheckUtils]: 23: Hoare triple {10877#(not (= ~t1_pc~0 1))} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {10877#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:10,330 INFO L290 TraceCheckUtils]: 24: Hoare triple {10877#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {10877#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:10,330 INFO L290 TraceCheckUtils]: 25: Hoare triple {10877#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10877#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 26: Hoare triple {10877#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {10875#false} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 27: Hoare triple {10875#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10875#false} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 28: Hoare triple {10875#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10875#false} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 29: Hoare triple {10875#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {10875#false} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 30: Hoare triple {10875#false} assume !(0 != activate_threads_~tmp___0~0#1); {10875#false} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 31: Hoare triple {10875#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10875#false} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 32: Hoare triple {10875#false} assume !(1 == ~t2_pc~0); {10875#false} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 33: Hoare triple {10875#false} is_transmit2_triggered_~__retres1~2#1 := 0; {10875#false} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 34: Hoare triple {10875#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10875#false} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 35: Hoare triple {10875#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {10875#false} is VALID [2022-02-21 04:24:10,331 INFO L290 TraceCheckUtils]: 36: Hoare triple {10875#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10875#false} is VALID [2022-02-21 04:24:10,332 INFO L290 TraceCheckUtils]: 37: Hoare triple {10875#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10875#false} is VALID [2022-02-21 04:24:10,332 INFO L290 TraceCheckUtils]: 38: Hoare triple {10875#false} assume 1 == ~t3_pc~0; {10875#false} is VALID [2022-02-21 04:24:10,332 INFO L290 TraceCheckUtils]: 39: Hoare triple {10875#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10875#false} is VALID [2022-02-21 04:24:10,332 INFO L290 TraceCheckUtils]: 40: Hoare triple {10875#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10875#false} is VALID [2022-02-21 04:24:10,332 INFO L290 TraceCheckUtils]: 41: Hoare triple {10875#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {10875#false} is VALID [2022-02-21 04:24:10,332 INFO L290 TraceCheckUtils]: 42: Hoare triple {10875#false} assume !(0 != activate_threads_~tmp___2~0#1); {10875#false} is VALID [2022-02-21 04:24:10,332 INFO L290 TraceCheckUtils]: 43: Hoare triple {10875#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10875#false} is VALID [2022-02-21 04:24:10,332 INFO L290 TraceCheckUtils]: 44: Hoare triple {10875#false} assume !(1 == ~t4_pc~0); {10875#false} is VALID [2022-02-21 04:24:10,332 INFO L290 TraceCheckUtils]: 45: Hoare triple {10875#false} is_transmit4_triggered_~__retres1~4#1 := 0; {10875#false} is VALID [2022-02-21 04:24:10,332 INFO L290 TraceCheckUtils]: 46: Hoare triple {10875#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10875#false} is VALID [2022-02-21 04:24:10,335 INFO L290 TraceCheckUtils]: 47: Hoare triple {10875#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {10875#false} is VALID [2022-02-21 04:24:10,335 INFO L290 TraceCheckUtils]: 48: Hoare triple {10875#false} assume !(0 != activate_threads_~tmp___3~0#1); {10875#false} is VALID [2022-02-21 04:24:10,335 INFO L290 TraceCheckUtils]: 49: Hoare triple {10875#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10875#false} is VALID [2022-02-21 04:24:10,336 INFO L290 TraceCheckUtils]: 50: Hoare triple {10875#false} assume !(1 == ~M_E~0); {10875#false} is VALID [2022-02-21 04:24:10,336 INFO L290 TraceCheckUtils]: 51: Hoare triple {10875#false} assume !(1 == ~T1_E~0); {10875#false} is VALID [2022-02-21 04:24:10,336 INFO L290 TraceCheckUtils]: 52: Hoare triple {10875#false} assume !(1 == ~T2_E~0); {10875#false} is VALID [2022-02-21 04:24:10,336 INFO L290 TraceCheckUtils]: 53: Hoare triple {10875#false} assume !(1 == ~T3_E~0); {10875#false} is VALID [2022-02-21 04:24:10,336 INFO L290 TraceCheckUtils]: 54: Hoare triple {10875#false} assume !(1 == ~T4_E~0); {10875#false} is VALID [2022-02-21 04:24:10,336 INFO L290 TraceCheckUtils]: 55: Hoare triple {10875#false} assume !(1 == ~E_1~0); {10875#false} is VALID [2022-02-21 04:24:10,336 INFO L290 TraceCheckUtils]: 56: Hoare triple {10875#false} assume !(1 == ~E_2~0); {10875#false} is VALID [2022-02-21 04:24:10,337 INFO L290 TraceCheckUtils]: 57: Hoare triple {10875#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10875#false} is VALID [2022-02-21 04:24:10,337 INFO L290 TraceCheckUtils]: 58: Hoare triple {10875#false} assume !(1 == ~E_4~0); {10875#false} is VALID [2022-02-21 04:24:10,337 INFO L290 TraceCheckUtils]: 59: Hoare triple {10875#false} assume { :end_inline_reset_delta_events } true; {10875#false} is VALID [2022-02-21 04:24:10,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:10,337 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:10,338 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439032887] [2022-02-21 04:24:10,338 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1439032887] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:10,338 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:10,338 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:10,338 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120437695] [2022-02-21 04:24:10,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:10,339 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:10,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:10,339 INFO L85 PathProgramCache]: Analyzing trace with hash -21400384, now seen corresponding path program 1 times [2022-02-21 04:24:10,339 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:10,340 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409351905] [2022-02-21 04:24:10,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:10,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:10,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:10,371 INFO L290 TraceCheckUtils]: 0: Hoare triple {10878#true} assume !false; {10878#true} is VALID [2022-02-21 04:24:10,371 INFO L290 TraceCheckUtils]: 1: Hoare triple {10878#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10878#true} is VALID [2022-02-21 04:24:10,371 INFO L290 TraceCheckUtils]: 2: Hoare triple {10878#true} assume !false; {10878#true} is VALID [2022-02-21 04:24:10,371 INFO L290 TraceCheckUtils]: 3: Hoare triple {10878#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {10878#true} is VALID [2022-02-21 04:24:10,371 INFO L290 TraceCheckUtils]: 4: Hoare triple {10878#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {10878#true} is VALID [2022-02-21 04:24:10,371 INFO L290 TraceCheckUtils]: 5: Hoare triple {10878#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {10878#true} is VALID [2022-02-21 04:24:10,371 INFO L290 TraceCheckUtils]: 6: Hoare triple {10878#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {10878#true} is VALID [2022-02-21 04:24:10,372 INFO L290 TraceCheckUtils]: 7: Hoare triple {10878#true} assume !(0 != eval_~tmp~0#1); {10878#true} is VALID [2022-02-21 04:24:10,372 INFO L290 TraceCheckUtils]: 8: Hoare triple {10878#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10878#true} is VALID [2022-02-21 04:24:10,372 INFO L290 TraceCheckUtils]: 9: Hoare triple {10878#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10878#true} is VALID [2022-02-21 04:24:10,372 INFO L290 TraceCheckUtils]: 10: Hoare triple {10878#true} assume !(0 == ~M_E~0); {10878#true} is VALID [2022-02-21 04:24:10,372 INFO L290 TraceCheckUtils]: 11: Hoare triple {10878#true} assume !(0 == ~T1_E~0); {10878#true} is VALID [2022-02-21 04:24:10,372 INFO L290 TraceCheckUtils]: 12: Hoare triple {10878#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {10878#true} is VALID [2022-02-21 04:24:10,372 INFO L290 TraceCheckUtils]: 13: Hoare triple {10878#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10878#true} is VALID [2022-02-21 04:24:10,372 INFO L290 TraceCheckUtils]: 14: Hoare triple {10878#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10878#true} is VALID [2022-02-21 04:24:10,372 INFO L290 TraceCheckUtils]: 15: Hoare triple {10878#true} assume 0 == ~E_1~0;~E_1~0 := 1; {10878#true} is VALID [2022-02-21 04:24:10,373 INFO L290 TraceCheckUtils]: 16: Hoare triple {10878#true} assume 0 == ~E_2~0;~E_2~0 := 1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,373 INFO L290 TraceCheckUtils]: 17: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,373 INFO L290 TraceCheckUtils]: 18: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,374 INFO L290 TraceCheckUtils]: 19: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,374 INFO L290 TraceCheckUtils]: 20: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~m_pc~0); {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,374 INFO L290 TraceCheckUtils]: 21: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,375 INFO L290 TraceCheckUtils]: 22: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,375 INFO L290 TraceCheckUtils]: 23: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,375 INFO L290 TraceCheckUtils]: 24: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,375 INFO L290 TraceCheckUtils]: 25: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,376 INFO L290 TraceCheckUtils]: 26: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,376 INFO L290 TraceCheckUtils]: 27: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,376 INFO L290 TraceCheckUtils]: 28: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,377 INFO L290 TraceCheckUtils]: 29: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,377 INFO L290 TraceCheckUtils]: 30: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,377 INFO L290 TraceCheckUtils]: 31: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,378 INFO L290 TraceCheckUtils]: 32: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t2_pc~0; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,378 INFO L290 TraceCheckUtils]: 33: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,378 INFO L290 TraceCheckUtils]: 34: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,379 INFO L290 TraceCheckUtils]: 35: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,379 INFO L290 TraceCheckUtils]: 36: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,379 INFO L290 TraceCheckUtils]: 37: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,379 INFO L290 TraceCheckUtils]: 38: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,380 INFO L290 TraceCheckUtils]: 39: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,380 INFO L290 TraceCheckUtils]: 40: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,380 INFO L290 TraceCheckUtils]: 41: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,381 INFO L290 TraceCheckUtils]: 42: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,381 INFO L290 TraceCheckUtils]: 43: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,381 INFO L290 TraceCheckUtils]: 44: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,382 INFO L290 TraceCheckUtils]: 45: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,382 INFO L290 TraceCheckUtils]: 46: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,382 INFO L290 TraceCheckUtils]: 47: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,382 INFO L290 TraceCheckUtils]: 48: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,383 INFO L290 TraceCheckUtils]: 49: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,383 INFO L290 TraceCheckUtils]: 50: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,383 INFO L290 TraceCheckUtils]: 51: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T1_E~0); {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,384 INFO L290 TraceCheckUtils]: 52: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,384 INFO L290 TraceCheckUtils]: 53: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,384 INFO L290 TraceCheckUtils]: 54: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,385 INFO L290 TraceCheckUtils]: 55: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {10880#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:10,385 INFO L290 TraceCheckUtils]: 56: Hoare triple {10880#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {10879#false} is VALID [2022-02-21 04:24:10,385 INFO L290 TraceCheckUtils]: 57: Hoare triple {10879#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10879#false} is VALID [2022-02-21 04:24:10,385 INFO L290 TraceCheckUtils]: 58: Hoare triple {10879#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10879#false} is VALID [2022-02-21 04:24:10,385 INFO L290 TraceCheckUtils]: 59: Hoare triple {10879#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {10879#false} is VALID [2022-02-21 04:24:10,385 INFO L290 TraceCheckUtils]: 60: Hoare triple {10879#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {10879#false} is VALID [2022-02-21 04:24:10,385 INFO L290 TraceCheckUtils]: 61: Hoare triple {10879#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {10879#false} is VALID [2022-02-21 04:24:10,386 INFO L290 TraceCheckUtils]: 62: Hoare triple {10879#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {10879#false} is VALID [2022-02-21 04:24:10,386 INFO L290 TraceCheckUtils]: 63: Hoare triple {10879#false} assume !(0 == start_simulation_~tmp~3#1); {10879#false} is VALID [2022-02-21 04:24:10,386 INFO L290 TraceCheckUtils]: 64: Hoare triple {10879#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {10879#false} is VALID [2022-02-21 04:24:10,386 INFO L290 TraceCheckUtils]: 65: Hoare triple {10879#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {10879#false} is VALID [2022-02-21 04:24:10,386 INFO L290 TraceCheckUtils]: 66: Hoare triple {10879#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {10879#false} is VALID [2022-02-21 04:24:10,386 INFO L290 TraceCheckUtils]: 67: Hoare triple {10879#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {10879#false} is VALID [2022-02-21 04:24:10,386 INFO L290 TraceCheckUtils]: 68: Hoare triple {10879#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {10879#false} is VALID [2022-02-21 04:24:10,386 INFO L290 TraceCheckUtils]: 69: Hoare triple {10879#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10879#false} is VALID [2022-02-21 04:24:10,386 INFO L290 TraceCheckUtils]: 70: Hoare triple {10879#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {10879#false} is VALID [2022-02-21 04:24:10,387 INFO L290 TraceCheckUtils]: 71: Hoare triple {10879#false} assume !(0 != start_simulation_~tmp___0~1#1); {10879#false} is VALID [2022-02-21 04:24:10,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:10,387 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:10,387 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409351905] [2022-02-21 04:24:10,387 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [409351905] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:10,387 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:10,388 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:10,388 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067037847] [2022-02-21 04:24:10,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:10,388 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:10,388 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:10,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:10,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:10,389 INFO L87 Difference]: Start difference. First operand 658 states and 963 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,538 INFO L93 Difference]: Finished difference Result 1490 states and 2153 transitions. [2022-02-21 04:24:11,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:11,538 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,583 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:11,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1490 states and 2153 transitions. [2022-02-21 04:24:11,671 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1382 [2022-02-21 04:24:11,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1490 states to 1490 states and 2153 transitions. [2022-02-21 04:24:11,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1490 [2022-02-21 04:24:11,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1490 [2022-02-21 04:24:11,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1490 states and 2153 transitions. [2022-02-21 04:24:11,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:11,758 INFO L681 BuchiCegarLoop]: Abstraction has 1490 states and 2153 transitions. [2022-02-21 04:24:11,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1490 states and 2153 transitions. [2022-02-21 04:24:11,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1490 to 1163. [2022-02-21 04:24:11,774 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:11,777 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1490 states and 2153 transitions. Second operand has 1163 states, 1163 states have (on average 1.4557179707652623) internal successors, (1693), 1162 states have internal predecessors, (1693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,780 INFO L74 IsIncluded]: Start isIncluded. First operand 1490 states and 2153 transitions. Second operand has 1163 states, 1163 states have (on average 1.4557179707652623) internal successors, (1693), 1162 states have internal predecessors, (1693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,782 INFO L87 Difference]: Start difference. First operand 1490 states and 2153 transitions. Second operand has 1163 states, 1163 states have (on average 1.4557179707652623) internal successors, (1693), 1162 states have internal predecessors, (1693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,863 INFO L93 Difference]: Finished difference Result 1490 states and 2153 transitions. [2022-02-21 04:24:11,864 INFO L276 IsEmpty]: Start isEmpty. Operand 1490 states and 2153 transitions. [2022-02-21 04:24:11,866 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:11,866 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:11,869 INFO L74 IsIncluded]: Start isIncluded. First operand has 1163 states, 1163 states have (on average 1.4557179707652623) internal successors, (1693), 1162 states have internal predecessors, (1693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1490 states and 2153 transitions. [2022-02-21 04:24:11,871 INFO L87 Difference]: Start difference. First operand has 1163 states, 1163 states have (on average 1.4557179707652623) internal successors, (1693), 1162 states have internal predecessors, (1693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1490 states and 2153 transitions. [2022-02-21 04:24:11,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,957 INFO L93 Difference]: Finished difference Result 1490 states and 2153 transitions. [2022-02-21 04:24:11,958 INFO L276 IsEmpty]: Start isEmpty. Operand 1490 states and 2153 transitions. [2022-02-21 04:24:11,980 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:11,980 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:11,980 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:11,980 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:11,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1163 states, 1163 states have (on average 1.4557179707652623) internal successors, (1693), 1162 states have internal predecessors, (1693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1163 states to 1163 states and 1693 transitions. [2022-02-21 04:24:12,032 INFO L704 BuchiCegarLoop]: Abstraction has 1163 states and 1693 transitions. [2022-02-21 04:24:12,032 INFO L587 BuchiCegarLoop]: Abstraction has 1163 states and 1693 transitions. [2022-02-21 04:24:12,032 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:12,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1163 states and 1693 transitions. [2022-02-21 04:24:12,037 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1098 [2022-02-21 04:24:12,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:12,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:12,038 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:12,039 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:12,039 INFO L791 eck$LassoCheckResult]: Stem: 12778#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 12733#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12373#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12374#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12496#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 12608#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12457#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12458#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12470#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12471#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12516#L502 assume !(0 == ~M_E~0); 12517#L502-2 assume !(0 == ~T1_E~0); 12446#L507-1 assume !(0 == ~T2_E~0); 12447#L512-1 assume !(0 == ~T3_E~0); 12609#L517-1 assume !(0 == ~T4_E~0); 12421#L522-1 assume !(0 == ~E_1~0); 12422#L527-1 assume !(0 == ~E_2~0); 12627#L532-1 assume !(0 == ~E_3~0); 12725#L537-1 assume !(0 == ~E_4~0); 12744#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12716#L238 assume !(1 == ~m_pc~0); 12717#L238-2 is_master_triggered_~__retres1~0#1 := 0; 12386#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12387#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12695#L615 assume !(0 != activate_threads_~tmp~1#1); 12405#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12406#L257 assume !(1 == ~t1_pc~0); 12524#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12525#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12560#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12380#L623 assume !(0 != activate_threads_~tmp___0~0#1); 12381#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12375#L276 assume !(1 == ~t2_pc~0); 12376#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12636#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12472#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12473#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12756#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12692#L295 assume 1 == ~t3_pc~0; 12536#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12491#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12676#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12726#L639 assume !(0 != activate_threads_~tmp___2~0#1); 12718#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12719#L314 assume !(1 == ~t4_pc~0); 12528#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12527#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12721#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12669#L647 assume !(0 != activate_threads_~tmp___3~0#1); 12621#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12622#L555 assume !(1 == ~M_E~0); 12541#L555-2 assume !(1 == ~T1_E~0); 12542#L560-1 assume !(1 == ~T2_E~0); 12423#L565-1 assume !(1 == ~T3_E~0); 12424#L570-1 assume !(1 == ~T4_E~0); 12501#L575-1 assume !(1 == ~E_1~0); 12502#L580-1 assume !(1 == ~E_2~0); 12670#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 12503#L590-1 assume !(1 == ~E_4~0); 12492#L595-1 assume { :end_inline_reset_delta_events } true; 12493#L776-2 [2022-02-21 04:24:12,043 INFO L793 eck$LassoCheckResult]: Loop: 12493#L776-2 assume !false; 12461#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12462#L477 assume !false; 12552#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12553#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12394#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12395#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12434#L416 assume !(0 != eval_~tmp~0#1); 12436#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12729#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12652#L502-3 assume !(0 == ~M_E~0); 12653#L502-5 assume !(0 == ~T1_E~0); 12682#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12601#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12602#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12588#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12589#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12671#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12604#L537-3 assume !(0 == ~E_4~0); 12605#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12614#L238-15 assume !(1 == ~m_pc~0); 12665#L238-17 is_master_triggered_~__retres1~0#1 := 0; 12705#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12706#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12522#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12523#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12453#L257-15 assume !(1 == ~t1_pc~0); 12454#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 12647#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12748#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12696#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12697#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12710#L276-15 assume 1 == ~t2_pc~0; 12585#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12568#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12569#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12780#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12662#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12487#L295-15 assume !(1 == ~t3_pc~0); 12488#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 12694#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12741#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12771#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12727#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12728#L314-15 assume 1 == ~t4_pc~0; 12640#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12641#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12583#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12584#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12715#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12661#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12388#L555-5 assume !(1 == ~T1_E~0); 12389#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12557#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12699#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12663#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12382#L580-3 assume !(1 == ~E_2~0); 12383#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12539#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12540#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12620#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12466#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12646#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 12689#L795 assume !(0 == start_simulation_~tmp~3#1); 12691#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12711#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12431#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12570#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 12571#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12548#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12549#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 12618#L808 assume !(0 != start_simulation_~tmp___0~1#1); 12493#L776-2 [2022-02-21 04:24:12,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:12,044 INFO L85 PathProgramCache]: Analyzing trace with hash 1261932300, now seen corresponding path program 1 times [2022-02-21 04:24:12,044 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:12,044 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847711115] [2022-02-21 04:24:12,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:12,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:12,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:12,087 INFO L290 TraceCheckUtils]: 0: Hoare triple {16519#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {16519#true} is VALID [2022-02-21 04:24:12,087 INFO L290 TraceCheckUtils]: 1: Hoare triple {16519#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {16519#true} is VALID [2022-02-21 04:24:12,088 INFO L290 TraceCheckUtils]: 2: Hoare triple {16519#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {16519#true} is VALID [2022-02-21 04:24:12,088 INFO L290 TraceCheckUtils]: 3: Hoare triple {16519#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {16519#true} is VALID [2022-02-21 04:24:12,088 INFO L290 TraceCheckUtils]: 4: Hoare triple {16519#true} assume 1 == ~m_i~0;~m_st~0 := 0; {16519#true} is VALID [2022-02-21 04:24:12,088 INFO L290 TraceCheckUtils]: 5: Hoare triple {16519#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {16519#true} is VALID [2022-02-21 04:24:12,088 INFO L290 TraceCheckUtils]: 6: Hoare triple {16519#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {16519#true} is VALID [2022-02-21 04:24:12,088 INFO L290 TraceCheckUtils]: 7: Hoare triple {16519#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {16519#true} is VALID [2022-02-21 04:24:12,088 INFO L290 TraceCheckUtils]: 8: Hoare triple {16519#true} assume 1 == ~t4_i~0;~t4_st~0 := 0; {16519#true} is VALID [2022-02-21 04:24:12,089 INFO L290 TraceCheckUtils]: 9: Hoare triple {16519#true} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {16519#true} is VALID [2022-02-21 04:24:12,089 INFO L290 TraceCheckUtils]: 10: Hoare triple {16519#true} assume !(0 == ~M_E~0); {16519#true} is VALID [2022-02-21 04:24:12,089 INFO L290 TraceCheckUtils]: 11: Hoare triple {16519#true} assume !(0 == ~T1_E~0); {16519#true} is VALID [2022-02-21 04:24:12,089 INFO L290 TraceCheckUtils]: 12: Hoare triple {16519#true} assume !(0 == ~T2_E~0); {16519#true} is VALID [2022-02-21 04:24:12,089 INFO L290 TraceCheckUtils]: 13: Hoare triple {16519#true} assume !(0 == ~T3_E~0); {16519#true} is VALID [2022-02-21 04:24:12,089 INFO L290 TraceCheckUtils]: 14: Hoare triple {16519#true} assume !(0 == ~T4_E~0); {16519#true} is VALID [2022-02-21 04:24:12,089 INFO L290 TraceCheckUtils]: 15: Hoare triple {16519#true} assume !(0 == ~E_1~0); {16519#true} is VALID [2022-02-21 04:24:12,090 INFO L290 TraceCheckUtils]: 16: Hoare triple {16519#true} assume !(0 == ~E_2~0); {16519#true} is VALID [2022-02-21 04:24:12,090 INFO L290 TraceCheckUtils]: 17: Hoare triple {16519#true} assume !(0 == ~E_3~0); {16519#true} is VALID [2022-02-21 04:24:12,090 INFO L290 TraceCheckUtils]: 18: Hoare triple {16519#true} assume !(0 == ~E_4~0); {16519#true} is VALID [2022-02-21 04:24:12,090 INFO L290 TraceCheckUtils]: 19: Hoare triple {16519#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16519#true} is VALID [2022-02-21 04:24:12,090 INFO L290 TraceCheckUtils]: 20: Hoare triple {16519#true} assume !(1 == ~m_pc~0); {16519#true} is VALID [2022-02-21 04:24:12,090 INFO L290 TraceCheckUtils]: 21: Hoare triple {16519#true} is_master_triggered_~__retres1~0#1 := 0; {16519#true} is VALID [2022-02-21 04:24:12,090 INFO L290 TraceCheckUtils]: 22: Hoare triple {16519#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16519#true} is VALID [2022-02-21 04:24:12,091 INFO L290 TraceCheckUtils]: 23: Hoare triple {16519#true} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {16519#true} is VALID [2022-02-21 04:24:12,091 INFO L290 TraceCheckUtils]: 24: Hoare triple {16519#true} assume !(0 != activate_threads_~tmp~1#1); {16519#true} is VALID [2022-02-21 04:24:12,091 INFO L290 TraceCheckUtils]: 25: Hoare triple {16519#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16519#true} is VALID [2022-02-21 04:24:12,091 INFO L290 TraceCheckUtils]: 26: Hoare triple {16519#true} assume !(1 == ~t1_pc~0); {16519#true} is VALID [2022-02-21 04:24:12,091 INFO L290 TraceCheckUtils]: 27: Hoare triple {16519#true} is_transmit1_triggered_~__retres1~1#1 := 0; {16519#true} is VALID [2022-02-21 04:24:12,091 INFO L290 TraceCheckUtils]: 28: Hoare triple {16519#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16519#true} is VALID [2022-02-21 04:24:12,092 INFO L290 TraceCheckUtils]: 29: Hoare triple {16519#true} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {16519#true} is VALID [2022-02-21 04:24:12,092 INFO L290 TraceCheckUtils]: 30: Hoare triple {16519#true} assume !(0 != activate_threads_~tmp___0~0#1); {16519#true} is VALID [2022-02-21 04:24:12,092 INFO L290 TraceCheckUtils]: 31: Hoare triple {16519#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16519#true} is VALID [2022-02-21 04:24:12,092 INFO L290 TraceCheckUtils]: 32: Hoare triple {16519#true} assume !(1 == ~t2_pc~0); {16519#true} is VALID [2022-02-21 04:24:12,092 INFO L290 TraceCheckUtils]: 33: Hoare triple {16519#true} is_transmit2_triggered_~__retres1~2#1 := 0; {16521#(= |ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1| 0)} is VALID [2022-02-21 04:24:12,093 INFO L290 TraceCheckUtils]: 34: Hoare triple {16521#(= |ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1| 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16522#(= |ULTIMATE.start_is_transmit2_triggered_#res#1| 0)} is VALID [2022-02-21 04:24:12,093 INFO L290 TraceCheckUtils]: 35: Hoare triple {16522#(= |ULTIMATE.start_is_transmit2_triggered_#res#1| 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {16523#(= |ULTIMATE.start_activate_threads_~tmp___1~0#1| 0)} is VALID [2022-02-21 04:24:12,094 INFO L290 TraceCheckUtils]: 36: Hoare triple {16523#(= |ULTIMATE.start_activate_threads_~tmp___1~0#1| 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {16520#false} is VALID [2022-02-21 04:24:12,094 INFO L290 TraceCheckUtils]: 37: Hoare triple {16520#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16520#false} is VALID [2022-02-21 04:24:12,094 INFO L290 TraceCheckUtils]: 38: Hoare triple {16520#false} assume 1 == ~t3_pc~0; {16520#false} is VALID [2022-02-21 04:24:12,094 INFO L290 TraceCheckUtils]: 39: Hoare triple {16520#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {16520#false} is VALID [2022-02-21 04:24:12,094 INFO L290 TraceCheckUtils]: 40: Hoare triple {16520#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16520#false} is VALID [2022-02-21 04:24:12,094 INFO L290 TraceCheckUtils]: 41: Hoare triple {16520#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {16520#false} is VALID [2022-02-21 04:24:12,095 INFO L290 TraceCheckUtils]: 42: Hoare triple {16520#false} assume !(0 != activate_threads_~tmp___2~0#1); {16520#false} is VALID [2022-02-21 04:24:12,095 INFO L290 TraceCheckUtils]: 43: Hoare triple {16520#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16520#false} is VALID [2022-02-21 04:24:12,095 INFO L290 TraceCheckUtils]: 44: Hoare triple {16520#false} assume !(1 == ~t4_pc~0); {16520#false} is VALID [2022-02-21 04:24:12,095 INFO L290 TraceCheckUtils]: 45: Hoare triple {16520#false} is_transmit4_triggered_~__retres1~4#1 := 0; {16520#false} is VALID [2022-02-21 04:24:12,095 INFO L290 TraceCheckUtils]: 46: Hoare triple {16520#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16520#false} is VALID [2022-02-21 04:24:12,095 INFO L290 TraceCheckUtils]: 47: Hoare triple {16520#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {16520#false} is VALID [2022-02-21 04:24:12,095 INFO L290 TraceCheckUtils]: 48: Hoare triple {16520#false} assume !(0 != activate_threads_~tmp___3~0#1); {16520#false} is VALID [2022-02-21 04:24:12,096 INFO L290 TraceCheckUtils]: 49: Hoare triple {16520#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16520#false} is VALID [2022-02-21 04:24:12,096 INFO L290 TraceCheckUtils]: 50: Hoare triple {16520#false} assume !(1 == ~M_E~0); {16520#false} is VALID [2022-02-21 04:24:12,096 INFO L290 TraceCheckUtils]: 51: Hoare triple {16520#false} assume !(1 == ~T1_E~0); {16520#false} is VALID [2022-02-21 04:24:12,096 INFO L290 TraceCheckUtils]: 52: Hoare triple {16520#false} assume !(1 == ~T2_E~0); {16520#false} is VALID [2022-02-21 04:24:12,096 INFO L290 TraceCheckUtils]: 53: Hoare triple {16520#false} assume !(1 == ~T3_E~0); {16520#false} is VALID [2022-02-21 04:24:12,096 INFO L290 TraceCheckUtils]: 54: Hoare triple {16520#false} assume !(1 == ~T4_E~0); {16520#false} is VALID [2022-02-21 04:24:12,096 INFO L290 TraceCheckUtils]: 55: Hoare triple {16520#false} assume !(1 == ~E_1~0); {16520#false} is VALID [2022-02-21 04:24:12,097 INFO L290 TraceCheckUtils]: 56: Hoare triple {16520#false} assume !(1 == ~E_2~0); {16520#false} is VALID [2022-02-21 04:24:12,097 INFO L290 TraceCheckUtils]: 57: Hoare triple {16520#false} assume 1 == ~E_3~0;~E_3~0 := 2; {16520#false} is VALID [2022-02-21 04:24:12,097 INFO L290 TraceCheckUtils]: 58: Hoare triple {16520#false} assume !(1 == ~E_4~0); {16520#false} is VALID [2022-02-21 04:24:12,097 INFO L290 TraceCheckUtils]: 59: Hoare triple {16520#false} assume { :end_inline_reset_delta_events } true; {16520#false} is VALID [2022-02-21 04:24:12,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:12,097 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:12,098 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [847711115] [2022-02-21 04:24:12,098 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [847711115] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:12,099 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:12,099 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:12,099 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539172448] [2022-02-21 04:24:12,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:12,100 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:12,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:12,100 INFO L85 PathProgramCache]: Analyzing trace with hash -21400384, now seen corresponding path program 2 times [2022-02-21 04:24:12,101 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:12,104 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070975626] [2022-02-21 04:24:12,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:12,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:12,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:12,143 INFO L290 TraceCheckUtils]: 0: Hoare triple {16524#true} assume !false; {16524#true} is VALID [2022-02-21 04:24:12,143 INFO L290 TraceCheckUtils]: 1: Hoare triple {16524#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {16524#true} is VALID [2022-02-21 04:24:12,143 INFO L290 TraceCheckUtils]: 2: Hoare triple {16524#true} assume !false; {16524#true} is VALID [2022-02-21 04:24:12,144 INFO L290 TraceCheckUtils]: 3: Hoare triple {16524#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {16524#true} is VALID [2022-02-21 04:24:12,144 INFO L290 TraceCheckUtils]: 4: Hoare triple {16524#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {16524#true} is VALID [2022-02-21 04:24:12,144 INFO L290 TraceCheckUtils]: 5: Hoare triple {16524#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {16524#true} is VALID [2022-02-21 04:24:12,144 INFO L290 TraceCheckUtils]: 6: Hoare triple {16524#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {16524#true} is VALID [2022-02-21 04:24:12,144 INFO L290 TraceCheckUtils]: 7: Hoare triple {16524#true} assume !(0 != eval_~tmp~0#1); {16524#true} is VALID [2022-02-21 04:24:12,144 INFO L290 TraceCheckUtils]: 8: Hoare triple {16524#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {16524#true} is VALID [2022-02-21 04:24:12,144 INFO L290 TraceCheckUtils]: 9: Hoare triple {16524#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {16524#true} is VALID [2022-02-21 04:24:12,145 INFO L290 TraceCheckUtils]: 10: Hoare triple {16524#true} assume !(0 == ~M_E~0); {16524#true} is VALID [2022-02-21 04:24:12,145 INFO L290 TraceCheckUtils]: 11: Hoare triple {16524#true} assume !(0 == ~T1_E~0); {16524#true} is VALID [2022-02-21 04:24:12,145 INFO L290 TraceCheckUtils]: 12: Hoare triple {16524#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {16524#true} is VALID [2022-02-21 04:24:12,145 INFO L290 TraceCheckUtils]: 13: Hoare triple {16524#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {16524#true} is VALID [2022-02-21 04:24:12,145 INFO L290 TraceCheckUtils]: 14: Hoare triple {16524#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {16524#true} is VALID [2022-02-21 04:24:12,145 INFO L290 TraceCheckUtils]: 15: Hoare triple {16524#true} assume 0 == ~E_1~0;~E_1~0 := 1; {16524#true} is VALID [2022-02-21 04:24:12,146 INFO L290 TraceCheckUtils]: 16: Hoare triple {16524#true} assume 0 == ~E_2~0;~E_2~0 := 1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,146 INFO L290 TraceCheckUtils]: 17: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,146 INFO L290 TraceCheckUtils]: 18: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,147 INFO L290 TraceCheckUtils]: 19: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,147 INFO L290 TraceCheckUtils]: 20: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~m_pc~0); {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,148 INFO L290 TraceCheckUtils]: 21: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,148 INFO L290 TraceCheckUtils]: 22: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,148 INFO L290 TraceCheckUtils]: 23: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,149 INFO L290 TraceCheckUtils]: 24: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,149 INFO L290 TraceCheckUtils]: 25: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,149 INFO L290 TraceCheckUtils]: 26: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,150 INFO L290 TraceCheckUtils]: 27: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,150 INFO L290 TraceCheckUtils]: 28: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,150 INFO L290 TraceCheckUtils]: 29: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,151 INFO L290 TraceCheckUtils]: 30: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,151 INFO L290 TraceCheckUtils]: 31: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,152 INFO L290 TraceCheckUtils]: 32: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t2_pc~0; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,152 INFO L290 TraceCheckUtils]: 33: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,152 INFO L290 TraceCheckUtils]: 34: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,153 INFO L290 TraceCheckUtils]: 35: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,153 INFO L290 TraceCheckUtils]: 36: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,153 INFO L290 TraceCheckUtils]: 37: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,154 INFO L290 TraceCheckUtils]: 38: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,154 INFO L290 TraceCheckUtils]: 39: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,154 INFO L290 TraceCheckUtils]: 40: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,155 INFO L290 TraceCheckUtils]: 41: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,155 INFO L290 TraceCheckUtils]: 42: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,155 INFO L290 TraceCheckUtils]: 43: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,156 INFO L290 TraceCheckUtils]: 44: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,156 INFO L290 TraceCheckUtils]: 45: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,156 INFO L290 TraceCheckUtils]: 46: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,157 INFO L290 TraceCheckUtils]: 47: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,157 INFO L290 TraceCheckUtils]: 48: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,158 INFO L290 TraceCheckUtils]: 49: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,158 INFO L290 TraceCheckUtils]: 50: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,158 INFO L290 TraceCheckUtils]: 51: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T1_E~0); {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,159 INFO L290 TraceCheckUtils]: 52: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,159 INFO L290 TraceCheckUtils]: 53: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,159 INFO L290 TraceCheckUtils]: 54: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,160 INFO L290 TraceCheckUtils]: 55: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {16526#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:12,160 INFO L290 TraceCheckUtils]: 56: Hoare triple {16526#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {16525#false} is VALID [2022-02-21 04:24:12,160 INFO L290 TraceCheckUtils]: 57: Hoare triple {16525#false} assume 1 == ~E_3~0;~E_3~0 := 2; {16525#false} is VALID [2022-02-21 04:24:12,160 INFO L290 TraceCheckUtils]: 58: Hoare triple {16525#false} assume 1 == ~E_4~0;~E_4~0 := 2; {16525#false} is VALID [2022-02-21 04:24:12,161 INFO L290 TraceCheckUtils]: 59: Hoare triple {16525#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {16525#false} is VALID [2022-02-21 04:24:12,161 INFO L290 TraceCheckUtils]: 60: Hoare triple {16525#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {16525#false} is VALID [2022-02-21 04:24:12,161 INFO L290 TraceCheckUtils]: 61: Hoare triple {16525#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {16525#false} is VALID [2022-02-21 04:24:12,161 INFO L290 TraceCheckUtils]: 62: Hoare triple {16525#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {16525#false} is VALID [2022-02-21 04:24:12,161 INFO L290 TraceCheckUtils]: 63: Hoare triple {16525#false} assume !(0 == start_simulation_~tmp~3#1); {16525#false} is VALID [2022-02-21 04:24:12,161 INFO L290 TraceCheckUtils]: 64: Hoare triple {16525#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {16525#false} is VALID [2022-02-21 04:24:12,161 INFO L290 TraceCheckUtils]: 65: Hoare triple {16525#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {16525#false} is VALID [2022-02-21 04:24:12,162 INFO L290 TraceCheckUtils]: 66: Hoare triple {16525#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {16525#false} is VALID [2022-02-21 04:24:12,162 INFO L290 TraceCheckUtils]: 67: Hoare triple {16525#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {16525#false} is VALID [2022-02-21 04:24:12,162 INFO L290 TraceCheckUtils]: 68: Hoare triple {16525#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {16525#false} is VALID [2022-02-21 04:24:12,162 INFO L290 TraceCheckUtils]: 69: Hoare triple {16525#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {16525#false} is VALID [2022-02-21 04:24:12,162 INFO L290 TraceCheckUtils]: 70: Hoare triple {16525#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {16525#false} is VALID [2022-02-21 04:24:12,162 INFO L290 TraceCheckUtils]: 71: Hoare triple {16525#false} assume !(0 != start_simulation_~tmp___0~1#1); {16525#false} is VALID [2022-02-21 04:24:12,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:12,163 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:12,165 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070975626] [2022-02-21 04:24:12,165 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1070975626] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:12,165 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:12,166 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:12,166 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36436515] [2022-02-21 04:24:12,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:12,166 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:12,166 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:12,167 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:12,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:12,167 INFO L87 Difference]: Start difference. First operand 1163 states and 1693 transitions. cyclomatic complexity: 532 Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,885 INFO L93 Difference]: Finished difference Result 2972 states and 4330 transitions. [2022-02-21 04:24:13,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:24:13,886 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,922 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:13,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2972 states and 4330 transitions. [2022-02-21 04:24:14,136 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2850 [2022-02-21 04:24:14,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2972 states to 2972 states and 4330 transitions. [2022-02-21 04:24:14,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2972 [2022-02-21 04:24:14,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2972 [2022-02-21 04:24:14,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2972 states and 4330 transitions. [2022-02-21 04:24:14,372 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:14,372 INFO L681 BuchiCegarLoop]: Abstraction has 2972 states and 4330 transitions. [2022-02-21 04:24:14,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states and 4330 transitions. [2022-02-21 04:24:14,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 1226. [2022-02-21 04:24:14,392 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:14,394 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2972 states and 4330 transitions. Second operand has 1226 states, 1226 states have (on average 1.432300163132137) internal successors, (1756), 1225 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,396 INFO L74 IsIncluded]: Start isIncluded. First operand 2972 states and 4330 transitions. Second operand has 1226 states, 1226 states have (on average 1.432300163132137) internal successors, (1756), 1225 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,398 INFO L87 Difference]: Start difference. First operand 2972 states and 4330 transitions. Second operand has 1226 states, 1226 states have (on average 1.432300163132137) internal successors, (1756), 1225 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:14,623 INFO L93 Difference]: Finished difference Result 2972 states and 4330 transitions. [2022-02-21 04:24:14,623 INFO L276 IsEmpty]: Start isEmpty. Operand 2972 states and 4330 transitions. [2022-02-21 04:24:14,628 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:14,628 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:14,631 INFO L74 IsIncluded]: Start isIncluded. First operand has 1226 states, 1226 states have (on average 1.432300163132137) internal successors, (1756), 1225 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2972 states and 4330 transitions. [2022-02-21 04:24:14,633 INFO L87 Difference]: Start difference. First operand has 1226 states, 1226 states have (on average 1.432300163132137) internal successors, (1756), 1225 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2972 states and 4330 transitions. [2022-02-21 04:24:14,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:14,849 INFO L93 Difference]: Finished difference Result 2972 states and 4330 transitions. [2022-02-21 04:24:14,849 INFO L276 IsEmpty]: Start isEmpty. Operand 2972 states and 4330 transitions. [2022-02-21 04:24:14,856 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:14,857 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:14,857 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:14,857 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:14,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1226 states, 1226 states have (on average 1.432300163132137) internal successors, (1756), 1225 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1226 states to 1226 states and 1756 transitions. [2022-02-21 04:24:14,911 INFO L704 BuchiCegarLoop]: Abstraction has 1226 states and 1756 transitions. [2022-02-21 04:24:14,911 INFO L587 BuchiCegarLoop]: Abstraction has 1226 states and 1756 transitions. [2022-02-21 04:24:14,911 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:14,911 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1226 states and 1756 transitions. [2022-02-21 04:24:14,915 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1158 [2022-02-21 04:24:14,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:14,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:14,916 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:14,917 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:14,917 INFO L791 eck$LassoCheckResult]: Stem: 19944#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 19881#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 19503#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19504#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19624#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 19739#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19587#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19588#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19600#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19601#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19646#L502 assume !(0 == ~M_E~0); 19647#L502-2 assume !(0 == ~T1_E~0); 19576#L507-1 assume !(0 == ~T2_E~0); 19577#L512-1 assume !(0 == ~T3_E~0); 19742#L517-1 assume !(0 == ~T4_E~0); 19548#L522-1 assume !(0 == ~E_1~0); 19549#L527-1 assume !(0 == ~E_2~0); 19764#L532-1 assume !(0 == ~E_3~0); 19876#L537-1 assume !(0 == ~E_4~0); 19895#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19865#L238 assume !(1 == ~m_pc~0); 19866#L238-2 is_master_triggered_~__retres1~0#1 := 0; 19514#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19515#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19842#L615 assume !(0 != activate_threads_~tmp~1#1); 19535#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19536#L257 assume !(1 == ~t1_pc~0); 19654#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19655#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19692#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19508#L623 assume !(0 != activate_threads_~tmp___0~0#1); 19509#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19505#L276 assume !(1 == ~t2_pc~0); 19506#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19774#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19902#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19911#L631 assume !(0 != activate_threads_~tmp___1~0#1); 19912#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19839#L295 assume 1 == ~t3_pc~0; 19666#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19621#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19820#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19877#L639 assume !(0 != activate_threads_~tmp___2~0#1); 19867#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19868#L314 assume !(1 == ~t4_pc~0); 19658#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19657#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19871#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19810#L647 assume !(0 != activate_threads_~tmp___3~0#1); 19756#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19757#L555 assume !(1 == ~M_E~0); 19671#L555-2 assume !(1 == ~T1_E~0); 19672#L560-1 assume !(1 == ~T2_E~0); 19550#L565-1 assume !(1 == ~T3_E~0); 19551#L570-1 assume !(1 == ~T4_E~0); 19631#L575-1 assume !(1 == ~E_1~0); 19632#L580-1 assume !(1 == ~E_2~0); 19811#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 19633#L590-1 assume !(1 == ~E_4~0); 19622#L595-1 assume { :end_inline_reset_delta_events } true; 19623#L776-2 [2022-02-21 04:24:14,917 INFO L793 eck$LassoCheckResult]: Loop: 19623#L776-2 assume !false; 19591#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19592#L477 assume !false; 19682#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 19683#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 19522#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 19523#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19564#L416 assume !(0 != eval_~tmp~0#1); 19566#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20719#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20717#L502-3 assume !(0 == ~M_E~0); 20715#L502-5 assume !(0 == ~T1_E~0); 20713#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20711#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20709#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20707#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20705#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20703#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20702#L537-3 assume !(0 == ~E_4~0); 19747#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19748#L238-15 assume !(1 == ~m_pc~0); 20689#L238-17 is_master_triggered_~__retres1~0#1 := 0; 20688#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20687#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20686#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20685#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19583#L257-15 assume !(1 == ~t1_pc~0); 19584#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 20683#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19930#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19843#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19844#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19859#L276-15 assume !(1 == ~t2_pc~0); 20675#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 20673#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20671#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20670#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 20634#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20632#L295-15 assume !(1 == ~t3_pc~0); 20628#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 20626#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20623#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20621#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20619#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20617#L314-15 assume 1 == ~t4_pc~0; 20611#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20610#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19714#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19715#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20554#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20553#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20552#L555-5 assume !(1 == ~T1_E~0); 19687#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19688#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20536#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19802#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19512#L580-3 assume !(1 == ~E_2~0); 19513#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19669#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19670#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 19754#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 19596#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 19783#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 19836#L795 assume !(0 == start_simulation_~tmp~3#1); 19838#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 19860#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 19558#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 19701#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 19702#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19678#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19679#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 19755#L808 assume !(0 != start_simulation_~tmp___0~1#1); 19623#L776-2 [2022-02-21 04:24:14,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:14,918 INFO L85 PathProgramCache]: Analyzing trace with hash 1127918794, now seen corresponding path program 1 times [2022-02-21 04:24:14,918 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:14,918 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888717751] [2022-02-21 04:24:14,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:14,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:14,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:14,952 INFO L290 TraceCheckUtils]: 0: Hoare triple {26676#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,953 INFO L290 TraceCheckUtils]: 1: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,953 INFO L290 TraceCheckUtils]: 2: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,954 INFO L290 TraceCheckUtils]: 3: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,954 INFO L290 TraceCheckUtils]: 4: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,954 INFO L290 TraceCheckUtils]: 5: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,955 INFO L290 TraceCheckUtils]: 6: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,955 INFO L290 TraceCheckUtils]: 7: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,956 INFO L290 TraceCheckUtils]: 8: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,956 INFO L290 TraceCheckUtils]: 9: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,956 INFO L290 TraceCheckUtils]: 10: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~M_E~0); {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,957 INFO L290 TraceCheckUtils]: 11: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T1_E~0); {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,957 INFO L290 TraceCheckUtils]: 12: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T2_E~0); {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,958 INFO L290 TraceCheckUtils]: 13: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T3_E~0); {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,958 INFO L290 TraceCheckUtils]: 14: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T4_E~0); {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,958 INFO L290 TraceCheckUtils]: 15: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_1~0); {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,959 INFO L290 TraceCheckUtils]: 16: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_2~0); {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,959 INFO L290 TraceCheckUtils]: 17: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_3~0); {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,960 INFO L290 TraceCheckUtils]: 18: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_4~0); {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,960 INFO L290 TraceCheckUtils]: 19: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26678#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:14,960 INFO L290 TraceCheckUtils]: 20: Hoare triple {26678#(= ~m_pc~0 ~t3_pc~0)} assume !(1 == ~m_pc~0); {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,961 INFO L290 TraceCheckUtils]: 21: Hoare triple {26679#(not (= ~t3_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,961 INFO L290 TraceCheckUtils]: 22: Hoare triple {26679#(not (= ~t3_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,962 INFO L290 TraceCheckUtils]: 23: Hoare triple {26679#(not (= ~t3_pc~0 1))} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,962 INFO L290 TraceCheckUtils]: 24: Hoare triple {26679#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,962 INFO L290 TraceCheckUtils]: 25: Hoare triple {26679#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,963 INFO L290 TraceCheckUtils]: 26: Hoare triple {26679#(not (= ~t3_pc~0 1))} assume !(1 == ~t1_pc~0); {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,963 INFO L290 TraceCheckUtils]: 27: Hoare triple {26679#(not (= ~t3_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,963 INFO L290 TraceCheckUtils]: 28: Hoare triple {26679#(not (= ~t3_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,964 INFO L290 TraceCheckUtils]: 29: Hoare triple {26679#(not (= ~t3_pc~0 1))} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,964 INFO L290 TraceCheckUtils]: 30: Hoare triple {26679#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,964 INFO L290 TraceCheckUtils]: 31: Hoare triple {26679#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,965 INFO L290 TraceCheckUtils]: 32: Hoare triple {26679#(not (= ~t3_pc~0 1))} assume !(1 == ~t2_pc~0); {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,965 INFO L290 TraceCheckUtils]: 33: Hoare triple {26679#(not (= ~t3_pc~0 1))} is_transmit2_triggered_~__retres1~2#1 := 0; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,965 INFO L290 TraceCheckUtils]: 34: Hoare triple {26679#(not (= ~t3_pc~0 1))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,966 INFO L290 TraceCheckUtils]: 35: Hoare triple {26679#(not (= ~t3_pc~0 1))} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,966 INFO L290 TraceCheckUtils]: 36: Hoare triple {26679#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___1~0#1); {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,967 INFO L290 TraceCheckUtils]: 37: Hoare triple {26679#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26679#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:14,967 INFO L290 TraceCheckUtils]: 38: Hoare triple {26679#(not (= ~t3_pc~0 1))} assume 1 == ~t3_pc~0; {26677#false} is VALID [2022-02-21 04:24:14,967 INFO L290 TraceCheckUtils]: 39: Hoare triple {26677#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {26677#false} is VALID [2022-02-21 04:24:14,967 INFO L290 TraceCheckUtils]: 40: Hoare triple {26677#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26677#false} is VALID [2022-02-21 04:24:14,967 INFO L290 TraceCheckUtils]: 41: Hoare triple {26677#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {26677#false} is VALID [2022-02-21 04:24:14,967 INFO L290 TraceCheckUtils]: 42: Hoare triple {26677#false} assume !(0 != activate_threads_~tmp___2~0#1); {26677#false} is VALID [2022-02-21 04:24:14,968 INFO L290 TraceCheckUtils]: 43: Hoare triple {26677#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26677#false} is VALID [2022-02-21 04:24:14,968 INFO L290 TraceCheckUtils]: 44: Hoare triple {26677#false} assume !(1 == ~t4_pc~0); {26677#false} is VALID [2022-02-21 04:24:14,968 INFO L290 TraceCheckUtils]: 45: Hoare triple {26677#false} is_transmit4_triggered_~__retres1~4#1 := 0; {26677#false} is VALID [2022-02-21 04:24:14,968 INFO L290 TraceCheckUtils]: 46: Hoare triple {26677#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26677#false} is VALID [2022-02-21 04:24:14,968 INFO L290 TraceCheckUtils]: 47: Hoare triple {26677#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {26677#false} is VALID [2022-02-21 04:24:14,968 INFO L290 TraceCheckUtils]: 48: Hoare triple {26677#false} assume !(0 != activate_threads_~tmp___3~0#1); {26677#false} is VALID [2022-02-21 04:24:14,968 INFO L290 TraceCheckUtils]: 49: Hoare triple {26677#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26677#false} is VALID [2022-02-21 04:24:14,969 INFO L290 TraceCheckUtils]: 50: Hoare triple {26677#false} assume !(1 == ~M_E~0); {26677#false} is VALID [2022-02-21 04:24:14,969 INFO L290 TraceCheckUtils]: 51: Hoare triple {26677#false} assume !(1 == ~T1_E~0); {26677#false} is VALID [2022-02-21 04:24:14,969 INFO L290 TraceCheckUtils]: 52: Hoare triple {26677#false} assume !(1 == ~T2_E~0); {26677#false} is VALID [2022-02-21 04:24:14,969 INFO L290 TraceCheckUtils]: 53: Hoare triple {26677#false} assume !(1 == ~T3_E~0); {26677#false} is VALID [2022-02-21 04:24:14,969 INFO L290 TraceCheckUtils]: 54: Hoare triple {26677#false} assume !(1 == ~T4_E~0); {26677#false} is VALID [2022-02-21 04:24:14,969 INFO L290 TraceCheckUtils]: 55: Hoare triple {26677#false} assume !(1 == ~E_1~0); {26677#false} is VALID [2022-02-21 04:24:14,970 INFO L290 TraceCheckUtils]: 56: Hoare triple {26677#false} assume !(1 == ~E_2~0); {26677#false} is VALID [2022-02-21 04:24:14,970 INFO L290 TraceCheckUtils]: 57: Hoare triple {26677#false} assume 1 == ~E_3~0;~E_3~0 := 2; {26677#false} is VALID [2022-02-21 04:24:14,970 INFO L290 TraceCheckUtils]: 58: Hoare triple {26677#false} assume !(1 == ~E_4~0); {26677#false} is VALID [2022-02-21 04:24:14,970 INFO L290 TraceCheckUtils]: 59: Hoare triple {26677#false} assume { :end_inline_reset_delta_events } true; {26677#false} is VALID [2022-02-21 04:24:14,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:14,970 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:14,971 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888717751] [2022-02-21 04:24:14,971 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888717751] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:14,971 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:14,971 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:14,971 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810619011] [2022-02-21 04:24:14,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:14,972 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:14,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:14,973 INFO L85 PathProgramCache]: Analyzing trace with hash -15775971, now seen corresponding path program 1 times [2022-02-21 04:24:14,973 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:14,973 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887104763] [2022-02-21 04:24:14,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:14,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:14,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:14,997 INFO L290 TraceCheckUtils]: 0: Hoare triple {26680#true} assume !false; {26680#true} is VALID [2022-02-21 04:24:14,997 INFO L290 TraceCheckUtils]: 1: Hoare triple {26680#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {26680#true} is VALID [2022-02-21 04:24:14,998 INFO L290 TraceCheckUtils]: 2: Hoare triple {26680#true} assume !false; {26680#true} is VALID [2022-02-21 04:24:14,998 INFO L290 TraceCheckUtils]: 3: Hoare triple {26680#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {26680#true} is VALID [2022-02-21 04:24:14,998 INFO L290 TraceCheckUtils]: 4: Hoare triple {26680#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {26680#true} is VALID [2022-02-21 04:24:14,998 INFO L290 TraceCheckUtils]: 5: Hoare triple {26680#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {26680#true} is VALID [2022-02-21 04:24:14,998 INFO L290 TraceCheckUtils]: 6: Hoare triple {26680#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {26680#true} is VALID [2022-02-21 04:24:14,998 INFO L290 TraceCheckUtils]: 7: Hoare triple {26680#true} assume !(0 != eval_~tmp~0#1); {26680#true} is VALID [2022-02-21 04:24:14,998 INFO L290 TraceCheckUtils]: 8: Hoare triple {26680#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {26680#true} is VALID [2022-02-21 04:24:14,999 INFO L290 TraceCheckUtils]: 9: Hoare triple {26680#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {26680#true} is VALID [2022-02-21 04:24:14,999 INFO L290 TraceCheckUtils]: 10: Hoare triple {26680#true} assume !(0 == ~M_E~0); {26680#true} is VALID [2022-02-21 04:24:14,999 INFO L290 TraceCheckUtils]: 11: Hoare triple {26680#true} assume !(0 == ~T1_E~0); {26680#true} is VALID [2022-02-21 04:24:14,999 INFO L290 TraceCheckUtils]: 12: Hoare triple {26680#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {26680#true} is VALID [2022-02-21 04:24:14,999 INFO L290 TraceCheckUtils]: 13: Hoare triple {26680#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {26680#true} is VALID [2022-02-21 04:24:14,999 INFO L290 TraceCheckUtils]: 14: Hoare triple {26680#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {26680#true} is VALID [2022-02-21 04:24:14,999 INFO L290 TraceCheckUtils]: 15: Hoare triple {26680#true} assume 0 == ~E_1~0;~E_1~0 := 1; {26680#true} is VALID [2022-02-21 04:24:15,000 INFO L290 TraceCheckUtils]: 16: Hoare triple {26680#true} assume 0 == ~E_2~0;~E_2~0 := 1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,000 INFO L290 TraceCheckUtils]: 17: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,001 INFO L290 TraceCheckUtils]: 18: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,001 INFO L290 TraceCheckUtils]: 19: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,001 INFO L290 TraceCheckUtils]: 20: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~m_pc~0); {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,002 INFO L290 TraceCheckUtils]: 21: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,002 INFO L290 TraceCheckUtils]: 22: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,002 INFO L290 TraceCheckUtils]: 23: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,003 INFO L290 TraceCheckUtils]: 24: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,003 INFO L290 TraceCheckUtils]: 25: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,003 INFO L290 TraceCheckUtils]: 26: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,004 INFO L290 TraceCheckUtils]: 27: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,004 INFO L290 TraceCheckUtils]: 28: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,004 INFO L290 TraceCheckUtils]: 29: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,005 INFO L290 TraceCheckUtils]: 30: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,005 INFO L290 TraceCheckUtils]: 31: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,005 INFO L290 TraceCheckUtils]: 32: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t2_pc~0); {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,006 INFO L290 TraceCheckUtils]: 33: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,006 INFO L290 TraceCheckUtils]: 34: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,006 INFO L290 TraceCheckUtils]: 35: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,007 INFO L290 TraceCheckUtils]: 36: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,007 INFO L290 TraceCheckUtils]: 37: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,007 INFO L290 TraceCheckUtils]: 38: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,008 INFO L290 TraceCheckUtils]: 39: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,008 INFO L290 TraceCheckUtils]: 40: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,008 INFO L290 TraceCheckUtils]: 41: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,009 INFO L290 TraceCheckUtils]: 42: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,009 INFO L290 TraceCheckUtils]: 43: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,009 INFO L290 TraceCheckUtils]: 44: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,010 INFO L290 TraceCheckUtils]: 45: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,010 INFO L290 TraceCheckUtils]: 46: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,010 INFO L290 TraceCheckUtils]: 47: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,011 INFO L290 TraceCheckUtils]: 48: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,011 INFO L290 TraceCheckUtils]: 49: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,011 INFO L290 TraceCheckUtils]: 50: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,012 INFO L290 TraceCheckUtils]: 51: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T1_E~0); {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,012 INFO L290 TraceCheckUtils]: 52: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,012 INFO L290 TraceCheckUtils]: 53: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,013 INFO L290 TraceCheckUtils]: 54: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,013 INFO L290 TraceCheckUtils]: 55: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {26682#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:15,013 INFO L290 TraceCheckUtils]: 56: Hoare triple {26682#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {26681#false} is VALID [2022-02-21 04:24:15,014 INFO L290 TraceCheckUtils]: 57: Hoare triple {26681#false} assume 1 == ~E_3~0;~E_3~0 := 2; {26681#false} is VALID [2022-02-21 04:24:15,014 INFO L290 TraceCheckUtils]: 58: Hoare triple {26681#false} assume 1 == ~E_4~0;~E_4~0 := 2; {26681#false} is VALID [2022-02-21 04:24:15,014 INFO L290 TraceCheckUtils]: 59: Hoare triple {26681#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {26681#false} is VALID [2022-02-21 04:24:15,014 INFO L290 TraceCheckUtils]: 60: Hoare triple {26681#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {26681#false} is VALID [2022-02-21 04:24:15,014 INFO L290 TraceCheckUtils]: 61: Hoare triple {26681#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {26681#false} is VALID [2022-02-21 04:24:15,014 INFO L290 TraceCheckUtils]: 62: Hoare triple {26681#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {26681#false} is VALID [2022-02-21 04:24:15,014 INFO L290 TraceCheckUtils]: 63: Hoare triple {26681#false} assume !(0 == start_simulation_~tmp~3#1); {26681#false} is VALID [2022-02-21 04:24:15,014 INFO L290 TraceCheckUtils]: 64: Hoare triple {26681#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {26681#false} is VALID [2022-02-21 04:24:15,015 INFO L290 TraceCheckUtils]: 65: Hoare triple {26681#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {26681#false} is VALID [2022-02-21 04:24:15,015 INFO L290 TraceCheckUtils]: 66: Hoare triple {26681#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {26681#false} is VALID [2022-02-21 04:24:15,015 INFO L290 TraceCheckUtils]: 67: Hoare triple {26681#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {26681#false} is VALID [2022-02-21 04:24:15,015 INFO L290 TraceCheckUtils]: 68: Hoare triple {26681#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {26681#false} is VALID [2022-02-21 04:24:15,015 INFO L290 TraceCheckUtils]: 69: Hoare triple {26681#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {26681#false} is VALID [2022-02-21 04:24:15,015 INFO L290 TraceCheckUtils]: 70: Hoare triple {26681#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {26681#false} is VALID [2022-02-21 04:24:15,015 INFO L290 TraceCheckUtils]: 71: Hoare triple {26681#false} assume !(0 != start_simulation_~tmp___0~1#1); {26681#false} is VALID [2022-02-21 04:24:15,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:15,016 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:15,017 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887104763] [2022-02-21 04:24:15,017 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1887104763] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:15,017 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:15,017 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:15,018 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867213877] [2022-02-21 04:24:15,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:15,018 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:15,018 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:15,019 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:15,019 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:15,020 INFO L87 Difference]: Start difference. First operand 1226 states and 1756 transitions. cyclomatic complexity: 532 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:16,264 INFO L93 Difference]: Finished difference Result 2784 states and 3948 transitions. [2022-02-21 04:24:16,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:16,264 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,303 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:16,305 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2784 states and 3948 transitions. [2022-02-21 04:24:16,514 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2624 [2022-02-21 04:24:16,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2784 states to 2784 states and 3948 transitions. [2022-02-21 04:24:16,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2784 [2022-02-21 04:24:16,728 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2784 [2022-02-21 04:24:16,728 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2784 states and 3948 transitions. [2022-02-21 04:24:16,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:16,731 INFO L681 BuchiCegarLoop]: Abstraction has 2784 states and 3948 transitions. [2022-02-21 04:24:16,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2784 states and 3948 transitions. [2022-02-21 04:24:16,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2784 to 2201. [2022-02-21 04:24:16,756 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:16,759 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2784 states and 3948 transitions. Second operand has 2201 states, 2201 states have (on average 1.4279872785097683) internal successors, (3143), 2200 states have internal predecessors, (3143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,761 INFO L74 IsIncluded]: Start isIncluded. First operand 2784 states and 3948 transitions. Second operand has 2201 states, 2201 states have (on average 1.4279872785097683) internal successors, (3143), 2200 states have internal predecessors, (3143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,763 INFO L87 Difference]: Start difference. First operand 2784 states and 3948 transitions. Second operand has 2201 states, 2201 states have (on average 1.4279872785097683) internal successors, (3143), 2200 states have internal predecessors, (3143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:16,936 INFO L93 Difference]: Finished difference Result 2784 states and 3948 transitions. [2022-02-21 04:24:16,936 INFO L276 IsEmpty]: Start isEmpty. Operand 2784 states and 3948 transitions. [2022-02-21 04:24:16,940 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:16,940 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:16,959 INFO L74 IsIncluded]: Start isIncluded. First operand has 2201 states, 2201 states have (on average 1.4279872785097683) internal successors, (3143), 2200 states have internal predecessors, (3143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2784 states and 3948 transitions. [2022-02-21 04:24:16,961 INFO L87 Difference]: Start difference. First operand has 2201 states, 2201 states have (on average 1.4279872785097683) internal successors, (3143), 2200 states have internal predecessors, (3143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2784 states and 3948 transitions. [2022-02-21 04:24:17,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,167 INFO L93 Difference]: Finished difference Result 2784 states and 3948 transitions. [2022-02-21 04:24:17,168 INFO L276 IsEmpty]: Start isEmpty. Operand 2784 states and 3948 transitions. [2022-02-21 04:24:17,171 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:17,171 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:17,171 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:17,171 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:17,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2201 states, 2201 states have (on average 1.4279872785097683) internal successors, (3143), 2200 states have internal predecessors, (3143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2201 states to 2201 states and 3143 transitions. [2022-02-21 04:24:17,282 INFO L704 BuchiCegarLoop]: Abstraction has 2201 states and 3143 transitions. [2022-02-21 04:24:17,282 INFO L587 BuchiCegarLoop]: Abstraction has 2201 states and 3143 transitions. [2022-02-21 04:24:17,282 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:17,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2201 states and 3143 transitions. [2022-02-21 04:24:17,288 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2132 [2022-02-21 04:24:17,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:17,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:17,290 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,290 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,290 INFO L791 eck$LassoCheckResult]: Stem: 29898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 29838#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 29469#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29470#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29590#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 29704#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29552#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29553#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29565#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29566#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29610#L502 assume !(0 == ~M_E~0); 29611#L502-2 assume !(0 == ~T1_E~0); 29541#L507-1 assume !(0 == ~T2_E~0); 29542#L512-1 assume !(0 == ~T3_E~0); 29706#L517-1 assume !(0 == ~T4_E~0); 29523#L522-1 assume !(0 == ~E_1~0); 29524#L527-1 assume !(0 == ~E_2~0); 29725#L532-1 assume !(0 == ~E_3~0); 29830#L537-1 assume !(0 == ~E_4~0); 29852#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29820#L238 assume !(1 == ~m_pc~0); 29821#L238-2 is_master_triggered_~__retres1~0#1 := 0; 29482#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29483#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29797#L615 assume !(0 != activate_threads_~tmp~1#1); 29505#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29506#L257 assume !(1 == ~t1_pc~0); 29618#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29619#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29653#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 29476#L623 assume !(0 != activate_threads_~tmp___0~0#1); 29477#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29471#L276 assume !(1 == ~t2_pc~0); 29472#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29734#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29567#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29568#L631 assume !(0 != activate_threads_~tmp___1~0#1); 29868#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29796#L295 assume !(1 == ~t3_pc~0); 29584#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29585#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29775#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29831#L639 assume !(0 != activate_threads_~tmp___2~0#1); 29824#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29825#L314 assume !(1 == ~t4_pc~0); 29623#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29622#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29826#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29767#L647 assume !(0 != activate_threads_~tmp___3~0#1); 29717#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29718#L555 assume !(1 == ~M_E~0); 29635#L555-2 assume !(1 == ~T1_E~0); 29636#L560-1 assume !(1 == ~T2_E~0); 29525#L565-1 assume !(1 == ~T3_E~0); 29526#L570-1 assume !(1 == ~T4_E~0); 29595#L575-1 assume !(1 == ~E_1~0); 29596#L580-1 assume !(1 == ~E_2~0); 29768#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 29597#L590-1 assume !(1 == ~E_4~0); 29586#L595-1 assume { :end_inline_reset_delta_events } true; 29587#L776-2 [2022-02-21 04:24:17,291 INFO L793 eck$LassoCheckResult]: Loop: 29587#L776-2 assume !false; 31551#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31547#L477 assume !false; 31542#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31538#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31533#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31532#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 29529#L416 assume !(0 != eval_~tmp~0#1); 29531#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31669#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31668#L502-3 assume !(0 == ~M_E~0); 31667#L502-5 assume !(0 == ~T1_E~0); 31666#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31665#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31664#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31663#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31662#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31661#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31660#L537-3 assume !(0 == ~E_4~0); 31659#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31658#L238-15 assume !(1 == ~m_pc~0); 31657#L238-17 is_master_triggered_~__retres1~0#1 := 0; 31656#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31655#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31654#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31623#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29546#L257-15 assume !(1 == ~t1_pc~0); 29547#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 29745#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29856#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 29798#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29799#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29814#L276-15 assume 1 == ~t2_pc~0; 29677#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29678#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31619#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31618#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29759#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29580#L295-15 assume !(1 == ~t3_pc~0); 29581#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 29849#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29850#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29884#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29832#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29833#L314-15 assume 1 == ~t4_pc~0; 29740#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29741#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29675#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29676#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29819#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29757#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29484#L555-5 assume !(1 == ~T1_E~0); 29485#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29650#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29801#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29760#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29478#L580-3 assume !(1 == ~E_2~0); 29479#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29633#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29634#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29715#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29561#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 29744#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 29790#L795 assume !(0 == start_simulation_~tmp~3#1); 29792#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31573#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31569#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31566#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 31564#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31563#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31560#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 31558#L808 assume !(0 != start_simulation_~tmp___0~1#1); 29587#L776-2 [2022-02-21 04:24:17,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,291 INFO L85 PathProgramCache]: Analyzing trace with hash 1014532137, now seen corresponding path program 1 times [2022-02-21 04:24:17,292 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,292 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522403617] [2022-02-21 04:24:17,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,323 INFO L290 TraceCheckUtils]: 0: Hoare triple {37241#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,323 INFO L290 TraceCheckUtils]: 1: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,324 INFO L290 TraceCheckUtils]: 2: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,324 INFO L290 TraceCheckUtils]: 3: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,325 INFO L290 TraceCheckUtils]: 4: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,325 INFO L290 TraceCheckUtils]: 5: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,325 INFO L290 TraceCheckUtils]: 6: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,326 INFO L290 TraceCheckUtils]: 7: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,326 INFO L290 TraceCheckUtils]: 8: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,327 INFO L290 TraceCheckUtils]: 9: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,327 INFO L290 TraceCheckUtils]: 10: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~M_E~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,327 INFO L290 TraceCheckUtils]: 11: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T1_E~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,328 INFO L290 TraceCheckUtils]: 12: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T2_E~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,328 INFO L290 TraceCheckUtils]: 13: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T3_E~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,329 INFO L290 TraceCheckUtils]: 14: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T4_E~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,329 INFO L290 TraceCheckUtils]: 15: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~E_1~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,329 INFO L290 TraceCheckUtils]: 16: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~E_2~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,330 INFO L290 TraceCheckUtils]: 17: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~E_3~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,330 INFO L290 TraceCheckUtils]: 18: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~E_4~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,331 INFO L290 TraceCheckUtils]: 19: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,331 INFO L290 TraceCheckUtils]: 20: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(1 == ~m_pc~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,331 INFO L290 TraceCheckUtils]: 21: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} is_master_triggered_~__retres1~0#1 := 0; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,332 INFO L290 TraceCheckUtils]: 22: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,332 INFO L290 TraceCheckUtils]: 23: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,333 INFO L290 TraceCheckUtils]: 24: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 != activate_threads_~tmp~1#1); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,333 INFO L290 TraceCheckUtils]: 25: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,333 INFO L290 TraceCheckUtils]: 26: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(1 == ~t1_pc~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,334 INFO L290 TraceCheckUtils]: 27: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,334 INFO L290 TraceCheckUtils]: 28: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,334 INFO L290 TraceCheckUtils]: 29: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,335 INFO L290 TraceCheckUtils]: 30: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 != activate_threads_~tmp___0~0#1); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,335 INFO L290 TraceCheckUtils]: 31: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,336 INFO L290 TraceCheckUtils]: 32: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(1 == ~t2_pc~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,336 INFO L290 TraceCheckUtils]: 33: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,336 INFO L290 TraceCheckUtils]: 34: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,337 INFO L290 TraceCheckUtils]: 35: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,337 INFO L290 TraceCheckUtils]: 36: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 != activate_threads_~tmp___1~0#1); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,338 INFO L290 TraceCheckUtils]: 37: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,338 INFO L290 TraceCheckUtils]: 38: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(1 == ~t3_pc~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,338 INFO L290 TraceCheckUtils]: 39: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} is_transmit3_triggered_~__retres1~3#1 := 0; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,339 INFO L290 TraceCheckUtils]: 40: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,339 INFO L290 TraceCheckUtils]: 41: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,340 INFO L290 TraceCheckUtils]: 42: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 != activate_threads_~tmp___2~0#1); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,340 INFO L290 TraceCheckUtils]: 43: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,340 INFO L290 TraceCheckUtils]: 44: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(1 == ~t4_pc~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,344 INFO L290 TraceCheckUtils]: 45: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} is_transmit4_triggered_~__retres1~4#1 := 0; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,345 INFO L290 TraceCheckUtils]: 46: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,345 INFO L290 TraceCheckUtils]: 47: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,346 INFO L290 TraceCheckUtils]: 48: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(0 != activate_threads_~tmp___3~0#1); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,347 INFO L290 TraceCheckUtils]: 49: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,347 INFO L290 TraceCheckUtils]: 50: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(1 == ~M_E~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,347 INFO L290 TraceCheckUtils]: 51: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(1 == ~T1_E~0); {37243#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:17,348 INFO L290 TraceCheckUtils]: 52: Hoare triple {37243#(= ~T2_E~0 ~E_3~0)} assume !(1 == ~T2_E~0); {37244#(not (= ~E_3~0 1))} is VALID [2022-02-21 04:24:17,348 INFO L290 TraceCheckUtils]: 53: Hoare triple {37244#(not (= ~E_3~0 1))} assume !(1 == ~T3_E~0); {37244#(not (= ~E_3~0 1))} is VALID [2022-02-21 04:24:17,348 INFO L290 TraceCheckUtils]: 54: Hoare triple {37244#(not (= ~E_3~0 1))} assume !(1 == ~T4_E~0); {37244#(not (= ~E_3~0 1))} is VALID [2022-02-21 04:24:17,349 INFO L290 TraceCheckUtils]: 55: Hoare triple {37244#(not (= ~E_3~0 1))} assume !(1 == ~E_1~0); {37244#(not (= ~E_3~0 1))} is VALID [2022-02-21 04:24:17,349 INFO L290 TraceCheckUtils]: 56: Hoare triple {37244#(not (= ~E_3~0 1))} assume !(1 == ~E_2~0); {37244#(not (= ~E_3~0 1))} is VALID [2022-02-21 04:24:17,349 INFO L290 TraceCheckUtils]: 57: Hoare triple {37244#(not (= ~E_3~0 1))} assume 1 == ~E_3~0;~E_3~0 := 2; {37242#false} is VALID [2022-02-21 04:24:17,350 INFO L290 TraceCheckUtils]: 58: Hoare triple {37242#false} assume !(1 == ~E_4~0); {37242#false} is VALID [2022-02-21 04:24:17,350 INFO L290 TraceCheckUtils]: 59: Hoare triple {37242#false} assume { :end_inline_reset_delta_events } true; {37242#false} is VALID [2022-02-21 04:24:17,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,350 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,350 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522403617] [2022-02-21 04:24:17,351 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522403617] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,351 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,351 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:17,351 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [170714035] [2022-02-21 04:24:17,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,352 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:17,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,352 INFO L85 PathProgramCache]: Analyzing trace with hash -21400384, now seen corresponding path program 3 times [2022-02-21 04:24:17,352 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,352 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219787897] [2022-02-21 04:24:17,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,378 INFO L290 TraceCheckUtils]: 0: Hoare triple {37245#true} assume !false; {37245#true} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 1: Hoare triple {37245#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {37245#true} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 2: Hoare triple {37245#true} assume !false; {37245#true} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 3: Hoare triple {37245#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {37245#true} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 4: Hoare triple {37245#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {37245#true} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 5: Hoare triple {37245#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {37245#true} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 6: Hoare triple {37245#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {37245#true} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 7: Hoare triple {37245#true} assume !(0 != eval_~tmp~0#1); {37245#true} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 8: Hoare triple {37245#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {37245#true} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 9: Hoare triple {37245#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {37245#true} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 10: Hoare triple {37245#true} assume !(0 == ~M_E~0); {37245#true} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 11: Hoare triple {37245#true} assume !(0 == ~T1_E~0); {37245#true} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 12: Hoare triple {37245#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {37245#true} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 13: Hoare triple {37245#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {37245#true} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 14: Hoare triple {37245#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {37245#true} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 15: Hoare triple {37245#true} assume 0 == ~E_1~0;~E_1~0 := 1; {37245#true} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 16: Hoare triple {37245#true} assume 0 == ~E_2~0;~E_2~0 := 1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 17: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 18: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 19: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 20: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~m_pc~0); {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 21: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 22: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 23: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 24: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 25: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 26: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 27: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 28: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 29: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 30: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 31: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 32: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t2_pc~0; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 33: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,388 INFO L290 TraceCheckUtils]: 34: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,388 INFO L290 TraceCheckUtils]: 35: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,388 INFO L290 TraceCheckUtils]: 36: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,389 INFO L290 TraceCheckUtils]: 37: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,389 INFO L290 TraceCheckUtils]: 38: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,389 INFO L290 TraceCheckUtils]: 39: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,390 INFO L290 TraceCheckUtils]: 40: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,390 INFO L290 TraceCheckUtils]: 41: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,390 INFO L290 TraceCheckUtils]: 42: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,391 INFO L290 TraceCheckUtils]: 43: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,391 INFO L290 TraceCheckUtils]: 44: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,392 INFO L290 TraceCheckUtils]: 45: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,392 INFO L290 TraceCheckUtils]: 46: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,392 INFO L290 TraceCheckUtils]: 47: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,393 INFO L290 TraceCheckUtils]: 48: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,393 INFO L290 TraceCheckUtils]: 49: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,393 INFO L290 TraceCheckUtils]: 50: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,394 INFO L290 TraceCheckUtils]: 51: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T1_E~0); {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,394 INFO L290 TraceCheckUtils]: 52: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,394 INFO L290 TraceCheckUtils]: 53: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,395 INFO L290 TraceCheckUtils]: 54: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,395 INFO L290 TraceCheckUtils]: 55: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {37247#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:17,395 INFO L290 TraceCheckUtils]: 56: Hoare triple {37247#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {37246#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 57: Hoare triple {37246#false} assume 1 == ~E_3~0;~E_3~0 := 2; {37246#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 58: Hoare triple {37246#false} assume 1 == ~E_4~0;~E_4~0 := 2; {37246#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 59: Hoare triple {37246#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {37246#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 60: Hoare triple {37246#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {37246#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 61: Hoare triple {37246#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {37246#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 62: Hoare triple {37246#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {37246#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 63: Hoare triple {37246#false} assume !(0 == start_simulation_~tmp~3#1); {37246#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 64: Hoare triple {37246#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {37246#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 65: Hoare triple {37246#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {37246#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 66: Hoare triple {37246#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {37246#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 67: Hoare triple {37246#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {37246#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 68: Hoare triple {37246#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {37246#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 69: Hoare triple {37246#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {37246#false} is VALID [2022-02-21 04:24:17,398 INFO L290 TraceCheckUtils]: 70: Hoare triple {37246#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {37246#false} is VALID [2022-02-21 04:24:17,398 INFO L290 TraceCheckUtils]: 71: Hoare triple {37246#false} assume !(0 != start_simulation_~tmp___0~1#1); {37246#false} is VALID [2022-02-21 04:24:17,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,398 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,399 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [219787897] [2022-02-21 04:24:17,399 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [219787897] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,399 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,399 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:17,399 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408194355] [2022-02-21 04:24:17,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,400 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:17,400 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:17,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:17,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:17,401 INFO L87 Difference]: Start difference. First operand 2201 states and 3143 transitions. cyclomatic complexity: 944 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,820 INFO L93 Difference]: Finished difference Result 4550 states and 6445 transitions. [2022-02-21 04:24:18,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:18,820 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,871 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:18,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4550 states and 6445 transitions. [2022-02-21 04:24:19,323 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4372 [2022-02-21 04:24:19,805 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4550 states to 4550 states and 6445 transitions. [2022-02-21 04:24:19,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4550 [2022-02-21 04:24:19,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4550 [2022-02-21 04:24:19,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4550 states and 6445 transitions. [2022-02-21 04:24:19,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:19,812 INFO L681 BuchiCegarLoop]: Abstraction has 4550 states and 6445 transitions. [2022-02-21 04:24:19,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4550 states and 6445 transitions. [2022-02-21 04:24:19,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4550 to 4494. [2022-02-21 04:24:19,870 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:19,877 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4550 states and 6445 transitions. Second operand has 4494 states, 4494 states have (on average 1.4181130396083668) internal successors, (6373), 4493 states have internal predecessors, (6373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,885 INFO L74 IsIncluded]: Start isIncluded. First operand 4550 states and 6445 transitions. Second operand has 4494 states, 4494 states have (on average 1.4181130396083668) internal successors, (6373), 4493 states have internal predecessors, (6373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,891 INFO L87 Difference]: Start difference. First operand 4550 states and 6445 transitions. Second operand has 4494 states, 4494 states have (on average 1.4181130396083668) internal successors, (6373), 4493 states have internal predecessors, (6373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,445 INFO L93 Difference]: Finished difference Result 4550 states and 6445 transitions. [2022-02-21 04:24:20,445 INFO L276 IsEmpty]: Start isEmpty. Operand 4550 states and 6445 transitions. [2022-02-21 04:24:20,450 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,450 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,457 INFO L74 IsIncluded]: Start isIncluded. First operand has 4494 states, 4494 states have (on average 1.4181130396083668) internal successors, (6373), 4493 states have internal predecessors, (6373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4550 states and 6445 transitions. [2022-02-21 04:24:20,465 INFO L87 Difference]: Start difference. First operand has 4494 states, 4494 states have (on average 1.4181130396083668) internal successors, (6373), 4493 states have internal predecessors, (6373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4550 states and 6445 transitions. [2022-02-21 04:24:20,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,967 INFO L93 Difference]: Finished difference Result 4550 states and 6445 transitions. [2022-02-21 04:24:20,967 INFO L276 IsEmpty]: Start isEmpty. Operand 4550 states and 6445 transitions. [2022-02-21 04:24:20,971 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,971 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,971 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:20,971 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:20,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4494 states, 4494 states have (on average 1.4181130396083668) internal successors, (6373), 4493 states have internal predecessors, (6373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4494 states to 4494 states and 6373 transitions. [2022-02-21 04:24:21,448 INFO L704 BuchiCegarLoop]: Abstraction has 4494 states and 6373 transitions. [2022-02-21 04:24:21,448 INFO L587 BuchiCegarLoop]: Abstraction has 4494 states and 6373 transitions. [2022-02-21 04:24:21,448 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:24:21,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4494 states and 6373 transitions. [2022-02-21 04:24:21,456 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4324 [2022-02-21 04:24:21,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:21,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:21,457 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:21,458 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:21,458 INFO L791 eck$LassoCheckResult]: Stem: 42277#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 42200#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 41800#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41801#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41925#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 42041#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41885#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41886#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41898#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41899#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41944#L502 assume !(0 == ~M_E~0); 41945#L502-2 assume !(0 == ~T1_E~0); 41873#L507-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41874#L512-1 assume !(0 == ~T3_E~0); 42044#L517-1 assume !(0 == ~T4_E~0); 41851#L522-1 assume !(0 == ~E_1~0); 41852#L527-1 assume !(0 == ~E_2~0); 42192#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 42193#L537-1 assume !(0 == ~E_4~0); 42337#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42336#L238 assume !(1 == ~m_pc~0); 42335#L238-2 is_master_triggered_~__retres1~0#1 := 0; 42334#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42333#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 42332#L615 assume !(0 != activate_threads_~tmp~1#1); 42331#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42330#L257 assume !(1 == ~t1_pc~0); 42329#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42328#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42327#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 42326#L623 assume !(0 != activate_threads_~tmp___0~0#1); 42325#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42324#L276 assume !(1 == ~t2_pc~0); 42323#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42321#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42319#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 42316#L631 assume !(0 != activate_threads_~tmp___1~0#1); 42315#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42314#L295 assume !(1 == ~t3_pc~0); 42313#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42312#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42311#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 42310#L639 assume !(0 != activate_threads_~tmp___2~0#1); 42309#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42308#L314 assume !(1 == ~t4_pc~0); 42307#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 42305#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42304#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42303#L647 assume !(0 != activate_threads_~tmp___3~0#1); 42302#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42301#L555 assume !(1 == ~M_E~0); 42300#L555-2 assume !(1 == ~T1_E~0); 42299#L560-1 assume !(1 == ~T2_E~0); 42298#L565-1 assume !(1 == ~T3_E~0); 42297#L570-1 assume !(1 == ~T4_E~0); 42296#L575-1 assume !(1 == ~E_1~0); 42295#L580-1 assume !(1 == ~E_2~0); 42293#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 42294#L590-1 assume !(1 == ~E_4~0); 44404#L595-1 assume { :end_inline_reset_delta_events } true; 44400#L776-2 [2022-02-21 04:24:21,458 INFO L793 eck$LassoCheckResult]: Loop: 44400#L776-2 assume !false; 44345#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44341#L477 assume !false; 44340#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44313#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44307#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44305#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 44302#L416 assume !(0 != eval_~tmp~0#1); 44303#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46096#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46095#L502-3 assume !(0 == ~M_E~0); 46093#L502-5 assume !(0 == ~T1_E~0); 46091#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46089#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46087#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46085#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46083#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46075#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46071#L537-3 assume !(0 == ~E_4~0); 46069#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46067#L238-15 assume !(1 == ~m_pc~0); 46065#L238-17 is_master_triggered_~__retres1~0#1 := 0; 46063#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46061#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 46059#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46057#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46047#L257-15 assume !(1 == ~t1_pc~0); 46046#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 46044#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46043#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 46042#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46041#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46039#L276-15 assume !(1 == ~t2_pc~0); 46036#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 46035#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46033#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46031#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 46028#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44532#L295-15 assume !(1 == ~t3_pc~0); 44531#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 44530#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44528#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44526#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44524#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44522#L314-15 assume 1 == ~t4_pc~0; 44519#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44517#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44515#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44513#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44509#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44507#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44505#L555-5 assume !(1 == ~T1_E~0); 44503#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44500#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44498#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44496#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44495#L580-3 assume !(1 == ~E_2~0); 44451#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44450#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44449#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44442#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44438#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44436#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 44434#L795 assume !(0 == start_simulation_~tmp~3#1); 44430#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44420#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44416#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44415#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 44414#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44413#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44410#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 44405#L808 assume !(0 != start_simulation_~tmp___0~1#1); 44400#L776-2 [2022-02-21 04:24:21,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:21,459 INFO L85 PathProgramCache]: Analyzing trace with hash -27236631, now seen corresponding path program 1 times [2022-02-21 04:24:21,459 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:21,459 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280206526] [2022-02-21 04:24:21,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:21,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:21,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:21,486 INFO L290 TraceCheckUtils]: 0: Hoare triple {55397#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,487 INFO L290 TraceCheckUtils]: 1: Hoare triple {55399#(= ~T2_E~0 2)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,487 INFO L290 TraceCheckUtils]: 2: Hoare triple {55399#(= ~T2_E~0 2)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,487 INFO L290 TraceCheckUtils]: 3: Hoare triple {55399#(= ~T2_E~0 2)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,488 INFO L290 TraceCheckUtils]: 4: Hoare triple {55399#(= ~T2_E~0 2)} assume 1 == ~m_i~0;~m_st~0 := 0; {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,488 INFO L290 TraceCheckUtils]: 5: Hoare triple {55399#(= ~T2_E~0 2)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,488 INFO L290 TraceCheckUtils]: 6: Hoare triple {55399#(= ~T2_E~0 2)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,489 INFO L290 TraceCheckUtils]: 7: Hoare triple {55399#(= ~T2_E~0 2)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,489 INFO L290 TraceCheckUtils]: 8: Hoare triple {55399#(= ~T2_E~0 2)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,489 INFO L290 TraceCheckUtils]: 9: Hoare triple {55399#(= ~T2_E~0 2)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,490 INFO L290 TraceCheckUtils]: 10: Hoare triple {55399#(= ~T2_E~0 2)} assume !(0 == ~M_E~0); {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,490 INFO L290 TraceCheckUtils]: 11: Hoare triple {55399#(= ~T2_E~0 2)} assume !(0 == ~T1_E~0); {55399#(= ~T2_E~0 2)} is VALID [2022-02-21 04:24:21,490 INFO L290 TraceCheckUtils]: 12: Hoare triple {55399#(= ~T2_E~0 2)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {55398#false} is VALID [2022-02-21 04:24:21,491 INFO L290 TraceCheckUtils]: 13: Hoare triple {55398#false} assume !(0 == ~T3_E~0); {55398#false} is VALID [2022-02-21 04:24:21,491 INFO L290 TraceCheckUtils]: 14: Hoare triple {55398#false} assume !(0 == ~T4_E~0); {55398#false} is VALID [2022-02-21 04:24:21,491 INFO L290 TraceCheckUtils]: 15: Hoare triple {55398#false} assume !(0 == ~E_1~0); {55398#false} is VALID [2022-02-21 04:24:21,491 INFO L290 TraceCheckUtils]: 16: Hoare triple {55398#false} assume !(0 == ~E_2~0); {55398#false} is VALID [2022-02-21 04:24:21,491 INFO L290 TraceCheckUtils]: 17: Hoare triple {55398#false} assume 0 == ~E_3~0;~E_3~0 := 1; {55398#false} is VALID [2022-02-21 04:24:21,491 INFO L290 TraceCheckUtils]: 18: Hoare triple {55398#false} assume !(0 == ~E_4~0); {55398#false} is VALID [2022-02-21 04:24:21,491 INFO L290 TraceCheckUtils]: 19: Hoare triple {55398#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {55398#false} is VALID [2022-02-21 04:24:21,492 INFO L290 TraceCheckUtils]: 20: Hoare triple {55398#false} assume !(1 == ~m_pc~0); {55398#false} is VALID [2022-02-21 04:24:21,492 INFO L290 TraceCheckUtils]: 21: Hoare triple {55398#false} is_master_triggered_~__retres1~0#1 := 0; {55398#false} is VALID [2022-02-21 04:24:21,492 INFO L290 TraceCheckUtils]: 22: Hoare triple {55398#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {55398#false} is VALID [2022-02-21 04:24:21,492 INFO L290 TraceCheckUtils]: 23: Hoare triple {55398#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {55398#false} is VALID [2022-02-21 04:24:21,492 INFO L290 TraceCheckUtils]: 24: Hoare triple {55398#false} assume !(0 != activate_threads_~tmp~1#1); {55398#false} is VALID [2022-02-21 04:24:21,493 INFO L290 TraceCheckUtils]: 25: Hoare triple {55398#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {55398#false} is VALID [2022-02-21 04:24:21,493 INFO L290 TraceCheckUtils]: 26: Hoare triple {55398#false} assume !(1 == ~t1_pc~0); {55398#false} is VALID [2022-02-21 04:24:21,493 INFO L290 TraceCheckUtils]: 27: Hoare triple {55398#false} is_transmit1_triggered_~__retres1~1#1 := 0; {55398#false} is VALID [2022-02-21 04:24:21,494 INFO L290 TraceCheckUtils]: 28: Hoare triple {55398#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {55398#false} is VALID [2022-02-21 04:24:21,494 INFO L290 TraceCheckUtils]: 29: Hoare triple {55398#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {55398#false} is VALID [2022-02-21 04:24:21,494 INFO L290 TraceCheckUtils]: 30: Hoare triple {55398#false} assume !(0 != activate_threads_~tmp___0~0#1); {55398#false} is VALID [2022-02-21 04:24:21,494 INFO L290 TraceCheckUtils]: 31: Hoare triple {55398#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {55398#false} is VALID [2022-02-21 04:24:21,494 INFO L290 TraceCheckUtils]: 32: Hoare triple {55398#false} assume !(1 == ~t2_pc~0); {55398#false} is VALID [2022-02-21 04:24:21,494 INFO L290 TraceCheckUtils]: 33: Hoare triple {55398#false} is_transmit2_triggered_~__retres1~2#1 := 0; {55398#false} is VALID [2022-02-21 04:24:21,494 INFO L290 TraceCheckUtils]: 34: Hoare triple {55398#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {55398#false} is VALID [2022-02-21 04:24:21,495 INFO L290 TraceCheckUtils]: 35: Hoare triple {55398#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {55398#false} is VALID [2022-02-21 04:24:21,495 INFO L290 TraceCheckUtils]: 36: Hoare triple {55398#false} assume !(0 != activate_threads_~tmp___1~0#1); {55398#false} is VALID [2022-02-21 04:24:21,495 INFO L290 TraceCheckUtils]: 37: Hoare triple {55398#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {55398#false} is VALID [2022-02-21 04:24:21,495 INFO L290 TraceCheckUtils]: 38: Hoare triple {55398#false} assume !(1 == ~t3_pc~0); {55398#false} is VALID [2022-02-21 04:24:21,495 INFO L290 TraceCheckUtils]: 39: Hoare triple {55398#false} is_transmit3_triggered_~__retres1~3#1 := 0; {55398#false} is VALID [2022-02-21 04:24:21,495 INFO L290 TraceCheckUtils]: 40: Hoare triple {55398#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {55398#false} is VALID [2022-02-21 04:24:21,495 INFO L290 TraceCheckUtils]: 41: Hoare triple {55398#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {55398#false} is VALID [2022-02-21 04:24:21,496 INFO L290 TraceCheckUtils]: 42: Hoare triple {55398#false} assume !(0 != activate_threads_~tmp___2~0#1); {55398#false} is VALID [2022-02-21 04:24:21,496 INFO L290 TraceCheckUtils]: 43: Hoare triple {55398#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {55398#false} is VALID [2022-02-21 04:24:21,496 INFO L290 TraceCheckUtils]: 44: Hoare triple {55398#false} assume !(1 == ~t4_pc~0); {55398#false} is VALID [2022-02-21 04:24:21,496 INFO L290 TraceCheckUtils]: 45: Hoare triple {55398#false} is_transmit4_triggered_~__retres1~4#1 := 0; {55398#false} is VALID [2022-02-21 04:24:21,496 INFO L290 TraceCheckUtils]: 46: Hoare triple {55398#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {55398#false} is VALID [2022-02-21 04:24:21,496 INFO L290 TraceCheckUtils]: 47: Hoare triple {55398#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {55398#false} is VALID [2022-02-21 04:24:21,496 INFO L290 TraceCheckUtils]: 48: Hoare triple {55398#false} assume !(0 != activate_threads_~tmp___3~0#1); {55398#false} is VALID [2022-02-21 04:24:21,497 INFO L290 TraceCheckUtils]: 49: Hoare triple {55398#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {55398#false} is VALID [2022-02-21 04:24:21,497 INFO L290 TraceCheckUtils]: 50: Hoare triple {55398#false} assume !(1 == ~M_E~0); {55398#false} is VALID [2022-02-21 04:24:21,497 INFO L290 TraceCheckUtils]: 51: Hoare triple {55398#false} assume !(1 == ~T1_E~0); {55398#false} is VALID [2022-02-21 04:24:21,497 INFO L290 TraceCheckUtils]: 52: Hoare triple {55398#false} assume !(1 == ~T2_E~0); {55398#false} is VALID [2022-02-21 04:24:21,497 INFO L290 TraceCheckUtils]: 53: Hoare triple {55398#false} assume !(1 == ~T3_E~0); {55398#false} is VALID [2022-02-21 04:24:21,497 INFO L290 TraceCheckUtils]: 54: Hoare triple {55398#false} assume !(1 == ~T4_E~0); {55398#false} is VALID [2022-02-21 04:24:21,497 INFO L290 TraceCheckUtils]: 55: Hoare triple {55398#false} assume !(1 == ~E_1~0); {55398#false} is VALID [2022-02-21 04:24:21,498 INFO L290 TraceCheckUtils]: 56: Hoare triple {55398#false} assume !(1 == ~E_2~0); {55398#false} is VALID [2022-02-21 04:24:21,498 INFO L290 TraceCheckUtils]: 57: Hoare triple {55398#false} assume 1 == ~E_3~0;~E_3~0 := 2; {55398#false} is VALID [2022-02-21 04:24:21,498 INFO L290 TraceCheckUtils]: 58: Hoare triple {55398#false} assume !(1 == ~E_4~0); {55398#false} is VALID [2022-02-21 04:24:21,498 INFO L290 TraceCheckUtils]: 59: Hoare triple {55398#false} assume { :end_inline_reset_delta_events } true; {55398#false} is VALID [2022-02-21 04:24:21,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:21,499 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:21,499 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280206526] [2022-02-21 04:24:21,499 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280206526] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:21,499 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:21,499 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:21,499 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262429424] [2022-02-21 04:24:21,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:21,500 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:21,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:21,500 INFO L85 PathProgramCache]: Analyzing trace with hash -15775971, now seen corresponding path program 2 times [2022-02-21 04:24:21,500 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:21,501 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162647757] [2022-02-21 04:24:21,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:21,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:21,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:21,528 INFO L290 TraceCheckUtils]: 0: Hoare triple {55400#true} assume !false; {55400#true} is VALID [2022-02-21 04:24:21,529 INFO L290 TraceCheckUtils]: 1: Hoare triple {55400#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {55400#true} is VALID [2022-02-21 04:24:21,529 INFO L290 TraceCheckUtils]: 2: Hoare triple {55400#true} assume !false; {55400#true} is VALID [2022-02-21 04:24:21,529 INFO L290 TraceCheckUtils]: 3: Hoare triple {55400#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {55400#true} is VALID [2022-02-21 04:24:21,529 INFO L290 TraceCheckUtils]: 4: Hoare triple {55400#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {55400#true} is VALID [2022-02-21 04:24:21,529 INFO L290 TraceCheckUtils]: 5: Hoare triple {55400#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {55400#true} is VALID [2022-02-21 04:24:21,529 INFO L290 TraceCheckUtils]: 6: Hoare triple {55400#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {55400#true} is VALID [2022-02-21 04:24:21,529 INFO L290 TraceCheckUtils]: 7: Hoare triple {55400#true} assume !(0 != eval_~tmp~0#1); {55400#true} is VALID [2022-02-21 04:24:21,530 INFO L290 TraceCheckUtils]: 8: Hoare triple {55400#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {55400#true} is VALID [2022-02-21 04:24:21,530 INFO L290 TraceCheckUtils]: 9: Hoare triple {55400#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {55400#true} is VALID [2022-02-21 04:24:21,530 INFO L290 TraceCheckUtils]: 10: Hoare triple {55400#true} assume !(0 == ~M_E~0); {55400#true} is VALID [2022-02-21 04:24:21,530 INFO L290 TraceCheckUtils]: 11: Hoare triple {55400#true} assume !(0 == ~T1_E~0); {55400#true} is VALID [2022-02-21 04:24:21,530 INFO L290 TraceCheckUtils]: 12: Hoare triple {55400#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {55400#true} is VALID [2022-02-21 04:24:21,530 INFO L290 TraceCheckUtils]: 13: Hoare triple {55400#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {55400#true} is VALID [2022-02-21 04:24:21,530 INFO L290 TraceCheckUtils]: 14: Hoare triple {55400#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {55400#true} is VALID [2022-02-21 04:24:21,530 INFO L290 TraceCheckUtils]: 15: Hoare triple {55400#true} assume 0 == ~E_1~0;~E_1~0 := 1; {55400#true} is VALID [2022-02-21 04:24:21,531 INFO L290 TraceCheckUtils]: 16: Hoare triple {55400#true} assume 0 == ~E_2~0;~E_2~0 := 1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,531 INFO L290 TraceCheckUtils]: 17: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,532 INFO L290 TraceCheckUtils]: 18: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,532 INFO L290 TraceCheckUtils]: 19: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,532 INFO L290 TraceCheckUtils]: 20: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~m_pc~0); {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,533 INFO L290 TraceCheckUtils]: 21: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,533 INFO L290 TraceCheckUtils]: 22: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,533 INFO L290 TraceCheckUtils]: 23: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,534 INFO L290 TraceCheckUtils]: 24: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,534 INFO L290 TraceCheckUtils]: 25: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,534 INFO L290 TraceCheckUtils]: 26: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,535 INFO L290 TraceCheckUtils]: 27: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,535 INFO L290 TraceCheckUtils]: 28: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,535 INFO L290 TraceCheckUtils]: 29: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,536 INFO L290 TraceCheckUtils]: 30: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,536 INFO L290 TraceCheckUtils]: 31: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,537 INFO L290 TraceCheckUtils]: 32: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t2_pc~0); {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,537 INFO L290 TraceCheckUtils]: 33: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,537 INFO L290 TraceCheckUtils]: 34: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,538 INFO L290 TraceCheckUtils]: 35: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,538 INFO L290 TraceCheckUtils]: 36: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,538 INFO L290 TraceCheckUtils]: 37: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,539 INFO L290 TraceCheckUtils]: 38: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,539 INFO L290 TraceCheckUtils]: 39: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,539 INFO L290 TraceCheckUtils]: 40: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,540 INFO L290 TraceCheckUtils]: 41: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,540 INFO L290 TraceCheckUtils]: 42: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,540 INFO L290 TraceCheckUtils]: 43: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,541 INFO L290 TraceCheckUtils]: 44: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,541 INFO L290 TraceCheckUtils]: 45: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,541 INFO L290 TraceCheckUtils]: 46: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,542 INFO L290 TraceCheckUtils]: 47: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,542 INFO L290 TraceCheckUtils]: 48: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,542 INFO L290 TraceCheckUtils]: 49: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,543 INFO L290 TraceCheckUtils]: 50: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,543 INFO L290 TraceCheckUtils]: 51: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T1_E~0); {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,543 INFO L290 TraceCheckUtils]: 52: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,544 INFO L290 TraceCheckUtils]: 53: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,544 INFO L290 TraceCheckUtils]: 54: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,544 INFO L290 TraceCheckUtils]: 55: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {55402#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:21,545 INFO L290 TraceCheckUtils]: 56: Hoare triple {55402#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {55401#false} is VALID [2022-02-21 04:24:21,545 INFO L290 TraceCheckUtils]: 57: Hoare triple {55401#false} assume 1 == ~E_3~0;~E_3~0 := 2; {55401#false} is VALID [2022-02-21 04:24:21,545 INFO L290 TraceCheckUtils]: 58: Hoare triple {55401#false} assume 1 == ~E_4~0;~E_4~0 := 2; {55401#false} is VALID [2022-02-21 04:24:21,545 INFO L290 TraceCheckUtils]: 59: Hoare triple {55401#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {55401#false} is VALID [2022-02-21 04:24:21,545 INFO L290 TraceCheckUtils]: 60: Hoare triple {55401#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {55401#false} is VALID [2022-02-21 04:24:21,546 INFO L290 TraceCheckUtils]: 61: Hoare triple {55401#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {55401#false} is VALID [2022-02-21 04:24:21,546 INFO L290 TraceCheckUtils]: 62: Hoare triple {55401#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {55401#false} is VALID [2022-02-21 04:24:21,546 INFO L290 TraceCheckUtils]: 63: Hoare triple {55401#false} assume !(0 == start_simulation_~tmp~3#1); {55401#false} is VALID [2022-02-21 04:24:21,546 INFO L290 TraceCheckUtils]: 64: Hoare triple {55401#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {55401#false} is VALID [2022-02-21 04:24:21,546 INFO L290 TraceCheckUtils]: 65: Hoare triple {55401#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {55401#false} is VALID [2022-02-21 04:24:21,546 INFO L290 TraceCheckUtils]: 66: Hoare triple {55401#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {55401#false} is VALID [2022-02-21 04:24:21,546 INFO L290 TraceCheckUtils]: 67: Hoare triple {55401#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {55401#false} is VALID [2022-02-21 04:24:21,547 INFO L290 TraceCheckUtils]: 68: Hoare triple {55401#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {55401#false} is VALID [2022-02-21 04:24:21,547 INFO L290 TraceCheckUtils]: 69: Hoare triple {55401#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {55401#false} is VALID [2022-02-21 04:24:21,547 INFO L290 TraceCheckUtils]: 70: Hoare triple {55401#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {55401#false} is VALID [2022-02-21 04:24:21,547 INFO L290 TraceCheckUtils]: 71: Hoare triple {55401#false} assume !(0 != start_simulation_~tmp___0~1#1); {55401#false} is VALID [2022-02-21 04:24:21,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:21,548 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:21,548 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162647757] [2022-02-21 04:24:21,548 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162647757] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:21,548 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:21,548 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:21,548 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1362488723] [2022-02-21 04:24:21,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:21,549 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:21,549 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:21,549 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:21,549 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:21,550 INFO L87 Difference]: Start difference. First operand 4494 states and 6373 transitions. cyclomatic complexity: 1883 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,523 INFO L93 Difference]: Finished difference Result 4444 states and 6260 transitions. [2022-02-21 04:24:22,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:22,523 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,591 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:22,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4444 states and 6260 transitions. [2022-02-21 04:24:23,026 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4324 [2022-02-21 04:24:23,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4444 states to 4444 states and 6260 transitions. [2022-02-21 04:24:23,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4444 [2022-02-21 04:24:23,463 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4444 [2022-02-21 04:24:23,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4444 states and 6260 transitions. [2022-02-21 04:24:23,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:23,468 INFO L681 BuchiCegarLoop]: Abstraction has 4444 states and 6260 transitions. [2022-02-21 04:24:23,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4444 states and 6260 transitions. [2022-02-21 04:24:23,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4444 to 2614. [2022-02-21 04:24:23,507 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:23,511 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4444 states and 6260 transitions. Second operand has 2614 states, 2614 states have (on average 1.4020657995409334) internal successors, (3665), 2613 states have internal predecessors, (3665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,514 INFO L74 IsIncluded]: Start isIncluded. First operand 4444 states and 6260 transitions. Second operand has 2614 states, 2614 states have (on average 1.4020657995409334) internal successors, (3665), 2613 states have internal predecessors, (3665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,518 INFO L87 Difference]: Start difference. First operand 4444 states and 6260 transitions. Second operand has 2614 states, 2614 states have (on average 1.4020657995409334) internal successors, (3665), 2613 states have internal predecessors, (3665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,953 INFO L93 Difference]: Finished difference Result 4444 states and 6260 transitions. [2022-02-21 04:24:23,953 INFO L276 IsEmpty]: Start isEmpty. Operand 4444 states and 6260 transitions. [2022-02-21 04:24:23,957 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:23,957 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:23,960 INFO L74 IsIncluded]: Start isIncluded. First operand has 2614 states, 2614 states have (on average 1.4020657995409334) internal successors, (3665), 2613 states have internal predecessors, (3665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4444 states and 6260 transitions. [2022-02-21 04:24:23,961 INFO L87 Difference]: Start difference. First operand has 2614 states, 2614 states have (on average 1.4020657995409334) internal successors, (3665), 2613 states have internal predecessors, (3665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4444 states and 6260 transitions. [2022-02-21 04:24:24,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,455 INFO L93 Difference]: Finished difference Result 4444 states and 6260 transitions. [2022-02-21 04:24:24,455 INFO L276 IsEmpty]: Start isEmpty. Operand 4444 states and 6260 transitions. [2022-02-21 04:24:24,459 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:24,459 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:24,459 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:24,459 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:24,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2614 states, 2614 states have (on average 1.4020657995409334) internal successors, (3665), 2613 states have internal predecessors, (3665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2614 states to 2614 states and 3665 transitions. [2022-02-21 04:24:24,611 INFO L704 BuchiCegarLoop]: Abstraction has 2614 states and 3665 transitions. [2022-02-21 04:24:24,611 INFO L587 BuchiCegarLoop]: Abstraction has 2614 states and 3665 transitions. [2022-02-21 04:24:24,611 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:24:24,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2614 states and 3665 transitions. [2022-02-21 04:24:24,616 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2500 [2022-02-21 04:24:24,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:24,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:24,617 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:24,617 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:24,618 INFO L791 eck$LassoCheckResult]: Stem: 60321#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 60234#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 59847#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59848#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59972#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 60084#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59930#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59931#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59943#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59944#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59989#L502 assume !(0 == ~M_E~0); 59990#L502-2 assume !(0 == ~T1_E~0); 59922#L507-1 assume !(0 == ~T2_E~0); 59923#L512-1 assume !(0 == ~T3_E~0); 60086#L517-1 assume !(0 == ~T4_E~0); 59901#L522-1 assume !(0 == ~E_1~0); 59902#L527-1 assume !(0 == ~E_2~0); 60106#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 60222#L537-1 assume !(0 == ~E_4~0); 60249#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60250#L238 assume !(1 == ~m_pc~0); 60302#L238-2 is_master_triggered_~__retres1~0#1 := 0; 60303#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60298#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 60299#L615 assume !(0 != activate_threads_~tmp~1#1); 59883#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59884#L257 assume !(1 == ~t1_pc~0); 59997#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 59998#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60034#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 60035#L623 assume !(0 != activate_threads_~tmp___0~0#1); 59958#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59959#L276 assume !(1 == ~t2_pc~0); 60118#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 60119#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59945#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 59946#L631 assume !(0 != activate_threads_~tmp___1~0#1); 60294#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60295#L295 assume !(1 == ~t3_pc~0); 59964#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59965#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60276#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 60277#L639 assume !(0 != activate_threads_~tmp___2~0#1); 60214#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60215#L314 assume !(1 == ~t4_pc~0); 60002#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 60001#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60216#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 60217#L647 assume !(0 != activate_threads_~tmp___3~0#1); 60098#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60099#L555 assume !(1 == ~M_E~0); 60014#L555-2 assume !(1 == ~T1_E~0); 60015#L560-1 assume !(1 == ~T2_E~0); 59903#L565-1 assume !(1 == ~T3_E~0); 59904#L570-1 assume !(1 == ~T4_E~0); 60344#L575-1 assume !(1 == ~E_1~0); 60153#L580-1 assume !(1 == ~E_2~0); 60154#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 59977#L590-1 assume !(1 == ~E_4~0); 59966#L595-1 assume { :end_inline_reset_delta_events } true; 59967#L776-2 [2022-02-21 04:24:24,618 INFO L793 eck$LassoCheckResult]: Loop: 59967#L776-2 assume !false; 59934#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59935#L477 assume !false; 60024#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 60025#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59866#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59867#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 59907#L416 assume !(0 != eval_~tmp~0#1); 59909#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61986#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61981#L502-3 assume !(0 == ~M_E~0); 61977#L502-5 assume !(0 == ~T1_E~0); 61973#L507-3 assume !(0 == ~T2_E~0); 61969#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61965#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61961#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61959#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61952#L532-3 assume !(0 == ~E_3~0); 61953#L537-3 assume !(0 == ~E_4~0); 62369#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62368#L238-15 assume !(1 == ~m_pc~0); 62367#L238-17 is_master_triggered_~__retres1~0#1 := 0; 62366#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62365#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 62364#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62362#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62034#L257-15 assume !(1 == ~t1_pc~0); 62032#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 62030#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62028#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 62026#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62024#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62022#L276-15 assume 1 == ~t2_pc~0; 62019#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62016#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62013#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 62010#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62008#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62006#L295-15 assume !(1 == ~t3_pc~0); 61722#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 62001#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61998#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61995#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61992#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61989#L314-15 assume !(1 == ~t4_pc~0); 61984#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 61979#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61975#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61971#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61967#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61963#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61960#L555-5 assume !(1 == ~T1_E~0); 61958#L560-3 assume !(1 == ~T2_E~0); 61957#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61956#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61955#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 61954#L580-3 assume !(1 == ~E_2~0); 61909#L585-3 assume !(1 == ~E_3~0); 61907#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61906#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 61826#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 61822#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 61820#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 61818#L795 assume !(0 == start_simulation_~tmp~3#1); 61816#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 61810#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 61807#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 61805#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 61801#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 61800#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60094#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 60095#L808 assume !(0 != start_simulation_~tmp___0~1#1); 59967#L776-2 [2022-02-21 04:24:24,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1911925415, now seen corresponding path program 1 times [2022-02-21 04:24:24,619 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,619 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103710950] [2022-02-21 04:24:24,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,644 INFO L290 TraceCheckUtils]: 0: Hoare triple {71352#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,645 INFO L290 TraceCheckUtils]: 1: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,645 INFO L290 TraceCheckUtils]: 2: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,645 INFO L290 TraceCheckUtils]: 3: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,646 INFO L290 TraceCheckUtils]: 4: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,646 INFO L290 TraceCheckUtils]: 5: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,647 INFO L290 TraceCheckUtils]: 6: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,647 INFO L290 TraceCheckUtils]: 7: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,647 INFO L290 TraceCheckUtils]: 8: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,648 INFO L290 TraceCheckUtils]: 9: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,648 INFO L290 TraceCheckUtils]: 10: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~M_E~0); {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,649 INFO L290 TraceCheckUtils]: 11: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T1_E~0); {71354#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:24,649 INFO L290 TraceCheckUtils]: 12: Hoare triple {71354#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T2_E~0); {71355#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:24,649 INFO L290 TraceCheckUtils]: 13: Hoare triple {71355#(not (= ~E_3~0 0))} assume !(0 == ~T3_E~0); {71355#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:24,650 INFO L290 TraceCheckUtils]: 14: Hoare triple {71355#(not (= ~E_3~0 0))} assume !(0 == ~T4_E~0); {71355#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:24,650 INFO L290 TraceCheckUtils]: 15: Hoare triple {71355#(not (= ~E_3~0 0))} assume !(0 == ~E_1~0); {71355#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:24,650 INFO L290 TraceCheckUtils]: 16: Hoare triple {71355#(not (= ~E_3~0 0))} assume !(0 == ~E_2~0); {71355#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:24,651 INFO L290 TraceCheckUtils]: 17: Hoare triple {71355#(not (= ~E_3~0 0))} assume 0 == ~E_3~0;~E_3~0 := 1; {71353#false} is VALID [2022-02-21 04:24:24,651 INFO L290 TraceCheckUtils]: 18: Hoare triple {71353#false} assume !(0 == ~E_4~0); {71353#false} is VALID [2022-02-21 04:24:24,651 INFO L290 TraceCheckUtils]: 19: Hoare triple {71353#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {71353#false} is VALID [2022-02-21 04:24:24,651 INFO L290 TraceCheckUtils]: 20: Hoare triple {71353#false} assume !(1 == ~m_pc~0); {71353#false} is VALID [2022-02-21 04:24:24,651 INFO L290 TraceCheckUtils]: 21: Hoare triple {71353#false} is_master_triggered_~__retres1~0#1 := 0; {71353#false} is VALID [2022-02-21 04:24:24,652 INFO L290 TraceCheckUtils]: 22: Hoare triple {71353#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {71353#false} is VALID [2022-02-21 04:24:24,652 INFO L290 TraceCheckUtils]: 23: Hoare triple {71353#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {71353#false} is VALID [2022-02-21 04:24:24,652 INFO L290 TraceCheckUtils]: 24: Hoare triple {71353#false} assume !(0 != activate_threads_~tmp~1#1); {71353#false} is VALID [2022-02-21 04:24:24,652 INFO L290 TraceCheckUtils]: 25: Hoare triple {71353#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {71353#false} is VALID [2022-02-21 04:24:24,652 INFO L290 TraceCheckUtils]: 26: Hoare triple {71353#false} assume !(1 == ~t1_pc~0); {71353#false} is VALID [2022-02-21 04:24:24,652 INFO L290 TraceCheckUtils]: 27: Hoare triple {71353#false} is_transmit1_triggered_~__retres1~1#1 := 0; {71353#false} is VALID [2022-02-21 04:24:24,652 INFO L290 TraceCheckUtils]: 28: Hoare triple {71353#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {71353#false} is VALID [2022-02-21 04:24:24,653 INFO L290 TraceCheckUtils]: 29: Hoare triple {71353#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {71353#false} is VALID [2022-02-21 04:24:24,653 INFO L290 TraceCheckUtils]: 30: Hoare triple {71353#false} assume !(0 != activate_threads_~tmp___0~0#1); {71353#false} is VALID [2022-02-21 04:24:24,653 INFO L290 TraceCheckUtils]: 31: Hoare triple {71353#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {71353#false} is VALID [2022-02-21 04:24:24,653 INFO L290 TraceCheckUtils]: 32: Hoare triple {71353#false} assume !(1 == ~t2_pc~0); {71353#false} is VALID [2022-02-21 04:24:24,653 INFO L290 TraceCheckUtils]: 33: Hoare triple {71353#false} is_transmit2_triggered_~__retres1~2#1 := 0; {71353#false} is VALID [2022-02-21 04:24:24,653 INFO L290 TraceCheckUtils]: 34: Hoare triple {71353#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {71353#false} is VALID [2022-02-21 04:24:24,653 INFO L290 TraceCheckUtils]: 35: Hoare triple {71353#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {71353#false} is VALID [2022-02-21 04:24:24,654 INFO L290 TraceCheckUtils]: 36: Hoare triple {71353#false} assume !(0 != activate_threads_~tmp___1~0#1); {71353#false} is VALID [2022-02-21 04:24:24,654 INFO L290 TraceCheckUtils]: 37: Hoare triple {71353#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {71353#false} is VALID [2022-02-21 04:24:24,654 INFO L290 TraceCheckUtils]: 38: Hoare triple {71353#false} assume !(1 == ~t3_pc~0); {71353#false} is VALID [2022-02-21 04:24:24,654 INFO L290 TraceCheckUtils]: 39: Hoare triple {71353#false} is_transmit3_triggered_~__retres1~3#1 := 0; {71353#false} is VALID [2022-02-21 04:24:24,654 INFO L290 TraceCheckUtils]: 40: Hoare triple {71353#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {71353#false} is VALID [2022-02-21 04:24:24,654 INFO L290 TraceCheckUtils]: 41: Hoare triple {71353#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {71353#false} is VALID [2022-02-21 04:24:24,654 INFO L290 TraceCheckUtils]: 42: Hoare triple {71353#false} assume !(0 != activate_threads_~tmp___2~0#1); {71353#false} is VALID [2022-02-21 04:24:24,655 INFO L290 TraceCheckUtils]: 43: Hoare triple {71353#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {71353#false} is VALID [2022-02-21 04:24:24,655 INFO L290 TraceCheckUtils]: 44: Hoare triple {71353#false} assume !(1 == ~t4_pc~0); {71353#false} is VALID [2022-02-21 04:24:24,655 INFO L290 TraceCheckUtils]: 45: Hoare triple {71353#false} is_transmit4_triggered_~__retres1~4#1 := 0; {71353#false} is VALID [2022-02-21 04:24:24,655 INFO L290 TraceCheckUtils]: 46: Hoare triple {71353#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {71353#false} is VALID [2022-02-21 04:24:24,655 INFO L290 TraceCheckUtils]: 47: Hoare triple {71353#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {71353#false} is VALID [2022-02-21 04:24:24,655 INFO L290 TraceCheckUtils]: 48: Hoare triple {71353#false} assume !(0 != activate_threads_~tmp___3~0#1); {71353#false} is VALID [2022-02-21 04:24:24,655 INFO L290 TraceCheckUtils]: 49: Hoare triple {71353#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {71353#false} is VALID [2022-02-21 04:24:24,656 INFO L290 TraceCheckUtils]: 50: Hoare triple {71353#false} assume !(1 == ~M_E~0); {71353#false} is VALID [2022-02-21 04:24:24,656 INFO L290 TraceCheckUtils]: 51: Hoare triple {71353#false} assume !(1 == ~T1_E~0); {71353#false} is VALID [2022-02-21 04:24:24,656 INFO L290 TraceCheckUtils]: 52: Hoare triple {71353#false} assume !(1 == ~T2_E~0); {71353#false} is VALID [2022-02-21 04:24:24,656 INFO L290 TraceCheckUtils]: 53: Hoare triple {71353#false} assume !(1 == ~T3_E~0); {71353#false} is VALID [2022-02-21 04:24:24,656 INFO L290 TraceCheckUtils]: 54: Hoare triple {71353#false} assume !(1 == ~T4_E~0); {71353#false} is VALID [2022-02-21 04:24:24,656 INFO L290 TraceCheckUtils]: 55: Hoare triple {71353#false} assume !(1 == ~E_1~0); {71353#false} is VALID [2022-02-21 04:24:24,656 INFO L290 TraceCheckUtils]: 56: Hoare triple {71353#false} assume !(1 == ~E_2~0); {71353#false} is VALID [2022-02-21 04:24:24,657 INFO L290 TraceCheckUtils]: 57: Hoare triple {71353#false} assume 1 == ~E_3~0;~E_3~0 := 2; {71353#false} is VALID [2022-02-21 04:24:24,657 INFO L290 TraceCheckUtils]: 58: Hoare triple {71353#false} assume !(1 == ~E_4~0); {71353#false} is VALID [2022-02-21 04:24:24,657 INFO L290 TraceCheckUtils]: 59: Hoare triple {71353#false} assume { :end_inline_reset_delta_events } true; {71353#false} is VALID [2022-02-21 04:24:24,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,657 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,657 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [103710950] [2022-02-21 04:24:24,658 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [103710950] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,658 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,658 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:24,658 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255248908] [2022-02-21 04:24:24,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,659 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:24,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,659 INFO L85 PathProgramCache]: Analyzing trace with hash -838742177, now seen corresponding path program 1 times [2022-02-21 04:24:24,659 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,659 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364185067] [2022-02-21 04:24:24,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,686 INFO L290 TraceCheckUtils]: 0: Hoare triple {71356#true} assume !false; {71356#true} is VALID [2022-02-21 04:24:24,686 INFO L290 TraceCheckUtils]: 1: Hoare triple {71356#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {71356#true} is VALID [2022-02-21 04:24:24,687 INFO L290 TraceCheckUtils]: 2: Hoare triple {71356#true} assume !false; {71356#true} is VALID [2022-02-21 04:24:24,687 INFO L290 TraceCheckUtils]: 3: Hoare triple {71356#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {71356#true} is VALID [2022-02-21 04:24:24,687 INFO L290 TraceCheckUtils]: 4: Hoare triple {71356#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {71356#true} is VALID [2022-02-21 04:24:24,687 INFO L290 TraceCheckUtils]: 5: Hoare triple {71356#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {71356#true} is VALID [2022-02-21 04:24:24,687 INFO L290 TraceCheckUtils]: 6: Hoare triple {71356#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {71356#true} is VALID [2022-02-21 04:24:24,687 INFO L290 TraceCheckUtils]: 7: Hoare triple {71356#true} assume !(0 != eval_~tmp~0#1); {71356#true} is VALID [2022-02-21 04:24:24,687 INFO L290 TraceCheckUtils]: 8: Hoare triple {71356#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {71356#true} is VALID [2022-02-21 04:24:24,688 INFO L290 TraceCheckUtils]: 9: Hoare triple {71356#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {71356#true} is VALID [2022-02-21 04:24:24,688 INFO L290 TraceCheckUtils]: 10: Hoare triple {71356#true} assume !(0 == ~M_E~0); {71356#true} is VALID [2022-02-21 04:24:24,688 INFO L290 TraceCheckUtils]: 11: Hoare triple {71356#true} assume !(0 == ~T1_E~0); {71356#true} is VALID [2022-02-21 04:24:24,688 INFO L290 TraceCheckUtils]: 12: Hoare triple {71356#true} assume !(0 == ~T2_E~0); {71356#true} is VALID [2022-02-21 04:24:24,688 INFO L290 TraceCheckUtils]: 13: Hoare triple {71356#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {71356#true} is VALID [2022-02-21 04:24:24,688 INFO L290 TraceCheckUtils]: 14: Hoare triple {71356#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {71356#true} is VALID [2022-02-21 04:24:24,688 INFO L290 TraceCheckUtils]: 15: Hoare triple {71356#true} assume 0 == ~E_1~0;~E_1~0 := 1; {71356#true} is VALID [2022-02-21 04:24:24,689 INFO L290 TraceCheckUtils]: 16: Hoare triple {71356#true} assume 0 == ~E_2~0;~E_2~0 := 1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,689 INFO L290 TraceCheckUtils]: 17: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_3~0); {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,690 INFO L290 TraceCheckUtils]: 18: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,690 INFO L290 TraceCheckUtils]: 19: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,690 INFO L290 TraceCheckUtils]: 20: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~m_pc~0); {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,691 INFO L290 TraceCheckUtils]: 21: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,691 INFO L290 TraceCheckUtils]: 22: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,691 INFO L290 TraceCheckUtils]: 23: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,692 INFO L290 TraceCheckUtils]: 24: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,692 INFO L290 TraceCheckUtils]: 25: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,693 INFO L290 TraceCheckUtils]: 26: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,693 INFO L290 TraceCheckUtils]: 27: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,693 INFO L290 TraceCheckUtils]: 28: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,694 INFO L290 TraceCheckUtils]: 29: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,694 INFO L290 TraceCheckUtils]: 30: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,694 INFO L290 TraceCheckUtils]: 31: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,695 INFO L290 TraceCheckUtils]: 32: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t2_pc~0; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,695 INFO L290 TraceCheckUtils]: 33: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,695 INFO L290 TraceCheckUtils]: 34: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,696 INFO L290 TraceCheckUtils]: 35: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,696 INFO L290 TraceCheckUtils]: 36: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,696 INFO L290 TraceCheckUtils]: 37: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,697 INFO L290 TraceCheckUtils]: 38: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,697 INFO L290 TraceCheckUtils]: 39: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,698 INFO L290 TraceCheckUtils]: 40: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,698 INFO L290 TraceCheckUtils]: 41: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,698 INFO L290 TraceCheckUtils]: 42: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,711 INFO L290 TraceCheckUtils]: 43: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,712 INFO L290 TraceCheckUtils]: 44: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t4_pc~0); {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,712 INFO L290 TraceCheckUtils]: 45: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,713 INFO L290 TraceCheckUtils]: 46: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,713 INFO L290 TraceCheckUtils]: 47: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,713 INFO L290 TraceCheckUtils]: 48: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,714 INFO L290 TraceCheckUtils]: 49: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,714 INFO L290 TraceCheckUtils]: 50: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,714 INFO L290 TraceCheckUtils]: 51: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T1_E~0); {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,715 INFO L290 TraceCheckUtils]: 52: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T2_E~0); {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,715 INFO L290 TraceCheckUtils]: 53: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,715 INFO L290 TraceCheckUtils]: 54: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,716 INFO L290 TraceCheckUtils]: 55: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {71358#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:24,716 INFO L290 TraceCheckUtils]: 56: Hoare triple {71358#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {71357#false} is VALID [2022-02-21 04:24:24,716 INFO L290 TraceCheckUtils]: 57: Hoare triple {71357#false} assume !(1 == ~E_3~0); {71357#false} is VALID [2022-02-21 04:24:24,716 INFO L290 TraceCheckUtils]: 58: Hoare triple {71357#false} assume 1 == ~E_4~0;~E_4~0 := 2; {71357#false} is VALID [2022-02-21 04:24:24,716 INFO L290 TraceCheckUtils]: 59: Hoare triple {71357#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {71357#false} is VALID [2022-02-21 04:24:24,717 INFO L290 TraceCheckUtils]: 60: Hoare triple {71357#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {71357#false} is VALID [2022-02-21 04:24:24,717 INFO L290 TraceCheckUtils]: 61: Hoare triple {71357#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {71357#false} is VALID [2022-02-21 04:24:24,717 INFO L290 TraceCheckUtils]: 62: Hoare triple {71357#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {71357#false} is VALID [2022-02-21 04:24:24,717 INFO L290 TraceCheckUtils]: 63: Hoare triple {71357#false} assume !(0 == start_simulation_~tmp~3#1); {71357#false} is VALID [2022-02-21 04:24:24,717 INFO L290 TraceCheckUtils]: 64: Hoare triple {71357#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {71357#false} is VALID [2022-02-21 04:24:24,717 INFO L290 TraceCheckUtils]: 65: Hoare triple {71357#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {71357#false} is VALID [2022-02-21 04:24:24,717 INFO L290 TraceCheckUtils]: 66: Hoare triple {71357#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {71357#false} is VALID [2022-02-21 04:24:24,718 INFO L290 TraceCheckUtils]: 67: Hoare triple {71357#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {71357#false} is VALID [2022-02-21 04:24:24,718 INFO L290 TraceCheckUtils]: 68: Hoare triple {71357#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {71357#false} is VALID [2022-02-21 04:24:24,718 INFO L290 TraceCheckUtils]: 69: Hoare triple {71357#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {71357#false} is VALID [2022-02-21 04:24:24,718 INFO L290 TraceCheckUtils]: 70: Hoare triple {71357#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {71357#false} is VALID [2022-02-21 04:24:24,718 INFO L290 TraceCheckUtils]: 71: Hoare triple {71357#false} assume !(0 != start_simulation_~tmp___0~1#1); {71357#false} is VALID [2022-02-21 04:24:24,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,719 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,719 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364185067] [2022-02-21 04:24:24,719 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364185067] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,719 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,719 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:24,719 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1086004372] [2022-02-21 04:24:24,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,720 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:24,720 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:24,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:24,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:24,721 INFO L87 Difference]: Start difference. First operand 2614 states and 3665 transitions. cyclomatic complexity: 1053 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:25,796 INFO L93 Difference]: Finished difference Result 4037 states and 5667 transitions. [2022-02-21 04:24:25,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:25,796 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,833 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:25,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4037 states and 5667 transitions. [2022-02-21 04:24:26,210 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3956 [2022-02-21 04:24:26,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4037 states to 4037 states and 5667 transitions. [2022-02-21 04:24:26,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4037 [2022-02-21 04:24:26,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4037 [2022-02-21 04:24:26,609 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4037 states and 5667 transitions. [2022-02-21 04:24:26,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:26,611 INFO L681 BuchiCegarLoop]: Abstraction has 4037 states and 5667 transitions. [2022-02-21 04:24:26,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4037 states and 5667 transitions. [2022-02-21 04:24:26,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4037 to 2201. [2022-02-21 04:24:26,658 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:26,660 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4037 states and 5667 transitions. Second operand has 2201 states, 2201 states have (on average 1.39709223080418) internal successors, (3075), 2200 states have internal predecessors, (3075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,662 INFO L74 IsIncluded]: Start isIncluded. First operand 4037 states and 5667 transitions. Second operand has 2201 states, 2201 states have (on average 1.39709223080418) internal successors, (3075), 2200 states have internal predecessors, (3075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,663 INFO L87 Difference]: Start difference. First operand 4037 states and 5667 transitions. Second operand has 2201 states, 2201 states have (on average 1.39709223080418) internal successors, (3075), 2200 states have internal predecessors, (3075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:27,018 INFO L93 Difference]: Finished difference Result 4037 states and 5667 transitions. [2022-02-21 04:24:27,018 INFO L276 IsEmpty]: Start isEmpty. Operand 4037 states and 5667 transitions. [2022-02-21 04:24:27,022 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:27,022 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:27,024 INFO L74 IsIncluded]: Start isIncluded. First operand has 2201 states, 2201 states have (on average 1.39709223080418) internal successors, (3075), 2200 states have internal predecessors, (3075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4037 states and 5667 transitions. [2022-02-21 04:24:27,025 INFO L87 Difference]: Start difference. First operand has 2201 states, 2201 states have (on average 1.39709223080418) internal successors, (3075), 2200 states have internal predecessors, (3075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4037 states and 5667 transitions. [2022-02-21 04:24:27,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:27,388 INFO L93 Difference]: Finished difference Result 4037 states and 5667 transitions. [2022-02-21 04:24:27,388 INFO L276 IsEmpty]: Start isEmpty. Operand 4037 states and 5667 transitions. [2022-02-21 04:24:27,392 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:27,392 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:27,392 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:27,392 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:27,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2201 states, 2201 states have (on average 1.39709223080418) internal successors, (3075), 2200 states have internal predecessors, (3075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2201 states to 2201 states and 3075 transitions. [2022-02-21 04:24:27,501 INFO L704 BuchiCegarLoop]: Abstraction has 2201 states and 3075 transitions. [2022-02-21 04:24:27,501 INFO L587 BuchiCegarLoop]: Abstraction has 2201 states and 3075 transitions. [2022-02-21 04:24:27,501 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:24:27,501 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2201 states and 3075 transitions. [2022-02-21 04:24:27,505 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2132 [2022-02-21 04:24:27,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:27,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:27,507 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:27,507 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:27,507 INFO L791 eck$LassoCheckResult]: Stem: 75825#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 75774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 75398#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75399#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75522#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 75634#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75482#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75483#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75495#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75496#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75539#L502 assume !(0 == ~M_E~0); 75540#L502-2 assume !(0 == ~T1_E~0); 75474#L507-1 assume !(0 == ~T2_E~0); 75475#L512-1 assume !(0 == ~T3_E~0); 75636#L517-1 assume !(0 == ~T4_E~0); 75453#L522-1 assume !(0 == ~E_1~0); 75454#L527-1 assume !(0 == ~E_2~0); 75655#L532-1 assume !(0 == ~E_3~0); 75764#L537-1 assume !(0 == ~E_4~0); 75787#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75754#L238 assume !(1 == ~m_pc~0); 75755#L238-2 is_master_triggered_~__retres1~0#1 := 0; 75411#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75412#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 75733#L615 assume !(0 != activate_threads_~tmp~1#1); 75432#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75433#L257 assume !(1 == ~t1_pc~0); 75547#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75548#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75583#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 75405#L623 assume !(0 != activate_threads_~tmp___0~0#1); 75406#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75400#L276 assume !(1 == ~t2_pc~0); 75401#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75668#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75497#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 75498#L631 assume !(0 != activate_threads_~tmp___1~0#1); 75804#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75732#L295 assume !(1 == ~t3_pc~0); 75514#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75515#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75711#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75765#L639 assume !(0 != activate_threads_~tmp___2~0#1); 75758#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75759#L314 assume !(1 == ~t4_pc~0); 75552#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75551#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75760#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75703#L647 assume !(0 != activate_threads_~tmp___3~0#1); 75648#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75649#L555 assume !(1 == ~M_E~0); 75565#L555-2 assume !(1 == ~T1_E~0); 75566#L560-1 assume !(1 == ~T2_E~0); 75455#L565-1 assume !(1 == ~T3_E~0); 75456#L570-1 assume !(1 == ~T4_E~0); 75525#L575-1 assume !(1 == ~E_1~0); 75526#L580-1 assume !(1 == ~E_2~0); 75704#L585-1 assume !(1 == ~E_3~0); 75527#L590-1 assume !(1 == ~E_4~0); 75516#L595-1 assume { :end_inline_reset_delta_events } true; 75517#L776-2 [2022-02-21 04:24:27,507 INFO L793 eck$LassoCheckResult]: Loop: 75517#L776-2 assume !false; 77244#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77242#L477 assume !false; 77241#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 75718#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 75417#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 75418#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 75459#L416 assume !(0 != eval_~tmp~0#1); 75461#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75768#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75683#L502-3 assume !(0 == ~M_E~0); 75684#L502-5 assume !(0 == ~T1_E~0); 75720#L507-3 assume !(0 == ~T2_E~0); 75627#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 75628#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75613#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 75614#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 75705#L532-3 assume !(0 == ~E_3~0); 75794#L537-3 assume !(0 == ~E_4~0); 77542#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75696#L238-15 assume !(1 == ~m_pc~0); 75697#L238-17 is_master_triggered_~__retres1~0#1 := 0; 75743#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75744#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 75545#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75546#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75819#L257-15 assume !(1 == ~t1_pc~0); 77340#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 77339#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77338#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 77336#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77335#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77334#L276-15 assume !(1 == ~t2_pc~0); 77331#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 77329#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77327#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77325#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 77322#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77320#L295-15 assume !(1 == ~t3_pc~0); 76901#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 77315#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77313#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77311#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77308#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77306#L314-15 assume 1 == ~t4_pc~0; 77303#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77302#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77300#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77298#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77296#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77294#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 77292#L555-5 assume !(1 == ~T1_E~0); 77289#L560-3 assume !(1 == ~T2_E~0); 77287#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77285#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77283#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77281#L580-3 assume !(1 == ~E_2~0); 77279#L585-3 assume !(1 == ~E_3~0); 77277#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77275#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 77268#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 77264#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 77262#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 77261#L795 assume !(0 == start_simulation_~tmp~3#1); 77259#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 77256#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 77253#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 77252#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 77250#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77248#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77246#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 77245#L808 assume !(0 != start_simulation_~tmp___0~1#1); 75517#L776-2 [2022-02-21 04:24:27,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:27,508 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 1 times [2022-02-21 04:24:27,508 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:27,508 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198344856] [2022-02-21 04:24:27,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:27,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:27,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:27,516 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:27,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:27,546 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:27,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:27,546 INFO L85 PathProgramCache]: Analyzing trace with hash -524678755, now seen corresponding path program 1 times [2022-02-21 04:24:27,547 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:27,547 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345204077] [2022-02-21 04:24:27,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:27,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:27,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:27,566 INFO L290 TraceCheckUtils]: 0: Hoare triple {85678#true} assume !false; {85678#true} is VALID [2022-02-21 04:24:27,566 INFO L290 TraceCheckUtils]: 1: Hoare triple {85678#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {85678#true} is VALID [2022-02-21 04:24:27,566 INFO L290 TraceCheckUtils]: 2: Hoare triple {85678#true} assume !false; {85678#true} is VALID [2022-02-21 04:24:27,566 INFO L290 TraceCheckUtils]: 3: Hoare triple {85678#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {85678#true} is VALID [2022-02-21 04:24:27,566 INFO L290 TraceCheckUtils]: 4: Hoare triple {85678#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {85678#true} is VALID [2022-02-21 04:24:27,567 INFO L290 TraceCheckUtils]: 5: Hoare triple {85678#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {85678#true} is VALID [2022-02-21 04:24:27,567 INFO L290 TraceCheckUtils]: 6: Hoare triple {85678#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {85678#true} is VALID [2022-02-21 04:24:27,567 INFO L290 TraceCheckUtils]: 7: Hoare triple {85678#true} assume !(0 != eval_~tmp~0#1); {85678#true} is VALID [2022-02-21 04:24:27,567 INFO L290 TraceCheckUtils]: 8: Hoare triple {85678#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {85678#true} is VALID [2022-02-21 04:24:27,567 INFO L290 TraceCheckUtils]: 9: Hoare triple {85678#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {85678#true} is VALID [2022-02-21 04:24:27,567 INFO L290 TraceCheckUtils]: 10: Hoare triple {85678#true} assume !(0 == ~M_E~0); {85678#true} is VALID [2022-02-21 04:24:27,567 INFO L290 TraceCheckUtils]: 11: Hoare triple {85678#true} assume !(0 == ~T1_E~0); {85678#true} is VALID [2022-02-21 04:24:27,568 INFO L290 TraceCheckUtils]: 12: Hoare triple {85678#true} assume !(0 == ~T2_E~0); {85678#true} is VALID [2022-02-21 04:24:27,568 INFO L290 TraceCheckUtils]: 13: Hoare triple {85678#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {85678#true} is VALID [2022-02-21 04:24:27,568 INFO L290 TraceCheckUtils]: 14: Hoare triple {85678#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {85678#true} is VALID [2022-02-21 04:24:27,568 INFO L290 TraceCheckUtils]: 15: Hoare triple {85678#true} assume 0 == ~E_1~0;~E_1~0 := 1; {85678#true} is VALID [2022-02-21 04:24:27,568 INFO L290 TraceCheckUtils]: 16: Hoare triple {85678#true} assume 0 == ~E_2~0;~E_2~0 := 1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,569 INFO L290 TraceCheckUtils]: 17: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_3~0); {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,569 INFO L290 TraceCheckUtils]: 18: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume !(0 == ~E_4~0); {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,569 INFO L290 TraceCheckUtils]: 19: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,570 INFO L290 TraceCheckUtils]: 20: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~m_pc~0); {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,570 INFO L290 TraceCheckUtils]: 21: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,570 INFO L290 TraceCheckUtils]: 22: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,571 INFO L290 TraceCheckUtils]: 23: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,571 INFO L290 TraceCheckUtils]: 24: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,571 INFO L290 TraceCheckUtils]: 25: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,572 INFO L290 TraceCheckUtils]: 26: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t1_pc~0); {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,572 INFO L290 TraceCheckUtils]: 27: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,572 INFO L290 TraceCheckUtils]: 28: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,573 INFO L290 TraceCheckUtils]: 29: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,573 INFO L290 TraceCheckUtils]: 30: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,573 INFO L290 TraceCheckUtils]: 31: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,574 INFO L290 TraceCheckUtils]: 32: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t2_pc~0); {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,574 INFO L290 TraceCheckUtils]: 33: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,574 INFO L290 TraceCheckUtils]: 34: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,575 INFO L290 TraceCheckUtils]: 35: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,575 INFO L290 TraceCheckUtils]: 36: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,575 INFO L290 TraceCheckUtils]: 37: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,576 INFO L290 TraceCheckUtils]: 38: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~t3_pc~0); {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,576 INFO L290 TraceCheckUtils]: 39: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,576 INFO L290 TraceCheckUtils]: 40: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,577 INFO L290 TraceCheckUtils]: 41: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,577 INFO L290 TraceCheckUtils]: 42: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,577 INFO L290 TraceCheckUtils]: 43: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,578 INFO L290 TraceCheckUtils]: 44: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~t4_pc~0; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,578 INFO L290 TraceCheckUtils]: 45: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,578 INFO L290 TraceCheckUtils]: 46: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,579 INFO L290 TraceCheckUtils]: 47: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,579 INFO L290 TraceCheckUtils]: 48: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,579 INFO L290 TraceCheckUtils]: 49: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,580 INFO L290 TraceCheckUtils]: 50: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,580 INFO L290 TraceCheckUtils]: 51: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T1_E~0); {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,580 INFO L290 TraceCheckUtils]: 52: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~T2_E~0); {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,581 INFO L290 TraceCheckUtils]: 53: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,581 INFO L290 TraceCheckUtils]: 54: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,581 INFO L290 TraceCheckUtils]: 55: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {85680#(= (+ (- 1) ~E_2~0) 0)} is VALID [2022-02-21 04:24:27,582 INFO L290 TraceCheckUtils]: 56: Hoare triple {85680#(= (+ (- 1) ~E_2~0) 0)} assume !(1 == ~E_2~0); {85679#false} is VALID [2022-02-21 04:24:27,582 INFO L290 TraceCheckUtils]: 57: Hoare triple {85679#false} assume !(1 == ~E_3~0); {85679#false} is VALID [2022-02-21 04:24:27,582 INFO L290 TraceCheckUtils]: 58: Hoare triple {85679#false} assume 1 == ~E_4~0;~E_4~0 := 2; {85679#false} is VALID [2022-02-21 04:24:27,582 INFO L290 TraceCheckUtils]: 59: Hoare triple {85679#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {85679#false} is VALID [2022-02-21 04:24:27,582 INFO L290 TraceCheckUtils]: 60: Hoare triple {85679#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {85679#false} is VALID [2022-02-21 04:24:27,582 INFO L290 TraceCheckUtils]: 61: Hoare triple {85679#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {85679#false} is VALID [2022-02-21 04:24:27,583 INFO L290 TraceCheckUtils]: 62: Hoare triple {85679#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {85679#false} is VALID [2022-02-21 04:24:27,583 INFO L290 TraceCheckUtils]: 63: Hoare triple {85679#false} assume !(0 == start_simulation_~tmp~3#1); {85679#false} is VALID [2022-02-21 04:24:27,583 INFO L290 TraceCheckUtils]: 64: Hoare triple {85679#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {85679#false} is VALID [2022-02-21 04:24:27,583 INFO L290 TraceCheckUtils]: 65: Hoare triple {85679#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {85679#false} is VALID [2022-02-21 04:24:27,583 INFO L290 TraceCheckUtils]: 66: Hoare triple {85679#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {85679#false} is VALID [2022-02-21 04:24:27,583 INFO L290 TraceCheckUtils]: 67: Hoare triple {85679#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {85679#false} is VALID [2022-02-21 04:24:27,584 INFO L290 TraceCheckUtils]: 68: Hoare triple {85679#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {85679#false} is VALID [2022-02-21 04:24:27,584 INFO L290 TraceCheckUtils]: 69: Hoare triple {85679#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {85679#false} is VALID [2022-02-21 04:24:27,584 INFO L290 TraceCheckUtils]: 70: Hoare triple {85679#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {85679#false} is VALID [2022-02-21 04:24:27,584 INFO L290 TraceCheckUtils]: 71: Hoare triple {85679#false} assume !(0 != start_simulation_~tmp___0~1#1); {85679#false} is VALID [2022-02-21 04:24:27,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:27,584 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:27,585 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345204077] [2022-02-21 04:24:27,585 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345204077] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:27,585 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:27,585 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:27,585 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2016611037] [2022-02-21 04:24:27,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:27,586 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:27,586 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:27,586 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:27,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:27,587 INFO L87 Difference]: Start difference. First operand 2201 states and 3075 transitions. cyclomatic complexity: 876 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,404 INFO L93 Difference]: Finished difference Result 3747 states and 5191 transitions. [2022-02-21 04:24:28,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:28,404 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,449 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 72 edges. 72 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:28,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3747 states and 5191 transitions. [2022-02-21 04:24:28,759 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3632 [2022-02-21 04:24:29,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3747 states to 3747 states and 5191 transitions. [2022-02-21 04:24:29,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3747 [2022-02-21 04:24:29,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3747 [2022-02-21 04:24:29,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3747 states and 5191 transitions. [2022-02-21 04:24:29,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:29,064 INFO L681 BuchiCegarLoop]: Abstraction has 3747 states and 5191 transitions. [2022-02-21 04:24:29,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3747 states and 5191 transitions. [2022-02-21 04:24:29,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3747 to 3743. [2022-02-21 04:24:29,101 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:29,105 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3747 states and 5191 transitions. Second operand has 3743 states, 3743 states have (on average 1.385786802030457) internal successors, (5187), 3742 states have internal predecessors, (5187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,109 INFO L74 IsIncluded]: Start isIncluded. First operand 3747 states and 5191 transitions. Second operand has 3743 states, 3743 states have (on average 1.385786802030457) internal successors, (5187), 3742 states have internal predecessors, (5187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,113 INFO L87 Difference]: Start difference. First operand 3747 states and 5191 transitions. Second operand has 3743 states, 3743 states have (on average 1.385786802030457) internal successors, (5187), 3742 states have internal predecessors, (5187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:29,423 INFO L93 Difference]: Finished difference Result 3747 states and 5191 transitions. [2022-02-21 04:24:29,423 INFO L276 IsEmpty]: Start isEmpty. Operand 3747 states and 5191 transitions. [2022-02-21 04:24:29,426 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:29,426 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:29,430 INFO L74 IsIncluded]: Start isIncluded. First operand has 3743 states, 3743 states have (on average 1.385786802030457) internal successors, (5187), 3742 states have internal predecessors, (5187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3747 states and 5191 transitions. [2022-02-21 04:24:29,432 INFO L87 Difference]: Start difference. First operand has 3743 states, 3743 states have (on average 1.385786802030457) internal successors, (5187), 3742 states have internal predecessors, (5187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3747 states and 5191 transitions. [2022-02-21 04:24:29,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:29,717 INFO L93 Difference]: Finished difference Result 3747 states and 5191 transitions. [2022-02-21 04:24:29,717 INFO L276 IsEmpty]: Start isEmpty. Operand 3747 states and 5191 transitions. [2022-02-21 04:24:29,721 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:29,721 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:29,721 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:29,721 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:29,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3743 states, 3743 states have (on average 1.385786802030457) internal successors, (5187), 3742 states have internal predecessors, (5187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3743 states to 3743 states and 5187 transitions. [2022-02-21 04:24:30,038 INFO L704 BuchiCegarLoop]: Abstraction has 3743 states and 5187 transitions. [2022-02-21 04:24:30,038 INFO L587 BuchiCegarLoop]: Abstraction has 3743 states and 5187 transitions. [2022-02-21 04:24:30,038 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:24:30,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3743 states and 5187 transitions. [2022-02-21 04:24:30,044 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3628 [2022-02-21 04:24:30,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:30,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:30,045 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:30,046 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:30,046 INFO L791 eck$LassoCheckResult]: Stem: 89887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 89803#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 89428#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89429#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89546#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 89660#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89511#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89512#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89524#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89525#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89567#L502 assume !(0 == ~M_E~0); 89568#L502-2 assume !(0 == ~T1_E~0); 89500#L507-1 assume !(0 == ~T2_E~0); 89501#L512-1 assume !(0 == ~T3_E~0); 89663#L517-1 assume !(0 == ~T4_E~0); 89473#L522-1 assume !(0 == ~E_1~0); 89474#L527-1 assume 0 == ~E_2~0;~E_2~0 := 1; 89681#L532-1 assume !(0 == ~E_3~0); 89864#L537-1 assume !(0 == ~E_4~0); 89865#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89924#L238 assume !(1 == ~m_pc~0); 89870#L238-2 is_master_triggered_~__retres1~0#1 := 0; 89439#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89440#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 89919#L615 assume !(0 != activate_threads_~tmp~1#1); 89460#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89461#L257 assume !(1 == ~t1_pc~0); 89575#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 89576#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89612#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 89433#L623 assume !(0 != activate_threads_~tmp___0~0#1); 89434#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89430#L276 assume !(1 == ~t2_pc~0); 89431#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 89692#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89526#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 89527#L631 assume !(0 != activate_threads_~tmp___1~0#1); 89863#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89757#L295 assume !(1 == ~t3_pc~0); 89542#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 89543#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89740#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 89920#L639 assume !(0 != activate_threads_~tmp___2~0#1); 89918#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89879#L314 assume !(1 == ~t4_pc~0); 89880#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89831#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89789#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 89790#L647 assume !(0 != activate_threads_~tmp___3~0#1); 89675#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89676#L555 assume !(1 == ~M_E~0); 89594#L555-2 assume !(1 == ~T1_E~0); 89595#L560-1 assume !(1 == ~T2_E~0); 89475#L565-1 assume !(1 == ~T3_E~0); 89476#L570-1 assume !(1 == ~T4_E~0); 89553#L575-1 assume !(1 == ~E_1~0); 89554#L580-1 assume 1 == ~E_2~0;~E_2~0 := 2; 89731#L585-1 assume !(1 == ~E_3~0); 89555#L590-1 assume !(1 == ~E_4~0); 89544#L595-1 assume { :end_inline_reset_delta_events } true; 89545#L776-2 [2022-02-21 04:24:30,046 INFO L793 eck$LassoCheckResult]: Loop: 89545#L776-2 assume !false; 89515#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89516#L477 assume !false; 89604#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 89605#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 89447#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 89448#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 89488#L416 assume !(0 != eval_~tmp~0#1); 89490#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 93158#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 93157#L502-3 assume !(0 == ~M_E~0); 89745#L502-5 assume !(0 == ~T1_E~0); 89746#L507-3 assume !(0 == ~T2_E~0); 89655#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89656#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 93062#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 93060#L527-3 assume !(0 == ~E_2~0); 93061#L532-3 assume !(0 == ~E_3~0); 93119#L537-3 assume !(0 == ~E_4~0); 93118#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93117#L238-15 assume !(1 == ~m_pc~0); 93116#L238-17 is_master_triggered_~__retres1~0#1 := 0; 93115#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93113#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 93111#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 93109#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93107#L257-15 assume !(1 == ~t1_pc~0); 92999#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 93104#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93103#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 93102#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 93101#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93100#L276-15 assume 1 == ~t2_pc~0; 93097#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 89637#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 93099#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 93091#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 89721#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89540#L295-15 assume !(1 == ~t3_pc~0); 89541#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 89815#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89816#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 89861#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89797#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89798#L314-15 assume 1 == ~t4_pc~0; 89697#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 89698#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89634#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 89635#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89783#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89720#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 89443#L555-5 assume !(1 == ~T1_E~0); 89444#L560-3 assume !(1 == ~T2_E~0); 89609#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89765#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89722#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 89437#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 89438#L585-3 assume !(1 == ~E_3~0); 89592#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89593#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 89673#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 89520#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 89702#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 89754#L795 assume !(0 == start_simulation_~tmp~3#1); 89756#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 89779#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 89483#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 89622#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 89623#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 89600#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89601#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 89674#L808 assume !(0 != start_simulation_~tmp___0~1#1); 89545#L776-2 [2022-02-21 04:24:30,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:30,047 INFO L85 PathProgramCache]: Analyzing trace with hash -1231104977, now seen corresponding path program 1 times [2022-02-21 04:24:30,047 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:30,047 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001673076] [2022-02-21 04:24:30,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:30,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:30,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:30,074 INFO L290 TraceCheckUtils]: 0: Hoare triple {100668#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,074 INFO L290 TraceCheckUtils]: 1: Hoare triple {100670#(<= 2 ~E_2~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,074 INFO L290 TraceCheckUtils]: 2: Hoare triple {100670#(<= 2 ~E_2~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,075 INFO L290 TraceCheckUtils]: 3: Hoare triple {100670#(<= 2 ~E_2~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,075 INFO L290 TraceCheckUtils]: 4: Hoare triple {100670#(<= 2 ~E_2~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,075 INFO L290 TraceCheckUtils]: 5: Hoare triple {100670#(<= 2 ~E_2~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,076 INFO L290 TraceCheckUtils]: 6: Hoare triple {100670#(<= 2 ~E_2~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,076 INFO L290 TraceCheckUtils]: 7: Hoare triple {100670#(<= 2 ~E_2~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,076 INFO L290 TraceCheckUtils]: 8: Hoare triple {100670#(<= 2 ~E_2~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,077 INFO L290 TraceCheckUtils]: 9: Hoare triple {100670#(<= 2 ~E_2~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,077 INFO L290 TraceCheckUtils]: 10: Hoare triple {100670#(<= 2 ~E_2~0)} assume !(0 == ~M_E~0); {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,077 INFO L290 TraceCheckUtils]: 11: Hoare triple {100670#(<= 2 ~E_2~0)} assume !(0 == ~T1_E~0); {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,078 INFO L290 TraceCheckUtils]: 12: Hoare triple {100670#(<= 2 ~E_2~0)} assume !(0 == ~T2_E~0); {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,078 INFO L290 TraceCheckUtils]: 13: Hoare triple {100670#(<= 2 ~E_2~0)} assume !(0 == ~T3_E~0); {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,078 INFO L290 TraceCheckUtils]: 14: Hoare triple {100670#(<= 2 ~E_2~0)} assume !(0 == ~T4_E~0); {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,079 INFO L290 TraceCheckUtils]: 15: Hoare triple {100670#(<= 2 ~E_2~0)} assume !(0 == ~E_1~0); {100670#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:24:30,079 INFO L290 TraceCheckUtils]: 16: Hoare triple {100670#(<= 2 ~E_2~0)} assume 0 == ~E_2~0;~E_2~0 := 1; {100669#false} is VALID [2022-02-21 04:24:30,079 INFO L290 TraceCheckUtils]: 17: Hoare triple {100669#false} assume !(0 == ~E_3~0); {100669#false} is VALID [2022-02-21 04:24:30,079 INFO L290 TraceCheckUtils]: 18: Hoare triple {100669#false} assume !(0 == ~E_4~0); {100669#false} is VALID [2022-02-21 04:24:30,080 INFO L290 TraceCheckUtils]: 19: Hoare triple {100669#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {100669#false} is VALID [2022-02-21 04:24:30,080 INFO L290 TraceCheckUtils]: 20: Hoare triple {100669#false} assume !(1 == ~m_pc~0); {100669#false} is VALID [2022-02-21 04:24:30,080 INFO L290 TraceCheckUtils]: 21: Hoare triple {100669#false} is_master_triggered_~__retres1~0#1 := 0; {100669#false} is VALID [2022-02-21 04:24:30,080 INFO L290 TraceCheckUtils]: 22: Hoare triple {100669#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {100669#false} is VALID [2022-02-21 04:24:30,080 INFO L290 TraceCheckUtils]: 23: Hoare triple {100669#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {100669#false} is VALID [2022-02-21 04:24:30,080 INFO L290 TraceCheckUtils]: 24: Hoare triple {100669#false} assume !(0 != activate_threads_~tmp~1#1); {100669#false} is VALID [2022-02-21 04:24:30,080 INFO L290 TraceCheckUtils]: 25: Hoare triple {100669#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {100669#false} is VALID [2022-02-21 04:24:30,081 INFO L290 TraceCheckUtils]: 26: Hoare triple {100669#false} assume !(1 == ~t1_pc~0); {100669#false} is VALID [2022-02-21 04:24:30,081 INFO L290 TraceCheckUtils]: 27: Hoare triple {100669#false} is_transmit1_triggered_~__retres1~1#1 := 0; {100669#false} is VALID [2022-02-21 04:24:30,081 INFO L290 TraceCheckUtils]: 28: Hoare triple {100669#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {100669#false} is VALID [2022-02-21 04:24:30,081 INFO L290 TraceCheckUtils]: 29: Hoare triple {100669#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {100669#false} is VALID [2022-02-21 04:24:30,081 INFO L290 TraceCheckUtils]: 30: Hoare triple {100669#false} assume !(0 != activate_threads_~tmp___0~0#1); {100669#false} is VALID [2022-02-21 04:24:30,081 INFO L290 TraceCheckUtils]: 31: Hoare triple {100669#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {100669#false} is VALID [2022-02-21 04:24:30,081 INFO L290 TraceCheckUtils]: 32: Hoare triple {100669#false} assume !(1 == ~t2_pc~0); {100669#false} is VALID [2022-02-21 04:24:30,082 INFO L290 TraceCheckUtils]: 33: Hoare triple {100669#false} is_transmit2_triggered_~__retres1~2#1 := 0; {100669#false} is VALID [2022-02-21 04:24:30,082 INFO L290 TraceCheckUtils]: 34: Hoare triple {100669#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {100669#false} is VALID [2022-02-21 04:24:30,082 INFO L290 TraceCheckUtils]: 35: Hoare triple {100669#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {100669#false} is VALID [2022-02-21 04:24:30,082 INFO L290 TraceCheckUtils]: 36: Hoare triple {100669#false} assume !(0 != activate_threads_~tmp___1~0#1); {100669#false} is VALID [2022-02-21 04:24:30,082 INFO L290 TraceCheckUtils]: 37: Hoare triple {100669#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {100669#false} is VALID [2022-02-21 04:24:30,082 INFO L290 TraceCheckUtils]: 38: Hoare triple {100669#false} assume !(1 == ~t3_pc~0); {100669#false} is VALID [2022-02-21 04:24:30,082 INFO L290 TraceCheckUtils]: 39: Hoare triple {100669#false} is_transmit3_triggered_~__retres1~3#1 := 0; {100669#false} is VALID [2022-02-21 04:24:30,083 INFO L290 TraceCheckUtils]: 40: Hoare triple {100669#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {100669#false} is VALID [2022-02-21 04:24:30,083 INFO L290 TraceCheckUtils]: 41: Hoare triple {100669#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {100669#false} is VALID [2022-02-21 04:24:30,094 INFO L290 TraceCheckUtils]: 42: Hoare triple {100669#false} assume !(0 != activate_threads_~tmp___2~0#1); {100669#false} is VALID [2022-02-21 04:24:30,094 INFO L290 TraceCheckUtils]: 43: Hoare triple {100669#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {100669#false} is VALID [2022-02-21 04:24:30,095 INFO L290 TraceCheckUtils]: 44: Hoare triple {100669#false} assume !(1 == ~t4_pc~0); {100669#false} is VALID [2022-02-21 04:24:30,095 INFO L290 TraceCheckUtils]: 45: Hoare triple {100669#false} is_transmit4_triggered_~__retres1~4#1 := 0; {100669#false} is VALID [2022-02-21 04:24:30,095 INFO L290 TraceCheckUtils]: 46: Hoare triple {100669#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {100669#false} is VALID [2022-02-21 04:24:30,095 INFO L290 TraceCheckUtils]: 47: Hoare triple {100669#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {100669#false} is VALID [2022-02-21 04:24:30,095 INFO L290 TraceCheckUtils]: 48: Hoare triple {100669#false} assume !(0 != activate_threads_~tmp___3~0#1); {100669#false} is VALID [2022-02-21 04:24:30,095 INFO L290 TraceCheckUtils]: 49: Hoare triple {100669#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {100669#false} is VALID [2022-02-21 04:24:30,095 INFO L290 TraceCheckUtils]: 50: Hoare triple {100669#false} assume !(1 == ~M_E~0); {100669#false} is VALID [2022-02-21 04:24:30,096 INFO L290 TraceCheckUtils]: 51: Hoare triple {100669#false} assume !(1 == ~T1_E~0); {100669#false} is VALID [2022-02-21 04:24:30,096 INFO L290 TraceCheckUtils]: 52: Hoare triple {100669#false} assume !(1 == ~T2_E~0); {100669#false} is VALID [2022-02-21 04:24:30,096 INFO L290 TraceCheckUtils]: 53: Hoare triple {100669#false} assume !(1 == ~T3_E~0); {100669#false} is VALID [2022-02-21 04:24:30,096 INFO L290 TraceCheckUtils]: 54: Hoare triple {100669#false} assume !(1 == ~T4_E~0); {100669#false} is VALID [2022-02-21 04:24:30,096 INFO L290 TraceCheckUtils]: 55: Hoare triple {100669#false} assume !(1 == ~E_1~0); {100669#false} is VALID [2022-02-21 04:24:30,096 INFO L290 TraceCheckUtils]: 56: Hoare triple {100669#false} assume 1 == ~E_2~0;~E_2~0 := 2; {100669#false} is VALID [2022-02-21 04:24:30,096 INFO L290 TraceCheckUtils]: 57: Hoare triple {100669#false} assume !(1 == ~E_3~0); {100669#false} is VALID [2022-02-21 04:24:30,097 INFO L290 TraceCheckUtils]: 58: Hoare triple {100669#false} assume !(1 == ~E_4~0); {100669#false} is VALID [2022-02-21 04:24:30,097 INFO L290 TraceCheckUtils]: 59: Hoare triple {100669#false} assume { :end_inline_reset_delta_events } true; {100669#false} is VALID [2022-02-21 04:24:30,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:30,097 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:30,098 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001673076] [2022-02-21 04:24:30,098 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2001673076] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:30,098 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:30,098 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:30,098 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923587241] [2022-02-21 04:24:30,098 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:30,100 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:30,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:30,101 INFO L85 PathProgramCache]: Analyzing trace with hash 531439936, now seen corresponding path program 1 times [2022-02-21 04:24:30,102 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:30,102 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349803383] [2022-02-21 04:24:30,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:30,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:30,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:30,139 INFO L290 TraceCheckUtils]: 0: Hoare triple {100671#true} assume !false; {100671#true} is VALID [2022-02-21 04:24:30,139 INFO L290 TraceCheckUtils]: 1: Hoare triple {100671#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {100671#true} is VALID [2022-02-21 04:24:30,139 INFO L290 TraceCheckUtils]: 2: Hoare triple {100671#true} assume !false; {100671#true} is VALID [2022-02-21 04:24:30,139 INFO L290 TraceCheckUtils]: 3: Hoare triple {100671#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {100671#true} is VALID [2022-02-21 04:24:30,140 INFO L290 TraceCheckUtils]: 4: Hoare triple {100671#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {100673#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~5#1|)} is VALID [2022-02-21 04:24:30,140 INFO L290 TraceCheckUtils]: 5: Hoare triple {100673#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~5#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {100674#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:30,141 INFO L290 TraceCheckUtils]: 6: Hoare triple {100674#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {100675#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:30,141 INFO L290 TraceCheckUtils]: 7: Hoare triple {100675#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {100672#false} is VALID [2022-02-21 04:24:30,141 INFO L290 TraceCheckUtils]: 8: Hoare triple {100672#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {100672#false} is VALID [2022-02-21 04:24:30,141 INFO L290 TraceCheckUtils]: 9: Hoare triple {100672#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {100672#false} is VALID [2022-02-21 04:24:30,141 INFO L290 TraceCheckUtils]: 10: Hoare triple {100672#false} assume !(0 == ~M_E~0); {100672#false} is VALID [2022-02-21 04:24:30,141 INFO L290 TraceCheckUtils]: 11: Hoare triple {100672#false} assume !(0 == ~T1_E~0); {100672#false} is VALID [2022-02-21 04:24:30,142 INFO L290 TraceCheckUtils]: 12: Hoare triple {100672#false} assume !(0 == ~T2_E~0); {100672#false} is VALID [2022-02-21 04:24:30,142 INFO L290 TraceCheckUtils]: 13: Hoare triple {100672#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {100672#false} is VALID [2022-02-21 04:24:30,142 INFO L290 TraceCheckUtils]: 14: Hoare triple {100672#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {100672#false} is VALID [2022-02-21 04:24:30,142 INFO L290 TraceCheckUtils]: 15: Hoare triple {100672#false} assume 0 == ~E_1~0;~E_1~0 := 1; {100672#false} is VALID [2022-02-21 04:24:30,142 INFO L290 TraceCheckUtils]: 16: Hoare triple {100672#false} assume !(0 == ~E_2~0); {100672#false} is VALID [2022-02-21 04:24:30,142 INFO L290 TraceCheckUtils]: 17: Hoare triple {100672#false} assume !(0 == ~E_3~0); {100672#false} is VALID [2022-02-21 04:24:30,142 INFO L290 TraceCheckUtils]: 18: Hoare triple {100672#false} assume !(0 == ~E_4~0); {100672#false} is VALID [2022-02-21 04:24:30,143 INFO L290 TraceCheckUtils]: 19: Hoare triple {100672#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {100672#false} is VALID [2022-02-21 04:24:30,143 INFO L290 TraceCheckUtils]: 20: Hoare triple {100672#false} assume !(1 == ~m_pc~0); {100672#false} is VALID [2022-02-21 04:24:30,143 INFO L290 TraceCheckUtils]: 21: Hoare triple {100672#false} is_master_triggered_~__retres1~0#1 := 0; {100672#false} is VALID [2022-02-21 04:24:30,143 INFO L290 TraceCheckUtils]: 22: Hoare triple {100672#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {100672#false} is VALID [2022-02-21 04:24:30,143 INFO L290 TraceCheckUtils]: 23: Hoare triple {100672#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {100672#false} is VALID [2022-02-21 04:24:30,143 INFO L290 TraceCheckUtils]: 24: Hoare triple {100672#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {100672#false} is VALID [2022-02-21 04:24:30,143 INFO L290 TraceCheckUtils]: 25: Hoare triple {100672#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {100672#false} is VALID [2022-02-21 04:24:30,144 INFO L290 TraceCheckUtils]: 26: Hoare triple {100672#false} assume !(1 == ~t1_pc~0); {100672#false} is VALID [2022-02-21 04:24:30,144 INFO L290 TraceCheckUtils]: 27: Hoare triple {100672#false} is_transmit1_triggered_~__retres1~1#1 := 0; {100672#false} is VALID [2022-02-21 04:24:30,144 INFO L290 TraceCheckUtils]: 28: Hoare triple {100672#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {100672#false} is VALID [2022-02-21 04:24:30,144 INFO L290 TraceCheckUtils]: 29: Hoare triple {100672#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {100672#false} is VALID [2022-02-21 04:24:30,144 INFO L290 TraceCheckUtils]: 30: Hoare triple {100672#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {100672#false} is VALID [2022-02-21 04:24:30,144 INFO L290 TraceCheckUtils]: 31: Hoare triple {100672#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {100672#false} is VALID [2022-02-21 04:24:30,144 INFO L290 TraceCheckUtils]: 32: Hoare triple {100672#false} assume 1 == ~t2_pc~0; {100672#false} is VALID [2022-02-21 04:24:30,145 INFO L290 TraceCheckUtils]: 33: Hoare triple {100672#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {100672#false} is VALID [2022-02-21 04:24:30,145 INFO L290 TraceCheckUtils]: 34: Hoare triple {100672#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {100672#false} is VALID [2022-02-21 04:24:30,145 INFO L290 TraceCheckUtils]: 35: Hoare triple {100672#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {100672#false} is VALID [2022-02-21 04:24:30,145 INFO L290 TraceCheckUtils]: 36: Hoare triple {100672#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {100672#false} is VALID [2022-02-21 04:24:30,145 INFO L290 TraceCheckUtils]: 37: Hoare triple {100672#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {100672#false} is VALID [2022-02-21 04:24:30,145 INFO L290 TraceCheckUtils]: 38: Hoare triple {100672#false} assume !(1 == ~t3_pc~0); {100672#false} is VALID [2022-02-21 04:24:30,145 INFO L290 TraceCheckUtils]: 39: Hoare triple {100672#false} is_transmit3_triggered_~__retres1~3#1 := 0; {100672#false} is VALID [2022-02-21 04:24:30,146 INFO L290 TraceCheckUtils]: 40: Hoare triple {100672#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {100672#false} is VALID [2022-02-21 04:24:30,146 INFO L290 TraceCheckUtils]: 41: Hoare triple {100672#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {100672#false} is VALID [2022-02-21 04:24:30,146 INFO L290 TraceCheckUtils]: 42: Hoare triple {100672#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {100672#false} is VALID [2022-02-21 04:24:30,146 INFO L290 TraceCheckUtils]: 43: Hoare triple {100672#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {100672#false} is VALID [2022-02-21 04:24:30,146 INFO L290 TraceCheckUtils]: 44: Hoare triple {100672#false} assume 1 == ~t4_pc~0; {100672#false} is VALID [2022-02-21 04:24:30,146 INFO L290 TraceCheckUtils]: 45: Hoare triple {100672#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {100672#false} is VALID [2022-02-21 04:24:30,146 INFO L290 TraceCheckUtils]: 46: Hoare triple {100672#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {100672#false} is VALID [2022-02-21 04:24:30,147 INFO L290 TraceCheckUtils]: 47: Hoare triple {100672#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {100672#false} is VALID [2022-02-21 04:24:30,147 INFO L290 TraceCheckUtils]: 48: Hoare triple {100672#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {100672#false} is VALID [2022-02-21 04:24:30,147 INFO L290 TraceCheckUtils]: 49: Hoare triple {100672#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {100672#false} is VALID [2022-02-21 04:24:30,147 INFO L290 TraceCheckUtils]: 50: Hoare triple {100672#false} assume 1 == ~M_E~0;~M_E~0 := 2; {100672#false} is VALID [2022-02-21 04:24:30,147 INFO L290 TraceCheckUtils]: 51: Hoare triple {100672#false} assume !(1 == ~T1_E~0); {100672#false} is VALID [2022-02-21 04:24:30,147 INFO L290 TraceCheckUtils]: 52: Hoare triple {100672#false} assume !(1 == ~T2_E~0); {100672#false} is VALID [2022-02-21 04:24:30,147 INFO L290 TraceCheckUtils]: 53: Hoare triple {100672#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {100672#false} is VALID [2022-02-21 04:24:30,148 INFO L290 TraceCheckUtils]: 54: Hoare triple {100672#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {100672#false} is VALID [2022-02-21 04:24:30,148 INFO L290 TraceCheckUtils]: 55: Hoare triple {100672#false} assume 1 == ~E_1~0;~E_1~0 := 2; {100672#false} is VALID [2022-02-21 04:24:30,148 INFO L290 TraceCheckUtils]: 56: Hoare triple {100672#false} assume 1 == ~E_2~0;~E_2~0 := 2; {100672#false} is VALID [2022-02-21 04:24:30,148 INFO L290 TraceCheckUtils]: 57: Hoare triple {100672#false} assume !(1 == ~E_3~0); {100672#false} is VALID [2022-02-21 04:24:30,148 INFO L290 TraceCheckUtils]: 58: Hoare triple {100672#false} assume 1 == ~E_4~0;~E_4~0 := 2; {100672#false} is VALID [2022-02-21 04:24:30,148 INFO L290 TraceCheckUtils]: 59: Hoare triple {100672#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {100672#false} is VALID [2022-02-21 04:24:30,148 INFO L290 TraceCheckUtils]: 60: Hoare triple {100672#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {100672#false} is VALID [2022-02-21 04:24:30,149 INFO L290 TraceCheckUtils]: 61: Hoare triple {100672#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {100672#false} is VALID [2022-02-21 04:24:30,149 INFO L290 TraceCheckUtils]: 62: Hoare triple {100672#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {100672#false} is VALID [2022-02-21 04:24:30,149 INFO L290 TraceCheckUtils]: 63: Hoare triple {100672#false} assume !(0 == start_simulation_~tmp~3#1); {100672#false} is VALID [2022-02-21 04:24:30,149 INFO L290 TraceCheckUtils]: 64: Hoare triple {100672#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {100672#false} is VALID [2022-02-21 04:24:30,149 INFO L290 TraceCheckUtils]: 65: Hoare triple {100672#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {100672#false} is VALID [2022-02-21 04:24:30,149 INFO L290 TraceCheckUtils]: 66: Hoare triple {100672#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {100672#false} is VALID [2022-02-21 04:24:30,149 INFO L290 TraceCheckUtils]: 67: Hoare triple {100672#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {100672#false} is VALID [2022-02-21 04:24:30,150 INFO L290 TraceCheckUtils]: 68: Hoare triple {100672#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {100672#false} is VALID [2022-02-21 04:24:30,150 INFO L290 TraceCheckUtils]: 69: Hoare triple {100672#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {100672#false} is VALID [2022-02-21 04:24:30,150 INFO L290 TraceCheckUtils]: 70: Hoare triple {100672#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {100672#false} is VALID [2022-02-21 04:24:30,150 INFO L290 TraceCheckUtils]: 71: Hoare triple {100672#false} assume !(0 != start_simulation_~tmp___0~1#1); {100672#false} is VALID [2022-02-21 04:24:30,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:30,151 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:30,151 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349803383] [2022-02-21 04:24:30,151 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [349803383] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:30,151 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:30,151 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:30,151 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1159091537] [2022-02-21 04:24:30,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:30,152 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:30,152 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:30,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:30,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:30,153 INFO L87 Difference]: Start difference. First operand 3743 states and 5187 transitions. cyclomatic complexity: 1446 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,542 INFO L93 Difference]: Finished difference Result 2102 states and 2880 transitions. [2022-02-21 04:24:30,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:30,542 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,578 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:30,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2102 states and 2880 transitions. [2022-02-21 04:24:30,671 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2036 [2022-02-21 04:24:30,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2102 states to 2102 states and 2880 transitions. [2022-02-21 04:24:30,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2102 [2022-02-21 04:24:30,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2102 [2022-02-21 04:24:30,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2102 states and 2880 transitions. [2022-02-21 04:24:30,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:30,766 INFO L681 BuchiCegarLoop]: Abstraction has 2102 states and 2880 transitions. [2022-02-21 04:24:30,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2102 states and 2880 transitions. [2022-02-21 04:24:30,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2102 to 2102. [2022-02-21 04:24:30,782 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:30,784 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2102 states and 2880 transitions. Second operand has 2102 states, 2102 states have (on average 1.3701236917221693) internal successors, (2880), 2101 states have internal predecessors, (2880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,786 INFO L74 IsIncluded]: Start isIncluded. First operand 2102 states and 2880 transitions. Second operand has 2102 states, 2102 states have (on average 1.3701236917221693) internal successors, (2880), 2101 states have internal predecessors, (2880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,787 INFO L87 Difference]: Start difference. First operand 2102 states and 2880 transitions. Second operand has 2102 states, 2102 states have (on average 1.3701236917221693) internal successors, (2880), 2101 states have internal predecessors, (2880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,879 INFO L93 Difference]: Finished difference Result 2102 states and 2880 transitions. [2022-02-21 04:24:30,879 INFO L276 IsEmpty]: Start isEmpty. Operand 2102 states and 2880 transitions. [2022-02-21 04:24:30,881 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:30,881 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:30,883 INFO L74 IsIncluded]: Start isIncluded. First operand has 2102 states, 2102 states have (on average 1.3701236917221693) internal successors, (2880), 2101 states have internal predecessors, (2880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2102 states and 2880 transitions. [2022-02-21 04:24:30,884 INFO L87 Difference]: Start difference. First operand has 2102 states, 2102 states have (on average 1.3701236917221693) internal successors, (2880), 2101 states have internal predecessors, (2880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2102 states and 2880 transitions. [2022-02-21 04:24:30,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,974 INFO L93 Difference]: Finished difference Result 2102 states and 2880 transitions. [2022-02-21 04:24:30,975 INFO L276 IsEmpty]: Start isEmpty. Operand 2102 states and 2880 transitions. [2022-02-21 04:24:30,976 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:30,976 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:30,977 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:30,977 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:30,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2102 states, 2102 states have (on average 1.3701236917221693) internal successors, (2880), 2101 states have internal predecessors, (2880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2102 states to 2102 states and 2880 transitions. [2022-02-21 04:24:31,070 INFO L704 BuchiCegarLoop]: Abstraction has 2102 states and 2880 transitions. [2022-02-21 04:24:31,070 INFO L587 BuchiCegarLoop]: Abstraction has 2102 states and 2880 transitions. [2022-02-21 04:24:31,070 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:24:31,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2102 states and 2880 transitions. [2022-02-21 04:24:31,074 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2036 [2022-02-21 04:24:31,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:31,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:31,075 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:31,075 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:31,075 INFO L791 eck$LassoCheckResult]: Stem: 103193#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 103144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 102778#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 102779#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 102899#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 103011#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102862#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102863#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102875#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102876#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102918#L502 assume !(0 == ~M_E~0); 102919#L502-2 assume !(0 == ~T1_E~0); 102851#L507-1 assume !(0 == ~T2_E~0); 102852#L512-1 assume !(0 == ~T3_E~0); 103012#L517-1 assume !(0 == ~T4_E~0); 102829#L522-1 assume !(0 == ~E_1~0); 102830#L527-1 assume !(0 == ~E_2~0); 103034#L532-1 assume !(0 == ~E_3~0); 103134#L537-1 assume !(0 == ~E_4~0); 103158#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103124#L238 assume !(1 == ~m_pc~0); 103125#L238-2 is_master_triggered_~__retres1~0#1 := 0; 102791#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102792#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 103104#L615 assume !(0 != activate_threads_~tmp~1#1); 102810#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102811#L257 assume !(1 == ~t1_pc~0); 102926#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 102927#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102962#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 102785#L623 assume !(0 != activate_threads_~tmp___0~0#1); 102786#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102780#L276 assume !(1 == ~t2_pc~0); 102781#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 103043#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102877#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102878#L631 assume !(0 != activate_threads_~tmp___1~0#1); 103172#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103100#L295 assume !(1 == ~t3_pc~0); 102893#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102894#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103084#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 103135#L639 assume !(0 != activate_threads_~tmp___2~0#1); 103128#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103129#L314 assume !(1 == ~t4_pc~0); 102931#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 102930#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103130#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 103076#L647 assume !(0 != activate_threads_~tmp___3~0#1); 103027#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103028#L555 assume !(1 == ~M_E~0); 102943#L555-2 assume !(1 == ~T1_E~0); 102944#L560-1 assume !(1 == ~T2_E~0); 102831#L565-1 assume !(1 == ~T3_E~0); 102832#L570-1 assume !(1 == ~T4_E~0); 102904#L575-1 assume !(1 == ~E_1~0); 102905#L580-1 assume !(1 == ~E_2~0); 103077#L585-1 assume !(1 == ~E_3~0); 102906#L590-1 assume !(1 == ~E_4~0); 102895#L595-1 assume { :end_inline_reset_delta_events } true; 102896#L776-2 [2022-02-21 04:24:31,075 INFO L793 eck$LassoCheckResult]: Loop: 102896#L776-2 assume !false; 102866#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102867#L477 assume !false; 102953#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 102954#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 102799#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 102800#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 102839#L416 assume !(0 != eval_~tmp~0#1); 102841#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103138#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103059#L502-3 assume !(0 == ~M_E~0); 103060#L502-5 assume !(0 == ~T1_E~0); 103090#L507-3 assume !(0 == ~T2_E~0); 103004#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103005#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 102990#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 102991#L527-3 assume !(0 == ~E_2~0); 103078#L532-3 assume !(0 == ~E_3~0); 103007#L537-3 assume !(0 == ~E_4~0); 103008#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103018#L238-15 assume !(1 == ~m_pc~0); 103072#L238-17 is_master_triggered_~__retres1~0#1 := 0; 103113#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103114#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 102924#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 102925#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102858#L257-15 assume !(1 == ~t1_pc~0); 102859#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 103054#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103162#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 103105#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103106#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103121#L276-15 assume !(1 == ~t2_pc~0); 102988#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 102970#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102971#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 103197#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 103069#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102891#L295-15 assume !(1 == ~t3_pc~0); 102892#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 103155#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103156#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 103184#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 103136#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103137#L314-15 assume 1 == ~t4_pc~0; 103047#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 103048#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102985#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 102986#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103123#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103067#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 102793#L555-5 assume !(1 == ~T1_E~0); 102794#L560-3 assume !(1 == ~T2_E~0); 102958#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 103108#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103070#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 102787#L580-3 assume !(1 == ~E_2~0); 102788#L585-3 assume !(1 == ~E_3~0); 102941#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 102942#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 103023#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 102871#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 103052#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 103097#L795 assume !(0 == start_simulation_~tmp~3#1); 103099#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 103127#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 103014#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 102972#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 102973#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 102951#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102952#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 103033#L808 assume !(0 != start_simulation_~tmp___0~1#1); 102896#L776-2 [2022-02-21 04:24:31,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:31,075 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 2 times [2022-02-21 04:24:31,076 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:31,076 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616835124] [2022-02-21 04:24:31,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:31,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:31,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:31,083 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:31,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:31,100 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:31,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:31,101 INFO L85 PathProgramCache]: Analyzing trace with hash -484004005, now seen corresponding path program 1 times [2022-02-21 04:24:31,101 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:31,101 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97441333] [2022-02-21 04:24:31,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:31,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:31,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:31,153 INFO L290 TraceCheckUtils]: 0: Hoare triple {109089#true} assume !false; {109089#true} is VALID [2022-02-21 04:24:31,154 INFO L290 TraceCheckUtils]: 1: Hoare triple {109089#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {109089#true} is VALID [2022-02-21 04:24:31,154 INFO L290 TraceCheckUtils]: 2: Hoare triple {109089#true} assume !false; {109089#true} is VALID [2022-02-21 04:24:31,154 INFO L290 TraceCheckUtils]: 3: Hoare triple {109089#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {109089#true} is VALID [2022-02-21 04:24:31,154 INFO L290 TraceCheckUtils]: 4: Hoare triple {109089#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {109091#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~5#1|)} is VALID [2022-02-21 04:24:31,155 INFO L290 TraceCheckUtils]: 5: Hoare triple {109091#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~5#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {109092#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:31,155 INFO L290 TraceCheckUtils]: 6: Hoare triple {109092#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {109093#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:31,155 INFO L290 TraceCheckUtils]: 7: Hoare triple {109093#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {109090#false} is VALID [2022-02-21 04:24:31,155 INFO L290 TraceCheckUtils]: 8: Hoare triple {109090#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 9: Hoare triple {109090#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 10: Hoare triple {109090#false} assume !(0 == ~M_E~0); {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 11: Hoare triple {109090#false} assume !(0 == ~T1_E~0); {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 12: Hoare triple {109090#false} assume !(0 == ~T2_E~0); {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 13: Hoare triple {109090#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 14: Hoare triple {109090#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 15: Hoare triple {109090#false} assume 0 == ~E_1~0;~E_1~0 := 1; {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 16: Hoare triple {109090#false} assume !(0 == ~E_2~0); {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 17: Hoare triple {109090#false} assume !(0 == ~E_3~0); {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 18: Hoare triple {109090#false} assume !(0 == ~E_4~0); {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 19: Hoare triple {109090#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 20: Hoare triple {109090#false} assume !(1 == ~m_pc~0); {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 21: Hoare triple {109090#false} is_master_triggered_~__retres1~0#1 := 0; {109090#false} is VALID [2022-02-21 04:24:31,156 INFO L290 TraceCheckUtils]: 22: Hoare triple {109090#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {109090#false} is VALID [2022-02-21 04:24:31,157 INFO L290 TraceCheckUtils]: 23: Hoare triple {109090#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {109090#false} is VALID [2022-02-21 04:24:31,157 INFO L290 TraceCheckUtils]: 24: Hoare triple {109090#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {109090#false} is VALID [2022-02-21 04:24:31,157 INFO L290 TraceCheckUtils]: 25: Hoare triple {109090#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {109090#false} is VALID [2022-02-21 04:24:31,157 INFO L290 TraceCheckUtils]: 26: Hoare triple {109090#false} assume !(1 == ~t1_pc~0); {109090#false} is VALID [2022-02-21 04:24:31,157 INFO L290 TraceCheckUtils]: 27: Hoare triple {109090#false} is_transmit1_triggered_~__retres1~1#1 := 0; {109090#false} is VALID [2022-02-21 04:24:31,157 INFO L290 TraceCheckUtils]: 28: Hoare triple {109090#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {109090#false} is VALID [2022-02-21 04:24:31,157 INFO L290 TraceCheckUtils]: 29: Hoare triple {109090#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {109090#false} is VALID [2022-02-21 04:24:31,157 INFO L290 TraceCheckUtils]: 30: Hoare triple {109090#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {109090#false} is VALID [2022-02-21 04:24:31,157 INFO L290 TraceCheckUtils]: 31: Hoare triple {109090#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {109090#false} is VALID [2022-02-21 04:24:31,157 INFO L290 TraceCheckUtils]: 32: Hoare triple {109090#false} assume !(1 == ~t2_pc~0); {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 33: Hoare triple {109090#false} is_transmit2_triggered_~__retres1~2#1 := 0; {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 34: Hoare triple {109090#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 35: Hoare triple {109090#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 36: Hoare triple {109090#false} assume !(0 != activate_threads_~tmp___1~0#1); {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 37: Hoare triple {109090#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 38: Hoare triple {109090#false} assume !(1 == ~t3_pc~0); {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 39: Hoare triple {109090#false} is_transmit3_triggered_~__retres1~3#1 := 0; {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 40: Hoare triple {109090#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 41: Hoare triple {109090#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 42: Hoare triple {109090#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 43: Hoare triple {109090#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 44: Hoare triple {109090#false} assume 1 == ~t4_pc~0; {109090#false} is VALID [2022-02-21 04:24:31,158 INFO L290 TraceCheckUtils]: 45: Hoare triple {109090#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {109090#false} is VALID [2022-02-21 04:24:31,159 INFO L290 TraceCheckUtils]: 46: Hoare triple {109090#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {109090#false} is VALID [2022-02-21 04:24:31,159 INFO L290 TraceCheckUtils]: 47: Hoare triple {109090#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {109090#false} is VALID [2022-02-21 04:24:31,159 INFO L290 TraceCheckUtils]: 48: Hoare triple {109090#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {109090#false} is VALID [2022-02-21 04:24:31,159 INFO L290 TraceCheckUtils]: 49: Hoare triple {109090#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {109090#false} is VALID [2022-02-21 04:24:31,159 INFO L290 TraceCheckUtils]: 50: Hoare triple {109090#false} assume 1 == ~M_E~0;~M_E~0 := 2; {109090#false} is VALID [2022-02-21 04:24:31,159 INFO L290 TraceCheckUtils]: 51: Hoare triple {109090#false} assume !(1 == ~T1_E~0); {109090#false} is VALID [2022-02-21 04:24:31,160 INFO L290 TraceCheckUtils]: 52: Hoare triple {109090#false} assume !(1 == ~T2_E~0); {109090#false} is VALID [2022-02-21 04:24:31,160 INFO L290 TraceCheckUtils]: 53: Hoare triple {109090#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {109090#false} is VALID [2022-02-21 04:24:31,160 INFO L290 TraceCheckUtils]: 54: Hoare triple {109090#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {109090#false} is VALID [2022-02-21 04:24:31,160 INFO L290 TraceCheckUtils]: 55: Hoare triple {109090#false} assume 1 == ~E_1~0;~E_1~0 := 2; {109090#false} is VALID [2022-02-21 04:24:31,160 INFO L290 TraceCheckUtils]: 56: Hoare triple {109090#false} assume !(1 == ~E_2~0); {109090#false} is VALID [2022-02-21 04:24:31,160 INFO L290 TraceCheckUtils]: 57: Hoare triple {109090#false} assume !(1 == ~E_3~0); {109090#false} is VALID [2022-02-21 04:24:31,160 INFO L290 TraceCheckUtils]: 58: Hoare triple {109090#false} assume 1 == ~E_4~0;~E_4~0 := 2; {109090#false} is VALID [2022-02-21 04:24:31,161 INFO L290 TraceCheckUtils]: 59: Hoare triple {109090#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {109090#false} is VALID [2022-02-21 04:24:31,161 INFO L290 TraceCheckUtils]: 60: Hoare triple {109090#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {109090#false} is VALID [2022-02-21 04:24:31,161 INFO L290 TraceCheckUtils]: 61: Hoare triple {109090#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {109090#false} is VALID [2022-02-21 04:24:31,161 INFO L290 TraceCheckUtils]: 62: Hoare triple {109090#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {109090#false} is VALID [2022-02-21 04:24:31,161 INFO L290 TraceCheckUtils]: 63: Hoare triple {109090#false} assume !(0 == start_simulation_~tmp~3#1); {109090#false} is VALID [2022-02-21 04:24:31,161 INFO L290 TraceCheckUtils]: 64: Hoare triple {109090#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {109090#false} is VALID [2022-02-21 04:24:31,161 INFO L290 TraceCheckUtils]: 65: Hoare triple {109090#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {109090#false} is VALID [2022-02-21 04:24:31,162 INFO L290 TraceCheckUtils]: 66: Hoare triple {109090#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {109090#false} is VALID [2022-02-21 04:24:31,162 INFO L290 TraceCheckUtils]: 67: Hoare triple {109090#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {109090#false} is VALID [2022-02-21 04:24:31,162 INFO L290 TraceCheckUtils]: 68: Hoare triple {109090#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {109090#false} is VALID [2022-02-21 04:24:31,162 INFO L290 TraceCheckUtils]: 69: Hoare triple {109090#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {109090#false} is VALID [2022-02-21 04:24:31,162 INFO L290 TraceCheckUtils]: 70: Hoare triple {109090#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {109090#false} is VALID [2022-02-21 04:24:31,162 INFO L290 TraceCheckUtils]: 71: Hoare triple {109090#false} assume !(0 != start_simulation_~tmp___0~1#1); {109090#false} is VALID [2022-02-21 04:24:31,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:31,163 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:31,163 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [97441333] [2022-02-21 04:24:31,163 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [97441333] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:31,163 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:31,163 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:31,163 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069917014] [2022-02-21 04:24:31,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:31,164 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:31,164 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:31,164 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:31,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:31,165 INFO L87 Difference]: Start difference. First operand 2102 states and 2880 transitions. cyclomatic complexity: 780 Second operand has 5 states, 5 states have (on average 14.4) internal successors, (72), 5 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:32,441 INFO L93 Difference]: Finished difference Result 3666 states and 4960 transitions. [2022-02-21 04:24:32,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-02-21 04:24:32,441 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 14.4) internal successors, (72), 5 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,498 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 72 edges. 72 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:32,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3666 states and 4960 transitions. [2022-02-21 04:24:32,809 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3596 [2022-02-21 04:24:33,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3666 states to 3666 states and 4960 transitions. [2022-02-21 04:24:33,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3666 [2022-02-21 04:24:33,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3666 [2022-02-21 04:24:33,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3666 states and 4960 transitions. [2022-02-21 04:24:33,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:33,132 INFO L681 BuchiCegarLoop]: Abstraction has 3666 states and 4960 transitions. [2022-02-21 04:24:33,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3666 states and 4960 transitions. [2022-02-21 04:24:33,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3666 to 2126. [2022-02-21 04:24:33,166 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:33,168 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3666 states and 4960 transitions. Second operand has 2126 states, 2126 states have (on average 1.3659454374412041) internal successors, (2904), 2125 states have internal predecessors, (2904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,170 INFO L74 IsIncluded]: Start isIncluded. First operand 3666 states and 4960 transitions. Second operand has 2126 states, 2126 states have (on average 1.3659454374412041) internal successors, (2904), 2125 states have internal predecessors, (2904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,171 INFO L87 Difference]: Start difference. First operand 3666 states and 4960 transitions. Second operand has 2126 states, 2126 states have (on average 1.3659454374412041) internal successors, (2904), 2125 states have internal predecessors, (2904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:33,473 INFO L93 Difference]: Finished difference Result 3666 states and 4960 transitions. [2022-02-21 04:24:33,474 INFO L276 IsEmpty]: Start isEmpty. Operand 3666 states and 4960 transitions. [2022-02-21 04:24:33,478 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:33,478 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:33,480 INFO L74 IsIncluded]: Start isIncluded. First operand has 2126 states, 2126 states have (on average 1.3659454374412041) internal successors, (2904), 2125 states have internal predecessors, (2904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3666 states and 4960 transitions. [2022-02-21 04:24:33,482 INFO L87 Difference]: Start difference. First operand has 2126 states, 2126 states have (on average 1.3659454374412041) internal successors, (2904), 2125 states have internal predecessors, (2904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3666 states and 4960 transitions. [2022-02-21 04:24:33,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:33,795 INFO L93 Difference]: Finished difference Result 3666 states and 4960 transitions. [2022-02-21 04:24:33,795 INFO L276 IsEmpty]: Start isEmpty. Operand 3666 states and 4960 transitions. [2022-02-21 04:24:33,798 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:33,799 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:33,799 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:33,799 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:33,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2126 states, 2126 states have (on average 1.3659454374412041) internal successors, (2904), 2125 states have internal predecessors, (2904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2126 states to 2126 states and 2904 transitions. [2022-02-21 04:24:33,892 INFO L704 BuchiCegarLoop]: Abstraction has 2126 states and 2904 transitions. [2022-02-21 04:24:33,892 INFO L587 BuchiCegarLoop]: Abstraction has 2126 states and 2904 transitions. [2022-02-21 04:24:33,892 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:24:33,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2126 states and 2904 transitions. [2022-02-21 04:24:33,896 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2060 [2022-02-21 04:24:33,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:33,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:33,896 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:33,897 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:33,897 INFO L791 eck$LassoCheckResult]: Stem: 113192#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 113135#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 112768#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112769#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112886#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 112999#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112851#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112852#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112864#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112865#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112907#L502 assume !(0 == ~M_E~0); 112908#L502-2 assume !(0 == ~T1_E~0); 112840#L507-1 assume !(0 == ~T2_E~0); 112841#L512-1 assume !(0 == ~T3_E~0); 113002#L517-1 assume !(0 == ~T4_E~0); 112813#L522-1 assume !(0 == ~E_1~0); 112814#L527-1 assume !(0 == ~E_2~0); 113022#L532-1 assume !(0 == ~E_3~0); 113127#L537-1 assume !(0 == ~E_4~0); 113148#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 113115#L238 assume !(1 == ~m_pc~0); 113116#L238-2 is_master_triggered_~__retres1~0#1 := 0; 112779#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112780#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 113095#L615 assume !(0 != activate_threads_~tmp~1#1); 112800#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112801#L257 assume !(1 == ~t1_pc~0); 112915#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 112916#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112950#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 112773#L623 assume !(0 != activate_threads_~tmp___0~0#1); 112774#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112770#L276 assume !(1 == ~t2_pc~0); 112771#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 113031#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112866#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 112867#L631 assume !(0 != activate_threads_~tmp___1~0#1); 113164#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 113092#L295 assume !(1 == ~t3_pc~0); 112882#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112883#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 113075#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 113128#L639 assume !(0 != activate_threads_~tmp___2~0#1); 113117#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113118#L314 assume !(1 == ~t4_pc~0); 112920#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 112919#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 113122#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 113068#L647 assume !(0 != activate_threads_~tmp___3~0#1); 113016#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 113017#L555 assume !(1 == ~M_E~0); 112932#L555-2 assume !(1 == ~T1_E~0); 112933#L560-1 assume !(1 == ~T2_E~0); 112815#L565-1 assume !(1 == ~T3_E~0); 112816#L570-1 assume !(1 == ~T4_E~0); 112893#L575-1 assume !(1 == ~E_1~0); 112894#L580-1 assume !(1 == ~E_2~0); 113069#L585-1 assume !(1 == ~E_3~0); 112895#L590-1 assume !(1 == ~E_4~0); 112884#L595-1 assume { :end_inline_reset_delta_events } true; 112885#L776-2 [2022-02-21 04:24:33,897 INFO L793 eck$LassoCheckResult]: Loop: 112885#L776-2 assume !false; 112855#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112856#L477 assume !false; 114390#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 114382#L374 assume !(0 == ~m_st~0); 114371#L378 assume !(0 == ~t1_st~0); 114367#L382 assume !(0 == ~t2_st~0); 114349#L386 assume !(0 == ~t3_st~0); 114317#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 114311#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 114306#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 114305#L416 assume !(0 != eval_~tmp~0#1); 114304#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 114303#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 114302#L502-3 assume !(0 == ~M_E~0); 114301#L502-5 assume !(0 == ~T1_E~0); 114300#L507-3 assume !(0 == ~T2_E~0); 114299#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 113205#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 112978#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 112979#L527-3 assume !(0 == ~E_2~0); 113070#L532-3 assume !(0 == ~E_3~0); 112997#L537-3 assume !(0 == ~E_4~0); 112998#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 113062#L238-15 assume !(1 == ~m_pc~0); 113063#L238-17 is_master_triggered_~__retres1~0#1 := 0; 113103#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 113104#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 112913#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 112914#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112847#L257-15 assume !(1 == ~t1_pc~0); 112848#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 114470#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 113182#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 113096#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 113097#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113109#L276-15 assume !(1 == ~t2_pc~0); 114466#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 114465#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113200#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 113197#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 113059#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112880#L295-15 assume !(1 == ~t3_pc~0); 112881#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 114720#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114719#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 114718#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 114717#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114716#L314-15 assume !(1 == ~t4_pc~0); 114715#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 114713#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114712#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 114711#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 114709#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114707#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 114705#L555-5 assume !(1 == ~T1_E~0); 114704#L560-3 assume !(1 == ~T2_E~0); 114703#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 114702#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 114701#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 114684#L580-3 assume !(1 == ~E_2~0); 114683#L585-3 assume !(1 == ~E_3~0); 112930#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 112931#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 113014#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 112860#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 113040#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 113089#L795 assume !(0 == start_simulation_~tmp~3#1); 113091#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 113121#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 113004#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 112960#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 112961#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 112938#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112939#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 113015#L808 assume !(0 != start_simulation_~tmp___0~1#1); 112885#L776-2 [2022-02-21 04:24:33,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:33,898 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 3 times [2022-02-21 04:24:33,898 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:33,898 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604892593] [2022-02-21 04:24:33,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:33,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:33,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:33,905 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:33,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:33,920 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:33,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:33,921 INFO L85 PathProgramCache]: Analyzing trace with hash 1258999150, now seen corresponding path program 1 times [2022-02-21 04:24:33,921 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:33,921 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953130876] [2022-02-21 04:24:33,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:33,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:33,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:33,999 INFO L290 TraceCheckUtils]: 0: Hoare triple {122231#true} assume !false; {122231#true} is VALID [2022-02-21 04:24:33,999 INFO L290 TraceCheckUtils]: 1: Hoare triple {122231#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {122231#true} is VALID [2022-02-21 04:24:33,999 INFO L290 TraceCheckUtils]: 2: Hoare triple {122231#true} assume !false; {122231#true} is VALID [2022-02-21 04:24:33,999 INFO L290 TraceCheckUtils]: 3: Hoare triple {122231#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {122231#true} is VALID [2022-02-21 04:24:33,999 INFO L290 TraceCheckUtils]: 4: Hoare triple {122231#true} assume !(0 == ~m_st~0); {122231#true} is VALID [2022-02-21 04:24:34,000 INFO L290 TraceCheckUtils]: 5: Hoare triple {122231#true} assume !(0 == ~t1_st~0); {122231#true} is VALID [2022-02-21 04:24:34,000 INFO L290 TraceCheckUtils]: 6: Hoare triple {122231#true} assume !(0 == ~t2_st~0); {122231#true} is VALID [2022-02-21 04:24:34,000 INFO L290 TraceCheckUtils]: 7: Hoare triple {122231#true} assume !(0 == ~t3_st~0); {122231#true} is VALID [2022-02-21 04:24:34,000 INFO L290 TraceCheckUtils]: 8: Hoare triple {122231#true} assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; {122231#true} is VALID [2022-02-21 04:24:34,000 INFO L290 TraceCheckUtils]: 9: Hoare triple {122231#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {122231#true} is VALID [2022-02-21 04:24:34,000 INFO L290 TraceCheckUtils]: 10: Hoare triple {122231#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {122231#true} is VALID [2022-02-21 04:24:34,000 INFO L290 TraceCheckUtils]: 11: Hoare triple {122231#true} assume !(0 != eval_~tmp~0#1); {122231#true} is VALID [2022-02-21 04:24:34,000 INFO L290 TraceCheckUtils]: 12: Hoare triple {122231#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {122231#true} is VALID [2022-02-21 04:24:34,000 INFO L290 TraceCheckUtils]: 13: Hoare triple {122231#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {122231#true} is VALID [2022-02-21 04:24:34,000 INFO L290 TraceCheckUtils]: 14: Hoare triple {122231#true} assume !(0 == ~M_E~0); {122231#true} is VALID [2022-02-21 04:24:34,001 INFO L290 TraceCheckUtils]: 15: Hoare triple {122231#true} assume !(0 == ~T1_E~0); {122231#true} is VALID [2022-02-21 04:24:34,001 INFO L290 TraceCheckUtils]: 16: Hoare triple {122231#true} assume !(0 == ~T2_E~0); {122231#true} is VALID [2022-02-21 04:24:34,001 INFO L290 TraceCheckUtils]: 17: Hoare triple {122231#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {122231#true} is VALID [2022-02-21 04:24:34,001 INFO L290 TraceCheckUtils]: 18: Hoare triple {122231#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {122231#true} is VALID [2022-02-21 04:24:34,001 INFO L290 TraceCheckUtils]: 19: Hoare triple {122231#true} assume 0 == ~E_1~0;~E_1~0 := 1; {122231#true} is VALID [2022-02-21 04:24:34,001 INFO L290 TraceCheckUtils]: 20: Hoare triple {122231#true} assume !(0 == ~E_2~0); {122231#true} is VALID [2022-02-21 04:24:34,001 INFO L290 TraceCheckUtils]: 21: Hoare triple {122231#true} assume !(0 == ~E_3~0); {122231#true} is VALID [2022-02-21 04:24:34,001 INFO L290 TraceCheckUtils]: 22: Hoare triple {122231#true} assume !(0 == ~E_4~0); {122231#true} is VALID [2022-02-21 04:24:34,001 INFO L290 TraceCheckUtils]: 23: Hoare triple {122231#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {122231#true} is VALID [2022-02-21 04:24:34,001 INFO L290 TraceCheckUtils]: 24: Hoare triple {122231#true} assume !(1 == ~m_pc~0); {122231#true} is VALID [2022-02-21 04:24:34,002 INFO L290 TraceCheckUtils]: 25: Hoare triple {122231#true} is_master_triggered_~__retres1~0#1 := 0; {122233#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is VALID [2022-02-21 04:24:34,003 INFO L290 TraceCheckUtils]: 26: Hoare triple {122233#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {122234#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} is VALID [2022-02-21 04:24:34,004 INFO L290 TraceCheckUtils]: 27: Hoare triple {122234#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {122235#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} is VALID [2022-02-21 04:24:34,004 INFO L290 TraceCheckUtils]: 28: Hoare triple {122235#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {122232#false} is VALID [2022-02-21 04:24:34,004 INFO L290 TraceCheckUtils]: 29: Hoare triple {122232#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {122232#false} is VALID [2022-02-21 04:24:34,004 INFO L290 TraceCheckUtils]: 30: Hoare triple {122232#false} assume !(1 == ~t1_pc~0); {122232#false} is VALID [2022-02-21 04:24:34,004 INFO L290 TraceCheckUtils]: 31: Hoare triple {122232#false} is_transmit1_triggered_~__retres1~1#1 := 0; {122232#false} is VALID [2022-02-21 04:24:34,005 INFO L290 TraceCheckUtils]: 32: Hoare triple {122232#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {122232#false} is VALID [2022-02-21 04:24:34,005 INFO L290 TraceCheckUtils]: 33: Hoare triple {122232#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {122232#false} is VALID [2022-02-21 04:24:34,005 INFO L290 TraceCheckUtils]: 34: Hoare triple {122232#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {122232#false} is VALID [2022-02-21 04:24:34,005 INFO L290 TraceCheckUtils]: 35: Hoare triple {122232#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {122232#false} is VALID [2022-02-21 04:24:34,005 INFO L290 TraceCheckUtils]: 36: Hoare triple {122232#false} assume !(1 == ~t2_pc~0); {122232#false} is VALID [2022-02-21 04:24:34,005 INFO L290 TraceCheckUtils]: 37: Hoare triple {122232#false} is_transmit2_triggered_~__retres1~2#1 := 0; {122232#false} is VALID [2022-02-21 04:24:34,005 INFO L290 TraceCheckUtils]: 38: Hoare triple {122232#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {122232#false} is VALID [2022-02-21 04:24:34,005 INFO L290 TraceCheckUtils]: 39: Hoare triple {122232#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {122232#false} is VALID [2022-02-21 04:24:34,005 INFO L290 TraceCheckUtils]: 40: Hoare triple {122232#false} assume !(0 != activate_threads_~tmp___1~0#1); {122232#false} is VALID [2022-02-21 04:24:34,005 INFO L290 TraceCheckUtils]: 41: Hoare triple {122232#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {122232#false} is VALID [2022-02-21 04:24:34,006 INFO L290 TraceCheckUtils]: 42: Hoare triple {122232#false} assume !(1 == ~t3_pc~0); {122232#false} is VALID [2022-02-21 04:24:34,006 INFO L290 TraceCheckUtils]: 43: Hoare triple {122232#false} is_transmit3_triggered_~__retres1~3#1 := 0; {122232#false} is VALID [2022-02-21 04:24:34,006 INFO L290 TraceCheckUtils]: 44: Hoare triple {122232#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {122232#false} is VALID [2022-02-21 04:24:34,006 INFO L290 TraceCheckUtils]: 45: Hoare triple {122232#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {122232#false} is VALID [2022-02-21 04:24:34,006 INFO L290 TraceCheckUtils]: 46: Hoare triple {122232#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {122232#false} is VALID [2022-02-21 04:24:34,006 INFO L290 TraceCheckUtils]: 47: Hoare triple {122232#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {122232#false} is VALID [2022-02-21 04:24:34,006 INFO L290 TraceCheckUtils]: 48: Hoare triple {122232#false} assume !(1 == ~t4_pc~0); {122232#false} is VALID [2022-02-21 04:24:34,006 INFO L290 TraceCheckUtils]: 49: Hoare triple {122232#false} is_transmit4_triggered_~__retres1~4#1 := 0; {122232#false} is VALID [2022-02-21 04:24:34,006 INFO L290 TraceCheckUtils]: 50: Hoare triple {122232#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {122232#false} is VALID [2022-02-21 04:24:34,006 INFO L290 TraceCheckUtils]: 51: Hoare triple {122232#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {122232#false} is VALID [2022-02-21 04:24:34,007 INFO L290 TraceCheckUtils]: 52: Hoare triple {122232#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {122232#false} is VALID [2022-02-21 04:24:34,007 INFO L290 TraceCheckUtils]: 53: Hoare triple {122232#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {122232#false} is VALID [2022-02-21 04:24:34,007 INFO L290 TraceCheckUtils]: 54: Hoare triple {122232#false} assume 1 == ~M_E~0;~M_E~0 := 2; {122232#false} is VALID [2022-02-21 04:24:34,007 INFO L290 TraceCheckUtils]: 55: Hoare triple {122232#false} assume !(1 == ~T1_E~0); {122232#false} is VALID [2022-02-21 04:24:34,007 INFO L290 TraceCheckUtils]: 56: Hoare triple {122232#false} assume !(1 == ~T2_E~0); {122232#false} is VALID [2022-02-21 04:24:34,007 INFO L290 TraceCheckUtils]: 57: Hoare triple {122232#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {122232#false} is VALID [2022-02-21 04:24:34,007 INFO L290 TraceCheckUtils]: 58: Hoare triple {122232#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {122232#false} is VALID [2022-02-21 04:24:34,007 INFO L290 TraceCheckUtils]: 59: Hoare triple {122232#false} assume 1 == ~E_1~0;~E_1~0 := 2; {122232#false} is VALID [2022-02-21 04:24:34,007 INFO L290 TraceCheckUtils]: 60: Hoare triple {122232#false} assume !(1 == ~E_2~0); {122232#false} is VALID [2022-02-21 04:24:34,007 INFO L290 TraceCheckUtils]: 61: Hoare triple {122232#false} assume !(1 == ~E_3~0); {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 62: Hoare triple {122232#false} assume 1 == ~E_4~0;~E_4~0 := 2; {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 63: Hoare triple {122232#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 64: Hoare triple {122232#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 65: Hoare triple {122232#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 66: Hoare triple {122232#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 67: Hoare triple {122232#false} assume !(0 == start_simulation_~tmp~3#1); {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 68: Hoare triple {122232#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 69: Hoare triple {122232#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 70: Hoare triple {122232#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 71: Hoare triple {122232#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {122232#false} is VALID [2022-02-21 04:24:34,008 INFO L290 TraceCheckUtils]: 72: Hoare triple {122232#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {122232#false} is VALID [2022-02-21 04:24:34,009 INFO L290 TraceCheckUtils]: 73: Hoare triple {122232#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {122232#false} is VALID [2022-02-21 04:24:34,009 INFO L290 TraceCheckUtils]: 74: Hoare triple {122232#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {122232#false} is VALID [2022-02-21 04:24:34,009 INFO L290 TraceCheckUtils]: 75: Hoare triple {122232#false} assume !(0 != start_simulation_~tmp___0~1#1); {122232#false} is VALID [2022-02-21 04:24:34,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:34,009 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:34,009 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953130876] [2022-02-21 04:24:34,009 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953130876] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:34,010 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:34,010 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:34,010 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051903176] [2022-02-21 04:24:34,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:34,010 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:34,010 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:34,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:34,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:34,011 INFO L87 Difference]: Start difference. First operand 2126 states and 2904 transitions. cyclomatic complexity: 780 Second operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 5 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:36,014 INFO L93 Difference]: Finished difference Result 4194 states and 5677 transitions. [2022-02-21 04:24:36,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:24:36,015 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 15.2) internal successors, (76), 5 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,068 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 76 edges. 76 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:36,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4194 states and 5677 transitions. [2022-02-21 04:24:36,610 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4128 [2022-02-21 04:24:37,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4194 states to 4194 states and 5677 transitions. [2022-02-21 04:24:37,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4194 [2022-02-21 04:24:37,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4194 [2022-02-21 04:24:37,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4194 states and 5677 transitions. [2022-02-21 04:24:37,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:37,046 INFO L681 BuchiCegarLoop]: Abstraction has 4194 states and 5677 transitions. [2022-02-21 04:24:37,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4194 states and 5677 transitions. [2022-02-21 04:24:37,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4194 to 2186. [2022-02-21 04:24:37,080 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:37,083 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4194 states and 5677 transitions. Second operand has 2186 states, 2186 states have (on average 1.348124428179323) internal successors, (2947), 2185 states have internal predecessors, (2947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,084 INFO L74 IsIncluded]: Start isIncluded. First operand 4194 states and 5677 transitions. Second operand has 2186 states, 2186 states have (on average 1.348124428179323) internal successors, (2947), 2185 states have internal predecessors, (2947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,085 INFO L87 Difference]: Start difference. First operand 4194 states and 5677 transitions. Second operand has 2186 states, 2186 states have (on average 1.348124428179323) internal successors, (2947), 2185 states have internal predecessors, (2947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:37,445 INFO L93 Difference]: Finished difference Result 4194 states and 5677 transitions. [2022-02-21 04:24:37,445 INFO L276 IsEmpty]: Start isEmpty. Operand 4194 states and 5677 transitions. [2022-02-21 04:24:37,448 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:37,448 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:37,450 INFO L74 IsIncluded]: Start isIncluded. First operand has 2186 states, 2186 states have (on average 1.348124428179323) internal successors, (2947), 2185 states have internal predecessors, (2947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4194 states and 5677 transitions. [2022-02-21 04:24:37,451 INFO L87 Difference]: Start difference. First operand has 2186 states, 2186 states have (on average 1.348124428179323) internal successors, (2947), 2185 states have internal predecessors, (2947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4194 states and 5677 transitions. [2022-02-21 04:24:37,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:37,808 INFO L93 Difference]: Finished difference Result 4194 states and 5677 transitions. [2022-02-21 04:24:37,808 INFO L276 IsEmpty]: Start isEmpty. Operand 4194 states and 5677 transitions. [2022-02-21 04:24:37,811 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:37,811 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:37,811 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:37,811 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:37,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2186 states, 2186 states have (on average 1.348124428179323) internal successors, (2947), 2185 states have internal predecessors, (2947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2186 states to 2186 states and 2947 transitions. [2022-02-21 04:24:37,908 INFO L704 BuchiCegarLoop]: Abstraction has 2186 states and 2947 transitions. [2022-02-21 04:24:37,908 INFO L587 BuchiCegarLoop]: Abstraction has 2186 states and 2947 transitions. [2022-02-21 04:24:37,908 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2022-02-21 04:24:37,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2186 states and 2947 transitions. [2022-02-21 04:24:37,911 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2120 [2022-02-21 04:24:37,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:37,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:37,912 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:37,912 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:37,913 INFO L791 eck$LassoCheckResult]: Stem: 126897#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 126823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 126435#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 126436#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 126557#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 126675#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126518#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126519#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126531#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126532#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126574#L502 assume !(0 == ~M_E~0); 126575#L502-2 assume !(0 == ~T1_E~0); 126510#L507-1 assume !(0 == ~T2_E~0); 126511#L512-1 assume !(0 == ~T3_E~0); 126678#L517-1 assume !(0 == ~T4_E~0); 126490#L522-1 assume !(0 == ~E_1~0); 126491#L527-1 assume !(0 == ~E_2~0); 126701#L532-1 assume !(0 == ~E_3~0); 126814#L537-1 assume !(0 == ~E_4~0); 126838#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126801#L238 assume !(1 == ~m_pc~0); 126802#L238-2 is_master_triggered_~__retres1~0#1 := 0; 126448#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126449#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 126774#L615 assume !(0 != activate_threads_~tmp~1#1); 126471#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126472#L257 assume !(1 == ~t1_pc~0); 126582#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 126583#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126619#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 126442#L623 assume !(0 != activate_threads_~tmp___0~0#1); 126443#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126437#L276 assume !(1 == ~t2_pc~0); 126438#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 126714#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126533#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 126534#L631 assume !(0 != activate_threads_~tmp___1~0#1); 126856#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126772#L295 assume !(1 == ~t3_pc~0); 126549#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 126550#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126755#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 126815#L639 assume !(0 != activate_threads_~tmp___2~0#1); 126806#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126807#L314 assume !(1 == ~t4_pc~0); 126587#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 126586#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126808#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 126745#L647 assume !(0 != activate_threads_~tmp___3~0#1); 126693#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126694#L555 assume !(1 == ~M_E~0); 126600#L555-2 assume !(1 == ~T1_E~0); 126601#L560-1 assume !(1 == ~T2_E~0); 126492#L565-1 assume !(1 == ~T3_E~0); 126493#L570-1 assume !(1 == ~T4_E~0); 126560#L575-1 assume !(1 == ~E_1~0); 126561#L580-1 assume !(1 == ~E_2~0); 126746#L585-1 assume !(1 == ~E_3~0); 126562#L590-1 assume !(1 == ~E_4~0); 126551#L595-1 assume { :end_inline_reset_delta_events } true; 126552#L776-2 [2022-02-21 04:24:37,913 INFO L793 eck$LassoCheckResult]: Loop: 126552#L776-2 assume !false; 127759#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 127756#L477 assume !false; 127755#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 127751#L374 assume !(0 == ~m_st~0); 127752#L378 assume !(0 == ~t1_st~0); 127754#L382 assume !(0 == ~t2_st~0); 127749#L386 assume !(0 == ~t3_st~0); 127750#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 127753#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 127347#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 127348#L416 assume !(0 != eval_~tmp~0#1); 128130#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 128129#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 128128#L502-3 assume !(0 == ~M_E~0); 128127#L502-5 assume !(0 == ~T1_E~0); 128126#L507-3 assume !(0 == ~T2_E~0); 128125#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 128124#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 128123#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 128122#L527-3 assume !(0 == ~E_2~0); 128121#L532-3 assume !(0 == ~E_3~0); 128120#L537-3 assume !(0 == ~E_4~0); 126685#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126686#L238-15 assume !(1 == ~m_pc~0); 126741#L238-17 is_master_triggered_~__retres1~0#1 := 0; 127860#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 127859#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 127858#L615-15 assume !(0 != activate_threads_~tmp~1#1); 127857#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 127856#L257-15 assume !(1 == ~t1_pc~0); 127728#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 127853#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 127851#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 127849#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 127847#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 127846#L276-15 assume !(1 == ~t2_pc~0); 127843#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 127841#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 127839#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 127837#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 127834#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127832#L295-15 assume !(1 == ~t3_pc~0); 127520#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 127829#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 127827#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 127825#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 127823#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127822#L314-15 assume 1 == ~t4_pc~0; 127819#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 127817#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 127815#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 127813#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 127811#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127808#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 127806#L555-5 assume !(1 == ~T1_E~0); 127804#L560-3 assume !(1 == ~T2_E~0); 127802#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 127800#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 127798#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 127796#L580-3 assume !(1 == ~E_2~0); 127794#L585-3 assume !(1 == ~E_3~0); 127792#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 127790#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 127786#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 127782#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 127780#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 127777#L795 assume !(0 == start_simulation_~tmp~3#1); 127775#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 127772#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 127769#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 127768#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 127767#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 127766#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 127764#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 127762#L808 assume !(0 != start_simulation_~tmp___0~1#1); 126552#L776-2 [2022-02-21 04:24:37,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:37,914 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 4 times [2022-02-21 04:24:37,914 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:37,914 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107038501] [2022-02-21 04:24:37,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:37,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:37,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:37,924 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:37,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:37,936 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:37,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:37,936 INFO L85 PathProgramCache]: Analyzing trace with hash -788367091, now seen corresponding path program 1 times [2022-02-21 04:24:37,936 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:37,937 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240212811] [2022-02-21 04:24:37,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:37,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:37,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:37,957 INFO L290 TraceCheckUtils]: 0: Hoare triple {137014#true} assume !false; {137014#true} is VALID [2022-02-21 04:24:37,957 INFO L290 TraceCheckUtils]: 1: Hoare triple {137014#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {137014#true} is VALID [2022-02-21 04:24:37,957 INFO L290 TraceCheckUtils]: 2: Hoare triple {137014#true} assume !false; {137014#true} is VALID [2022-02-21 04:24:37,957 INFO L290 TraceCheckUtils]: 3: Hoare triple {137014#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {137014#true} is VALID [2022-02-21 04:24:37,958 INFO L290 TraceCheckUtils]: 4: Hoare triple {137014#true} assume !(0 == ~m_st~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,958 INFO L290 TraceCheckUtils]: 5: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 == ~t1_st~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,958 INFO L290 TraceCheckUtils]: 6: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 == ~t2_st~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,959 INFO L290 TraceCheckUtils]: 7: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 == ~t3_st~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,959 INFO L290 TraceCheckUtils]: 8: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,959 INFO L290 TraceCheckUtils]: 9: Hoare triple {137016#(not (= ~m_st~0 0))} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,960 INFO L290 TraceCheckUtils]: 10: Hoare triple {137016#(not (= ~m_st~0 0))} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,960 INFO L290 TraceCheckUtils]: 11: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 != eval_~tmp~0#1); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,960 INFO L290 TraceCheckUtils]: 12: Hoare triple {137016#(not (= ~m_st~0 0))} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,961 INFO L290 TraceCheckUtils]: 13: Hoare triple {137016#(not (= ~m_st~0 0))} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,961 INFO L290 TraceCheckUtils]: 14: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 == ~M_E~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,961 INFO L290 TraceCheckUtils]: 15: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 == ~T1_E~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,962 INFO L290 TraceCheckUtils]: 16: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 == ~T2_E~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,962 INFO L290 TraceCheckUtils]: 17: Hoare triple {137016#(not (= ~m_st~0 0))} assume 0 == ~T3_E~0;~T3_E~0 := 1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,963 INFO L290 TraceCheckUtils]: 18: Hoare triple {137016#(not (= ~m_st~0 0))} assume 0 == ~T4_E~0;~T4_E~0 := 1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,963 INFO L290 TraceCheckUtils]: 19: Hoare triple {137016#(not (= ~m_st~0 0))} assume 0 == ~E_1~0;~E_1~0 := 1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,963 INFO L290 TraceCheckUtils]: 20: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 == ~E_2~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,964 INFO L290 TraceCheckUtils]: 21: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 == ~E_3~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,964 INFO L290 TraceCheckUtils]: 22: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 == ~E_4~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,964 INFO L290 TraceCheckUtils]: 23: Hoare triple {137016#(not (= ~m_st~0 0))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,965 INFO L290 TraceCheckUtils]: 24: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(1 == ~m_pc~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,965 INFO L290 TraceCheckUtils]: 25: Hoare triple {137016#(not (= ~m_st~0 0))} is_master_triggered_~__retres1~0#1 := 0; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,965 INFO L290 TraceCheckUtils]: 26: Hoare triple {137016#(not (= ~m_st~0 0))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,966 INFO L290 TraceCheckUtils]: 27: Hoare triple {137016#(not (= ~m_st~0 0))} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,966 INFO L290 TraceCheckUtils]: 28: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 != activate_threads_~tmp~1#1); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,966 INFO L290 TraceCheckUtils]: 29: Hoare triple {137016#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,967 INFO L290 TraceCheckUtils]: 30: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(1 == ~t1_pc~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,967 INFO L290 TraceCheckUtils]: 31: Hoare triple {137016#(not (= ~m_st~0 0))} is_transmit1_triggered_~__retres1~1#1 := 0; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,967 INFO L290 TraceCheckUtils]: 32: Hoare triple {137016#(not (= ~m_st~0 0))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,968 INFO L290 TraceCheckUtils]: 33: Hoare triple {137016#(not (= ~m_st~0 0))} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,968 INFO L290 TraceCheckUtils]: 34: Hoare triple {137016#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,968 INFO L290 TraceCheckUtils]: 35: Hoare triple {137016#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,969 INFO L290 TraceCheckUtils]: 36: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(1 == ~t2_pc~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,969 INFO L290 TraceCheckUtils]: 37: Hoare triple {137016#(not (= ~m_st~0 0))} is_transmit2_triggered_~__retres1~2#1 := 0; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,969 INFO L290 TraceCheckUtils]: 38: Hoare triple {137016#(not (= ~m_st~0 0))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,970 INFO L290 TraceCheckUtils]: 39: Hoare triple {137016#(not (= ~m_st~0 0))} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,970 INFO L290 TraceCheckUtils]: 40: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(0 != activate_threads_~tmp___1~0#1); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,972 INFO L290 TraceCheckUtils]: 41: Hoare triple {137016#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,972 INFO L290 TraceCheckUtils]: 42: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(1 == ~t3_pc~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,973 INFO L290 TraceCheckUtils]: 43: Hoare triple {137016#(not (= ~m_st~0 0))} is_transmit3_triggered_~__retres1~3#1 := 0; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,973 INFO L290 TraceCheckUtils]: 44: Hoare triple {137016#(not (= ~m_st~0 0))} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,973 INFO L290 TraceCheckUtils]: 45: Hoare triple {137016#(not (= ~m_st~0 0))} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,974 INFO L290 TraceCheckUtils]: 46: Hoare triple {137016#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,974 INFO L290 TraceCheckUtils]: 47: Hoare triple {137016#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,974 INFO L290 TraceCheckUtils]: 48: Hoare triple {137016#(not (= ~m_st~0 0))} assume 1 == ~t4_pc~0; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,975 INFO L290 TraceCheckUtils]: 49: Hoare triple {137016#(not (= ~m_st~0 0))} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,975 INFO L290 TraceCheckUtils]: 50: Hoare triple {137016#(not (= ~m_st~0 0))} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,975 INFO L290 TraceCheckUtils]: 51: Hoare triple {137016#(not (= ~m_st~0 0))} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,976 INFO L290 TraceCheckUtils]: 52: Hoare triple {137016#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,976 INFO L290 TraceCheckUtils]: 53: Hoare triple {137016#(not (= ~m_st~0 0))} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,976 INFO L290 TraceCheckUtils]: 54: Hoare triple {137016#(not (= ~m_st~0 0))} assume 1 == ~M_E~0;~M_E~0 := 2; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,977 INFO L290 TraceCheckUtils]: 55: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(1 == ~T1_E~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,977 INFO L290 TraceCheckUtils]: 56: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(1 == ~T2_E~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,977 INFO L290 TraceCheckUtils]: 57: Hoare triple {137016#(not (= ~m_st~0 0))} assume 1 == ~T3_E~0;~T3_E~0 := 2; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,978 INFO L290 TraceCheckUtils]: 58: Hoare triple {137016#(not (= ~m_st~0 0))} assume 1 == ~T4_E~0;~T4_E~0 := 2; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,978 INFO L290 TraceCheckUtils]: 59: Hoare triple {137016#(not (= ~m_st~0 0))} assume 1 == ~E_1~0;~E_1~0 := 2; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,978 INFO L290 TraceCheckUtils]: 60: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(1 == ~E_2~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,979 INFO L290 TraceCheckUtils]: 61: Hoare triple {137016#(not (= ~m_st~0 0))} assume !(1 == ~E_3~0); {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,979 INFO L290 TraceCheckUtils]: 62: Hoare triple {137016#(not (= ~m_st~0 0))} assume 1 == ~E_4~0;~E_4~0 := 2; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,979 INFO L290 TraceCheckUtils]: 63: Hoare triple {137016#(not (= ~m_st~0 0))} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {137016#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:24:37,980 INFO L290 TraceCheckUtils]: 64: Hoare triple {137016#(not (= ~m_st~0 0))} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {137015#false} is VALID [2022-02-21 04:24:37,980 INFO L290 TraceCheckUtils]: 65: Hoare triple {137015#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {137015#false} is VALID [2022-02-21 04:24:37,980 INFO L290 TraceCheckUtils]: 66: Hoare triple {137015#false} start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {137015#false} is VALID [2022-02-21 04:24:37,980 INFO L290 TraceCheckUtils]: 67: Hoare triple {137015#false} assume !(0 == start_simulation_~tmp~3#1); {137015#false} is VALID [2022-02-21 04:24:37,980 INFO L290 TraceCheckUtils]: 68: Hoare triple {137015#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {137015#false} is VALID [2022-02-21 04:24:37,981 INFO L290 TraceCheckUtils]: 69: Hoare triple {137015#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {137015#false} is VALID [2022-02-21 04:24:37,981 INFO L290 TraceCheckUtils]: 70: Hoare triple {137015#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {137015#false} is VALID [2022-02-21 04:24:37,981 INFO L290 TraceCheckUtils]: 71: Hoare triple {137015#false} stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; {137015#false} is VALID [2022-02-21 04:24:37,981 INFO L290 TraceCheckUtils]: 72: Hoare triple {137015#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {137015#false} is VALID [2022-02-21 04:24:37,981 INFO L290 TraceCheckUtils]: 73: Hoare triple {137015#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {137015#false} is VALID [2022-02-21 04:24:37,981 INFO L290 TraceCheckUtils]: 74: Hoare triple {137015#false} start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {137015#false} is VALID [2022-02-21 04:24:37,981 INFO L290 TraceCheckUtils]: 75: Hoare triple {137015#false} assume !(0 != start_simulation_~tmp___0~1#1); {137015#false} is VALID [2022-02-21 04:24:37,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:37,982 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:37,982 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240212811] [2022-02-21 04:24:37,982 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1240212811] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:37,982 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:37,982 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:37,983 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114950741] [2022-02-21 04:24:37,983 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:37,983 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:37,983 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:37,984 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:37,984 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:37,984 INFO L87 Difference]: Start difference. First operand 2186 states and 2947 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:38,608 INFO L93 Difference]: Finished difference Result 3576 states and 4749 transitions. [2022-02-21 04:24:38,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:38,609 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,673 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 76 edges. 76 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:38,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3576 states and 4749 transitions. [2022-02-21 04:24:38,959 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3508 [2022-02-21 04:24:39,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3576 states to 3576 states and 4749 transitions. [2022-02-21 04:24:39,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3576 [2022-02-21 04:24:39,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3576 [2022-02-21 04:24:39,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3576 states and 4749 transitions. [2022-02-21 04:24:39,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:39,359 INFO L681 BuchiCegarLoop]: Abstraction has 3576 states and 4749 transitions. [2022-02-21 04:24:39,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3576 states and 4749 transitions. [2022-02-21 04:24:39,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3576 to 3452. [2022-02-21 04:24:39,401 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:39,404 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3576 states and 4749 transitions. Second operand has 3452 states, 3452 states have (on average 1.3311123986095017) internal successors, (4595), 3451 states have internal predecessors, (4595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,408 INFO L74 IsIncluded]: Start isIncluded. First operand 3576 states and 4749 transitions. Second operand has 3452 states, 3452 states have (on average 1.3311123986095017) internal successors, (4595), 3451 states have internal predecessors, (4595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,411 INFO L87 Difference]: Start difference. First operand 3576 states and 4749 transitions. Second operand has 3452 states, 3452 states have (on average 1.3311123986095017) internal successors, (4595), 3451 states have internal predecessors, (4595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:39,689 INFO L93 Difference]: Finished difference Result 3576 states and 4749 transitions. [2022-02-21 04:24:39,689 INFO L276 IsEmpty]: Start isEmpty. Operand 3576 states and 4749 transitions. [2022-02-21 04:24:39,692 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:39,692 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:39,697 INFO L74 IsIncluded]: Start isIncluded. First operand has 3452 states, 3452 states have (on average 1.3311123986095017) internal successors, (4595), 3451 states have internal predecessors, (4595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3576 states and 4749 transitions. [2022-02-21 04:24:39,701 INFO L87 Difference]: Start difference. First operand has 3452 states, 3452 states have (on average 1.3311123986095017) internal successors, (4595), 3451 states have internal predecessors, (4595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3576 states and 4749 transitions. [2022-02-21 04:24:39,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:39,978 INFO L93 Difference]: Finished difference Result 3576 states and 4749 transitions. [2022-02-21 04:24:39,978 INFO L276 IsEmpty]: Start isEmpty. Operand 3576 states and 4749 transitions. [2022-02-21 04:24:39,980 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:39,980 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:39,981 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:39,981 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:39,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3452 states, 3452 states have (on average 1.3311123986095017) internal successors, (4595), 3451 states have internal predecessors, (4595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3452 states to 3452 states and 4595 transitions. [2022-02-21 04:24:40,241 INFO L704 BuchiCegarLoop]: Abstraction has 3452 states and 4595 transitions. [2022-02-21 04:24:40,241 INFO L587 BuchiCegarLoop]: Abstraction has 3452 states and 4595 transitions. [2022-02-21 04:24:40,241 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2022-02-21 04:24:40,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3452 states and 4595 transitions. [2022-02-21 04:24:40,245 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3384 [2022-02-21 04:24:40,246 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:40,246 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:40,246 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:40,246 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:40,246 INFO L791 eck$LassoCheckResult]: Stem: 141048#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 140971#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 140593#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 140594#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 140713#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 140829#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 140676#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 140677#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 140689#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 140690#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 140732#L502 assume !(0 == ~M_E~0); 140733#L502-2 assume !(0 == ~T1_E~0); 140668#L507-1 assume !(0 == ~T2_E~0); 140669#L512-1 assume !(0 == ~T3_E~0); 140831#L517-1 assume !(0 == ~T4_E~0); 140646#L522-1 assume !(0 == ~E_1~0); 140647#L527-1 assume !(0 == ~E_2~0); 140853#L532-1 assume !(0 == ~E_3~0); 140960#L537-1 assume !(0 == ~E_4~0); 140988#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 140951#L238 assume !(1 == ~m_pc~0); 140952#L238-2 is_master_triggered_~__retres1~0#1 := 0; 140606#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 140607#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 140930#L615 assume !(0 != activate_threads_~tmp~1#1); 140629#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 140630#L257 assume !(1 == ~t1_pc~0); 140740#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 140741#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 140776#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 140600#L623 assume !(0 != activate_threads_~tmp___0~0#1); 140601#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 140595#L276 assume !(1 == ~t2_pc~0); 140596#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 140866#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 140691#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 140692#L631 assume !(0 != activate_threads_~tmp___1~0#1); 141004#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 140929#L295 assume !(1 == ~t3_pc~0); 140707#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 140708#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 140911#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 140961#L639 assume !(0 != activate_threads_~tmp___2~0#1); 140954#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 140955#L314 assume !(1 == ~t4_pc~0); 140745#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 140744#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 140956#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 140901#L647 assume !(0 != activate_threads_~tmp___3~0#1); 140844#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140845#L555 assume !(1 == ~M_E~0); 140757#L555-2 assume !(1 == ~T1_E~0); 140758#L560-1 assume !(1 == ~T2_E~0); 140648#L565-1 assume !(1 == ~T3_E~0); 140649#L570-1 assume !(1 == ~T4_E~0); 140718#L575-1 assume !(1 == ~E_1~0); 140719#L580-1 assume !(1 == ~E_2~0); 140902#L585-1 assume !(1 == ~E_3~0); 140720#L590-1 assume !(1 == ~E_4~0); 140709#L595-1 assume { :end_inline_reset_delta_events } true; 140710#L776-2 assume !false; 143359#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143355#L477 [2022-02-21 04:24:40,246 INFO L793 eck$LassoCheckResult]: Loop: 143355#L477 assume !false; 143349#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 143346#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 143344#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 143342#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 143340#L416 assume 0 != eval_~tmp~0#1; 143337#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 143332#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 143330#L421 assume !(0 == ~t1_st~0); 143326#L435 assume !(0 == ~t2_st~0); 143322#L449 assume !(0 == ~t3_st~0); 143321#L463 assume !(0 == ~t4_st~0); 143355#L477 [2022-02-21 04:24:40,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:40,247 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 1 times [2022-02-21 04:24:40,247 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:40,247 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311203197] [2022-02-21 04:24:40,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:40,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:40,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:40,257 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:40,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:40,280 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:40,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:40,281 INFO L85 PathProgramCache]: Analyzing trace with hash 839567500, now seen corresponding path program 1 times [2022-02-21 04:24:40,281 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:40,281 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1868025539] [2022-02-21 04:24:40,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:40,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:40,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:40,287 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:40,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:40,290 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:40,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:40,290 INFO L85 PathProgramCache]: Analyzing trace with hash -1729123880, now seen corresponding path program 1 times [2022-02-21 04:24:40,291 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:40,291 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678342326] [2022-02-21 04:24:40,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:40,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:40,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 0: Hoare triple {151204#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {151204#true} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 1: Hoare triple {151204#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {151204#true} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 2: Hoare triple {151204#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {151204#true} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 3: Hoare triple {151204#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {151204#true} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 4: Hoare triple {151204#true} assume 1 == ~m_i~0;~m_st~0 := 0; {151204#true} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 5: Hoare triple {151204#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 6: Hoare triple {151206#(= ~t1_st~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 7: Hoare triple {151206#(= ~t1_st~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 8: Hoare triple {151206#(= ~t1_st~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 9: Hoare triple {151206#(= ~t1_st~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 10: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 == ~M_E~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 11: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 == ~T1_E~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 12: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 == ~T2_E~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 13: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 == ~T3_E~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 14: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 == ~T4_E~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 15: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 == ~E_1~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 16: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 == ~E_2~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 17: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 == ~E_3~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 18: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 == ~E_4~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 19: Hoare triple {151206#(= ~t1_st~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 20: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~m_pc~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 21: Hoare triple {151206#(= ~t1_st~0 0)} is_master_triggered_~__retres1~0#1 := 0; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 22: Hoare triple {151206#(= ~t1_st~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 23: Hoare triple {151206#(= ~t1_st~0 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 24: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp~1#1); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,331 INFO L290 TraceCheckUtils]: 25: Hoare triple {151206#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,331 INFO L290 TraceCheckUtils]: 26: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~t1_pc~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,331 INFO L290 TraceCheckUtils]: 27: Hoare triple {151206#(= ~t1_st~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 28: Hoare triple {151206#(= ~t1_st~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 29: Hoare triple {151206#(= ~t1_st~0 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 30: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,333 INFO L290 TraceCheckUtils]: 31: Hoare triple {151206#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,333 INFO L290 TraceCheckUtils]: 32: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~t2_pc~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,333 INFO L290 TraceCheckUtils]: 33: Hoare triple {151206#(= ~t1_st~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,334 INFO L290 TraceCheckUtils]: 34: Hoare triple {151206#(= ~t1_st~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,334 INFO L290 TraceCheckUtils]: 35: Hoare triple {151206#(= ~t1_st~0 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,334 INFO L290 TraceCheckUtils]: 36: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,335 INFO L290 TraceCheckUtils]: 37: Hoare triple {151206#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,335 INFO L290 TraceCheckUtils]: 38: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~t3_pc~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,335 INFO L290 TraceCheckUtils]: 39: Hoare triple {151206#(= ~t1_st~0 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,336 INFO L290 TraceCheckUtils]: 40: Hoare triple {151206#(= ~t1_st~0 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,336 INFO L290 TraceCheckUtils]: 41: Hoare triple {151206#(= ~t1_st~0 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,336 INFO L290 TraceCheckUtils]: 42: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___2~0#1); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,337 INFO L290 TraceCheckUtils]: 43: Hoare triple {151206#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,337 INFO L290 TraceCheckUtils]: 44: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~t4_pc~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,337 INFO L290 TraceCheckUtils]: 45: Hoare triple {151206#(= ~t1_st~0 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,338 INFO L290 TraceCheckUtils]: 46: Hoare triple {151206#(= ~t1_st~0 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,338 INFO L290 TraceCheckUtils]: 47: Hoare triple {151206#(= ~t1_st~0 0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,338 INFO L290 TraceCheckUtils]: 48: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___3~0#1); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,339 INFO L290 TraceCheckUtils]: 49: Hoare triple {151206#(= ~t1_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,339 INFO L290 TraceCheckUtils]: 50: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~M_E~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,339 INFO L290 TraceCheckUtils]: 51: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~T1_E~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,340 INFO L290 TraceCheckUtils]: 52: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~T2_E~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,340 INFO L290 TraceCheckUtils]: 53: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~T3_E~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,340 INFO L290 TraceCheckUtils]: 54: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~T4_E~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,341 INFO L290 TraceCheckUtils]: 55: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~E_1~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,341 INFO L290 TraceCheckUtils]: 56: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~E_2~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,341 INFO L290 TraceCheckUtils]: 57: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~E_3~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,342 INFO L290 TraceCheckUtils]: 58: Hoare triple {151206#(= ~t1_st~0 0)} assume !(1 == ~E_4~0); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,342 INFO L290 TraceCheckUtils]: 59: Hoare triple {151206#(= ~t1_st~0 0)} assume { :end_inline_reset_delta_events } true; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,342 INFO L290 TraceCheckUtils]: 60: Hoare triple {151206#(= ~t1_st~0 0)} assume !false; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,343 INFO L290 TraceCheckUtils]: 61: Hoare triple {151206#(= ~t1_st~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,343 INFO L290 TraceCheckUtils]: 62: Hoare triple {151206#(= ~t1_st~0 0)} assume !false; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,343 INFO L290 TraceCheckUtils]: 63: Hoare triple {151206#(= ~t1_st~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,344 INFO L290 TraceCheckUtils]: 64: Hoare triple {151206#(= ~t1_st~0 0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,344 INFO L290 TraceCheckUtils]: 65: Hoare triple {151206#(= ~t1_st~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,344 INFO L290 TraceCheckUtils]: 66: Hoare triple {151206#(= ~t1_st~0 0)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,345 INFO L290 TraceCheckUtils]: 67: Hoare triple {151206#(= ~t1_st~0 0)} assume 0 != eval_~tmp~0#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,345 INFO L290 TraceCheckUtils]: 68: Hoare triple {151206#(= ~t1_st~0 0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,345 INFO L290 TraceCheckUtils]: 69: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 != eval_~tmp_ndt_1~0#1); {151206#(= ~t1_st~0 0)} is VALID [2022-02-21 04:24:40,346 INFO L290 TraceCheckUtils]: 70: Hoare triple {151206#(= ~t1_st~0 0)} assume !(0 == ~t1_st~0); {151205#false} is VALID [2022-02-21 04:24:40,346 INFO L290 TraceCheckUtils]: 71: Hoare triple {151205#false} assume !(0 == ~t2_st~0); {151205#false} is VALID [2022-02-21 04:24:40,346 INFO L290 TraceCheckUtils]: 72: Hoare triple {151205#false} assume !(0 == ~t3_st~0); {151205#false} is VALID [2022-02-21 04:24:40,346 INFO L290 TraceCheckUtils]: 73: Hoare triple {151205#false} assume !(0 == ~t4_st~0); {151205#false} is VALID [2022-02-21 04:24:40,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:40,347 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:40,347 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1678342326] [2022-02-21 04:24:40,347 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1678342326] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:40,347 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:40,347 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:40,347 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1183967601] [2022-02-21 04:24:40,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:40,441 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:40,441 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:40,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:40,441 INFO L87 Difference]: Start difference. First operand 3452 states and 4595 transitions. cyclomatic complexity: 1146 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:41,954 INFO L93 Difference]: Finished difference Result 6396 states and 8409 transitions. [2022-02-21 04:24:41,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:41,954 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,005 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 74 edges. 74 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:42,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6396 states and 8409 transitions. [2022-02-21 04:24:42,838 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6266 [2022-02-21 04:24:43,716 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6396 states to 6396 states and 8409 transitions. [2022-02-21 04:24:43,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6396 [2022-02-21 04:24:43,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6396 [2022-02-21 04:24:43,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6396 states and 8409 transitions. [2022-02-21 04:24:43,721 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:43,721 INFO L681 BuchiCegarLoop]: Abstraction has 6396 states and 8409 transitions. [2022-02-21 04:24:43,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6396 states and 8409 transitions. [2022-02-21 04:24:43,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6396 to 6176. [2022-02-21 04:24:43,760 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:43,764 INFO L82 GeneralOperation]: Start isEquivalent. First operand 6396 states and 8409 transitions. Second operand has 6176 states, 6176 states have (on average 1.3175194300518134) internal successors, (8137), 6175 states have internal predecessors, (8137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:43,767 INFO L74 IsIncluded]: Start isIncluded. First operand 6396 states and 8409 transitions. Second operand has 6176 states, 6176 states have (on average 1.3175194300518134) internal successors, (8137), 6175 states have internal predecessors, (8137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:43,770 INFO L87 Difference]: Start difference. First operand 6396 states and 8409 transitions. Second operand has 6176 states, 6176 states have (on average 1.3175194300518134) internal successors, (8137), 6175 states have internal predecessors, (8137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:44,628 INFO L93 Difference]: Finished difference Result 6396 states and 8409 transitions. [2022-02-21 04:24:44,628 INFO L276 IsEmpty]: Start isEmpty. Operand 6396 states and 8409 transitions. [2022-02-21 04:24:44,633 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:44,633 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:44,638 INFO L74 IsIncluded]: Start isIncluded. First operand has 6176 states, 6176 states have (on average 1.3175194300518134) internal successors, (8137), 6175 states have internal predecessors, (8137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6396 states and 8409 transitions. [2022-02-21 04:24:44,643 INFO L87 Difference]: Start difference. First operand has 6176 states, 6176 states have (on average 1.3175194300518134) internal successors, (8137), 6175 states have internal predecessors, (8137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6396 states and 8409 transitions. [2022-02-21 04:24:45,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:45,497 INFO L93 Difference]: Finished difference Result 6396 states and 8409 transitions. [2022-02-21 04:24:45,498 INFO L276 IsEmpty]: Start isEmpty. Operand 6396 states and 8409 transitions. [2022-02-21 04:24:45,502 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:45,502 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:45,503 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:45,503 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:45,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6176 states, 6176 states have (on average 1.3175194300518134) internal successors, (8137), 6175 states have internal predecessors, (8137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6176 states to 6176 states and 8137 transitions. [2022-02-21 04:24:46,283 INFO L704 BuchiCegarLoop]: Abstraction has 6176 states and 8137 transitions. [2022-02-21 04:24:46,284 INFO L587 BuchiCegarLoop]: Abstraction has 6176 states and 8137 transitions. [2022-02-21 04:24:46,284 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2022-02-21 04:24:46,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6176 states and 8137 transitions. [2022-02-21 04:24:46,291 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2022-02-21 04:24:46,291 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:46,291 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:46,291 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:46,291 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:46,292 INFO L791 eck$LassoCheckResult]: Stem: 158062#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 157981#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 157603#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 157604#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 157720#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 157832#L341-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 157686#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157687#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 157699#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157700#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 157741#L502 assume !(0 == ~M_E~0); 157742#L502-2 assume !(0 == ~T1_E~0); 157675#L507-1 assume !(0 == ~T2_E~0); 157676#L512-1 assume !(0 == ~T3_E~0); 157835#L517-1 assume !(0 == ~T4_E~0); 157649#L522-1 assume !(0 == ~E_1~0); 157650#L527-1 assume !(0 == ~E_2~0); 157857#L532-1 assume !(0 == ~E_3~0); 157970#L537-1 assume !(0 == ~E_4~0); 158000#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157958#L238 assume !(1 == ~m_pc~0); 157959#L238-2 is_master_triggered_~__retres1~0#1 := 0; 157615#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 157616#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 157936#L615 assume !(0 != activate_threads_~tmp~1#1); 157636#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 157637#L257 assume !(1 == ~t1_pc~0); 157749#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 157750#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 157785#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 157608#L623 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 157609#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160842#L276 assume !(1 == ~t2_pc~0); 160840#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 160839#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160838#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 160837#L631 assume !(0 != activate_threads_~tmp___1~0#1); 160836#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 160835#L295 assume !(1 == ~t3_pc~0); 160834#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 160833#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160832#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 160831#L639 assume !(0 != activate_threads_~tmp___2~0#1); 160830#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 160829#L314 assume !(1 == ~t4_pc~0); 157754#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 157753#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 157964#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 157905#L647 assume !(0 != activate_threads_~tmp___3~0#1); 157849#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 157850#L555 assume !(1 == ~M_E~0); 157766#L555-2 assume !(1 == ~T1_E~0); 157767#L560-1 assume !(1 == ~T2_E~0); 160819#L565-1 assume !(1 == ~T3_E~0); 160817#L570-1 assume !(1 == ~T4_E~0); 157727#L575-1 assume !(1 == ~E_1~0); 157728#L580-1 assume !(1 == ~E_2~0); 157990#L585-1 assume !(1 == ~E_3~0); 157991#L590-1 assume !(1 == ~E_4~0); 160607#L595-1 assume { :end_inline_reset_delta_events } true; 160606#L776-2 assume !false; 160604#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 160602#L477 [2022-02-21 04:24:46,292 INFO L793 eck$LassoCheckResult]: Loop: 160602#L477 assume !false; 160601#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 160600#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 160599#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 160598#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 160597#L416 assume 0 != eval_~tmp~0#1; 160549#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 160550#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 159035#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 158859#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 158860#L435 assume !(0 == ~t2_st~0); 160586#L449 assume !(0 == ~t3_st~0); 160585#L463 assume !(0 == ~t4_st~0); 160602#L477 [2022-02-21 04:24:46,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:46,293 INFO L85 PathProgramCache]: Analyzing trace with hash 995820945, now seen corresponding path program 1 times [2022-02-21 04:24:46,293 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:46,293 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217175105] [2022-02-21 04:24:46,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:46,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:46,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:46,315 INFO L290 TraceCheckUtils]: 0: Hoare triple {176574#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {176574#true} is VALID [2022-02-21 04:24:46,315 INFO L290 TraceCheckUtils]: 1: Hoare triple {176574#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {176576#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:46,316 INFO L290 TraceCheckUtils]: 2: Hoare triple {176576#(= ~t1_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {176576#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:46,316 INFO L290 TraceCheckUtils]: 3: Hoare triple {176576#(= ~t1_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {176576#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:46,316 INFO L290 TraceCheckUtils]: 4: Hoare triple {176576#(= ~t1_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {176576#(= ~t1_i~0 1)} is VALID [2022-02-21 04:24:46,317 INFO L290 TraceCheckUtils]: 5: Hoare triple {176576#(= ~t1_i~0 1)} assume !(1 == ~t1_i~0);~t1_st~0 := 2; {176575#false} is VALID [2022-02-21 04:24:46,317 INFO L290 TraceCheckUtils]: 6: Hoare triple {176575#false} assume 1 == ~t2_i~0;~t2_st~0 := 0; {176575#false} is VALID [2022-02-21 04:24:46,317 INFO L290 TraceCheckUtils]: 7: Hoare triple {176575#false} assume 1 == ~t3_i~0;~t3_st~0 := 0; {176575#false} is VALID [2022-02-21 04:24:46,317 INFO L290 TraceCheckUtils]: 8: Hoare triple {176575#false} assume 1 == ~t4_i~0;~t4_st~0 := 0; {176575#false} is VALID [2022-02-21 04:24:46,317 INFO L290 TraceCheckUtils]: 9: Hoare triple {176575#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {176575#false} is VALID [2022-02-21 04:24:46,318 INFO L290 TraceCheckUtils]: 10: Hoare triple {176575#false} assume !(0 == ~M_E~0); {176575#false} is VALID [2022-02-21 04:24:46,318 INFO L290 TraceCheckUtils]: 11: Hoare triple {176575#false} assume !(0 == ~T1_E~0); {176575#false} is VALID [2022-02-21 04:24:46,318 INFO L290 TraceCheckUtils]: 12: Hoare triple {176575#false} assume !(0 == ~T2_E~0); {176575#false} is VALID [2022-02-21 04:24:46,318 INFO L290 TraceCheckUtils]: 13: Hoare triple {176575#false} assume !(0 == ~T3_E~0); {176575#false} is VALID [2022-02-21 04:24:46,318 INFO L290 TraceCheckUtils]: 14: Hoare triple {176575#false} assume !(0 == ~T4_E~0); {176575#false} is VALID [2022-02-21 04:24:46,318 INFO L290 TraceCheckUtils]: 15: Hoare triple {176575#false} assume !(0 == ~E_1~0); {176575#false} is VALID [2022-02-21 04:24:46,318 INFO L290 TraceCheckUtils]: 16: Hoare triple {176575#false} assume !(0 == ~E_2~0); {176575#false} is VALID [2022-02-21 04:24:46,318 INFO L290 TraceCheckUtils]: 17: Hoare triple {176575#false} assume !(0 == ~E_3~0); {176575#false} is VALID [2022-02-21 04:24:46,319 INFO L290 TraceCheckUtils]: 18: Hoare triple {176575#false} assume !(0 == ~E_4~0); {176575#false} is VALID [2022-02-21 04:24:46,319 INFO L290 TraceCheckUtils]: 19: Hoare triple {176575#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {176575#false} is VALID [2022-02-21 04:24:46,319 INFO L290 TraceCheckUtils]: 20: Hoare triple {176575#false} assume !(1 == ~m_pc~0); {176575#false} is VALID [2022-02-21 04:24:46,319 INFO L290 TraceCheckUtils]: 21: Hoare triple {176575#false} is_master_triggered_~__retres1~0#1 := 0; {176575#false} is VALID [2022-02-21 04:24:46,319 INFO L290 TraceCheckUtils]: 22: Hoare triple {176575#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {176575#false} is VALID [2022-02-21 04:24:46,319 INFO L290 TraceCheckUtils]: 23: Hoare triple {176575#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {176575#false} is VALID [2022-02-21 04:24:46,319 INFO L290 TraceCheckUtils]: 24: Hoare triple {176575#false} assume !(0 != activate_threads_~tmp~1#1); {176575#false} is VALID [2022-02-21 04:24:46,320 INFO L290 TraceCheckUtils]: 25: Hoare triple {176575#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {176575#false} is VALID [2022-02-21 04:24:46,320 INFO L290 TraceCheckUtils]: 26: Hoare triple {176575#false} assume !(1 == ~t1_pc~0); {176575#false} is VALID [2022-02-21 04:24:46,320 INFO L290 TraceCheckUtils]: 27: Hoare triple {176575#false} is_transmit1_triggered_~__retres1~1#1 := 0; {176575#false} is VALID [2022-02-21 04:24:46,320 INFO L290 TraceCheckUtils]: 28: Hoare triple {176575#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {176575#false} is VALID [2022-02-21 04:24:46,320 INFO L290 TraceCheckUtils]: 29: Hoare triple {176575#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {176575#false} is VALID [2022-02-21 04:24:46,320 INFO L290 TraceCheckUtils]: 30: Hoare triple {176575#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {176575#false} is VALID [2022-02-21 04:24:46,320 INFO L290 TraceCheckUtils]: 31: Hoare triple {176575#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {176575#false} is VALID [2022-02-21 04:24:46,321 INFO L290 TraceCheckUtils]: 32: Hoare triple {176575#false} assume !(1 == ~t2_pc~0); {176575#false} is VALID [2022-02-21 04:24:46,321 INFO L290 TraceCheckUtils]: 33: Hoare triple {176575#false} is_transmit2_triggered_~__retres1~2#1 := 0; {176575#false} is VALID [2022-02-21 04:24:46,321 INFO L290 TraceCheckUtils]: 34: Hoare triple {176575#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {176575#false} is VALID [2022-02-21 04:24:46,321 INFO L290 TraceCheckUtils]: 35: Hoare triple {176575#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {176575#false} is VALID [2022-02-21 04:24:46,321 INFO L290 TraceCheckUtils]: 36: Hoare triple {176575#false} assume !(0 != activate_threads_~tmp___1~0#1); {176575#false} is VALID [2022-02-21 04:24:46,321 INFO L290 TraceCheckUtils]: 37: Hoare triple {176575#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {176575#false} is VALID [2022-02-21 04:24:46,321 INFO L290 TraceCheckUtils]: 38: Hoare triple {176575#false} assume !(1 == ~t3_pc~0); {176575#false} is VALID [2022-02-21 04:24:46,322 INFO L290 TraceCheckUtils]: 39: Hoare triple {176575#false} is_transmit3_triggered_~__retres1~3#1 := 0; {176575#false} is VALID [2022-02-21 04:24:46,322 INFO L290 TraceCheckUtils]: 40: Hoare triple {176575#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {176575#false} is VALID [2022-02-21 04:24:46,322 INFO L290 TraceCheckUtils]: 41: Hoare triple {176575#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {176575#false} is VALID [2022-02-21 04:24:46,322 INFO L290 TraceCheckUtils]: 42: Hoare triple {176575#false} assume !(0 != activate_threads_~tmp___2~0#1); {176575#false} is VALID [2022-02-21 04:24:46,322 INFO L290 TraceCheckUtils]: 43: Hoare triple {176575#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {176575#false} is VALID [2022-02-21 04:24:46,322 INFO L290 TraceCheckUtils]: 44: Hoare triple {176575#false} assume !(1 == ~t4_pc~0); {176575#false} is VALID [2022-02-21 04:24:46,322 INFO L290 TraceCheckUtils]: 45: Hoare triple {176575#false} is_transmit4_triggered_~__retres1~4#1 := 0; {176575#false} is VALID [2022-02-21 04:24:46,323 INFO L290 TraceCheckUtils]: 46: Hoare triple {176575#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {176575#false} is VALID [2022-02-21 04:24:46,323 INFO L290 TraceCheckUtils]: 47: Hoare triple {176575#false} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {176575#false} is VALID [2022-02-21 04:24:46,323 INFO L290 TraceCheckUtils]: 48: Hoare triple {176575#false} assume !(0 != activate_threads_~tmp___3~0#1); {176575#false} is VALID [2022-02-21 04:24:46,323 INFO L290 TraceCheckUtils]: 49: Hoare triple {176575#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {176575#false} is VALID [2022-02-21 04:24:46,323 INFO L290 TraceCheckUtils]: 50: Hoare triple {176575#false} assume !(1 == ~M_E~0); {176575#false} is VALID [2022-02-21 04:24:46,323 INFO L290 TraceCheckUtils]: 51: Hoare triple {176575#false} assume !(1 == ~T1_E~0); {176575#false} is VALID [2022-02-21 04:24:46,323 INFO L290 TraceCheckUtils]: 52: Hoare triple {176575#false} assume !(1 == ~T2_E~0); {176575#false} is VALID [2022-02-21 04:24:46,324 INFO L290 TraceCheckUtils]: 53: Hoare triple {176575#false} assume !(1 == ~T3_E~0); {176575#false} is VALID [2022-02-21 04:24:46,324 INFO L290 TraceCheckUtils]: 54: Hoare triple {176575#false} assume !(1 == ~T4_E~0); {176575#false} is VALID [2022-02-21 04:24:46,324 INFO L290 TraceCheckUtils]: 55: Hoare triple {176575#false} assume !(1 == ~E_1~0); {176575#false} is VALID [2022-02-21 04:24:46,324 INFO L290 TraceCheckUtils]: 56: Hoare triple {176575#false} assume !(1 == ~E_2~0); {176575#false} is VALID [2022-02-21 04:24:46,324 INFO L290 TraceCheckUtils]: 57: Hoare triple {176575#false} assume !(1 == ~E_3~0); {176575#false} is VALID [2022-02-21 04:24:46,324 INFO L290 TraceCheckUtils]: 58: Hoare triple {176575#false} assume !(1 == ~E_4~0); {176575#false} is VALID [2022-02-21 04:24:46,324 INFO L290 TraceCheckUtils]: 59: Hoare triple {176575#false} assume { :end_inline_reset_delta_events } true; {176575#false} is VALID [2022-02-21 04:24:46,325 INFO L290 TraceCheckUtils]: 60: Hoare triple {176575#false} assume !false; {176575#false} is VALID [2022-02-21 04:24:46,325 INFO L290 TraceCheckUtils]: 61: Hoare triple {176575#false} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {176575#false} is VALID [2022-02-21 04:24:46,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:46,325 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:46,325 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217175105] [2022-02-21 04:24:46,325 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1217175105] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:46,326 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:46,326 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:46,326 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116184783] [2022-02-21 04:24:46,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:46,327 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:46,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:46,327 INFO L85 PathProgramCache]: Analyzing trace with hash 109617948, now seen corresponding path program 1 times [2022-02-21 04:24:46,328 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:46,328 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590164775] [2022-02-21 04:24:46,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:46,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:46,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:46,336 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:46,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:46,341 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:46,434 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:46,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:46,435 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:46,435 INFO L87 Difference]: Start difference. First operand 6176 states and 8137 transitions. cyclomatic complexity: 1964 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:47,486 INFO L93 Difference]: Finished difference Result 6118 states and 8062 transitions. [2022-02-21 04:24:47,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:47,486 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,522 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:47,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6118 states and 8062 transitions. [2022-02-21 04:24:48,356 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2022-02-21 04:24:49,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6118 states to 6118 states and 8062 transitions. [2022-02-21 04:24:49,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6118 [2022-02-21 04:24:49,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6118 [2022-02-21 04:24:49,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6118 states and 8062 transitions. [2022-02-21 04:24:49,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:49,251 INFO L681 BuchiCegarLoop]: Abstraction has 6118 states and 8062 transitions. [2022-02-21 04:24:49,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6118 states and 8062 transitions. [2022-02-21 04:24:49,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6118 to 6118. [2022-02-21 04:24:49,330 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:49,337 INFO L82 GeneralOperation]: Start isEquivalent. First operand 6118 states and 8062 transitions. Second operand has 6118 states, 6118 states have (on average 1.317750898986597) internal successors, (8062), 6117 states have internal predecessors, (8062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,343 INFO L74 IsIncluded]: Start isIncluded. First operand 6118 states and 8062 transitions. Second operand has 6118 states, 6118 states have (on average 1.317750898986597) internal successors, (8062), 6117 states have internal predecessors, (8062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,349 INFO L87 Difference]: Start difference. First operand 6118 states and 8062 transitions. Second operand has 6118 states, 6118 states have (on average 1.317750898986597) internal successors, (8062), 6117 states have internal predecessors, (8062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:50,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:50,160 INFO L93 Difference]: Finished difference Result 6118 states and 8062 transitions. [2022-02-21 04:24:50,160 INFO L276 IsEmpty]: Start isEmpty. Operand 6118 states and 8062 transitions. [2022-02-21 04:24:50,164 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:50,164 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:50,169 INFO L74 IsIncluded]: Start isIncluded. First operand has 6118 states, 6118 states have (on average 1.317750898986597) internal successors, (8062), 6117 states have internal predecessors, (8062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6118 states and 8062 transitions. [2022-02-21 04:24:50,173 INFO L87 Difference]: Start difference. First operand has 6118 states, 6118 states have (on average 1.317750898986597) internal successors, (8062), 6117 states have internal predecessors, (8062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6118 states and 8062 transitions. [2022-02-21 04:24:50,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:50,933 INFO L93 Difference]: Finished difference Result 6118 states and 8062 transitions. [2022-02-21 04:24:50,933 INFO L276 IsEmpty]: Start isEmpty. Operand 6118 states and 8062 transitions. [2022-02-21 04:24:50,937 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:50,938 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:50,938 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:50,938 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:50,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6118 states, 6118 states have (on average 1.317750898986597) internal successors, (8062), 6117 states have internal predecessors, (8062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6118 states to 6118 states and 8062 transitions. [2022-02-21 04:24:51,788 INFO L704 BuchiCegarLoop]: Abstraction has 6118 states and 8062 transitions. [2022-02-21 04:24:51,788 INFO L587 BuchiCegarLoop]: Abstraction has 6118 states and 8062 transitions. [2022-02-21 04:24:51,788 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2022-02-21 04:24:51,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6118 states and 8062 transitions. [2022-02-21 04:24:51,796 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2022-02-21 04:24:51,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:51,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:51,796 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:51,796 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:51,797 INFO L791 eck$LassoCheckResult]: Stem: 183151#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 183074#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 182697#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 182698#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 182816#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 182930#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 182780#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 182781#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 182793#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 182794#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 182835#L502 assume !(0 == ~M_E~0); 182836#L502-2 assume !(0 == ~T1_E~0); 182772#L507-1 assume !(0 == ~T2_E~0); 182773#L512-1 assume !(0 == ~T3_E~0); 182932#L517-1 assume !(0 == ~T4_E~0); 182750#L522-1 assume !(0 == ~E_1~0); 182751#L527-1 assume !(0 == ~E_2~0); 182951#L532-1 assume !(0 == ~E_3~0); 183062#L537-1 assume !(0 == ~E_4~0); 183089#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 183050#L238 assume !(1 == ~m_pc~0); 183051#L238-2 is_master_triggered_~__retres1~0#1 := 0; 182710#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 182711#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 183026#L615 assume !(0 != activate_threads_~tmp~1#1); 182733#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 182734#L257 assume !(1 == ~t1_pc~0); 182843#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 182844#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 182879#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 182704#L623 assume !(0 != activate_threads_~tmp___0~0#1); 182705#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 182699#L276 assume !(1 == ~t2_pc~0); 182700#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 182964#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 182795#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 182796#L631 assume !(0 != activate_threads_~tmp___1~0#1); 183103#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 183024#L295 assume !(1 == ~t3_pc~0); 182810#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 182811#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 183009#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 183064#L639 assume !(0 != activate_threads_~tmp___2~0#1); 183055#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183056#L314 assume !(1 == ~t4_pc~0); 182848#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 182847#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 183057#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 182999#L647 assume !(0 != activate_threads_~tmp___3~0#1); 182944#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 182945#L555 assume !(1 == ~M_E~0); 182861#L555-2 assume !(1 == ~T1_E~0); 182862#L560-1 assume !(1 == ~T2_E~0); 182752#L565-1 assume !(1 == ~T3_E~0); 182753#L570-1 assume !(1 == ~T4_E~0); 182822#L575-1 assume !(1 == ~E_1~0); 182823#L580-1 assume !(1 == ~E_2~0); 183000#L585-1 assume !(1 == ~E_3~0); 182821#L590-1 assume !(1 == ~E_4~0); 182812#L595-1 assume { :end_inline_reset_delta_events } true; 182813#L776-2 assume !false; 185374#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 185367#L477 [2022-02-21 04:24:51,797 INFO L793 eck$LassoCheckResult]: Loop: 185367#L477 assume !false; 185368#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 185359#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 185360#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 185353#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 185336#L416 assume 0 != eval_~tmp~0#1; 185335#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 185331#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 184865#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 184861#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 184862#L435 assume !(0 == ~t2_st~0); 185389#L449 assume !(0 == ~t3_st~0); 185388#L463 assume !(0 == ~t4_st~0); 185367#L477 [2022-02-21 04:24:51,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:51,797 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 2 times [2022-02-21 04:24:51,797 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:51,798 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721789506] [2022-02-21 04:24:51,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:51,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:51,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:51,804 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:51,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:51,815 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:51,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:51,816 INFO L85 PathProgramCache]: Analyzing trace with hash 109617948, now seen corresponding path program 2 times [2022-02-21 04:24:51,816 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:51,816 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833048026] [2022-02-21 04:24:51,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:51,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:51,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:51,820 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:24:51,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:24:51,822 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:24:51,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:51,823 INFO L85 PathProgramCache]: Analyzing trace with hash 2084563792, now seen corresponding path program 1 times [2022-02-21 04:24:51,823 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:51,823 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198349055] [2022-02-21 04:24:51,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:51,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:51,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:51,860 INFO L290 TraceCheckUtils]: 0: Hoare triple {201058#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {201058#true} is VALID [2022-02-21 04:24:51,860 INFO L290 TraceCheckUtils]: 1: Hoare triple {201058#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {201058#true} is VALID [2022-02-21 04:24:51,860 INFO L290 TraceCheckUtils]: 2: Hoare triple {201058#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {201058#true} is VALID [2022-02-21 04:24:51,860 INFO L290 TraceCheckUtils]: 3: Hoare triple {201058#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {201058#true} is VALID [2022-02-21 04:24:51,861 INFO L290 TraceCheckUtils]: 4: Hoare triple {201058#true} assume 1 == ~m_i~0;~m_st~0 := 0; {201058#true} is VALID [2022-02-21 04:24:51,861 INFO L290 TraceCheckUtils]: 5: Hoare triple {201058#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {201058#true} is VALID [2022-02-21 04:24:51,861 INFO L290 TraceCheckUtils]: 6: Hoare triple {201058#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,861 INFO L290 TraceCheckUtils]: 7: Hoare triple {201060#(= 0 ~t2_st~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,862 INFO L290 TraceCheckUtils]: 8: Hoare triple {201060#(= 0 ~t2_st~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,862 INFO L290 TraceCheckUtils]: 9: Hoare triple {201060#(= 0 ~t2_st~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,863 INFO L290 TraceCheckUtils]: 10: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 == ~M_E~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,863 INFO L290 TraceCheckUtils]: 11: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 == ~T1_E~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,863 INFO L290 TraceCheckUtils]: 12: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 == ~T2_E~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,864 INFO L290 TraceCheckUtils]: 13: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 == ~T3_E~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,864 INFO L290 TraceCheckUtils]: 14: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 == ~T4_E~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,864 INFO L290 TraceCheckUtils]: 15: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 == ~E_1~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,865 INFO L290 TraceCheckUtils]: 16: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 == ~E_2~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,865 INFO L290 TraceCheckUtils]: 17: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 == ~E_3~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,865 INFO L290 TraceCheckUtils]: 18: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 == ~E_4~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,866 INFO L290 TraceCheckUtils]: 19: Hoare triple {201060#(= 0 ~t2_st~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,866 INFO L290 TraceCheckUtils]: 20: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~m_pc~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,866 INFO L290 TraceCheckUtils]: 21: Hoare triple {201060#(= 0 ~t2_st~0)} is_master_triggered_~__retres1~0#1 := 0; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,867 INFO L290 TraceCheckUtils]: 22: Hoare triple {201060#(= 0 ~t2_st~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,867 INFO L290 TraceCheckUtils]: 23: Hoare triple {201060#(= 0 ~t2_st~0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,867 INFO L290 TraceCheckUtils]: 24: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp~1#1); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,868 INFO L290 TraceCheckUtils]: 25: Hoare triple {201060#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,868 INFO L290 TraceCheckUtils]: 26: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~t1_pc~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,868 INFO L290 TraceCheckUtils]: 27: Hoare triple {201060#(= 0 ~t2_st~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,869 INFO L290 TraceCheckUtils]: 28: Hoare triple {201060#(= 0 ~t2_st~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,869 INFO L290 TraceCheckUtils]: 29: Hoare triple {201060#(= 0 ~t2_st~0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,870 INFO L290 TraceCheckUtils]: 30: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___0~0#1); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,870 INFO L290 TraceCheckUtils]: 31: Hoare triple {201060#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,870 INFO L290 TraceCheckUtils]: 32: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~t2_pc~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,871 INFO L290 TraceCheckUtils]: 33: Hoare triple {201060#(= 0 ~t2_st~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,871 INFO L290 TraceCheckUtils]: 34: Hoare triple {201060#(= 0 ~t2_st~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,871 INFO L290 TraceCheckUtils]: 35: Hoare triple {201060#(= 0 ~t2_st~0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,872 INFO L290 TraceCheckUtils]: 36: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___1~0#1); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,872 INFO L290 TraceCheckUtils]: 37: Hoare triple {201060#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,872 INFO L290 TraceCheckUtils]: 38: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~t3_pc~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,873 INFO L290 TraceCheckUtils]: 39: Hoare triple {201060#(= 0 ~t2_st~0)} is_transmit3_triggered_~__retres1~3#1 := 0; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,873 INFO L290 TraceCheckUtils]: 40: Hoare triple {201060#(= 0 ~t2_st~0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,873 INFO L290 TraceCheckUtils]: 41: Hoare triple {201060#(= 0 ~t2_st~0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,874 INFO L290 TraceCheckUtils]: 42: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___2~0#1); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,874 INFO L290 TraceCheckUtils]: 43: Hoare triple {201060#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,874 INFO L290 TraceCheckUtils]: 44: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~t4_pc~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,875 INFO L290 TraceCheckUtils]: 45: Hoare triple {201060#(= 0 ~t2_st~0)} is_transmit4_triggered_~__retres1~4#1 := 0; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,875 INFO L290 TraceCheckUtils]: 46: Hoare triple {201060#(= 0 ~t2_st~0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,876 INFO L290 TraceCheckUtils]: 47: Hoare triple {201060#(= 0 ~t2_st~0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,876 INFO L290 TraceCheckUtils]: 48: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___3~0#1); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,876 INFO L290 TraceCheckUtils]: 49: Hoare triple {201060#(= 0 ~t2_st~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,877 INFO L290 TraceCheckUtils]: 50: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~M_E~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,877 INFO L290 TraceCheckUtils]: 51: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~T1_E~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,877 INFO L290 TraceCheckUtils]: 52: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~T2_E~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,878 INFO L290 TraceCheckUtils]: 53: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~T3_E~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,878 INFO L290 TraceCheckUtils]: 54: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~T4_E~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,878 INFO L290 TraceCheckUtils]: 55: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~E_1~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,879 INFO L290 TraceCheckUtils]: 56: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~E_2~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,879 INFO L290 TraceCheckUtils]: 57: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~E_3~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,879 INFO L290 TraceCheckUtils]: 58: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(1 == ~E_4~0); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,880 INFO L290 TraceCheckUtils]: 59: Hoare triple {201060#(= 0 ~t2_st~0)} assume { :end_inline_reset_delta_events } true; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,880 INFO L290 TraceCheckUtils]: 60: Hoare triple {201060#(= 0 ~t2_st~0)} assume !false; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,881 INFO L290 TraceCheckUtils]: 61: Hoare triple {201060#(= 0 ~t2_st~0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,881 INFO L290 TraceCheckUtils]: 62: Hoare triple {201060#(= 0 ~t2_st~0)} assume !false; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,881 INFO L290 TraceCheckUtils]: 63: Hoare triple {201060#(= 0 ~t2_st~0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,882 INFO L290 TraceCheckUtils]: 64: Hoare triple {201060#(= 0 ~t2_st~0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,882 INFO L290 TraceCheckUtils]: 65: Hoare triple {201060#(= 0 ~t2_st~0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,882 INFO L290 TraceCheckUtils]: 66: Hoare triple {201060#(= 0 ~t2_st~0)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,883 INFO L290 TraceCheckUtils]: 67: Hoare triple {201060#(= 0 ~t2_st~0)} assume 0 != eval_~tmp~0#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,883 INFO L290 TraceCheckUtils]: 68: Hoare triple {201060#(= 0 ~t2_st~0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,883 INFO L290 TraceCheckUtils]: 69: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 != eval_~tmp_ndt_1~0#1); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,884 INFO L290 TraceCheckUtils]: 70: Hoare triple {201060#(= 0 ~t2_st~0)} assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,884 INFO L290 TraceCheckUtils]: 71: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 != eval_~tmp_ndt_2~0#1); {201060#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:24:51,884 INFO L290 TraceCheckUtils]: 72: Hoare triple {201060#(= 0 ~t2_st~0)} assume !(0 == ~t2_st~0); {201059#false} is VALID [2022-02-21 04:24:51,885 INFO L290 TraceCheckUtils]: 73: Hoare triple {201059#false} assume !(0 == ~t3_st~0); {201059#false} is VALID [2022-02-21 04:24:51,885 INFO L290 TraceCheckUtils]: 74: Hoare triple {201059#false} assume !(0 == ~t4_st~0); {201059#false} is VALID [2022-02-21 04:24:51,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:51,885 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:51,885 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1198349055] [2022-02-21 04:24:51,886 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1198349055] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:51,886 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:51,886 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:51,886 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703701143] [2022-02-21 04:24:51,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:51,974 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:51,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:51,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:51,975 INFO L87 Difference]: Start difference. First operand 6118 states and 8062 transitions. cyclomatic complexity: 1947 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:54,262 INFO L93 Difference]: Finished difference Result 9420 states and 12360 transitions. [2022-02-21 04:24:54,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:54,262 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,311 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 75 edges. 75 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:54,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9420 states and 12360 transitions. [2022-02-21 04:24:56,349 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9340 [2022-02-21 04:24:58,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9420 states to 9420 states and 12360 transitions. [2022-02-21 04:24:58,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9420 [2022-02-21 04:24:58,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9420 [2022-02-21 04:24:58,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9420 states and 12360 transitions. [2022-02-21 04:24:58,190 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:58,190 INFO L681 BuchiCegarLoop]: Abstraction has 9420 states and 12360 transitions. [2022-02-21 04:24:58,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9420 states and 12360 transitions. [2022-02-21 04:24:58,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9420 to 9420. [2022-02-21 04:24:58,264 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:58,274 INFO L82 GeneralOperation]: Start isEquivalent. First operand 9420 states and 12360 transitions. Second operand has 9420 states, 9420 states have (on average 1.3121019108280254) internal successors, (12360), 9419 states have internal predecessors, (12360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:58,284 INFO L74 IsIncluded]: Start isIncluded. First operand 9420 states and 12360 transitions. Second operand has 9420 states, 9420 states have (on average 1.3121019108280254) internal successors, (12360), 9419 states have internal predecessors, (12360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:58,293 INFO L87 Difference]: Start difference. First operand 9420 states and 12360 transitions. Second operand has 9420 states, 9420 states have (on average 1.3121019108280254) internal successors, (12360), 9419 states have internal predecessors, (12360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:00,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:00,121 INFO L93 Difference]: Finished difference Result 9420 states and 12360 transitions. [2022-02-21 04:25:00,121 INFO L276 IsEmpty]: Start isEmpty. Operand 9420 states and 12360 transitions. [2022-02-21 04:25:00,127 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:00,127 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:00,138 INFO L74 IsIncluded]: Start isIncluded. First operand has 9420 states, 9420 states have (on average 1.3121019108280254) internal successors, (12360), 9419 states have internal predecessors, (12360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9420 states and 12360 transitions. [2022-02-21 04:25:00,147 INFO L87 Difference]: Start difference. First operand has 9420 states, 9420 states have (on average 1.3121019108280254) internal successors, (12360), 9419 states have internal predecessors, (12360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9420 states and 12360 transitions. [2022-02-21 04:25:02,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:02,070 INFO L93 Difference]: Finished difference Result 9420 states and 12360 transitions. [2022-02-21 04:25:02,070 INFO L276 IsEmpty]: Start isEmpty. Operand 9420 states and 12360 transitions. [2022-02-21 04:25:02,075 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:02,076 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:02,076 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:02,076 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:02,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9420 states, 9420 states have (on average 1.3121019108280254) internal successors, (12360), 9419 states have internal predecessors, (12360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:03,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9420 states to 9420 states and 12360 transitions. [2022-02-21 04:25:03,860 INFO L704 BuchiCegarLoop]: Abstraction has 9420 states and 12360 transitions. [2022-02-21 04:25:03,860 INFO L587 BuchiCegarLoop]: Abstraction has 9420 states and 12360 transitions. [2022-02-21 04:25:03,860 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2022-02-21 04:25:03,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9420 states and 12360 transitions. [2022-02-21 04:25:03,878 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9340 [2022-02-21 04:25:03,878 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:03,878 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:03,879 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:03,879 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:03,879 INFO L791 eck$LassoCheckResult]: Stem: 210933#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 210856#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 210481#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 210482#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 210597#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 210715#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 210563#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 210564#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 210576#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 210577#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 210618#L502 assume !(0 == ~M_E~0); 210619#L502-2 assume !(0 == ~T1_E~0); 210552#L507-1 assume !(0 == ~T2_E~0); 210553#L512-1 assume !(0 == ~T3_E~0); 210718#L517-1 assume !(0 == ~T4_E~0); 210526#L522-1 assume !(0 == ~E_1~0); 210527#L527-1 assume !(0 == ~E_2~0); 210740#L532-1 assume !(0 == ~E_3~0); 210847#L537-1 assume !(0 == ~E_4~0); 210871#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210838#L238 assume !(1 == ~m_pc~0); 210839#L238-2 is_master_triggered_~__retres1~0#1 := 0; 210492#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 210493#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 210814#L615 assume !(0 != activate_threads_~tmp~1#1); 210513#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 210514#L257 assume !(1 == ~t1_pc~0); 210626#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 210627#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 210662#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 210486#L623 assume !(0 != activate_threads_~tmp___0~0#1); 210487#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210483#L276 assume !(1 == ~t2_pc~0); 210484#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 210749#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 210578#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 210579#L631 assume !(0 != activate_threads_~tmp___1~0#1); 210888#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 210811#L295 assume !(1 == ~t3_pc~0); 210593#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 210594#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 210794#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 210848#L639 assume !(0 != activate_threads_~tmp___2~0#1); 210840#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 210841#L314 assume !(1 == ~t4_pc~0); 210631#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 210630#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 210843#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 210786#L647 assume !(0 != activate_threads_~tmp___3~0#1); 210733#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 210734#L555 assume !(1 == ~M_E~0); 210644#L555-2 assume !(1 == ~T1_E~0); 210645#L560-1 assume !(1 == ~T2_E~0); 210528#L565-1 assume !(1 == ~T3_E~0); 210529#L570-1 assume !(1 == ~T4_E~0); 210604#L575-1 assume !(1 == ~E_1~0); 210605#L580-1 assume !(1 == ~E_2~0); 210787#L585-1 assume !(1 == ~E_3~0); 210606#L590-1 assume !(1 == ~E_4~0); 210595#L595-1 assume { :end_inline_reset_delta_events } true; 210596#L776-2 assume !false; 216716#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 216710#L477 [2022-02-21 04:25:03,880 INFO L793 eck$LassoCheckResult]: Loop: 216710#L477 assume !false; 216709#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 216706#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 216705#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 216703#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 216701#L416 assume 0 != eval_~tmp~0#1; 216698#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 216695#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 216691#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 214209#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 216681#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 216755#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 216721#L449 assume !(0 == ~t3_st~0); 216715#L463 assume !(0 == ~t4_st~0); 216710#L477 [2022-02-21 04:25:03,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:03,880 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 3 times [2022-02-21 04:25:03,881 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:03,881 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854649784] [2022-02-21 04:25:03,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:03,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:03,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:25:03,888 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:25:03,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:25:03,899 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:25:03,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:03,899 INFO L85 PathProgramCache]: Analyzing trace with hash -901553796, now seen corresponding path program 1 times [2022-02-21 04:25:03,899 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:03,899 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097362139] [2022-02-21 04:25:03,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:03,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:03,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:25:03,903 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:25:03,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:25:03,905 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:25:03,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:03,906 INFO L85 PathProgramCache]: Analyzing trace with hash 192225224, now seen corresponding path program 1 times [2022-02-21 04:25:03,906 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:03,906 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115753194] [2022-02-21 04:25:03,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:03,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:03,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:03,928 INFO L290 TraceCheckUtils]: 0: Hoare triple {238748#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; {238748#true} is VALID [2022-02-21 04:25:03,928 INFO L290 TraceCheckUtils]: 1: Hoare triple {238748#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {238748#true} is VALID [2022-02-21 04:25:03,928 INFO L290 TraceCheckUtils]: 2: Hoare triple {238748#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {238748#true} is VALID [2022-02-21 04:25:03,928 INFO L290 TraceCheckUtils]: 3: Hoare triple {238748#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {238748#true} is VALID [2022-02-21 04:25:03,929 INFO L290 TraceCheckUtils]: 4: Hoare triple {238748#true} assume 1 == ~m_i~0;~m_st~0 := 0; {238748#true} is VALID [2022-02-21 04:25:03,929 INFO L290 TraceCheckUtils]: 5: Hoare triple {238748#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {238748#true} is VALID [2022-02-21 04:25:03,929 INFO L290 TraceCheckUtils]: 6: Hoare triple {238748#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {238748#true} is VALID [2022-02-21 04:25:03,929 INFO L290 TraceCheckUtils]: 7: Hoare triple {238748#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,930 INFO L290 TraceCheckUtils]: 8: Hoare triple {238750#(= 0 ~t3_st~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,930 INFO L290 TraceCheckUtils]: 9: Hoare triple {238750#(= 0 ~t3_st~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,931 INFO L290 TraceCheckUtils]: 10: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 == ~M_E~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,931 INFO L290 TraceCheckUtils]: 11: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 == ~T1_E~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,931 INFO L290 TraceCheckUtils]: 12: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 == ~T2_E~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,932 INFO L290 TraceCheckUtils]: 13: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 == ~T3_E~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,932 INFO L290 TraceCheckUtils]: 14: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 == ~T4_E~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,932 INFO L290 TraceCheckUtils]: 15: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 == ~E_1~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,933 INFO L290 TraceCheckUtils]: 16: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 == ~E_2~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,933 INFO L290 TraceCheckUtils]: 17: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 == ~E_3~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,933 INFO L290 TraceCheckUtils]: 18: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 == ~E_4~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,934 INFO L290 TraceCheckUtils]: 19: Hoare triple {238750#(= 0 ~t3_st~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,934 INFO L290 TraceCheckUtils]: 20: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~m_pc~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,934 INFO L290 TraceCheckUtils]: 21: Hoare triple {238750#(= 0 ~t3_st~0)} is_master_triggered_~__retres1~0#1 := 0; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,935 INFO L290 TraceCheckUtils]: 22: Hoare triple {238750#(= 0 ~t3_st~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,935 INFO L290 TraceCheckUtils]: 23: Hoare triple {238750#(= 0 ~t3_st~0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,935 INFO L290 TraceCheckUtils]: 24: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 != activate_threads_~tmp~1#1); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,935 INFO L290 TraceCheckUtils]: 25: Hoare triple {238750#(= 0 ~t3_st~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,936 INFO L290 TraceCheckUtils]: 26: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~t1_pc~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,936 INFO L290 TraceCheckUtils]: 27: Hoare triple {238750#(= 0 ~t3_st~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,936 INFO L290 TraceCheckUtils]: 28: Hoare triple {238750#(= 0 ~t3_st~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,937 INFO L290 TraceCheckUtils]: 29: Hoare triple {238750#(= 0 ~t3_st~0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,937 INFO L290 TraceCheckUtils]: 30: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 != activate_threads_~tmp___0~0#1); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,937 INFO L290 TraceCheckUtils]: 31: Hoare triple {238750#(= 0 ~t3_st~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,938 INFO L290 TraceCheckUtils]: 32: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~t2_pc~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,938 INFO L290 TraceCheckUtils]: 33: Hoare triple {238750#(= 0 ~t3_st~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,938 INFO L290 TraceCheckUtils]: 34: Hoare triple {238750#(= 0 ~t3_st~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,939 INFO L290 TraceCheckUtils]: 35: Hoare triple {238750#(= 0 ~t3_st~0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,939 INFO L290 TraceCheckUtils]: 36: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 != activate_threads_~tmp___1~0#1); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,939 INFO L290 TraceCheckUtils]: 37: Hoare triple {238750#(= 0 ~t3_st~0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,940 INFO L290 TraceCheckUtils]: 38: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~t3_pc~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,940 INFO L290 TraceCheckUtils]: 39: Hoare triple {238750#(= 0 ~t3_st~0)} is_transmit3_triggered_~__retres1~3#1 := 0; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,941 INFO L290 TraceCheckUtils]: 40: Hoare triple {238750#(= 0 ~t3_st~0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,941 INFO L290 TraceCheckUtils]: 41: Hoare triple {238750#(= 0 ~t3_st~0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,941 INFO L290 TraceCheckUtils]: 42: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 != activate_threads_~tmp___2~0#1); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,942 INFO L290 TraceCheckUtils]: 43: Hoare triple {238750#(= 0 ~t3_st~0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,942 INFO L290 TraceCheckUtils]: 44: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~t4_pc~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,942 INFO L290 TraceCheckUtils]: 45: Hoare triple {238750#(= 0 ~t3_st~0)} is_transmit4_triggered_~__retres1~4#1 := 0; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,943 INFO L290 TraceCheckUtils]: 46: Hoare triple {238750#(= 0 ~t3_st~0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,943 INFO L290 TraceCheckUtils]: 47: Hoare triple {238750#(= 0 ~t3_st~0)} activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,943 INFO L290 TraceCheckUtils]: 48: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 != activate_threads_~tmp___3~0#1); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,944 INFO L290 TraceCheckUtils]: 49: Hoare triple {238750#(= 0 ~t3_st~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,945 INFO L290 TraceCheckUtils]: 50: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~M_E~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,946 INFO L290 TraceCheckUtils]: 51: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~T1_E~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,946 INFO L290 TraceCheckUtils]: 52: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~T2_E~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,947 INFO L290 TraceCheckUtils]: 53: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~T3_E~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,947 INFO L290 TraceCheckUtils]: 54: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~T4_E~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,947 INFO L290 TraceCheckUtils]: 55: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~E_1~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,948 INFO L290 TraceCheckUtils]: 56: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~E_2~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,948 INFO L290 TraceCheckUtils]: 57: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~E_3~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,948 INFO L290 TraceCheckUtils]: 58: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(1 == ~E_4~0); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,949 INFO L290 TraceCheckUtils]: 59: Hoare triple {238750#(= 0 ~t3_st~0)} assume { :end_inline_reset_delta_events } true; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,953 INFO L290 TraceCheckUtils]: 60: Hoare triple {238750#(= 0 ~t3_st~0)} assume !false; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,954 INFO L290 TraceCheckUtils]: 61: Hoare triple {238750#(= 0 ~t3_st~0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,954 INFO L290 TraceCheckUtils]: 62: Hoare triple {238750#(= 0 ~t3_st~0)} assume !false; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,954 INFO L290 TraceCheckUtils]: 63: Hoare triple {238750#(= 0 ~t3_st~0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,955 INFO L290 TraceCheckUtils]: 64: Hoare triple {238750#(= 0 ~t3_st~0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,955 INFO L290 TraceCheckUtils]: 65: Hoare triple {238750#(= 0 ~t3_st~0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,956 INFO L290 TraceCheckUtils]: 66: Hoare triple {238750#(= 0 ~t3_st~0)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,956 INFO L290 TraceCheckUtils]: 67: Hoare triple {238750#(= 0 ~t3_st~0)} assume 0 != eval_~tmp~0#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,956 INFO L290 TraceCheckUtils]: 68: Hoare triple {238750#(= 0 ~t3_st~0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,957 INFO L290 TraceCheckUtils]: 69: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 != eval_~tmp_ndt_1~0#1); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,957 INFO L290 TraceCheckUtils]: 70: Hoare triple {238750#(= 0 ~t3_st~0)} assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,957 INFO L290 TraceCheckUtils]: 71: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 != eval_~tmp_ndt_2~0#1); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,958 INFO L290 TraceCheckUtils]: 72: Hoare triple {238750#(= 0 ~t3_st~0)} assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,958 INFO L290 TraceCheckUtils]: 73: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 != eval_~tmp_ndt_3~0#1); {238750#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:25:03,958 INFO L290 TraceCheckUtils]: 74: Hoare triple {238750#(= 0 ~t3_st~0)} assume !(0 == ~t3_st~0); {238749#false} is VALID [2022-02-21 04:25:03,958 INFO L290 TraceCheckUtils]: 75: Hoare triple {238749#false} assume !(0 == ~t4_st~0); {238749#false} is VALID [2022-02-21 04:25:03,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:03,959 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:03,959 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115753194] [2022-02-21 04:25:03,959 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115753194] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:03,959 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:03,959 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:03,959 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114305068] [2022-02-21 04:25:03,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:04,069 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:04,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:25:04,070 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:25:04,070 INFO L87 Difference]: Start difference. First operand 9420 states and 12360 transitions. cyclomatic complexity: 2943 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)